1 #include <system_def.h>
11 #include <hal_machperiph.h>
17 #include <ul_logreg.h>
19 #include "appl_defs.h"
20 #include "appl_fpga.h"
22 int cmd_do_test_memusage(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
29 snprintf(str, sizeof(str), "memusage maxaddr 0x%08lx\n", (unsigned long)maxaddr);
30 cmd_io_write(cmd_io, str, strlen(str));
35 int cmd_do_test_adc(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
37 printf("ADC: %ld %ld %ld %ld %ld\n", (LPC_ADC->DR[0] & 0xFFF0) >> 4,
38 (LPC_ADC->DR[1] & 0xFFF0) >> 4,
39 (LPC_ADC->DR[2] & 0xFFF0) >> 4,
40 (LPC_ADC->DR[3] & 0xFFF0) >> 4,
41 (LPC_ADC->DR[7] & 0xFFF0) >> 4);
45 #ifdef APPL_WITH_DISTORE_EEPROM_USER
46 int cmd_do_test_distore(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
48 appl_distore_user_set_check4change();
52 int cmd_do_test_diload(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
54 appl_distore_user_restore();
57 #endif /*APPL_WITH_DISTORE_EEPROM_USER*/
59 int cmd_do_test_loglevel_cb(ul_log_domain_t *domain, void *context)
62 cmd_io_t *cmd_io = (cmd_io_t *)context;
65 snprintf(s, sizeof(s) - 1, "%s (%d)\n\r", domain->name, domain->level);
66 cmd_io_puts(cmd_io, s);
70 int cmd_do_test_loglevel(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
76 if (!line || (si_skspace(&line), !*line))
78 ul_logreg_for_each_domain(cmd_do_test_loglevel_cb, cmd_io);
82 res = ul_log_domain_arg2levels(line);
85 return res >= 0 ? 0 : CMDERR_BADPAR;
88 int cmd_do_spimst_blocking(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
93 int spi_chan = (int)(intptr_t)des->info[0];
94 uint8_t *tx_buff = NULL;
95 uint8_t *rx_buff = NULL;
100 if ((opchar = cmd_opchar_check(cmd_io, des, param)) < 0)
104 return -CMDERR_OPCHAR;
107 spi_chan = *param[1] - '0';
109 spi_drv = spi_find_drv(NULL, spi_chan);
112 return -CMDERR_BADSUF;
118 if (isdigit((int)*p))
120 if (si_long(&p, &addr, 16) < 0)
121 return -CMDERR_BADPAR;
124 if (si_fndsep(&p, "({") < 0)
125 return -CMDERR_BADSEP;
127 if ((res = si_add_to_arr(&p, (void **)&tx_buff, &len, 16, 1, "})")) < 0)
128 return -CMDERR_BADPAR;
130 rx_buff = malloc(len);
135 res = spi_transfer(spi_drv, addr, len, tx_buff, rx_buff);
139 printf("SPI! %02lX ERROR\n", addr);
144 printf("SPI! %02lX ", addr);
147 for (i = 0; i < len; i++)
148 printf("%s%02X", i ? "," : "", tx_buff[i]);
152 for (i = 0; i < len; i++)
153 printf("%s%02X", i ? "," : "", rx_buff[i]);
170 int sdram_access_test(void)
173 unsigned int pattern;
174 size_t ramsz = SDRAM_SIZE;
182 pattern = 0x12abcdef;
184 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
187 pattern = pattern + 0x87654321;
191 printf("SDRAM write %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
196 pattern = 0x12abcdef;
198 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
202 printf("SDRAM error modify at %p (%08x)\n", ptr, *ptr ^ pattern);
207 pattern = pattern + 0x87654321;
211 printf("SDRAM modify %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
216 pattern = 0x12abcdef;
218 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
220 if (*(ptr++) != ~pattern)
222 printf("SDRAM error read at %p (%08x)\n", ptr, *ptr ^ pattern);
226 pattern = pattern + 0x87654321;
230 printf("SDRAM read %d ms\n", (int)(lt_msdiff_t)(actual_msec - tic));
237 for (cnt = ramsz / sizeof(*ptr), ptr = (typeof(ptr))SDRAM_BASE; cnt--;)
243 printf("SDRAM sum %d ms res 0x%08x\n", (int)(lt_msdiff_t)(actual_msec - tic), pattern);
245 for (blksz = 1; blksz < 256 ; blksz *= 2)
252 for (cnt = ramsz / sizeof(*ptr); cnt; cnt -= blksz)
254 ptr = (typeof(ptr))SDRAM_BASE;
256 //ptr = (typeof(ptr))cmd_do_test_memusage;
257 //ptr = (typeof(ptr))&ptr;
258 for (i = blksz; i--;)
263 printf("SDRAM sum %d blksz %d ms res 0x%08x\n", (int)(lt_msdiff_t)(actual_msec - tic), (int)blksz, pattern);
269 int cmd_do_testsdram(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
274 #endif /*SDRAM_BASE*/
276 #define LXPWR_RX_TIM LPC_TIM2
277 #define LXPWR_RX_IRQn TIMER2_IRQn
279 volatile void *lxpwr_rx_data_hist_buff;
280 volatile void *lxpwr_rx_data_hist_buff_end;
282 uint32_t lxpwr_rx_last_irq;
283 uint32_t lxpwr_rx_cycle_time;
284 uint32_t lxpwr_rx_irq_latency;
285 uint32_t lxpwr_rx_irq_latency_max;
287 IRQ_HANDLER_FNC(lxpwr_rx_done_isr)
291 ir = LXPWR_RX_TIM->IR & LPC_TIM_IR_ALL_m;
292 LXPWR_RX_TIM->IR = ir;
293 if (ir & LPC_TIM_IR_CR1INT_m) {
295 cr0 = LXPWR_RX_TIM->CR0;
296 cr1 = LXPWR_RX_TIM->CR1;
298 lxpwr_rx_cycle_time = cr1 - lxpwr_rx_last_irq;
299 lxpwr_rx_last_irq = cr1;
301 hal_gpio_set_value(T2MAT0_PIN, 1);
302 hal_gpio_set_value(T2MAT1_PIN, 0);
303 hal_gpio_set_value(T2MAT0_PIN, 0);
305 if (lxpwr_rx_data_hist_buff >= lxpwr_rx_data_hist_buff_end)
306 lxpwr_rx_data_hist_buff = NULL;
308 if (lxpwr_rx_data_hist_buff != NULL) {
310 volatile uint32_t *pwm_reg = fpga_lx_master_transmitter_base + 8;
311 volatile uint32_t *rec_reg = fpga_lx_master_receiver_base + 8;
312 uint16_t *pbuf = (uint16_t *)lxpwr_rx_data_hist_buff;
313 for (i = 0; i < 8; i++) {
314 *(pbuf++) = *(rec_reg++);
316 for (i = 0; i < 8; i++) {
317 *(pbuf++) = *(pwm_reg++);
319 lxpwr_rx_data_hist_buff = pbuf;
322 lxpwr_rx_irq_latency = LXPWR_RX_TIM->TC - cr1;
323 if (lxpwr_rx_irq_latency > lxpwr_rx_irq_latency_max)
324 lxpwr_rx_irq_latency_max = lxpwr_rx_irq_latency;
330 int lxpwr_rx_done_isr_init(void)
333 disable_irq(LXPWR_RX_IRQn);
335 hal_pin_conf_set(T2MAT0_PIN, PORT_CONF_GPIO_OUT_LO);
336 hal_pin_conf_set(T2MAT1_PIN, PORT_CONF_GPIO_OUT_LO);
337 hal_pin_conf(T2CAP0_PIN);
338 hal_pin_conf(T2CAP1_PIN);
340 hal_gpio_direction_output(T2MAT0_PIN, 1);
341 hal_gpio_direction_output(T2MAT1_PIN, 0);
342 hal_gpio_set_value(T2MAT0_PIN, 0);
344 /* Enable CLKOUT pin function, source CCLK, divide by 1 */
345 LPC_SC->CLKOUTCFG = 0x0100;
347 request_irq(LXPWR_RX_IRQn, lxpwr_rx_done_isr, 0, NULL,NULL);
349 LXPWR_RX_TIM->TCR = 0;
350 LXPWR_RX_TIM->CTCR = 0;
351 LXPWR_RX_TIM->PR = 0; /* Divide by 1 */
353 LXPWR_RX_TIM->CCR = LPC_TIM_CCR_CAP0RE_m | LPC_TIM_CCR_CAP1FE_m |
356 LXPWR_RX_TIM->EMR = __val2mfld(LPC_TIM_EMR_EMC0_m, LPC_TIM_EMR_NOP) |
357 __val2mfld(LPC_TIM_EMR_EMC1_m, LPC_TIM_EMR_NOP);
359 LXPWR_RX_TIM->MCR = 0; /* No IRQ on MRx */
360 LXPWR_RX_TIM->TCR = LPC_TIM_TCR_CEN_m; /* Enable timer counting */
361 enable_irq(LXPWR_RX_IRQn); /* Enable interrupt */
367 int cmd_do_testlxpwrrx(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
369 lxpwr_rx_data_hist_buff = NULL;
370 lxpwr_rx_done_isr_init();
371 lxpwr_rx_data_hist_buff_end = (void *)(FPGA_CONFIGURATION_FILE_ADDRESS +
373 lxpwr_rx_data_hist_buff = (void *)FPGA_CONFIGURATION_FILE_ADDRESS;
377 int cmd_do_testlxpwrstat(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
379 printf("lxpwrrx period %ld latency %ld max %ld\n",
380 (long)lxpwr_rx_cycle_time, (long)lxpwr_rx_irq_latency,
381 (long)lxpwr_rx_irq_latency_max);
385 cmd_des_t const cmd_des_test_memusage = {0, 0,
386 "memusage", "report memory usage", cmd_do_test_memusage,
393 cmd_des_t const cmd_des_test_adc = {0, 0,
394 "testadc", "adc test", cmd_do_test_adc,
401 #ifdef APPL_WITH_DISTORE_EEPROM_USER
402 cmd_des_t const cmd_des_test_distore = {0, 0,
403 "testdistore", "test DINFO store", cmd_do_test_distore,
410 cmd_des_t const cmd_des_test_diload = {0, 0,
411 "testdiload", "test DINFO load", cmd_do_test_diload,
417 #endif /*APPL_WITH_DISTORE_EEPROM_USER*/
419 cmd_des_t const cmd_des_test_loglevel = {0, 0,
420 "loglevel", "select logging level",
421 cmd_do_test_loglevel, {}
424 cmd_des_t const cmd_des_spimst = {0, CDESM_OPCHR | CDESM_WR,
425 "SPIMST", "SPI master communication request",
426 cmd_do_spimst_blocking, {(void *)0}
429 cmd_des_t const cmd_des_spimstx = {0, CDESM_OPCHR | CDESM_WR,
430 "SPIMST#", "SPI# master communication request",
431 cmd_do_spimst_blocking, {(void *) - 1}
435 cmd_des_t const cmd_des_testsdram = {0, 0,
436 "testsdram", "test SDRAM",
437 cmd_do_testsdram, {(void *)0}
439 #endif /*SDRAM_BASE*/
442 cmd_des_t const cmd_des_testlxpwrrx = {0, 0,
443 "testlxpwrrx", "capture data stream from lxpwr",
444 cmd_do_testlxpwrrx, {(void *)0}
447 cmd_des_t const cmd_des_testlxpwrstat = {0, 0,
448 "testlxpwrstat", "lxpwr interrupt statistic",
449 cmd_do_testlxpwrstat, {(void *)0}
452 cmd_des_t const *const cmd_appl_tests[] =
454 &cmd_des_test_memusage,
456 #ifdef APPL_WITH_DISTORE_EEPROM_USER
457 &cmd_des_test_distore,
458 &cmd_des_test_diload,
459 #endif /*APPL_WITH_DISTORE_EEPROM_USER*/
460 &cmd_des_test_loglevel,
465 #endif /*SDRAM_BASE*/
466 &cmd_des_testlxpwrrx,
467 &cmd_des_testlxpwrstat,