2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_arith.all;
4 use ieee.std_logic_unsigned.all;
5 use ieee.numeric_std.all;
8 use unisim.vcomponents.all;
11 use work.lx_rocon_pkg.all;
13 -- lx_rocon_top - wires the modules with the outside world
15 -- ======================================================
16 -- MASTER CPU EXTERNAL MEMORY BUS
17 -- ======================================================
19 -- Master cpu memory bus has the following wires:
21 -- - address[15..0] The address, used to mark chip enable
22 -- - data_in[31..0] The data coming to bus
23 -- - data_out[31..0] The data coming from bus, multiplexed
24 -- - bls[3..0] Write enable for respective bytes
26 entity lx_rocon_top is
30 --clk_cpu : in std_logic;
31 clk_50m : in std_logic;
33 cs0_xc : in std_logic;
36 bls : in std_logic_vector(3 downto 0);
37 address : in std_logic_vector(15 downto 0);
38 data : inout std_logic_vector(31 downto 0);
40 irc0_a : in std_logic;
41 irc0_b : in std_logic;
42 irc0_index : in std_logic;
43 irc0_mark : in std_logic;
45 irc1_a : in std_logic;
46 irc1_b : in std_logic;
47 irc1_index : in std_logic;
48 irc1_mark : in std_logic;
50 irc2_a : in std_logic;
51 irc2_b : in std_logic;
52 irc2_index : in std_logic;
53 irc2_mark : in std_logic;
55 irc3_a : in std_logic;
56 irc3_b : in std_logic;
57 irc3_index : in std_logic;
58 irc3_mark : in std_logic;
60 irc4_a : in std_logic;
61 irc4_b : in std_logic;
62 irc4_index : in std_logic;
63 irc4_mark : in std_logic;
65 irc5_a : in std_logic;
66 irc5_b : in std_logic;
67 irc5_index : in std_logic;
68 irc5_mark : in std_logic;
70 irc6_a : in std_logic;
71 irc6_b : in std_logic;
72 irc6_index : in std_logic;
73 irc6_mark : in std_logic;
75 irc7_a : in std_logic;
76 irc7_b : in std_logic;
77 irc7_index : in std_logic;
78 irc7_mark : in std_logic;
82 s1_clk_in : in std_logic;
83 s1_miso : in std_logic;
84 s1_sync_in : in std_logic;
86 s1_clk_out : out std_logic;
87 s1_mosi : out std_logic;
88 s1_sync_out : out std_logic;
89 -- signal connected to external JK FF
90 event_jk_j : out std_logic
94 architecture Behavioral of lx_rocon_top is
97 signal reset_s : std_logic;
98 signal init_s : std_logic;
99 -- Peripherals on the memory buses
100 -- Master to Tumbl DMEM / IMEM (Master)
101 signal tumbl_out_s : std_logic_vector(31 downto 0);
102 signal tumbl_ce_s : std_logic;
103 -- Measurement (Master)
104 signal meas_out_s : std_logic_vector(31 downto 0);
105 signal meas_ce_s : std_logic;
106 -- Master to Tumbl XMEM
107 signal master_tumbl_xmem_out_s : std_logic_vector(31 downto 0);
108 signal master_tumbl_xmem_ce_s : std_logic;
109 signal master_tumbl_xmem_lock_s : std_logic;
111 signal irc_proc_out_s : std_logic_vector(31 downto 0);
112 signal irc_proc_ce_s : std_logic;
113 signal irc_proc_next_ce_s : std_logic;
115 signal lxmaster_out_s : std_logic_vector(15 downto 0);
116 signal lxmaster_ce_s : std_logic;
117 signal lxmaster_next_ce_s : std_logic;
118 -- LX function approximation
119 signal lxfncapprox_out_s : std_logic_vector(31 downto 0);
120 signal lxfncapprox_ce_s : std_logic;
121 signal lxfncapprox_next_ce_s : std_logic;
122 -- Signals for external bus transmission
123 signal data_i_s : std_logic_vector(31 downto 0);
124 signal data_o_s : std_logic_vector(31 downto 0);
125 -- Signals for internal transaction
126 signal last_address_s : std_logic_vector(15 downto 0);
127 signal next_last_address_s : std_logic_vector(15 downto 0);
128 signal next_address_hold_s : std_logic;
129 signal address_hold_s : std_logic;
130 signal last_rd_s : std_logic;
131 signal next_last_rd_s : std_logic;
132 signal last_bls_s : std_logic_vector(3 downto 0); -- prev bls_f_s (active 1)
133 signal next_last_bls_s : std_logic_vector(3 downto 0);
135 -- Reading logic for Master CPU:
136 -- Broadcast rd only till ta (transaction acknowledge)
137 -- is received, then latch the data till the state of
138 -- rd or address changes
140 -- Data latching is synchronous - it's purpose is to
141 -- provide stable data for CPU on the bus
142 signal cs0_xc_f_s : std_logic;
143 signal rd_f_s : std_logic; -- Filtered RD
144 signal i_rd_s : std_logic; -- Internal bus RD (active 1)
145 -- signal next_i_rd_s : std_logic;
146 signal last_i_rd_s : std_logic; -- Delayed RD bus, used for latching
147 signal next_last_i_rd_s : std_logic;
148 signal i_rd_cycle2_s : std_logic; -- Some internal subsystems provide
149 signal next_i_rd_cycle2_s : std_logic; -- data only after 2 cycles
151 signal address_f_s : std_logic_vector(15 downto 0); -- Filtered address
153 signal data_f_s : std_logic_vector(31 downto 0); -- Filterred input data
155 signal data_read_s : std_logic_vector(31 downto 0); -- Latched read data
156 signal next_data_read_s : std_logic_vector(31 downto 0);
159 signal bls_f_s : std_logic_vector(3 downto 0); -- Filtered BLS (active 1)
160 signal i_bls_s : std_logic_vector(3 downto 0); -- Internal BLS (active 1)
161 signal next_i_bls_s : std_logic_vector(3 downto 0);
163 signal data_write_s : std_logic_vector(31 downto 0); -- Data broadcasted to write
164 signal next_data_write_s : std_logic_vector(31 downto 0);
167 signal tumbl_bls_s : std_logic_vector(3 downto 0);
168 signal tumbl_address_s : std_logic_vector(14 downto 0);
169 signal tumbl_data_i_s : std_logic_vector(31 downto 0);
171 signal tumbl_xmemb_o_s : CORE2DMEMB_Type;
172 signal tumbl_xmemb_i_s : DMEMB2CORE_Type;
173 signal tumbl_xmemb_sel_s : std_logic;
174 -- Interrupt event sources and processing
175 signal lxmaster_rx_done_s : std_logic;
176 signal lxmaster_rx_done_r : std_logic;
177 signal lxmaster_rx_done_last_s : std_logic;
178 signal lxmaster_rx_done_last_r : std_logic;
180 -- signal s0 : std_logic;
181 -- signal s1 : std_logic;
182 -- signal s2 : std_logic;
185 attribute REGISTER_DUPLICATION : string;
186 attribute REGISTER_DUPLICATION of rd : signal is "NO";
187 attribute REGISTER_DUPLICATION of rd_f_s : signal is "NO";
188 attribute REGISTER_DUPLICATION of bls : signal is "NO";
189 attribute REGISTER_DUPLICATION of bls_f_s : signal is "NO";
190 attribute REGISTER_DUPLICATION of address : signal is "NO";
191 attribute REGISTER_DUPLICATION of address_f_s : signal is "NO";
192 attribute REGISTER_DUPLICATION of cs0_xc : signal is "NO";
193 attribute REGISTER_DUPLICATION of cs0_xc_f_s : signal is "NO";
198 memory_bus_tumbl: bus_tumbl
205 address_i => address_f_s(11 downto 0),
207 data_o => tumbl_out_s,
209 xmemb_o => tumbl_xmemb_o_s,
210 xmemb_i => tumbl_xmemb_i_s,
211 xmemb_sel_o => tumbl_xmemb_sel_s
215 memory_bus_measurement: bus_measurement
221 address_i => address_f_s(1 downto 0),
228 memory_bus_irc: bus_irc
234 address_i => tumbl_address_s(4 downto 0),
235 next_ce_i => irc_proc_next_ce_s,
236 data_i => tumbl_data_i_s,
237 data_o => irc_proc_out_s,
238 bls_i => tumbl_bls_s,
240 irc_i(0).a => irc0_a,
241 irc_i(0).b => irc0_b,
242 irc_i(0).index => irc0_index,
243 irc_i(0).mark => irc0_mark,
245 irc_i(1).a => irc1_a,
246 irc_i(1).b => irc1_b,
247 irc_i(1).index => irc1_index,
248 irc_i(1).mark => irc1_mark,
250 irc_i(2).a => irc2_a,
251 irc_i(2).b => irc2_b,
252 irc_i(2).index => irc2_index,
253 irc_i(2).mark => irc2_mark,
255 irc_i(3).a => irc3_a,
256 irc_i(3).b => irc3_b,
257 irc_i(3).index => irc3_index,
258 irc_i(3).mark => irc3_mark,
260 irc_i(4).a => irc4_a,
261 irc_i(4).b => irc4_b,
262 irc_i(4).index => irc4_index,
263 irc_i(4).mark => irc4_mark,
265 irc_i(5).a => irc5_a,
266 irc_i(5).b => irc5_b,
267 irc_i(5).index => irc5_index,
268 irc_i(5).mark => irc5_mark,
270 irc_i(6).a => irc6_a,
271 irc_i(6).b => irc6_b,
272 irc_i(6).index => irc6_index,
273 irc_i(6).mark => irc6_mark,
275 irc_i(7).a => irc7_a,
276 irc_i(7).b => irc7_b,
277 irc_i(7).index => irc7_index,
278 irc_i(7).mark => irc7_mark
282 memory_bus_lxmaster: bus_lxmaster
288 address_i => tumbl_address_s(10 downto 0),
289 next_ce_i => lxmaster_next_ce_s,
290 data_i => tumbl_data_i_s(15 downto 0),
291 data_o => lxmaster_out_s,
292 bls_i => tumbl_bls_s(1 downto 0),
294 rx_done_o => lxmaster_rx_done_s,
296 clock_i => s1_clk_in,
298 sync_i => s1_sync_in,
300 clock_o => s1_clk_out,
302 sync_o => s1_sync_out
315 -- s1_sync_out <= s2;
318 function_approx: component lx_fncapprox
324 address_i => tumbl_address_s(4 downto 0),
325 next_ce_i => lxfncapprox_next_ce_s,
326 data_i => tumbl_data_i_s,
327 data_o => lxfncapprox_out_s,
344 data_i_s <= data_write_s;
347 tumbl_bls_s <= i_bls_s when (master_tumbl_xmem_lock_s = '1')
348 else tumbl_xmemb_o_s.bls when (tumbl_xmemb_sel_s = '1')
350 tumbl_address_s <= address_f_s(14 downto 0) when (master_tumbl_xmem_lock_s = '1')
351 else tumbl_xmemb_o_s.addr when (tumbl_xmemb_sel_s = '1')
352 else (others => '0');
353 tumbl_data_i_s <= data_i_s when (master_tumbl_xmem_lock_s = '1')
354 else tumbl_xmemb_o_s.data when (tumbl_xmemb_sel_s = '1')
355 else (others => '0');
357 tumbl_xmemb_i_s.int <= '0'; -- No interrupt
358 -- Enable clken only when available for Tumbl
359 tumbl_xmemb_i_s.bus_taken <= master_tumbl_xmem_lock_s;
360 tumbl_xmemb_i_s.bus_wait <= '0';
366 process(cs0_xc_f_s, rd_f_s, last_rd_s, i_rd_cycle2_s, last_i_rd_s,
367 bls_f_s, last_bls_s, data_f_s, data_write_s,
368 data_o_s, data_read_s, last_address_s, address_f_s)
371 next_i_rd_cycle2_s <= '0';
372 next_address_hold_s <= '0';
374 -- Check if we have chip select
375 if cs0_xc_f_s = '1' then
380 if last_rd_s = '0' or (last_address_s /= address_f_s) then
382 next_i_rd_cycle2_s <= '1';
383 next_last_i_rd_s <= '1';
384 elsif i_rd_cycle2_s = '1' then -- FIXME it seems that some internal
385 i_rd_s <= '1'; -- peripherals demands 2 cycles to read
386 next_last_i_rd_s <= '1';
389 next_last_i_rd_s <= '0';
392 if last_i_rd_s = '1' then
393 -- Latch data we just read - they are valid in this cycle
394 next_data_read_s <= data_o_s;
396 next_data_read_s <= data_read_s;
399 -- -- Not reading, anything goes
400 -- data_read_s <= (others => 'X');
401 next_data_read_s <= data_read_s;
403 next_last_i_rd_s <= '0';
406 next_last_rd_s <= rd_f_s;
408 -- Data for write are captured only when BLS signals are stable
409 if bls_f_s /= "0000" then
410 next_data_write_s <= data_f_s;
411 next_address_hold_s <= '1';
413 next_data_write_s <= data_write_s;
416 if (bls_f_s /= "0000") or (rd_f_s = '1') then
417 next_last_address_s <= address_f_s;
419 next_last_address_s <= last_address_s;
422 next_last_rd_s <= '0';
424 next_last_i_rd_s <= '0';
426 next_i_bls_s <= "0000";
427 next_data_write_s <= data_write_s;
428 next_data_read_s <= data_read_s;
429 next_last_address_s <= last_address_s;
432 -- Data for write are captured at/before BLS signals are negated
433 -- and actual write cycle takes place exacly after BLS negation
434 if ((last_bls_s and not bls_f_s) /= "0000") or
435 ((last_bls_s /= "0000") and (cs0_xc_f_s = '0')) then
436 next_i_bls_s <= last_bls_s;
437 next_last_bls_s <= "0000";
438 next_address_hold_s <= '1';
440 next_i_bls_s <= "0000";
441 if cs0_xc_f_s = '1' then
442 next_last_bls_s <= bls_f_s;
444 next_last_bls_s <= "0000" ;
455 wait until clk_50m = '1' and clk_50m'event;
457 address_hold_s <= next_address_hold_s;
459 -- Synchronized external signals with main clock domain
460 cs0_xc_f_s <= not cs0_xc;
464 if address_hold_s = '0' then
465 address_f_s <= address;
467 address_f_s <= next_last_address_s;
470 -- Synchronoust state andvance to next period
471 last_bls_s <= next_last_bls_s;
472 last_rd_s <= next_last_rd_s;
473 i_bls_s <= next_i_bls_s;
474 -- i_rd_s <= next_i_rd_s;
475 i_rd_cycle2_s <= next_i_rd_cycle2_s;
476 last_i_rd_s <= next_last_i_rd_s;
477 data_write_s <= next_data_write_s;
478 last_address_s <= next_last_address_s;
479 data_read_s <= next_data_read_s;
481 -- ======================================================
483 -- ======================================================
485 -- Just copy these to their desired next state
486 irc_proc_ce_s <= irc_proc_next_ce_s;
487 lxmaster_ce_s <= lxmaster_next_ce_s;
488 lxfncapprox_ce_s <= lxfncapprox_next_ce_s;
492 -- Do the actual wiring here
494 process(cs0_xc_f_s, i_bls_s, address_f_s, tumbl_out_s, meas_out_s, master_tumbl_xmem_out_s)
497 -- Inactive by default
500 master_tumbl_xmem_ce_s <= '0';
501 data_o_s <= (others => '0');
503 if cs0_xc_f_s = '1' or i_bls_s /= "0000" then
505 -- Memory Map (16-bit address @ 32-bit each)
507 -- Each address is seen as 32-bit entry now
508 -- 0x0000 - 0x0FFF: Tumbl IMEM / DMEM
509 -- 0x1FFC - 0x1FFF: Measurement
510 -- 0x8000 - 0x8FFF: Tumbl BUS
512 if address_f_s < "0001000000000000" then -- Tumbl
514 data_o_s <= tumbl_out_s;
515 elsif address_f_s(15 downto 2) = "00011111111111" then -- Measurement
517 data_o_s <= meas_out_s;
518 elsif address_f_s(15) = '1' then -- Tumbl External BUS
519 master_tumbl_xmem_ce_s <= '1';
520 data_o_s <= master_tumbl_xmem_out_s;
527 -- If RD and BLS is not high, we must keep DATA at high impedance
528 -- or the FPGA collides with SDRAM (damaging each other)
530 process(cs0_xc, rd, data_read_s)
533 -- CS0 / RD / BLS are active LOW
534 if cs0_xc = '0' and rd = '0' then
535 -- Don't risk flipping (between data_o_s and latched data_read_s, it's better to wait)
536 -- Maybe check this later.
537 -- if last_i_rd_s = '1' then
544 data <= (others => 'Z');
549 -- Outputs from Tumbl (enabling and address muxing) and Master CPU
551 process(tumbl_xmemb_sel_s, tumbl_xmemb_o_s, master_tumbl_xmem_ce_s, address_f_s, i_rd_s, i_bls_s)
552 variable addr_v : std_logic_vector(14 downto 0); -- This space is visible by both (32-bit)
553 variable sel_v : std_logic;
557 irc_proc_next_ce_s <= '0';
558 lxmaster_next_ce_s <= '0';
559 lxfncapprox_next_ce_s <= '0';
560 master_tumbl_xmem_lock_s <= '0';
562 addr_v := (others => '0');
565 -- Check who is accessing
566 if master_tumbl_xmem_ce_s = '1' and (i_rd_s = '1' or i_bls_s /= "0000") then
567 -- Master blocks Tumbl
568 master_tumbl_xmem_lock_s <= '1';
569 addr_v := address_f_s(14 downto 0);
572 addr_v := tumbl_xmemb_o_s.addr;
577 -- IRC: 0x0800 - 0x081F (32-bit address)
578 -- LX FNC AP: 0x0C00 - 0x0C1F (32-bit address)
579 -- LX MASTER: 0x1000 - 0x17FF (32-bit address)
580 if addr_v(14 downto 5) = "0001000000" then
581 irc_proc_next_ce_s <= '1';
582 elsif addr_v(14 downto 5) = "0001100000" then
583 lxfncapprox_next_ce_s <= '1';
584 elsif addr_v(14 downto 11) = "0010" then
585 lxmaster_next_ce_s <= '1';
591 -- Inputs to Tumbl (enabling and address muxing)
593 process(irc_proc_ce_s, irc_proc_out_s, lxmaster_ce_s, lxmaster_out_s,
594 lxfncapprox_ce_s, lxfncapprox_out_s, tumbl_xmemb_i_s)
597 tumbl_xmemb_i_s.data <= (others => 'X');
599 -- NOTE: This is input to Tumbl EXEQ - with MUL instruction for input > 18-bit,
600 -- (i.e. more DSPs in a sequence), this already has tough timing constraints
601 -- and SmartXplorer has to be used with XiSE or use Synplify.
602 if irc_proc_ce_s = '1' then
603 tumbl_xmemb_i_s.data <= irc_proc_out_s;
604 elsif lxmaster_ce_s = '1' then
605 tumbl_xmemb_i_s.data(15 downto 0) <= lxmaster_out_s;
606 tumbl_xmemb_i_s.data(31 downto 16) <= (others => '0');
607 elsif lxfncapprox_ce_s = '1' then
608 tumbl_xmemb_i_s.data <= lxfncapprox_out_s;
611 master_tumbl_xmem_out_s <= tumbl_xmemb_i_s.data;
616 process(lxmaster_rx_done_r, lxmaster_rx_done_last_r)
618 event_jk_j <= lxmaster_rx_done_r or lxmaster_rx_done_last_r;
619 lxmaster_rx_done_last_s <= lxmaster_rx_done_r;
625 wait until clk_50m = '1' and clk_50m'event;
627 lxmaster_rx_done_r <= lxmaster_rx_done_s;
628 lxmaster_rx_done_last_r <= lxmaster_rx_done_last_s;