return CMDERR_TIMEOUT;
}
}
- if (status & (1 << 2)) {
+ if (status & FPGA_DAD_CTRL_BANK_m) {
testaddr = fpga_dad_result_bank1;
} else {
testaddr = fpga_dad_result_bank0;
val += (1 << 17);
val &= (1 << 18) - 1;
val -= (1 << 17);
- values[i] = -1 * val;
+ values[i] = +1 * val;
}
fprintf(F, "bank%d status 0x%02"PRIx32" old 0x%02"PRIx32
" wait cycles %"PRId32"\r\n",
return 0;
}
+int cmd_do_phasetime(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
+{
+ int res;
+ int opchar;
+ long val;
+ char *p;
+ int tn = (int)(intptr_t)des->info[0];
+ volatile uint32_t *paraddr;
+
+ if((opchar=cmd_opchar_check(cmd_io,des,param))<0) return opchar;
+
+ if(tn==-1)
+ tn=*param[1]-'0';
+
+ if ((tn < 1) || (tn > 16))
+ return CMDERR_BADSUF;
+
+ paraddr = fpga_dad_sens_timing + tn - 1;
+
+ if (opchar == '?')
+ return cmd_opchar_replong(cmd_io, param, *paraddr, 0, 0);
+
+ if (opchar != ':')
+ return CMDERR_OPCHAR;
+
+ p=param[3];
+ if(si_long(&p,&val,0)<0) return -CMDERR_BADPAR;
+ si_skspace(&p);
+ if(*p) return -CMDERR_GARBAG;
+ *paraddr=val;
+
+ return 0;
+}
int cmd_do_init(cmd_io_t *cmd_io, const struct cmd_des *des, char *param[])
{
FILE *F;
+ uint32_t mode = (uint32_t)des->info[0];
F = cmd_io_as_direct_file(cmd_io, "r+");
- fprintf(F, "init!\r\n");
+ fprintf(F, "init 0x%02"PRIx32"!\r\n", mode);
volatile uint32_t *testaddr = fpga_dad_sens_timing;
- *fpga_dad_ctrl_reg = FPGA_DAD_CTRL_STD_m;
+ *fpga_dad_ctrl_reg = mode & ~(FPGA_DAD_CTRL_CR_m | FPGA_DAD_CTRL_SR_m);
// *testaddr++;
*testaddr++ = 9;
*testaddr++ = 5023999;
*testaddr=499;
- *fpga_dad_ctrl_reg = FPGA_DAD_CTRL_STD_m | FPGA_DAD_CTRL_CR_m;
+ *fpga_dad_ctrl_reg = mode;
fprintf(F, "OK!\r\n");
fclose(F);
"scan", "read values from spectrometer (2 readouts)",
cmd_do_single, {(void*)0x10}};
+cmd_des_t const cmd_des_phasetime={0, CDESM_OPCHR|CDESM_RW,
+ "PHT#","Phase # time",
+ cmd_do_phasetime,{(void*)-1}};
+
cmd_des_t const cmd_des_init={0, 0,
- "init", "inicializacni vypis pro zacatek komunikace",
- cmd_do_init, {(void*)0}};
+ "init", "initialize DAD converter for continuous reading",
+ cmd_do_init, {(void*)(FPGA_DAD_CTRL_STD_m | FPGA_DAD_CTRL_CR_m)}};
+
+cmd_des_t const cmd_des_initmulti={0, 0,
+ "initmulti", "initialize DAD converter for multivalue read",
+ cmd_do_init, {(void*)(FPGA_DAD_CTRL_MULT_m | FPGA_DAD_CTRL_CR_m)}};
cmd_des_t const cmd_des_sendvalue={0, 0,
"send", "send value to given address",
cmd_des_t const cmd_des_running_meas = {0, 0,
"run", "read values from spectrometer (running)",
- cmd_do_running_meas, {(void*)0x10}};
+ cmd_do_running_meas, {(void*)0}};
cmd_des_t const *const cmd_appl_tests[]={
&cmd_des_test_memusage,
&cmd_des_dadstatus,
&cmd_des_zmer,
&cmd_des_scan,
+ &cmd_des_phasetime,
&cmd_des_init,
+ &cmd_des_initmulti,
&cmd_des_sendvalue,
& cmd_des_running_meas,
NULL