board/advantech/imx6q-rsb4411-a1/merica-terminal.dts

   1 /*
   2  * Copyright 2012 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14
  15 #include "imx6q.dtsi"
  16 #include "imx6qdl-advantech.dtsi"
  17
  18 / {
  19         model = "Freescale i.MX6 Quad RSB4411 A1";
  20         compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
  21
  22         board {
  23                 compatible = "proc-board";
  24                 board-type = "RSB-4411 A1";
  25                 board-cpu = "DualQuad";
  26         };
  27
  28         regulators {
  29                 reg_usb_otg_vbus: usb_otg_vbus {
  30                         compatible = "regulator-fixed";
  31                         regulator-name = "usb_otg_vbus";
  32                         regulator-min-microvolt = <5000000>;
  33                         regulator-max-microvolt = <5000000>;
  34                         gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
  35                         enable-active-high;
  36                 };
  37         };
  38         aliases {
  39                         mmc2 = &usdhc1;
  40                         mmc1 = &usdhc3;
  41                         mmc0 = &usdhc4;
  42                 };
  43
  44     gpio-keys {
  45         compatible = "gpio-keys";
  46         #address-cells = <1>;
  47         #size-cells = <0>;
  48         label = "gpio-keys";
  49         gpio01 {
  50             label = "gpio01";
  51             gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
  52             linux,code = <KEY_A>;
  53             gpio-key,wakeup;
  54         };
  55         gpio02 {
  56             label = "gpio02";
  57             gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
  58             linux,code = <KEY_B>;
  59             gpio-key,wakeup;
  60         };
  61         gpio03 {
  62             label = "gpio03";
  63             gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
  64             linux,code = <KEY_C>;
  65             gpio-key,wakeup;
  66         };
  67         gpio04 {
  68             label = "gpio04";
  69             gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
  70             linux,code = <KEY_D>;
  71             gpio-key,wakeup;
  72         };
  73         gpio05 {
  74             label = "gpio05";
  75             gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
  76             linux,code = <KEY_E>;
  77             gpio-key,wakeup;
  78         };
  79         gpio06 {
  80             label = "gpio06";
  81             gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
  82             linux,code = <KEY_F>;
  83             gpio-key,wakeup;
  84         };
  85         gpio07 {
  86             label = "gpio07";
  87             gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
  88             linux,code = <KEY_G>;
  89             gpio-key,wakeup;
  90         };
  91         gpio08 {
  92             label = "gpio08";
  93             gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
  94             linux,code = <KEY_H>;
  95             gpio-key,wakeup;
  96         };
  97         gpio09 {
  98             label = "gpio09";
  99             gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
 100             linux,code = <KEY_I>;
 101             gpio-key,wakeup;
 102         };
 103         gpio10 {
 104             label = "gpio10";
 105             gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
 106             linux,code = <KEY_J>;
 107             gpio-key,wakeup;
 108         };
 109         gpio11 {
 110             label = "gpio11";
 111             gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 112             linux,code = <KEY_K>;
 113             gpio-key,wakeup;
 114         };
 115         gpio12 {
 116             label = "gpio12";
 117             gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 118             linux,code = <KEY_L>;
 119             gpio-key,wakeup;
 120         };
 121         gpio13 {
 122             label = "gpio13";
 123             gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 124             linux,code = <KEY_M>;
 125             gpio-key,wakeup;
 126         };
 127         gpio14 {
 128             label = "gpio14";
 129             gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
 130             linux,code = <KEY_N>;
 131             gpio-key,wakeup;
 132         };
 133         gpio15 {
 134             label = "gpio15";
 135             gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
 136             linux,code = <KEY_O>;
 137             gpio-key,wakeup;
 138         };
 139         gpio16 {
 140             label = "gpio16";
 141             gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
 142             linux,code = <KEY_P>;
 143             gpio-key,wakeup;
 144         };
 145         gpio17 {
 146             label = "gpio17";
 147             gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
 148             linux,code = <KEY_Q>;
 149             gpio-key,wakeup;
 150         };
 151         gpio18 {
 152             label = "gpio18";
 153             gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
 154             linux,code = <KEY_R>;
 155             gpio-key,wakeup;
 156         };
 157         gpio19 {
 158             label = "gpio19";
 159             gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 160             linux,code = <KEY_S>;
 161             gpio-key,wakeup;
 162         };
 163         gpio20 {
 164             label = "gpio20";
 165             gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
 166             linux,code = <KEY_T>;
 167             gpio-key,wakeup;
 168         };
 169     };
 170
 171 };
 172
 173 &audio_sgtl5000 {
 174         audio-codec = <&codec>;
 175         mux-ext-port = <4>;
 176         status = "okay";
 177 };
 178
 179 &bkl {
 180         lvds-bkl-enable = <&gpio4 6 1>;
 181         lvds-vcc-enable = <&gpio4 7 1>;
 182         pwms = <&pwm2 0 5000000>;
 183         status = "okay";
 184 };
 185
 186 &ecspi2 {
 187         fsl,spi-num-chipselects = <1>;
 188         cs-gpios = <&gpio2 26 0>;
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&pinctrl_ecspi2_cs_0 &pinctrl_ecspi2_1>;
 191         status = "okay";
 192
 193         m25p80@0 {
 194                 #address-cells = <1>;
 195                 #size-cells = <1>;
 196                 compatible = "micron,n25qba16";
 197                 spi-max-frequency = <20000000>;
 198                 reg = <0>;
 199         };
 200 };
 201
 202
 203
 204 &can1 {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_flexcan1_1>;
 207         status = "okay";
 208 };
 209
 210 &can2 {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pinctrl_flexcan2_1>;
 213         status = "okay";
 214 };
 215
 216 &i2c1 {
 217
 218         codec: sgtl5000@0a {
 219                 compatible = "fsl,sgtl5000";
 220                 reg = <0x0a>;
 221                 clocks = <&clks 201>;
 222                 VDDA-supply = <&reg_2p5v>;
 223                 VDDIO-supply = <&reg_3p3v>;
 224                 mclk = <16000000>;
 225                 mclk_source = <0>;
 226         };
 227
 228         s35390a@30 {
 229                 compatible = "fsl,s35390a";
 230                 reg = <0x30>;
 231         };
 232
 233         wdt@29 {
 234                 compatible = "fsl,adv-wdt-i2c";
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&pinctrl_wdt_en_1 &pinctrl_wdt_ping_1>;
 237                 status = "okay";
 238                 wdt-en = <&gpio2 5 0>;
 239                 wdt-ping = <&gpio1 9 0>;
 240                 reg = <0x29>;
 241         };
 242
 243         ov5640_mipi: ov5640_mipi@3c {
 244                 compatible = "ovti,ov564x_mipi";
 245                 reg = <0x3c>;
 246                 clocks = <&clks 201>;
 247                 clock-names = "csi_mclk";
 248                 DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
 249                 AVDD-supply = <&reg_3p3v>;  /* 1.8v */
 250                 DVDD-supply = <&reg_3p3v>;  /* 1.8v */
 251                 PVDD-supply = <&reg_3p3v>;  /* 1.8v */
 252                 pwn-gpios = <&gpio1 2 1>;   /* active low: SD1_CLK */
 253                 rst-gpios = <&gpio1 5 0>;   /* active high: SD1_DAT2 */
 254                 csi_id = <1>;
 255                 mclk = <24000000>;
 256                 mclk_source = <0>;
 257         };
 258
 259         24c32@51 {
 260                 compatible = "fsl,24c32";
 261                 reg = <0x51>;
 262         };
 263
 264
 265 };
 266
 267 &i2c2 {
 268
 269         hdmi_edid: edid@50 {
 270                 compatible = "fsl,imx6-hdmi-i2c";
 271                 reg = <0x50>;
 272         };
 273 };
 274
 275 &i2c3 {
 276
 277         ch7055@76 {
 278                 compatible = "fsl,ch7055";
 279                 reg = <0x76>;
 280         };
 281
 282         mxc_vga_i2c@50 {
 283                 compatible = "fsl,mxc_vga_i2c";
 284                 reg = <0x50>;
 285         };
 286
 287         24c32@51 {
 288                 compatible = "fsl,24c32";
 289                 reg = <0x51>;
 290         };
 291 };
 292
 293 &iomuxc {
 294         pinctrl-names = "default";
 295         pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_2>;
 296
 297         hog {
 298                 pinctrl_hog_1: hoggrp-1 {
 299                         fsl,pins = <
 300                                 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x80000000      /* SD3_CD */
 301                                 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x80000000      /* SD3_WP */
 302                                 MX6QDL_PAD_SD2_CMD__GPIO1_IO11          0x80000000      /* SDIO RST */
 303                                 MX6QDL_PAD_SD2_CLK__GPIO1_IO10          0x80000000      /* SDIO WAKE */
 304                                 MX6QDL_PAD_NANDF_D7__GPIO2_IO07         0x80000000      /* M.2 WLAN OFF */
 305                                 MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x80000000      /* M.2 BT OFF */
 306                                 MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x80000000      /* UART 5 WAKE */
 307                                 MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0         /* AUDIO CLK */
 308                         >;
 309                 };
 310                 pinctrl_hog_2: hoggrp-2 {
 311                         fsl,pins = <
 312                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27        0x80000000      /* GPIO1 */
 313                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x80000000      /* GPIO2 */
 314                                 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25      0x80000000      /* GPIO3 */
 315                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x80000000      /* GPIO4 */
 316                                 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31         0x80000000      /* GPIO5 */
 317                                 MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x80000000      /* GPIO6 */
 318                                 MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x80000000      /* GPIO7 */
 319                                 MX6QDL_PAD_EIM_D21__GPIO3_IO21          0x80000000      /* GPIO8 */
 320                                 MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x80000000      /* GPIO9 */
 321                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x80000000      /* GPI10 */
 322                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x80000000      /* GPI11 */
 323                                 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x80000000      /* GPI12 */
 324                                 MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x80000000      /* GPI13 */
 325                                 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x80000000      /* GPI14 */
 326                                 MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x80000000      /* GPI15 */
 327                                 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x80000000      /* GPI16 */
 328                                 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07        0x80000000      /* GPI17 */
 329                                 MX6QDL_PAD_NANDF_D4__GPIO2_IO04         0x80000000      /* GPI18 */
 330                                 MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x80000000      /* GPI19 */
 331                                 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x80000000      /* GPI20 */
 332                         >;
 333                 };
 334         };
 335
 336         mipi-csi {
 337                 pinctrl_mipi_csi_1: mipi_csi1grp-1{
 338                         fsl,pins = <
 339                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x80000000      /* GPIO1=MIPICSI_PWN */
 340                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x80000000      /* GPIO3=MIPICSI_RST */
 341                                 MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1         0x80000000      /* CSI0_MCLK */
 342                         >;
 343                 };
 344         };
 345
 346         pcie {
 347                 pinctrl_pcie_1: pciegrp-1 {
 348                         fsl,pins = <
 349                                 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15                0x80000000      /* 3G_RF_OFF */
 350                         >;
 351                 };
 352         };
 353
 354         pwm {
 355                 pinctrl_pwm2_1: pwm2grp-1 {
 356                         fsl,pins = <
 357                                 MX6QDL_PAD_GPIO_1__PWM2_OUT                     0x1b0b1
 358                         >;
 359                 };
 360         };
 361
 362         spi1 {
 363                 pinctrl_ecspi1_cs_0: ecspi1_cs_grp-0 {
 364                         fsl,pins = <
 365                                 MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x80000000      /* ECSPI1_CS0 */
 366                         >;
 367                 };
 368         };
 369
 370         spi2 {
 371                 pinctrl_ecspi2_cs_0: ecspi2_cs_grp-0 {
 372                         fsl,pins = <
 373                                 MX6QDL_PAD_EIM_RW__GPIO2_IO26           0x80000000      /* ECSPI2_CS0 */
 374                         >;
 375                 };
 376                 pinctrl_ecspi2_1: ecspi2grp-1 {
 377                         fsl,pins = <
 378                                 MX6QDL_PAD_EIM_OE__ECSPI2_MISO          0x170f1         /* ECSPI2_MISO */
 379                                 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK         0x170f1         /* ECSPI2_CLK */
 380                                 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI         0x1B008         /* ECSPI2_MOSI */
 381                         >;
 382                 };
 383         };
 384
 385         uart2 {
 386                 pinctrl_uart2_3: uart2grp-3 { /* DCE mode */
 387                         fsl,pins = <
 388                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
 389                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
 390                                 MX6QDL_PAD_EIM_D28__UART2_CTS_B         0x1b0b1
 391                                 MX6QDL_PAD_EIM_D29__UART2_RTS_B         0x1b0b1
 392                         >;
 393                 };
 394         };
 395
 396         uart3 {
 397                 pinctrl_uart3_1: uart3grp-1 {
 398                         fsl,pins = <
 399                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 400                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 401                         >;
 402                 };
 403         };
 404
 405         uart4 {
 406                 pinctrl_uart4_1: uart4grp-1 {
 407                         fsl,pins = <
 408                                 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
 409                                 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
 410                         >;
 411                 };
 412         };
 413
 414         uart5 {
 415                 pinctrl_uart5_2: uart5grp-1 {
 416                         fsl,pins = <
 417                                 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x1b0b1
 418                                 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x1b0b1
 419                                 MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B      0x1b0b1
 420                                 MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B      0x1b0b1
 421                         >;
 422                 };
 423         };
 424
 425         wdt{
 426                 pinctrl_wdt_en_1: wdt_engrp-1 {
 427                         fsl,pins = <
 428                                 MX6QDL_PAD_NANDF_D5__GPIO2_IO05         0x80000000
 429                         >;
 430                 };
 431                 pinctrl_wdt_ping_1: wdt_pinggrp-1 {
 432                         fsl,pins = <
 433                                 MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x80000000
 434                         >;
 435                 };
 436         };
 437
 438         usbotg {
 439                 pinctrl_usbotg_3: usbh1_grp-3 {
 440                         fsl,pins = <
 441                                 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x80000000      /* USB_OTG_PWR */
 442                         >;
 443                 };
 444         };
 445
 446 };
 447
 448 &mipi_csi {
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&pinctrl_mipi_csi_1>;
 451         status = "okay";
 452 };
 453
 454 &audmux {
 455         pinctrl-names = "default";
 456         pinctrl-0 = <&pinctrl_audmux_1>;
 457         status = "okay";
 458 };
 459
 460 &ldb {
 461         status = "okay";
 462 };
 463
 464 &mxcfb1 {
 465         status = "okay";
 466 };
 467
 468 &mxcfb2 {
 469         status = "okay";
 470 };
 471
 472 &mxcfb3 {
 473         status = "okay";
 474 };
 475
 476 &mxcfb4 {
 477         status = "okay";
 478 };
 479
 480 &pcie {
 481         pinctrl-names = "default";
 482         pinctrl-0 = <&pinctrl_pcie_1>;
 483         disable-gpio = <&gpio6 15 0>;
 484         status = "okay";
 485 };
 486
 487 &pwm2 {
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&pinctrl_pwm2_1>;
 490         status = "okay";
 491 };
 492
 493 &uart1 {
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&pinctrl_uart1_1>;
 496         status = "okay";
 497 };
 498
 499 &uart2 {
 500         pinctrl-names = "default";
 501         pinctrl-0 = <&pinctrl_uart2_3>;
 502         fsl,uart-has-rtscts;
 503         status = "okay";
 504 };
 505
 506 &uart3 {
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&pinctrl_uart3_1>;
 509         status = "okay";
 510 };
 511
 512 &uart4 {
 513         pinctrl-names = "default";
 514         pinctrl-0 = <&pinctrl_uart4_1>;
 515         status = "okay";
 516 };
 517
 518 &uart5 {
 519         pinctrl-names = "default";
 520         pinctrl-0 = <&pinctrl_uart5_2>;
 521         status = "okay";
 522 };
 523
 524 &sata {
 525         status = "okay";
 526 };
 527
 528 &usbh1 {
 529         status = "okay";
 530 };
 531
 532 &usbotg {
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&pinctrl_usbotg_2 &pinctrl_usbotg_3>;
 535         vbus-supply = <&reg_usb_otg_vbus>;
 536         imx6-usb-charger-detection;
 537         status = "okay";
 538 };
 539
 540 &usdhc1 {
 541         pinctrl-names = "default";
 542         pinctrl-0 = <&pinctrl_usdhc1_1>;
 543         bus-width = <4>;
 544         status = "okay";
 545 };
 546
 547 &usdhc3 {
 548         pinctrl-names = "default";
 549         pinctrl-0 = <&pinctrl_usdhc3_2>;
 550         bus-width = <4>;
 551         cd-gpios = <&gpio7 1 0>;
 552         wp-gpios = <&gpio7 0 0>;
 553         status = "okay";
 554 };
 555
 556 &usdhc4 {
 557         pinctrl-names = "default";
 558         pinctrl-0 = <&pinctrl_usdhc4_1>;
 559         bus-width = <8>;
 560         non-removable;
 561         no-1-8-v;
 562         keep-power-in-suspend;
 563         status = "okay";
 564 };
 565
 566 &v4l2_capture_1 {
 567         status = "okay";
 568 };
 569
 570 &wdog1 {
 571         status = "disabled";
 572 };