1 # mips default CPU ISAs
2 config BR2_MIPS_CPU_MIPS32
4 select BR2_MIPS_NAN_LEGACY
5 config BR2_MIPS_CPU_MIPS32R2
7 select BR2_MIPS_NAN_LEGACY
8 config BR2_MIPS_CPU_MIPS32R5
10 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
11 config BR2_MIPS_CPU_MIPS32R6
13 select BR2_MIPS_NAN_2008
14 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
15 config BR2_MIPS_CPU_MIPS64
17 select BR2_MIPS_NAN_LEGACY
18 config BR2_MIPS_CPU_MIPS64R2
20 select BR2_MIPS_NAN_LEGACY
21 config BR2_MIPS_CPU_MIPS64R5
23 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
24 config BR2_MIPS_CPU_MIPS64R6
26 select BR2_MIPS_NAN_2008
27 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
30 prompt "Target Architecture Variant"
31 depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
32 default BR2_mips_32 if BR2_mips || BR2_mipsel
33 default BR2_mips_64 if BR2_mips64 || BR2_mips64el
35 Specific CPU variant to use
37 64bit cabable: 64, 64r2, 64r5, 64r6
38 non-64bit capable: 32, 32r2, 32r5, 32r6
42 depends on !BR2_ARCH_IS_64
43 select BR2_MIPS_CPU_MIPS32
45 bool "Generic MIPS32R2"
46 depends on !BR2_ARCH_IS_64
47 select BR2_MIPS_CPU_MIPS32R2
49 bool "Generic MIPS32R5"
50 depends on !BR2_ARCH_IS_64
51 select BR2_MIPS_CPU_MIPS32R5
53 bool "Generic MIPS32R6"
54 depends on !BR2_ARCH_IS_64
55 select BR2_MIPS_CPU_MIPS32R6
56 config BR2_mips_interaptiv
58 depends on !BR2_ARCH_IS_64
59 select BR2_MIPS_CPU_MIPS32R2
60 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
63 depends on !BR2_ARCH_IS_64
64 select BR2_MIPS_CPU_MIPS32R5
65 select BR2_MIPS_NAN_2008
66 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
69 depends on !BR2_ARCH_IS_64
70 select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
71 select BR2_MIPS_CPU_MIPS32R6
74 depends on !BR2_ARCH_IS_64
75 select BR2_MIPS_CPU_MIPS32R5
76 select BR2_MIPS_NAN_2008
77 config BR2_mips_xburst
79 depends on !BR2_ARCH_IS_64
80 select BR2_MIPS_CPU_MIPS32R2
82 The Ingenic XBurst is a MIPS32R2 microprocessor. It has a
83 bug in the FPU that can generate incorrect results in
84 certain cases. The problem shows up when you have several
85 fused madd instructions in sequence with dependant
86 operands. This requires the -mno-fused-madd compiler option
87 to be used in order to prevent emitting these instructions.
89 See http://www.ingenic.com/en/?xburst.html
92 depends on BR2_ARCH_IS_64
93 select BR2_MIPS_CPU_MIPS64
95 bool "Generic MIPS64R2"
96 depends on BR2_ARCH_IS_64
97 select BR2_MIPS_CPU_MIPS64R2
99 bool "Generic MIPS64R5"
100 depends on BR2_ARCH_IS_64
101 select BR2_MIPS_CPU_MIPS64R5
103 bool "Generic MIPS64R6"
104 depends on BR2_ARCH_IS_64
105 select BR2_MIPS_CPU_MIPS64R6
106 config BR2_mips_i6400
108 depends on BR2_ARCH_IS_64
109 select BR2_MIPS_CPU_MIPS64R6
110 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6
111 config BR2_mips_p6600
113 depends on BR2_ARCH_IS_64
114 select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
115 select BR2_MIPS_CPU_MIPS64R6
121 depends on BR2_mips64 || BR2_mips64el
122 default BR2_MIPS_NABI32
125 Application Binary Interface to use
127 config BR2_MIPS_NABI32
129 depends on BR2_ARCH_IS_64
130 select BR2_KERNEL_64_USERLAND_32
131 config BR2_MIPS_NABI64
133 depends on BR2_ARCH_IS_64
136 config BR2_MIPS_SOFT_FLOAT
137 bool "Use soft-float"
139 select BR2_SOFT_FLOAT
141 If your target CPU does not have a Floating Point Unit (FPU)
142 or a kernel FPU emulator, but you still wish to support
143 floating point functions, then everything will need to be
144 compiled with soft floating point support (-msoft-float).
148 depends on !BR2_ARCH_IS_64 && !BR2_MIPS_SOFT_FLOAT
149 default BR2_MIPS_FP32_MODE_XX
151 MIPS32 supports different FP modes (32,xx,64). Information about FP
152 modes can be found here:
153 https://sourceware.org/binutils/docs/as/MIPS-Options.html
154 https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code
156 config BR2_MIPS_FP32_MODE_32
158 depends on !BR2_MIPS_CPU_MIPS32R6
160 config BR2_MIPS_FP32_MODE_XX
162 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
164 config BR2_MIPS_FP32_MODE_64
166 depends on !BR2_MIPS_CPU_MIPS32
169 config BR2_GCC_TARGET_FP32_MODE
170 default "32" if BR2_MIPS_FP32_MODE_32
171 default "xx" if BR2_MIPS_FP32_MODE_XX
172 default "64" if BR2_MIPS_FP32_MODE_64
174 config BR2_MIPS_NAN_LEGACY
177 config BR2_MIPS_NAN_2008
179 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9
183 depends on BR2_mips_32r5 || BR2_mips_64r5
184 default BR2_MIPS_ENABLE_NAN_2008
186 MIPS supports two different NaN encodings, legacy and 2008.
187 Information about MIPS NaN encodings can be found here:
188 https://sourceware.org/binutils/docs/as/MIPS-NaN-Encodings.html
190 config BR2_MIPS_ENABLE_NAN_LEGACY
192 select BR2_MIPS_NAN_LEGACY
194 config BR2_MIPS_ENABLE_NAN_2008
196 depends on !BR2_MIPS_SOFT_FLOAT
197 select BR2_MIPS_NAN_2008
200 config BR2_GCC_TARGET_NAN
201 default "legacy" if BR2_MIPS_NAN_LEGACY
202 default "2008" if BR2_MIPS_NAN_2008
205 default "mips" if BR2_mips
206 default "mipsel" if BR2_mipsel
207 default "mips64" if BR2_mips64
208 default "mips64el" if BR2_mips64el
211 default "LITTLE" if BR2_mipsel || BR2_mips64el
212 default "BIG" if BR2_mips || BR2_mips64
214 config BR2_GCC_TARGET_ARCH
215 default "mips32" if BR2_mips_32
216 default "mips32r2" if BR2_mips_32r2
217 default "mips32r5" if BR2_mips_32r5
218 default "mips32r6" if BR2_mips_32r6
219 default "interaptiv" if BR2_mips_interaptiv
220 default "m5101" if BR2_mips_m5150
221 default "m6201" if BR2_mips_m6250
222 default "p5600" if BR2_mips_p5600
223 default "mips32r2" if BR2_mips_xburst
224 default "mips64" if BR2_mips_64
225 default "mips64r2" if BR2_mips_64r2
226 default "mips64r5" if BR2_mips_64r5
227 default "mips64r6" if BR2_mips_64r6
228 default "i6400" if BR2_mips_i6400
229 default "p6600" if BR2_mips_p6600
231 config BR2_MIPS_OABI32
233 default y if BR2_mips || BR2_mipsel
235 config BR2_GCC_TARGET_ABI
236 default "32" if BR2_MIPS_OABI32
237 default "n32" if BR2_MIPS_NABI32
238 default "64" if BR2_MIPS_NABI64
240 config BR2_READELF_ARCH_NAME