]> rtime.felk.cvut.cz Git - can-eth-gw-linux.git/commitdiff
PCI/portdrv: Use PCI Express Capability accessors
authorJiang Liu <jiang.liu@huawei.com>
Tue, 24 Jul 2012 09:20:08 +0000 (17:20 +0800)
committerBjorn Helgaas <bhelgaas@google.com>
Thu, 23 Aug 2012 16:11:11 +0000 (10:11 -0600)
Use PCI Express Capability access functions to simplify portdrv.

Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
drivers/pci/pcie/portdrv_core.c
drivers/pci/pcie/portdrv_pci.c

index bf320a9419f45df3d3734189d21206436c24e156..aede99171e901eae4399e3db152e2bf5f8c58aee 100644 (file)
@@ -246,8 +246,7 @@ static void cleanup_service_irqs(struct pci_dev *dev)
  */
 static int get_port_device_capability(struct pci_dev *dev)
 {
-       int services = 0, pos;
-       u16 reg16;
+       int services = 0;
        u32 reg32;
        int cap_mask = 0;
        int err;
@@ -265,11 +264,9 @@ static int get_port_device_capability(struct pci_dev *dev)
                        return 0;
        }
 
-       pos = pci_pcie_cap(dev);
-       pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &reg16);
        /* Hot-Plug Capable */
-       if ((cap_mask & PCIE_PORT_SERVICE_HP) && (reg16 & PCI_EXP_FLAGS_SLOT)) {
-               pci_read_config_dword(dev, pos + PCI_EXP_SLTCAP, &reg32);
+       if (cap_mask & PCIE_PORT_SERVICE_HP) {
+               pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, &reg32);
                if (reg32 & PCI_EXP_SLTCAP_HPC) {
                        services |= PCIE_PORT_SERVICE_HP;
                        /*
@@ -277,10 +274,8 @@ static int get_port_device_capability(struct pci_dev *dev)
                         * enabled by the BIOS and the hot-plug service driver
                         * is not loaded.
                         */
-                       pos += PCI_EXP_SLTCTL;
-                       pci_read_config_word(dev, pos, &reg16);
-                       reg16 &= ~(PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
-                       pci_write_config_word(dev, pos, reg16);
+                       pcie_capability_clear_word(dev, PCI_EXP_SLTCTL,
+                               PCI_EXP_SLTCTL_CCIE | PCI_EXP_SLTCTL_HPIE);
                }
        }
        /* AER capable */
index 24d1463e688b5ff7798fd45722d5588d92d0fe77..2360330e48f1a6b8f00d68f1dd4a6735f4db582d 100644 (file)
@@ -64,14 +64,7 @@ __setup("pcie_ports=", pcie_port_setup);
  */
 void pcie_clear_root_pme_status(struct pci_dev *dev)
 {
-       int rtsta_pos;
-       u32 rtsta;
-
-       rtsta_pos = pci_pcie_cap(dev) + PCI_EXP_RTSTA;
-
-       pci_read_config_dword(dev, rtsta_pos, &rtsta);
-       rtsta |= PCI_EXP_RTSTA_PME;
-       pci_write_config_dword(dev, rtsta_pos, rtsta);
+       pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
 }
 
 static int pcie_portdrv_restore_config(struct pci_dev *dev)