1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
32 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
33 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
34 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
35 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
36 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
37 u16 *data, bool read, bool page_set);
38 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
39 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
40 u16 *data, bool read);
42 /* Cable length tables */
43 static const u16 e1000_m88_cable_length_table[] = {
44 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
45 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
46 ARRAY_SIZE(e1000_m88_cable_length_table)
48 static const u16 e1000_igp_2_cable_length_table[] = {
49 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
60 #define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62 #define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
67 #define HV_INTC_FC_PAGE_START 768
68 #define I82578_ADDR_REG 29
69 #define I82577_ADDR_REG 16
70 #define I82577_CFG_REG 22
71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73 #define I82577_CTRL_REG 23
75 /* 82577 specific PHY registers */
76 #define I82577_PHY_CTRL_2 18
77 #define I82577_PHY_STATUS_2 26
78 #define I82577_PHY_DIAG_STATUS 31
80 /* I82577 PHY Status 2 */
81 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
82 #define I82577_PHY_STATUS2_MDIX 0x0800
83 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
84 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
86 /* I82577 PHY Control 2 */
87 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
88 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
89 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
91 /* I82577 PHY Diagnostics Status */
92 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
93 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
95 /* BM PHY Copper Specific Control 1 */
96 #define BM_CS_CTRL1 16
98 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
99 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
100 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
103 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
104 * @hw: pointer to the HW structure
106 * Read the PHY management control register and check whether a PHY reset
107 * is blocked. If a reset is not blocked return 0, otherwise
108 * return E1000_BLK_PHY_RESET (12).
110 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
116 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
117 E1000_BLK_PHY_RESET : 0;
121 * e1000e_get_phy_id - Retrieve the PHY ID and revision
122 * @hw: pointer to the HW structure
124 * Reads the PHY registers and stores the PHY ID and possibly the PHY
125 * revision in the hardware structure.
127 s32 e1000e_get_phy_id(struct e1000_hw *hw)
129 struct e1000_phy_info *phy = &hw->phy;
134 if (!phy->ops.read_reg)
137 while (retry_count < 2) {
138 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
142 phy->id = (u32)(phy_id << 16);
144 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
148 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
149 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
151 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
161 * e1000e_phy_reset_dsp - Reset PHY DSP
162 * @hw: pointer to the HW structure
164 * Reset the digital signal processor.
166 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
170 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
174 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
178 * e1000e_read_phy_reg_mdic - Read MDI control register
179 * @hw: pointer to the HW structure
180 * @offset: register offset to be read
181 * @data: pointer to the read data
183 * Reads the MDI control register in the PHY at offset and stores the
184 * information read to data.
186 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
188 struct e1000_phy_info *phy = &hw->phy;
191 if (offset > MAX_PHY_REG_ADDRESS) {
192 e_dbg("PHY Address %d is out of range\n", offset);
193 return -E1000_ERR_PARAM;
196 /* Set up Op-code, Phy Address, and register offset in the MDI
197 * Control register. The MAC will take care of interfacing with the
198 * PHY to retrieve the desired data.
200 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
201 (phy->addr << E1000_MDIC_PHY_SHIFT) |
202 (E1000_MDIC_OP_READ));
206 /* Poll the ready bit to see if the MDI read completed
207 * Increasing the time out as testing showed failures with
210 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
213 if (mdic & E1000_MDIC_READY)
216 if (!(mdic & E1000_MDIC_READY)) {
217 e_dbg("MDI Read did not complete\n");
218 return -E1000_ERR_PHY;
220 if (mdic & E1000_MDIC_ERROR) {
221 e_dbg("MDI Error\n");
222 return -E1000_ERR_PHY;
226 /* Allow some time after each MDIC transaction to avoid
227 * reading duplicate data in the next MDIC transaction.
229 if (hw->mac.type == e1000_pch2lan)
236 * e1000e_write_phy_reg_mdic - Write MDI control register
237 * @hw: pointer to the HW structure
238 * @offset: register offset to write to
239 * @data: data to write to register at offset
241 * Writes data to MDI control register in the PHY at offset.
243 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
245 struct e1000_phy_info *phy = &hw->phy;
248 if (offset > MAX_PHY_REG_ADDRESS) {
249 e_dbg("PHY Address %d is out of range\n", offset);
250 return -E1000_ERR_PARAM;
253 /* Set up Op-code, Phy Address, and register offset in the MDI
254 * Control register. The MAC will take care of interfacing with the
255 * PHY to retrieve the desired data.
257 mdic = (((u32)data) |
258 (offset << E1000_MDIC_REG_SHIFT) |
259 (phy->addr << E1000_MDIC_PHY_SHIFT) |
260 (E1000_MDIC_OP_WRITE));
264 /* Poll the ready bit to see if the MDI read completed
265 * Increasing the time out as testing showed failures with
268 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
271 if (mdic & E1000_MDIC_READY)
274 if (!(mdic & E1000_MDIC_READY)) {
275 e_dbg("MDI Write did not complete\n");
276 return -E1000_ERR_PHY;
278 if (mdic & E1000_MDIC_ERROR) {
279 e_dbg("MDI Error\n");
280 return -E1000_ERR_PHY;
283 /* Allow some time after each MDIC transaction to avoid
284 * reading duplicate data in the next MDIC transaction.
286 if (hw->mac.type == e1000_pch2lan)
293 * e1000e_read_phy_reg_m88 - Read m88 PHY register
294 * @hw: pointer to the HW structure
295 * @offset: register offset to be read
296 * @data: pointer to the read data
298 * Acquires semaphore, if necessary, then reads the PHY register at offset
299 * and storing the retrieved information in data. Release any acquired
300 * semaphores before exiting.
302 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
306 ret_val = hw->phy.ops.acquire(hw);
310 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
313 hw->phy.ops.release(hw);
319 * e1000e_write_phy_reg_m88 - Write m88 PHY register
320 * @hw: pointer to the HW structure
321 * @offset: register offset to write to
322 * @data: data to write at register offset
324 * Acquires semaphore, if necessary, then writes the data to PHY register
325 * at the offset. Release any acquired semaphores before exiting.
327 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
331 ret_val = hw->phy.ops.acquire(hw);
335 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
338 hw->phy.ops.release(hw);
344 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
345 * @hw: pointer to the HW structure
346 * @page: page to set (shifted left when necessary)
348 * Sets PHY page required for PHY register access. Assumes semaphore is
349 * already acquired. Note, this function sets phy.addr to 1 so the caller
350 * must set it appropriately (if necessary) after this function returns.
352 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
354 e_dbg("Setting page 0x%x\n", page);
358 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
362 * __e1000e_read_phy_reg_igp - Read igp PHY register
363 * @hw: pointer to the HW structure
364 * @offset: register offset to be read
365 * @data: pointer to the read data
366 * @locked: semaphore has already been acquired or not
368 * Acquires semaphore, if necessary, then reads the PHY register at offset
369 * and stores the retrieved information in data. Release any acquired
370 * semaphores before exiting.
372 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
378 if (!hw->phy.ops.acquire)
381 ret_val = hw->phy.ops.acquire(hw);
386 if (offset > MAX_PHY_MULTI_PAGE_REG)
387 ret_val = e1000e_write_phy_reg_mdic(hw,
388 IGP01E1000_PHY_PAGE_SELECT,
391 ret_val = e1000e_read_phy_reg_mdic(hw,
392 MAX_PHY_REG_ADDRESS & offset,
395 hw->phy.ops.release(hw);
401 * e1000e_read_phy_reg_igp - Read igp PHY register
402 * @hw: pointer to the HW structure
403 * @offset: register offset to be read
404 * @data: pointer to the read data
406 * Acquires semaphore then reads the PHY register at offset and stores the
407 * retrieved information in data.
408 * Release the acquired semaphore before exiting.
410 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
412 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
416 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
417 * @hw: pointer to the HW structure
418 * @offset: register offset to be read
419 * @data: pointer to the read data
421 * Reads the PHY register at offset and stores the retrieved information
422 * in data. Assumes semaphore already acquired.
424 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
426 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
430 * e1000e_write_phy_reg_igp - Write igp PHY register
431 * @hw: pointer to the HW structure
432 * @offset: register offset to write to
433 * @data: data to write at register offset
434 * @locked: semaphore has already been acquired or not
436 * Acquires semaphore, if necessary, then writes the data to PHY register
437 * at the offset. Release any acquired semaphores before exiting.
439 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
445 if (!hw->phy.ops.acquire)
448 ret_val = hw->phy.ops.acquire(hw);
453 if (offset > MAX_PHY_MULTI_PAGE_REG)
454 ret_val = e1000e_write_phy_reg_mdic(hw,
455 IGP01E1000_PHY_PAGE_SELECT,
458 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
462 hw->phy.ops.release(hw);
468 * e1000e_write_phy_reg_igp - Write igp PHY register
469 * @hw: pointer to the HW structure
470 * @offset: register offset to write to
471 * @data: data to write at register offset
473 * Acquires semaphore then writes the data to PHY register
474 * at the offset. Release any acquired semaphores before exiting.
476 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
478 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
482 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
483 * @hw: pointer to the HW structure
484 * @offset: register offset to write to
485 * @data: data to write at register offset
487 * Writes the data to PHY register at the offset.
488 * Assumes semaphore already acquired.
490 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
492 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
496 * __e1000_read_kmrn_reg - Read kumeran register
497 * @hw: pointer to the HW structure
498 * @offset: register offset to be read
499 * @data: pointer to the read data
500 * @locked: semaphore has already been acquired or not
502 * Acquires semaphore, if necessary. Then reads the PHY register at offset
503 * using the kumeran interface. The information retrieved is stored in data.
504 * Release any acquired semaphores before exiting.
506 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
514 if (!hw->phy.ops.acquire)
517 ret_val = hw->phy.ops.acquire(hw);
522 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
523 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
524 ew32(KMRNCTRLSTA, kmrnctrlsta);
529 kmrnctrlsta = er32(KMRNCTRLSTA);
530 *data = (u16)kmrnctrlsta;
533 hw->phy.ops.release(hw);
539 * e1000e_read_kmrn_reg - Read kumeran register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be read
542 * @data: pointer to the read data
544 * Acquires semaphore then reads the PHY register at offset using the
545 * kumeran interface. The information retrieved is stored in data.
546 * Release the acquired semaphore before exiting.
548 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
550 return __e1000_read_kmrn_reg(hw, offset, data, false);
554 * e1000e_read_kmrn_reg_locked - Read kumeran register
555 * @hw: pointer to the HW structure
556 * @offset: register offset to be read
557 * @data: pointer to the read data
559 * Reads the PHY register at offset using the kumeran interface. The
560 * information retrieved is stored in data.
561 * Assumes semaphore already acquired.
563 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
565 return __e1000_read_kmrn_reg(hw, offset, data, true);
569 * __e1000_write_kmrn_reg - Write kumeran register
570 * @hw: pointer to the HW structure
571 * @offset: register offset to write to
572 * @data: data to write at register offset
573 * @locked: semaphore has already been acquired or not
575 * Acquires semaphore, if necessary. Then write the data to PHY register
576 * at the offset using the kumeran interface. Release any acquired semaphores
579 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
587 if (!hw->phy.ops.acquire)
590 ret_val = hw->phy.ops.acquire(hw);
595 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
596 E1000_KMRNCTRLSTA_OFFSET) | data;
597 ew32(KMRNCTRLSTA, kmrnctrlsta);
603 hw->phy.ops.release(hw);
609 * e1000e_write_kmrn_reg - Write kumeran register
610 * @hw: pointer to the HW structure
611 * @offset: register offset to write to
612 * @data: data to write at register offset
614 * Acquires semaphore then writes the data to the PHY register at the offset
615 * using the kumeran interface. Release the acquired semaphore before exiting.
617 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
619 return __e1000_write_kmrn_reg(hw, offset, data, false);
623 * e1000e_write_kmrn_reg_locked - Write kumeran register
624 * @hw: pointer to the HW structure
625 * @offset: register offset to write to
626 * @data: data to write at register offset
628 * Write the data to PHY register at the offset using the kumeran interface.
629 * Assumes semaphore already acquired.
631 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
633 return __e1000_write_kmrn_reg(hw, offset, data, true);
637 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
638 * @hw: pointer to the HW structure
640 * Sets up Master/slave mode
642 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
647 /* Resolve Master/Slave mode */
648 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &phy_data);
652 /* load defaults for future use */
653 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
654 ((phy_data & CR_1000T_MS_VALUE) ?
655 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
657 switch (hw->phy.ms_type) {
658 case e1000_ms_force_master:
659 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
661 case e1000_ms_force_slave:
662 phy_data |= CR_1000T_MS_ENABLE;
663 phy_data &= ~(CR_1000T_MS_VALUE);
666 phy_data &= ~CR_1000T_MS_ENABLE;
672 return e1e_wphy(hw, PHY_1000T_CTRL, phy_data);
676 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
677 * @hw: pointer to the HW structure
679 * Sets up Carrier-sense on Transmit and downshift values.
681 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
686 /* Enable CRS on Tx. This must be set for half-duplex operation. */
687 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
691 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
693 /* Enable downshift */
694 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
696 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
700 /* Set MDI/MDIX mode */
701 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
704 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
710 switch (hw->phy.mdix) {
714 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
718 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
721 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
725 return e1000_set_master_slave_mode(hw);
729 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
730 * @hw: pointer to the HW structure
732 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
733 * and downshift values are set also.
735 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
737 struct e1000_phy_info *phy = &hw->phy;
741 /* Enable CRS on Tx. This must be set for half-duplex operation. */
742 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
746 /* For BM PHY this bit is downshift enable */
747 if (phy->type != e1000_phy_bm)
748 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
751 * MDI/MDI-X = 0 (default)
752 * 0 - Auto for all speeds
755 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
757 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
761 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
764 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
767 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
771 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
776 * disable_polarity_correction = 0 (default)
777 * Automatic Correction for Reversed Cable Polarity
781 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
782 if (phy->disable_polarity_correction)
783 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
785 /* Enable downshift on BM (disabled by default) */
786 if (phy->type == e1000_phy_bm) {
787 /* For 82574/82583, first disable then enable downshift */
788 if (phy->id == BME1000_E_PHY_ID_R2) {
789 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
790 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
794 /* Commit the changes. */
795 ret_val = e1000e_commit_phy(hw);
797 e_dbg("Error committing the PHY changes\n");
802 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
805 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
809 if ((phy->type == e1000_phy_m88) &&
810 (phy->revision < E1000_REVISION_4) &&
811 (phy->id != BME1000_E_PHY_ID_R2)) {
812 /* Force TX_CLK in the Extended PHY Specific Control Register
815 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
819 phy_data |= M88E1000_EPSCR_TX_CLK_25;
821 if ((phy->revision == 2) &&
822 (phy->id == M88E1111_I_PHY_ID)) {
823 /* 82573L PHY - set the downshift counter to 5x. */
824 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
825 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
827 /* Configure Master and Slave downshift values */
828 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
829 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
830 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
831 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
833 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
838 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
839 /* Set PHY page 0, register 29 to 0x0003 */
840 ret_val = e1e_wphy(hw, 29, 0x0003);
844 /* Set PHY page 0, register 30 to 0x0000 */
845 ret_val = e1e_wphy(hw, 30, 0x0000);
850 /* Commit the changes. */
851 ret_val = e1000e_commit_phy(hw);
853 e_dbg("Error committing the PHY changes\n");
857 if (phy->type == e1000_phy_82578) {
858 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
862 /* 82578 PHY - set the downshift count to 1x. */
863 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
864 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
865 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
874 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
875 * @hw: pointer to the HW structure
877 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
880 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
882 struct e1000_phy_info *phy = &hw->phy;
886 ret_val = e1000_phy_hw_reset(hw);
888 e_dbg("Error resetting the PHY.\n");
892 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
893 * timeout issues when LFS is enabled.
897 /* disable lplu d0 during driver init */
898 ret_val = e1000_set_d0_lplu_state(hw, false);
900 e_dbg("Error Disabling LPLU D0\n");
903 /* Configure mdi-mdix settings */
904 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
908 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
912 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
915 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
919 data |= IGP01E1000_PSCR_AUTO_MDIX;
922 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
926 /* set auto-master slave resolution settings */
927 if (hw->mac.autoneg) {
928 /* when autonegotiation advertisement is only 1000Mbps then we
929 * should disable SmartSpeed and enable Auto MasterSlave
930 * resolution as hardware default.
932 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
933 /* Disable SmartSpeed */
934 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
939 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
940 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
945 /* Set auto Master/Slave resolution process */
946 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
950 data &= ~CR_1000T_MS_ENABLE;
951 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
956 ret_val = e1000_set_master_slave_mode(hw);
963 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
964 * @hw: pointer to the HW structure
966 * Reads the MII auto-neg advertisement register and/or the 1000T control
967 * register and if the PHY is already setup for auto-negotiation, then
968 * return successful. Otherwise, setup advertisement and flow control to
969 * the appropriate values for the wanted auto-negotiation.
971 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
973 struct e1000_phy_info *phy = &hw->phy;
975 u16 mii_autoneg_adv_reg;
976 u16 mii_1000t_ctrl_reg = 0;
978 phy->autoneg_advertised &= phy->autoneg_mask;
980 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
981 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
985 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
986 /* Read the MII 1000Base-T Control Register (Address 9). */
987 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
992 /* Need to parse both autoneg_advertised and fc and set up
993 * the appropriate PHY registers. First we will parse for
994 * autoneg_advertised software override. Since we can advertise
995 * a plethora of combinations, we need to check each bit
999 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1000 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1001 * the 1000Base-T Control Register (Address 9).
1003 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1004 NWAY_AR_100TX_HD_CAPS |
1005 NWAY_AR_10T_FD_CAPS |
1006 NWAY_AR_10T_HD_CAPS);
1007 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1009 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
1011 /* Do we want to advertise 10 Mb Half Duplex? */
1012 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1013 e_dbg("Advertise 10mb Half duplex\n");
1014 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1017 /* Do we want to advertise 10 Mb Full Duplex? */
1018 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1019 e_dbg("Advertise 10mb Full duplex\n");
1020 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1023 /* Do we want to advertise 100 Mb Half Duplex? */
1024 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1025 e_dbg("Advertise 100mb Half duplex\n");
1026 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1029 /* Do we want to advertise 100 Mb Full Duplex? */
1030 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1031 e_dbg("Advertise 100mb Full duplex\n");
1032 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1035 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1036 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1037 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1039 /* Do we want to advertise 1000 Mb Full Duplex? */
1040 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1041 e_dbg("Advertise 1000mb Full duplex\n");
1042 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1045 /* Check for a software override of the flow control settings, and
1046 * setup the PHY advertisement registers accordingly. If
1047 * auto-negotiation is enabled, then software will have to set the
1048 * "PAUSE" bits to the correct value in the Auto-Negotiation
1049 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1052 * The possible values of the "fc" parameter are:
1053 * 0: Flow control is completely disabled
1054 * 1: Rx flow control is enabled (we can receive pause frames
1055 * but not send pause frames).
1056 * 2: Tx flow control is enabled (we can send pause frames
1057 * but we do not support receiving pause frames).
1058 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1059 * other: No software override. The flow control configuration
1060 * in the EEPROM is used.
1062 switch (hw->fc.current_mode) {
1064 /* Flow control (Rx & Tx) is completely disabled by a
1065 * software over-ride.
1067 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1069 case e1000_fc_rx_pause:
1070 /* Rx Flow control is enabled, and Tx Flow control is
1071 * disabled, by a software over-ride.
1073 * Since there really isn't a way to advertise that we are
1074 * capable of Rx Pause ONLY, we will advertise that we
1075 * support both symmetric and asymmetric Rx PAUSE. Later
1076 * (in e1000e_config_fc_after_link_up) we will disable the
1077 * hw's ability to send PAUSE frames.
1079 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1081 case e1000_fc_tx_pause:
1082 /* Tx Flow control is enabled, and Rx Flow control is
1083 * disabled, by a software over-ride.
1085 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1086 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1089 /* Flow control (both Rx and Tx) is enabled by a software
1092 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1095 e_dbg("Flow control param set incorrectly\n");
1096 return -E1000_ERR_CONFIG;
1099 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1103 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1105 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1106 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1112 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1113 * @hw: pointer to the HW structure
1115 * Performs initial bounds checking on autoneg advertisement parameter, then
1116 * configure to advertise the full capability. Setup the PHY to autoneg
1117 * and restart the negotiation process between the link partner. If
1118 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1120 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1122 struct e1000_phy_info *phy = &hw->phy;
1126 /* Perform some bounds checking on the autoneg advertisement
1129 phy->autoneg_advertised &= phy->autoneg_mask;
1131 /* If autoneg_advertised is zero, we assume it was not defaulted
1132 * by the calling code so we set to advertise full capability.
1134 if (!phy->autoneg_advertised)
1135 phy->autoneg_advertised = phy->autoneg_mask;
1137 e_dbg("Reconfiguring auto-neg advertisement params\n");
1138 ret_val = e1000_phy_setup_autoneg(hw);
1140 e_dbg("Error Setting up Auto-Negotiation\n");
1143 e_dbg("Restarting Auto-Neg\n");
1145 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1146 * the Auto Neg Restart bit in the PHY control register.
1148 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1152 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1153 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1157 /* Does the user want to wait for Auto-Neg to complete here, or
1158 * check at a later time (for example, callback routine).
1160 if (phy->autoneg_wait_to_complete) {
1161 ret_val = e1000_wait_autoneg(hw);
1163 e_dbg("Error while waiting for autoneg to complete\n");
1168 hw->mac.get_link_status = true;
1174 * e1000e_setup_copper_link - Configure copper link settings
1175 * @hw: pointer to the HW structure
1177 * Calls the appropriate function to configure the link for auto-neg or forced
1178 * speed and duplex. Then we check for link, once link is established calls
1179 * to configure collision distance and flow control are called. If link is
1180 * not established, we return -E1000_ERR_PHY (-2).
1182 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1187 if (hw->mac.autoneg) {
1188 /* Setup autoneg and flow control advertisement and perform
1191 ret_val = e1000_copper_link_autoneg(hw);
1195 /* PHY will be set to 10H, 10F, 100H or 100F
1196 * depending on user settings.
1198 e_dbg("Forcing Speed and Duplex\n");
1199 ret_val = e1000_phy_force_speed_duplex(hw);
1201 e_dbg("Error Forcing Speed and Duplex\n");
1206 /* Check link status. Wait up to 100 microseconds for link to become
1209 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1215 e_dbg("Valid link established!!!\n");
1216 hw->mac.ops.config_collision_dist(hw);
1217 ret_val = e1000e_config_fc_after_link_up(hw);
1219 e_dbg("Unable to establish link!!!\n");
1226 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1227 * @hw: pointer to the HW structure
1229 * Calls the PHY setup function to force speed and duplex. Clears the
1230 * auto-crossover to force MDI manually. Waits for link and returns
1231 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1233 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1235 struct e1000_phy_info *phy = &hw->phy;
1240 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1244 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1246 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1250 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1251 * forced whenever speed and duplex are forced.
1253 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1257 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1258 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1260 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1264 e_dbg("IGP PSCR: %X\n", phy_data);
1268 if (phy->autoneg_wait_to_complete) {
1269 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1271 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1277 e_dbg("Link taking longer than expected.\n");
1280 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1288 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1289 * @hw: pointer to the HW structure
1291 * Calls the PHY setup function to force speed and duplex. Clears the
1292 * auto-crossover to force MDI manually. Resets the PHY to commit the
1293 * changes. If time expires while waiting for link up, we reset the DSP.
1294 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1295 * successful completion, else return corresponding error code.
1297 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1299 struct e1000_phy_info *phy = &hw->phy;
1304 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1305 * forced whenever speed and duplex are forced.
1307 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1311 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1312 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1316 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1318 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1322 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1324 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1328 /* Reset the phy to commit changes. */
1329 ret_val = e1000e_commit_phy(hw);
1333 if (phy->autoneg_wait_to_complete) {
1334 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1336 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1342 if (hw->phy.type != e1000_phy_m88) {
1343 e_dbg("Link taking longer than expected.\n");
1345 /* We didn't get link.
1346 * Reset the DSP and cross our fingers.
1348 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1352 ret_val = e1000e_phy_reset_dsp(hw);
1359 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1365 if (hw->phy.type != e1000_phy_m88)
1368 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1372 /* Resetting the phy means we need to re-force TX_CLK in the
1373 * Extended PHY Specific Control Register to 25MHz clock from
1374 * the reset value of 2.5MHz.
1376 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1377 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1381 /* In addition, we must re-enable CRS on Tx for both half and full
1384 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1388 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1389 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1395 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1396 * @hw: pointer to the HW structure
1398 * Forces the speed and duplex settings of the PHY.
1399 * This is a function pointer entry point only called by
1400 * PHY setup routines.
1402 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1404 struct e1000_phy_info *phy = &hw->phy;
1409 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1413 e1000e_phy_force_speed_duplex_setup(hw, &data);
1415 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1419 /* Disable MDI-X support for 10/100 */
1420 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1424 data &= ~IFE_PMC_AUTO_MDIX;
1425 data &= ~IFE_PMC_FORCE_MDIX;
1427 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1431 e_dbg("IFE PMC: %X\n", data);
1435 if (phy->autoneg_wait_to_complete) {
1436 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1438 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1444 e_dbg("Link taking longer than expected.\n");
1447 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1457 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1458 * @hw: pointer to the HW structure
1459 * @phy_ctrl: pointer to current value of PHY_CONTROL
1461 * Forces speed and duplex on the PHY by doing the following: disable flow
1462 * control, force speed/duplex on the MAC, disable auto speed detection,
1463 * disable auto-negotiation, configure duplex, configure speed, configure
1464 * the collision distance, write configuration to CTRL register. The
1465 * caller must write to the PHY_CONTROL register for these settings to
1468 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1470 struct e1000_mac_info *mac = &hw->mac;
1473 /* Turn off flow control when forcing speed/duplex */
1474 hw->fc.current_mode = e1000_fc_none;
1476 /* Force speed/duplex on the mac */
1478 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1479 ctrl &= ~E1000_CTRL_SPD_SEL;
1481 /* Disable Auto Speed Detection */
1482 ctrl &= ~E1000_CTRL_ASDE;
1484 /* Disable autoneg on the phy */
1485 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1487 /* Forcing Full or Half Duplex? */
1488 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1489 ctrl &= ~E1000_CTRL_FD;
1490 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1491 e_dbg("Half Duplex\n");
1493 ctrl |= E1000_CTRL_FD;
1494 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1495 e_dbg("Full Duplex\n");
1498 /* Forcing 10mb or 100mb? */
1499 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1500 ctrl |= E1000_CTRL_SPD_100;
1501 *phy_ctrl |= MII_CR_SPEED_100;
1502 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1503 e_dbg("Forcing 100mb\n");
1505 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1506 *phy_ctrl |= MII_CR_SPEED_10;
1507 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1508 e_dbg("Forcing 10mb\n");
1511 hw->mac.ops.config_collision_dist(hw);
1517 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1518 * @hw: pointer to the HW structure
1519 * @active: boolean used to enable/disable lplu
1521 * Success returns 0, Failure returns 1
1523 * The low power link up (lplu) state is set to the power management level D3
1524 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1525 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1526 * is used during Dx states where the power conservation is most important.
1527 * During driver activity, SmartSpeed should be enabled so performance is
1530 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1532 struct e1000_phy_info *phy = &hw->phy;
1536 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1541 data &= ~IGP02E1000_PM_D3_LPLU;
1542 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1545 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1546 * during Dx states where the power conservation is most
1547 * important. During driver activity we should enable
1548 * SmartSpeed, so performance is maintained.
1550 if (phy->smart_speed == e1000_smart_speed_on) {
1551 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1556 data |= IGP01E1000_PSCFR_SMART_SPEED;
1557 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1561 } else if (phy->smart_speed == e1000_smart_speed_off) {
1562 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1567 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1568 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1573 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1574 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1575 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1576 data |= IGP02E1000_PM_D3_LPLU;
1577 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1581 /* When LPLU is enabled, we should disable SmartSpeed */
1582 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1586 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1587 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1594 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1595 * @hw: pointer to the HW structure
1597 * Success returns 0, Failure returns 1
1599 * A downshift is detected by querying the PHY link health.
1601 s32 e1000e_check_downshift(struct e1000_hw *hw)
1603 struct e1000_phy_info *phy = &hw->phy;
1605 u16 phy_data, offset, mask;
1607 switch (phy->type) {
1609 case e1000_phy_gg82563:
1611 case e1000_phy_82578:
1612 offset = M88E1000_PHY_SPEC_STATUS;
1613 mask = M88E1000_PSSR_DOWNSHIFT;
1615 case e1000_phy_igp_2:
1616 case e1000_phy_igp_3:
1617 offset = IGP01E1000_PHY_LINK_HEALTH;
1618 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1621 /* speed downshift not supported */
1622 phy->speed_downgraded = false;
1626 ret_val = e1e_rphy(hw, offset, &phy_data);
1629 phy->speed_downgraded = !!(phy_data & mask);
1635 * e1000_check_polarity_m88 - Checks the polarity.
1636 * @hw: pointer to the HW structure
1638 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1640 * Polarity is determined based on the PHY specific status register.
1642 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1644 struct e1000_phy_info *phy = &hw->phy;
1648 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1651 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1652 ? e1000_rev_polarity_reversed
1653 : e1000_rev_polarity_normal;
1659 * e1000_check_polarity_igp - Checks the polarity.
1660 * @hw: pointer to the HW structure
1662 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1664 * Polarity is determined based on the PHY port status register, and the
1665 * current speed (since there is no polarity at 100Mbps).
1667 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1669 struct e1000_phy_info *phy = &hw->phy;
1671 u16 data, offset, mask;
1673 /* Polarity is determined based on the speed of
1676 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1680 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1681 IGP01E1000_PSSR_SPEED_1000MBPS) {
1682 offset = IGP01E1000_PHY_PCS_INIT_REG;
1683 mask = IGP01E1000_PHY_POLARITY_MASK;
1685 /* This really only applies to 10Mbps since
1686 * there is no polarity for 100Mbps (always 0).
1688 offset = IGP01E1000_PHY_PORT_STATUS;
1689 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1692 ret_val = e1e_rphy(hw, offset, &data);
1695 phy->cable_polarity = (data & mask)
1696 ? e1000_rev_polarity_reversed
1697 : e1000_rev_polarity_normal;
1703 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1704 * @hw: pointer to the HW structure
1706 * Polarity is determined on the polarity reversal feature being enabled.
1708 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1710 struct e1000_phy_info *phy = &hw->phy;
1712 u16 phy_data, offset, mask;
1714 /* Polarity is determined based on the reversal feature being enabled.
1716 if (phy->polarity_correction) {
1717 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1718 mask = IFE_PESC_POLARITY_REVERSED;
1720 offset = IFE_PHY_SPECIAL_CONTROL;
1721 mask = IFE_PSC_FORCE_POLARITY;
1724 ret_val = e1e_rphy(hw, offset, &phy_data);
1727 phy->cable_polarity = (phy_data & mask)
1728 ? e1000_rev_polarity_reversed
1729 : e1000_rev_polarity_normal;
1735 * e1000_wait_autoneg - Wait for auto-neg completion
1736 * @hw: pointer to the HW structure
1738 * Waits for auto-negotiation to complete or for the auto-negotiation time
1739 * limit to expire, which ever happens first.
1741 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1746 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1747 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1748 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1751 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1754 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1759 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1766 * e1000e_phy_has_link_generic - Polls PHY for link
1767 * @hw: pointer to the HW structure
1768 * @iterations: number of times to poll for link
1769 * @usec_interval: delay between polling attempts
1770 * @success: pointer to whether polling was successful or not
1772 * Polls the PHY status register for link, 'iterations' number of times.
1774 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1775 u32 usec_interval, bool *success)
1780 for (i = 0; i < iterations; i++) {
1781 /* Some PHYs require the PHY_STATUS register to be read
1782 * twice due to the link bit being sticky. No harm doing
1783 * it across the board.
1785 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1787 /* If the first read fails, another entity may have
1788 * ownership of the resources, wait and try again to
1789 * see if they have relinquished the resources yet.
1791 udelay(usec_interval);
1792 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1795 if (phy_status & MII_SR_LINK_STATUS)
1797 if (usec_interval >= 1000)
1798 mdelay(usec_interval/1000);
1800 udelay(usec_interval);
1803 *success = (i < iterations);
1809 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1810 * @hw: pointer to the HW structure
1812 * Reads the PHY specific status register to retrieve the cable length
1813 * information. The cable length is determined by averaging the minimum and
1814 * maximum values to get the "average" cable length. The m88 PHY has four
1815 * possible cable length values, which are:
1816 * Register Value Cable Length
1820 * 3 110 - 140 meters
1823 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1825 struct e1000_phy_info *phy = &hw->phy;
1827 u16 phy_data, index;
1829 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1833 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1834 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1836 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1837 return -E1000_ERR_PHY;
1839 phy->min_cable_length = e1000_m88_cable_length_table[index];
1840 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1842 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1848 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1849 * @hw: pointer to the HW structure
1851 * The automatic gain control (agc) normalizes the amplitude of the
1852 * received signal, adjusting for the attenuation produced by the
1853 * cable. By reading the AGC registers, which represent the
1854 * combination of coarse and fine gain value, the value can be put
1855 * into a lookup table to obtain the approximate cable length
1858 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1860 struct e1000_phy_info *phy = &hw->phy;
1862 u16 phy_data, i, agc_value = 0;
1863 u16 cur_agc_index, max_agc_index = 0;
1864 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1865 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1866 IGP02E1000_PHY_AGC_A,
1867 IGP02E1000_PHY_AGC_B,
1868 IGP02E1000_PHY_AGC_C,
1869 IGP02E1000_PHY_AGC_D
1872 /* Read the AGC registers for all channels */
1873 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1874 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1878 /* Getting bits 15:9, which represent the combination of
1879 * coarse and fine gain values. The result is a number
1880 * that can be put into the lookup table to obtain the
1881 * approximate cable length.
1883 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1884 IGP02E1000_AGC_LENGTH_MASK;
1886 /* Array index bound check. */
1887 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1888 (cur_agc_index == 0))
1889 return -E1000_ERR_PHY;
1891 /* Remove min & max AGC values from calculation. */
1892 if (e1000_igp_2_cable_length_table[min_agc_index] >
1893 e1000_igp_2_cable_length_table[cur_agc_index])
1894 min_agc_index = cur_agc_index;
1895 if (e1000_igp_2_cable_length_table[max_agc_index] <
1896 e1000_igp_2_cable_length_table[cur_agc_index])
1897 max_agc_index = cur_agc_index;
1899 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1902 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1903 e1000_igp_2_cable_length_table[max_agc_index]);
1904 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1906 /* Calculate cable length with the error range of +/- 10 meters. */
1907 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1908 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1909 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1911 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1917 * e1000e_get_phy_info_m88 - Retrieve PHY information
1918 * @hw: pointer to the HW structure
1920 * Valid for only copper links. Read the PHY status register (sticky read)
1921 * to verify that link is up. Read the PHY special control register to
1922 * determine the polarity and 10base-T extended distance. Read the PHY
1923 * special status register to determine MDI/MDIx and current speed. If
1924 * speed is 1000, then determine cable length, local and remote receiver.
1926 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1928 struct e1000_phy_info *phy = &hw->phy;
1933 if (phy->media_type != e1000_media_type_copper) {
1934 e_dbg("Phy info is only valid for copper media\n");
1935 return -E1000_ERR_CONFIG;
1938 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1943 e_dbg("Phy info is only valid if link is up\n");
1944 return -E1000_ERR_CONFIG;
1947 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1951 phy->polarity_correction = !!(phy_data &
1952 M88E1000_PSCR_POLARITY_REVERSAL);
1954 ret_val = e1000_check_polarity_m88(hw);
1958 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1962 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1964 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1965 ret_val = e1000_get_cable_length(hw);
1969 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1973 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1974 ? e1000_1000t_rx_status_ok
1975 : e1000_1000t_rx_status_not_ok;
1977 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1978 ? e1000_1000t_rx_status_ok
1979 : e1000_1000t_rx_status_not_ok;
1981 /* Set values to "undefined" */
1982 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1983 phy->local_rx = e1000_1000t_rx_status_undefined;
1984 phy->remote_rx = e1000_1000t_rx_status_undefined;
1991 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1992 * @hw: pointer to the HW structure
1994 * Read PHY status to determine if link is up. If link is up, then
1995 * set/determine 10base-T extended distance and polarity correction. Read
1996 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1997 * determine on the cable length, local and remote receiver.
1999 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2001 struct e1000_phy_info *phy = &hw->phy;
2006 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2011 e_dbg("Phy info is only valid if link is up\n");
2012 return -E1000_ERR_CONFIG;
2015 phy->polarity_correction = true;
2017 ret_val = e1000_check_polarity_igp(hw);
2021 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2025 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2027 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2028 IGP01E1000_PSSR_SPEED_1000MBPS) {
2029 ret_val = e1000_get_cable_length(hw);
2033 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2037 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2038 ? e1000_1000t_rx_status_ok
2039 : e1000_1000t_rx_status_not_ok;
2041 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2042 ? e1000_1000t_rx_status_ok
2043 : e1000_1000t_rx_status_not_ok;
2045 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2046 phy->local_rx = e1000_1000t_rx_status_undefined;
2047 phy->remote_rx = e1000_1000t_rx_status_undefined;
2054 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2055 * @hw: pointer to the HW structure
2057 * Populates "phy" structure with various feature states.
2059 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2061 struct e1000_phy_info *phy = &hw->phy;
2066 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2071 e_dbg("Phy info is only valid if link is up\n");
2072 return -E1000_ERR_CONFIG;
2075 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2078 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2080 if (phy->polarity_correction) {
2081 ret_val = e1000_check_polarity_ife(hw);
2085 /* Polarity is forced */
2086 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2087 ? e1000_rev_polarity_reversed
2088 : e1000_rev_polarity_normal;
2091 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2095 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2097 /* The following parameters are undefined for 10/100 operation. */
2098 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2099 phy->local_rx = e1000_1000t_rx_status_undefined;
2100 phy->remote_rx = e1000_1000t_rx_status_undefined;
2106 * e1000e_phy_sw_reset - PHY software reset
2107 * @hw: pointer to the HW structure
2109 * Does a software reset of the PHY by reading the PHY control register and
2110 * setting/write the control register reset bit to the PHY.
2112 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2117 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2121 phy_ctrl |= MII_CR_RESET;
2122 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2132 * e1000e_phy_hw_reset_generic - PHY hardware reset
2133 * @hw: pointer to the HW structure
2135 * Verify the reset block is not blocking us from resetting. Acquire
2136 * semaphore (if necessary) and read/set/write the device control reset
2137 * bit in the PHY. Wait the appropriate delay time for the device to
2138 * reset and release the semaphore (if necessary).
2140 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2142 struct e1000_phy_info *phy = &hw->phy;
2146 if (phy->ops.check_reset_block) {
2147 ret_val = phy->ops.check_reset_block(hw);
2152 ret_val = phy->ops.acquire(hw);
2157 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2160 udelay(phy->reset_delay_us);
2167 phy->ops.release(hw);
2169 return e1000_get_phy_cfg_done(hw);
2173 * e1000e_get_cfg_done - Generic configuration done
2174 * @hw: pointer to the HW structure
2176 * Generic function to wait 10 milli-seconds for configuration to complete
2177 * and return success.
2179 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2187 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2188 * @hw: pointer to the HW structure
2190 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2192 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2194 e_dbg("Running IGP 3 PHY init script\n");
2196 /* PHY init IGP 3 */
2197 /* Enable rise/fall, 10-mode work in class-A */
2198 e1e_wphy(hw, 0x2F5B, 0x9018);
2199 /* Remove all caps from Replica path filter */
2200 e1e_wphy(hw, 0x2F52, 0x0000);
2201 /* Bias trimming for ADC, AFE and Driver (Default) */
2202 e1e_wphy(hw, 0x2FB1, 0x8B24);
2203 /* Increase Hybrid poly bias */
2204 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2205 /* Add 4% to Tx amplitude in Gig mode */
2206 e1e_wphy(hw, 0x2010, 0x10B0);
2207 /* Disable trimming (TTT) */
2208 e1e_wphy(hw, 0x2011, 0x0000);
2209 /* Poly DC correction to 94.6% + 2% for all channels */
2210 e1e_wphy(hw, 0x20DD, 0x249A);
2211 /* ABS DC correction to 95.9% */
2212 e1e_wphy(hw, 0x20DE, 0x00D3);
2213 /* BG temp curve trim */
2214 e1e_wphy(hw, 0x28B4, 0x04CE);
2215 /* Increasing ADC OPAMP stage 1 currents to max */
2216 e1e_wphy(hw, 0x2F70, 0x29E4);
2217 /* Force 1000 ( required for enabling PHY regs configuration) */
2218 e1e_wphy(hw, 0x0000, 0x0140);
2219 /* Set upd_freq to 6 */
2220 e1e_wphy(hw, 0x1F30, 0x1606);
2222 e1e_wphy(hw, 0x1F31, 0xB814);
2223 /* Disable adaptive fixed FFE (Default) */
2224 e1e_wphy(hw, 0x1F35, 0x002A);
2225 /* Enable FFE hysteresis */
2226 e1e_wphy(hw, 0x1F3E, 0x0067);
2227 /* Fixed FFE for short cable lengths */
2228 e1e_wphy(hw, 0x1F54, 0x0065);
2229 /* Fixed FFE for medium cable lengths */
2230 e1e_wphy(hw, 0x1F55, 0x002A);
2231 /* Fixed FFE for long cable lengths */
2232 e1e_wphy(hw, 0x1F56, 0x002A);
2233 /* Enable Adaptive Clip Threshold */
2234 e1e_wphy(hw, 0x1F72, 0x3FB0);
2235 /* AHT reset limit to 1 */
2236 e1e_wphy(hw, 0x1F76, 0xC0FF);
2237 /* Set AHT master delay to 127 msec */
2238 e1e_wphy(hw, 0x1F77, 0x1DEC);
2239 /* Set scan bits for AHT */
2240 e1e_wphy(hw, 0x1F78, 0xF9EF);
2241 /* Set AHT Preset bits */
2242 e1e_wphy(hw, 0x1F79, 0x0210);
2243 /* Change integ_factor of channel A to 3 */
2244 e1e_wphy(hw, 0x1895, 0x0003);
2245 /* Change prop_factor of channels BCD to 8 */
2246 e1e_wphy(hw, 0x1796, 0x0008);
2247 /* Change cg_icount + enable integbp for channels BCD */
2248 e1e_wphy(hw, 0x1798, 0xD008);
2249 /* Change cg_icount + enable integbp + change prop_factor_master
2250 * to 8 for channel A
2252 e1e_wphy(hw, 0x1898, 0xD918);
2253 /* Disable AHT in Slave mode on channel A */
2254 e1e_wphy(hw, 0x187A, 0x0800);
2255 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2258 e1e_wphy(hw, 0x0019, 0x008D);
2259 /* Enable restart AN on an1000_dis change */
2260 e1e_wphy(hw, 0x001B, 0x2080);
2261 /* Enable wh_fifo read clock in 10/100 modes */
2262 e1e_wphy(hw, 0x0014, 0x0045);
2263 /* Restart AN, Speed selection is 1000 */
2264 e1e_wphy(hw, 0x0000, 0x1340);
2269 /* Internal function pointers */
2272 * e1000_get_phy_cfg_done - Generic PHY configuration done
2273 * @hw: pointer to the HW structure
2275 * Return success if silicon family did not implement a family specific
2276 * get_cfg_done function.
2278 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2280 if (hw->phy.ops.get_cfg_done)
2281 return hw->phy.ops.get_cfg_done(hw);
2287 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2288 * @hw: pointer to the HW structure
2290 * When the silicon family has not implemented a forced speed/duplex
2291 * function for the PHY, simply return 0.
2293 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2295 if (hw->phy.ops.force_speed_duplex)
2296 return hw->phy.ops.force_speed_duplex(hw);
2302 * e1000e_get_phy_type_from_id - Get PHY type from id
2303 * @phy_id: phy_id read from the phy
2305 * Returns the phy type from the id.
2307 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2309 enum e1000_phy_type phy_type = e1000_phy_unknown;
2312 case M88E1000_I_PHY_ID:
2313 case M88E1000_E_PHY_ID:
2314 case M88E1111_I_PHY_ID:
2315 case M88E1011_I_PHY_ID:
2316 phy_type = e1000_phy_m88;
2318 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2319 phy_type = e1000_phy_igp_2;
2321 case GG82563_E_PHY_ID:
2322 phy_type = e1000_phy_gg82563;
2324 case IGP03E1000_E_PHY_ID:
2325 phy_type = e1000_phy_igp_3;
2328 case IFE_PLUS_E_PHY_ID:
2329 case IFE_C_E_PHY_ID:
2330 phy_type = e1000_phy_ife;
2332 case BME1000_E_PHY_ID:
2333 case BME1000_E_PHY_ID_R2:
2334 phy_type = e1000_phy_bm;
2336 case I82578_E_PHY_ID:
2337 phy_type = e1000_phy_82578;
2339 case I82577_E_PHY_ID:
2340 phy_type = e1000_phy_82577;
2342 case I82579_E_PHY_ID:
2343 phy_type = e1000_phy_82579;
2346 phy_type = e1000_phy_i217;
2349 phy_type = e1000_phy_unknown;
2356 * e1000e_determine_phy_address - Determines PHY address.
2357 * @hw: pointer to the HW structure
2359 * This uses a trial and error method to loop through possible PHY
2360 * addresses. It tests each by reading the PHY ID registers and
2361 * checking for a match.
2363 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2367 enum e1000_phy_type phy_type = e1000_phy_unknown;
2369 hw->phy.id = phy_type;
2371 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2372 hw->phy.addr = phy_addr;
2376 e1000e_get_phy_id(hw);
2377 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2379 /* If phy_type is valid, break - we found our
2382 if (phy_type != e1000_phy_unknown)
2385 usleep_range(1000, 2000);
2390 return -E1000_ERR_PHY_TYPE;
2394 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2395 * @page: page to access
2397 * Returns the phy address for the page requested.
2399 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2403 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2410 * e1000e_write_phy_reg_bm - Write BM PHY register
2411 * @hw: pointer to the HW structure
2412 * @offset: register offset to write to
2413 * @data: data to write at register offset
2415 * Acquires semaphore, if necessary, then writes the data to PHY register
2416 * at the offset. Release any acquired semaphores before exiting.
2418 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2421 u32 page = offset >> IGP_PAGE_SHIFT;
2423 ret_val = hw->phy.ops.acquire(hw);
2427 /* Page 800 works differently than the rest so it has its own func */
2428 if (page == BM_WUC_PAGE) {
2429 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2434 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2436 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2437 u32 page_shift, page_select;
2439 /* Page select is register 31 for phy address 1 and 22 for
2440 * phy address 2 and 3. Page select is shifted only for
2443 if (hw->phy.addr == 1) {
2444 page_shift = IGP_PAGE_SHIFT;
2445 page_select = IGP01E1000_PHY_PAGE_SELECT;
2448 page_select = BM_PHY_PAGE_SELECT;
2451 /* Page is shifted left, PHY expects (page x 32) */
2452 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2453 (page << page_shift));
2458 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2462 hw->phy.ops.release(hw);
2467 * e1000e_read_phy_reg_bm - Read BM PHY register
2468 * @hw: pointer to the HW structure
2469 * @offset: register offset to be read
2470 * @data: pointer to the read data
2472 * Acquires semaphore, if necessary, then reads the PHY register at offset
2473 * and storing the retrieved information in data. Release any acquired
2474 * semaphores before exiting.
2476 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2479 u32 page = offset >> IGP_PAGE_SHIFT;
2481 ret_val = hw->phy.ops.acquire(hw);
2485 /* Page 800 works differently than the rest so it has its own func */
2486 if (page == BM_WUC_PAGE) {
2487 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2492 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2494 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2495 u32 page_shift, page_select;
2497 /* Page select is register 31 for phy address 1 and 22 for
2498 * phy address 2 and 3. Page select is shifted only for
2501 if (hw->phy.addr == 1) {
2502 page_shift = IGP_PAGE_SHIFT;
2503 page_select = IGP01E1000_PHY_PAGE_SELECT;
2506 page_select = BM_PHY_PAGE_SELECT;
2509 /* Page is shifted left, PHY expects (page x 32) */
2510 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2511 (page << page_shift));
2516 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2519 hw->phy.ops.release(hw);
2524 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2525 * @hw: pointer to the HW structure
2526 * @offset: register offset to be read
2527 * @data: pointer to the read data
2529 * Acquires semaphore, if necessary, then reads the PHY register at offset
2530 * and storing the retrieved information in data. Release any acquired
2531 * semaphores before exiting.
2533 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2536 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2538 ret_val = hw->phy.ops.acquire(hw);
2542 /* Page 800 works differently than the rest so it has its own func */
2543 if (page == BM_WUC_PAGE) {
2544 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2551 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2553 /* Page is shifted left, PHY expects (page x 32) */
2554 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2561 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2564 hw->phy.ops.release(hw);
2569 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2570 * @hw: pointer to the HW structure
2571 * @offset: register offset to write to
2572 * @data: data to write at register offset
2574 * Acquires semaphore, if necessary, then writes the data to PHY register
2575 * at the offset. Release any acquired semaphores before exiting.
2577 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2580 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2582 ret_val = hw->phy.ops.acquire(hw);
2586 /* Page 800 works differently than the rest so it has its own func */
2587 if (page == BM_WUC_PAGE) {
2588 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2595 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2596 /* Page is shifted left, PHY expects (page x 32) */
2597 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2604 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2608 hw->phy.ops.release(hw);
2613 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2614 * @hw: pointer to the HW structure
2615 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2617 * Assumes semaphore already acquired and phy_reg points to a valid memory
2618 * address to store contents of the BM_WUC_ENABLE_REG register.
2620 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2625 /* All page select, port ctrl and wakeup registers use phy address 1 */
2628 /* Select Port Control Registers page */
2629 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2631 e_dbg("Could not set Port Control page\n");
2635 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2637 e_dbg("Could not read PHY register %d.%d\n",
2638 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2642 /* Enable both PHY wakeup mode and Wakeup register page writes.
2643 * Prevent a power state change by disabling ME and Host PHY wakeup.
2646 temp |= BM_WUC_ENABLE_BIT;
2647 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2649 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2651 e_dbg("Could not write PHY register %d.%d\n",
2652 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2656 /* Select Host Wakeup Registers page - caller now able to write
2657 * registers on the Wakeup registers page
2659 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2663 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2664 * @hw: pointer to the HW structure
2665 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2667 * Restore BM_WUC_ENABLE_REG to its original value.
2669 * Assumes semaphore already acquired and *phy_reg is the contents of the
2670 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2673 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2677 /* Select Port Control Registers page */
2678 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2680 e_dbg("Could not set Port Control page\n");
2684 /* Restore 769.17 to its original value */
2685 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2687 e_dbg("Could not restore PHY register %d.%d\n",
2688 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2694 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2695 * @hw: pointer to the HW structure
2696 * @offset: register offset to be read or written
2697 * @data: pointer to the data to read or write
2698 * @read: determines if operation is read or write
2699 * @page_set: BM_WUC_PAGE already set and access enabled
2701 * Read the PHY register at offset and store the retrieved information in
2702 * data, or write data to PHY register at offset. Note the procedure to
2703 * access the PHY wakeup registers is different than reading the other PHY
2704 * registers. It works as such:
2705 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2706 * 2) Set page to 800 for host (801 if we were manageability)
2707 * 3) Write the address using the address opcode (0x11)
2708 * 4) Read or write the data using the data opcode (0x12)
2709 * 5) Restore 769.17.2 to its original value
2711 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2712 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2714 * Assumes semaphore is already acquired. When page_set==true, assumes
2715 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2716 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2718 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2719 u16 *data, bool read, bool page_set)
2722 u16 reg = BM_PHY_REG_NUM(offset);
2723 u16 page = BM_PHY_REG_PAGE(offset);
2726 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2727 if ((hw->mac.type == e1000_pchlan) &&
2728 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2729 e_dbg("Attempting to access page %d while gig enabled.\n",
2733 /* Enable access to PHY wakeup registers */
2734 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2736 e_dbg("Could not enable PHY wakeup reg access\n");
2741 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2743 /* Write the Wakeup register page offset value using opcode 0x11 */
2744 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2746 e_dbg("Could not write address opcode to page %d\n", page);
2751 /* Read the Wakeup register page value using opcode 0x12 */
2752 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2755 /* Write the Wakeup register page value using opcode 0x12 */
2756 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2761 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2766 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2772 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2773 * @hw: pointer to the HW structure
2775 * In the case of a PHY power down to save power, or to turn off link during a
2776 * driver unload, or wake on lan is not enabled, restore the link to previous
2779 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2783 /* The PHY will retain its settings across a power down/up cycle */
2784 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2785 mii_reg &= ~MII_CR_POWER_DOWN;
2786 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2790 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2791 * @hw: pointer to the HW structure
2793 * In the case of a PHY power down to save power, or to turn off link during a
2794 * driver unload, or wake on lan is not enabled, restore the link to previous
2797 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2801 /* The PHY will retain its settings across a power down/up cycle */
2802 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2803 mii_reg |= MII_CR_POWER_DOWN;
2804 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2805 usleep_range(1000, 2000);
2809 * e1000e_commit_phy - Soft PHY reset
2810 * @hw: pointer to the HW structure
2812 * Performs a soft PHY reset on those that apply. This is a function pointer
2813 * entry point called by drivers.
2815 s32 e1000e_commit_phy(struct e1000_hw *hw)
2817 if (hw->phy.ops.commit)
2818 return hw->phy.ops.commit(hw);
2824 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2825 * @hw: pointer to the HW structure
2826 * @active: boolean used to enable/disable lplu
2828 * Success returns 0, Failure returns 1
2830 * The low power link up (lplu) state is set to the power management level D0
2831 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2832 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2833 * is used during Dx states where the power conservation is most important.
2834 * During driver activity, SmartSpeed should be enabled so performance is
2835 * maintained. This is a function pointer entry point called by drivers.
2837 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2839 if (hw->phy.ops.set_d0_lplu_state)
2840 return hw->phy.ops.set_d0_lplu_state(hw, active);
2846 * __e1000_read_phy_reg_hv - Read HV PHY register
2847 * @hw: pointer to the HW structure
2848 * @offset: register offset to be read
2849 * @data: pointer to the read data
2850 * @locked: semaphore has already been acquired or not
2852 * Acquires semaphore, if necessary, then reads the PHY register at offset
2853 * and stores the retrieved information in data. Release any acquired
2854 * semaphore before exiting.
2856 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2857 bool locked, bool page_set)
2860 u16 page = BM_PHY_REG_PAGE(offset);
2861 u16 reg = BM_PHY_REG_NUM(offset);
2862 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2865 ret_val = hw->phy.ops.acquire(hw);
2870 /* Page 800 works differently than the rest so it has its own func */
2871 if (page == BM_WUC_PAGE) {
2872 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2877 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2878 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2884 if (page == HV_INTC_FC_PAGE_START)
2887 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2888 /* Page is shifted left, PHY expects (page x 32) */
2889 ret_val = e1000_set_page_igp(hw,
2890 (page << IGP_PAGE_SHIFT));
2892 hw->phy.addr = phy_addr;
2899 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2900 page << IGP_PAGE_SHIFT, reg);
2902 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2906 hw->phy.ops.release(hw);
2912 * e1000_read_phy_reg_hv - Read HV PHY register
2913 * @hw: pointer to the HW structure
2914 * @offset: register offset to be read
2915 * @data: pointer to the read data
2917 * Acquires semaphore then reads the PHY register at offset and stores
2918 * the retrieved information in data. Release the acquired semaphore
2921 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2923 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2927 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2928 * @hw: pointer to the HW structure
2929 * @offset: register offset to be read
2930 * @data: pointer to the read data
2932 * Reads the PHY register at offset and stores the retrieved information
2933 * in data. Assumes semaphore already acquired.
2935 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2937 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2941 * e1000_read_phy_reg_page_hv - Read HV PHY register
2942 * @hw: pointer to the HW structure
2943 * @offset: register offset to write to
2944 * @data: data to write at register offset
2946 * Reads the PHY register at offset and stores the retrieved information
2947 * in data. Assumes semaphore already acquired and page already set.
2949 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2951 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2955 * __e1000_write_phy_reg_hv - Write HV PHY register
2956 * @hw: pointer to the HW structure
2957 * @offset: register offset to write to
2958 * @data: data to write at register offset
2959 * @locked: semaphore has already been acquired or not
2961 * Acquires semaphore, if necessary, then writes the data to PHY register
2962 * at the offset. Release any acquired semaphores before exiting.
2964 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2965 bool locked, bool page_set)
2968 u16 page = BM_PHY_REG_PAGE(offset);
2969 u16 reg = BM_PHY_REG_NUM(offset);
2970 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2973 ret_val = hw->phy.ops.acquire(hw);
2978 /* Page 800 works differently than the rest so it has its own func */
2979 if (page == BM_WUC_PAGE) {
2980 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2985 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2986 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2992 if (page == HV_INTC_FC_PAGE_START)
2995 /* Workaround MDIO accesses being disabled after entering IEEE
2996 * Power Down (when bit 11 of the PHY Control register is set)
2998 if ((hw->phy.type == e1000_phy_82578) &&
2999 (hw->phy.revision >= 1) &&
3000 (hw->phy.addr == 2) &&
3001 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
3003 ret_val = e1000_access_phy_debug_regs_hv(hw,
3010 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3011 /* Page is shifted left, PHY expects (page x 32) */
3012 ret_val = e1000_set_page_igp(hw,
3013 (page << IGP_PAGE_SHIFT));
3015 hw->phy.addr = phy_addr;
3022 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3023 page << IGP_PAGE_SHIFT, reg);
3025 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3030 hw->phy.ops.release(hw);
3036 * e1000_write_phy_reg_hv - Write HV PHY register
3037 * @hw: pointer to the HW structure
3038 * @offset: register offset to write to
3039 * @data: data to write at register offset
3041 * Acquires semaphore then writes the data to PHY register at the offset.
3042 * Release the acquired semaphores before exiting.
3044 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3046 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3050 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3051 * @hw: pointer to the HW structure
3052 * @offset: register offset to write to
3053 * @data: data to write at register offset
3055 * Writes the data to PHY register at the offset. Assumes semaphore
3058 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3060 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3064 * e1000_write_phy_reg_page_hv - Write HV PHY register
3065 * @hw: pointer to the HW structure
3066 * @offset: register offset to write to
3067 * @data: data to write at register offset
3069 * Writes the data to PHY register at the offset. Assumes semaphore
3070 * already acquired and page already set.
3072 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3074 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3078 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3079 * @page: page to be accessed
3081 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3085 if (page >= HV_INTC_FC_PAGE_START)
3092 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3093 * @hw: pointer to the HW structure
3094 * @offset: register offset to be read or written
3095 * @data: pointer to the data to be read or written
3096 * @read: determines if operation is read or write
3098 * Reads the PHY register at offset and stores the retreived information
3099 * in data. Assumes semaphore already acquired. Note that the procedure
3100 * to access these regs uses the address port and data port to read/write.
3101 * These accesses done with PHY address 2 and without using pages.
3103 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3104 u16 *data, bool read)
3110 /* This takes care of the difference with desktop vs mobile phy */
3111 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3112 I82578_ADDR_REG : I82577_ADDR_REG;
3113 data_reg = addr_reg + 1;
3115 /* All operations in this function are phy address 2 */
3118 /* masking with 0x3F to remove the page from offset */
3119 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3121 e_dbg("Could not write the Address Offset port register\n");
3125 /* Read or write the data value next */
3127 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3129 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3132 e_dbg("Could not access the Data port register\n");
3138 * e1000_link_stall_workaround_hv - Si workaround
3139 * @hw: pointer to the HW structure
3141 * This function works around a Si bug where the link partner can get
3142 * a link up indication before the PHY does. If small packets are sent
3143 * by the link partner they can be placed in the packet buffer without
3144 * being properly accounted for by the PHY and will stall preventing
3145 * further packets from being received. The workaround is to clear the
3146 * packet buffer after the PHY detects link up.
3148 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3153 if (hw->phy.type != e1000_phy_82578)
3156 /* Do not apply workaround if in PHY loopback bit 14 set */
3157 e1e_rphy(hw, PHY_CONTROL, &data);
3158 if (data & PHY_CONTROL_LB)
3161 /* check if link is up and at 1Gbps */
3162 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3166 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3167 BM_CS_STATUS_SPEED_MASK;
3169 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3170 BM_CS_STATUS_SPEED_1000))
3175 /* flush the packets in the fifo buffer */
3176 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3177 HV_MUX_DATA_CTRL_FORCE_SPEED);
3181 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3185 * e1000_check_polarity_82577 - Checks the polarity.
3186 * @hw: pointer to the HW structure
3188 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3190 * Polarity is determined based on the PHY specific status register.
3192 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3194 struct e1000_phy_info *phy = &hw->phy;
3198 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3201 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3202 ? e1000_rev_polarity_reversed
3203 : e1000_rev_polarity_normal;
3209 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3210 * @hw: pointer to the HW structure
3212 * Calls the PHY setup function to force speed and duplex.
3214 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3216 struct e1000_phy_info *phy = &hw->phy;
3221 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3225 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3227 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3233 if (phy->autoneg_wait_to_complete) {
3234 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3236 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3242 e_dbg("Link taking longer than expected.\n");
3245 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3253 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3254 * @hw: pointer to the HW structure
3256 * Read PHY status to determine if link is up. If link is up, then
3257 * set/determine 10base-T extended distance and polarity correction. Read
3258 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3259 * determine on the cable length, local and remote receiver.
3261 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3263 struct e1000_phy_info *phy = &hw->phy;
3268 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3273 e_dbg("Phy info is only valid if link is up\n");
3274 return -E1000_ERR_CONFIG;
3277 phy->polarity_correction = true;
3279 ret_val = e1000_check_polarity_82577(hw);
3283 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3287 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3289 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3290 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3291 ret_val = hw->phy.ops.get_cable_length(hw);
3295 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3299 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3300 ? e1000_1000t_rx_status_ok
3301 : e1000_1000t_rx_status_not_ok;
3303 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3304 ? e1000_1000t_rx_status_ok
3305 : e1000_1000t_rx_status_not_ok;
3307 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3308 phy->local_rx = e1000_1000t_rx_status_undefined;
3309 phy->remote_rx = e1000_1000t_rx_status_undefined;
3316 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3317 * @hw: pointer to the HW structure
3319 * Reads the diagnostic status register and verifies result is valid before
3320 * placing it in the phy_cable_length field.
3322 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3324 struct e1000_phy_info *phy = &hw->phy;
3326 u16 phy_data, length;
3328 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3332 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3333 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3335 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3336 ret_val = -E1000_ERR_PHY;
3338 phy->cable_length = length;