arch/arm/mach-omap2/omap_hwmod_2430_data.c

   1 /*
   2  * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * XXX handle crossbar/shared link difference for L3?
  13  * XXX these should be marked initdata for multi-OMAP kernels
  14  */
  15
  16 #include <linux/i2c-omap.h>
  17 #include <linux/platform_data/asoc-ti-mcbsp.h>
  18 #include <linux/platform_data/spi-omap2-mcspi.h>
  19 #include <linux/omap-dma.h>
  20 #include <plat/dmtimer.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "mmc.h"
  24 #include "l3_2xxx.h"
  25
  26 #include "soc.h"
  27 #include "omap_hwmod_common_data.h"
  28 #include "prm-regbits-24xx.h"
  29 #include "cm-regbits-24xx.h"
  30 #include "i2c.h"
  31 #include "wd_timer.h"
  32
  33 /*
  34  * OMAP2430 hardware module integration data
  35  *
  36  * All of the data in this section should be autogeneratable from the
  37  * TI hardware database or other technical documentation.  Data that
  38  * is driver-specific or driver-kernel integration-specific belongs
  39  * elsewhere.
  40  */
  41
  42 /*
  43  * IP blocks
  44  */
  45
  46 /* IVA2 (IVA2) */
  47 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
  48         { .name = "logic", .rst_shift = 0 },
  49         { .name = "mmu", .rst_shift = 1 },
  50 };
  51
  52 static struct omap_hwmod omap2430_iva_hwmod = {
  53         .name           = "iva",
  54         .class          = &iva_hwmod_class,
  55         .clkdm_name     = "dsp_clkdm",
  56         .rst_lines      = omap2430_iva_resets,
  57         .rst_lines_cnt  = ARRAY_SIZE(omap2430_iva_resets),
  58         .main_clk       = "dsp_fck",
  59 };
  60
  61 /* I2C common */
  62 static struct omap_hwmod_class_sysconfig i2c_sysc = {
  63         .rev_offs       = 0x00,
  64         .sysc_offs      = 0x20,
  65         .syss_offs      = 0x10,
  66         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  67                            SYSS_HAS_RESET_STATUS),
  68         .sysc_fields    = &omap_hwmod_sysc_type1,
  69 };
  70
  71 static struct omap_hwmod_class i2c_class = {
  72         .name           = "i2c",
  73         .sysc           = &i2c_sysc,
  74         .rev            = OMAP_I2C_IP_VERSION_1,
  75         .reset          = &omap_i2c_reset,
  76 };
  77
  78 static struct omap_i2c_dev_attr i2c_dev_attr = {
  79         .fifo_depth     = 8, /* bytes */
  80         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
  81                           OMAP_I2C_FLAG_BUS_SHIFT_2 |
  82                           OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
  83 };
  84
  85 /* I2C1 */
  86 static struct omap_hwmod omap2430_i2c1_hwmod = {
  87         .name           = "i2c1",
  88         .flags          = HWMOD_16BIT_REG,
  89         .mpu_irqs       = omap2_i2c1_mpu_irqs,
  90         .sdma_reqs      = omap2_i2c1_sdma_reqs,
  91         .main_clk       = "i2chs1_fck",
  92         .prcm           = {
  93                 .omap2 = {
  94                         /*
  95                          * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
  96                          * I2CHS IP's do not follow the usual pattern.
  97                          * prcm_reg_id alone cannot be used to program
  98                          * the iclk and fclk. Needs to be handled using
  99                          * additional flags when clk handling is moved
 100                          * to hwmod framework.
 101                          */
 102                         .module_offs = CORE_MOD,
 103                         .prcm_reg_id = 1,
 104                         .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
 105                         .idlest_reg_id = 1,
 106                         .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
 107                 },
 108         },
 109         .class          = &i2c_class,
 110         .dev_attr       = &i2c_dev_attr,
 111 };
 112
 113 /* I2C2 */
 114 static struct omap_hwmod omap2430_i2c2_hwmod = {
 115         .name           = "i2c2",
 116         .flags          = HWMOD_16BIT_REG,
 117         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 118         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 119         .main_clk       = "i2chs2_fck",
 120         .prcm           = {
 121                 .omap2 = {
 122                         .module_offs = CORE_MOD,
 123                         .prcm_reg_id = 1,
 124                         .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
 125                         .idlest_reg_id = 1,
 126                         .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
 127                 },
 128         },
 129         .class          = &i2c_class,
 130         .dev_attr       = &i2c_dev_attr,
 131 };
 132
 133 /* gpio5 */
 134 static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
 135         { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
 136         { .irq = -1 },
 137 };
 138
 139 static struct omap_hwmod omap2430_gpio5_hwmod = {
 140         .name           = "gpio5",
 141         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 142         .mpu_irqs       = omap243x_gpio5_irqs,
 143         .main_clk       = "gpio5_fck",
 144         .prcm           = {
 145                 .omap2 = {
 146                         .prcm_reg_id = 2,
 147                         .module_bit = OMAP2430_EN_GPIO5_SHIFT,
 148                         .module_offs = CORE_MOD,
 149                         .idlest_reg_id = 2,
 150                         .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
 151                 },
 152         },
 153         .class          = &omap2xxx_gpio_hwmod_class,
 154         .dev_attr       = &omap2xxx_gpio_dev_attr,
 155 };
 156
 157 /* dma attributes */
 158 static struct omap_dma_dev_attr dma_dev_attr = {
 159         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 160                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 161         .lch_count = 32,
 162 };
 163
 164 static struct omap_hwmod omap2430_dma_system_hwmod = {
 165         .name           = "dma",
 166         .class          = &omap2xxx_dma_hwmod_class,
 167         .mpu_irqs       = omap2_dma_system_irqs,
 168         .main_clk       = "core_l3_ck",
 169         .dev_attr       = &dma_dev_attr,
 170         .flags          = HWMOD_NO_IDLEST,
 171 };
 172
 173 /* mailbox */
 174 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
 175         { .irq = 26 + OMAP_INTC_START, },
 176         { .irq = -1 },
 177 };
 178
 179 static struct omap_hwmod omap2430_mailbox_hwmod = {
 180         .name           = "mailbox",
 181         .class          = &omap2xxx_mailbox_hwmod_class,
 182         .mpu_irqs       = omap2430_mailbox_irqs,
 183         .main_clk       = "mailboxes_ick",
 184         .prcm           = {
 185                 .omap2 = {
 186                         .prcm_reg_id = 1,
 187                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
 188                         .module_offs = CORE_MOD,
 189                         .idlest_reg_id = 1,
 190                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 191                 },
 192         },
 193 };
 194
 195 /* mcspi3 */
 196 static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
 197         { .irq = 91 + OMAP_INTC_START, },
 198         { .irq = -1 },
 199 };
 200
 201 static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
 202         { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
 203         { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
 204         { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
 205         { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
 206         { .dma_req = -1 }
 207 };
 208
 209 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
 210         .num_chipselect = 2,
 211 };
 212
 213 static struct omap_hwmod omap2430_mcspi3_hwmod = {
 214         .name           = "mcspi3",
 215         .mpu_irqs       = omap2430_mcspi3_mpu_irqs,
 216         .sdma_reqs      = omap2430_mcspi3_sdma_reqs,
 217         .main_clk       = "mcspi3_fck",
 218         .prcm           = {
 219                 .omap2 = {
 220                         .module_offs = CORE_MOD,
 221                         .prcm_reg_id = 2,
 222                         .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
 223                         .idlest_reg_id = 2,
 224                         .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
 225                 },
 226         },
 227         .class          = &omap2xxx_mcspi_class,
 228         .dev_attr       = &omap_mcspi3_dev_attr,
 229 };
 230
 231 /* usbhsotg */
 232 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
 233         .rev_offs       = 0x0400,
 234         .sysc_offs      = 0x0404,
 235         .syss_offs      = 0x0408,
 236         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
 237                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 238                           SYSC_HAS_AUTOIDLE),
 239         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 240                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 241         .sysc_fields    = &omap_hwmod_sysc_type1,
 242 };
 243
 244 static struct omap_hwmod_class usbotg_class = {
 245         .name = "usbotg",
 246         .sysc = &omap2430_usbhsotg_sysc,
 247 };
 248
 249 /* usb_otg_hs */
 250 static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
 251
 252         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
 253         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
 254         { .irq = -1 },
 255 };
 256
 257 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
 258         .name           = "usb_otg_hs",
 259         .mpu_irqs       = omap2430_usbhsotg_mpu_irqs,
 260         .main_clk       = "usbhs_ick",
 261         .prcm           = {
 262                 .omap2 = {
 263                         .prcm_reg_id = 1,
 264                         .module_bit = OMAP2430_EN_USBHS_MASK,
 265                         .module_offs = CORE_MOD,
 266                         .idlest_reg_id = 1,
 267                         .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
 268                 },
 269         },
 270         .class          = &usbotg_class,
 271         /*
 272          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
 273          * broken when autoidle is enabled
 274          * workaround is to disable the autoidle bit at module level.
 275          */
 276         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
 277                                 | HWMOD_SWSUP_MSTANDBY,
 278 };
 279
 280 /*
 281  * 'mcbsp' class
 282  * multi channel buffered serial port controller
 283  */
 284
 285 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
 286         .rev_offs       = 0x007C,
 287         .sysc_offs      = 0x008C,
 288         .sysc_flags     = (SYSC_HAS_SOFTRESET),
 289         .sysc_fields    = &omap_hwmod_sysc_type1,
 290 };
 291
 292 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
 293         .name = "mcbsp",
 294         .sysc = &omap2430_mcbsp_sysc,
 295         .rev  = MCBSP_CONFIG_TYPE2,
 296 };
 297
 298 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 299         { .role = "pad_fck", .clk = "mcbsp_clks" },
 300         { .role = "prcm_fck", .clk = "func_96m_ck" },
 301 };
 302
 303 /* mcbsp1 */
 304 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
 305         { .name = "tx",         .irq = 59 + OMAP_INTC_START, },
 306         { .name = "rx",         .irq = 60 + OMAP_INTC_START, },
 307         { .name = "ovr",        .irq = 61 + OMAP_INTC_START, },
 308         { .name = "common",     .irq = 64 + OMAP_INTC_START, },
 309         { .irq = -1 },
 310 };
 311
 312 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
 313         .name           = "mcbsp1",
 314         .class          = &omap2430_mcbsp_hwmod_class,
 315         .mpu_irqs       = omap2430_mcbsp1_irqs,
 316         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
 317         .main_clk       = "mcbsp1_fck",
 318         .prcm           = {
 319                 .omap2 = {
 320                         .prcm_reg_id = 1,
 321                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
 322                         .module_offs = CORE_MOD,
 323                         .idlest_reg_id = 1,
 324                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
 325                 },
 326         },
 327         .opt_clks       = mcbsp_opt_clks,
 328         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 329 };
 330
 331 /* mcbsp2 */
 332 static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
 333         { .name = "tx",         .irq = 62 + OMAP_INTC_START, },
 334         { .name = "rx",         .irq = 63 + OMAP_INTC_START, },
 335         { .name = "common",     .irq = 16 + OMAP_INTC_START, },
 336         { .irq = -1 },
 337 };
 338
 339 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
 340         .name           = "mcbsp2",
 341         .class          = &omap2430_mcbsp_hwmod_class,
 342         .mpu_irqs       = omap2430_mcbsp2_irqs,
 343         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
 344         .main_clk       = "mcbsp2_fck",
 345         .prcm           = {
 346                 .omap2 = {
 347                         .prcm_reg_id = 1,
 348                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
 349                         .module_offs = CORE_MOD,
 350                         .idlest_reg_id = 1,
 351                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
 352                 },
 353         },
 354         .opt_clks       = mcbsp_opt_clks,
 355         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 356 };
 357
 358 /* mcbsp3 */
 359 static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
 360         { .name = "tx",         .irq = 89 + OMAP_INTC_START, },
 361         { .name = "rx",         .irq = 90 + OMAP_INTC_START, },
 362         { .name = "common",     .irq = 17 + OMAP_INTC_START, },
 363         { .irq = -1 },
 364 };
 365
 366 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
 367         .name           = "mcbsp3",
 368         .class          = &omap2430_mcbsp_hwmod_class,
 369         .mpu_irqs       = omap2430_mcbsp3_irqs,
 370         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
 371         .main_clk       = "mcbsp3_fck",
 372         .prcm           = {
 373                 .omap2 = {
 374                         .prcm_reg_id = 1,
 375                         .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
 376                         .module_offs = CORE_MOD,
 377                         .idlest_reg_id = 2,
 378                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
 379                 },
 380         },
 381         .opt_clks       = mcbsp_opt_clks,
 382         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 383 };
 384
 385 /* mcbsp4 */
 386 static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
 387         { .name = "tx",         .irq = 54 + OMAP_INTC_START, },
 388         { .name = "rx",         .irq = 55 + OMAP_INTC_START, },
 389         { .name = "common",     .irq = 18 + OMAP_INTC_START, },
 390         { .irq = -1 },
 391 };
 392
 393 static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
 394         { .name = "rx", .dma_req = 20 },
 395         { .name = "tx", .dma_req = 19 },
 396         { .dma_req = -1 }
 397 };
 398
 399 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
 400         .name           = "mcbsp4",
 401         .class          = &omap2430_mcbsp_hwmod_class,
 402         .mpu_irqs       = omap2430_mcbsp4_irqs,
 403         .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
 404         .main_clk       = "mcbsp4_fck",
 405         .prcm           = {
 406                 .omap2 = {
 407                         .prcm_reg_id = 1,
 408                         .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
 409                         .module_offs = CORE_MOD,
 410                         .idlest_reg_id = 2,
 411                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
 412                 },
 413         },
 414         .opt_clks       = mcbsp_opt_clks,
 415         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 416 };
 417
 418 /* mcbsp5 */
 419 static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
 420         { .name = "tx",         .irq = 81 + OMAP_INTC_START, },
 421         { .name = "rx",         .irq = 82 + OMAP_INTC_START, },
 422         { .name = "common",     .irq = 19 + OMAP_INTC_START, },
 423         { .irq = -1 },
 424 };
 425
 426 static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
 427         { .name = "rx", .dma_req = 22 },
 428         { .name = "tx", .dma_req = 21 },
 429         { .dma_req = -1 }
 430 };
 431
 432 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
 433         .name           = "mcbsp5",
 434         .class          = &omap2430_mcbsp_hwmod_class,
 435         .mpu_irqs       = omap2430_mcbsp5_irqs,
 436         .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
 437         .main_clk       = "mcbsp5_fck",
 438         .prcm           = {
 439                 .omap2 = {
 440                         .prcm_reg_id = 1,
 441                         .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
 442                         .module_offs = CORE_MOD,
 443                         .idlest_reg_id = 2,
 444                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
 445                 },
 446         },
 447         .opt_clks       = mcbsp_opt_clks,
 448         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 449 };
 450
 451 /* MMC/SD/SDIO common */
 452 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
 453         .rev_offs       = 0x1fc,
 454         .sysc_offs      = 0x10,
 455         .syss_offs      = 0x14,
 456         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 457                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 458                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 459         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 460         .sysc_fields    = &omap_hwmod_sysc_type1,
 461 };
 462
 463 static struct omap_hwmod_class omap2430_mmc_class = {
 464         .name = "mmc",
 465         .sysc = &omap2430_mmc_sysc,
 466 };
 467
 468 /* MMC/SD/SDIO1 */
 469 static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
 470         { .irq = 83 + OMAP_INTC_START, },
 471         { .irq = -1 },
 472 };
 473
 474 static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
 475         { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
 476         { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
 477         { .dma_req = -1 }
 478 };
 479
 480 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
 481         { .role = "dbck", .clk = "mmchsdb1_fck" },
 482 };
 483
 484 static struct omap_mmc_dev_attr mmc1_dev_attr = {
 485         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 486 };
 487
 488 static struct omap_hwmod omap2430_mmc1_hwmod = {
 489         .name           = "mmc1",
 490         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 491         .mpu_irqs       = omap2430_mmc1_mpu_irqs,
 492         .sdma_reqs      = omap2430_mmc1_sdma_reqs,
 493         .opt_clks       = omap2430_mmc1_opt_clks,
 494         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
 495         .main_clk       = "mmchs1_fck",
 496         .prcm           = {
 497                 .omap2 = {
 498                         .module_offs = CORE_MOD,
 499                         .prcm_reg_id = 2,
 500                         .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
 501                         .idlest_reg_id = 2,
 502                         .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
 503                 },
 504         },
 505         .dev_attr       = &mmc1_dev_attr,
 506         .class          = &omap2430_mmc_class,
 507 };
 508
 509 /* MMC/SD/SDIO2 */
 510 static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
 511         { .irq = 86 + OMAP_INTC_START, },
 512         { .irq = -1 },
 513 };
 514
 515 static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
 516         { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
 517         { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
 518         { .dma_req = -1 }
 519 };
 520
 521 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
 522         { .role = "dbck", .clk = "mmchsdb2_fck" },
 523 };
 524
 525 static struct omap_hwmod omap2430_mmc2_hwmod = {
 526         .name           = "mmc2",
 527         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 528         .mpu_irqs       = omap2430_mmc2_mpu_irqs,
 529         .sdma_reqs      = omap2430_mmc2_sdma_reqs,
 530         .opt_clks       = omap2430_mmc2_opt_clks,
 531         .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
 532         .main_clk       = "mmchs2_fck",
 533         .prcm           = {
 534                 .omap2 = {
 535                         .module_offs = CORE_MOD,
 536                         .prcm_reg_id = 2,
 537                         .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
 538                         .idlest_reg_id = 2,
 539                         .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
 540                 },
 541         },
 542         .class          = &omap2430_mmc_class,
 543 };
 544
 545 /* HDQ1W/1-wire */
 546 static struct omap_hwmod omap2430_hdq1w_hwmod = {
 547         .name           = "hdq1w",
 548         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
 549         .main_clk       = "hdq_fck",
 550         .prcm           = {
 551                 .omap2 = {
 552                         .module_offs = CORE_MOD,
 553                         .prcm_reg_id = 1,
 554                         .module_bit = OMAP24XX_EN_HDQ_SHIFT,
 555                         .idlest_reg_id = 1,
 556                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
 557                 },
 558         },
 559         .class          = &omap2_hdq1w_class,
 560 };
 561
 562 /*
 563  * interfaces
 564  */
 565
 566 /* L3 -> L4_CORE interface */
 567 /* l3_core -> usbhsotg  interface */
 568 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
 569         .master         = &omap2430_usbhsotg_hwmod,
 570         .slave          = &omap2xxx_l3_main_hwmod,
 571         .clk            = "core_l3_ck",
 572         .user           = OCP_USER_MPU,
 573 };
 574
 575 /* L4 CORE -> I2C1 interface */
 576 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
 577         .master         = &omap2xxx_l4_core_hwmod,
 578         .slave          = &omap2430_i2c1_hwmod,
 579         .clk            = "i2c1_ick",
 580         .addr           = omap2_i2c1_addr_space,
 581         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 582 };
 583
 584 /* L4 CORE -> I2C2 interface */
 585 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
 586         .master         = &omap2xxx_l4_core_hwmod,
 587         .slave          = &omap2430_i2c2_hwmod,
 588         .clk            = "i2c2_ick",
 589         .addr           = omap2_i2c2_addr_space,
 590         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 591 };
 592
 593 static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
 594         {
 595                 .pa_start       = OMAP243X_HS_BASE,
 596                 .pa_end         = OMAP243X_HS_BASE + SZ_4K - 1,
 597                 .flags          = ADDR_TYPE_RT
 598         },
 599         { }
 600 };
 601
 602 /*  l4_core ->usbhsotg  interface */
 603 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
 604         .master         = &omap2xxx_l4_core_hwmod,
 605         .slave          = &omap2430_usbhsotg_hwmod,
 606         .clk            = "usb_l4_ick",
 607         .addr           = omap2430_usbhsotg_addrs,
 608         .user           = OCP_USER_MPU,
 609 };
 610
 611 /* L4 CORE -> MMC1 interface */
 612 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
 613         .master         = &omap2xxx_l4_core_hwmod,
 614         .slave          = &omap2430_mmc1_hwmod,
 615         .clk            = "mmchs1_ick",
 616         .addr           = omap2430_mmc1_addr_space,
 617         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 618 };
 619
 620 /* L4 CORE -> MMC2 interface */
 621 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
 622         .master         = &omap2xxx_l4_core_hwmod,
 623         .slave          = &omap2430_mmc2_hwmod,
 624         .clk            = "mmchs2_ick",
 625         .addr           = omap2430_mmc2_addr_space,
 626         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 627 };
 628
 629 /* l4 core -> mcspi3 interface */
 630 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
 631         .master         = &omap2xxx_l4_core_hwmod,
 632         .slave          = &omap2430_mcspi3_hwmod,
 633         .clk            = "mcspi3_ick",
 634         .addr           = omap2430_mcspi3_addr_space,
 635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 636 };
 637
 638 /* IVA2 <- L3 interface */
 639 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
 640         .master         = &omap2xxx_l3_main_hwmod,
 641         .slave          = &omap2430_iva_hwmod,
 642         .clk            = "core_l3_ck",
 643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 644 };
 645
 646 static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
 647         {
 648                 .pa_start       = 0x49018000,
 649                 .pa_end         = 0x49018000 + SZ_1K - 1,
 650                 .flags          = ADDR_TYPE_RT
 651         },
 652         { }
 653 };
 654
 655 /* l4_wkup -> timer1 */
 656 static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
 657         .master         = &omap2xxx_l4_wkup_hwmod,
 658         .slave          = &omap2xxx_timer1_hwmod,
 659         .clk            = "gpt1_ick",
 660         .addr           = omap2430_timer1_addrs,
 661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 662 };
 663
 664 /* l4_wkup -> wd_timer2 */
 665 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
 666         {
 667                 .pa_start       = 0x49016000,
 668                 .pa_end         = 0x4901607f,
 669                 .flags          = ADDR_TYPE_RT
 670         },
 671         { }
 672 };
 673
 674 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
 675         .master         = &omap2xxx_l4_wkup_hwmod,
 676         .slave          = &omap2xxx_wd_timer2_hwmod,
 677         .clk            = "mpu_wdt_ick",
 678         .addr           = omap2430_wd_timer2_addrs,
 679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 680 };
 681
 682 /* l4_wkup -> gpio1 */
 683 static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
 684         {
 685                 .pa_start       = 0x4900C000,
 686                 .pa_end         = 0x4900C1ff,
 687                 .flags          = ADDR_TYPE_RT
 688         },
 689         { }
 690 };
 691
 692 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
 693         .master         = &omap2xxx_l4_wkup_hwmod,
 694         .slave          = &omap2xxx_gpio1_hwmod,
 695         .clk            = "gpios_ick",
 696         .addr           = omap2430_gpio1_addr_space,
 697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 698 };
 699
 700 /* l4_wkup -> gpio2 */
 701 static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
 702         {
 703                 .pa_start       = 0x4900E000,
 704                 .pa_end         = 0x4900E1ff,
 705                 .flags          = ADDR_TYPE_RT
 706         },
 707         { }
 708 };
 709
 710 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
 711         .master         = &omap2xxx_l4_wkup_hwmod,
 712         .slave          = &omap2xxx_gpio2_hwmod,
 713         .clk            = "gpios_ick",
 714         .addr           = omap2430_gpio2_addr_space,
 715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 716 };
 717
 718 /* l4_wkup -> gpio3 */
 719 static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
 720         {
 721                 .pa_start       = 0x49010000,
 722                 .pa_end         = 0x490101ff,
 723                 .flags          = ADDR_TYPE_RT
 724         },
 725         { }
 726 };
 727
 728 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
 729         .master         = &omap2xxx_l4_wkup_hwmod,
 730         .slave          = &omap2xxx_gpio3_hwmod,
 731         .clk            = "gpios_ick",
 732         .addr           = omap2430_gpio3_addr_space,
 733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 734 };
 735
 736 /* l4_wkup -> gpio4 */
 737 static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
 738         {
 739                 .pa_start       = 0x49012000,
 740                 .pa_end         = 0x490121ff,
 741                 .flags          = ADDR_TYPE_RT
 742         },
 743         { }
 744 };
 745
 746 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
 747         .master         = &omap2xxx_l4_wkup_hwmod,
 748         .slave          = &omap2xxx_gpio4_hwmod,
 749         .clk            = "gpios_ick",
 750         .addr           = omap2430_gpio4_addr_space,
 751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 752 };
 753
 754 /* l4_core -> gpio5 */
 755 static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
 756         {
 757                 .pa_start       = 0x480B6000,
 758                 .pa_end         = 0x480B61ff,
 759                 .flags          = ADDR_TYPE_RT
 760         },
 761         { }
 762 };
 763
 764 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
 765         .master         = &omap2xxx_l4_core_hwmod,
 766         .slave          = &omap2430_gpio5_hwmod,
 767         .clk            = "gpio5_ick",
 768         .addr           = omap2430_gpio5_addr_space,
 769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 770 };
 771
 772 /* dma_system -> L3 */
 773 static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
 774         .master         = &omap2430_dma_system_hwmod,
 775         .slave          = &omap2xxx_l3_main_hwmod,
 776         .clk            = "core_l3_ck",
 777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 778 };
 779
 780 /* l4_core -> dma_system */
 781 static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
 782         .master         = &omap2xxx_l4_core_hwmod,
 783         .slave          = &omap2430_dma_system_hwmod,
 784         .clk            = "sdma_ick",
 785         .addr           = omap2_dma_system_addrs,
 786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 787 };
 788
 789 /* l4_core -> mailbox */
 790 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
 791         .master         = &omap2xxx_l4_core_hwmod,
 792         .slave          = &omap2430_mailbox_hwmod,
 793         .addr           = omap2_mailbox_addrs,
 794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 795 };
 796
 797 /* l4_core -> mcbsp1 */
 798 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
 799         .master         = &omap2xxx_l4_core_hwmod,
 800         .slave          = &omap2430_mcbsp1_hwmod,
 801         .clk            = "mcbsp1_ick",
 802         .addr           = omap2_mcbsp1_addrs,
 803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 804 };
 805
 806 /* l4_core -> mcbsp2 */
 807 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
 808         .master         = &omap2xxx_l4_core_hwmod,
 809         .slave          = &omap2430_mcbsp2_hwmod,
 810         .clk            = "mcbsp2_ick",
 811         .addr           = omap2xxx_mcbsp2_addrs,
 812         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 813 };
 814
 815 static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
 816         {
 817                 .name           = "mpu",
 818                 .pa_start       = 0x4808C000,
 819                 .pa_end         = 0x4808C0ff,
 820                 .flags          = ADDR_TYPE_RT
 821         },
 822         { }
 823 };
 824
 825 /* l4_core -> mcbsp3 */
 826 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
 827         .master         = &omap2xxx_l4_core_hwmod,
 828         .slave          = &omap2430_mcbsp3_hwmod,
 829         .clk            = "mcbsp3_ick",
 830         .addr           = omap2430_mcbsp3_addrs,
 831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 832 };
 833
 834 static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
 835         {
 836                 .name           = "mpu",
 837                 .pa_start       = 0x4808E000,
 838                 .pa_end         = 0x4808E0ff,
 839                 .flags          = ADDR_TYPE_RT
 840         },
 841         { }
 842 };
 843
 844 /* l4_core -> mcbsp4 */
 845 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
 846         .master         = &omap2xxx_l4_core_hwmod,
 847         .slave          = &omap2430_mcbsp4_hwmod,
 848         .clk            = "mcbsp4_ick",
 849         .addr           = omap2430_mcbsp4_addrs,
 850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 851 };
 852
 853 static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
 854         {
 855                 .name           = "mpu",
 856                 .pa_start       = 0x48096000,
 857                 .pa_end         = 0x480960ff,
 858                 .flags          = ADDR_TYPE_RT
 859         },
 860         { }
 861 };
 862
 863 /* l4_core -> mcbsp5 */
 864 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
 865         .master         = &omap2xxx_l4_core_hwmod,
 866         .slave          = &omap2430_mcbsp5_hwmod,
 867         .clk            = "mcbsp5_ick",
 868         .addr           = omap2430_mcbsp5_addrs,
 869         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 870 };
 871
 872 /* l4_core -> hdq1w */
 873 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
 874         .master         = &omap2xxx_l4_core_hwmod,
 875         .slave          = &omap2430_hdq1w_hwmod,
 876         .clk            = "hdq_ick",
 877         .addr           = omap2_hdq1w_addr_space,
 878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 879         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 880 };
 881
 882 /* l4_wkup -> 32ksync_counter */
 883 static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
 884         {
 885                 .pa_start       = 0x49020000,
 886                 .pa_end         = 0x4902001f,
 887                 .flags          = ADDR_TYPE_RT
 888         },
 889         { }
 890 };
 891
 892 static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
 893         {
 894                 .pa_start       = 0x6e000000,
 895                 .pa_end         = 0x6e000fff,
 896                 .flags          = ADDR_TYPE_RT
 897         },
 898         { }
 899 };
 900
 901 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
 902         .master         = &omap2xxx_l4_wkup_hwmod,
 903         .slave          = &omap2xxx_counter_32k_hwmod,
 904         .clk            = "sync_32k_ick",
 905         .addr           = omap2430_counter_32k_addrs,
 906         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 907 };
 908
 909 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
 910         .master         = &omap2xxx_l3_main_hwmod,
 911         .slave          = &omap2xxx_gpmc_hwmod,
 912         .clk            = "core_l3_ck",
 913         .addr           = omap2430_gpmc_addrs,
 914         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 915 };
 916
 917 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 918         &omap2xxx_l3_main__l4_core,
 919         &omap2xxx_mpu__l3_main,
 920         &omap2xxx_dss__l3,
 921         &omap2430_usbhsotg__l3,
 922         &omap2430_l4_core__i2c1,
 923         &omap2430_l4_core__i2c2,
 924         &omap2xxx_l4_core__l4_wkup,
 925         &omap2_l4_core__uart1,
 926         &omap2_l4_core__uart2,
 927         &omap2_l4_core__uart3,
 928         &omap2430_l4_core__usbhsotg,
 929         &omap2430_l4_core__mmc1,
 930         &omap2430_l4_core__mmc2,
 931         &omap2xxx_l4_core__mcspi1,
 932         &omap2xxx_l4_core__mcspi2,
 933         &omap2430_l4_core__mcspi3,
 934         &omap2430_l3__iva,
 935         &omap2430_l4_wkup__timer1,
 936         &omap2xxx_l4_core__timer2,
 937         &omap2xxx_l4_core__timer3,
 938         &omap2xxx_l4_core__timer4,
 939         &omap2xxx_l4_core__timer5,
 940         &omap2xxx_l4_core__timer6,
 941         &omap2xxx_l4_core__timer7,
 942         &omap2xxx_l4_core__timer8,
 943         &omap2xxx_l4_core__timer9,
 944         &omap2xxx_l4_core__timer10,
 945         &omap2xxx_l4_core__timer11,
 946         &omap2xxx_l4_core__timer12,
 947         &omap2430_l4_wkup__wd_timer2,
 948         &omap2xxx_l4_core__dss,
 949         &omap2xxx_l4_core__dss_dispc,
 950         &omap2xxx_l4_core__dss_rfbi,
 951         &omap2xxx_l4_core__dss_venc,
 952         &omap2430_l4_wkup__gpio1,
 953         &omap2430_l4_wkup__gpio2,
 954         &omap2430_l4_wkup__gpio3,
 955         &omap2430_l4_wkup__gpio4,
 956         &omap2430_l4_core__gpio5,
 957         &omap2430_dma_system__l3,
 958         &omap2430_l4_core__dma_system,
 959         &omap2430_l4_core__mailbox,
 960         &omap2430_l4_core__mcbsp1,
 961         &omap2430_l4_core__mcbsp2,
 962         &omap2430_l4_core__mcbsp3,
 963         &omap2430_l4_core__mcbsp4,
 964         &omap2430_l4_core__mcbsp5,
 965         &omap2430_l4_core__hdq1w,
 966         &omap2xxx_l4_core__rng,
 967         &omap2430_l4_wkup__counter_32k,
 968         &omap2430_l3__gpmc,
 969         NULL,
 970 };
 971
 972 int __init omap2430_hwmod_init(void)
 973 {
 974         omap_hwmod_init();
 975         return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
 976 }