arch/arm/mach-exynos/pm.c

   1 /*
   2  * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - Power Management support
   6  *
   7  * Based on arch/arm/mach-s3c2410/pm.c
   8  * Copyright (c) 2006 Simtec Electronics
   9  *      Ben Dooks <ben@simtec.co.uk>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/smp_scu.h>
  26
  27 #include <plat/cpu.h>
  28 #include <plat/pm.h>
  29 #include <plat/pll.h>
  30 #include <plat/regs-srom.h>
  31
  32 #include <mach/regs-irq.h>
  33 #include <mach/regs-gpio.h>
  34 #include <mach/regs-clock.h>
  35 #include <mach/regs-pmu.h>
  36 #include <mach/pm-core.h>
  37 #include <mach/pmu.h>
  38
  39 static struct sleep_save exynos4_set_clksrc[] = {
  40         { .reg = EXYNOS4_CLKSRC_MASK_TOP                , .val = 0x00000001, },
  41         { .reg = EXYNOS4_CLKSRC_MASK_CAM                , .val = 0x11111111, },
  42         { .reg = EXYNOS4_CLKSRC_MASK_TV                 , .val = 0x00000111, },
  43         { .reg = EXYNOS4_CLKSRC_MASK_LCD0               , .val = 0x00001111, },
  44         { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO             , .val = 0x00000001, },
  45         { .reg = EXYNOS4_CLKSRC_MASK_FSYS               , .val = 0x01011111, },
  46         { .reg = EXYNOS4_CLKSRC_MASK_PERIL0             , .val = 0x01111111, },
  47         { .reg = EXYNOS4_CLKSRC_MASK_PERIL1             , .val = 0x01110111, },
  48         { .reg = EXYNOS4_CLKSRC_MASK_DMC                , .val = 0x00010000, },
  49 };
  50
  51 static struct sleep_save exynos4210_set_clksrc[] = {
  52         { .reg = EXYNOS4210_CLKSRC_MASK_LCD1            , .val = 0x00001111, },
  53 };
  54
  55 static struct sleep_save exynos4_epll_save[] = {
  56         SAVE_ITEM(EXYNOS4_EPLL_CON0),
  57         SAVE_ITEM(EXYNOS4_EPLL_CON1),
  58 };
  59
  60 static struct sleep_save exynos4_vpll_save[] = {
  61         SAVE_ITEM(EXYNOS4_VPLL_CON0),
  62         SAVE_ITEM(EXYNOS4_VPLL_CON1),
  63 };
  64
  65 static struct sleep_save exynos_core_save[] = {
  66         /* SROM side */
  67         SAVE_ITEM(S5P_SROM_BW),
  68         SAVE_ITEM(S5P_SROM_BC0),
  69         SAVE_ITEM(S5P_SROM_BC1),
  70         SAVE_ITEM(S5P_SROM_BC2),
  71         SAVE_ITEM(S5P_SROM_BC3),
  72 };
  73
  74
  75 /* For Cortex-A9 Diagnostic and Power control register */
  76 static unsigned int save_arm_register[2];
  77
  78 static int exynos_cpu_suspend(unsigned long arg)
  79 {
  80 #ifdef CONFIG_CACHE_L2X0
  81         outer_flush_all();
  82 #endif
  83
  84         if (soc_is_exynos5250())
  85                 flush_cache_all();
  86
  87         /* issue the standby signal into the pm unit. */
  88         cpu_do_idle();
  89
  90         /* we should never get past here */
  91         panic("sleep resumed to originator?");
  92 }
  93
  94 static void exynos_pm_prepare(void)
  95 {
  96         unsigned int tmp;
  97
  98         s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
  99
 100         if (!soc_is_exynos5250()) {
 101                 s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
 102                 s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
 103         } else {
 104                 /* Disable USE_RETENTION of JPEG_MEM_OPTION */
 105                 tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
 106                 tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
 107                 __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
 108         }
 109
 110         /* Set value of power down register for sleep mode */
 111
 112         exynos_sys_powerdown_conf(SYS_SLEEP);
 113         __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
 114
 115         /* ensure at least INFORM0 has the resume address */
 116
 117         __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
 118
 119         /* Before enter central sequence mode, clock src register have to set */
 120
 121         if (!soc_is_exynos5250())
 122                 s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
 123
 124         if (soc_is_exynos4210())
 125                 s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
 126
 127 }
 128
 129 static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
 130 {
 131         pm_cpu_prep = exynos_pm_prepare;
 132         pm_cpu_sleep = exynos_cpu_suspend;
 133
 134         return 0;
 135 }
 136
 137 static unsigned long pll_base_rate;
 138
 139 static void exynos4_restore_pll(void)
 140 {
 141         unsigned long pll_con, locktime, lockcnt;
 142         unsigned long pll_in_rate;
 143         unsigned int p_div, epll_wait = 0, vpll_wait = 0;
 144
 145         if (pll_base_rate == 0)
 146                 return;
 147
 148         pll_in_rate = pll_base_rate;
 149
 150         /* EPLL */
 151         pll_con = exynos4_epll_save[0].val;
 152
 153         if (pll_con & (1 << 31)) {
 154                 pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
 155                 p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
 156
 157                 pll_in_rate /= 1000000;
 158
 159                 locktime = (3000 / pll_in_rate) * p_div;
 160                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 161
 162                 __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
 163
 164                 s3c_pm_do_restore_core(exynos4_epll_save,
 165                                         ARRAY_SIZE(exynos4_epll_save));
 166                 epll_wait = 1;
 167         }
 168
 169         pll_in_rate = pll_base_rate;
 170
 171         /* VPLL */
 172         pll_con = exynos4_vpll_save[0].val;
 173
 174         if (pll_con & (1 << 31)) {
 175                 pll_in_rate /= 1000000;
 176                 /* 750us */
 177                 locktime = 750;
 178                 lockcnt = locktime * 10000 / (10000 / pll_in_rate);
 179
 180                 __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
 181
 182                 s3c_pm_do_restore_core(exynos4_vpll_save,
 183                                         ARRAY_SIZE(exynos4_vpll_save));
 184                 vpll_wait = 1;
 185         }
 186
 187         /* Wait PLL locking */
 188
 189         do {
 190                 if (epll_wait) {
 191                         pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
 192                         if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
 193                                 epll_wait = 0;
 194                 }
 195
 196                 if (vpll_wait) {
 197                         pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
 198                         if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
 199                                 vpll_wait = 0;
 200                 }
 201         } while (epll_wait || vpll_wait);
 202 }
 203
 204 static struct subsys_interface exynos_pm_interface = {
 205         .name           = "exynos_pm",
 206         .subsys         = &exynos_subsys,
 207         .add_dev        = exynos_pm_add,
 208 };
 209
 210 static __init int exynos_pm_drvinit(void)
 211 {
 212         struct clk *pll_base;
 213         unsigned int tmp;
 214
 215         s3c_pm_init();
 216
 217         /* All wakeup disable */
 218
 219         tmp = __raw_readl(S5P_WAKEUP_MASK);
 220         tmp |= ((0xFF << 8) | (0x1F << 1));
 221         __raw_writel(tmp, S5P_WAKEUP_MASK);
 222
 223         if (!soc_is_exynos5250()) {
 224                 pll_base = clk_get(NULL, "xtal");
 225
 226                 if (!IS_ERR(pll_base)) {
 227                         pll_base_rate = clk_get_rate(pll_base);
 228                         clk_put(pll_base);
 229                 }
 230         }
 231
 232         return subsys_interface_register(&exynos_pm_interface);
 233 }
 234 arch_initcall(exynos_pm_drvinit);
 235
 236 static int exynos_pm_suspend(void)
 237 {
 238         unsigned long tmp;
 239
 240         /* Setting Central Sequence Register for power down mode */
 241
 242         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 243         tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 244         __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 245
 246         /* Setting SEQ_OPTION register */
 247
 248         tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
 249         __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
 250
 251         if (!soc_is_exynos5250()) {
 252                 /* Save Power control register */
 253                 asm ("mrc p15, 0, %0, c15, c0, 0"
 254                      : "=r" (tmp) : : "cc");
 255                 save_arm_register[0] = tmp;
 256
 257                 /* Save Diagnostic register */
 258                 asm ("mrc p15, 0, %0, c15, c0, 1"
 259                      : "=r" (tmp) : : "cc");
 260                 save_arm_register[1] = tmp;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static void exynos_pm_resume(void)
 267 {
 268         unsigned long tmp;
 269
 270         /*
 271          * If PMU failed while entering sleep mode, WFI will be
 272          * ignored by PMU and then exiting cpu_do_idle().
 273          * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
 274          * in this situation.
 275          */
 276         tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
 277         if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
 278                 tmp |= S5P_CENTRAL_LOWPWR_CFG;
 279                 __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 280                 /* No need to perform below restore code */
 281                 goto early_wakeup;
 282         }
 283         if (!soc_is_exynos5250()) {
 284                 /* Restore Power control register */
 285                 tmp = save_arm_register[0];
 286                 asm volatile ("mcr p15, 0, %0, c15, c0, 0"
 287                               : : "r" (tmp)
 288                               : "cc");
 289
 290                 /* Restore Diagnostic register */
 291                 tmp = save_arm_register[1];
 292                 asm volatile ("mcr p15, 0, %0, c15, c0, 1"
 293                               : : "r" (tmp)
 294                               : "cc");
 295         }
 296
 297         /* For release retention */
 298
 299         __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
 300         __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
 301         __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
 302         __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
 303         __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
 304         __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
 305         __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
 306
 307         s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
 308
 309         if (!soc_is_exynos5250()) {
 310                 exynos4_restore_pll();
 311
 312 #ifdef CONFIG_SMP
 313                 scu_enable(S5P_VA_SCU);
 314 #endif
 315         }
 316
 317 early_wakeup:
 318
 319         /* Clear SLEEP mode set in INFORM1 */
 320         __raw_writel(0x0, S5P_INFORM1);
 321
 322         return;
 323 }
 324
 325 static struct syscore_ops exynos_pm_syscore_ops = {
 326         .suspend        = exynos_pm_suspend,
 327         .resume         = exynos_pm_resume,
 328 };
 329
 330 static __init int exynos_pm_syscore_init(void)
 331 {
 332         register_syscore_ops(&exynos_pm_syscore_ops);
 333         return 0;
 334 }
 335 arch_initcall(exynos_pm_syscore_init);