arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_fdt.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/export.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/of_address.h>
  26
  27 #include <asm/proc-fns.h>
  28 #include <asm/exception.h>
  29 #include <asm/hardware/cache-l2x0.h>
  30 #include <asm/hardware/gic.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33 #include <asm/cacheflush.h>
  34
  35 #include <mach/regs-irq.h>
  36 #include <mach/regs-pmu.h>
  37 #include <mach/regs-gpio.h>
  38 #include <mach/pmu.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/clock.h>
  42 #include <plat/devs.h>
  43 #include <plat/pm.h>
  44 #include <plat/sdhci.h>
  45 #include <plat/gpio-cfg.h>
  46 #include <plat/adc-core.h>
  47 #include <plat/fb-core.h>
  48 #include <plat/fimc-core.h>
  49 #include <plat/iic-core.h>
  50 #include <plat/tv-core.h>
  51 #include <plat/spi-core.h>
  52 #include <plat/regs-serial.h>
  53
  54 #include "common.h"
  55 #define L2_AUX_VAL 0x7C470001
  56 #define L2_AUX_MASK 0xC200ffff
  57
  58 static const char name_exynos4210[] = "EXYNOS4210";
  59 static const char name_exynos4212[] = "EXYNOS4212";
  60 static const char name_exynos4412[] = "EXYNOS4412";
  61 static const char name_exynos5250[] = "EXYNOS5250";
  62 static const char name_exynos5440[] = "EXYNOS5440";
  63
  64 static void exynos4_map_io(void);
  65 static void exynos5_map_io(void);
  66 static void exynos5440_map_io(void);
  67 static void exynos4_init_clocks(int xtal);
  68 static void exynos5_init_clocks(int xtal);
  69 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  70 static int exynos_init(void);
  71
  72 static struct cpu_table cpu_ids[] __initdata = {
  73         {
  74                 .idcode         = EXYNOS4210_CPU_ID,
  75                 .idmask         = EXYNOS4_CPU_MASK,
  76                 .map_io         = exynos4_map_io,
  77                 .init_clocks    = exynos4_init_clocks,
  78                 .init_uarts     = exynos4_init_uarts,
  79                 .init           = exynos_init,
  80                 .name           = name_exynos4210,
  81         }, {
  82                 .idcode         = EXYNOS4212_CPU_ID,
  83                 .idmask         = EXYNOS4_CPU_MASK,
  84                 .map_io         = exynos4_map_io,
  85                 .init_clocks    = exynos4_init_clocks,
  86                 .init_uarts     = exynos4_init_uarts,
  87                 .init           = exynos_init,
  88                 .name           = name_exynos4212,
  89         }, {
  90                 .idcode         = EXYNOS4412_CPU_ID,
  91                 .idmask         = EXYNOS4_CPU_MASK,
  92                 .map_io         = exynos4_map_io,
  93                 .init_clocks    = exynos4_init_clocks,
  94                 .init_uarts     = exynos4_init_uarts,
  95                 .init           = exynos_init,
  96                 .name           = name_exynos4412,
  97         }, {
  98                 .idcode         = EXYNOS5250_SOC_ID,
  99                 .idmask         = EXYNOS5_SOC_MASK,
 100                 .map_io         = exynos5_map_io,
 101                 .init_clocks    = exynos5_init_clocks,
 102                 .init           = exynos_init,
 103                 .name           = name_exynos5250,
 104         }, {
 105                 .idcode         = EXYNOS5440_SOC_ID,
 106                 .idmask         = EXYNOS5_SOC_MASK,
 107                 .map_io         = exynos5440_map_io,
 108                 .init           = exynos_init,
 109                 .name           = name_exynos5440,
 110         },
 111 };
 112
 113 /* Initial IO mappings */
 114
 115 static struct map_desc exynos_iodesc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 118                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 119                 .length         = SZ_4K,
 120                 .type           = MT_DEVICE,
 121         },
 122 };
 123
 124 #ifdef CONFIG_ARCH_EXYNOS5
 125 static struct map_desc exynos5440_iodesc[] __initdata = {
 126         {
 127                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 128                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 129                 .length         = SZ_4K,
 130                 .type           = MT_DEVICE,
 131         },
 132 };
 133 #endif
 134
 135 static struct map_desc exynos4_iodesc[] __initdata = {
 136         {
 137                 .virtual        = (unsigned long)S3C_VA_SYS,
 138                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 139                 .length         = SZ_64K,
 140                 .type           = MT_DEVICE,
 141         }, {
 142                 .virtual        = (unsigned long)S3C_VA_TIMER,
 143                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 144                 .length         = SZ_16K,
 145                 .type           = MT_DEVICE,
 146         }, {
 147                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 148                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 149                 .length         = SZ_4K,
 150                 .type           = MT_DEVICE,
 151         }, {
 152                 .virtual        = (unsigned long)S5P_VA_SROMC,
 153                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 154                 .length         = SZ_4K,
 155                 .type           = MT_DEVICE,
 156         }, {
 157                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 158                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 159                 .length         = SZ_4K,
 160                 .type           = MT_DEVICE,
 161         }, {
 162                 .virtual        = (unsigned long)S5P_VA_PMU,
 163                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 164                 .length         = SZ_64K,
 165                 .type           = MT_DEVICE,
 166         }, {
 167                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 168                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 169                 .length         = SZ_4K,
 170                 .type           = MT_DEVICE,
 171         }, {
 172                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 173                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 174                 .length         = SZ_64K,
 175                 .type           = MT_DEVICE,
 176         }, {
 177                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 178                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 179                 .length         = SZ_64K,
 180                 .type           = MT_DEVICE,
 181         }, {
 182                 .virtual        = (unsigned long)S3C_VA_UART,
 183                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 184                 .length         = SZ_512K,
 185                 .type           = MT_DEVICE,
 186         }, {
 187                 .virtual        = (unsigned long)S5P_VA_CMU,
 188                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 189                 .length         = SZ_128K,
 190                 .type           = MT_DEVICE,
 191         }, {
 192                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 193                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 194                 .length         = SZ_8K,
 195                 .type           = MT_DEVICE,
 196         }, {
 197                 .virtual        = (unsigned long)S5P_VA_L2CC,
 198                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 199                 .length         = SZ_4K,
 200                 .type           = MT_DEVICE,
 201         }, {
 202                 .virtual        = (unsigned long)S5P_VA_DMC0,
 203                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 204                 .length         = SZ_64K,
 205                 .type           = MT_DEVICE,
 206         }, {
 207                 .virtual        = (unsigned long)S5P_VA_DMC1,
 208                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 209                 .length         = SZ_64K,
 210                 .type           = MT_DEVICE,
 211         }, {
 212                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 213                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 214                 .length         = SZ_4K,
 215                 .type           = MT_DEVICE,
 216         },
 217 };
 218
 219 static struct map_desc exynos4_iodesc0[] __initdata = {
 220         {
 221                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 222                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 223                 .length         = SZ_4K,
 224                 .type           = MT_DEVICE,
 225         },
 226 };
 227
 228 static struct map_desc exynos4_iodesc1[] __initdata = {
 229         {
 230                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 231                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 232                 .length         = SZ_4K,
 233                 .type           = MT_DEVICE,
 234         },
 235 };
 236
 237 static struct map_desc exynos5_iodesc[] __initdata = {
 238         {
 239                 .virtual        = (unsigned long)S3C_VA_SYS,
 240                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 241                 .length         = SZ_64K,
 242                 .type           = MT_DEVICE,
 243         }, {
 244                 .virtual        = (unsigned long)S3C_VA_TIMER,
 245                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 246                 .length         = SZ_16K,
 247                 .type           = MT_DEVICE,
 248         }, {
 249                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 250                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 251                 .length         = SZ_4K,
 252                 .type           = MT_DEVICE,
 253         }, {
 254                 .virtual        = (unsigned long)S5P_VA_SROMC,
 255                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 256                 .length         = SZ_4K,
 257                 .type           = MT_DEVICE,
 258         }, {
 259                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 260                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 261                 .length         = SZ_4K,
 262                 .type           = MT_DEVICE,
 263         }, {
 264                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 265                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 266                 .length         = SZ_4K,
 267                 .type           = MT_DEVICE,
 268         }, {
 269                 .virtual        = (unsigned long)S5P_VA_CMU,
 270                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 271                 .length         = 144 * SZ_1K,
 272                 .type           = MT_DEVICE,
 273         }, {
 274                 .virtual        = (unsigned long)S5P_VA_PMU,
 275                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 276                 .length         = SZ_64K,
 277                 .type           = MT_DEVICE,
 278         }, {
 279                 .virtual        = (unsigned long)S3C_VA_UART,
 280                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 281                 .length         = SZ_512K,
 282                 .type           = MT_DEVICE,
 283         },
 284 };
 285
 286 static struct map_desc exynos5440_iodesc0[] __initdata = {
 287         {
 288                 .virtual        = (unsigned long)S3C_VA_UART,
 289                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 290                 .length         = SZ_512K,
 291                 .type           = MT_DEVICE,
 292         },
 293 };
 294
 295 void exynos4_restart(char mode, const char *cmd)
 296 {
 297         __raw_writel(0x1, S5P_SWRESET);
 298 }
 299
 300 void exynos5_restart(char mode, const char *cmd)
 301 {
 302         u32 val;
 303         void __iomem *addr;
 304
 305         if (of_machine_is_compatible("samsung,exynos5250")) {
 306                 val = 0x1;
 307                 addr = EXYNOS_SWRESET;
 308         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 309                 val = (0x10 << 20) | (0x1 << 16);
 310                 addr = EXYNOS5440_SWRESET;
 311         } else {
 312                 pr_err("%s: cannot support non-DT\n", __func__);
 313                 return;
 314         }
 315
 316         __raw_writel(val, addr);
 317 }
 318
 319 void __init exynos_init_late(void)
 320 {
 321         if (of_machine_is_compatible("samsung,exynos5440"))
 322                 /* to be supported later */
 323                 return;
 324
 325         exynos_pm_late_initcall();
 326 }
 327
 328 /*
 329  * exynos_map_io
 330  *
 331  * register the standard cpu IO areas
 332  */
 333
 334 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 335 {
 336         struct map_desc *iodesc = exynos_iodesc;
 337         int iodesc_sz = ARRAY_SIZE(exynos_iodesc);
 338 #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5)
 339         unsigned long root = of_get_flat_dt_root();
 340
 341         /* initialize the io descriptors we need for initialization */
 342         if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) {
 343                 iodesc = exynos5440_iodesc;
 344                 iodesc_sz = ARRAY_SIZE(exynos5440_iodesc);
 345         }
 346 #endif
 347
 348         iotable_init(iodesc, iodesc_sz);
 349
 350         if (mach_desc)
 351                 iotable_init(mach_desc, size);
 352
 353         /* detect cpu id and rev. */
 354         s5p_init_cpu(S5P_VA_CHIPID);
 355
 356         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 357 }
 358
 359 static void __init exynos4_map_io(void)
 360 {
 361         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 362
 363         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 364                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 365         else
 366                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 367
 368         /* initialize device information early */
 369         exynos4_default_sdhci0();
 370         exynos4_default_sdhci1();
 371         exynos4_default_sdhci2();
 372         exynos4_default_sdhci3();
 373
 374         s3c_adc_setname("samsung-adc-v3");
 375
 376         s3c_fimc_setname(0, "exynos4-fimc");
 377         s3c_fimc_setname(1, "exynos4-fimc");
 378         s3c_fimc_setname(2, "exynos4-fimc");
 379         s3c_fimc_setname(3, "exynos4-fimc");
 380
 381         s3c_sdhci_setname(0, "exynos4-sdhci");
 382         s3c_sdhci_setname(1, "exynos4-sdhci");
 383         s3c_sdhci_setname(2, "exynos4-sdhci");
 384         s3c_sdhci_setname(3, "exynos4-sdhci");
 385
 386         /* The I2C bus controllers are directly compatible with s3c2440 */
 387         s3c_i2c0_setname("s3c2440-i2c");
 388         s3c_i2c1_setname("s3c2440-i2c");
 389         s3c_i2c2_setname("s3c2440-i2c");
 390
 391         s5p_fb_setname(0, "exynos4-fb");
 392         s5p_hdmi_setname("exynos4-hdmi");
 393
 394         s3c64xx_spi_setname("exynos4210-spi");
 395 }
 396
 397 static void __init exynos5_map_io(void)
 398 {
 399         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 400 }
 401
 402 static void __init exynos4_init_clocks(int xtal)
 403 {
 404         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 405
 406         s3c24xx_register_baseclocks(xtal);
 407         s5p_register_clocks(xtal);
 408
 409         if (soc_is_exynos4210())
 410                 exynos4210_register_clocks();
 411         else if (soc_is_exynos4212() || soc_is_exynos4412())
 412                 exynos4212_register_clocks();
 413
 414         exynos4_register_clocks();
 415         exynos4_setup_clocks();
 416 }
 417
 418 static void __init exynos5440_map_io(void)
 419 {
 420         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 421 }
 422
 423 static void __init exynos5_init_clocks(int xtal)
 424 {
 425         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 426
 427         s3c24xx_register_baseclocks(xtal);
 428         s5p_register_clocks(xtal);
 429
 430         exynos5_register_clocks();
 431         exynos5_setup_clocks();
 432 }
 433
 434 #define COMBINER_ENABLE_SET     0x0
 435 #define COMBINER_ENABLE_CLEAR   0x4
 436 #define COMBINER_INT_STATUS     0xC
 437
 438 static DEFINE_SPINLOCK(irq_controller_lock);
 439
 440 struct combiner_chip_data {
 441         unsigned int irq_offset;
 442         unsigned int irq_mask;
 443         void __iomem *base;
 444 };
 445
 446 static struct irq_domain *combiner_irq_domain;
 447 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 448
 449 static inline void __iomem *combiner_base(struct irq_data *data)
 450 {
 451         struct combiner_chip_data *combiner_data =
 452                 irq_data_get_irq_chip_data(data);
 453
 454         return combiner_data->base;
 455 }
 456
 457 static void combiner_mask_irq(struct irq_data *data)
 458 {
 459         u32 mask = 1 << (data->hwirq % 32);
 460
 461         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 462 }
 463
 464 static void combiner_unmask_irq(struct irq_data *data)
 465 {
 466         u32 mask = 1 << (data->hwirq % 32);
 467
 468         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 469 }
 470
 471 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 472 {
 473         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 474         struct irq_chip *chip = irq_get_chip(irq);
 475         unsigned int cascade_irq, combiner_irq;
 476         unsigned long status;
 477
 478         chained_irq_enter(chip, desc);
 479
 480         spin_lock(&irq_controller_lock);
 481         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 482         spin_unlock(&irq_controller_lock);
 483         status &= chip_data->irq_mask;
 484
 485         if (status == 0)
 486                 goto out;
 487
 488         combiner_irq = __ffs(status);
 489
 490         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 491         if (unlikely(cascade_irq >= NR_IRQS))
 492                 do_bad_IRQ(cascade_irq, desc);
 493         else
 494                 generic_handle_irq(cascade_irq);
 495
 496  out:
 497         chained_irq_exit(chip, desc);
 498 }
 499
 500 static struct irq_chip combiner_chip = {
 501         .name           = "COMBINER",
 502         .irq_mask       = combiner_mask_irq,
 503         .irq_unmask     = combiner_unmask_irq,
 504 };
 505
 506 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 507 {
 508         unsigned int max_nr;
 509
 510         if (soc_is_exynos5250())
 511                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 512         else
 513                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 514
 515         if (combiner_nr >= max_nr)
 516                 BUG();
 517         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 518                 BUG();
 519         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 520 }
 521
 522 static void __init combiner_init_one(unsigned int combiner_nr,
 523                                      void __iomem *base)
 524 {
 525         combiner_data[combiner_nr].base = base;
 526         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 527                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 528         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 529
 530         /* Disable all interrupts */
 531         __raw_writel(combiner_data[combiner_nr].irq_mask,
 532                      base + COMBINER_ENABLE_CLEAR);
 533 }
 534
 535 #ifdef CONFIG_OF
 536 static int combiner_irq_domain_xlate(struct irq_domain *d,
 537                                      struct device_node *controller,
 538                                      const u32 *intspec, unsigned int intsize,
 539                                      unsigned long *out_hwirq,
 540                                      unsigned int *out_type)
 541 {
 542         if (d->of_node != controller)
 543                 return -EINVAL;
 544
 545         if (intsize < 2)
 546                 return -EINVAL;
 547
 548         *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
 549         *out_type = 0;
 550
 551         return 0;
 552 }
 553 #else
 554 static int combiner_irq_domain_xlate(struct irq_domain *d,
 555                                      struct device_node *controller,
 556                                      const u32 *intspec, unsigned int intsize,
 557                                      unsigned long *out_hwirq,
 558                                      unsigned int *out_type)
 559 {
 560         return -EINVAL;
 561 }
 562 #endif
 563
 564 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 565                                    irq_hw_number_t hw)
 566 {
 567         irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
 568         irq_set_chip_data(irq, &combiner_data[hw >> 3]);
 569         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 570
 571         return 0;
 572 }
 573
 574 static struct irq_domain_ops combiner_irq_domain_ops = {
 575         .xlate  = combiner_irq_domain_xlate,
 576         .map    = combiner_irq_domain_map,
 577 };
 578
 579 static void __init combiner_init(void __iomem *combiner_base,
 580                                  struct device_node *np)
 581 {
 582         int i, irq, irq_base;
 583         unsigned int max_nr, nr_irq;
 584
 585         if (np) {
 586                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 587                         pr_warning("%s: number of combiners not specified, "
 588                                 "setting default as %d.\n",
 589                                 __func__, EXYNOS4_MAX_COMBINER_NR);
 590                         max_nr = EXYNOS4_MAX_COMBINER_NR;
 591                 }
 592         } else {
 593                 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 594                                                 EXYNOS4_MAX_COMBINER_NR;
 595         }
 596         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 597
 598         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
 599         if (IS_ERR_VALUE(irq_base)) {
 600                 irq_base = COMBINER_IRQ(0, 0);
 601                 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
 602         }
 603
 604         combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
 605                                 &combiner_irq_domain_ops, &combiner_data);
 606         if (WARN_ON(!combiner_irq_domain)) {
 607                 pr_warning("%s: irq domain init failed\n", __func__);
 608                 return;
 609         }
 610
 611         for (i = 0; i < max_nr; i++) {
 612                 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 613                 irq = IRQ_SPI(i);
 614 #ifdef CONFIG_OF
 615                 if (np)
 616                         irq = irq_of_parse_and_map(np, i);
 617 #endif
 618                 combiner_cascade_irq(i, irq);
 619         }
 620 }
 621
 622 #ifdef CONFIG_OF
 623 static int __init combiner_of_init(struct device_node *np,
 624                                    struct device_node *parent)
 625 {
 626         void __iomem *combiner_base;
 627
 628         combiner_base = of_iomap(np, 0);
 629         if (!combiner_base) {
 630                 pr_err("%s: failed to map combiner registers\n", __func__);
 631                 return -ENXIO;
 632         }
 633
 634         combiner_init(combiner_base, np);
 635
 636         return 0;
 637 }
 638
 639 static const struct of_device_id exynos_dt_irq_match[] = {
 640         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 641         { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
 642         { .compatible = "samsung,exynos4210-combiner",
 643                         .data = combiner_of_init, },
 644         {},
 645 };
 646 #endif
 647
 648 void __init exynos4_init_irq(void)
 649 {
 650         unsigned int gic_bank_offset;
 651
 652         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 653
 654         if (!of_have_populated_dt())
 655                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 656 #ifdef CONFIG_OF
 657         else
 658                 of_irq_init(exynos_dt_irq_match);
 659 #endif
 660
 661         if (!of_have_populated_dt())
 662                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 663
 664         /*
 665          * The parameters of s5p_init_irq() are for VIC init.
 666          * Theses parameters should be NULL and 0 because EXYNOS4
 667          * uses GIC instead of VIC.
 668          */
 669         s5p_init_irq(NULL, 0);
 670 }
 671
 672 void __init exynos5_init_irq(void)
 673 {
 674 #ifdef CONFIG_OF
 675         of_irq_init(exynos_dt_irq_match);
 676 #endif
 677         /*
 678          * The parameters of s5p_init_irq() are for VIC init.
 679          * Theses parameters should be NULL and 0 because EXYNOS4
 680          * uses GIC instead of VIC.
 681          */
 682         s5p_init_irq(NULL, 0);
 683
 684         gic_arch_extn.irq_set_wake = s3c_irq_wake;
 685 }
 686
 687 struct bus_type exynos_subsys = {
 688         .name           = "exynos-core",
 689         .dev_name       = "exynos-core",
 690 };
 691
 692 static struct device exynos4_dev = {
 693         .bus    = &exynos_subsys,
 694 };
 695
 696 static int __init exynos_core_init(void)
 697 {
 698         return subsys_system_register(&exynos_subsys, NULL);
 699 }
 700 core_initcall(exynos_core_init);
 701
 702 #ifdef CONFIG_CACHE_L2X0
 703 static int __init exynos4_l2x0_cache_init(void)
 704 {
 705         int ret;
 706
 707         if (soc_is_exynos5250() || soc_is_exynos5440())
 708                 return 0;
 709
 710         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 711         if (!ret) {
 712                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 713                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 714                 return 0;
 715         }
 716
 717         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 718                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 719                 /* TAG, Data Latency Control: 2 cycles */
 720                 l2x0_saved_regs.tag_latency = 0x110;
 721
 722                 if (soc_is_exynos4212() || soc_is_exynos4412())
 723                         l2x0_saved_regs.data_latency = 0x120;
 724                 else
 725                         l2x0_saved_regs.data_latency = 0x110;
 726
 727                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 728                 l2x0_saved_regs.pwr_ctrl =
 729                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 730
 731                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 732
 733                 __raw_writel(l2x0_saved_regs.tag_latency,
 734                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 735                 __raw_writel(l2x0_saved_regs.data_latency,
 736                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 737
 738                 /* L2X0 Prefetch Control */
 739                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 740                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 741
 742                 /* L2X0 Power Control */
 743                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 744                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 745
 746                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 747                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 748         }
 749
 750         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 751         return 0;
 752 }
 753 early_initcall(exynos4_l2x0_cache_init);
 754 #endif
 755
 756 static int __init exynos_init(void)
 757 {
 758         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 759
 760         return device_register(&exynos4_dev);
 761 }
 762
 763 /* uart registration process */
 764
 765 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 766 {
 767         struct s3c2410_uartcfg *tcfg = cfg;
 768         u32 ucnt;
 769
 770         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 771                 tcfg->has_fracval = 1;
 772
 773         s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 774 }
 775
 776 static void __iomem *exynos_eint_base;
 777
 778 static DEFINE_SPINLOCK(eint_lock);
 779
 780 static unsigned int eint0_15_data[16];
 781
 782 static inline int exynos4_irq_to_gpio(unsigned int irq)
 783 {
 784         if (irq < IRQ_EINT(0))
 785                 return -EINVAL;
 786
 787         irq -= IRQ_EINT(0);
 788         if (irq < 8)
 789                 return EXYNOS4_GPX0(irq);
 790
 791         irq -= 8;
 792         if (irq < 8)
 793                 return EXYNOS4_GPX1(irq);
 794
 795         irq -= 8;
 796         if (irq < 8)
 797                 return EXYNOS4_GPX2(irq);
 798
 799         irq -= 8;
 800         if (irq < 8)
 801                 return EXYNOS4_GPX3(irq);
 802
 803         return -EINVAL;
 804 }
 805
 806 static inline int exynos5_irq_to_gpio(unsigned int irq)
 807 {
 808         if (irq < IRQ_EINT(0))
 809                 return -EINVAL;
 810
 811         irq -= IRQ_EINT(0);
 812         if (irq < 8)
 813                 return EXYNOS5_GPX0(irq);
 814
 815         irq -= 8;
 816         if (irq < 8)
 817                 return EXYNOS5_GPX1(irq);
 818
 819         irq -= 8;
 820         if (irq < 8)
 821                 return EXYNOS5_GPX2(irq);
 822
 823         irq -= 8;
 824         if (irq < 8)
 825                 return EXYNOS5_GPX3(irq);
 826
 827         return -EINVAL;
 828 }
 829
 830 static unsigned int exynos4_eint0_15_src_int[16] = {
 831         EXYNOS4_IRQ_EINT0,
 832         EXYNOS4_IRQ_EINT1,
 833         EXYNOS4_IRQ_EINT2,
 834         EXYNOS4_IRQ_EINT3,
 835         EXYNOS4_IRQ_EINT4,
 836         EXYNOS4_IRQ_EINT5,
 837         EXYNOS4_IRQ_EINT6,
 838         EXYNOS4_IRQ_EINT7,
 839         EXYNOS4_IRQ_EINT8,
 840         EXYNOS4_IRQ_EINT9,
 841         EXYNOS4_IRQ_EINT10,
 842         EXYNOS4_IRQ_EINT11,
 843         EXYNOS4_IRQ_EINT12,
 844         EXYNOS4_IRQ_EINT13,
 845         EXYNOS4_IRQ_EINT14,
 846         EXYNOS4_IRQ_EINT15,
 847 };
 848
 849 static unsigned int exynos5_eint0_15_src_int[16] = {
 850         EXYNOS5_IRQ_EINT0,
 851         EXYNOS5_IRQ_EINT1,
 852         EXYNOS5_IRQ_EINT2,
 853         EXYNOS5_IRQ_EINT3,
 854         EXYNOS5_IRQ_EINT4,
 855         EXYNOS5_IRQ_EINT5,
 856         EXYNOS5_IRQ_EINT6,
 857         EXYNOS5_IRQ_EINT7,
 858         EXYNOS5_IRQ_EINT8,
 859         EXYNOS5_IRQ_EINT9,
 860         EXYNOS5_IRQ_EINT10,
 861         EXYNOS5_IRQ_EINT11,
 862         EXYNOS5_IRQ_EINT12,
 863         EXYNOS5_IRQ_EINT13,
 864         EXYNOS5_IRQ_EINT14,
 865         EXYNOS5_IRQ_EINT15,
 866 };
 867 static inline void exynos_irq_eint_mask(struct irq_data *data)
 868 {
 869         u32 mask;
 870
 871         spin_lock(&eint_lock);
 872         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 873         mask |= EINT_OFFSET_BIT(data->irq);
 874         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 875         spin_unlock(&eint_lock);
 876 }
 877
 878 static void exynos_irq_eint_unmask(struct irq_data *data)
 879 {
 880         u32 mask;
 881
 882         spin_lock(&eint_lock);
 883         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 884         mask &= ~(EINT_OFFSET_BIT(data->irq));
 885         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 886         spin_unlock(&eint_lock);
 887 }
 888
 889 static inline void exynos_irq_eint_ack(struct irq_data *data)
 890 {
 891         __raw_writel(EINT_OFFSET_BIT(data->irq),
 892                      EINT_PEND(exynos_eint_base, data->irq));
 893 }
 894
 895 static void exynos_irq_eint_maskack(struct irq_data *data)
 896 {
 897         exynos_irq_eint_mask(data);
 898         exynos_irq_eint_ack(data);
 899 }
 900
 901 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 902 {
 903         int offs = EINT_OFFSET(data->irq);
 904         int shift;
 905         u32 ctrl, mask;
 906         u32 newvalue = 0;
 907
 908         switch (type) {
 909         case IRQ_TYPE_EDGE_RISING:
 910                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 911                 break;
 912
 913         case IRQ_TYPE_EDGE_FALLING:
 914                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 915                 break;
 916
 917         case IRQ_TYPE_EDGE_BOTH:
 918                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 919                 break;
 920
 921         case IRQ_TYPE_LEVEL_LOW:
 922                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 923                 break;
 924
 925         case IRQ_TYPE_LEVEL_HIGH:
 926                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 927                 break;
 928
 929         default:
 930                 printk(KERN_ERR "No such irq type %d", type);
 931                 return -EINVAL;
 932         }
 933
 934         shift = (offs & 0x7) * 4;
 935         mask = 0x7 << shift;
 936
 937         spin_lock(&eint_lock);
 938         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 939         ctrl &= ~mask;
 940         ctrl |= newvalue << shift;
 941         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 942         spin_unlock(&eint_lock);
 943
 944         if (soc_is_exynos5250())
 945                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 946         else
 947                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 948
 949         return 0;
 950 }
 951
 952 static struct irq_chip exynos_irq_eint = {
 953         .name           = "exynos-eint",
 954         .irq_mask       = exynos_irq_eint_mask,
 955         .irq_unmask     = exynos_irq_eint_unmask,
 956         .irq_mask_ack   = exynos_irq_eint_maskack,
 957         .irq_ack        = exynos_irq_eint_ack,
 958         .irq_set_type   = exynos_irq_eint_set_type,
 959 #ifdef CONFIG_PM
 960         .irq_set_wake   = s3c_irqext_wake,
 961 #endif
 962 };
 963
 964 /*
 965  * exynos4_irq_demux_eint
 966  *
 967  * This function demuxes the IRQ from from EINTs 16 to 31.
 968  * It is designed to be inlined into the specific handler
 969  * s5p_irq_demux_eintX_Y.
 970  *
 971  * Each EINT pend/mask registers handle eight of them.
 972  */
 973 static inline void exynos_irq_demux_eint(unsigned int start)
 974 {
 975         unsigned int irq;
 976
 977         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 978         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 979
 980         status &= ~mask;
 981         status &= 0xff;
 982
 983         while (status) {
 984                 irq = fls(status) - 1;
 985                 generic_handle_irq(irq + start);
 986                 status &= ~(1 << irq);
 987         }
 988 }
 989
 990 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 991 {
 992         struct irq_chip *chip = irq_get_chip(irq);
 993         chained_irq_enter(chip, desc);
 994         exynos_irq_demux_eint(IRQ_EINT(16));
 995         exynos_irq_demux_eint(IRQ_EINT(24));
 996         chained_irq_exit(chip, desc);
 997 }
 998
 999 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
1000 {
1001         u32 *irq_data = irq_get_handler_data(irq);
1002         struct irq_chip *chip = irq_get_chip(irq);
1003
1004         chained_irq_enter(chip, desc);
1005         generic_handle_irq(*irq_data);
1006         chained_irq_exit(chip, desc);
1007 }
1008
1009 static int __init exynos_init_irq_eint(void)
1010 {
1011         int irq;
1012
1013 #ifdef CONFIG_PINCTRL_SAMSUNG
1014         /*
1015          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
1016          * functionality along with support for external gpio and wakeup
1017          * interrupts. If the samsung pinctrl driver is enabled and includes
1018          * the wakeup interrupt support, then the setting up external wakeup
1019          * interrupts here can be skipped. This check here is temporary to
1020          * allow exynos4 platforms that do not use Samsung pinctrl driver to
1021          * co-exist with platforms that do. When all of the Samsung Exynos4
1022          * platforms switch over to using the pinctrl driver, the wakeup
1023          * interrupt support code here can be completely removed.
1024          */
1025         static const struct of_device_id exynos_pinctrl_ids[] = {
1026                 { .compatible = "samsung,pinctrl-exynos4210", },
1027                 { .compatible = "samsung,pinctrl-exynos4x12", },
1028         };
1029         struct device_node *pctrl_np, *wkup_np;
1030         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1031
1032         for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
1033                 if (of_device_is_available(pctrl_np)) {
1034                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
1035                                                         wkup_compat);
1036                         if (wkup_np)
1037                                 return -ENODEV;
1038                 }
1039         }
1040 #endif
1041         if (soc_is_exynos5440())
1042                 return 0;
1043
1044         if (soc_is_exynos5250())
1045                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1046         else
1047                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1048
1049         if (exynos_eint_base == NULL) {
1050                 pr_err("unable to ioremap for EINT base address\n");
1051                 return -ENOMEM;
1052         }
1053
1054         for (irq = 0 ; irq <= 31 ; irq++) {
1055                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
1056                                          handle_level_irq);
1057                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1058         }
1059
1060         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
1061
1062         for (irq = 0 ; irq <= 15 ; irq++) {
1063                 eint0_15_data[irq] = IRQ_EINT(irq);
1064
1065                 if (soc_is_exynos5250()) {
1066                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1067                                              &eint0_15_data[irq]);
1068                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1069                                                 exynos_irq_eint0_15);
1070                 } else {
1071                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1072                                              &eint0_15_data[irq]);
1073                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1074                                                 exynos_irq_eint0_15);
1075                 }
1076         }
1077
1078         return 0;
1079 }
1080 arch_initcall(exynos_init_irq_eint);