arch/arm/boot/dts/tegra30.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra30";
   5         interrupt-parent = <&intc>;
   6
   7         host1x {
   8                 compatible = "nvidia,tegra30-host1x", "simple-bus";
   9                 reg = <0x50000000 0x00024000>;
  10                 interrupts = <0 65 0x04   /* mpcore syncpt */
  11                               0 67 0x04>; /* mpcore general */
  12
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15
  16                 ranges = <0x54000000 0x54000000 0x04000000>;
  17
  18                 mpe {
  19                         compatible = "nvidia,tegra30-mpe";
  20                         reg = <0x54040000 0x00040000>;
  21                         interrupts = <0 68 0x04>;
  22                 };
  23
  24                 vi {
  25                         compatible = "nvidia,tegra30-vi";
  26                         reg = <0x54080000 0x00040000>;
  27                         interrupts = <0 69 0x04>;
  28                 };
  29
  30                 epp {
  31                         compatible = "nvidia,tegra30-epp";
  32                         reg = <0x540c0000 0x00040000>;
  33                         interrupts = <0 70 0x04>;
  34                 };
  35
  36                 isp {
  37                         compatible = "nvidia,tegra30-isp";
  38                         reg = <0x54100000 0x00040000>;
  39                         interrupts = <0 71 0x04>;
  40                 };
  41
  42                 gr2d {
  43                         compatible = "nvidia,tegra30-gr2d";
  44                         reg = <0x54140000 0x00040000>;
  45                         interrupts = <0 72 0x04>;
  46                 };
  47
  48                 gr3d {
  49                         compatible = "nvidia,tegra30-gr3d";
  50                         reg = <0x54180000 0x00040000>;
  51                 };
  52
  53                 dc@54200000 {
  54                         compatible = "nvidia,tegra30-dc";
  55                         reg = <0x54200000 0x00040000>;
  56                         interrupts = <0 73 0x04>;
  57
  58                         rgb {
  59                                 status = "disabled";
  60                         };
  61                 };
  62
  63                 dc@54240000 {
  64                         compatible = "nvidia,tegra30-dc";
  65                         reg = <0x54240000 0x00040000>;
  66                         interrupts = <0 74 0x04>;
  67
  68                         rgb {
  69                                 status = "disabled";
  70                         };
  71                 };
  72
  73                 hdmi {
  74                         compatible = "nvidia,tegra30-hdmi";
  75                         reg = <0x54280000 0x00040000>;
  76                         interrupts = <0 75 0x04>;
  77                         status = "disabled";
  78                 };
  79
  80                 tvo {
  81                         compatible = "nvidia,tegra30-tvo";
  82                         reg = <0x542c0000 0x00040000>;
  83                         interrupts = <0 76 0x04>;
  84                         status = "disabled";
  85                 };
  86
  87                 dsi {
  88                         compatible = "nvidia,tegra30-dsi";
  89                         reg = <0x54300000 0x00040000>;
  90                         status = "disabled";
  91                 };
  92         };
  93
  94         timer@50004600 {
  95                 compatible = "arm,cortex-a9-twd-timer";
  96                 reg = <0x50040600 0x20>;
  97                 interrupts = <1 13 0xf04>;
  98         };
  99
 100         cache-controller@50043000 {
 101                 compatible = "arm,pl310-cache";
 102                 reg = <0x50043000 0x1000>;
 103                 arm,data-latency = <6 6 2>;
 104                 arm,tag-latency = <5 5 2>;
 105                 cache-unified;
 106                 cache-level = <2>;
 107         };
 108
 109         intc: interrupt-controller {
 110                 compatible = "arm,cortex-a9-gic";
 111                 reg = <0x50041000 0x1000
 112                        0x50040100 0x0100>;
 113                 interrupt-controller;
 114                 #interrupt-cells = <3>;
 115         };
 116
 117         timer@60005000 {
 118                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 119                 reg = <0x60005000 0x400>;
 120                 interrupts = <0 0 0x04
 121                               0 1 0x04
 122                               0 41 0x04
 123                               0 42 0x04
 124                               0 121 0x04
 125                               0 122 0x04>;
 126         };
 127
 128         apbdma: dma {
 129                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 130                 reg = <0x6000a000 0x1400>;
 131                 interrupts = <0 104 0x04
 132                               0 105 0x04
 133                               0 106 0x04
 134                               0 107 0x04
 135                               0 108 0x04
 136                               0 109 0x04
 137                               0 110 0x04
 138                               0 111 0x04
 139                               0 112 0x04
 140                               0 113 0x04
 141                               0 114 0x04
 142                               0 115 0x04
 143                               0 116 0x04
 144                               0 117 0x04
 145                               0 118 0x04
 146                               0 119 0x04
 147                               0 128 0x04
 148                               0 129 0x04
 149                               0 130 0x04
 150                               0 131 0x04
 151                               0 132 0x04
 152                               0 133 0x04
 153                               0 134 0x04
 154                               0 135 0x04
 155                               0 136 0x04
 156                               0 137 0x04
 157                               0 138 0x04
 158                               0 139 0x04
 159                               0 140 0x04
 160                               0 141 0x04
 161                               0 142 0x04
 162                               0 143 0x04>;
 163         };
 164
 165         ahb: ahb {
 166                 compatible = "nvidia,tegra30-ahb";
 167                 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
 168         };
 169
 170         gpio: gpio {
 171                 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
 172                 reg = <0x6000d000 0x1000>;
 173                 interrupts = <0 32 0x04
 174                               0 33 0x04
 175                               0 34 0x04
 176                               0 35 0x04
 177                               0 55 0x04
 178                               0 87 0x04
 179                               0 89 0x04
 180                               0 125 0x04>;
 181                 #gpio-cells = <2>;
 182                 gpio-controller;
 183                 #interrupt-cells = <2>;
 184                 interrupt-controller;
 185         };
 186
 187         pinmux: pinmux {
 188                 compatible = "nvidia,tegra30-pinmux";
 189                 reg = <0x70000868 0xd4    /* Pad control registers */
 190                        0x70003000 0x3e4>; /* Mux registers */
 191         };
 192
 193         serial@70006000 {
 194                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 195                 reg = <0x70006000 0x40>;
 196                 reg-shift = <2>;
 197                 interrupts = <0 36 0x04>;
 198                 status = "disabled";
 199         };
 200
 201         serial@70006040 {
 202                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 203                 reg = <0x70006040 0x40>;
 204                 reg-shift = <2>;
 205                 interrupts = <0 37 0x04>;
 206                 status = "disabled";
 207         };
 208
 209         serial@70006200 {
 210                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 211                 reg = <0x70006200 0x100>;
 212                 reg-shift = <2>;
 213                 interrupts = <0 46 0x04>;
 214                 status = "disabled";
 215         };
 216
 217         serial@70006300 {
 218                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 219                 reg = <0x70006300 0x100>;
 220                 reg-shift = <2>;
 221                 interrupts = <0 90 0x04>;
 222                 status = "disabled";
 223         };
 224
 225         serial@70006400 {
 226                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 227                 reg = <0x70006400 0x100>;
 228                 reg-shift = <2>;
 229                 interrupts = <0 91 0x04>;
 230                 status = "disabled";
 231         };
 232
 233         pwm: pwm {
 234                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 235                 reg = <0x7000a000 0x100>;
 236                 #pwm-cells = <2>;
 237         };
 238
 239         rtc {
 240                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 241                 reg = <0x7000e000 0x100>;
 242                 interrupts = <0 2 0x04>;
 243         };
 244
 245         i2c@7000c000 {
 246                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 247                 reg = <0x7000c000 0x100>;
 248                 interrupts = <0 38 0x04>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         i2c@7000c400 {
 255                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 256                 reg = <0x7000c400 0x100>;
 257                 interrupts = <0 84 0x04>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 status = "disabled";
 261         };
 262
 263         i2c@7000c500 {
 264                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 265                 reg = <0x7000c500 0x100>;
 266                 interrupts = <0 92 0x04>;
 267                 #address-cells = <1>;
 268                 #size-cells = <0>;
 269                 status = "disabled";
 270         };
 271
 272         i2c@7000c700 {
 273                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 274                 reg = <0x7000c700 0x100>;
 275                 interrupts = <0 120 0x04>;
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278                 status = "disabled";
 279         };
 280
 281         i2c@7000d000 {
 282                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 283                 reg = <0x7000d000 0x100>;
 284                 interrupts = <0 53 0x04>;
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 status = "disabled";
 288         };
 289
 290         spi@7000d400 {
 291                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 292                 reg = <0x7000d400 0x200>;
 293                 interrupts = <0 59 0x04>;
 294                 nvidia,dma-request-selector = <&apbdma 15>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 status = "disabled";
 298         };
 299
 300         spi@7000d600 {
 301                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 302                 reg = <0x7000d600 0x200>;
 303                 interrupts = <0 82 0x04>;
 304                 nvidia,dma-request-selector = <&apbdma 16>;
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307                 status = "disabled";
 308         };
 309
 310         spi@7000d800 {
 311                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 312                 reg = <0x7000d480 0x200>;
 313                 interrupts = <0 83 0x04>;
 314                 nvidia,dma-request-selector = <&apbdma 17>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 status = "disabled";
 318         };
 319
 320         spi@7000da00 {
 321                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 322                 reg = <0x7000da00 0x200>;
 323                 interrupts = <0 93 0x04>;
 324                 nvidia,dma-request-selector = <&apbdma 18>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 status = "disabled";
 328         };
 329
 330         spi@7000dc00 {
 331                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 332                 reg = <0x7000dc00 0x200>;
 333                 interrupts = <0 94 0x04>;
 334                 nvidia,dma-request-selector = <&apbdma 27>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337                 status = "disabled";
 338         };
 339
 340         spi@7000de00 {
 341                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 342                 reg = <0x7000de00 0x200>;
 343                 interrupts = <0 79 0x04>;
 344                 nvidia,dma-request-selector = <&apbdma 28>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 status = "disabled";
 348         };
 349
 350         pmc {
 351                 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
 352                 reg = <0x7000e400 0x400>;
 353         };
 354
 355         memory-controller {
 356                 compatible = "nvidia,tegra30-mc";
 357                 reg = <0x7000f000 0x010
 358                        0x7000f03c 0x1b4
 359                        0x7000f200 0x028
 360                        0x7000f284 0x17c>;
 361                 interrupts = <0 77 0x04>;
 362         };
 363
 364         smmu {
 365                 compatible = "nvidia,tegra30-smmu";
 366                 reg = <0x7000f010 0x02c
 367                        0x7000f1f0 0x010
 368                        0x7000f228 0x05c>;
 369                 nvidia,#asids = <4>;            /* # of ASIDs */
 370                 dma-window = <0 0x40000000>;    /* IOVA start & length */
 371                 nvidia,ahb = <&ahb>;
 372         };
 373
 374         ahub {
 375                 compatible = "nvidia,tegra30-ahub";
 376                 reg = <0x70080000 0x200
 377                        0x70080200 0x100>;
 378                 interrupts = <0 103 0x04>;
 379                 nvidia,dma-request-selector = <&apbdma 1>;
 380
 381                 ranges;
 382                 #address-cells = <1>;
 383                 #size-cells = <1>;
 384
 385                 tegra_i2s0: i2s@70080300 {
 386                         compatible = "nvidia,tegra30-i2s";
 387                         reg = <0x70080300 0x100>;
 388                         nvidia,ahub-cif-ids = <4 4>;
 389                         status = "disabled";
 390                 };
 391
 392                 tegra_i2s1: i2s@70080400 {
 393                         compatible = "nvidia,tegra30-i2s";
 394                         reg = <0x70080400 0x100>;
 395                         nvidia,ahub-cif-ids = <5 5>;
 396                         status = "disabled";
 397                 };
 398
 399                 tegra_i2s2: i2s@70080500 {
 400                         compatible = "nvidia,tegra30-i2s";
 401                         reg = <0x70080500 0x100>;
 402                         nvidia,ahub-cif-ids = <6 6>;
 403                         status = "disabled";
 404                 };
 405
 406                 tegra_i2s3: i2s@70080600 {
 407                         compatible = "nvidia,tegra30-i2s";
 408                         reg = <0x70080600 0x100>;
 409                         nvidia,ahub-cif-ids = <7 7>;
 410                         status = "disabled";
 411                 };
 412
 413                 tegra_i2s4: i2s@70080700 {
 414                         compatible = "nvidia,tegra30-i2s";
 415                         reg = <0x70080700 0x100>;
 416                         nvidia,ahub-cif-ids = <8 8>;
 417                         status = "disabled";
 418                 };
 419         };
 420
 421         sdhci@78000000 {
 422                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 423                 reg = <0x78000000 0x200>;
 424                 interrupts = <0 14 0x04>;
 425                 status = "disabled";
 426         };
 427
 428         sdhci@78000200 {
 429                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 430                 reg = <0x78000200 0x200>;
 431                 interrupts = <0 15 0x04>;
 432                 status = "disabled";
 433         };
 434
 435         sdhci@78000400 {
 436                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 437                 reg = <0x78000400 0x200>;
 438                 interrupts = <0 19 0x04>;
 439                 status = "disabled";
 440         };
 441
 442         sdhci@78000600 {
 443                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 444                 reg = <0x78000600 0x200>;
 445                 interrupts = <0 31 0x04>;
 446                 status = "disabled";
 447         };
 448
 449         pmu {
 450                 compatible = "arm,cortex-a9-pmu";
 451                 interrupts = <0 144 0x04
 452                               0 145 0x04
 453                               0 146 0x04
 454                               0 147 0x04>;
 455         };
 456 };