drivers/net/wireless/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, write to the
  28         Free Software Foundation, Inc.,
  29         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /*
  33         Module: rt2800lib
  34         Abstract: rt2800 generic device routines.
  35  */
  36
  37 #include <linux/crc-ccitt.h>
  38 #include <linux/kernel.h>
  39 #include <linux/module.h>
  40 #include <linux/slab.h>
  41
  42 #include "rt2x00.h"
  43 #include "rt2800lib.h"
  44 #include "rt2800.h"
  45
  46 /*
  47  * Register access.
  48  * All access to the CSR registers will go through the methods
  49  * rt2800_register_read and rt2800_register_write.
  50  * BBP and RF register require indirect register access,
  51  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  52  * These indirect registers work with busy bits,
  53  * and we will try maximal REGISTER_BUSY_COUNT times to access
  54  * the register while taking a REGISTER_BUSY_DELAY us delay
  55  * between each attampt. When the busy bit is still set at that time,
  56  * the access attempt is considered to have failed,
  57  * and we will print an error.
  58  * The _lock versions must be used if you already hold the csr_mutex
  59  */
  60 #define WAIT_FOR_BBP(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  64 #define WAIT_FOR_RF(__dev, __reg) \
  65         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  66 #define WAIT_FOR_MCU(__dev, __reg) \
  67         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  68                             H2M_MAILBOX_CSR_OWNER, (__reg))
  69
  70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  71 {
  72         /* check for rt2872 on SoC */
  73         if (!rt2x00_is_soc(rt2x00dev) ||
  74             !rt2x00_rt(rt2x00dev, RT2872))
  75                 return false;
  76
  77         /* we know for sure that these rf chipsets are used on rt305x boards */
  78         if (rt2x00_rf(rt2x00dev, RF3020) ||
  79             rt2x00_rf(rt2x00dev, RF3021) ||
  80             rt2x00_rf(rt2x00dev, RF3022))
  81                 return true;
  82
  83         NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
  84         return false;
  85 }
  86
  87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  88                              const unsigned int word, const u8 value)
  89 {
  90         u32 reg;
  91
  92         mutex_lock(&rt2x00dev->csr_mutex);
  93
  94         /*
  95          * Wait until the BBP becomes available, afterwards we
  96          * can safely write the new data into the register.
  97          */
  98         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  99                 reg = 0;
 100                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 105
 106                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 107         }
 108
 109         mutex_unlock(&rt2x00dev->csr_mutex);
 110 }
 111
 112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 113                             const unsigned int word, u8 *value)
 114 {
 115         u32 reg;
 116
 117         mutex_lock(&rt2x00dev->csr_mutex);
 118
 119         /*
 120          * Wait until the BBP becomes available, afterwards we
 121          * can safely write the read request into the register.
 122          * After the data has been written, we wait until hardware
 123          * returns the correct value, if at any time the register
 124          * doesn't become available in time, reg will be 0xffffffff
 125          * which means we return 0xff to the caller.
 126          */
 127         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 128                 reg = 0;
 129                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 133
 134                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 135
 136                 WAIT_FOR_BBP(rt2x00dev, &reg);
 137         }
 138
 139         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 140
 141         mutex_unlock(&rt2x00dev->csr_mutex);
 142 }
 143
 144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 145                                const unsigned int word, const u8 value)
 146 {
 147         u32 reg;
 148
 149         mutex_lock(&rt2x00dev->csr_mutex);
 150
 151         /*
 152          * Wait until the RFCSR becomes available, afterwards we
 153          * can safely write the new data into the register.
 154          */
 155         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 156                 reg = 0;
 157                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 158                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 159                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 160                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 161
 162                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 163         }
 164
 165         mutex_unlock(&rt2x00dev->csr_mutex);
 166 }
 167
 168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 169                               const unsigned int word, u8 *value)
 170 {
 171         u32 reg;
 172
 173         mutex_lock(&rt2x00dev->csr_mutex);
 174
 175         /*
 176          * Wait until the RFCSR becomes available, afterwards we
 177          * can safely write the read request into the register.
 178          * After the data has been written, we wait until hardware
 179          * returns the correct value, if at any time the register
 180          * doesn't become available in time, reg will be 0xffffffff
 181          * which means we return 0xff to the caller.
 182          */
 183         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 184                 reg = 0;
 185                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 186                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 187                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 188
 189                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 190
 191                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 192         }
 193
 194         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 195
 196         mutex_unlock(&rt2x00dev->csr_mutex);
 197 }
 198
 199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 200                             const unsigned int word, const u32 value)
 201 {
 202         u32 reg;
 203
 204         mutex_lock(&rt2x00dev->csr_mutex);
 205
 206         /*
 207          * Wait until the RF becomes available, afterwards we
 208          * can safely write the new data into the register.
 209          */
 210         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 211                 reg = 0;
 212                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 213                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 214                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 215                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 216
 217                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 218                 rt2x00_rf_write(rt2x00dev, word, value);
 219         }
 220
 221         mutex_unlock(&rt2x00dev->csr_mutex);
 222 }
 223
 224 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 225 {
 226         u32 reg;
 227         int i, count;
 228
 229         rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 230         if (rt2x00_get_field32(reg, WLAN_EN))
 231                 return 0;
 232
 233         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 234         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 235         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 236         rt2x00_set_field32(&reg, WLAN_EN, 1);
 237         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 238
 239         udelay(REGISTER_BUSY_DELAY);
 240
 241         count = 0;
 242         do {
 243                 /*
 244                  * Check PLL_LD & XTAL_RDY.
 245                  */
 246                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 247                         rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
 248                         if (rt2x00_get_field32(reg, PLL_LD) &&
 249                             rt2x00_get_field32(reg, XTAL_RDY))
 250                                 break;
 251                         udelay(REGISTER_BUSY_DELAY);
 252                 }
 253
 254                 if (i >= REGISTER_BUSY_COUNT) {
 255
 256                         if (count >= 10)
 257                                 return -EIO;
 258
 259                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 260                         udelay(REGISTER_BUSY_DELAY);
 261                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 262                         udelay(REGISTER_BUSY_DELAY);
 263                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 264                         udelay(REGISTER_BUSY_DELAY);
 265                         count++;
 266                 } else {
 267                         count = 0;
 268                 }
 269
 270                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 271                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 272                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 273                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 274                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 275                 udelay(10);
 276                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 277                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 278                 udelay(10);
 279                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 280         } while (count != 0);
 281
 282         return 0;
 283 }
 284
 285 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 286                         const u8 command, const u8 token,
 287                         const u8 arg0, const u8 arg1)
 288 {
 289         u32 reg;
 290
 291         /*
 292          * SOC devices don't support MCU requests.
 293          */
 294         if (rt2x00_is_soc(rt2x00dev))
 295                 return;
 296
 297         mutex_lock(&rt2x00dev->csr_mutex);
 298
 299         /*
 300          * Wait until the MCU becomes available, afterwards we
 301          * can safely write the new data into the register.
 302          */
 303         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 304                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 305                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 306                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 307                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 308                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 309
 310                 reg = 0;
 311                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 312                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 313         }
 314
 315         mutex_unlock(&rt2x00dev->csr_mutex);
 316 }
 317 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 318
 319 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 320 {
 321         unsigned int i = 0;
 322         u32 reg;
 323
 324         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 325                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 326                 if (reg && reg != ~0)
 327                         return 0;
 328                 msleep(1);
 329         }
 330
 331         ERROR(rt2x00dev, "Unstable hardware.\n");
 332         return -EBUSY;
 333 }
 334 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 335
 336 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 337 {
 338         unsigned int i;
 339         u32 reg;
 340
 341         /*
 342          * Some devices are really slow to respond here. Wait a whole second
 343          * before timing out.
 344          */
 345         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 346                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 347                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 348                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 349                         return 0;
 350
 351                 msleep(10);
 352         }
 353
 354         ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
 355         return -EACCES;
 356 }
 357 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 358
 359 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 360 {
 361         u32 reg;
 362
 363         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 364         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 365         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 366         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 367         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 368         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 369         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 370 }
 371 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 372
 373 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 374 {
 375         u16 fw_crc;
 376         u16 crc;
 377
 378         /*
 379          * The last 2 bytes in the firmware array are the crc checksum itself,
 380          * this means that we should never pass those 2 bytes to the crc
 381          * algorithm.
 382          */
 383         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 384
 385         /*
 386          * Use the crc ccitt algorithm.
 387          * This will return the same value as the legacy driver which
 388          * used bit ordering reversion on the both the firmware bytes
 389          * before input input as well as on the final output.
 390          * Obviously using crc ccitt directly is much more efficient.
 391          */
 392         crc = crc_ccitt(~0, data, len - 2);
 393
 394         /*
 395          * There is a small difference between the crc-itu-t + bitrev and
 396          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 397          * will be swapped, use swab16 to convert the crc to the correct
 398          * value.
 399          */
 400         crc = swab16(crc);
 401
 402         return fw_crc == crc;
 403 }
 404
 405 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 406                           const u8 *data, const size_t len)
 407 {
 408         size_t offset = 0;
 409         size_t fw_len;
 410         bool multiple;
 411
 412         /*
 413          * PCI(e) & SOC devices require firmware with a length
 414          * of 8kb. USB devices require firmware files with a length
 415          * of 4kb. Certain USB chipsets however require different firmware,
 416          * which Ralink only provides attached to the original firmware
 417          * file. Thus for USB devices, firmware files have a length
 418          * which is a multiple of 4kb. The firmware for rt3290 chip also
 419          * have a length which is a multiple of 4kb.
 420          */
 421         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 422                 fw_len = 4096;
 423         else
 424                 fw_len = 8192;
 425
 426         multiple = true;
 427         /*
 428          * Validate the firmware length
 429          */
 430         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 431                 return FW_BAD_LENGTH;
 432
 433         /*
 434          * Check if the chipset requires one of the upper parts
 435          * of the firmware.
 436          */
 437         if (rt2x00_is_usb(rt2x00dev) &&
 438             !rt2x00_rt(rt2x00dev, RT2860) &&
 439             !rt2x00_rt(rt2x00dev, RT2872) &&
 440             !rt2x00_rt(rt2x00dev, RT3070) &&
 441             ((len / fw_len) == 1))
 442                 return FW_BAD_VERSION;
 443
 444         /*
 445          * 8kb firmware files must be checked as if it were
 446          * 2 separate firmware files.
 447          */
 448         while (offset < len) {
 449                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 450                         return FW_BAD_CRC;
 451
 452                 offset += fw_len;
 453         }
 454
 455         return FW_OK;
 456 }
 457 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 458
 459 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 460                          const u8 *data, const size_t len)
 461 {
 462         unsigned int i;
 463         u32 reg;
 464         int retval;
 465
 466         if (rt2x00_rt(rt2x00dev, RT3290)) {
 467                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 468                 if (retval)
 469                         return -EBUSY;
 470         }
 471
 472         /*
 473          * If driver doesn't wake up firmware here,
 474          * rt2800_load_firmware will hang forever when interface is up again.
 475          */
 476         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 477
 478         /*
 479          * Wait for stable hardware.
 480          */
 481         if (rt2800_wait_csr_ready(rt2x00dev))
 482                 return -EBUSY;
 483
 484         if (rt2x00_is_pci(rt2x00dev)) {
 485                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 486                     rt2x00_rt(rt2x00dev, RT3572) ||
 487                     rt2x00_rt(rt2x00dev, RT5390) ||
 488                     rt2x00_rt(rt2x00dev, RT5392)) {
 489                         rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
 490                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 491                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 492                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 493                 }
 494                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 495         }
 496
 497         rt2800_disable_wpdma(rt2x00dev);
 498
 499         /*
 500          * Write firmware to the device.
 501          */
 502         rt2800_drv_write_firmware(rt2x00dev, data, len);
 503
 504         /*
 505          * Wait for device to stabilize.
 506          */
 507         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 508                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
 509                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 510                         break;
 511                 msleep(1);
 512         }
 513
 514         if (i == REGISTER_BUSY_COUNT) {
 515                 ERROR(rt2x00dev, "PBF system register not ready.\n");
 516                 return -EBUSY;
 517         }
 518
 519         /*
 520          * Disable DMA, will be reenabled later when enabling
 521          * the radio.
 522          */
 523         rt2800_disable_wpdma(rt2x00dev);
 524
 525         /*
 526          * Initialize firmware.
 527          */
 528         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 529         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 530         if (rt2x00_is_usb(rt2x00dev))
 531                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 532         msleep(1);
 533
 534         return 0;
 535 }
 536 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 537
 538 void rt2800_write_tx_data(struct queue_entry *entry,
 539                           struct txentry_desc *txdesc)
 540 {
 541         __le32 *txwi = rt2800_drv_get_txwi(entry);
 542         u32 word;
 543
 544         /*
 545          * Initialize TX Info descriptor
 546          */
 547         rt2x00_desc_read(txwi, 0, &word);
 548         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 549                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 550         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 551                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 552         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 553         rt2x00_set_field32(&word, TXWI_W0_TS,
 554                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 555         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 556                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 557         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 558                            txdesc->u.ht.mpdu_density);
 559         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 560         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 561         rt2x00_set_field32(&word, TXWI_W0_BW,
 562                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 563         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 564                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 565         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 566         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 567         rt2x00_desc_write(txwi, 0, word);
 568
 569         rt2x00_desc_read(txwi, 1, &word);
 570         rt2x00_set_field32(&word, TXWI_W1_ACK,
 571                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 572         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 573                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 574         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 575         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 576                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 577                            txdesc->key_idx : txdesc->u.ht.wcid);
 578         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 579                            txdesc->length);
 580         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 581         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 582         rt2x00_desc_write(txwi, 1, word);
 583
 584         /*
 585          * Always write 0 to IV/EIV fields, hardware will insert the IV
 586          * from the IVEIV register when TXD_W3_WIV is set to 0.
 587          * When TXD_W3_WIV is set to 1 it will use the IV data
 588          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 589          * crypto entry in the registers should be used to encrypt the frame.
 590          */
 591         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
 592         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
 593 }
 594 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 595
 596 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 597 {
 598         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 599         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 600         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 601         u16 eeprom;
 602         u8 offset0;
 603         u8 offset1;
 604         u8 offset2;
 605
 606         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
 607                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
 608                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 609                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 610                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 611                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 612         } else {
 613                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
 614                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 615                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 616                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 617                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 618         }
 619
 620         /*
 621          * Convert the value from the descriptor into the RSSI value
 622          * If the value in the descriptor is 0, it is considered invalid
 623          * and the default (extremely low) rssi value is assumed
 624          */
 625         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 626         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 627         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 628
 629         /*
 630          * mac80211 only accepts a single RSSI value. Calculating the
 631          * average doesn't deliver a fair answer either since -60:-60 would
 632          * be considered equally good as -50:-70 while the second is the one
 633          * which gives less energy...
 634          */
 635         rssi0 = max(rssi0, rssi1);
 636         return (int)max(rssi0, rssi2);
 637 }
 638
 639 void rt2800_process_rxwi(struct queue_entry *entry,
 640                          struct rxdone_entry_desc *rxdesc)
 641 {
 642         __le32 *rxwi = (__le32 *) entry->skb->data;
 643         u32 word;
 644
 645         rt2x00_desc_read(rxwi, 0, &word);
 646
 647         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 648         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 649
 650         rt2x00_desc_read(rxwi, 1, &word);
 651
 652         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 653                 rxdesc->flags |= RX_FLAG_SHORT_GI;
 654
 655         if (rt2x00_get_field32(word, RXWI_W1_BW))
 656                 rxdesc->flags |= RX_FLAG_40MHZ;
 657
 658         /*
 659          * Detect RX rate, always use MCS as signal type.
 660          */
 661         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 662         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 663         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 664
 665         /*
 666          * Mask of 0x8 bit to remove the short preamble flag.
 667          */
 668         if (rxdesc->rate_mode == RATE_MODE_CCK)
 669                 rxdesc->signal &= ~0x8;
 670
 671         rt2x00_desc_read(rxwi, 2, &word);
 672
 673         /*
 674          * Convert descriptor AGC value to RSSI value.
 675          */
 676         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 677
 678         /*
 679          * Remove RXWI descriptor from start of buffer.
 680          */
 681         skb_pull(entry->skb, RXWI_DESC_SIZE);
 682 }
 683 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 684
 685 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
 686 {
 687         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 688         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 689         struct txdone_entry_desc txdesc;
 690         u32 word;
 691         u16 mcs, real_mcs;
 692         int aggr, ampdu;
 693
 694         /*
 695          * Obtain the status about this packet.
 696          */
 697         txdesc.flags = 0;
 698         rt2x00_desc_read(txwi, 0, &word);
 699
 700         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 701         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 702
 703         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 704         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 705
 706         /*
 707          * If a frame was meant to be sent as a single non-aggregated MPDU
 708          * but ended up in an aggregate the used tx rate doesn't correlate
 709          * with the one specified in the TXWI as the whole aggregate is sent
 710          * with the same rate.
 711          *
 712          * For example: two frames are sent to rt2x00, the first one sets
 713          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 714          * and requests MCS15. If the hw aggregates both frames into one
 715          * AMDPU the tx status for both frames will contain MCS7 although
 716          * the frame was sent successfully.
 717          *
 718          * Hence, replace the requested rate with the real tx rate to not
 719          * confuse the rate control algortihm by providing clearly wrong
 720          * data.
 721          */
 722         if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
 723                 skbdesc->tx_rate_idx = real_mcs;
 724                 mcs = real_mcs;
 725         }
 726
 727         if (aggr == 1 || ampdu == 1)
 728                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
 729
 730         /*
 731          * Ralink has a retry mechanism using a global fallback
 732          * table. We setup this fallback table to try the immediate
 733          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
 734          * always contains the MCS used for the last transmission, be
 735          * it successful or not.
 736          */
 737         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
 738                 /*
 739                  * Transmission succeeded. The number of retries is
 740                  * mcs - real_mcs
 741                  */
 742                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
 743                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
 744         } else {
 745                 /*
 746                  * Transmission failed. The number of retries is
 747                  * always 7 in this case (for a total number of 8
 748                  * frames sent).
 749                  */
 750                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
 751                 txdesc.retry = rt2x00dev->long_retry;
 752         }
 753
 754         /*
 755          * the frame was retried at least once
 756          * -> hw used fallback rates
 757          */
 758         if (txdesc.retry)
 759                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
 760
 761         rt2x00lib_txdone(entry, &txdesc);
 762 }
 763 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
 764
 765 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 766 {
 767         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 768         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 769         unsigned int beacon_base;
 770         unsigned int padding_len;
 771         u32 orig_reg, reg;
 772
 773         /*
 774          * Disable beaconing while we are reloading the beacon data,
 775          * otherwise we might be sending out invalid data.
 776          */
 777         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 778         orig_reg = reg;
 779         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 780         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 781
 782         /*
 783          * Add space for the TXWI in front of the skb.
 784          */
 785         memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
 786
 787         /*
 788          * Register descriptor details in skb frame descriptor.
 789          */
 790         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
 791         skbdesc->desc = entry->skb->data;
 792         skbdesc->desc_len = TXWI_DESC_SIZE;
 793
 794         /*
 795          * Add the TXWI for the beacon to the skb.
 796          */
 797         rt2800_write_tx_data(entry, txdesc);
 798
 799         /*
 800          * Dump beacon to userspace through debugfs.
 801          */
 802         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 803
 804         /*
 805          * Write entire beacon with TXWI and padding to register.
 806          */
 807         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
 808         if (padding_len && skb_pad(entry->skb, padding_len)) {
 809                 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
 810                 /* skb freed by skb_pad() on failure */
 811                 entry->skb = NULL;
 812                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
 813                 return;
 814         }
 815
 816         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
 817         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
 818                                    entry->skb->len + padding_len);
 819
 820         /*
 821          * Enable beaconing again.
 822          */
 823         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 824         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 825
 826         /*
 827          * Clean up beacon skb.
 828          */
 829         dev_kfree_skb_any(entry->skb);
 830         entry->skb = NULL;
 831 }
 832 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 833
 834 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
 835                                                 unsigned int beacon_base)
 836 {
 837         int i;
 838
 839         /*
 840          * For the Beacon base registers we only need to clear
 841          * the whole TXWI which (when set to 0) will invalidate
 842          * the entire beacon.
 843          */
 844         for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
 845                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
 846 }
 847
 848 void rt2800_clear_beacon(struct queue_entry *entry)
 849 {
 850         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 851         u32 reg;
 852
 853         /*
 854          * Disable beaconing while we are reloading the beacon data,
 855          * otherwise we might be sending out invalid data.
 856          */
 857         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 858         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 859         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 860
 861         /*
 862          * Clear beacon.
 863          */
 864         rt2800_clear_beacon_register(rt2x00dev,
 865                                      HW_BEACON_OFFSET(entry->entry_idx));
 866
 867         /*
 868          * Enabled beaconing again.
 869          */
 870         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 871         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 872 }
 873 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
 874
 875 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 876 const struct rt2x00debug rt2800_rt2x00debug = {
 877         .owner  = THIS_MODULE,
 878         .csr    = {
 879                 .read           = rt2800_register_read,
 880                 .write          = rt2800_register_write,
 881                 .flags          = RT2X00DEBUGFS_OFFSET,
 882                 .word_base      = CSR_REG_BASE,
 883                 .word_size      = sizeof(u32),
 884                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 885         },
 886         .eeprom = {
 887                 .read           = rt2x00_eeprom_read,
 888                 .write          = rt2x00_eeprom_write,
 889                 .word_base      = EEPROM_BASE,
 890                 .word_size      = sizeof(u16),
 891                 .word_count     = EEPROM_SIZE / sizeof(u16),
 892         },
 893         .bbp    = {
 894                 .read           = rt2800_bbp_read,
 895                 .write          = rt2800_bbp_write,
 896                 .word_base      = BBP_BASE,
 897                 .word_size      = sizeof(u8),
 898                 .word_count     = BBP_SIZE / sizeof(u8),
 899         },
 900         .rf     = {
 901                 .read           = rt2x00_rf_read,
 902                 .write          = rt2800_rf_write,
 903                 .word_base      = RF_BASE,
 904                 .word_size      = sizeof(u32),
 905                 .word_count     = RF_SIZE / sizeof(u32),
 906         },
 907         .rfcsr  = {
 908                 .read           = rt2800_rfcsr_read,
 909                 .write          = rt2800_rfcsr_write,
 910                 .word_base      = RFCSR_BASE,
 911                 .word_size      = sizeof(u8),
 912                 .word_count     = RFCSR_SIZE / sizeof(u8),
 913         },
 914 };
 915 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
 916 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 917
 918 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 919 {
 920         u32 reg;
 921
 922         if (rt2x00_rt(rt2x00dev, RT3290)) {
 923                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
 924                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
 925         } else {
 926                 rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
 927                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
 928         }
 929 }
 930 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
 931
 932 #ifdef CONFIG_RT2X00_LIB_LEDS
 933 static void rt2800_brightness_set(struct led_classdev *led_cdev,
 934                                   enum led_brightness brightness)
 935 {
 936         struct rt2x00_led *led =
 937             container_of(led_cdev, struct rt2x00_led, led_dev);
 938         unsigned int enabled = brightness != LED_OFF;
 939         unsigned int bg_mode =
 940             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 941         unsigned int polarity =
 942                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 943                                    EEPROM_FREQ_LED_POLARITY);
 944         unsigned int ledmode =
 945                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 946                                    EEPROM_FREQ_LED_MODE);
 947         u32 reg;
 948
 949         /* Check for SoC (SOC devices don't support MCU requests) */
 950         if (rt2x00_is_soc(led->rt2x00dev)) {
 951                 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 952
 953                 /* Set LED Polarity */
 954                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
 955
 956                 /* Set LED Mode */
 957                 if (led->type == LED_TYPE_RADIO) {
 958                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
 959                                            enabled ? 3 : 0);
 960                 } else if (led->type == LED_TYPE_ASSOC) {
 961                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
 962                                            enabled ? 3 : 0);
 963                 } else if (led->type == LED_TYPE_QUALITY) {
 964                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
 965                                            enabled ? 3 : 0);
 966                 }
 967
 968                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 969
 970         } else {
 971                 if (led->type == LED_TYPE_RADIO) {
 972                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 973                                               enabled ? 0x20 : 0);
 974                 } else if (led->type == LED_TYPE_ASSOC) {
 975                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 976                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 977                 } else if (led->type == LED_TYPE_QUALITY) {
 978                         /*
 979                          * The brightness is divided into 6 levels (0 - 5),
 980                          * The specs tell us the following levels:
 981                          *      0, 1 ,3, 7, 15, 31
 982                          * to determine the level in a simple way we can simply
 983                          * work with bitshifting:
 984                          *      (1 << level) - 1
 985                          */
 986                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 987                                               (1 << brightness / (LED_FULL / 6)) - 1,
 988                                               polarity);
 989                 }
 990         }
 991 }
 992
 993 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
 994                      struct rt2x00_led *led, enum led_type type)
 995 {
 996         led->rt2x00dev = rt2x00dev;
 997         led->type = type;
 998         led->led_dev.brightness_set = rt2800_brightness_set;
 999         led->flags = LED_INITIALIZED;
1000 }
1001 #endif /* CONFIG_RT2X00_LIB_LEDS */
1002
1003 /*
1004  * Configuration handlers.
1005  */
1006 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1007                                const u8 *address,
1008                                int wcid)
1009 {
1010         struct mac_wcid_entry wcid_entry;
1011         u32 offset;
1012
1013         offset = MAC_WCID_ENTRY(wcid);
1014
1015         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1016         if (address)
1017                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1018
1019         rt2800_register_multiwrite(rt2x00dev, offset,
1020                                       &wcid_entry, sizeof(wcid_entry));
1021 }
1022
1023 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1024 {
1025         u32 offset;
1026         offset = MAC_WCID_ATTR_ENTRY(wcid);
1027         rt2800_register_write(rt2x00dev, offset, 0);
1028 }
1029
1030 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1031                                            int wcid, u32 bssidx)
1032 {
1033         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1034         u32 reg;
1035
1036         /*
1037          * The BSS Idx numbers is split in a main value of 3 bits,
1038          * and a extended field for adding one additional bit to the value.
1039          */
1040         rt2800_register_read(rt2x00dev, offset, &reg);
1041         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1042         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1043                            (bssidx & 0x8) >> 3);
1044         rt2800_register_write(rt2x00dev, offset, reg);
1045 }
1046
1047 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1048                                            struct rt2x00lib_crypto *crypto,
1049                                            struct ieee80211_key_conf *key)
1050 {
1051         struct mac_iveiv_entry iveiv_entry;
1052         u32 offset;
1053         u32 reg;
1054
1055         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1056
1057         if (crypto->cmd == SET_KEY) {
1058                 rt2800_register_read(rt2x00dev, offset, &reg);
1059                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1060                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1061                 /*
1062                  * Both the cipher as the BSS Idx numbers are split in a main
1063                  * value of 3 bits, and a extended field for adding one additional
1064                  * bit to the value.
1065                  */
1066                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1067                                    (crypto->cipher & 0x7));
1068                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1069                                    (crypto->cipher & 0x8) >> 3);
1070                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1071                 rt2800_register_write(rt2x00dev, offset, reg);
1072         } else {
1073                 /* Delete the cipher without touching the bssidx */
1074                 rt2800_register_read(rt2x00dev, offset, &reg);
1075                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1076                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1077                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1078                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1079                 rt2800_register_write(rt2x00dev, offset, reg);
1080         }
1081
1082         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1083
1084         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1085         if ((crypto->cipher == CIPHER_TKIP) ||
1086             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1087             (crypto->cipher == CIPHER_AES))
1088                 iveiv_entry.iv[3] |= 0x20;
1089         iveiv_entry.iv[3] |= key->keyidx << 6;
1090         rt2800_register_multiwrite(rt2x00dev, offset,
1091                                       &iveiv_entry, sizeof(iveiv_entry));
1092 }
1093
1094 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1095                              struct rt2x00lib_crypto *crypto,
1096                              struct ieee80211_key_conf *key)
1097 {
1098         struct hw_key_entry key_entry;
1099         struct rt2x00_field32 field;
1100         u32 offset;
1101         u32 reg;
1102
1103         if (crypto->cmd == SET_KEY) {
1104                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1105
1106                 memcpy(key_entry.key, crypto->key,
1107                        sizeof(key_entry.key));
1108                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1109                        sizeof(key_entry.tx_mic));
1110                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1111                        sizeof(key_entry.rx_mic));
1112
1113                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1114                 rt2800_register_multiwrite(rt2x00dev, offset,
1115                                               &key_entry, sizeof(key_entry));
1116         }
1117
1118         /*
1119          * The cipher types are stored over multiple registers
1120          * starting with SHARED_KEY_MODE_BASE each word will have
1121          * 32 bits and contains the cipher types for 2 bssidx each.
1122          * Using the correct defines correctly will cause overhead,
1123          * so just calculate the correct offset.
1124          */
1125         field.bit_offset = 4 * (key->hw_key_idx % 8);
1126         field.bit_mask = 0x7 << field.bit_offset;
1127
1128         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1129
1130         rt2800_register_read(rt2x00dev, offset, &reg);
1131         rt2x00_set_field32(&reg, field,
1132                            (crypto->cmd == SET_KEY) * crypto->cipher);
1133         rt2800_register_write(rt2x00dev, offset, reg);
1134
1135         /*
1136          * Update WCID information
1137          */
1138         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1139         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1140                                        crypto->bssidx);
1141         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1142
1143         return 0;
1144 }
1145 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1146
1147 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1148 {
1149         struct mac_wcid_entry wcid_entry;
1150         int idx;
1151         u32 offset;
1152
1153         /*
1154          * Search for the first free WCID entry and return the corresponding
1155          * index.
1156          *
1157          * Make sure the WCID starts _after_ the last possible shared key
1158          * entry (>32).
1159          *
1160          * Since parts of the pairwise key table might be shared with
1161          * the beacon frame buffers 6 & 7 we should only write into the
1162          * first 222 entries.
1163          */
1164         for (idx = 33; idx <= 222; idx++) {
1165                 offset = MAC_WCID_ENTRY(idx);
1166                 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1167                                           sizeof(wcid_entry));
1168                 if (is_broadcast_ether_addr(wcid_entry.mac))
1169                         return idx;
1170         }
1171
1172         /*
1173          * Use -1 to indicate that we don't have any more space in the WCID
1174          * table.
1175          */
1176         return -1;
1177 }
1178
1179 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1180                                struct rt2x00lib_crypto *crypto,
1181                                struct ieee80211_key_conf *key)
1182 {
1183         struct hw_key_entry key_entry;
1184         u32 offset;
1185
1186         if (crypto->cmd == SET_KEY) {
1187                 /*
1188                  * Allow key configuration only for STAs that are
1189                  * known by the hw.
1190                  */
1191                 if (crypto->wcid < 0)
1192                         return -ENOSPC;
1193                 key->hw_key_idx = crypto->wcid;
1194
1195                 memcpy(key_entry.key, crypto->key,
1196                        sizeof(key_entry.key));
1197                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1198                        sizeof(key_entry.tx_mic));
1199                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1200                        sizeof(key_entry.rx_mic));
1201
1202                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1203                 rt2800_register_multiwrite(rt2x00dev, offset,
1204                                               &key_entry, sizeof(key_entry));
1205         }
1206
1207         /*
1208          * Update WCID information
1209          */
1210         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1211
1212         return 0;
1213 }
1214 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1215
1216 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1217                    struct ieee80211_sta *sta)
1218 {
1219         int wcid;
1220         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1221
1222         /*
1223          * Find next free WCID.
1224          */
1225         wcid = rt2800_find_wcid(rt2x00dev);
1226
1227         /*
1228          * Store selected wcid even if it is invalid so that we can
1229          * later decide if the STA is uploaded into the hw.
1230          */
1231         sta_priv->wcid = wcid;
1232
1233         /*
1234          * No space left in the device, however, we can still communicate
1235          * with the STA -> No error.
1236          */
1237         if (wcid < 0)
1238                 return 0;
1239
1240         /*
1241          * Clean up WCID attributes and write STA address to the device.
1242          */
1243         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1244         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1245         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1246                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1247         return 0;
1248 }
1249 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1250
1251 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1252 {
1253         /*
1254          * Remove WCID entry, no need to clean the attributes as they will
1255          * get renewed when the WCID is reused.
1256          */
1257         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1258
1259         return 0;
1260 }
1261 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1262
1263 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1264                           const unsigned int filter_flags)
1265 {
1266         u32 reg;
1267
1268         /*
1269          * Start configuration steps.
1270          * Note that the version error will always be dropped
1271          * and broadcast frames will always be accepted since
1272          * there is no filter for it at this time.
1273          */
1274         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
1275         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1276                            !(filter_flags & FIF_FCSFAIL));
1277         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1278                            !(filter_flags & FIF_PLCPFAIL));
1279         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1280                            !(filter_flags & FIF_PROMISC_IN_BSS));
1281         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1282         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1283         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1284                            !(filter_flags & FIF_ALLMULTI));
1285         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1286         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1287         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1288                            !(filter_flags & FIF_CONTROL));
1289         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1290                            !(filter_flags & FIF_CONTROL));
1291         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1292                            !(filter_flags & FIF_CONTROL));
1293         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1294                            !(filter_flags & FIF_CONTROL));
1295         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1296                            !(filter_flags & FIF_CONTROL));
1297         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1298                            !(filter_flags & FIF_PSPOLL));
1299         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA,
1300                            !(filter_flags & FIF_CONTROL));
1301         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1302                            !(filter_flags & FIF_CONTROL));
1303         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1304                            !(filter_flags & FIF_CONTROL));
1305         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1306 }
1307 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1308
1309 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1310                         struct rt2x00intf_conf *conf, const unsigned int flags)
1311 {
1312         u32 reg;
1313         bool update_bssid = false;
1314
1315         if (flags & CONFIG_UPDATE_TYPE) {
1316                 /*
1317                  * Enable synchronisation.
1318                  */
1319                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1320                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1321                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1322
1323                 if (conf->sync == TSF_SYNC_AP_NONE) {
1324                         /*
1325                          * Tune beacon queue transmit parameters for AP mode
1326                          */
1327                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1328                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1329                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1330                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1331                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1332                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1333                 } else {
1334                         rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
1335                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1336                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1337                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1338                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1339                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1340                 }
1341         }
1342
1343         if (flags & CONFIG_UPDATE_MAC) {
1344                 if (flags & CONFIG_UPDATE_TYPE &&
1345                     conf->sync == TSF_SYNC_AP_NONE) {
1346                         /*
1347                          * The BSSID register has to be set to our own mac
1348                          * address in AP mode.
1349                          */
1350                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1351                         update_bssid = true;
1352                 }
1353
1354                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1355                         reg = le32_to_cpu(conf->mac[1]);
1356                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1357                         conf->mac[1] = cpu_to_le32(reg);
1358                 }
1359
1360                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1361                                               conf->mac, sizeof(conf->mac));
1362         }
1363
1364         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1365                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1366                         reg = le32_to_cpu(conf->bssid[1]);
1367                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1368                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1369                         conf->bssid[1] = cpu_to_le32(reg);
1370                 }
1371
1372                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1373                                               conf->bssid, sizeof(conf->bssid));
1374         }
1375 }
1376 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1377
1378 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1379                                     struct rt2x00lib_erp *erp)
1380 {
1381         bool any_sta_nongf = !!(erp->ht_opmode &
1382                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1383         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1384         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1385         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1386         u32 reg;
1387
1388         /* default protection rate for HT20: OFDM 24M */
1389         mm20_rate = gf20_rate = 0x4004;
1390
1391         /* default protection rate for HT40: duplicate OFDM 24M */
1392         mm40_rate = gf40_rate = 0x4084;
1393
1394         switch (protection) {
1395         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1396                 /*
1397                  * All STAs in this BSS are HT20/40 but there might be
1398                  * STAs not supporting greenfield mode.
1399                  * => Disable protection for HT transmissions.
1400                  */
1401                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1402
1403                 break;
1404         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1405                 /*
1406                  * All STAs in this BSS are HT20 or HT20/40 but there
1407                  * might be STAs not supporting greenfield mode.
1408                  * => Protect all HT40 transmissions.
1409                  */
1410                 mm20_mode = gf20_mode = 0;
1411                 mm40_mode = gf40_mode = 2;
1412
1413                 break;
1414         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1415                 /*
1416                  * Nonmember protection:
1417                  * According to 802.11n we _should_ protect all
1418                  * HT transmissions (but we don't have to).
1419                  *
1420                  * But if cts_protection is enabled we _shall_ protect
1421                  * all HT transmissions using a CCK rate.
1422                  *
1423                  * And if any station is non GF we _shall_ protect
1424                  * GF transmissions.
1425                  *
1426                  * We decide to protect everything
1427                  * -> fall through to mixed mode.
1428                  */
1429         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1430                 /*
1431                  * Legacy STAs are present
1432                  * => Protect all HT transmissions.
1433                  */
1434                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1435
1436                 /*
1437                  * If erp protection is needed we have to protect HT
1438                  * transmissions with CCK 11M long preamble.
1439                  */
1440                 if (erp->cts_protection) {
1441                         /* don't duplicate RTS/CTS in CCK mode */
1442                         mm20_rate = mm40_rate = 0x0003;
1443                         gf20_rate = gf40_rate = 0x0003;
1444                 }
1445                 break;
1446         }
1447
1448         /* check for STAs not supporting greenfield mode */
1449         if (any_sta_nongf)
1450                 gf20_mode = gf40_mode = 2;
1451
1452         /* Update HT protection config */
1453         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1454         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1455         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1456         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1457
1458         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1459         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1460         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1461         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1462
1463         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1464         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1465         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1466         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1467
1468         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1469         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1470         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1471         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1472 }
1473
1474 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1475                        u32 changed)
1476 {
1477         u32 reg;
1478
1479         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1480                 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1481                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
1482                                    !!erp->short_preamble);
1483                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1484                                    !!erp->short_preamble);
1485                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1486         }
1487
1488         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1489                 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1490                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1491                                    erp->cts_protection ? 2 : 0);
1492                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1493         }
1494
1495         if (changed & BSS_CHANGED_BASIC_RATES) {
1496                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1497                                          erp->basic_rates);
1498                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1499         }
1500
1501         if (changed & BSS_CHANGED_ERP_SLOT) {
1502                 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1503                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1504                                    erp->slot_time);
1505                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1506
1507                 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1508                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1509                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1510         }
1511
1512         if (changed & BSS_CHANGED_BEACON_INT) {
1513                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1514                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1515                                    erp->beacon_int * 16);
1516                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1517         }
1518
1519         if (changed & BSS_CHANGED_HT)
1520                 rt2800_config_ht_opmode(rt2x00dev, erp);
1521 }
1522 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1523
1524 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1525 {
1526         u32 reg;
1527         u16 eeprom;
1528         u8 led_ctrl, led_g_mode, led_r_mode;
1529
1530         rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1531         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1532                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1533                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1534         } else {
1535                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1536                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1537         }
1538         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1539
1540         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1541         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1542         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1543         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1544             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1545                 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1546                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1547                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1548                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1549                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1550                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1551                 } else {
1552                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1553                                            (led_g_mode << 2) | led_r_mode, 1);
1554                 }
1555         }
1556 }
1557
1558 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1559                                      enum antenna ant)
1560 {
1561         u32 reg;
1562         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1563         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1564
1565         if (rt2x00_is_pci(rt2x00dev)) {
1566                 rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
1567                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1568                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1569         } else if (rt2x00_is_usb(rt2x00dev))
1570                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1571                                    eesk_pin, 0);
1572
1573         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1574         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1575         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1576         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1577 }
1578
1579 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1580 {
1581         u8 r1;
1582         u8 r3;
1583         u16 eeprom;
1584
1585         rt2800_bbp_read(rt2x00dev, 1, &r1);
1586         rt2800_bbp_read(rt2x00dev, 3, &r3);
1587
1588         if (rt2x00_rt(rt2x00dev, RT3572) &&
1589             test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1590                 rt2800_config_3572bt_ant(rt2x00dev);
1591
1592         /*
1593          * Configure the TX antenna.
1594          */
1595         switch (ant->tx_chain_num) {
1596         case 1:
1597                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1598                 break;
1599         case 2:
1600                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1601                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1602                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1603                 else
1604                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1605                 break;
1606         case 3:
1607                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1608                 break;
1609         }
1610
1611         /*
1612          * Configure the RX antenna.
1613          */
1614         switch (ant->rx_chain_num) {
1615         case 1:
1616                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1617                     rt2x00_rt(rt2x00dev, RT3090) ||
1618                     rt2x00_rt(rt2x00dev, RT3352) ||
1619                     rt2x00_rt(rt2x00dev, RT3390)) {
1620                         rt2x00_eeprom_read(rt2x00dev,
1621                                            EEPROM_NIC_CONF1, &eeprom);
1622                         if (rt2x00_get_field16(eeprom,
1623                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1624                                 rt2800_set_ant_diversity(rt2x00dev,
1625                                                 rt2x00dev->default_ant.rx);
1626                 }
1627                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1628                 break;
1629         case 2:
1630                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1631                     test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1632                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1633                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1634                                 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1635                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1636                 } else {
1637                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1638                 }
1639                 break;
1640         case 3:
1641                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1642                 break;
1643         }
1644
1645         rt2800_bbp_write(rt2x00dev, 3, r3);
1646         rt2800_bbp_write(rt2x00dev, 1, r1);
1647 }
1648 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1649
1650 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1651                                    struct rt2x00lib_conf *libconf)
1652 {
1653         u16 eeprom;
1654         short lna_gain;
1655
1656         if (libconf->rf.channel <= 14) {
1657                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1658                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1659         } else if (libconf->rf.channel <= 64) {
1660                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1661                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1662         } else if (libconf->rf.channel <= 128) {
1663                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1664                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1665         } else {
1666                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1667                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1668         }
1669
1670         rt2x00dev->lna_gain = lna_gain;
1671 }
1672
1673 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1674                                          struct ieee80211_conf *conf,
1675                                          struct rf_channel *rf,
1676                                          struct channel_info *info)
1677 {
1678         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1679
1680         if (rt2x00dev->default_ant.tx_chain_num == 1)
1681                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1682
1683         if (rt2x00dev->default_ant.rx_chain_num == 1) {
1684                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1685                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1686         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1687                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1688
1689         if (rf->channel > 14) {
1690                 /*
1691                  * When TX power is below 0, we should increase it by 7 to
1692                  * make it a positive value (Minimum value is -7).
1693                  * However this means that values between 0 and 7 have
1694                  * double meaning, and we should set a 7DBm boost flag.
1695                  */
1696                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1697                                    (info->default_power1 >= 0));
1698
1699                 if (info->default_power1 < 0)
1700                         info->default_power1 += 7;
1701
1702                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1703
1704                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1705                                    (info->default_power2 >= 0));
1706
1707                 if (info->default_power2 < 0)
1708                         info->default_power2 += 7;
1709
1710                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1711         } else {
1712                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1713                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1714         }
1715
1716         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1717
1718         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1719         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1720         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1721         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1722
1723         udelay(200);
1724
1725         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1726         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1727         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1728         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1729
1730         udelay(200);
1731
1732         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1733         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1734         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1735         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1736 }
1737
1738 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1739                                          struct ieee80211_conf *conf,
1740                                          struct rf_channel *rf,
1741                                          struct channel_info *info)
1742 {
1743         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1744         u8 rfcsr, calib_tx, calib_rx;
1745
1746         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1747
1748         rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1749         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1750         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1751
1752         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1753         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1754         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1755
1756         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1757         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1758         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1759
1760         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1761         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1762         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1763
1764         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1765         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1766         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1767                           rt2x00dev->default_ant.rx_chain_num <= 1);
1768         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
1769                           rt2x00dev->default_ant.rx_chain_num <= 2);
1770         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1771         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1772                           rt2x00dev->default_ant.tx_chain_num <= 1);
1773         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
1774                           rt2x00dev->default_ant.tx_chain_num <= 2);
1775         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1776
1777         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1778         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1779         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1780         msleep(1);
1781         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1782         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1783
1784         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1785         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1786         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1787
1788         if (rt2x00_rt(rt2x00dev, RT3390)) {
1789                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1790                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1791         } else {
1792                 if (conf_is_ht40(conf)) {
1793                         calib_tx = drv_data->calibration_bw40;
1794                         calib_rx = drv_data->calibration_bw40;
1795                 } else {
1796                         calib_tx = drv_data->calibration_bw20;
1797                         calib_rx = drv_data->calibration_bw20;
1798                 }
1799         }
1800
1801         rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1802         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1803         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1804
1805         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1806         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1807         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1808
1809         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1810         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1811         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1812
1813         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1814         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1815         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1816         msleep(1);
1817         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1818         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1819 }
1820
1821 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1822                                          struct ieee80211_conf *conf,
1823                                          struct rf_channel *rf,
1824                                          struct channel_info *info)
1825 {
1826         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1827         u8 rfcsr;
1828         u32 reg;
1829
1830         if (rf->channel <= 14) {
1831                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1832                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1833         } else {
1834                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1835                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1836         }
1837
1838         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1839         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1840
1841         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1842         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1843         if (rf->channel <= 14)
1844                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1845         else
1846                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1847         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1848
1849         rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1850         if (rf->channel <= 14)
1851                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1852         else
1853                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1854         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1855
1856         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1857         if (rf->channel <= 14) {
1858                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1859                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1860                                   info->default_power1);
1861         } else {
1862                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1863                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1864                                 (info->default_power1 & 0x3) |
1865                                 ((info->default_power1 & 0xC) << 1));
1866         }
1867         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1868
1869         rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1870         if (rf->channel <= 14) {
1871                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1872                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1873                                   info->default_power2);
1874         } else {
1875                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1876                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1877                                 (info->default_power2 & 0x3) |
1878                                 ((info->default_power2 & 0xC) << 1));
1879         }
1880         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1881
1882         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1883         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1884         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1885         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1886         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1887         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1888         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1889         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1890                 if (rf->channel <= 14) {
1891                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1892                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1893                 }
1894                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1895                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1896         } else {
1897                 switch (rt2x00dev->default_ant.tx_chain_num) {
1898                 case 1:
1899                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1900                 case 2:
1901                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1902                         break;
1903                 }
1904
1905                 switch (rt2x00dev->default_ant.rx_chain_num) {
1906                 case 1:
1907                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1908                 case 2:
1909                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1910                         break;
1911                 }
1912         }
1913         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1914
1915         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1916         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1917         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1918
1919         if (conf_is_ht40(conf)) {
1920                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1921                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1922         } else {
1923                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1924                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1925         }
1926
1927         if (rf->channel <= 14) {
1928                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1929                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1930                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1931                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1932                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1933                 rfcsr = 0x4c;
1934                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1935                                   drv_data->txmixer_gain_24g);
1936                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1937                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1938                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1939                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1940                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1941                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1942                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1943                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1944         } else {
1945                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1946                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1947                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1948                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1949                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1950                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1951                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1952                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1953                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1954                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1955                 rfcsr = 0x7a;
1956                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1957                                   drv_data->txmixer_gain_5g);
1958                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1959                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1960                 if (rf->channel <= 64) {
1961                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1962                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1963                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1964                 } else if (rf->channel <= 128) {
1965                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1966                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1967                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1968                 } else {
1969                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1970                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1971                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1972                 }
1973                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1974                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1975                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1976         }
1977
1978         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
1979         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
1980         if (rf->channel <= 14)
1981                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
1982         else
1983                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
1984         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1985
1986         rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1987         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1988         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1989 }
1990
1991 #define POWER_BOUND             0x27
1992 #define FREQ_OFFSET_BOUND       0x5f
1993
1994 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1995                                          struct ieee80211_conf *conf,
1996                                          struct rf_channel *rf,
1997                                          struct channel_info *info)
1998 {
1999         u8 rfcsr;
2000
2001         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2002         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2003         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2004         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2005         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2006
2007         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2008         if (info->default_power1 > POWER_BOUND)
2009                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2010         else
2011                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2012         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2013
2014         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2015         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2016                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2017         else
2018                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2019         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2020
2021         if (rf->channel <= 14) {
2022                 if (rf->channel == 6)
2023                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2024                 else
2025                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2026
2027                 if (rf->channel >= 1 && rf->channel <= 6)
2028                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2029                 else if (rf->channel >= 7 && rf->channel <= 11)
2030                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2031                 else if (rf->channel >= 12 && rf->channel <= 14)
2032                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2033         }
2034 }
2035
2036 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2037                                          struct ieee80211_conf *conf,
2038                                          struct rf_channel *rf,
2039                                          struct channel_info *info)
2040 {
2041         u8 rfcsr;
2042
2043         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2044         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2045
2046         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2047         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2048         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2049
2050         if (info->default_power1 > POWER_BOUND)
2051                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2052         else
2053                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2054
2055         if (info->default_power2 > POWER_BOUND)
2056                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2057         else
2058                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2059
2060         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2061         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2062                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2063         else
2064                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2065
2066         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2067
2068         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2069         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2070         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2071
2072         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2073                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2074         else
2075                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2076
2077         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2078                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2079         else
2080                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2081
2082         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2083         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2084
2085         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2086
2087         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2088 }
2089
2090 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2091                                          struct ieee80211_conf *conf,
2092                                          struct rf_channel *rf,
2093                                          struct channel_info *info)
2094 {
2095         u8 rfcsr;
2096
2097         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2098         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2099         rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
2100         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2101         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2102
2103         rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2104         if (info->default_power1 > POWER_BOUND)
2105                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2106         else
2107                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2108         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2109
2110         if (rt2x00_rt(rt2x00dev, RT5392)) {
2111                 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2112                 if (info->default_power1 > POWER_BOUND)
2113                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2114                 else
2115                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2116                                           info->default_power2);
2117                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2118         }
2119
2120         rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2121         if (rt2x00_rt(rt2x00dev, RT5392)) {
2122                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2123                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2124         }
2125         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2126         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2127         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2128         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2129         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2130
2131         rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2132         if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2133                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2134         else
2135                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2136         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2137
2138         if (rf->channel <= 14) {
2139                 int idx = rf->channel-1;
2140
2141                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2142                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2143                                 /* r55/r59 value array of channel 1~14 */
2144                                 static const char r55_bt_rev[] = {0x83, 0x83,
2145                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2146                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2147                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2148                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2149                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2150
2151                                 rt2800_rfcsr_write(rt2x00dev, 55,
2152                                                    r55_bt_rev[idx]);
2153                                 rt2800_rfcsr_write(rt2x00dev, 59,
2154                                                    r59_bt_rev[idx]);
2155                         } else {
2156                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2157                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2158                                         0x88, 0x88, 0x86, 0x85, 0x84};
2159
2160                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2161                         }
2162                 } else {
2163                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2164                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2165                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2166                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2167                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2168                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2169                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2170
2171                                 rt2800_rfcsr_write(rt2x00dev, 55,
2172                                                    r55_nonbt_rev[idx]);
2173                                 rt2800_rfcsr_write(rt2x00dev, 59,
2174                                                    r59_nonbt_rev[idx]);
2175                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2176                                            rt2x00_rt(rt2x00dev, RT5392)) {
2177                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2178                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2179                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2180
2181                                 rt2800_rfcsr_write(rt2x00dev, 59,
2182                                                    r59_non_bt[idx]);
2183                         }
2184                 }
2185         }
2186 }
2187
2188 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2189                                   struct ieee80211_conf *conf,
2190                                   struct rf_channel *rf,
2191                                   struct channel_info *info)
2192 {
2193         u32 reg;
2194         unsigned int tx_pin;
2195         u8 bbp, rfcsr;
2196
2197         if (rf->channel <= 14) {
2198                 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2199                 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2200         } else {
2201                 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2202                 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2203         }
2204
2205         switch (rt2x00dev->chip.rf) {
2206         case RF2020:
2207         case RF3020:
2208         case RF3021:
2209         case RF3022:
2210         case RF3320:
2211                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2212                 break;
2213         case RF3052:
2214                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2215                 break;
2216         case RF3290:
2217                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2218                 break;
2219         case RF3322:
2220                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2221                 break;
2222         case RF5360:
2223         case RF5370:
2224         case RF5372:
2225         case RF5390:
2226         case RF5392:
2227                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2228                 break;
2229         default:
2230                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2231         }
2232
2233         if (rt2x00_rf(rt2x00dev, RF3290) ||
2234             rt2x00_rf(rt2x00dev, RF3322) ||
2235             rt2x00_rf(rt2x00dev, RF5360) ||
2236             rt2x00_rf(rt2x00dev, RF5370) ||
2237             rt2x00_rf(rt2x00dev, RF5372) ||
2238             rt2x00_rf(rt2x00dev, RF5390) ||
2239             rt2x00_rf(rt2x00dev, RF5392)) {
2240                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2241                 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2242                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2243                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2244
2245                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2246                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2247                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2248         }
2249
2250         /*
2251          * Change BBP settings
2252          */
2253         if (rt2x00_rt(rt2x00dev, RT3352)) {
2254                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2255                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2256                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2257                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
2258         } else {
2259                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2260                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2261                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2262                 rt2800_bbp_write(rt2x00dev, 86, 0);
2263         }
2264
2265         if (rf->channel <= 14) {
2266                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2267                         !rt2x00_rt(rt2x00dev, RT5392)) {
2268                         if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2269                                      &rt2x00dev->cap_flags)) {
2270                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2271                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2272                         } else {
2273                                 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2274                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2275                         }
2276                 }
2277         } else {
2278                 if (rt2x00_rt(rt2x00dev, RT3572))
2279                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
2280                 else
2281                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2282
2283                 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2284                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
2285                 else
2286                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
2287         }
2288
2289         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
2290         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2291         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
2292         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
2293         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2294
2295         if (rt2x00_rt(rt2x00dev, RT3572))
2296                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2297
2298         tx_pin = 0;
2299
2300         /* Turn on unused PA or LNA when not using 1T or 1R */
2301         if (rt2x00dev->default_ant.tx_chain_num == 2) {
2302                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2303                                    rf->channel > 14);
2304                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2305                                    rf->channel <= 14);
2306         }
2307
2308         /* Turn on unused PA or LNA when not using 1T or 1R */
2309         if (rt2x00dev->default_ant.rx_chain_num == 2) {
2310                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2311                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2312         }
2313
2314         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2315         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2316         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2317         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2318         if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2319                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2320         else
2321                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2322                                    rf->channel <= 14);
2323         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2324
2325         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2326
2327         if (rt2x00_rt(rt2x00dev, RT3572))
2328                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2329
2330         rt2800_bbp_read(rt2x00dev, 4, &bbp);
2331         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2332         rt2800_bbp_write(rt2x00dev, 4, bbp);
2333
2334         rt2800_bbp_read(rt2x00dev, 3, &bbp);
2335         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2336         rt2800_bbp_write(rt2x00dev, 3, bbp);
2337
2338         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2339                 if (conf_is_ht40(conf)) {
2340                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2341                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2342                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
2343                 } else {
2344                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
2345                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
2346                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
2347                 }
2348         }
2349
2350         msleep(1);
2351
2352         /*
2353          * Clear channel statistic counters
2354          */
2355         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2356         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2357         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2358
2359         /*
2360          * Clear update flag
2361          */
2362         if (rt2x00_rt(rt2x00dev, RT3352)) {
2363                 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2364                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2365                 rt2800_bbp_write(rt2x00dev, 49, bbp);
2366         }
2367 }
2368
2369 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2370 {
2371         u8 tssi_bounds[9];
2372         u8 current_tssi;
2373         u16 eeprom;
2374         u8 step;
2375         int i;
2376
2377         /*
2378          * Read TSSI boundaries for temperature compensation from
2379          * the EEPROM.
2380          *
2381          * Array idx               0    1    2    3    4    5    6    7    8
2382          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
2383          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2384          */
2385         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2386                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2387                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2388                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
2389                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2390                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
2391
2392                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2393                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2394                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
2395                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2396                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
2397
2398                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2399                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2400                                         EEPROM_TSSI_BOUND_BG3_REF);
2401                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2402                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
2403
2404                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2405                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2406                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
2407                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2408                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
2409
2410                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2411                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2412                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
2413
2414                 step = rt2x00_get_field16(eeprom,
2415                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2416         } else {
2417                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2418                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2419                                         EEPROM_TSSI_BOUND_A1_MINUS4);
2420                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2421                                         EEPROM_TSSI_BOUND_A1_MINUS3);
2422
2423                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2424                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2425                                         EEPROM_TSSI_BOUND_A2_MINUS2);
2426                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2427                                         EEPROM_TSSI_BOUND_A2_MINUS1);
2428
2429                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2430                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2431                                         EEPROM_TSSI_BOUND_A3_REF);
2432                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2433                                         EEPROM_TSSI_BOUND_A3_PLUS1);
2434
2435                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2436                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2437                                         EEPROM_TSSI_BOUND_A4_PLUS2);
2438                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2439                                         EEPROM_TSSI_BOUND_A4_PLUS3);
2440
2441                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2442                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2443                                         EEPROM_TSSI_BOUND_A5_PLUS4);
2444
2445                 step = rt2x00_get_field16(eeprom,
2446                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
2447         }
2448
2449         /*
2450          * Check if temperature compensation is supported.
2451          */
2452         if (tssi_bounds[4] == 0xff || step == 0xff)
2453                 return 0;
2454
2455         /*
2456          * Read current TSSI (BBP 49).
2457          */
2458         rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
2459
2460         /*
2461          * Compare TSSI value (BBP49) with the compensation boundaries
2462          * from the EEPROM and increase or decrease tx power.
2463          */
2464         for (i = 0; i <= 3; i++) {
2465                 if (current_tssi > tssi_bounds[i])
2466                         break;
2467         }
2468
2469         if (i == 4) {
2470                 for (i = 8; i >= 5; i--) {
2471                         if (current_tssi < tssi_bounds[i])
2472                                 break;
2473                 }
2474         }
2475
2476         return (i - 4) * step;
2477 }
2478
2479 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2480                                       enum ieee80211_band band)
2481 {
2482         u16 eeprom;
2483         u8 comp_en;
2484         u8 comp_type;
2485         int comp_value = 0;
2486
2487         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2488
2489         /*
2490          * HT40 compensation not required.
2491          */
2492         if (eeprom == 0xffff ||
2493             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2494                 return 0;
2495
2496         if (band == IEEE80211_BAND_2GHZ) {
2497                 comp_en = rt2x00_get_field16(eeprom,
2498                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
2499                 if (comp_en) {
2500                         comp_type = rt2x00_get_field16(eeprom,
2501                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
2502                         comp_value = rt2x00_get_field16(eeprom,
2503                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
2504                         if (!comp_type)
2505                                 comp_value = -comp_value;
2506                 }
2507         } else {
2508                 comp_en = rt2x00_get_field16(eeprom,
2509                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
2510                 if (comp_en) {
2511                         comp_type = rt2x00_get_field16(eeprom,
2512                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
2513                         comp_value = rt2x00_get_field16(eeprom,
2514                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
2515                         if (!comp_type)
2516                                 comp_value = -comp_value;
2517                 }
2518         }
2519
2520         return comp_value;
2521 }
2522
2523 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2524                                    enum ieee80211_band band, int power_level,
2525                                    u8 txpower, int delta)
2526 {
2527         u32 reg;
2528         u16 eeprom;
2529         u8 criterion;
2530         u8 eirp_txpower;
2531         u8 eirp_txpower_criterion;
2532         u8 reg_limit;
2533
2534         if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2535                 return txpower;
2536
2537         if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2538                 /*
2539                  * Check if eirp txpower exceed txpower_limit.
2540                  * We use OFDM 6M as criterion and its eirp txpower
2541                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
2542                  * .11b data rate need add additional 4dbm
2543                  * when calculating eirp txpower.
2544                  */
2545                 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
2546                 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2547
2548                 rt2x00_eeprom_read(rt2x00dev,
2549                                    EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2550
2551                 if (band == IEEE80211_BAND_2GHZ)
2552                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2553                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2554                 else
2555                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2556                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2557
2558                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2559                                (is_rate_b ? 4 : 0) + delta;
2560
2561                 reg_limit = (eirp_txpower > power_level) ?
2562                                         (eirp_txpower - power_level) : 0;
2563         } else
2564                 reg_limit = 0;
2565
2566         return txpower + delta - reg_limit;
2567 }
2568
2569 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2570                                   enum ieee80211_band band,
2571                                   int power_level)
2572 {
2573         u8 txpower;
2574         u16 eeprom;
2575         int i, is_rate_b;
2576         u32 reg;
2577         u8 r1;
2578         u32 offset;
2579         int delta;
2580
2581         /*
2582          * Calculate HT40 compensation delta
2583          */
2584         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2585
2586         /*
2587          * calculate temperature compensation delta
2588          */
2589         delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2590
2591         /*
2592          * set to normal bbp tx power control mode: +/- 0dBm
2593          */
2594         rt2800_bbp_read(rt2x00dev, 1, &r1);
2595         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2596         rt2800_bbp_write(rt2x00dev, 1, r1);
2597         offset = TX_PWR_CFG_0;
2598
2599         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2600                 /* just to be safe */
2601                 if (offset > TX_PWR_CFG_4)
2602                         break;
2603
2604                 rt2800_register_read(rt2x00dev, offset, &reg);
2605
2606                 /* read the next four txpower values */
2607                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2608                                    &eeprom);
2609
2610                 is_rate_b = i ? 0 : 1;
2611                 /*
2612                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2613                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2614                  * TX_PWR_CFG_4: unknown
2615                  */
2616                 txpower = rt2x00_get_field16(eeprom,
2617                                              EEPROM_TXPOWER_BYRATE_RATE0);
2618                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2619                                              power_level, txpower, delta);
2620                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
2621
2622                 /*
2623                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2624                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2625                  * TX_PWR_CFG_4: unknown
2626                  */
2627                 txpower = rt2x00_get_field16(eeprom,
2628                                              EEPROM_TXPOWER_BYRATE_RATE1);
2629                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2630                                              power_level, txpower, delta);
2631                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
2632
2633                 /*
2634                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2635                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
2636                  * TX_PWR_CFG_4: unknown
2637                  */
2638                 txpower = rt2x00_get_field16(eeprom,
2639                                              EEPROM_TXPOWER_BYRATE_RATE2);
2640                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2641                                              power_level, txpower, delta);
2642                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
2643
2644                 /*
2645                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2646                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
2647                  * TX_PWR_CFG_4: unknown
2648                  */
2649                 txpower = rt2x00_get_field16(eeprom,
2650                                              EEPROM_TXPOWER_BYRATE_RATE3);
2651                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2652                                              power_level, txpower, delta);
2653                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
2654
2655                 /* read the next four txpower values */
2656                 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2657                                    &eeprom);
2658
2659                 is_rate_b = 0;
2660                 /*
2661                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2662                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2663                  * TX_PWR_CFG_4: unknown
2664                  */
2665                 txpower = rt2x00_get_field16(eeprom,
2666                                              EEPROM_TXPOWER_BYRATE_RATE0);
2667                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2668                                              power_level, txpower, delta);
2669                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
2670
2671                 /*
2672                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2673                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2674                  * TX_PWR_CFG_4: unknown
2675                  */
2676                 txpower = rt2x00_get_field16(eeprom,
2677                                              EEPROM_TXPOWER_BYRATE_RATE1);
2678                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2679                                              power_level, txpower, delta);
2680                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
2681
2682                 /*
2683                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2684                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2685                  * TX_PWR_CFG_4: unknown
2686                  */
2687                 txpower = rt2x00_get_field16(eeprom,
2688                                              EEPROM_TXPOWER_BYRATE_RATE2);
2689                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2690                                              power_level, txpower, delta);
2691                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
2692
2693                 /*
2694                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2695                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2696                  * TX_PWR_CFG_4: unknown
2697                  */
2698                 txpower = rt2x00_get_field16(eeprom,
2699                                              EEPROM_TXPOWER_BYRATE_RATE3);
2700                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2701                                              power_level, txpower, delta);
2702                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
2703
2704                 rt2800_register_write(rt2x00dev, offset, reg);
2705
2706                 /* next TX_PWR_CFG register */
2707                 offset += 4;
2708         }
2709 }
2710
2711 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2712 {
2713         rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2714                               rt2x00dev->tx_power);
2715 }
2716 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2717
2718 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2719 {
2720         u32     tx_pin;
2721         u8      rfcsr;
2722
2723         /*
2724          * A voltage-controlled oscillator(VCO) is an electronic oscillator
2725          * designed to be controlled in oscillation frequency by a voltage
2726          * input. Maybe the temperature will affect the frequency of
2727          * oscillation to be shifted. The VCO calibration will be called
2728          * periodically to adjust the frequency to be precision.
2729         */
2730
2731         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2732         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2733         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2734
2735         switch (rt2x00dev->chip.rf) {
2736         case RF2020:
2737         case RF3020:
2738         case RF3021:
2739         case RF3022:
2740         case RF3320:
2741         case RF3052:
2742                 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2743                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2744                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2745                 break;
2746         case RF3290:
2747         case RF5360:
2748         case RF5370:
2749         case RF5372:
2750         case RF5390:
2751         case RF5392:
2752                 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2753                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2754                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2755                 break;
2756         default:
2757                 return;
2758         }
2759
2760         mdelay(1);
2761
2762         rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2763         if (rt2x00dev->rf_channel <= 14) {
2764                 switch (rt2x00dev->default_ant.tx_chain_num) {
2765                 case 3:
2766                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2767                         /* fall through */
2768                 case 2:
2769                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2770                         /* fall through */
2771                 case 1:
2772                 default:
2773                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2774                         break;
2775                 }
2776         } else {
2777                 switch (rt2x00dev->default_ant.tx_chain_num) {
2778                 case 3:
2779                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2780                         /* fall through */
2781                 case 2:
2782                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2783                         /* fall through */
2784                 case 1:
2785                 default:
2786                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2787                         break;
2788                 }
2789         }
2790         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2791
2792 }
2793 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2794
2795 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2796                                       struct rt2x00lib_conf *libconf)
2797 {
2798         u32 reg;
2799
2800         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
2801         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
2802                            libconf->conf->short_frame_max_tx_count);
2803         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
2804                            libconf->conf->long_frame_max_tx_count);
2805         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2806 }
2807
2808 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2809                              struct rt2x00lib_conf *libconf)
2810 {
2811         enum dev_state state =
2812             (libconf->conf->flags & IEEE80211_CONF_PS) ?
2813                 STATE_SLEEP : STATE_AWAKE;
2814         u32 reg;
2815
2816         if (state == STATE_SLEEP) {
2817                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2818
2819                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2820                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2821                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2822                                    libconf->conf->listen_interval - 1);
2823                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2824                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2825
2826                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2827         } else {
2828                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
2829                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2830                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2831                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2832                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2833
2834                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2835         }
2836 }
2837
2838 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2839                    struct rt2x00lib_conf *libconf,
2840                    const unsigned int flags)
2841 {
2842         /* Always recalculate LNA gain before changing configuration */
2843         rt2800_config_lna_gain(rt2x00dev, libconf);
2844
2845         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2846                 rt2800_config_channel(rt2x00dev, libconf->conf,
2847                                       &libconf->rf, &libconf->channel);
2848                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2849                                       libconf->conf->power_level);
2850         }
2851         if (flags & IEEE80211_CONF_CHANGE_POWER)
2852                 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2853                                       libconf->conf->power_level);
2854         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2855                 rt2800_config_retry_limit(rt2x00dev, libconf);
2856         if (flags & IEEE80211_CONF_CHANGE_PS)
2857                 rt2800_config_ps(rt2x00dev, libconf);
2858 }
2859 EXPORT_SYMBOL_GPL(rt2800_config);
2860
2861 /*
2862  * Link tuning
2863  */
2864 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2865 {
2866         u32 reg;
2867
2868         /*
2869          * Update FCS error count from register.
2870          */
2871         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
2872         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2873 }
2874 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2875
2876 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2877 {
2878         u8 vgc;
2879
2880         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2881                 if (rt2x00_rt(rt2x00dev, RT3070) ||
2882                     rt2x00_rt(rt2x00dev, RT3071) ||
2883                     rt2x00_rt(rt2x00dev, RT3090) ||
2884                     rt2x00_rt(rt2x00dev, RT3290) ||
2885                     rt2x00_rt(rt2x00dev, RT3390) ||
2886                     rt2x00_rt(rt2x00dev, RT3572) ||
2887                     rt2x00_rt(rt2x00dev, RT5390) ||
2888                     rt2x00_rt(rt2x00dev, RT5392))
2889                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
2890                 else
2891                         vgc = 0x2e + rt2x00dev->lna_gain;
2892         } else { /* 5GHZ band */
2893                 if (rt2x00_rt(rt2x00dev, RT3572))
2894                         vgc = 0x22 + (rt2x00dev->lna_gain * 5) / 3;
2895                 else {
2896                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2897                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2898                         else
2899                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2900                 }
2901         }
2902
2903         return vgc;
2904 }
2905
2906 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2907                                   struct link_qual *qual, u8 vgc_level)
2908 {
2909         if (qual->vgc_level != vgc_level) {
2910                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2911                 qual->vgc_level = vgc_level;
2912                 qual->vgc_level_reg = vgc_level;
2913         }
2914 }
2915
2916 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2917 {
2918         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2919 }
2920 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2921
2922 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2923                        const u32 count)
2924 {
2925         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2926                 return;
2927
2928         /*
2929          * When RSSI is better then -80 increase VGC level with 0x10
2930          */
2931         rt2800_set_vgc(rt2x00dev, qual,
2932                        rt2800_get_default_vgc(rt2x00dev) +
2933                        ((qual->rssi > -80) * 0x10));
2934 }
2935 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2936
2937 /*
2938  * Initialization functions.
2939  */
2940 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2941 {
2942         u32 reg;
2943         u16 eeprom;
2944         unsigned int i;
2945         int ret;
2946
2947         rt2800_disable_wpdma(rt2x00dev);
2948
2949         ret = rt2800_drv_init_registers(rt2x00dev);
2950         if (ret)
2951                 return ret;
2952
2953         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
2954         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2955         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2956         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2957         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2958         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2959
2960         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
2961         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2962         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2963         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2964         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2965         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2966
2967         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2968         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2969
2970         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2971
2972         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2973         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2974         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
2975         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
2976         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
2977         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2978         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2979         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2980
2981         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2982
2983         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
2984         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2985         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2986         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2987
2988         if (rt2x00_rt(rt2x00dev, RT3290)) {
2989                 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
2990                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
2991                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
2992                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
2993                 }
2994
2995                 rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
2996                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
2997                         rt2x00_set_field32(&reg, LDO0_EN, 1);
2998                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
2999                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
3000                 }
3001
3002                 rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
3003                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
3004                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
3005                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
3006                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
3007
3008                 rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
3009                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
3010                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
3011
3012                 rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
3013                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
3014                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
3015                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
3016                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
3017                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
3018
3019                 rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
3020                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
3021                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
3022         }
3023
3024         if (rt2x00_rt(rt2x00dev, RT3071) ||
3025             rt2x00_rt(rt2x00dev, RT3090) ||
3026             rt2x00_rt(rt2x00dev, RT3290) ||
3027             rt2x00_rt(rt2x00dev, RT3390)) {
3028
3029                 if (rt2x00_rt(rt2x00dev, RT3290))
3030                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3031                                               0x00000404);
3032                 else
3033                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
3034                                               0x00000400);
3035
3036                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3037                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3038                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
3039                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
3040                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3041                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
3042                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3043                                                       0x0000002c);
3044                         else
3045                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
3046                                                       0x0000000f);
3047                 } else {
3048                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3049                 }
3050         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
3051                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3052
3053                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3054                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3055                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
3056                 } else {
3057                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3058                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3059                 }
3060         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3061                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3062                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3063                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3064         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3065                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3066                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3067                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3068         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3069                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3070                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3071         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3072                    rt2x00_rt(rt2x00dev, RT5392)) {
3073                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
3074                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3075                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3076         } else {
3077                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
3078                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3079         }
3080
3081         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
3082         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
3083         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
3084         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
3085         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
3086         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
3087         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
3088         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
3089         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
3090         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
3091
3092         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
3093         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
3094         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
3095         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
3096         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
3097
3098         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
3099         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
3100         if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
3101             rt2x00_rt(rt2x00dev, RT2883) ||
3102             rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
3103                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
3104         else
3105                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
3106         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
3107         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
3108         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
3109
3110         rt2800_register_read(rt2x00dev, LED_CFG, &reg);
3111         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
3112         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
3113         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
3114         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
3115         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
3116         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
3117         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
3118         rt2800_register_write(rt2x00dev, LED_CFG, reg);
3119
3120         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
3121
3122         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
3123         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
3124         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
3125         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
3126         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
3127         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
3128         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
3129         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
3130
3131         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
3132         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
3133         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
3134         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3135         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
3136         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3137         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3138         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3139         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3140
3141         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3142         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
3143         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
3144         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3145         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3146         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3147         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3148         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3149         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3150         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3151         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
3152         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3153
3154         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3155         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
3156         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3157         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3158         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3159         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3160         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3161         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3162         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3163         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3164         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
3165         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3166
3167         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3168         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3169         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
3170         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3171         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3172         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3173         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3174         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3175         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3176         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3177         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
3178         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3179
3180         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3181         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3182         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
3183         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3184         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3185         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3186         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3187         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3188         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3189         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3190         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
3191         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3192
3193         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3194         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3195         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
3196         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3197         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3198         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3199         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3200         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3201         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3202         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3203         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
3204         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3205
3206         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3207         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3208         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
3209         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3210         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3211         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3212         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3213         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3214         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3215         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3216         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
3217         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3218
3219         if (rt2x00_is_usb(rt2x00dev)) {
3220                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3221
3222                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
3223                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3224                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3225                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3226                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3227                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3228                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3229                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3230                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3231                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3232                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3233         }
3234
3235         /*
3236          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3237          * although it is reserved.
3238          */
3239         rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
3240         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3241         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3242         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3243         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3244         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3245         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3246         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3247         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3248         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3249         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3250         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3251
3252         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
3253
3254         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3255         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3256         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
3257                            IEEE80211_MAX_RTS_THRESHOLD);
3258         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
3259         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3260
3261         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3262
3263         /*
3264          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3265          * time should be set to 16. However, the original Ralink driver uses
3266          * 16 for both and indeed using a value of 10 for CCK SIFS results in
3267          * connection problems with 11g + CTS protection. Hence, use the same
3268          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3269          */
3270         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
3271         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3272         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3273         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3274         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
3275         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3276         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3277
3278         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3279
3280         /*
3281          * ASIC will keep garbage value after boot, clear encryption keys.
3282          */
3283         for (i = 0; i < 4; i++)
3284                 rt2800_register_write(rt2x00dev,
3285                                          SHARED_KEY_MODE_ENTRY(i), 0);
3286
3287         for (i = 0; i < 256; i++) {
3288                 rt2800_config_wcid(rt2x00dev, NULL, i);
3289                 rt2800_delete_wcid_attr(rt2x00dev, i);
3290                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3291         }
3292
3293         /*
3294          * Clear all beacons
3295          */
3296         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3297         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3298         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3299         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3300         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3301         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3302         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3303         rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3304
3305         if (rt2x00_is_usb(rt2x00dev)) {
3306                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3307                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
3308                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3309         } else if (rt2x00_is_pcie(rt2x00dev)) {
3310                 rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
3311                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
3312                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3313         }
3314
3315         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
3316         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
3317         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
3318         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
3319         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
3320         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
3321         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
3322         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
3323         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
3324         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3325
3326         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
3327         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
3328         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
3329         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
3330         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
3331         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
3332         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
3333         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
3334         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
3335         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3336
3337         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
3338         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3339         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3340         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3341         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3342         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3343         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3344         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3345         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3346         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3347
3348         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
3349         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
3350         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
3351         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
3352         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
3353         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3354
3355         /*
3356          * Do not force the BA window size, we use the TXWI to set it
3357          */
3358         rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
3359         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3360         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3361         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3362
3363         /*
3364          * We must clear the error counters.
3365          * These registers are cleared on read,
3366          * so we may pass a useless variable to store the value.
3367          */
3368         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
3369         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
3370         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
3371         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
3372         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
3373         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
3374
3375         /*
3376          * Setup leadtime for pre tbtt interrupt to 6ms
3377          */
3378         rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
3379         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3380         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3381
3382         /*
3383          * Set up channel statistics timer
3384          */
3385         rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
3386         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
3387         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
3388         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
3389         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
3390         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
3391         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3392
3393         return 0;
3394 }
3395
3396 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3397 {
3398         unsigned int i;
3399         u32 reg;
3400
3401         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3402                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
3403                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3404                         return 0;
3405
3406                 udelay(REGISTER_BUSY_DELAY);
3407         }
3408
3409         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3410         return -EACCES;
3411 }
3412
3413 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3414 {
3415         unsigned int i;
3416         u8 value;
3417
3418         /*
3419          * BBP was enabled after firmware was loaded,
3420          * but we need to reactivate it now.
3421          */
3422         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3423         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3424         msleep(1);
3425
3426         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3427                 rt2800_bbp_read(rt2x00dev, 0, &value);
3428                 if ((value != 0xff) && (value != 0x00))
3429                         return 0;
3430                 udelay(REGISTER_BUSY_DELAY);
3431         }
3432
3433         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3434         return -EACCES;
3435 }
3436
3437 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3438 {
3439         unsigned int i;
3440         u16 eeprom;
3441         u8 reg_id;
3442         u8 value;
3443
3444         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3445                      rt2800_wait_bbp_ready(rt2x00dev)))
3446                 return -EACCES;
3447
3448         if (rt2x00_rt(rt2x00dev, RT3352)) {
3449                 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3450                 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3451         }
3452
3453         if (rt2x00_rt(rt2x00dev, RT3290) ||
3454             rt2x00_rt(rt2x00dev, RT5390) ||
3455             rt2x00_rt(rt2x00dev, RT5392)) {
3456                 rt2800_bbp_read(rt2x00dev, 4, &value);
3457                 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3458                 rt2800_bbp_write(rt2x00dev, 4, value);
3459         }
3460
3461         if (rt2800_is_305x_soc(rt2x00dev) ||
3462             rt2x00_rt(rt2x00dev, RT3290) ||
3463             rt2x00_rt(rt2x00dev, RT3352) ||
3464             rt2x00_rt(rt2x00dev, RT3572) ||
3465             rt2x00_rt(rt2x00dev, RT5390) ||
3466             rt2x00_rt(rt2x00dev, RT5392))
3467                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3468
3469         if (rt2x00_rt(rt2x00dev, RT3352))
3470                 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3471
3472         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3473         rt2800_bbp_write(rt2x00dev, 66, 0x38);
3474
3475         if (rt2x00_rt(rt2x00dev, RT3290) ||
3476             rt2x00_rt(rt2x00dev, RT3352) ||
3477             rt2x00_rt(rt2x00dev, RT5390) ||
3478             rt2x00_rt(rt2x00dev, RT5392))
3479                 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3480
3481         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3482                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3483                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3484         } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3485                    rt2x00_rt(rt2x00dev, RT3352) ||
3486                    rt2x00_rt(rt2x00dev, RT5390) ||
3487                    rt2x00_rt(rt2x00dev, RT5392)) {
3488                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3489                 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3490                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3491                 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3492
3493                 if (rt2x00_rt(rt2x00dev, RT3290))
3494                         rt2800_bbp_write(rt2x00dev, 77, 0x58);
3495                 else
3496                         rt2800_bbp_write(rt2x00dev, 77, 0x59);
3497         } else {
3498                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3499                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3500         }
3501
3502         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3503
3504         if (rt2x00_rt(rt2x00dev, RT3070) ||
3505             rt2x00_rt(rt2x00dev, RT3071) ||
3506             rt2x00_rt(rt2x00dev, RT3090) ||
3507             rt2x00_rt(rt2x00dev, RT3390) ||
3508             rt2x00_rt(rt2x00dev, RT3572) ||
3509             rt2x00_rt(rt2x00dev, RT5390) ||
3510             rt2x00_rt(rt2x00dev, RT5392)) {
3511                 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3512                 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3513                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3514         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3515                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3516                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3517         } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3518                 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3519                 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3520                 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3521                 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3522         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3523                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3524                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3525                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3526         } else {
3527                 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3528         }
3529
3530         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3531         if (rt2x00_rt(rt2x00dev, RT3290) ||
3532             rt2x00_rt(rt2x00dev, RT5390) ||
3533             rt2x00_rt(rt2x00dev, RT5392))
3534                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3535         else
3536                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3537
3538         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3539                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3540         else if (rt2x00_rt(rt2x00dev, RT3290) ||
3541                      rt2x00_rt(rt2x00dev, RT5390) ||
3542                      rt2x00_rt(rt2x00dev, RT5392))
3543                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3544         else
3545                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3546
3547         if (rt2x00_rt(rt2x00dev, RT3290) ||
3548             rt2x00_rt(rt2x00dev, RT3352) ||
3549             rt2x00_rt(rt2x00dev, RT5390) ||
3550             rt2x00_rt(rt2x00dev, RT5392))
3551                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3552         else
3553                 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3554
3555         if (rt2x00_rt(rt2x00dev, RT3352) ||
3556             rt2x00_rt(rt2x00dev, RT5392))
3557                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3558
3559         rt2800_bbp_write(rt2x00dev, 91, 0x04);
3560
3561         if (rt2x00_rt(rt2x00dev, RT3290) ||
3562             rt2x00_rt(rt2x00dev, RT3352) ||
3563             rt2x00_rt(rt2x00dev, RT5390) ||
3564             rt2x00_rt(rt2x00dev, RT5392))
3565                 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3566         else
3567                 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3568
3569         if (rt2x00_rt(rt2x00dev, RT5392)) {
3570                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3571                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3572         }
3573
3574         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3575             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3576             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3577             rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3578             rt2x00_rt(rt2x00dev, RT3290) ||
3579             rt2x00_rt(rt2x00dev, RT3352) ||
3580             rt2x00_rt(rt2x00dev, RT3572) ||
3581             rt2x00_rt(rt2x00dev, RT5390) ||
3582             rt2x00_rt(rt2x00dev, RT5392) ||
3583             rt2800_is_305x_soc(rt2x00dev))
3584                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3585         else
3586                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3587
3588         if (rt2x00_rt(rt2x00dev, RT3290) ||
3589             rt2x00_rt(rt2x00dev, RT3352) ||
3590             rt2x00_rt(rt2x00dev, RT5390) ||
3591             rt2x00_rt(rt2x00dev, RT5392))
3592                 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3593
3594         if (rt2800_is_305x_soc(rt2x00dev))
3595                 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3596         else if (rt2x00_rt(rt2x00dev, RT3290))
3597                 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3598         else if (rt2x00_rt(rt2x00dev, RT3352))
3599                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3600         else if (rt2x00_rt(rt2x00dev, RT5390) ||
3601                          rt2x00_rt(rt2x00dev, RT5392))
3602                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3603         else
3604                 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3605
3606         if (rt2x00_rt(rt2x00dev, RT3290) ||
3607             rt2x00_rt(rt2x00dev, RT5390))
3608                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3609         else if (rt2x00_rt(rt2x00dev, RT3352))
3610                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
3611         else if (rt2x00_rt(rt2x00dev, RT5392))
3612                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3613         else
3614                 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3615
3616         if (rt2x00_rt(rt2x00dev, RT3352))
3617                 rt2800_bbp_write(rt2x00dev, 120, 0x50);
3618
3619         if (rt2x00_rt(rt2x00dev, RT3290) ||
3620             rt2x00_rt(rt2x00dev, RT5390) ||
3621             rt2x00_rt(rt2x00dev, RT5392))
3622                 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3623
3624         if (rt2x00_rt(rt2x00dev, RT5392)) {
3625                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3626                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3627         }
3628
3629         if (rt2x00_rt(rt2x00dev, RT3352))
3630                 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
3631
3632         if (rt2x00_rt(rt2x00dev, RT3071) ||
3633             rt2x00_rt(rt2x00dev, RT3090) ||
3634             rt2x00_rt(rt2x00dev, RT3390) ||
3635             rt2x00_rt(rt2x00dev, RT3572) ||
3636             rt2x00_rt(rt2x00dev, RT5390) ||
3637             rt2x00_rt(rt2x00dev, RT5392)) {
3638                 rt2800_bbp_read(rt2x00dev, 138, &value);
3639
3640                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3641                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3642                         value |= 0x20;
3643                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3644                         value &= ~0x02;
3645
3646                 rt2800_bbp_write(rt2x00dev, 138, value);
3647         }
3648
3649         if (rt2x00_rt(rt2x00dev, RT3290)) {
3650                 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3651                 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3652                 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3653                 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3654                 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3655                 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3656                 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3657                 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3658                 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3659                 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3660
3661                 rt2800_bbp_read(rt2x00dev, 47, &value);
3662                 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3663                 rt2800_bbp_write(rt2x00dev, 47, value);
3664
3665                 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3666                 rt2800_bbp_read(rt2x00dev, 3, &value);
3667                 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3668                 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3669                 rt2800_bbp_write(rt2x00dev, 3, value);
3670         }
3671
3672         if (rt2x00_rt(rt2x00dev, RT3352)) {
3673                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
3674                 /* Set ITxBF timeout to 0x9c40=1000msec */
3675                 rt2800_bbp_write(rt2x00dev, 179, 0x02);
3676                 rt2800_bbp_write(rt2x00dev, 180, 0x00);
3677                 rt2800_bbp_write(rt2x00dev, 182, 0x40);
3678                 rt2800_bbp_write(rt2x00dev, 180, 0x01);
3679                 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
3680                 rt2800_bbp_write(rt2x00dev, 179, 0x00);
3681                 /* Reprogram the inband interface to put right values in RXWI */
3682                 rt2800_bbp_write(rt2x00dev, 142, 0x04);
3683                 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
3684                 rt2800_bbp_write(rt2x00dev, 142, 0x06);
3685                 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
3686                 rt2800_bbp_write(rt2x00dev, 142, 0x07);
3687                 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
3688                 rt2800_bbp_write(rt2x00dev, 142, 0x08);
3689                 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
3690
3691                 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
3692         }
3693
3694         if (rt2x00_rt(rt2x00dev, RT5390) ||
3695                 rt2x00_rt(rt2x00dev, RT5392)) {
3696                 int ant, div_mode;
3697
3698                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3699                 div_mode = rt2x00_get_field16(eeprom,
3700                                               EEPROM_NIC_CONF1_ANT_DIVERSITY);
3701                 ant = (div_mode == 3) ? 1 : 0;
3702
3703                 /* check if this is a Bluetooth combo card */
3704                 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3705                         u32 reg;
3706
3707                         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
3708                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
3709                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
3710                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
3711                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
3712                         if (ant == 0)
3713                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
3714                         else if (ant == 1)
3715                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
3716                         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3717                 }
3718
3719                 /* This chip has hardware antenna diversity*/
3720                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3721                         rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3722                         rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3723                         rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3724                 }
3725
3726                 rt2800_bbp_read(rt2x00dev, 152, &value);
3727                 if (ant == 0)
3728                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3729                 else
3730                         rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3731                 rt2800_bbp_write(rt2x00dev, 152, value);
3732
3733                 /* Init frequency calibration */
3734                 rt2800_bbp_write(rt2x00dev, 142, 1);
3735                 rt2800_bbp_write(rt2x00dev, 143, 57);
3736         }
3737
3738         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3739                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3740
3741                 if (eeprom != 0xffff && eeprom != 0x0000) {
3742                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3743                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3744                         rt2800_bbp_write(rt2x00dev, reg_id, value);
3745                 }
3746         }
3747
3748         return 0;
3749 }
3750
3751 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3752                                 bool bw40, u8 rfcsr24, u8 filter_target)
3753 {
3754         unsigned int i;
3755         u8 bbp;
3756         u8 rfcsr;
3757         u8 passband;
3758         u8 stopband;
3759         u8 overtuned = 0;
3760
3761         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3762
3763         rt2800_bbp_read(rt2x00dev, 4, &bbp);
3764         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3765         rt2800_bbp_write(rt2x00dev, 4, bbp);
3766
3767         rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3768         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3769         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3770
3771         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3772         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3773         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3774
3775         /*
3776          * Set power & frequency of passband test tone
3777          */
3778         rt2800_bbp_write(rt2x00dev, 24, 0);
3779
3780         for (i = 0; i < 100; i++) {
3781                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3782                 msleep(1);
3783
3784                 rt2800_bbp_read(rt2x00dev, 55, &passband);
3785                 if (passband)
3786                         break;
3787         }
3788
3789         /*
3790          * Set power & frequency of stopband test tone
3791          */
3792         rt2800_bbp_write(rt2x00dev, 24, 0x06);
3793
3794         for (i = 0; i < 100; i++) {
3795                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3796                 msleep(1);
3797
3798                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3799
3800                 if ((passband - stopband) <= filter_target) {
3801                         rfcsr24++;
3802                         overtuned += ((passband - stopband) == filter_target);
3803                 } else
3804                         break;
3805
3806                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3807         }
3808
3809         rfcsr24 -= !!overtuned;
3810
3811         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3812         return rfcsr24;
3813 }
3814
3815 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3816 {
3817         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3818         u8 rfcsr;
3819         u8 bbp;
3820         u32 reg;
3821         u16 eeprom;
3822
3823         if (!rt2x00_rt(rt2x00dev, RT3070) &&
3824             !rt2x00_rt(rt2x00dev, RT3071) &&
3825             !rt2x00_rt(rt2x00dev, RT3090) &&
3826             !rt2x00_rt(rt2x00dev, RT3290) &&
3827             !rt2x00_rt(rt2x00dev, RT3352) &&
3828             !rt2x00_rt(rt2x00dev, RT3390) &&
3829             !rt2x00_rt(rt2x00dev, RT3572) &&
3830             !rt2x00_rt(rt2x00dev, RT5390) &&
3831             !rt2x00_rt(rt2x00dev, RT5392) &&
3832             !rt2800_is_305x_soc(rt2x00dev))
3833                 return 0;
3834
3835         /*
3836          * Init RF calibration.
3837          */
3838         if (rt2x00_rt(rt2x00dev, RT3290) ||
3839             rt2x00_rt(rt2x00dev, RT5390) ||
3840             rt2x00_rt(rt2x00dev, RT5392)) {
3841                 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3842                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3843                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3844                 msleep(1);
3845                 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3846                 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3847         } else {
3848                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3849                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3850                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3851                 msleep(1);
3852                 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3853                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3854         }
3855
3856         if (rt2x00_rt(rt2x00dev, RT3070) ||
3857             rt2x00_rt(rt2x00dev, RT3071) ||
3858             rt2x00_rt(rt2x00dev, RT3090)) {
3859                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3860                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3861                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3862                 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3863                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3864                 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3865                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3866                 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3867                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3868                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3869                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3870                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3871                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3872                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3873                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3874                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3875                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3876                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3877                 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3878         } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3879                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3880                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3881                 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3882                 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3883                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3884                 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3885                 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3886                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3887                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3888                 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3889                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3890                 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3891                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3892                 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3893                 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3894                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3895                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3896                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3897                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3898                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3899                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3900                 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3901                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3902                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3903                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3904                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3905                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3906                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3907                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3908                 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3909                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3910                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3911                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3912                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3913                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3914                 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3915                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3916                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3917                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3918                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3919                 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3920                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3921                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3922                 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3923                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3924                 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
3925         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3926                 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3927                 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3928                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3929                 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3930                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3931                 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3932                 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3933                 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3934                 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3935                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3936                 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3937                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3938                 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3939                 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3940                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3941                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3942                 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3943                 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3944                 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3945                 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3946                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3947                 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3948                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3949                 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3950                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3951                 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3952                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3953                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3954                 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3955                 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3956                 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3957                 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3958         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3959                 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3960                 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3961                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3962                 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3963                 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3964                 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3965                 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3966                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3967                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3968                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3969                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3970                 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3971                 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3972                 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3973                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3974                 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3975                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3976                 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3977                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3978                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3979                 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3980                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3981                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3982                 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3983                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3984                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3985                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3986                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3987                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3988                 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3989                 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3990         } else if (rt2800_is_305x_soc(rt2x00dev)) {
3991                 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3992                 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3993                 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3994                 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3995                 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3996                 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3997                 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3998                 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3999                 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
4000                 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
4001                 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
4002                 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
4003                 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
4004                 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
4005                 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
4006                 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
4007                 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
4008                 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
4009                 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
4010                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4011                 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
4012                 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
4013                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4014                 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
4015                 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
4016                 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
4017                 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
4018                 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
4019                 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
4020                 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
4021                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4022                 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
4023                 return 0;
4024         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4025                 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4026                 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4027                 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4028                 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4029                 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4030                 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4031                 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4032                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4033                 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4034                 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4035                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4036                 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4037                 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4038                 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4039                 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4040                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4041                 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4042                 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4043                 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4044                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4045                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4046                 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4047                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4048                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4049                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4050                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4051                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4052                 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4053                 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4054                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4055                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4056                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4057                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4058                 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4059                 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4060                 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4061                 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4062                 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4063                 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4064                 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4065                 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4066                 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4067                 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4068                 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4069                 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4070                 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4071                 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4072                 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4073                 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4074                 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4075                 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4076                 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4077                 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4078                 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4079                 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4080                 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4081                 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4082                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4083                 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4084                 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4085                 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4086                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4087                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4088         } else if (rt2x00_rt(rt2x00dev, RT5390)) {
4089                 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
4090                 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4091                 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4092                 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4093                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4094                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4095                 else
4096                         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
4097                 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4098                 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4099                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4100                 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
4101                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4102                 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4103                 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4104                 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4105                 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4106                 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
4107
4108                 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4109                 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4110                 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4111                 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4112                 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4113                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4114                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4115                 else
4116                         rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
4117                 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4118                 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4119                 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4120                 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4121
4122                 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
4123                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4124                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4125                 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4126                 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4127                 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4128                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4129                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4130                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
4131                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4132
4133                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4134                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
4135                 else
4136                         rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
4137                 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4138                 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
4139                 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
4140                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4141                 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4142                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4143                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4144                 else
4145                         rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
4146                 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
4147                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4148                 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4149
4150                 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
4151                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4152                         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
4153                 else
4154                         rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
4155                 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
4156                 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
4157                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
4158                 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
4159                 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
4160                 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
4161
4162                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4163                 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
4164                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
4165                 else
4166                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
4167                 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4168                 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
4169         }       else if (rt2x00_rt(rt2x00dev, RT5392)) {
4170                         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
4171                         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
4172                         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
4173                         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
4174                         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
4175                         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4176                         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
4177                         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
4178                         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
4179                         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
4180                         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
4181                         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4182                         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
4183                         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
4184                         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
4185                         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4186                         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
4187                         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
4188                         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
4189                         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
4190                         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4191                         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
4192                         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
4193                         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
4194                         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
4195                         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4196                         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4197                         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
4198                         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
4199                         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
4200                         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
4201                         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
4202                         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
4203                         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
4204                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
4205                         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
4206                         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
4207                         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
4208                         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
4209                         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
4210                         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
4211                         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
4212                         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
4213                         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
4214                         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
4215                         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
4216                         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
4217                         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
4218                         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
4219                         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
4220                         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
4221                         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
4222                         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
4223                         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
4224                         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
4225                         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
4226                         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
4227                         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
4228                         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
4229         }
4230
4231         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
4232                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4233                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4234                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4235                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4236         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4237                    rt2x00_rt(rt2x00dev, RT3090)) {
4238                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
4239
4240                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4241                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4242                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4243
4244                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4245                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4246                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4247                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
4248                         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4249                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4250                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4251                         else
4252                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4253                 }
4254                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4255
4256                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4257                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4258                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4259         } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4260                 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
4261                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
4262                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4263         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4264                 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4265                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4266                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4267
4268                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4269                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4270                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4271                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4272                 msleep(1);
4273                 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
4274                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4275                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
4276                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4277         }
4278
4279         /*
4280          * Set RX Filter calibration for 20MHz and 40MHz
4281          */
4282         if (rt2x00_rt(rt2x00dev, RT3070)) {
4283                 drv_data->calibration_bw20 =
4284                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4285                 drv_data->calibration_bw40 =
4286                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4287         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4288                    rt2x00_rt(rt2x00dev, RT3090) ||
4289                    rt2x00_rt(rt2x00dev, RT3352) ||
4290                    rt2x00_rt(rt2x00dev, RT3390) ||
4291                    rt2x00_rt(rt2x00dev, RT3572)) {
4292                 drv_data->calibration_bw20 =
4293                         rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4294                 drv_data->calibration_bw40 =
4295                         rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4296         }
4297
4298         /*
4299          * Save BBP 25 & 26 values for later use in channel switching
4300          */
4301         rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4302         rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4303
4304         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4305                 !rt2x00_rt(rt2x00dev, RT5392)) {
4306                 /*
4307                  * Set back to initial state
4308                  */
4309                 rt2800_bbp_write(rt2x00dev, 24, 0);
4310
4311                 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4312                 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4313                 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4314
4315                 /*
4316                  * Set BBP back to BW20
4317                  */
4318                 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4319                 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4320                 rt2800_bbp_write(rt2x00dev, 4, bbp);
4321         }
4322
4323         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4324             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4325             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4326             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4327                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4328
4329         rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
4330         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
4331         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4332
4333         if (!rt2x00_rt(rt2x00dev, RT5390) &&
4334                 !rt2x00_rt(rt2x00dev, RT5392)) {
4335                 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4336                 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4337                 if (rt2x00_rt(rt2x00dev, RT3070) ||
4338                     rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4339                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4340                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4341                         if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4342                                       &rt2x00dev->cap_flags))
4343                                 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4344                 }
4345                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4346                                   drv_data->txmixer_gain_24g);
4347                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4348         }
4349
4350         if (rt2x00_rt(rt2x00dev, RT3090)) {
4351                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4352
4353                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
4354                 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4355                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4356                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4357                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4358                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4359
4360                 rt2800_bbp_write(rt2x00dev, 138, bbp);
4361         }
4362
4363         if (rt2x00_rt(rt2x00dev, RT3071) ||
4364             rt2x00_rt(rt2x00dev, RT3090) ||
4365             rt2x00_rt(rt2x00dev, RT3390)) {
4366                 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4367                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4368                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4369                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4370                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4371                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4372                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4373
4374                 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4375                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4376                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4377
4378                 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4379                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4380                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4381
4382                 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4383                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4384                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4385         }
4386
4387         if (rt2x00_rt(rt2x00dev, RT3070)) {
4388                 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4389                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4390                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4391                 else
4392                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4393                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4394                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4395                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4396                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4397         }
4398
4399         if (rt2x00_rt(rt2x00dev, RT3290)) {
4400                 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4401                 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4402                 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4403         }
4404
4405         if (rt2x00_rt(rt2x00dev, RT5390) ||
4406                 rt2x00_rt(rt2x00dev, RT5392)) {
4407                 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4408                 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4409                 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4410
4411                 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4412                 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4413                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4414
4415                 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4416                 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4417                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4418         }
4419
4420         return 0;
4421 }
4422
4423 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4424 {
4425         u32 reg;
4426         u16 word;
4427
4428         /*
4429          * Initialize all registers.
4430          */
4431         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4432                      rt2800_init_registers(rt2x00dev) ||
4433                      rt2800_init_bbp(rt2x00dev) ||
4434                      rt2800_init_rfcsr(rt2x00dev)))
4435                 return -EIO;
4436
4437         /*
4438          * Send signal to firmware during boot time.
4439          */
4440         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4441
4442         if (rt2x00_is_usb(rt2x00dev) &&
4443             (rt2x00_rt(rt2x00dev, RT3070) ||
4444              rt2x00_rt(rt2x00dev, RT3071) ||
4445              rt2x00_rt(rt2x00dev, RT3572))) {
4446                 udelay(200);
4447                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4448                 udelay(10);
4449         }
4450
4451         /*
4452          * Enable RX.
4453          */
4454         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4455         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4456         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4457         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4458
4459         udelay(50);
4460
4461         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
4462         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4463         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4464         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4465         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4466         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4467
4468         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4469         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
4470         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
4471         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4472
4473         /*
4474          * Initialize LED control
4475          */
4476         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4477         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
4478                            word & 0xff, (word >> 8) & 0xff);
4479
4480         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4481         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
4482                            word & 0xff, (word >> 8) & 0xff);
4483
4484         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4485         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
4486                            word & 0xff, (word >> 8) & 0xff);
4487
4488         return 0;
4489 }
4490 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4491
4492 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4493 {
4494         u32 reg;
4495
4496         rt2800_disable_wpdma(rt2x00dev);
4497
4498         /* Wait for DMA, ignore error */
4499         rt2800_wait_wpdma_ready(rt2x00dev);
4500
4501         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
4502         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
4503         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
4504         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4505 }
4506 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4507
4508 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4509 {
4510         u32 reg;
4511         u16 efuse_ctrl_reg;
4512
4513         if (rt2x00_rt(rt2x00dev, RT3290))
4514                 efuse_ctrl_reg = EFUSE_CTRL_3290;
4515         else
4516                 efuse_ctrl_reg = EFUSE_CTRL;
4517
4518         rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
4519         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4520 }
4521 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4522
4523 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4524 {
4525         u32 reg;
4526         u16 efuse_ctrl_reg;
4527         u16 efuse_data0_reg;
4528         u16 efuse_data1_reg;
4529         u16 efuse_data2_reg;
4530         u16 efuse_data3_reg;
4531
4532         if (rt2x00_rt(rt2x00dev, RT3290)) {
4533                 efuse_ctrl_reg = EFUSE_CTRL_3290;
4534                 efuse_data0_reg = EFUSE_DATA0_3290;
4535                 efuse_data1_reg = EFUSE_DATA1_3290;
4536                 efuse_data2_reg = EFUSE_DATA2_3290;
4537                 efuse_data3_reg = EFUSE_DATA3_3290;
4538         } else {
4539                 efuse_ctrl_reg = EFUSE_CTRL;
4540                 efuse_data0_reg = EFUSE_DATA0;
4541                 efuse_data1_reg = EFUSE_DATA1;
4542                 efuse_data2_reg = EFUSE_DATA2;
4543                 efuse_data3_reg = EFUSE_DATA3;
4544         }
4545         mutex_lock(&rt2x00dev->csr_mutex);
4546
4547         rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
4548         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
4549         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
4550         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
4551         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
4552
4553         /* Wait until the EEPROM has been loaded */
4554         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
4555         /* Apparently the data is read from end to start */
4556         rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
4557         /* The returned value is in CPU order, but eeprom is le */
4558         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4559         rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
4560         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4561         rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
4562         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4563         rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
4564         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4565
4566         mutex_unlock(&rt2x00dev->csr_mutex);
4567 }
4568
4569 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4570 {
4571         unsigned int i;
4572
4573         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4574                 rt2800_efuse_read(rt2x00dev, i);
4575 }
4576 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4577
4578 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4579 {
4580         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4581         u16 word;
4582         u8 *mac;
4583         u8 default_lna_gain;
4584
4585         /*
4586          * Read the EEPROM.
4587          */
4588         rt2800_read_eeprom(rt2x00dev);
4589
4590         /*
4591          * Start validation of the data that has been read.
4592          */
4593         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4594         if (!is_valid_ether_addr(mac)) {
4595                 eth_random_addr(mac);
4596                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4597         }
4598
4599         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
4600         if (word == 0xffff) {
4601                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4602                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4603                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4604                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4605                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
4606         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
4607                    rt2x00_rt(rt2x00dev, RT2872)) {
4608                 /*
4609                  * There is a max of 2 RX streams for RT28x0 series
4610                  */
4611                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4612                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4613                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4614         }
4615
4616         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
4617         if (word == 0xffff) {
4618                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4619                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4620                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4621                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4622                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4623                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4624                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4625                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4626                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4627                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4628                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4629                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4630                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4631                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4632                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4633                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4634                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4635         }
4636
4637         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4638         if ((word & 0x00ff) == 0x00ff) {
4639                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4640                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4641                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4642         }
4643         if ((word & 0xff00) == 0xff00) {
4644                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4645                                    LED_MODE_TXRX_ACTIVITY);
4646                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4647                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4648                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4649                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4650                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4651                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
4652         }
4653
4654         /*
4655          * During the LNA validation we are going to use
4656          * lna0 as correct value. Note that EEPROM_LNA
4657          * is never validated.
4658          */
4659         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4660         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4661
4662         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4663         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4664                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4665         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4666                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4667         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4668
4669         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4670         if ((word & 0x00ff) != 0x00ff) {
4671                 drv_data->txmixer_gain_24g =
4672                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4673         } else {
4674                 drv_data->txmixer_gain_24g = 0;
4675         }
4676
4677         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4678         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4679                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4680         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4681             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4682                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4683                                    default_lna_gain);
4684         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4685
4686         rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4687         if ((word & 0x00ff) != 0x00ff) {
4688                 drv_data->txmixer_gain_5g =
4689                         rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4690         } else {
4691                 drv_data->txmixer_gain_5g = 0;
4692         }
4693
4694         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4695         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4696                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4697         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4698                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4699         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4700
4701         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4702         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4703                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4704         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4705             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4706                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4707                                    default_lna_gain);
4708         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4709
4710         return 0;
4711 }
4712
4713 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4714 {
4715         u32 reg;
4716         u16 value;
4717         u16 eeprom;
4718
4719         /*
4720          * Read EEPROM word for configuration.
4721          */
4722         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4723
4724         /*
4725          * Identify RF chipset by EEPROM value
4726          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4727          * RT53xx: defined in "EEPROM_CHIP_ID" field
4728          */
4729         if (rt2x00_rt(rt2x00dev, RT3290))
4730                 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
4731         else
4732                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
4733
4734         if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4735             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4736             rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4737                 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4738         else
4739                 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4740
4741         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4742                         value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4743
4744         switch (rt2x00dev->chip.rt) {
4745         case RT2860:
4746         case RT2872:
4747         case RT2883:
4748         case RT3070:
4749         case RT3071:
4750         case RT3090:
4751         case RT3290:
4752         case RT3352:
4753         case RT3390:
4754         case RT3572:
4755         case RT5390:
4756         case RT5392:
4757                 break;
4758         default:
4759                 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4760                 return -ENODEV;
4761         }
4762
4763         switch (rt2x00dev->chip.rf) {
4764         case RF2820:
4765         case RF2850:
4766         case RF2720:
4767         case RF2750:
4768         case RF3020:
4769         case RF2020:
4770         case RF3021:
4771         case RF3022:
4772         case RF3052:
4773         case RF3290:
4774         case RF3320:
4775         case RF3322:
4776         case RF5360:
4777         case RF5370:
4778         case RF5372:
4779         case RF5390:
4780         case RF5392:
4781                 break;
4782         default:
4783                 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
4784                       rt2x00dev->chip.rf);
4785                 return -ENODEV;
4786         }
4787
4788         /*
4789          * Identify default antenna configuration.
4790          */
4791         rt2x00dev->default_ant.tx_chain_num =
4792             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4793         rt2x00dev->default_ant.rx_chain_num =
4794             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4795
4796         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4797
4798         if (rt2x00_rt(rt2x00dev, RT3070) ||
4799             rt2x00_rt(rt2x00dev, RT3090) ||
4800             rt2x00_rt(rt2x00dev, RT3352) ||
4801             rt2x00_rt(rt2x00dev, RT3390)) {
4802                 value = rt2x00_get_field16(eeprom,
4803                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4804                 switch (value) {
4805                 case 0:
4806                 case 1:
4807                 case 2:
4808                         rt2x00dev->default_ant.tx = ANTENNA_A;
4809                         rt2x00dev->default_ant.rx = ANTENNA_A;
4810                         break;
4811                 case 3:
4812                         rt2x00dev->default_ant.tx = ANTENNA_A;
4813                         rt2x00dev->default_ant.rx = ANTENNA_B;
4814                         break;
4815                 }
4816         } else {
4817                 rt2x00dev->default_ant.tx = ANTENNA_A;
4818                 rt2x00dev->default_ant.rx = ANTENNA_A;
4819         }
4820
4821         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4822                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4823                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4824         }
4825
4826         /*
4827          * Determine external LNA informations.
4828          */
4829         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4830                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4831         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4832                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4833
4834         /*
4835          * Detect if this device has an hardware controlled radio.
4836          */
4837         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4838                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4839
4840         /*
4841          * Detect if this device has Bluetooth co-existence.
4842          */
4843         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4844                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4845
4846         /*
4847          * Read frequency offset and RF programming sequence.
4848          */
4849         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4850         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4851
4852         /*
4853          * Store led settings, for correct led behaviour.
4854          */
4855 #ifdef CONFIG_RT2X00_LIB_LEDS
4856         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4857         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4858         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4859
4860         rt2x00dev->led_mcu_reg = eeprom;
4861 #endif /* CONFIG_RT2X00_LIB_LEDS */
4862
4863         /*
4864          * Check if support EIRP tx power limit feature.
4865          */
4866         rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4867
4868         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4869                                         EIRP_MAX_TX_POWER_LIMIT)
4870                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4871
4872         return 0;
4873 }
4874
4875 /*
4876  * RF value list for rt28xx
4877  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4878  */
4879 static const struct rf_channel rf_vals[] = {
4880         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4881         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4882         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4883         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4884         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4885         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4886         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4887         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4888         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4889         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4890         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4891         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4892         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4893         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4894
4895         /* 802.11 UNI / HyperLan 2 */
4896         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4897         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4898         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4899         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4900         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4901         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4902         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4903         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4904         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4905         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4906         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4907         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4908
4909         /* 802.11 HyperLan 2 */
4910         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4911         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4912         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4913         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4914         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4915         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4916         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4917         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4918         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4919         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4920         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4921         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4922         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4923         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4924         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4925         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4926
4927         /* 802.11 UNII */
4928         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4929         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4930         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4931         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4932         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4933         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4934         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4935         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4936         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4937         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4938         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4939
4940         /* 802.11 Japan */
4941         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4942         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4943         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4944         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4945         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4946         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4947         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4948 };
4949
4950 /*
4951  * RF value list for rt3xxx
4952  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4953  */
4954 static const struct rf_channel rf_vals_3x[] = {
4955         {1,  241, 2, 2 },
4956         {2,  241, 2, 7 },
4957         {3,  242, 2, 2 },
4958         {4,  242, 2, 7 },
4959         {5,  243, 2, 2 },
4960         {6,  243, 2, 7 },
4961         {7,  244, 2, 2 },
4962         {8,  244, 2, 7 },
4963         {9,  245, 2, 2 },
4964         {10, 245, 2, 7 },
4965         {11, 246, 2, 2 },
4966         {12, 246, 2, 7 },
4967         {13, 247, 2, 2 },
4968         {14, 248, 2, 4 },
4969
4970         /* 802.11 UNI / HyperLan 2 */
4971         {36, 0x56, 0, 4},
4972         {38, 0x56, 0, 6},
4973         {40, 0x56, 0, 8},
4974         {44, 0x57, 0, 0},
4975         {46, 0x57, 0, 2},
4976         {48, 0x57, 0, 4},
4977         {52, 0x57, 0, 8},
4978         {54, 0x57, 0, 10},
4979         {56, 0x58, 0, 0},
4980         {60, 0x58, 0, 4},
4981         {62, 0x58, 0, 6},
4982         {64, 0x58, 0, 8},
4983
4984         /* 802.11 HyperLan 2 */
4985         {100, 0x5b, 0, 8},
4986         {102, 0x5b, 0, 10},
4987         {104, 0x5c, 0, 0},
4988         {108, 0x5c, 0, 4},
4989         {110, 0x5c, 0, 6},
4990         {112, 0x5c, 0, 8},
4991         {116, 0x5d, 0, 0},
4992         {118, 0x5d, 0, 2},
4993         {120, 0x5d, 0, 4},
4994         {124, 0x5d, 0, 8},
4995         {126, 0x5d, 0, 10},
4996         {128, 0x5e, 0, 0},
4997         {132, 0x5e, 0, 4},
4998         {134, 0x5e, 0, 6},
4999         {136, 0x5e, 0, 8},
5000         {140, 0x5f, 0, 0},
5001
5002         /* 802.11 UNII */
5003         {149, 0x5f, 0, 9},
5004         {151, 0x5f, 0, 11},
5005         {153, 0x60, 0, 1},
5006         {157, 0x60, 0, 5},
5007         {159, 0x60, 0, 7},
5008         {161, 0x60, 0, 9},
5009         {165, 0x61, 0, 1},
5010         {167, 0x61, 0, 3},
5011         {169, 0x61, 0, 5},
5012         {171, 0x61, 0, 7},
5013         {173, 0x61, 0, 9},
5014 };
5015
5016 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
5017 {
5018         struct hw_mode_spec *spec = &rt2x00dev->spec;
5019         struct channel_info *info;
5020         char *default_power1;
5021         char *default_power2;
5022         unsigned int i;
5023         u16 eeprom;
5024
5025         /*
5026          * Disable powersaving as default on PCI devices.
5027          */
5028         if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
5029                 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
5030
5031         /*
5032          * Initialize all hw fields.
5033          */
5034         rt2x00dev->hw->flags =
5035             IEEE80211_HW_SIGNAL_DBM |
5036             IEEE80211_HW_SUPPORTS_PS |
5037             IEEE80211_HW_PS_NULLFUNC_STACK |
5038             IEEE80211_HW_AMPDU_AGGREGATION |
5039             IEEE80211_HW_REPORTS_TX_ACK_STATUS;
5040
5041         /*
5042          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
5043          * unless we are capable of sending the buffered frames out after the
5044          * DTIM transmission using rt2x00lib_beacondone. This will send out
5045          * multicast and broadcast traffic immediately instead of buffering it
5046          * infinitly and thus dropping it after some time.
5047          */
5048         if (!rt2x00_is_usb(rt2x00dev))
5049                 rt2x00dev->hw->flags |=
5050                         IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
5051
5052         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
5053         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
5054                                 rt2x00_eeprom_addr(rt2x00dev,
5055                                                    EEPROM_MAC_ADDR_0));
5056
5057         /*
5058          * As rt2800 has a global fallback table we cannot specify
5059          * more then one tx rate per frame but since the hw will
5060          * try several rates (based on the fallback table) we should
5061          * initialize max_report_rates to the maximum number of rates
5062          * we are going to try. Otherwise mac80211 will truncate our
5063          * reported tx rates and the rc algortihm will end up with
5064          * incorrect data.
5065          */
5066         rt2x00dev->hw->max_rates = 1;
5067         rt2x00dev->hw->max_report_rates = 7;
5068         rt2x00dev->hw->max_rate_tries = 1;
5069
5070         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
5071
5072         /*
5073          * Initialize hw_mode information.
5074          */
5075         spec->supported_bands = SUPPORT_BAND_2GHZ;
5076         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
5077
5078         if (rt2x00_rf(rt2x00dev, RF2820) ||
5079             rt2x00_rf(rt2x00dev, RF2720)) {
5080                 spec->num_channels = 14;
5081                 spec->channels = rf_vals;
5082         } else if (rt2x00_rf(rt2x00dev, RF2850) ||
5083                    rt2x00_rf(rt2x00dev, RF2750)) {
5084                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5085                 spec->num_channels = ARRAY_SIZE(rf_vals);
5086                 spec->channels = rf_vals;
5087         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
5088                    rt2x00_rf(rt2x00dev, RF2020) ||
5089                    rt2x00_rf(rt2x00dev, RF3021) ||
5090                    rt2x00_rf(rt2x00dev, RF3022) ||
5091                    rt2x00_rf(rt2x00dev, RF3290) ||
5092                    rt2x00_rf(rt2x00dev, RF3320) ||
5093                    rt2x00_rf(rt2x00dev, RF3322) ||
5094                    rt2x00_rf(rt2x00dev, RF5360) ||
5095                    rt2x00_rf(rt2x00dev, RF5370) ||
5096                    rt2x00_rf(rt2x00dev, RF5372) ||
5097                    rt2x00_rf(rt2x00dev, RF5390) ||
5098                    rt2x00_rf(rt2x00dev, RF5392)) {
5099                 spec->num_channels = 14;
5100                 spec->channels = rf_vals_3x;
5101         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
5102                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
5103                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
5104                 spec->channels = rf_vals_3x;
5105         }
5106
5107         /*
5108          * Initialize HT information.
5109          */
5110         if (!rt2x00_rf(rt2x00dev, RF2020))
5111                 spec->ht.ht_supported = true;
5112         else
5113                 spec->ht.ht_supported = false;
5114
5115         spec->ht.cap =
5116             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5117             IEEE80211_HT_CAP_GRN_FLD |
5118             IEEE80211_HT_CAP_SGI_20 |
5119             IEEE80211_HT_CAP_SGI_40;
5120
5121         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
5122                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
5123
5124         spec->ht.cap |=
5125             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
5126                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
5127
5128         spec->ht.ampdu_factor = 3;
5129         spec->ht.ampdu_density = 4;
5130         spec->ht.mcs.tx_params =
5131             IEEE80211_HT_MCS_TX_DEFINED |
5132             IEEE80211_HT_MCS_TX_RX_DIFF |
5133             ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
5134                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
5135
5136         switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
5137         case 3:
5138                 spec->ht.mcs.rx_mask[2] = 0xff;
5139         case 2:
5140                 spec->ht.mcs.rx_mask[1] = 0xff;
5141         case 1:
5142                 spec->ht.mcs.rx_mask[0] = 0xff;
5143                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
5144                 break;
5145         }
5146
5147         /*
5148          * Create channel information array
5149          */
5150         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
5151         if (!info)
5152                 return -ENOMEM;
5153
5154         spec->channels_info = info;
5155
5156         default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
5157         default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
5158
5159         for (i = 0; i < 14; i++) {
5160                 info[i].default_power1 = default_power1[i];
5161                 info[i].default_power2 = default_power2[i];
5162         }
5163
5164         if (spec->num_channels > 14) {
5165                 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
5166                 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
5167
5168                 for (i = 14; i < spec->num_channels; i++) {
5169                         info[i].default_power1 = default_power1[i];
5170                         info[i].default_power2 = default_power2[i];
5171                 }
5172         }
5173
5174         switch (rt2x00dev->chip.rf) {
5175         case RF2020:
5176         case RF3020:
5177         case RF3021:
5178         case RF3022:
5179         case RF3320:
5180         case RF3052:
5181         case RF3290:
5182         case RF5360:
5183         case RF5370:
5184         case RF5372:
5185         case RF5390:
5186         case RF5392:
5187                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
5188                 break;
5189         }
5190
5191         return 0;
5192 }
5193
5194 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
5195 {
5196         int retval;
5197         u32 reg;
5198
5199         /*
5200          * Allocate eeprom data.
5201          */
5202         retval = rt2800_validate_eeprom(rt2x00dev);
5203         if (retval)
5204                 return retval;
5205
5206         retval = rt2800_init_eeprom(rt2x00dev);
5207         if (retval)
5208                 return retval;
5209
5210         /*
5211          * Enable rfkill polling by setting GPIO direction of the
5212          * rfkill switch GPIO pin correctly.
5213          */
5214         rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
5215         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
5216         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
5217
5218         /*
5219          * Initialize hw specifications.
5220          */
5221         retval = rt2800_probe_hw_mode(rt2x00dev);
5222         if (retval)
5223                 return retval;
5224
5225         /*
5226          * Set device capabilities.
5227          */
5228         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
5229         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
5230         if (!rt2x00_is_usb(rt2x00dev))
5231                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
5232
5233         /*
5234          * Set device requirements.
5235          */
5236         if (!rt2x00_is_soc(rt2x00dev))
5237                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
5238         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
5239         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
5240         if (!rt2800_hwcrypt_disabled(rt2x00dev))
5241                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
5242         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
5243         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
5244         if (rt2x00_is_usb(rt2x00dev))
5245                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
5246         else {
5247                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
5248                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
5249         }
5250
5251         /*
5252          * Set the rssi offset.
5253          */
5254         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
5255
5256         return 0;
5257 }
5258 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
5259
5260 /*
5261  * IEEE80211 stack callback functions.
5262  */
5263 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
5264                          u16 *iv16)
5265 {
5266         struct rt2x00_dev *rt2x00dev = hw->priv;
5267         struct mac_iveiv_entry iveiv_entry;
5268         u32 offset;
5269
5270         offset = MAC_IVEIV_ENTRY(hw_key_idx);
5271         rt2800_register_multiread(rt2x00dev, offset,
5272                                       &iveiv_entry, sizeof(iveiv_entry));
5273
5274         memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
5275         memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
5276 }
5277 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
5278
5279 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5280 {
5281         struct rt2x00_dev *rt2x00dev = hw->priv;
5282         u32 reg;
5283         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
5284
5285         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
5286         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
5287         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5288
5289         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
5290         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
5291         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5292
5293         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
5294         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
5295         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5296
5297         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
5298         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
5299         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5300
5301         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
5302         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
5303         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5304
5305         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
5306         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
5307         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5308
5309         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
5310         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
5311         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5312
5313         return 0;
5314 }
5315 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
5316
5317 int rt2800_conf_tx(struct ieee80211_hw *hw,
5318                    struct ieee80211_vif *vif, u16 queue_idx,
5319                    const struct ieee80211_tx_queue_params *params)
5320 {
5321         struct rt2x00_dev *rt2x00dev = hw->priv;
5322         struct data_queue *queue;
5323         struct rt2x00_field32 field;
5324         int retval;
5325         u32 reg;
5326         u32 offset;
5327
5328         /*
5329          * First pass the configuration through rt2x00lib, that will
5330          * update the queue settings and validate the input. After that
5331          * we are free to update the registers based on the value
5332          * in the queue parameter.
5333          */
5334         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
5335         if (retval)
5336                 return retval;
5337
5338         /*
5339          * We only need to perform additional register initialization
5340          * for WMM queues/
5341          */
5342         if (queue_idx >= 4)
5343                 return 0;
5344
5345         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
5346
5347         /* Update WMM TXOP register */
5348         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
5349         field.bit_offset = (queue_idx & 1) * 16;
5350         field.bit_mask = 0xffff << field.bit_offset;
5351
5352         rt2800_register_read(rt2x00dev, offset, &reg);
5353         rt2x00_set_field32(&reg, field, queue->txop);
5354         rt2800_register_write(rt2x00dev, offset, reg);
5355
5356         /* Update WMM registers */
5357         field.bit_offset = queue_idx * 4;
5358         field.bit_mask = 0xf << field.bit_offset;
5359
5360         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
5361         rt2x00_set_field32(&reg, field, queue->aifs);
5362         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
5363
5364         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
5365         rt2x00_set_field32(&reg, field, queue->cw_min);
5366         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
5367
5368         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
5369         rt2x00_set_field32(&reg, field, queue->cw_max);
5370         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
5371
5372         /* Update EDCA registers */
5373         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
5374
5375         rt2800_register_read(rt2x00dev, offset, &reg);
5376         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
5377         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
5378         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
5379         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
5380         rt2800_register_write(rt2x00dev, offset, reg);
5381
5382         return 0;
5383 }
5384 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
5385
5386 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
5387 {
5388         struct rt2x00_dev *rt2x00dev = hw->priv;
5389         u64 tsf;
5390         u32 reg;
5391
5392         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
5393         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
5394         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
5395         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
5396
5397         return tsf;
5398 }
5399 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
5400
5401 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5402                         enum ieee80211_ampdu_mlme_action action,
5403                         struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5404                         u8 buf_size)
5405 {
5406         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
5407         int ret = 0;
5408
5409         /*
5410          * Don't allow aggregation for stations the hardware isn't aware
5411          * of because tx status reports for frames to an unknown station
5412          * always contain wcid=255 and thus we can't distinguish between
5413          * multiple stations which leads to unwanted situations when the
5414          * hw reorders frames due to aggregation.
5415          */
5416         if (sta_priv->wcid < 0)
5417                 return 1;
5418
5419         switch (action) {
5420         case IEEE80211_AMPDU_RX_START:
5421         case IEEE80211_AMPDU_RX_STOP:
5422                 /*
5423                  * The hw itself takes care of setting up BlockAck mechanisms.
5424                  * So, we only have to allow mac80211 to nagotiate a BlockAck
5425                  * agreement. Once that is done, the hw will BlockAck incoming
5426                  * AMPDUs without further setup.
5427                  */
5428                 break;
5429         case IEEE80211_AMPDU_TX_START:
5430                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5431                 break;
5432         case IEEE80211_AMPDU_TX_STOP:
5433                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5434                 break;
5435         case IEEE80211_AMPDU_TX_OPERATIONAL:
5436                 break;
5437         default:
5438                 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
5439         }
5440
5441         return ret;
5442 }
5443 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
5444
5445 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
5446                       struct survey_info *survey)
5447 {
5448         struct rt2x00_dev *rt2x00dev = hw->priv;
5449         struct ieee80211_conf *conf = &hw->conf;
5450         u32 idle, busy, busy_ext;
5451
5452         if (idx != 0)
5453                 return -ENOENT;
5454
5455         survey->channel = conf->channel;
5456
5457         rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
5458         rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
5459         rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
5460
5461         if (idle || busy) {
5462                 survey->filled = SURVEY_INFO_CHANNEL_TIME |
5463                                  SURVEY_INFO_CHANNEL_TIME_BUSY |
5464                                  SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
5465
5466                 survey->channel_time = (idle + busy) / 1000;
5467                 survey->channel_time_busy = busy / 1000;
5468                 survey->channel_time_ext_busy = busy_ext / 1000;
5469         }
5470
5471         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
5472                 survey->filled |= SURVEY_INFO_IN_USE;
5473
5474         return 0;
5475
5476 }
5477 EXPORT_SYMBOL_GPL(rt2800_get_survey);
5478
5479 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
5480 MODULE_VERSION(DRV_VERSION);
5481 MODULE_DESCRIPTION("Ralink RT2800 library");
5482 MODULE_LICENSE("GPL");