drivers/net/wireless/ath/ath9k/eeprom_4k.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9002_phy.h"
  20
  21 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  22 {
  23         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  24 }
  25
  26 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  27 {
  28         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  29 }
  30
  31 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  32
  33 static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  34 {
  35         struct ath_common *common = ath9k_hw_common(ah);
  36         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  37         int addr, eep_start_loc = 64;
  38
  39         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  40                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  41                         ath_dbg(common, EEPROM,
  42                                 "Unable to read eeprom region\n");
  43                         return false;
  44                 }
  45                 eep_data++;
  46         }
  47
  48         return true;
  49 }
  50
  51 static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
  52 {
  53         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  54
  55         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
  56
  57         return true;
  58 }
  59
  60 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  61 {
  62         struct ath_common *common = ath9k_hw_common(ah);
  63
  64         if (!ath9k_hw_use_flash(ah)) {
  65                 ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n");
  66         }
  67
  68         if (common->bus_ops->ath_bus_type == ATH_USB)
  69                 return __ath9k_hw_usb_4k_fill_eeprom(ah);
  70         else
  71                 return __ath9k_hw_4k_fill_eeprom(ah);
  72 }
  73
  74 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
  75 static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size,
  76                                       struct modal_eep_4k_header *modal_hdr)
  77 {
  78         PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
  79         PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
  80         PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
  81         PR_EEP("Switch Settle", modal_hdr->switchSettling);
  82         PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]);
  83         PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]);
  84         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
  85         PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize);
  86         PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]);
  87         PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
  88         PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn);
  89         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
  90         PR_EEP("CCA Threshold)", modal_hdr->thresh62);
  91         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
  92         PR_EEP("xpdGain", modal_hdr->xpdGain);
  93         PR_EEP("External PD", modal_hdr->xpd);
  94         PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]);
  95         PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]);
  96         PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap);
  97         PR_EEP("O/D Bias Version", modal_hdr->version);
  98         PR_EEP("CCK OutputBias", modal_hdr->ob_0);
  99         PR_EEP("BPSK OutputBias", modal_hdr->ob_1);
 100         PR_EEP("QPSK OutputBias", modal_hdr->ob_2);
 101         PR_EEP("16QAM OutputBias", modal_hdr->ob_3);
 102         PR_EEP("64QAM OutputBias", modal_hdr->ob_4);
 103         PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0);
 104         PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1);
 105         PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2);
 106         PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3);
 107         PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4);
 108         PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0);
 109         PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1);
 110         PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2);
 111         PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3);
 112         PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4);
 113         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
 114         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
 115         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
 116         PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc);
 117         PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]);
 118         PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]);
 119         PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40);
 120         PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]);
 121         PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]);
 122         PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1);
 123         PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2);
 124         PR_EEP("TX Diversity", modal_hdr->tx_diversity);
 125
 126         return len;
 127 }
 128
 129 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 130                                        u8 *buf, u32 len, u32 size)
 131 {
 132         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 133         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 134
 135         if (!dump_base_hdr) {
 136                 len += snprintf(buf + len, size - len,
 137                                 "%20s :\n", "2GHz modal Header");
 138                 len = ath9k_dump_4k_modal_eeprom(buf, len, size,
 139                                                   &eep->modalHeader);
 140                 goto out;
 141         }
 142
 143         PR_EEP("Major Version", pBase->version >> 12);
 144         PR_EEP("Minor Version", pBase->version & 0xFFF);
 145         PR_EEP("Checksum", pBase->checksum);
 146         PR_EEP("Length", pBase->length);
 147         PR_EEP("RegDomain1", pBase->regDmn[0]);
 148         PR_EEP("RegDomain2", pBase->regDmn[1]);
 149         PR_EEP("TX Mask", pBase->txMask);
 150         PR_EEP("RX Mask", pBase->rxMask);
 151         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
 152         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G));
 153         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags &
 154                                         AR5416_OPFLAGS_N_2G_HT20));
 155         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags &
 156                                         AR5416_OPFLAGS_N_2G_HT40));
 157         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags &
 158                                         AR5416_OPFLAGS_N_5G_HT20));
 159         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
 160                                         AR5416_OPFLAGS_N_5G_HT40));
 161         PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
 162         PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
 163         PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
 164         PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
 165         PR_EEP("TX Gain type", pBase->txGainType);
 166
 167         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
 168                         pBase->macAddr);
 169
 170 out:
 171         if (len > size)
 172                 len = size;
 173
 174         return len;
 175 }
 176 #else
 177 static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
 178                                        u8 *buf, u32 len, u32 size)
 179 {
 180         return 0;
 181 }
 182 #endif
 183
 184
 185 #undef SIZE_EEPROM_4K
 186
 187 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 188 {
 189 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 190         struct ath_common *common = ath9k_hw_common(ah);
 191         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 192         u16 *eepdata, temp, magic, magic2;
 193         u32 sum = 0, el;
 194         bool need_swap = false;
 195         int i, addr;
 196
 197
 198         if (!ath9k_hw_use_flash(ah)) {
 199                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
 200                                          &magic)) {
 201                         ath_err(common, "Reading Magic # failed\n");
 202                         return false;
 203                 }
 204
 205                 ath_dbg(common, EEPROM, "Read Magic = 0x%04X\n", magic);
 206
 207                 if (magic != AR5416_EEPROM_MAGIC) {
 208                         magic2 = swab16(magic);
 209
 210                         if (magic2 == AR5416_EEPROM_MAGIC) {
 211                                 need_swap = true;
 212                                 eepdata = (u16 *) (&ah->eeprom);
 213
 214                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
 215                                         temp = swab16(*eepdata);
 216                                         *eepdata = temp;
 217                                         eepdata++;
 218                                 }
 219                         } else {
 220                                 ath_err(common,
 221                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
 222                                 return -EINVAL;
 223                         }
 224                 }
 225         }
 226
 227         ath_dbg(common, EEPROM, "need_swap = %s\n",
 228                 need_swap ? "True" : "False");
 229
 230         if (need_swap)
 231                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 232         else
 233                 el = ah->eeprom.map4k.baseEepHeader.length;
 234
 235         if (el > sizeof(struct ar5416_eeprom_4k))
 236                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 237         else
 238                 el = el / sizeof(u16);
 239
 240         eepdata = (u16 *)(&ah->eeprom);
 241
 242         for (i = 0; i < el; i++)
 243                 sum ^= *eepdata++;
 244
 245         if (need_swap) {
 246                 u32 integer;
 247                 u16 word;
 248
 249                 ath_dbg(common, EEPROM,
 250                         "EEPROM Endianness is not native.. Changing\n");
 251
 252                 word = swab16(eep->baseEepHeader.length);
 253                 eep->baseEepHeader.length = word;
 254
 255                 word = swab16(eep->baseEepHeader.checksum);
 256                 eep->baseEepHeader.checksum = word;
 257
 258                 word = swab16(eep->baseEepHeader.version);
 259                 eep->baseEepHeader.version = word;
 260
 261                 word = swab16(eep->baseEepHeader.regDmn[0]);
 262                 eep->baseEepHeader.regDmn[0] = word;
 263
 264                 word = swab16(eep->baseEepHeader.regDmn[1]);
 265                 eep->baseEepHeader.regDmn[1] = word;
 266
 267                 word = swab16(eep->baseEepHeader.rfSilent);
 268                 eep->baseEepHeader.rfSilent = word;
 269
 270                 word = swab16(eep->baseEepHeader.blueToothOptions);
 271                 eep->baseEepHeader.blueToothOptions = word;
 272
 273                 word = swab16(eep->baseEepHeader.deviceCap);
 274                 eep->baseEepHeader.deviceCap = word;
 275
 276                 integer = swab32(eep->modalHeader.antCtrlCommon);
 277                 eep->modalHeader.antCtrlCommon = integer;
 278
 279                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 280                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 281                         eep->modalHeader.antCtrlChain[i] = integer;
 282                 }
 283
 284                 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 285                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 286                         eep->modalHeader.spurChans[i].spurChan = word;
 287                 }
 288         }
 289
 290         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 291             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 292                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 293                         sum, ah->eep_ops->get_eeprom_ver(ah));
 294                 return -EINVAL;
 295         }
 296
 297         return 0;
 298 #undef EEPROM_4K_SIZE
 299 }
 300
 301 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 302                                   enum eeprom_param param)
 303 {
 304         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 305         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 306         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 307         u16 ver_minor;
 308
 309         ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 310
 311         switch (param) {
 312         case EEP_NFTHRESH_2:
 313                 return pModal->noiseFloorThreshCh[0];
 314         case EEP_MAC_LSW:
 315                 return get_unaligned_be16(pBase->macAddr);
 316         case EEP_MAC_MID:
 317                 return get_unaligned_be16(pBase->macAddr + 2);
 318         case EEP_MAC_MSW:
 319                 return get_unaligned_be16(pBase->macAddr + 4);
 320         case EEP_REG_0:
 321                 return pBase->regDmn[0];
 322         case EEP_OP_CAP:
 323                 return pBase->deviceCap;
 324         case EEP_OP_MODE:
 325                 return pBase->opCapFlags;
 326         case EEP_RF_SILENT:
 327                 return pBase->rfSilent;
 328         case EEP_OB_2:
 329                 return pModal->ob_0;
 330         case EEP_DB_2:
 331                 return pModal->db1_1;
 332         case EEP_MINOR_REV:
 333                 return ver_minor;
 334         case EEP_TX_MASK:
 335                 return pBase->txMask;
 336         case EEP_RX_MASK:
 337                 return pBase->rxMask;
 338         case EEP_FRAC_N_5G:
 339                 return 0;
 340         case EEP_PWR_TABLE_OFFSET:
 341                 return AR5416_PWR_TABLE_OFFSET_DB;
 342         case EEP_MODAL_VER:
 343                 return pModal->version;
 344         case EEP_ANT_DIV_CTL1:
 345                 return pModal->antdiv_ctl1;
 346         case EEP_TXGAIN_TYPE:
 347                 return pBase->txGainType;
 348         case EEP_ANTENNA_GAIN_2G:
 349                 return pModal->antennaGainCh[0];
 350         default:
 351                 return 0;
 352         }
 353 }
 354
 355 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 356                                   struct ath9k_channel *chan)
 357 {
 358         struct ath_common *common = ath9k_hw_common(ah);
 359         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 360         struct cal_data_per_freq_4k *pRawDataset;
 361         u8 *pCalBChans = NULL;
 362         u16 pdGainOverlap_t2;
 363         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 364         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 365         u16 numPiers, i, j;
 366         u16 numXpdGain, xpdMask;
 367         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 368         u32 reg32, regOffset, regChainOffset;
 369
 370         xpdMask = pEepData->modalHeader.xpdGain;
 371
 372         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 373             AR5416_EEP_MINOR_VER_2) {
 374                 pdGainOverlap_t2 =
 375                         pEepData->modalHeader.pdGainOverlap;
 376         } else {
 377                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 378                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 379         }
 380
 381         pCalBChans = pEepData->calFreqPier2G;
 382         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 383
 384         numXpdGain = 0;
 385
 386         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 387                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 388                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 389                                 break;
 390                         xpdGainValues[numXpdGain] =
 391                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 392                         numXpdGain++;
 393                 }
 394         }
 395
 396         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 397                       (numXpdGain - 1) & 0x3);
 398         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 399                       xpdGainValues[0]);
 400         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 401                       xpdGainValues[1]);
 402         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 403
 404         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 405                 regChainOffset = i * 0x1000;
 406
 407                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 408                         pRawDataset = pEepData->calPierData2G[i];
 409
 410                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
 411                                             pRawDataset, pCalBChans,
 412                                             numPiers, pdGainOverlap_t2,
 413                                             gainBoundaries,
 414                                             pdadcValues, numXpdGain);
 415
 416                         ENABLE_REGWRITE_BUFFER(ah);
 417
 418                         REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 419                                   SM(pdGainOverlap_t2,
 420                                      AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 421                                   | SM(gainBoundaries[0],
 422                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 423                                   | SM(gainBoundaries[1],
 424                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 425                                   | SM(gainBoundaries[2],
 426                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 427                                   | SM(gainBoundaries[3],
 428                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 429
 430                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 431                         for (j = 0; j < 32; j++) {
 432                                 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
 433                                 REG_WRITE(ah, regOffset, reg32);
 434
 435                                 ath_dbg(common, EEPROM,
 436                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 437                                         i, regChainOffset, regOffset,
 438                                         reg32);
 439                                 ath_dbg(common, EEPROM,
 440                                         "PDADC: Chain %d | "
 441                                         "PDADC %3d Value %3d | "
 442                                         "PDADC %3d Value %3d | "
 443                                         "PDADC %3d Value %3d | "
 444                                         "PDADC %3d Value %3d |\n",
 445                                         i, 4 * j, pdadcValues[4 * j],
 446                                         4 * j + 1, pdadcValues[4 * j + 1],
 447                                         4 * j + 2, pdadcValues[4 * j + 2],
 448                                         4 * j + 3, pdadcValues[4 * j + 3]);
 449
 450                                 regOffset += 4;
 451                         }
 452
 453                         REGWRITE_BUFFER_FLUSH(ah);
 454                 }
 455         }
 456 }
 457
 458 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 459                                                  struct ath9k_channel *chan,
 460                                                  int16_t *ratesArray,
 461                                                  u16 cfgCtl,
 462                                                  u16 antenna_reduction,
 463                                                  u16 powerLimit)
 464 {
 465 #define CMP_TEST_GRP \
 466         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
 467          pEepData->ctlIndex[i])                                         \
 468         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 469             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 470
 471         int i;
 472         u16 twiceMinEdgePower;
 473         u16 twiceMaxEdgePower;
 474         u16 scaledPower = 0, minCtlPower;
 475         u16 numCtlModes;
 476         const u16 *pCtlMode;
 477         u16 ctlMode, freq;
 478         struct chan_centers centers;
 479         struct cal_ctl_data_4k *rep;
 480         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 481         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 482                 0, { 0, 0, 0, 0}
 483         };
 484         struct cal_target_power_leg targetPowerOfdmExt = {
 485                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 486                 0, { 0, 0, 0, 0 }
 487         };
 488         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 489                 0, {0, 0, 0, 0}
 490         };
 491         static const u16 ctlModesFor11g[] = {
 492                 CTL_11B, CTL_11G, CTL_2GHT20,
 493                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 494         };
 495
 496         ath9k_hw_get_channel_centers(ah, chan, &centers);
 497
 498         scaledPower = powerLimit - antenna_reduction;
 499         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 500         pCtlMode = ctlModesFor11g;
 501
 502         ath9k_hw_get_legacy_target_powers(ah, chan,
 503                         pEepData->calTargetPowerCck,
 504                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 505                         &targetPowerCck, 4, false);
 506         ath9k_hw_get_legacy_target_powers(ah, chan,
 507                         pEepData->calTargetPower2G,
 508                         AR5416_NUM_2G_20_TARGET_POWERS,
 509                         &targetPowerOfdm, 4, false);
 510         ath9k_hw_get_target_powers(ah, chan,
 511                         pEepData->calTargetPower2GHT20,
 512                         AR5416_NUM_2G_20_TARGET_POWERS,
 513                         &targetPowerHt20, 8, false);
 514
 515         if (IS_CHAN_HT40(chan)) {
 516                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 517                 ath9k_hw_get_target_powers(ah, chan,
 518                                 pEepData->calTargetPower2GHT40,
 519                                 AR5416_NUM_2G_40_TARGET_POWERS,
 520                                 &targetPowerHt40, 8, true);
 521                 ath9k_hw_get_legacy_target_powers(ah, chan,
 522                                 pEepData->calTargetPowerCck,
 523                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 524                                 &targetPowerCckExt, 4, true);
 525                 ath9k_hw_get_legacy_target_powers(ah, chan,
 526                                 pEepData->calTargetPower2G,
 527                                 AR5416_NUM_2G_20_TARGET_POWERS,
 528                                 &targetPowerOfdmExt, 4, true);
 529         }
 530
 531         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 532                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 533                         (pCtlMode[ctlMode] == CTL_2GHT40);
 534
 535                 if (isHt40CtlMode)
 536                         freq = centers.synth_center;
 537                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 538                         freq = centers.ext_center;
 539                 else
 540                         freq = centers.ctl_center;
 541
 542                 twiceMaxEdgePower = MAX_RATE_POWER;
 543
 544                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 545                              pEepData->ctlIndex[i]; i++) {
 546
 547                         if (CMP_TEST_GRP) {
 548                                 rep = &(pEepData->ctlData[i]);
 549
 550                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
 551                                         freq,
 552                                         rep->ctlEdges[
 553                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
 554                                         IS_CHAN_2GHZ(chan),
 555                                         AR5416_EEP4K_NUM_BAND_EDGES);
 556
 557                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 558                                         twiceMaxEdgePower =
 559                                                 min(twiceMaxEdgePower,
 560                                                     twiceMinEdgePower);
 561                                 } else {
 562                                         twiceMaxEdgePower = twiceMinEdgePower;
 563                                         break;
 564                                 }
 565                         }
 566                 }
 567
 568                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 569
 570                 switch (pCtlMode[ctlMode]) {
 571                 case CTL_11B:
 572                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 573                                 targetPowerCck.tPow2x[i] =
 574                                         min((u16)targetPowerCck.tPow2x[i],
 575                                             minCtlPower);
 576                         }
 577                         break;
 578                 case CTL_11G:
 579                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 580                                 targetPowerOfdm.tPow2x[i] =
 581                                         min((u16)targetPowerOfdm.tPow2x[i],
 582                                             minCtlPower);
 583                         }
 584                         break;
 585                 case CTL_2GHT20:
 586                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 587                                 targetPowerHt20.tPow2x[i] =
 588                                         min((u16)targetPowerHt20.tPow2x[i],
 589                                             minCtlPower);
 590                         }
 591                         break;
 592                 case CTL_11B_EXT:
 593                         targetPowerCckExt.tPow2x[0] =
 594                                 min((u16)targetPowerCckExt.tPow2x[0],
 595                                     minCtlPower);
 596                         break;
 597                 case CTL_11G_EXT:
 598                         targetPowerOfdmExt.tPow2x[0] =
 599                                 min((u16)targetPowerOfdmExt.tPow2x[0],
 600                                     minCtlPower);
 601                         break;
 602                 case CTL_2GHT40:
 603                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 604                                 targetPowerHt40.tPow2x[i] =
 605                                         min((u16)targetPowerHt40.tPow2x[i],
 606                                             minCtlPower);
 607                         }
 608                         break;
 609                 default:
 610                         break;
 611                 }
 612         }
 613
 614         ratesArray[rate6mb] =
 615         ratesArray[rate9mb] =
 616         ratesArray[rate12mb] =
 617         ratesArray[rate18mb] =
 618         ratesArray[rate24mb] =
 619         targetPowerOfdm.tPow2x[0];
 620
 621         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 622         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 623         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 624         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 625
 626         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 627                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 628
 629         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 630         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 631         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 632         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 633
 634         if (IS_CHAN_HT40(chan)) {
 635                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 636                         ratesArray[rateHt40_0 + i] =
 637                                 targetPowerHt40.tPow2x[i];
 638                 }
 639                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 640                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
 641                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 642                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 643         }
 644
 645 #undef CMP_TEST_GRP
 646 }
 647
 648 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 649                                     struct ath9k_channel *chan,
 650                                     u16 cfgCtl,
 651                                     u8 twiceAntennaReduction,
 652                                     u8 powerLimit, bool test)
 653 {
 654         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 655         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 656         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
 657         int16_t ratesArray[Ar5416RateSize];
 658         u8 ht40PowerIncForPdadc = 2;
 659         int i;
 660
 661         memset(ratesArray, 0, sizeof(ratesArray));
 662
 663         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 664             AR5416_EEP_MINOR_VER_2) {
 665                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 666         }
 667
 668         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
 669                                              &ratesArray[0], cfgCtl,
 670                                              twiceAntennaReduction,
 671                                              powerLimit);
 672
 673         ath9k_hw_set_4k_power_cal_table(ah, chan);
 674
 675         regulatory->max_power_level = 0;
 676         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 677                 if (ratesArray[i] > MAX_RATE_POWER)
 678                         ratesArray[i] = MAX_RATE_POWER;
 679
 680                 if (ratesArray[i] > regulatory->max_power_level)
 681                         regulatory->max_power_level = ratesArray[i];
 682         }
 683
 684         if (test)
 685             return;
 686
 687         for (i = 0; i < Ar5416RateSize; i++)
 688                 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
 689
 690         ENABLE_REGWRITE_BUFFER(ah);
 691
 692         /* OFDM power per rate */
 693         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 694                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 695                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 696                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 697                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 698         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 699                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 700                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 701                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 702                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 703
 704         /* CCK power per rate */
 705         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 706                   ATH9K_POW_SM(ratesArray[rate2s], 24)
 707                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
 708                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
 709                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
 710         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 711                   ATH9K_POW_SM(ratesArray[rate11s], 24)
 712                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
 713                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 714                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 715
 716         /* HT20 power per rate */
 717         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 718                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 719                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 720                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 721                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 722         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 723                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 724                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 725                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 726                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 727
 728         /* HT40 power per rate */
 729         if (IS_CHAN_HT40(chan)) {
 730                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 731                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
 732                                        ht40PowerIncForPdadc, 24)
 733                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 734                                          ht40PowerIncForPdadc, 16)
 735                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 736                                          ht40PowerIncForPdadc, 8)
 737                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 738                                          ht40PowerIncForPdadc, 0));
 739                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 740                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
 741                                        ht40PowerIncForPdadc, 24)
 742                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 743                                          ht40PowerIncForPdadc, 16)
 744                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 745                                          ht40PowerIncForPdadc, 8)
 746                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 747                                          ht40PowerIncForPdadc, 0));
 748                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 749                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 750                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 751                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 752                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 753         }
 754
 755         REGWRITE_BUFFER_FLUSH(ah);
 756 }
 757
 758 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
 759                                  struct modal_eep_4k_header *pModal,
 760                                  struct ar5416_eeprom_4k *eep,
 761                                  u8 txRxAttenLocal)
 762 {
 763         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
 764                   pModal->antCtrlChain[0]);
 765
 766         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
 767                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 768                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 769                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 770                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 771                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 772
 773         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 774             AR5416_EEP_MINOR_VER_3) {
 775                 txRxAttenLocal = pModal->txRxAttenCh[0];
 776
 777                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 778                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
 779                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 780                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 781                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 782                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 783                               pModal->xatten2Margin[0]);
 784                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 785                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
 786
 787                 /* Set the block 1 value to block 0 value */
 788                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 789                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 790                               pModal->bswMargin[0]);
 791                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 792                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 793                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 794                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 795                               pModal->xatten2Margin[0]);
 796                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 797                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 798                               pModal->xatten2Db[0]);
 799         }
 800
 801         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 802                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 803         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 804                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 805
 806         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 807                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 808         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 809                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 810 }
 811
 812 /*
 813  * Read EEPROM header info and program the device for correct operation
 814  * given the channel value.
 815  */
 816 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 817                                          struct ath9k_channel *chan)
 818 {
 819         struct modal_eep_4k_header *pModal;
 820         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 821         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 822         u8 txRxAttenLocal;
 823         u8 ob[5], db1[5], db2[5];
 824         u8 ant_div_control1, ant_div_control2;
 825         u8 bb_desired_scale;
 826         u32 regVal;
 827
 828         pModal = &eep->modalHeader;
 829         txRxAttenLocal = 23;
 830
 831         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 832
 833         /* Single chain for 4K EEPROM*/
 834         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
 835
 836         /* Initialize Ant Diversity settings from EEPROM */
 837         if (pModal->version >= 3) {
 838                 ant_div_control1 = pModal->antdiv_ctl1;
 839                 ant_div_control2 = pModal->antdiv_ctl2;
 840
 841                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 842                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
 843
 844                 regVal |= SM(ant_div_control1,
 845                              AR_PHY_9285_ANT_DIV_CTL);
 846                 regVal |= SM(ant_div_control2,
 847                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
 848                 regVal |= SM((ant_div_control2 >> 2),
 849                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
 850                 regVal |= SM((ant_div_control1 >> 1),
 851                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
 852                 regVal |= SM((ant_div_control1 >> 2),
 853                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
 854
 855
 856                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 857                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 858                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 859                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 860                 regVal |= SM((ant_div_control1 >> 3),
 861                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 862
 863                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
 864                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 865         }
 866
 867         if (pModal->version >= 2) {
 868                 ob[0] = pModal->ob_0;
 869                 ob[1] = pModal->ob_1;
 870                 ob[2] = pModal->ob_2;
 871                 ob[3] = pModal->ob_3;
 872                 ob[4] = pModal->ob_4;
 873
 874                 db1[0] = pModal->db1_0;
 875                 db1[1] = pModal->db1_1;
 876                 db1[2] = pModal->db1_2;
 877                 db1[3] = pModal->db1_3;
 878                 db1[4] = pModal->db1_4;
 879
 880                 db2[0] = pModal->db2_0;
 881                 db2[1] = pModal->db2_1;
 882                 db2[2] = pModal->db2_2;
 883                 db2[3] = pModal->db2_3;
 884                 db2[4] = pModal->db2_4;
 885         } else if (pModal->version == 1) {
 886                 ob[0] = pModal->ob_0;
 887                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
 888                 db1[0] = pModal->db1_0;
 889                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
 890                 db2[0] = pModal->db2_0;
 891                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
 892         } else {
 893                 int i;
 894
 895                 for (i = 0; i < 5; i++) {
 896                         ob[i] = pModal->ob_0;
 897                         db1[i] = pModal->db1_0;
 898                         db2[i] = pModal->db1_0;
 899                 }
 900         }
 901
 902         if (AR_SREV_9271(ah)) {
 903                 ath9k_hw_analog_shift_rmw(ah,
 904                                           AR9285_AN_RF2G3,
 905                                           AR9271_AN_RF2G3_OB_cck,
 906                                           AR9271_AN_RF2G3_OB_cck_S,
 907                                           ob[0]);
 908                 ath9k_hw_analog_shift_rmw(ah,
 909                                           AR9285_AN_RF2G3,
 910                                           AR9271_AN_RF2G3_OB_psk,
 911                                           AR9271_AN_RF2G3_OB_psk_S,
 912                                           ob[1]);
 913                 ath9k_hw_analog_shift_rmw(ah,
 914                                           AR9285_AN_RF2G3,
 915                                           AR9271_AN_RF2G3_OB_qam,
 916                                           AR9271_AN_RF2G3_OB_qam_S,
 917                                           ob[2]);
 918                 ath9k_hw_analog_shift_rmw(ah,
 919                                           AR9285_AN_RF2G3,
 920                                           AR9271_AN_RF2G3_DB_1,
 921                                           AR9271_AN_RF2G3_DB_1_S,
 922                                           db1[0]);
 923                 ath9k_hw_analog_shift_rmw(ah,
 924                                           AR9285_AN_RF2G4,
 925                                           AR9271_AN_RF2G4_DB_2,
 926                                           AR9271_AN_RF2G4_DB_2_S,
 927                                           db2[0]);
 928         } else {
 929                 ath9k_hw_analog_shift_rmw(ah,
 930                                           AR9285_AN_RF2G3,
 931                                           AR9285_AN_RF2G3_OB_0,
 932                                           AR9285_AN_RF2G3_OB_0_S,
 933                                           ob[0]);
 934                 ath9k_hw_analog_shift_rmw(ah,
 935                                           AR9285_AN_RF2G3,
 936                                           AR9285_AN_RF2G3_OB_1,
 937                                           AR9285_AN_RF2G3_OB_1_S,
 938                                           ob[1]);
 939                 ath9k_hw_analog_shift_rmw(ah,
 940                                           AR9285_AN_RF2G3,
 941                                           AR9285_AN_RF2G3_OB_2,
 942                                           AR9285_AN_RF2G3_OB_2_S,
 943                                           ob[2]);
 944                 ath9k_hw_analog_shift_rmw(ah,
 945                                           AR9285_AN_RF2G3,
 946                                           AR9285_AN_RF2G3_OB_3,
 947                                           AR9285_AN_RF2G3_OB_3_S,
 948                                           ob[3]);
 949                 ath9k_hw_analog_shift_rmw(ah,
 950                                           AR9285_AN_RF2G3,
 951                                           AR9285_AN_RF2G3_OB_4,
 952                                           AR9285_AN_RF2G3_OB_4_S,
 953                                           ob[4]);
 954
 955                 ath9k_hw_analog_shift_rmw(ah,
 956                                           AR9285_AN_RF2G3,
 957                                           AR9285_AN_RF2G3_DB1_0,
 958                                           AR9285_AN_RF2G3_DB1_0_S,
 959                                           db1[0]);
 960                 ath9k_hw_analog_shift_rmw(ah,
 961                                           AR9285_AN_RF2G3,
 962                                           AR9285_AN_RF2G3_DB1_1,
 963                                           AR9285_AN_RF2G3_DB1_1_S,
 964                                           db1[1]);
 965                 ath9k_hw_analog_shift_rmw(ah,
 966                                           AR9285_AN_RF2G3,
 967                                           AR9285_AN_RF2G3_DB1_2,
 968                                           AR9285_AN_RF2G3_DB1_2_S,
 969                                           db1[2]);
 970                 ath9k_hw_analog_shift_rmw(ah,
 971                                           AR9285_AN_RF2G4,
 972                                           AR9285_AN_RF2G4_DB1_3,
 973                                           AR9285_AN_RF2G4_DB1_3_S,
 974                                           db1[3]);
 975                 ath9k_hw_analog_shift_rmw(ah,
 976                                           AR9285_AN_RF2G4,
 977                                           AR9285_AN_RF2G4_DB1_4,
 978                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
 979
 980                 ath9k_hw_analog_shift_rmw(ah,
 981                                           AR9285_AN_RF2G4,
 982                                           AR9285_AN_RF2G4_DB2_0,
 983                                           AR9285_AN_RF2G4_DB2_0_S,
 984                                           db2[0]);
 985                 ath9k_hw_analog_shift_rmw(ah,
 986                                           AR9285_AN_RF2G4,
 987                                           AR9285_AN_RF2G4_DB2_1,
 988                                           AR9285_AN_RF2G4_DB2_1_S,
 989                                           db2[1]);
 990                 ath9k_hw_analog_shift_rmw(ah,
 991                                           AR9285_AN_RF2G4,
 992                                           AR9285_AN_RF2G4_DB2_2,
 993                                           AR9285_AN_RF2G4_DB2_2_S,
 994                                           db2[2]);
 995                 ath9k_hw_analog_shift_rmw(ah,
 996                                           AR9285_AN_RF2G4,
 997                                           AR9285_AN_RF2G4_DB2_3,
 998                                           AR9285_AN_RF2G4_DB2_3_S,
 999                                           db2[3]);
1000                 ath9k_hw_analog_shift_rmw(ah,
1001                                           AR9285_AN_RF2G4,
1002                                           AR9285_AN_RF2G4_DB2_4,
1003                                           AR9285_AN_RF2G4_DB2_4_S,
1004                                           db2[4]);
1005         }
1006
1007
1008         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1009                       pModal->switchSettling);
1010         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1011                       pModal->adcDesiredSize);
1012
1013         REG_WRITE(ah, AR_PHY_RF_CTL4,
1014                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1015                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1016                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1017                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1018
1019         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1020                       pModal->txEndToRxOn);
1021
1022         if (AR_SREV_9271_10(ah))
1023                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1024                               pModal->txEndToRxOn);
1025         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1026                       pModal->thresh62);
1027         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1028                       pModal->thresh62);
1029
1030         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1031                                                 AR5416_EEP_MINOR_VER_2) {
1032                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1033                               pModal->txFrameToDataStart);
1034                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1035                               pModal->txFrameToPaOn);
1036         }
1037
1038         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1039                                                 AR5416_EEP_MINOR_VER_3) {
1040                 if (IS_CHAN_HT40(chan))
1041                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1042                                       AR_PHY_SETTLING_SWITCH,
1043                                       pModal->swSettleHt40);
1044         }
1045
1046         bb_desired_scale = (pModal->bb_scale_smrt_antenna &
1047                         EEP_4K_BB_DESIRED_SCALE_MASK);
1048         if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
1049                 u32 pwrctrl, mask, clr;
1050
1051                 mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
1052                 pwrctrl = mask * bb_desired_scale;
1053                 clr = mask * 0x1f;
1054                 REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1055                 REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1056                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1057
1058                 mask = BIT(0)|BIT(5)|BIT(15);
1059                 pwrctrl = mask * bb_desired_scale;
1060                 clr = mask * 0x1f;
1061                 REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1062
1063                 mask = BIT(0)|BIT(5);
1064                 pwrctrl = mask * bb_desired_scale;
1065                 clr = mask * 0x1f;
1066                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1067                 REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1068         }
1069 }
1070
1071 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1072 {
1073 #define EEP_MAP4K_SPURCHAN \
1074         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1075         struct ath_common *common = ath9k_hw_common(ah);
1076
1077         u16 spur_val = AR_NO_SPUR;
1078
1079         ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n",
1080                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1081
1082         switch (ah->config.spurmode) {
1083         case SPUR_DISABLE:
1084                 break;
1085         case SPUR_ENABLE_IOCTL:
1086                 spur_val = ah->config.spurchans[i][is2GHz];
1087                 ath_dbg(common, ANI, "Getting spur val from new loc. %d\n",
1088                         spur_val);
1089                 break;
1090         case SPUR_ENABLE_EEPROM:
1091                 spur_val = EEP_MAP4K_SPURCHAN;
1092                 break;
1093         }
1094
1095         return spur_val;
1096
1097 #undef EEP_MAP4K_SPURCHAN
1098 }
1099
1100 const struct eeprom_ops eep_4k_ops = {
1101         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1102         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1103         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1104         .dump_eeprom            = ath9k_hw_4k_dump_eeprom,
1105         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1106         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1107         .set_board_values       = ath9k_hw_4k_set_board_values,
1108         .set_txpower            = ath9k_hw_4k_set_txpower,
1109         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1110 };