drivers/net/ethernet/brocade/bna/bna_hw_defs.h

   1 /*
   2  * Linux network driver for Brocade Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2011 Brocade Communications Systems, Inc.
  15  * All rights reserved
  16  * www.brocade.com
  17  */
  18
  19 /* File for interrupt macros and functions */
  20
  21 #ifndef __BNA_HW_DEFS_H__
  22 #define __BNA_HW_DEFS_H__
  23
  24 #include "bfi_reg.h"
  25
  26 /* SW imposed limits */
  27
  28 #define BFI_ENET_DEF_TXQ                1
  29 #define BFI_ENET_DEF_RXP                1
  30 #define BFI_ENET_DEF_UCAM               1
  31 #define BFI_ENET_DEF_RITSZ              1
  32
  33 #define BFI_ENET_MAX_MCAM               256
  34
  35 #define BFI_INVALID_RID                 -1
  36
  37 #define BFI_IBIDX_SIZE                  4
  38
  39 #define BFI_VLAN_WORD_SHIFT             5       /* 32 bits */
  40 #define BFI_VLAN_WORD_MASK              0x1F
  41 #define BFI_VLAN_BLOCK_SHIFT            9       /* 512 bits */
  42 #define BFI_VLAN_BMASK_ALL              0xFF
  43
  44 #define BFI_COALESCING_TIMER_UNIT       5       /* 5us */
  45 #define BFI_MAX_COALESCING_TIMEO        0xFF    /* in 5us units */
  46 #define BFI_MAX_INTERPKT_COUNT          0xFF
  47 #define BFI_MAX_INTERPKT_TIMEO          0xF     /* in 0.5us units */
  48 #define BFI_TX_COALESCING_TIMEO         20      /* 20 * 5 = 100us */
  49 #define BFI_TX_INTERPKT_COUNT           32
  50 #define BFI_RX_COALESCING_TIMEO         12      /* 12 * 5 = 60us */
  51 #define BFI_RX_INTERPKT_COUNT           6       /* Pkt Cnt = 6 */
  52 #define BFI_RX_INTERPKT_TIMEO           3       /* 3 * 0.5 = 1.5us */
  53
  54 #define BFI_TXQ_WI_SIZE                 64      /* bytes */
  55 #define BFI_RXQ_WI_SIZE                 8       /* bytes */
  56 #define BFI_CQ_WI_SIZE                  16      /* bytes */
  57 #define BFI_TX_MAX_WRR_QUOTA            0xFFF
  58
  59 #define BFI_TX_MAX_VECTORS_PER_WI       4
  60 #define BFI_TX_MAX_VECTORS_PER_PKT      0xFF
  61 #define BFI_TX_MAX_DATA_PER_VECTOR      0xFFFF
  62 #define BFI_TX_MAX_DATA_PER_PKT         0xFFFFFF
  63
  64 /* Small Q buffer size */
  65 #define BFI_SMALL_RXBUF_SIZE            128
  66
  67 #define BFI_TX_MAX_PRIO                 8
  68 #define BFI_TX_PRIO_MAP_ALL             0xFF
  69
  70 /*
  71  *
  72  * Register definitions and macros
  73  *
  74  */
  75
  76 #define BNA_PCI_REG_CT_ADDRSZ           (0x40000)
  77
  78 #define ct_reg_addr_init(_bna, _pcidev)                                 \
  79 {                                                                       \
  80         struct bna_reg_offset reg_offset[] =                            \
  81         {{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK},                         \
  82          {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK},                         \
  83          {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK},                         \
  84          {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} };                       \
  85                                                                         \
  86         (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +           \
  87                                 reg_offset[(_pcidev)->pci_func].fn_int_status;\
  88         (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +             \
  89                                 reg_offset[(_pcidev)->pci_func].fn_int_mask;\
  90 }
  91
  92 #define ct_bit_defn_init(_bna, _pcidev)                                 \
  93 {                                                                       \
  94         (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 |          \
  95                                         __HFN_INT_MBOX_LPU1);           \
  96         (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 |            \
  97                                         __HFN_INT_MBOX_LPU1);           \
  98         (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK);          \
  99         (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK);            \
 100         (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT;              \
 101         (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT;                \
 102 }
 103
 104 #define ct2_reg_addr_init(_bna, _pcidev)                                \
 105 {                                                                       \
 106         (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +           \
 107                                 CT2_HOSTFN_INT_STATUS;                  \
 108         (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +             \
 109                                 CT2_HOSTFN_INTR_MASK;                   \
 110 }
 111
 112 #define ct2_bit_defn_init(_bna, _pcidev)                                \
 113 {                                                                       \
 114         (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 |      \
 115                                         __HFN_INT_MBOX_LPU1_CT2);       \
 116         (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 |        \
 117                                         __HFN_INT_MBOX_LPU1_CT2);       \
 118         (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2);      \
 119         (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2);        \
 120         (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2;         \
 121         (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2;           \
 122 }
 123
 124 #define bna_reg_addr_init(_bna, _pcidev)                                \
 125 {                                                                       \
 126         switch ((_pcidev)->device_id) {                                 \
 127         case PCI_DEVICE_ID_BROCADE_CT:                                  \
 128                 ct_reg_addr_init((_bna), (_pcidev));                    \
 129                 ct_bit_defn_init((_bna), (_pcidev));                    \
 130                 break;                                                  \
 131         case BFA_PCI_DEVICE_ID_CT2:                                     \
 132                 ct2_reg_addr_init((_bna), (_pcidev));                   \
 133                 ct2_bit_defn_init((_bna), (_pcidev));                   \
 134                 break;                                                  \
 135         }                                                               \
 136 }
 137
 138 #define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id)
 139
 140 /*  Interrupt related bits, flags and macros  */
 141
 142 #define IB_STATUS_BITS          0x0000ffff
 143
 144 #define BNA_IS_MBOX_INTR(_bna, _intr_status)                            \
 145         ((_intr_status) & (_bna)->bits.mbox_status_bits)
 146
 147 #define BNA_IS_HALT_INTR(_bna, _intr_status)                            \
 148         ((_intr_status) & (_bna)->bits.halt_status_bits)
 149
 150 #define BNA_IS_ERR_INTR(_bna, _intr_status)     \
 151         ((_intr_status) & (_bna)->bits.error_status_bits)
 152
 153 #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status)        \
 154         (BNA_IS_MBOX_INTR(_bna, _intr_status) |         \
 155         BNA_IS_ERR_INTR(_bna, _intr_status))
 156
 157 #define BNA_IS_INTX_DATA_INTR(_intr_status)             \
 158                 ((_intr_status) & IB_STATUS_BITS)
 159
 160 #define bna_halt_clear(_bna)                                            \
 161 do {                                                                    \
 162         u32 init_halt;                                          \
 163         init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 164         init_halt &= ~__FW_INIT_HALT_P;                                 \
 165         writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 166         init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
 167 } while (0)
 168
 169 #define bna_intx_disable(_bna, _cur_mask)                               \
 170 {                                                                       \
 171         (_cur_mask) = readl((_bna)->regs.fn_int_mask);          \
 172         writel(0xffffffff, (_bna)->regs.fn_int_mask);           \
 173 }
 174
 175 #define bna_intx_enable(bna, new_mask)                                  \
 176         writel((new_mask), (bna)->regs.fn_int_mask)
 177 #define bna_mbox_intr_disable(bna)                                      \
 178 do {                                                                    \
 179         u32 mask;                                                       \
 180         mask = readl((bna)->regs.fn_int_mask);                          \
 181         writel((mask | (bna)->bits.mbox_mask_bits |                     \
 182                 (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \
 183         mask = readl((bna)->regs.fn_int_mask);                          \
 184 } while (0)
 185
 186 #define bna_mbox_intr_enable(bna)                                       \
 187 do {                                                                    \
 188         u32 mask;                                                       \
 189         mask = readl((bna)->regs.fn_int_mask);                          \
 190         writel((mask & ~((bna)->bits.mbox_mask_bits |                   \
 191                 (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\
 192         mask = readl((bna)->regs.fn_int_mask);                          \
 193 } while (0)
 194
 195 #define bna_intr_status_get(_bna, _status)                              \
 196 {                                                                       \
 197         (_status) = readl((_bna)->regs.fn_int_status);                  \
 198         if (_status) {                                                  \
 199                 writel(((_status) & ~(_bna)->bits.mbox_status_bits),    \
 200                         (_bna)->regs.fn_int_status);                    \
 201         }                                                               \
 202 }
 203
 204 /*
 205  * MAX ACK EVENTS : No. of acks that can be accumulated in driver,
 206  * before acking to h/w. The no. of bits is 16 in the doorbell register,
 207  * however we keep this limited to 15 bits.
 208  * This is because around the edge of 64K boundary (16 bits), one
 209  * single poll can make the accumulated ACK counter cross the 64K boundary,
 210  * causing problems, when we try to ack with a value greater than 64K.
 211  * 15 bits (32K) should  be large enough to accumulate, anyways, and the max.
 212  * acked events to h/w can be (32K + max poll weight) (currently 64).
 213  */
 214 #define BNA_IB_MAX_ACK_EVENTS           (1 << 15)
 215
 216 /* These macros build the data portion of the TxQ/RxQ doorbell */
 217 #define BNA_DOORBELL_Q_PRD_IDX(_pi)     (0x80000000 | (_pi))
 218 #define BNA_DOORBELL_Q_STOP             (0x40000000)
 219
 220 /* These macros build the data portion of the IB doorbell */
 221 #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events)                      \
 222         (0x80000000 | ((_timeout) << 16) | (_events))
 223 #define BNA_DOORBELL_IB_INT_DISABLE     (0x40000000)
 224
 225 /* Set the coalescing timer for the given ib */
 226 #define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer)               \
 227         ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0));
 228
 229 /* Acks 'events' # of events for a given ib while disabling interrupts */
 230 #define bna_ib_ack_disable_irq(_i_dbell, _events)                       \
 231         (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)), \
 232                 (_i_dbell)->doorbell_addr));
 233
 234 /* Acks 'events' # of events for a given ib */
 235 #define bna_ib_ack(_i_dbell, _events)                                   \
 236         (writel(((_i_dbell)->doorbell_ack | (_events)), \
 237                 (_i_dbell)->doorbell_addr));
 238
 239 #define bna_ib_start(_bna, _ib, _is_regular)                            \
 240 {                                                                       \
 241         u32 intx_mask;                                          \
 242         struct bna_ib *ib = _ib;                                        \
 243         if ((ib->intr_type == BNA_INTR_T_INTX)) {                       \
 244                 bna_intx_disable((_bna), intx_mask);                    \
 245                 intx_mask &= ~(ib->intr_vector);                        \
 246                 bna_intx_enable((_bna), intx_mask);                     \
 247         }                                                               \
 248         bna_ib_coalescing_timer_set(&ib->door_bell,                     \
 249                         ib->coalescing_timeo);                          \
 250         if (_is_regular)                                                \
 251                 bna_ib_ack(&ib->door_bell, 0);                          \
 252 }
 253
 254 #define bna_ib_stop(_bna, _ib)                                          \
 255 {                                                                       \
 256         u32 intx_mask;                                          \
 257         struct bna_ib *ib = _ib;                                        \
 258         writel(BNA_DOORBELL_IB_INT_DISABLE,                             \
 259                 ib->door_bell.doorbell_addr);                           \
 260         if (ib->intr_type == BNA_INTR_T_INTX) {                         \
 261                 bna_intx_disable((_bna), intx_mask);                    \
 262                 intx_mask |= ib->intr_vector;                           \
 263                 bna_intx_enable((_bna), intx_mask);                     \
 264         }                                                               \
 265 }
 266
 267 #define bna_txq_prod_indx_doorbell(_tcb)                                \
 268         (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index), \
 269                 (_tcb)->q_dbell));
 270
 271 #define bna_rxq_prod_indx_doorbell(_rcb)                                \
 272         (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index), \
 273                 (_rcb)->q_dbell));
 274
 275 /* TxQ, RxQ, CQ related bits, offsets, macros */
 276
 277 /* TxQ Entry Opcodes */
 278 #define BNA_TXQ_WI_SEND                 (0x402) /* Single Frame Transmission */
 279 #define BNA_TXQ_WI_SEND_LSO             (0x403) /* Multi-Frame Transmission */
 280 #define BNA_TXQ_WI_EXTENSION            (0x104) /* Extension WI */
 281
 282 /* TxQ Entry Control Flags */
 283 #define BNA_TXQ_WI_CF_FCOE_CRC          (1 << 8)
 284 #define BNA_TXQ_WI_CF_IPID_MODE         (1 << 5)
 285 #define BNA_TXQ_WI_CF_INS_PRIO          (1 << 4)
 286 #define BNA_TXQ_WI_CF_INS_VLAN          (1 << 3)
 287 #define BNA_TXQ_WI_CF_UDP_CKSUM         (1 << 2)
 288 #define BNA_TXQ_WI_CF_TCP_CKSUM         (1 << 1)
 289 #define BNA_TXQ_WI_CF_IP_CKSUM          (1 << 0)
 290
 291 #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
 292                 (((_hdr_size) << 10) | ((_offset) & 0x3FF))
 293
 294 /*
 295  * Completion Q defines
 296  */
 297 /* CQ Entry Flags */
 298 #define BNA_CQ_EF_MAC_ERROR     (1 <<  0)
 299 #define BNA_CQ_EF_FCS_ERROR     (1 <<  1)
 300 #define BNA_CQ_EF_TOO_LONG      (1 <<  2)
 301 #define BNA_CQ_EF_FC_CRC_OK     (1 <<  3)
 302
 303 #define BNA_CQ_EF_RSVD1         (1 <<  4)
 304 #define BNA_CQ_EF_L4_CKSUM_OK   (1 <<  5)
 305 #define BNA_CQ_EF_L3_CKSUM_OK   (1 <<  6)
 306 #define BNA_CQ_EF_HDS_HEADER    (1 <<  7)
 307
 308 #define BNA_CQ_EF_UDP           (1 <<  8)
 309 #define BNA_CQ_EF_TCP           (1 <<  9)
 310 #define BNA_CQ_EF_IP_OPTIONS    (1 << 10)
 311 #define BNA_CQ_EF_IPV6          (1 << 11)
 312
 313 #define BNA_CQ_EF_IPV4          (1 << 12)
 314 #define BNA_CQ_EF_VLAN          (1 << 13)
 315 #define BNA_CQ_EF_RSS           (1 << 14)
 316 #define BNA_CQ_EF_RSVD2         (1 << 15)
 317
 318 #define BNA_CQ_EF_MCAST_MATCH   (1 << 16)
 319 #define BNA_CQ_EF_MCAST         (1 << 17)
 320 #define BNA_CQ_EF_BCAST         (1 << 18)
 321 #define BNA_CQ_EF_REMOTE        (1 << 19)
 322
 323 #define BNA_CQ_EF_LOCAL         (1 << 20)
 324
 325 /* Data structures */
 326
 327 struct bna_reg_offset {
 328         u32 fn_int_status;
 329         u32 fn_int_mask;
 330 };
 331
 332 struct bna_bit_defn {
 333         u32 mbox_status_bits;
 334         u32 mbox_mask_bits;
 335         u32 error_status_bits;
 336         u32 error_mask_bits;
 337         u32 halt_status_bits;
 338         u32 halt_mask_bits;
 339 };
 340
 341 struct bna_reg {
 342         void __iomem *fn_int_status;
 343         void __iomem *fn_int_mask;
 344 };
 345
 346 /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
 347 struct bna_dma_addr {
 348         u32             msb;
 349         u32             lsb;
 350 };
 351
 352 struct bna_txq_wi_vector {
 353         u16             reserved;
 354         u16             length;         /* Only 14 LSB are valid */
 355         struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
 356 };
 357
 358 /*  TxQ Entry Structure
 359  *
 360  *  BEWARE:  Load values into this structure with correct endianess.
 361  */
 362 struct bna_txq_entry {
 363         union {
 364                 struct {
 365                         u8 reserved;
 366                         u8 num_vectors; /* number of vectors present */
 367                         u16 opcode; /* Either */
 368                                                     /* BNA_TXQ_WI_SEND or */
 369                                                     /* BNA_TXQ_WI_SEND_LSO */
 370                         u16 flags; /* OR of all the flags */
 371                         u16 l4_hdr_size_n_offset;
 372                         u16 vlan_tag;
 373                         u16 lso_mss;    /* Only 14 LSB are valid */
 374                         u32 frame_length;       /* Only 24 LSB are valid */
 375                 } wi;
 376
 377                 struct {
 378                         u16 reserved;
 379                         u16 opcode; /* Must be */
 380                                                     /* BNA_TXQ_WI_EXTENSION */
 381                         u32 reserved2[3];       /* Place holder for */
 382                                                 /* removed vector (12 bytes) */
 383                 } wi_ext;
 384         } hdr;
 385         struct bna_txq_wi_vector vector[4];
 386 };
 387
 388 /* RxQ Entry Structure */
 389 struct bna_rxq_entry {          /* Rx-Buffer */
 390         struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
 391 };
 392
 393 /* CQ Entry Structure */
 394 struct bna_cq_entry {
 395         u32 flags;
 396         u16 vlan_tag;
 397         u16 length;
 398         u32 rss_hash;
 399         u8 valid;
 400         u8 reserved1;
 401         u8 reserved2;
 402         u8 rxq_id;
 403 };
 404
 405 #endif /* __BNA_HW_DEFS_H__ */