arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21
  22 #include <plat-omap/dma-omap.h>
  23 #include "l3_3xxx.h"
  24 #include "l4_3xxx.h"
  25 #include <linux/platform_data/asoc-ti-mcbsp.h>
  26 #include <linux/platform_data/spi-omap2-mcspi.h>
  27 #include <plat/dmtimer.h>
  28 #include <plat/iommu.h>
  29
  30 #include "am35xx.h"
  31
  32 #include "soc.h"
  33 #include "omap_hwmod.h"
  34 #include "omap_hwmod_common_data.h"
  35 #include "prm-regbits-34xx.h"
  36 #include "cm-regbits-34xx.h"
  37
  38 #include "dma.h"
  39 #include "i2c.h"
  40 #include "mmc.h"
  41 #include "wd_timer.h"
  42 #include "serial.h"
  43
  44 /*
  45  * OMAP3xxx hardware module integration data
  46  *
  47  * All of the data in this section should be autogeneratable from the
  48  * TI hardware database or other technical documentation.  Data that
  49  * is driver-specific or driver-kernel integration-specific belongs
  50  * elsewhere.
  51  */
  52
  53 /*
  54  * IP blocks
  55  */
  56
  57 /* L3 */
  58 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  59         { .irq = 9 + OMAP_INTC_START, },
  60         { .irq = 10 + OMAP_INTC_START, },
  61         { .irq = -1 },
  62 };
  63
  64 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  65         .name           = "l3_main",
  66         .class          = &l3_hwmod_class,
  67         .mpu_irqs       = omap3xxx_l3_main_irqs,
  68         .flags          = HWMOD_NO_IDLEST,
  69 };
  70
  71 /* L4 CORE */
  72 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  73         .name           = "l4_core",
  74         .class          = &l4_hwmod_class,
  75         .flags          = HWMOD_NO_IDLEST,
  76 };
  77
  78 /* L4 PER */
  79 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  80         .name           = "l4_per",
  81         .class          = &l4_hwmod_class,
  82         .flags          = HWMOD_NO_IDLEST,
  83 };
  84
  85 /* L4 WKUP */
  86 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  87         .name           = "l4_wkup",
  88         .class          = &l4_hwmod_class,
  89         .flags          = HWMOD_NO_IDLEST,
  90 };
  91
  92 /* L4 SEC */
  93 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  94         .name           = "l4_sec",
  95         .class          = &l4_hwmod_class,
  96         .flags          = HWMOD_NO_IDLEST,
  97 };
  98
  99 /* MPU */
 100 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
 101         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 102         { .irq = -1 }
 103 };
 104
 105 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 106         .name           = "mpu",
 107         .mpu_irqs       = omap3xxx_mpu_irqs,
 108         .class          = &mpu_hwmod_class,
 109         .main_clk       = "arm_fck",
 110 };
 111
 112 /* IVA2 (IVA2) */
 113 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 114         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 115         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 116         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 117 };
 118
 119 static struct omap_hwmod omap3xxx_iva_hwmod = {
 120         .name           = "iva",
 121         .class          = &iva_hwmod_class,
 122         .clkdm_name     = "iva2_clkdm",
 123         .rst_lines      = omap3xxx_iva_resets,
 124         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 125         .main_clk       = "iva2_ck",
 126         .prcm = {
 127                 .omap2 = {
 128                         .module_offs = OMAP3430_IVA2_MOD,
 129                         .prcm_reg_id = 1,
 130                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 131                         .idlest_reg_id = 1,
 132                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 133                 }
 134         },
 135 };
 136
 137 /*
 138  * 'debugss' class
 139  * debug and emulation sub system
 140  */
 141
 142 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 143         .name   = "debugss",
 144 };
 145
 146 /* debugss */
 147 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 148         .name           = "debugss",
 149         .class          = &omap3xxx_debugss_hwmod_class,
 150         .clkdm_name     = "emu_clkdm",
 151         .main_clk       = "emu_src_ck",
 152         .flags          = HWMOD_NO_IDLEST,
 153 };
 154
 155 /* timer class */
 156 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 157         .rev_offs       = 0x0000,
 158         .sysc_offs      = 0x0010,
 159         .syss_offs      = 0x0014,
 160         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 161                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 162                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 164         .sysc_fields    = &omap_hwmod_sysc_type1,
 165 };
 166
 167 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 168         .name = "timer",
 169         .sysc = &omap3xxx_timer_1ms_sysc,
 170 };
 171
 172 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 173         .rev_offs       = 0x0000,
 174         .sysc_offs      = 0x0010,
 175         .syss_offs      = 0x0014,
 176         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 177                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 178         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 179         .sysc_fields    = &omap_hwmod_sysc_type1,
 180 };
 181
 182 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 183         .name = "timer",
 184         .sysc = &omap3xxx_timer_sysc,
 185 };
 186
 187 /* secure timers dev attribute */
 188 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 189         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 190 };
 191
 192 /* always-on timers dev attribute */
 193 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 194         .timer_capability       = OMAP_TIMER_ALWON,
 195 };
 196
 197 /* pwm timers dev attribute */
 198 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 199         .timer_capability       = OMAP_TIMER_HAS_PWM,
 200 };
 201
 202 /* timers with DSP interrupt dev attribute */
 203 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 204         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 205 };
 206
 207 /* pwm timers with DSP interrupt dev attribute */
 208 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 209         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 210 };
 211
 212 /* timer1 */
 213 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 214         .name           = "timer1",
 215         .mpu_irqs       = omap2_timer1_mpu_irqs,
 216         .main_clk       = "gpt1_fck",
 217         .prcm           = {
 218                 .omap2 = {
 219                         .prcm_reg_id = 1,
 220                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 221                         .module_offs = WKUP_MOD,
 222                         .idlest_reg_id = 1,
 223                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 224                 },
 225         },
 226         .dev_attr       = &capability_alwon_dev_attr,
 227         .class          = &omap3xxx_timer_1ms_hwmod_class,
 228 };
 229
 230 /* timer2 */
 231 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 232         .name           = "timer2",
 233         .mpu_irqs       = omap2_timer2_mpu_irqs,
 234         .main_clk       = "gpt2_fck",
 235         .prcm           = {
 236                 .omap2 = {
 237                         .prcm_reg_id = 1,
 238                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 239                         .module_offs = OMAP3430_PER_MOD,
 240                         .idlest_reg_id = 1,
 241                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 242                 },
 243         },
 244         .class          = &omap3xxx_timer_1ms_hwmod_class,
 245 };
 246
 247 /* timer3 */
 248 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 249         .name           = "timer3",
 250         .mpu_irqs       = omap2_timer3_mpu_irqs,
 251         .main_clk       = "gpt3_fck",
 252         .prcm           = {
 253                 .omap2 = {
 254                         .prcm_reg_id = 1,
 255                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 256                         .module_offs = OMAP3430_PER_MOD,
 257                         .idlest_reg_id = 1,
 258                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 259                 },
 260         },
 261         .class          = &omap3xxx_timer_hwmod_class,
 262 };
 263
 264 /* timer4 */
 265 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 266         .name           = "timer4",
 267         .mpu_irqs       = omap2_timer4_mpu_irqs,
 268         .main_clk       = "gpt4_fck",
 269         .prcm           = {
 270                 .omap2 = {
 271                         .prcm_reg_id = 1,
 272                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 273                         .module_offs = OMAP3430_PER_MOD,
 274                         .idlest_reg_id = 1,
 275                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 276                 },
 277         },
 278         .class          = &omap3xxx_timer_hwmod_class,
 279 };
 280
 281 /* timer5 */
 282 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 283         .name           = "timer5",
 284         .mpu_irqs       = omap2_timer5_mpu_irqs,
 285         .main_clk       = "gpt5_fck",
 286         .prcm           = {
 287                 .omap2 = {
 288                         .prcm_reg_id = 1,
 289                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 290                         .module_offs = OMAP3430_PER_MOD,
 291                         .idlest_reg_id = 1,
 292                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 293                 },
 294         },
 295         .dev_attr       = &capability_dsp_dev_attr,
 296         .class          = &omap3xxx_timer_hwmod_class,
 297 };
 298
 299 /* timer6 */
 300 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 301         .name           = "timer6",
 302         .mpu_irqs       = omap2_timer6_mpu_irqs,
 303         .main_clk       = "gpt6_fck",
 304         .prcm           = {
 305                 .omap2 = {
 306                         .prcm_reg_id = 1,
 307                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 308                         .module_offs = OMAP3430_PER_MOD,
 309                         .idlest_reg_id = 1,
 310                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 311                 },
 312         },
 313         .dev_attr       = &capability_dsp_dev_attr,
 314         .class          = &omap3xxx_timer_hwmod_class,
 315 };
 316
 317 /* timer7 */
 318 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 319         .name           = "timer7",
 320         .mpu_irqs       = omap2_timer7_mpu_irqs,
 321         .main_clk       = "gpt7_fck",
 322         .prcm           = {
 323                 .omap2 = {
 324                         .prcm_reg_id = 1,
 325                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 326                         .module_offs = OMAP3430_PER_MOD,
 327                         .idlest_reg_id = 1,
 328                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 329                 },
 330         },
 331         .dev_attr       = &capability_dsp_dev_attr,
 332         .class          = &omap3xxx_timer_hwmod_class,
 333 };
 334
 335 /* timer8 */
 336 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 337         .name           = "timer8",
 338         .mpu_irqs       = omap2_timer8_mpu_irqs,
 339         .main_clk       = "gpt8_fck",
 340         .prcm           = {
 341                 .omap2 = {
 342                         .prcm_reg_id = 1,
 343                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 344                         .module_offs = OMAP3430_PER_MOD,
 345                         .idlest_reg_id = 1,
 346                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 347                 },
 348         },
 349         .dev_attr       = &capability_dsp_pwm_dev_attr,
 350         .class          = &omap3xxx_timer_hwmod_class,
 351 };
 352
 353 /* timer9 */
 354 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 355         .name           = "timer9",
 356         .mpu_irqs       = omap2_timer9_mpu_irqs,
 357         .main_clk       = "gpt9_fck",
 358         .prcm           = {
 359                 .omap2 = {
 360                         .prcm_reg_id = 1,
 361                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 362                         .module_offs = OMAP3430_PER_MOD,
 363                         .idlest_reg_id = 1,
 364                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 365                 },
 366         },
 367         .dev_attr       = &capability_pwm_dev_attr,
 368         .class          = &omap3xxx_timer_hwmod_class,
 369 };
 370
 371 /* timer10 */
 372 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 373         .name           = "timer10",
 374         .mpu_irqs       = omap2_timer10_mpu_irqs,
 375         .main_clk       = "gpt10_fck",
 376         .prcm           = {
 377                 .omap2 = {
 378                         .prcm_reg_id = 1,
 379                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 380                         .module_offs = CORE_MOD,
 381                         .idlest_reg_id = 1,
 382                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 383                 },
 384         },
 385         .dev_attr       = &capability_pwm_dev_attr,
 386         .class          = &omap3xxx_timer_1ms_hwmod_class,
 387 };
 388
 389 /* timer11 */
 390 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 391         .name           = "timer11",
 392         .mpu_irqs       = omap2_timer11_mpu_irqs,
 393         .main_clk       = "gpt11_fck",
 394         .prcm           = {
 395                 .omap2 = {
 396                         .prcm_reg_id = 1,
 397                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 398                         .module_offs = CORE_MOD,
 399                         .idlest_reg_id = 1,
 400                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 401                 },
 402         },
 403         .dev_attr       = &capability_pwm_dev_attr,
 404         .class          = &omap3xxx_timer_hwmod_class,
 405 };
 406
 407 /* timer12 */
 408 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 409         { .irq = 95 + OMAP_INTC_START, },
 410         { .irq = -1 },
 411 };
 412
 413 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 414         .name           = "timer12",
 415         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 416         .main_clk       = "gpt12_fck",
 417         .prcm           = {
 418                 .omap2 = {
 419                         .prcm_reg_id = 1,
 420                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 421                         .module_offs = WKUP_MOD,
 422                         .idlest_reg_id = 1,
 423                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 424                 },
 425         },
 426         .dev_attr       = &capability_secure_dev_attr,
 427         .class          = &omap3xxx_timer_hwmod_class,
 428 };
 429
 430 /*
 431  * 'wd_timer' class
 432  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 433  * overflow condition
 434  */
 435
 436 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 437         .rev_offs       = 0x0000,
 438         .sysc_offs      = 0x0010,
 439         .syss_offs      = 0x0014,
 440         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 441                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 442                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 443                            SYSS_HAS_RESET_STATUS),
 444         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 445         .sysc_fields    = &omap_hwmod_sysc_type1,
 446 };
 447
 448 /* I2C common */
 449 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 450         .rev_offs       = 0x00,
 451         .sysc_offs      = 0x20,
 452         .syss_offs      = 0x10,
 453         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 454                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 455                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 456         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 457         .clockact       = CLOCKACT_TEST_ICLK,
 458         .sysc_fields    = &omap_hwmod_sysc_type1,
 459 };
 460
 461 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 462         .name           = "wd_timer",
 463         .sysc           = &omap3xxx_wd_timer_sysc,
 464         .pre_shutdown   = &omap2_wd_timer_disable,
 465         .reset          = &omap2_wd_timer_reset,
 466 };
 467
 468 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 469         .name           = "wd_timer2",
 470         .class          = &omap3xxx_wd_timer_hwmod_class,
 471         .main_clk       = "wdt2_fck",
 472         .prcm           = {
 473                 .omap2 = {
 474                         .prcm_reg_id = 1,
 475                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 476                         .module_offs = WKUP_MOD,
 477                         .idlest_reg_id = 1,
 478                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 479                 },
 480         },
 481         /*
 482          * XXX: Use software supervised mode, HW supervised smartidle seems to
 483          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 484          */
 485         .flags          = HWMOD_SWSUP_SIDLE,
 486 };
 487
 488 /* UART1 */
 489 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 490         .name           = "uart1",
 491         .mpu_irqs       = omap2_uart1_mpu_irqs,
 492         .sdma_reqs      = omap2_uart1_sdma_reqs,
 493         .main_clk       = "uart1_fck",
 494         .prcm           = {
 495                 .omap2 = {
 496                         .module_offs = CORE_MOD,
 497                         .prcm_reg_id = 1,
 498                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 499                         .idlest_reg_id = 1,
 500                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 501                 },
 502         },
 503         .class          = &omap2_uart_class,
 504 };
 505
 506 /* UART2 */
 507 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 508         .name           = "uart2",
 509         .mpu_irqs       = omap2_uart2_mpu_irqs,
 510         .sdma_reqs      = omap2_uart2_sdma_reqs,
 511         .main_clk       = "uart2_fck",
 512         .prcm           = {
 513                 .omap2 = {
 514                         .module_offs = CORE_MOD,
 515                         .prcm_reg_id = 1,
 516                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 517                         .idlest_reg_id = 1,
 518                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 519                 },
 520         },
 521         .class          = &omap2_uart_class,
 522 };
 523
 524 /* UART3 */
 525 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 526         .name           = "uart3",
 527         .mpu_irqs       = omap2_uart3_mpu_irqs,
 528         .sdma_reqs      = omap2_uart3_sdma_reqs,
 529         .main_clk       = "uart3_fck",
 530         .prcm           = {
 531                 .omap2 = {
 532                         .module_offs = OMAP3430_PER_MOD,
 533                         .prcm_reg_id = 1,
 534                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 535                         .idlest_reg_id = 1,
 536                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 537                 },
 538         },
 539         .class          = &omap2_uart_class,
 540 };
 541
 542 /* UART4 */
 543 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 544         { .irq = 80 + OMAP_INTC_START, },
 545         { .irq = -1 },
 546 };
 547
 548 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 549         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 550         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 551         { .dma_req = -1 }
 552 };
 553
 554 static struct omap_hwmod omap36xx_uart4_hwmod = {
 555         .name           = "uart4",
 556         .mpu_irqs       = uart4_mpu_irqs,
 557         .sdma_reqs      = uart4_sdma_reqs,
 558         .main_clk       = "uart4_fck",
 559         .prcm           = {
 560                 .omap2 = {
 561                         .module_offs = OMAP3430_PER_MOD,
 562                         .prcm_reg_id = 1,
 563                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 564                         .idlest_reg_id = 1,
 565                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 566                 },
 567         },
 568         .class          = &omap2_uart_class,
 569 };
 570
 571 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 572         { .irq = 84 + OMAP_INTC_START, },
 573         { .irq = -1 },
 574 };
 575
 576 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 577         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 578         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 579         { .dma_req = -1 }
 580 };
 581
 582 /*
 583  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 584  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 585  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 586  * should not be needed.  The functional clock structure of the AM35xx
 587  * UART4 is extremely unclear and opaque; it is unclear what the role
 588  * of uart1/2_fck is for the UART4.  Any clarification from either
 589  * empirical testing or the AM3505/3517 hardware designers would be
 590  * most welcome.
 591  */
 592 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 593         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 594 };
 595
 596 static struct omap_hwmod am35xx_uart4_hwmod = {
 597         .name           = "uart4",
 598         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 599         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 600         .main_clk       = "uart4_fck",
 601         .prcm           = {
 602                 .omap2 = {
 603                         .module_offs = CORE_MOD,
 604                         .prcm_reg_id = 1,
 605                         .module_bit = AM35XX_EN_UART4_SHIFT,
 606                         .idlest_reg_id = 1,
 607                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 608                 },
 609         },
 610         .opt_clks       = am35xx_uart4_opt_clks,
 611         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 612         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 613         .class          = &omap2_uart_class,
 614 };
 615
 616 static struct omap_hwmod_class i2c_class = {
 617         .name   = "i2c",
 618         .sysc   = &i2c_sysc,
 619         .rev    = OMAP_I2C_IP_VERSION_1,
 620         .reset  = &omap_i2c_reset,
 621 };
 622
 623 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 624         { .name = "dispc", .dma_req = 5 },
 625         { .name = "dsi1", .dma_req = 74 },
 626         { .dma_req = -1 }
 627 };
 628
 629 /* dss */
 630 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 631         /*
 632          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 633          * driver does not use these clocks.
 634          */
 635         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 636         { .role = "tv_clk", .clk = "dss_tv_fck" },
 637         /* required only on OMAP3430 */
 638         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 639 };
 640
 641 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 642         .name           = "dss_core",
 643         .class          = &omap2_dss_hwmod_class,
 644         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 645         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 646         .prcm           = {
 647                 .omap2 = {
 648                         .prcm_reg_id = 1,
 649                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 650                         .module_offs = OMAP3430_DSS_MOD,
 651                         .idlest_reg_id = 1,
 652                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 653                 },
 654         },
 655         .opt_clks       = dss_opt_clks,
 656         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 657         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 658 };
 659
 660 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 661         .name           = "dss_core",
 662         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 663         .class          = &omap2_dss_hwmod_class,
 664         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 665         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 666         .prcm           = {
 667                 .omap2 = {
 668                         .prcm_reg_id = 1,
 669                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 670                         .module_offs = OMAP3430_DSS_MOD,
 671                         .idlest_reg_id = 1,
 672                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 673                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 674                 },
 675         },
 676         .opt_clks       = dss_opt_clks,
 677         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 678 };
 679
 680 /*
 681  * 'dispc' class
 682  * display controller
 683  */
 684
 685 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 686         .rev_offs       = 0x0000,
 687         .sysc_offs      = 0x0010,
 688         .syss_offs      = 0x0014,
 689         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 690                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 691                            SYSC_HAS_ENAWAKEUP),
 692         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 693                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 694         .sysc_fields    = &omap_hwmod_sysc_type1,
 695 };
 696
 697 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 698         .name   = "dispc",
 699         .sysc   = &omap3_dispc_sysc,
 700 };
 701
 702 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 703         .name           = "dss_dispc",
 704         .class          = &omap3_dispc_hwmod_class,
 705         .mpu_irqs       = omap2_dispc_irqs,
 706         .main_clk       = "dss1_alwon_fck",
 707         .prcm           = {
 708                 .omap2 = {
 709                         .prcm_reg_id = 1,
 710                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 711                         .module_offs = OMAP3430_DSS_MOD,
 712                 },
 713         },
 714         .flags          = HWMOD_NO_IDLEST,
 715         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 716 };
 717
 718 /*
 719  * 'dsi' class
 720  * display serial interface controller
 721  */
 722
 723 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 724         .name = "dsi",
 725 };
 726
 727 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 728         { .irq = 25 + OMAP_INTC_START, },
 729         { .irq = -1 },
 730 };
 731
 732 /* dss_dsi1 */
 733 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 734         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 735 };
 736
 737 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 738         .name           = "dss_dsi1",
 739         .class          = &omap3xxx_dsi_hwmod_class,
 740         .mpu_irqs       = omap3xxx_dsi1_irqs,
 741         .main_clk       = "dss1_alwon_fck",
 742         .prcm           = {
 743                 .omap2 = {
 744                         .prcm_reg_id = 1,
 745                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 746                         .module_offs = OMAP3430_DSS_MOD,
 747                 },
 748         },
 749         .opt_clks       = dss_dsi1_opt_clks,
 750         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 751         .flags          = HWMOD_NO_IDLEST,
 752 };
 753
 754 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 755         { .role = "ick", .clk = "dss_ick" },
 756 };
 757
 758 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 759         .name           = "dss_rfbi",
 760         .class          = &omap2_rfbi_hwmod_class,
 761         .main_clk       = "dss1_alwon_fck",
 762         .prcm           = {
 763                 .omap2 = {
 764                         .prcm_reg_id = 1,
 765                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 766                         .module_offs = OMAP3430_DSS_MOD,
 767                 },
 768         },
 769         .opt_clks       = dss_rfbi_opt_clks,
 770         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 771         .flags          = HWMOD_NO_IDLEST,
 772 };
 773
 774 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 775         /* required only on OMAP3430 */
 776         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 777 };
 778
 779 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 780         .name           = "dss_venc",
 781         .class          = &omap2_venc_hwmod_class,
 782         .main_clk       = "dss_tv_fck",
 783         .prcm           = {
 784                 .omap2 = {
 785                         .prcm_reg_id = 1,
 786                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 787                         .module_offs = OMAP3430_DSS_MOD,
 788                 },
 789         },
 790         .opt_clks       = dss_venc_opt_clks,
 791         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 792         .flags          = HWMOD_NO_IDLEST,
 793 };
 794
 795 /* I2C1 */
 796 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 797         .fifo_depth     = 8, /* bytes */
 798         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 799                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 800                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 801 };
 802
 803 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 804         .name           = "i2c1",
 805         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 806         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 807         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 808         .main_clk       = "i2c1_fck",
 809         .prcm           = {
 810                 .omap2 = {
 811                         .module_offs = CORE_MOD,
 812                         .prcm_reg_id = 1,
 813                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 814                         .idlest_reg_id = 1,
 815                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 816                 },
 817         },
 818         .class          = &i2c_class,
 819         .dev_attr       = &i2c1_dev_attr,
 820 };
 821
 822 /* I2C2 */
 823 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 824         .fifo_depth     = 8, /* bytes */
 825         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 826                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 827                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 828 };
 829
 830 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 831         .name           = "i2c2",
 832         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 833         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 834         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 835         .main_clk       = "i2c2_fck",
 836         .prcm           = {
 837                 .omap2 = {
 838                         .module_offs = CORE_MOD,
 839                         .prcm_reg_id = 1,
 840                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 841                         .idlest_reg_id = 1,
 842                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 843                 },
 844         },
 845         .class          = &i2c_class,
 846         .dev_attr       = &i2c2_dev_attr,
 847 };
 848
 849 /* I2C3 */
 850 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 851         .fifo_depth     = 64, /* bytes */
 852         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 853                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 854                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 855 };
 856
 857 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 858         { .irq = 61 + OMAP_INTC_START, },
 859         { .irq = -1 },
 860 };
 861
 862 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 863         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 864         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 865         { .dma_req = -1 }
 866 };
 867
 868 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 869         .name           = "i2c3",
 870         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 871         .mpu_irqs       = i2c3_mpu_irqs,
 872         .sdma_reqs      = i2c3_sdma_reqs,
 873         .main_clk       = "i2c3_fck",
 874         .prcm           = {
 875                 .omap2 = {
 876                         .module_offs = CORE_MOD,
 877                         .prcm_reg_id = 1,
 878                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 879                         .idlest_reg_id = 1,
 880                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 881                 },
 882         },
 883         .class          = &i2c_class,
 884         .dev_attr       = &i2c3_dev_attr,
 885 };
 886
 887 /*
 888  * 'gpio' class
 889  * general purpose io module
 890  */
 891
 892 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 893         .rev_offs       = 0x0000,
 894         .sysc_offs      = 0x0010,
 895         .syss_offs      = 0x0014,
 896         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 897                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 898                            SYSS_HAS_RESET_STATUS),
 899         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 900         .sysc_fields    = &omap_hwmod_sysc_type1,
 901 };
 902
 903 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 904         .name = "gpio",
 905         .sysc = &omap3xxx_gpio_sysc,
 906         .rev = 1,
 907 };
 908
 909 /* gpio_dev_attr */
 910 static struct omap_gpio_dev_attr gpio_dev_attr = {
 911         .bank_width = 32,
 912         .dbck_flag = true,
 913 };
 914
 915 /* gpio1 */
 916 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 917         { .role = "dbclk", .clk = "gpio1_dbck", },
 918 };
 919
 920 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 921         .name           = "gpio1",
 922         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 923         .mpu_irqs       = omap2_gpio1_irqs,
 924         .main_clk       = "gpio1_ick",
 925         .opt_clks       = gpio1_opt_clks,
 926         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 927         .prcm           = {
 928                 .omap2 = {
 929                         .prcm_reg_id = 1,
 930                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 931                         .module_offs = WKUP_MOD,
 932                         .idlest_reg_id = 1,
 933                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 934                 },
 935         },
 936         .class          = &omap3xxx_gpio_hwmod_class,
 937         .dev_attr       = &gpio_dev_attr,
 938 };
 939
 940 /* gpio2 */
 941 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 942         { .role = "dbclk", .clk = "gpio2_dbck", },
 943 };
 944
 945 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 946         .name           = "gpio2",
 947         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 948         .mpu_irqs       = omap2_gpio2_irqs,
 949         .main_clk       = "gpio2_ick",
 950         .opt_clks       = gpio2_opt_clks,
 951         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 952         .prcm           = {
 953                 .omap2 = {
 954                         .prcm_reg_id = 1,
 955                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 956                         .module_offs = OMAP3430_PER_MOD,
 957                         .idlest_reg_id = 1,
 958                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 959                 },
 960         },
 961         .class          = &omap3xxx_gpio_hwmod_class,
 962         .dev_attr       = &gpio_dev_attr,
 963 };
 964
 965 /* gpio3 */
 966 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 967         { .role = "dbclk", .clk = "gpio3_dbck", },
 968 };
 969
 970 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 971         .name           = "gpio3",
 972         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 973         .mpu_irqs       = omap2_gpio3_irqs,
 974         .main_clk       = "gpio3_ick",
 975         .opt_clks       = gpio3_opt_clks,
 976         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 977         .prcm           = {
 978                 .omap2 = {
 979                         .prcm_reg_id = 1,
 980                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 981                         .module_offs = OMAP3430_PER_MOD,
 982                         .idlest_reg_id = 1,
 983                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 984                 },
 985         },
 986         .class          = &omap3xxx_gpio_hwmod_class,
 987         .dev_attr       = &gpio_dev_attr,
 988 };
 989
 990 /* gpio4 */
 991 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 992         { .role = "dbclk", .clk = "gpio4_dbck", },
 993 };
 994
 995 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 996         .name           = "gpio4",
 997         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 998         .mpu_irqs       = omap2_gpio4_irqs,
 999         .main_clk       = "gpio4_ick",
1000         .opt_clks       = gpio4_opt_clks,
1001         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1002         .prcm           = {
1003                 .omap2 = {
1004                         .prcm_reg_id = 1,
1005                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1006                         .module_offs = OMAP3430_PER_MOD,
1007                         .idlest_reg_id = 1,
1008                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1009                 },
1010         },
1011         .class          = &omap3xxx_gpio_hwmod_class,
1012         .dev_attr       = &gpio_dev_attr,
1013 };
1014
1015 /* gpio5 */
1016 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1017         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1018         { .irq = -1 },
1019 };
1020
1021 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1022         { .role = "dbclk", .clk = "gpio5_dbck", },
1023 };
1024
1025 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1026         .name           = "gpio5",
1027         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1028         .mpu_irqs       = omap3xxx_gpio5_irqs,
1029         .main_clk       = "gpio5_ick",
1030         .opt_clks       = gpio5_opt_clks,
1031         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1032         .prcm           = {
1033                 .omap2 = {
1034                         .prcm_reg_id = 1,
1035                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1036                         .module_offs = OMAP3430_PER_MOD,
1037                         .idlest_reg_id = 1,
1038                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1039                 },
1040         },
1041         .class          = &omap3xxx_gpio_hwmod_class,
1042         .dev_attr       = &gpio_dev_attr,
1043 };
1044
1045 /* gpio6 */
1046 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1047         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1048         { .irq = -1 },
1049 };
1050
1051 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1052         { .role = "dbclk", .clk = "gpio6_dbck", },
1053 };
1054
1055 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1056         .name           = "gpio6",
1057         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1058         .mpu_irqs       = omap3xxx_gpio6_irqs,
1059         .main_clk       = "gpio6_ick",
1060         .opt_clks       = gpio6_opt_clks,
1061         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1062         .prcm           = {
1063                 .omap2 = {
1064                         .prcm_reg_id = 1,
1065                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1066                         .module_offs = OMAP3430_PER_MOD,
1067                         .idlest_reg_id = 1,
1068                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1069                 },
1070         },
1071         .class          = &omap3xxx_gpio_hwmod_class,
1072         .dev_attr       = &gpio_dev_attr,
1073 };
1074
1075 /* dma attributes */
1076 static struct omap_dma_dev_attr dma_dev_attr = {
1077         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1078                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1079         .lch_count = 32,
1080 };
1081
1082 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1083         .rev_offs       = 0x0000,
1084         .sysc_offs      = 0x002c,
1085         .syss_offs      = 0x0028,
1086         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1087                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1088                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1089                            SYSS_HAS_RESET_STATUS),
1090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1091                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1092         .sysc_fields    = &omap_hwmod_sysc_type1,
1093 };
1094
1095 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1096         .name = "dma",
1097         .sysc = &omap3xxx_dma_sysc,
1098 };
1099
1100 /* dma_system */
1101 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1102         .name           = "dma",
1103         .class          = &omap3xxx_dma_hwmod_class,
1104         .mpu_irqs       = omap2_dma_system_irqs,
1105         .main_clk       = "core_l3_ick",
1106         .prcm = {
1107                 .omap2 = {
1108                         .module_offs            = CORE_MOD,
1109                         .prcm_reg_id            = 1,
1110                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1111                         .idlest_reg_id          = 1,
1112                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1113                 },
1114         },
1115         .dev_attr       = &dma_dev_attr,
1116         .flags          = HWMOD_NO_IDLEST,
1117 };
1118
1119 /*
1120  * 'mcbsp' class
1121  * multi channel buffered serial port controller
1122  */
1123
1124 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1125         .sysc_offs      = 0x008c,
1126         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1127                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1128         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1129         .sysc_fields    = &omap_hwmod_sysc_type1,
1130         .clockact       = 0x2,
1131 };
1132
1133 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1134         .name = "mcbsp",
1135         .sysc = &omap3xxx_mcbsp_sysc,
1136         .rev  = MCBSP_CONFIG_TYPE3,
1137 };
1138
1139 /* McBSP functional clock mapping */
1140 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1141         { .role = "pad_fck", .clk = "mcbsp_clks" },
1142         { .role = "prcm_fck", .clk = "core_96m_fck" },
1143 };
1144
1145 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1146         { .role = "pad_fck", .clk = "mcbsp_clks" },
1147         { .role = "prcm_fck", .clk = "per_96m_fck" },
1148 };
1149
1150 /* mcbsp1 */
1151 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1152         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1153         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1154         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1155         { .irq = -1 },
1156 };
1157
1158 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1159         .name           = "mcbsp1",
1160         .class          = &omap3xxx_mcbsp_hwmod_class,
1161         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1162         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1163         .main_clk       = "mcbsp1_fck",
1164         .prcm           = {
1165                 .omap2 = {
1166                         .prcm_reg_id = 1,
1167                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1168                         .module_offs = CORE_MOD,
1169                         .idlest_reg_id = 1,
1170                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1171                 },
1172         },
1173         .opt_clks       = mcbsp15_opt_clks,
1174         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1175 };
1176
1177 /* mcbsp2 */
1178 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1179         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1180         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1181         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1182         { .irq = -1 },
1183 };
1184
1185 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1186         .sidetone       = "mcbsp2_sidetone",
1187 };
1188
1189 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1190         .name           = "mcbsp2",
1191         .class          = &omap3xxx_mcbsp_hwmod_class,
1192         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1193         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1194         .main_clk       = "mcbsp2_fck",
1195         .prcm           = {
1196                 .omap2 = {
1197                         .prcm_reg_id = 1,
1198                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1199                         .module_offs = OMAP3430_PER_MOD,
1200                         .idlest_reg_id = 1,
1201                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1202                 },
1203         },
1204         .opt_clks       = mcbsp234_opt_clks,
1205         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1206         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1207 };
1208
1209 /* mcbsp3 */
1210 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1211         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1212         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1213         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1214         { .irq = -1 },
1215 };
1216
1217 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1218         .sidetone       = "mcbsp3_sidetone",
1219 };
1220
1221 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1222         .name           = "mcbsp3",
1223         .class          = &omap3xxx_mcbsp_hwmod_class,
1224         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1225         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1226         .main_clk       = "mcbsp3_fck",
1227         .prcm           = {
1228                 .omap2 = {
1229                         .prcm_reg_id = 1,
1230                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1231                         .module_offs = OMAP3430_PER_MOD,
1232                         .idlest_reg_id = 1,
1233                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1234                 },
1235         },
1236         .opt_clks       = mcbsp234_opt_clks,
1237         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1238         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1239 };
1240
1241 /* mcbsp4 */
1242 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1243         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1244         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1245         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1246         { .irq = -1 },
1247 };
1248
1249 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1250         { .name = "rx", .dma_req = 20 },
1251         { .name = "tx", .dma_req = 19 },
1252         { .dma_req = -1 }
1253 };
1254
1255 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1256         .name           = "mcbsp4",
1257         .class          = &omap3xxx_mcbsp_hwmod_class,
1258         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1259         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1260         .main_clk       = "mcbsp4_fck",
1261         .prcm           = {
1262                 .omap2 = {
1263                         .prcm_reg_id = 1,
1264                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1265                         .module_offs = OMAP3430_PER_MOD,
1266                         .idlest_reg_id = 1,
1267                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1268                 },
1269         },
1270         .opt_clks       = mcbsp234_opt_clks,
1271         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1272 };
1273
1274 /* mcbsp5 */
1275 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1276         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1277         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1278         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1279         { .irq = -1 },
1280 };
1281
1282 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1283         { .name = "rx", .dma_req = 22 },
1284         { .name = "tx", .dma_req = 21 },
1285         { .dma_req = -1 }
1286 };
1287
1288 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1289         .name           = "mcbsp5",
1290         .class          = &omap3xxx_mcbsp_hwmod_class,
1291         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1292         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1293         .main_clk       = "mcbsp5_fck",
1294         .prcm           = {
1295                 .omap2 = {
1296                         .prcm_reg_id = 1,
1297                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1298                         .module_offs = CORE_MOD,
1299                         .idlest_reg_id = 1,
1300                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1301                 },
1302         },
1303         .opt_clks       = mcbsp15_opt_clks,
1304         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1305 };
1306
1307 /* 'mcbsp sidetone' class */
1308 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1309         .sysc_offs      = 0x0010,
1310         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1311         .sysc_fields    = &omap_hwmod_sysc_type1,
1312 };
1313
1314 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1315         .name = "mcbsp_sidetone",
1316         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1317 };
1318
1319 /* mcbsp2_sidetone */
1320 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1321         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1322         { .irq = -1 },
1323 };
1324
1325 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1326         .name           = "mcbsp2_sidetone",
1327         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1328         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1329         .main_clk       = "mcbsp2_fck",
1330         .prcm           = {
1331                 .omap2 = {
1332                         .prcm_reg_id = 1,
1333                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1334                         .module_offs = OMAP3430_PER_MOD,
1335                         .idlest_reg_id = 1,
1336                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1337                 },
1338         },
1339 };
1340
1341 /* mcbsp3_sidetone */
1342 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1343         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1344         { .irq = -1 },
1345 };
1346
1347 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1348         .name           = "mcbsp3_sidetone",
1349         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1350         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1351         .main_clk       = "mcbsp3_fck",
1352         .prcm           = {
1353                 .omap2 = {
1354                         .prcm_reg_id = 1,
1355                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1356                         .module_offs = OMAP3430_PER_MOD,
1357                         .idlest_reg_id = 1,
1358                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1359                 },
1360         },
1361 };
1362
1363 /* SR common */
1364 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1365         .clkact_shift   = 20,
1366 };
1367
1368 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1369         .sysc_offs      = 0x24,
1370         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1371         .clockact       = CLOCKACT_TEST_ICLK,
1372         .sysc_fields    = &omap34xx_sr_sysc_fields,
1373 };
1374
1375 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1376         .name = "smartreflex",
1377         .sysc = &omap34xx_sr_sysc,
1378         .rev  = 1,
1379 };
1380
1381 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1382         .sidle_shift    = 24,
1383         .enwkup_shift   = 26,
1384 };
1385
1386 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1387         .sysc_offs      = 0x38,
1388         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1389         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1390                         SYSC_NO_CACHE),
1391         .sysc_fields    = &omap36xx_sr_sysc_fields,
1392 };
1393
1394 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1395         .name = "smartreflex",
1396         .sysc = &omap36xx_sr_sysc,
1397         .rev  = 2,
1398 };
1399
1400 /* SR1 */
1401 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1402         .sensor_voltdm_name   = "mpu_iva",
1403 };
1404
1405 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1406         { .irq = 18 + OMAP_INTC_START, },
1407         { .irq = -1 },
1408 };
1409
1410 static struct omap_hwmod omap34xx_sr1_hwmod = {
1411         .name           = "smartreflex_mpu_iva",
1412         .class          = &omap34xx_smartreflex_hwmod_class,
1413         .main_clk       = "sr1_fck",
1414         .prcm           = {
1415                 .omap2 = {
1416                         .prcm_reg_id = 1,
1417                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1418                         .module_offs = WKUP_MOD,
1419                         .idlest_reg_id = 1,
1420                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1421                 },
1422         },
1423         .dev_attr       = &sr1_dev_attr,
1424         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1425         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1426 };
1427
1428 static struct omap_hwmod omap36xx_sr1_hwmod = {
1429         .name           = "smartreflex_mpu_iva",
1430         .class          = &omap36xx_smartreflex_hwmod_class,
1431         .main_clk       = "sr1_fck",
1432         .prcm           = {
1433                 .omap2 = {
1434                         .prcm_reg_id = 1,
1435                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1436                         .module_offs = WKUP_MOD,
1437                         .idlest_reg_id = 1,
1438                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1439                 },
1440         },
1441         .dev_attr       = &sr1_dev_attr,
1442         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1443 };
1444
1445 /* SR2 */
1446 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1447         .sensor_voltdm_name     = "core",
1448 };
1449
1450 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1451         { .irq = 19 + OMAP_INTC_START, },
1452         { .irq = -1 },
1453 };
1454
1455 static struct omap_hwmod omap34xx_sr2_hwmod = {
1456         .name           = "smartreflex_core",
1457         .class          = &omap34xx_smartreflex_hwmod_class,
1458         .main_clk       = "sr2_fck",
1459         .prcm           = {
1460                 .omap2 = {
1461                         .prcm_reg_id = 1,
1462                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1463                         .module_offs = WKUP_MOD,
1464                         .idlest_reg_id = 1,
1465                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1466                 },
1467         },
1468         .dev_attr       = &sr2_dev_attr,
1469         .mpu_irqs       = omap3_smartreflex_core_irqs,
1470         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1471 };
1472
1473 static struct omap_hwmod omap36xx_sr2_hwmod = {
1474         .name           = "smartreflex_core",
1475         .class          = &omap36xx_smartreflex_hwmod_class,
1476         .main_clk       = "sr2_fck",
1477         .prcm           = {
1478                 .omap2 = {
1479                         .prcm_reg_id = 1,
1480                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1481                         .module_offs = WKUP_MOD,
1482                         .idlest_reg_id = 1,
1483                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1484                 },
1485         },
1486         .dev_attr       = &sr2_dev_attr,
1487         .mpu_irqs       = omap3_smartreflex_core_irqs,
1488 };
1489
1490 /*
1491  * 'mailbox' class
1492  * mailbox module allowing communication between the on-chip processors
1493  * using a queued mailbox-interrupt mechanism.
1494  */
1495
1496 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1497         .rev_offs       = 0x000,
1498         .sysc_offs      = 0x010,
1499         .syss_offs      = 0x014,
1500         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1501                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1502         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1503         .sysc_fields    = &omap_hwmod_sysc_type1,
1504 };
1505
1506 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1507         .name = "mailbox",
1508         .sysc = &omap3xxx_mailbox_sysc,
1509 };
1510
1511 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1512         { .irq = 26 + OMAP_INTC_START, },
1513         { .irq = -1 },
1514 };
1515
1516 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1517         .name           = "mailbox",
1518         .class          = &omap3xxx_mailbox_hwmod_class,
1519         .mpu_irqs       = omap3xxx_mailbox_irqs,
1520         .main_clk       = "mailboxes_ick",
1521         .prcm           = {
1522                 .omap2 = {
1523                         .prcm_reg_id = 1,
1524                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1525                         .module_offs = CORE_MOD,
1526                         .idlest_reg_id = 1,
1527                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1528                 },
1529         },
1530 };
1531
1532 /*
1533  * 'mcspi' class
1534  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1535  * bus
1536  */
1537
1538 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1539         .rev_offs       = 0x0000,
1540         .sysc_offs      = 0x0010,
1541         .syss_offs      = 0x0014,
1542         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1543                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1544                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1545         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1546         .sysc_fields    = &omap_hwmod_sysc_type1,
1547 };
1548
1549 static struct omap_hwmod_class omap34xx_mcspi_class = {
1550         .name = "mcspi",
1551         .sysc = &omap34xx_mcspi_sysc,
1552         .rev = OMAP3_MCSPI_REV,
1553 };
1554
1555 /* mcspi1 */
1556 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1557         .num_chipselect = 4,
1558 };
1559
1560 static struct omap_hwmod omap34xx_mcspi1 = {
1561         .name           = "mcspi1",
1562         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1563         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1564         .main_clk       = "mcspi1_fck",
1565         .prcm           = {
1566                 .omap2 = {
1567                         .module_offs = CORE_MOD,
1568                         .prcm_reg_id = 1,
1569                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1570                         .idlest_reg_id = 1,
1571                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1572                 },
1573         },
1574         .class          = &omap34xx_mcspi_class,
1575         .dev_attr       = &omap_mcspi1_dev_attr,
1576 };
1577
1578 /* mcspi2 */
1579 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1580         .num_chipselect = 2,
1581 };
1582
1583 static struct omap_hwmod omap34xx_mcspi2 = {
1584         .name           = "mcspi2",
1585         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1586         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1587         .main_clk       = "mcspi2_fck",
1588         .prcm           = {
1589                 .omap2 = {
1590                         .module_offs = CORE_MOD,
1591                         .prcm_reg_id = 1,
1592                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1593                         .idlest_reg_id = 1,
1594                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1595                 },
1596         },
1597         .class          = &omap34xx_mcspi_class,
1598         .dev_attr       = &omap_mcspi2_dev_attr,
1599 };
1600
1601 /* mcspi3 */
1602 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1603         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1604         { .irq = -1 },
1605 };
1606
1607 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1608         { .name = "tx0", .dma_req = 15 },
1609         { .name = "rx0", .dma_req = 16 },
1610         { .name = "tx1", .dma_req = 23 },
1611         { .name = "rx1", .dma_req = 24 },
1612         { .dma_req = -1 }
1613 };
1614
1615 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1616         .num_chipselect = 2,
1617 };
1618
1619 static struct omap_hwmod omap34xx_mcspi3 = {
1620         .name           = "mcspi3",
1621         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1622         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1623         .main_clk       = "mcspi3_fck",
1624         .prcm           = {
1625                 .omap2 = {
1626                         .module_offs = CORE_MOD,
1627                         .prcm_reg_id = 1,
1628                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1629                         .idlest_reg_id = 1,
1630                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1631                 },
1632         },
1633         .class          = &omap34xx_mcspi_class,
1634         .dev_attr       = &omap_mcspi3_dev_attr,
1635 };
1636
1637 /* mcspi4 */
1638 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1639         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1640         { .irq = -1 },
1641 };
1642
1643 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1644         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1645         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1646         { .dma_req = -1 }
1647 };
1648
1649 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1650         .num_chipselect = 1,
1651 };
1652
1653 static struct omap_hwmod omap34xx_mcspi4 = {
1654         .name           = "mcspi4",
1655         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1656         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1657         .main_clk       = "mcspi4_fck",
1658         .prcm           = {
1659                 .omap2 = {
1660                         .module_offs = CORE_MOD,
1661                         .prcm_reg_id = 1,
1662                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1663                         .idlest_reg_id = 1,
1664                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1665                 },
1666         },
1667         .class          = &omap34xx_mcspi_class,
1668         .dev_attr       = &omap_mcspi4_dev_attr,
1669 };
1670
1671 /* usbhsotg */
1672 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1673         .rev_offs       = 0x0400,
1674         .sysc_offs      = 0x0404,
1675         .syss_offs      = 0x0408,
1676         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1677                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1678                           SYSC_HAS_AUTOIDLE),
1679         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1680                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1681         .sysc_fields    = &omap_hwmod_sysc_type1,
1682 };
1683
1684 static struct omap_hwmod_class usbotg_class = {
1685         .name = "usbotg",
1686         .sysc = &omap3xxx_usbhsotg_sysc,
1687 };
1688
1689 /* usb_otg_hs */
1690 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1691
1692         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1693         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1694         { .irq = -1 },
1695 };
1696
1697 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1698         .name           = "usb_otg_hs",
1699         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1700         .main_clk       = "hsotgusb_ick",
1701         .prcm           = {
1702                 .omap2 = {
1703                         .prcm_reg_id = 1,
1704                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1705                         .module_offs = CORE_MOD,
1706                         .idlest_reg_id = 1,
1707                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1708                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1709                 },
1710         },
1711         .class          = &usbotg_class,
1712
1713         /*
1714          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1715          * broken when autoidle is enabled
1716          * workaround is to disable the autoidle bit at module level.
1717          */
1718         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1719                                 | HWMOD_SWSUP_MSTANDBY,
1720 };
1721
1722 /* usb_otg_hs */
1723 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1724         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1725         { .irq = -1 },
1726 };
1727
1728 static struct omap_hwmod_class am35xx_usbotg_class = {
1729         .name = "am35xx_usbotg",
1730 };
1731
1732 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1733         .name           = "am35x_otg_hs",
1734         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1735         .main_clk       = "hsotgusb_fck",
1736         .class          = &am35xx_usbotg_class,
1737         .flags          = HWMOD_NO_IDLEST,
1738 };
1739
1740 /* MMC/SD/SDIO common */
1741 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1742         .rev_offs       = 0x1fc,
1743         .sysc_offs      = 0x10,
1744         .syss_offs      = 0x14,
1745         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1746                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1747                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1748         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1749         .sysc_fields    = &omap_hwmod_sysc_type1,
1750 };
1751
1752 static struct omap_hwmod_class omap34xx_mmc_class = {
1753         .name = "mmc",
1754         .sysc = &omap34xx_mmc_sysc,
1755 };
1756
1757 /* MMC/SD/SDIO1 */
1758
1759 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1760         { .irq = 83 + OMAP_INTC_START, },
1761         { .irq = -1 },
1762 };
1763
1764 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1765         { .name = "tx", .dma_req = 61, },
1766         { .name = "rx", .dma_req = 62, },
1767         { .dma_req = -1 }
1768 };
1769
1770 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1771         { .role = "dbck", .clk = "omap_32k_fck", },
1772 };
1773
1774 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1775         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1776 };
1777
1778 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1779 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1780         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1781                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1782 };
1783
1784 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1785         .name           = "mmc1",
1786         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1787         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1788         .opt_clks       = omap34xx_mmc1_opt_clks,
1789         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1790         .main_clk       = "mmchs1_fck",
1791         .prcm           = {
1792                 .omap2 = {
1793                         .module_offs = CORE_MOD,
1794                         .prcm_reg_id = 1,
1795                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1796                         .idlest_reg_id = 1,
1797                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1798                 },
1799         },
1800         .dev_attr       = &mmc1_pre_es3_dev_attr,
1801         .class          = &omap34xx_mmc_class,
1802 };
1803
1804 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1805         .name           = "mmc1",
1806         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1807         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1808         .opt_clks       = omap34xx_mmc1_opt_clks,
1809         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1810         .main_clk       = "mmchs1_fck",
1811         .prcm           = {
1812                 .omap2 = {
1813                         .module_offs = CORE_MOD,
1814                         .prcm_reg_id = 1,
1815                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1816                         .idlest_reg_id = 1,
1817                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1818                 },
1819         },
1820         .dev_attr       = &mmc1_dev_attr,
1821         .class          = &omap34xx_mmc_class,
1822 };
1823
1824 /* MMC/SD/SDIO2 */
1825
1826 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1827         { .irq = 86 + OMAP_INTC_START, },
1828         { .irq = -1 },
1829 };
1830
1831 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1832         { .name = "tx", .dma_req = 47, },
1833         { .name = "rx", .dma_req = 48, },
1834         { .dma_req = -1 }
1835 };
1836
1837 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1838         { .role = "dbck", .clk = "omap_32k_fck", },
1839 };
1840
1841 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1842 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1843         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1844 };
1845
1846 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1847         .name           = "mmc2",
1848         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1849         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1850         .opt_clks       = omap34xx_mmc2_opt_clks,
1851         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1852         .main_clk       = "mmchs2_fck",
1853         .prcm           = {
1854                 .omap2 = {
1855                         .module_offs = CORE_MOD,
1856                         .prcm_reg_id = 1,
1857                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1858                         .idlest_reg_id = 1,
1859                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1860                 },
1861         },
1862         .dev_attr       = &mmc2_pre_es3_dev_attr,
1863         .class          = &omap34xx_mmc_class,
1864 };
1865
1866 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1867         .name           = "mmc2",
1868         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1869         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1870         .opt_clks       = omap34xx_mmc2_opt_clks,
1871         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1872         .main_clk       = "mmchs2_fck",
1873         .prcm           = {
1874                 .omap2 = {
1875                         .module_offs = CORE_MOD,
1876                         .prcm_reg_id = 1,
1877                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1878                         .idlest_reg_id = 1,
1879                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1880                 },
1881         },
1882         .class          = &omap34xx_mmc_class,
1883 };
1884
1885 /* MMC/SD/SDIO3 */
1886
1887 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1888         { .irq = 94 + OMAP_INTC_START, },
1889         { .irq = -1 },
1890 };
1891
1892 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1893         { .name = "tx", .dma_req = 77, },
1894         { .name = "rx", .dma_req = 78, },
1895         { .dma_req = -1 }
1896 };
1897
1898 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1899         { .role = "dbck", .clk = "omap_32k_fck", },
1900 };
1901
1902 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1903         .name           = "mmc3",
1904         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1905         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1906         .opt_clks       = omap34xx_mmc3_opt_clks,
1907         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1908         .main_clk       = "mmchs3_fck",
1909         .prcm           = {
1910                 .omap2 = {
1911                         .prcm_reg_id = 1,
1912                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1913                         .idlest_reg_id = 1,
1914                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1915                 },
1916         },
1917         .class          = &omap34xx_mmc_class,
1918 };
1919
1920 /*
1921  * 'usb_host_hs' class
1922  * high-speed multi-port usb host controller
1923  */
1924
1925 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1926         .rev_offs       = 0x0000,
1927         .sysc_offs      = 0x0010,
1928         .syss_offs      = 0x0014,
1929         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1930                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1931                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1932         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1933                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1934         .sysc_fields    = &omap_hwmod_sysc_type1,
1935 };
1936
1937 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1938         .name = "usb_host_hs",
1939         .sysc = &omap3xxx_usb_host_hs_sysc,
1940 };
1941
1942 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1943           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1944 };
1945
1946 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1947         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1948         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1949         { .irq = -1 },
1950 };
1951
1952 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1953         .name           = "usb_host_hs",
1954         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1955         .clkdm_name     = "l3_init_clkdm",
1956         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1957         .main_clk       = "usbhost_48m_fck",
1958         .prcm = {
1959                 .omap2 = {
1960                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1961                         .prcm_reg_id = 1,
1962                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1963                         .idlest_reg_id = 1,
1964                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1965                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1966                 },
1967         },
1968         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1969         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1970
1971         /*
1972          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1973          * id: i660
1974          *
1975          * Description:
1976          * In the following configuration :
1977          * - USBHOST module is set to smart-idle mode
1978          * - PRCM asserts idle_req to the USBHOST module ( This typically
1979          *   happens when the system is going to a low power mode : all ports
1980          *   have been suspended, the master part of the USBHOST module has
1981          *   entered the standby state, and SW has cut the functional clocks)
1982          * - an USBHOST interrupt occurs before the module is able to answer
1983          *   idle_ack, typically a remote wakeup IRQ.
1984          * Then the USB HOST module will enter a deadlock situation where it
1985          * is no more accessible nor functional.
1986          *
1987          * Workaround:
1988          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1989          */
1990
1991         /*
1992          * Errata: USB host EHCI may stall when entering smart-standby mode
1993          * Id: i571
1994          *
1995          * Description:
1996          * When the USBHOST module is set to smart-standby mode, and when it is
1997          * ready to enter the standby state (i.e. all ports are suspended and
1998          * all attached devices are in suspend mode), then it can wrongly assert
1999          * the Mstandby signal too early while there are still some residual OCP
2000          * transactions ongoing. If this condition occurs, the internal state
2001          * machine may go to an undefined state and the USB link may be stuck
2002          * upon the next resume.
2003          *
2004          * Workaround:
2005          * Don't use smart standby; use only force standby,
2006          * hence HWMOD_SWSUP_MSTANDBY
2007          */
2008
2009         /*
2010          * During system boot; If the hwmod framework resets the module
2011          * the module will have smart idle settings; which can lead to deadlock
2012          * (above Errata Id:i660); so, dont reset the module during boot;
2013          * Use HWMOD_INIT_NO_RESET.
2014          */
2015
2016         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2017                           HWMOD_INIT_NO_RESET,
2018 };
2019
2020 /*
2021  * 'usb_tll_hs' class
2022  * usb_tll_hs module is the adapter on the usb_host_hs ports
2023  */
2024 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2025         .rev_offs       = 0x0000,
2026         .sysc_offs      = 0x0010,
2027         .syss_offs      = 0x0014,
2028         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2029                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2030                            SYSC_HAS_AUTOIDLE),
2031         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2032         .sysc_fields    = &omap_hwmod_sysc_type1,
2033 };
2034
2035 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2036         .name = "usb_tll_hs",
2037         .sysc = &omap3xxx_usb_tll_hs_sysc,
2038 };
2039
2040 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2041         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2042         { .irq = -1 },
2043 };
2044
2045 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2046         .name           = "usb_tll_hs",
2047         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2048         .clkdm_name     = "l3_init_clkdm",
2049         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2050         .main_clk       = "usbtll_fck",
2051         .prcm = {
2052                 .omap2 = {
2053                         .module_offs = CORE_MOD,
2054                         .prcm_reg_id = 3,
2055                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2056                         .idlest_reg_id = 3,
2057                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2058                 },
2059         },
2060 };
2061
2062 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2063         .name           = "hdq1w",
2064         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2065         .main_clk       = "hdq_fck",
2066         .prcm           = {
2067                 .omap2 = {
2068                         .module_offs = CORE_MOD,
2069                         .prcm_reg_id = 1,
2070                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2071                         .idlest_reg_id = 1,
2072                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2073                 },
2074         },
2075         .class          = &omap2_hdq1w_class,
2076 };
2077
2078 /* SAD2D */
2079 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2080         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2081         { .name = "rst_modem_sw", .rst_shift = 1 },
2082 };
2083
2084 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2085         .name                   = "sad2d",
2086 };
2087
2088 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2089         .name           = "sad2d",
2090         .rst_lines      = omap3xxx_sad2d_resets,
2091         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2092         .main_clk       = "sad2d_ick",
2093         .prcm           = {
2094                 .omap2 = {
2095                         .module_offs = CORE_MOD,
2096                         .prcm_reg_id = 1,
2097                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2098                         .idlest_reg_id = 1,
2099                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2100                 },
2101         },
2102         .class          = &omap3xxx_sad2d_class,
2103 };
2104
2105 /*
2106  * '32K sync counter' class
2107  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2108  */
2109 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2110         .rev_offs       = 0x0000,
2111         .sysc_offs      = 0x0004,
2112         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2113         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2114         .sysc_fields    = &omap_hwmod_sysc_type1,
2115 };
2116
2117 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2118         .name   = "counter",
2119         .sysc   = &omap3xxx_counter_sysc,
2120 };
2121
2122 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2123         .name           = "counter_32k",
2124         .class          = &omap3xxx_counter_hwmod_class,
2125         .clkdm_name     = "wkup_clkdm",
2126         .flags          = HWMOD_SWSUP_SIDLE,
2127         .main_clk       = "wkup_32k_fck",
2128         .prcm           = {
2129                 .omap2  = {
2130                         .module_offs = WKUP_MOD,
2131                         .prcm_reg_id = 1,
2132                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2133                         .idlest_reg_id = 1,
2134                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2135                 },
2136         },
2137 };
2138
2139 /*
2140  * 'gpmc' class
2141  * general purpose memory controller
2142  */
2143
2144 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2145         .rev_offs       = 0x0000,
2146         .sysc_offs      = 0x0010,
2147         .syss_offs      = 0x0014,
2148         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2149                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2150         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2151         .sysc_fields    = &omap_hwmod_sysc_type1,
2152 };
2153
2154 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2155         .name   = "gpmc",
2156         .sysc   = &omap3xxx_gpmc_sysc,
2157 };
2158
2159 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2160         { .irq = 20 },
2161         { .irq = -1 }
2162 };
2163
2164 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2165         .name           = "gpmc",
2166         .class          = &omap3xxx_gpmc_hwmod_class,
2167         .clkdm_name     = "core_l3_clkdm",
2168         .mpu_irqs       = omap3xxx_gpmc_irqs,
2169         .main_clk       = "gpmc_fck",
2170         /*
2171          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2172          * block.  It is not being added due to any known bugs with
2173          * resetting the GPMC IP block, but rather because any timings
2174          * set by the bootloader are not being correctly programmed by
2175          * the kernel from the board file or DT data.
2176          * HWMOD_INIT_NO_RESET should be removed ASAP.
2177          */
2178         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2179                            HWMOD_NO_IDLEST),
2180 };
2181
2182 /*
2183  * interfaces
2184  */
2185
2186 /* L3 -> L4_CORE interface */
2187 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2188         .master = &omap3xxx_l3_main_hwmod,
2189         .slave  = &omap3xxx_l4_core_hwmod,
2190         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2191 };
2192
2193 /* L3 -> L4_PER interface */
2194 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2195         .master = &omap3xxx_l3_main_hwmod,
2196         .slave  = &omap3xxx_l4_per_hwmod,
2197         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2198 };
2199
2200 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2201         {
2202                 .pa_start       = 0x68000000,
2203                 .pa_end         = 0x6800ffff,
2204                 .flags          = ADDR_TYPE_RT,
2205         },
2206         { }
2207 };
2208
2209 /* MPU -> L3 interface */
2210 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2211         .master   = &omap3xxx_mpu_hwmod,
2212         .slave    = &omap3xxx_l3_main_hwmod,
2213         .addr     = omap3xxx_l3_main_addrs,
2214         .user   = OCP_USER_MPU,
2215 };
2216
2217 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2218         {
2219                 .pa_start       = 0x54000000,
2220                 .pa_end         = 0x547fffff,
2221                 .flags          = ADDR_TYPE_RT,
2222         },
2223         { }
2224 };
2225
2226 /* l3 -> debugss */
2227 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2228         .master         = &omap3xxx_l3_main_hwmod,
2229         .slave          = &omap3xxx_debugss_hwmod,
2230         .addr           = omap3xxx_l4_emu_addrs,
2231         .user           = OCP_USER_MPU,
2232 };
2233
2234 /* DSS -> l3 */
2235 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2236         .master         = &omap3430es1_dss_core_hwmod,
2237         .slave          = &omap3xxx_l3_main_hwmod,
2238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2239 };
2240
2241 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2242         .master         = &omap3xxx_dss_core_hwmod,
2243         .slave          = &omap3xxx_l3_main_hwmod,
2244         .fw = {
2245                 .omap2 = {
2246                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2247                         .flags  = OMAP_FIREWALL_L3,
2248                 }
2249         },
2250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2251 };
2252
2253 /* l3_core -> usbhsotg interface */
2254 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2255         .master         = &omap3xxx_usbhsotg_hwmod,
2256         .slave          = &omap3xxx_l3_main_hwmod,
2257         .clk            = "core_l3_ick",
2258         .user           = OCP_USER_MPU,
2259 };
2260
2261 /* l3_core -> am35xx_usbhsotg interface */
2262 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2263         .master         = &am35xx_usbhsotg_hwmod,
2264         .slave          = &omap3xxx_l3_main_hwmod,
2265         .clk            = "hsotgusb_ick",
2266         .user           = OCP_USER_MPU,
2267 };
2268
2269 /* l3_core -> sad2d interface */
2270 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2271         .master         = &omap3xxx_sad2d_hwmod,
2272         .slave          = &omap3xxx_l3_main_hwmod,
2273         .clk            = "core_l3_ick",
2274         .user           = OCP_USER_MPU,
2275 };
2276
2277 /* L4_CORE -> L4_WKUP interface */
2278 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2279         .master = &omap3xxx_l4_core_hwmod,
2280         .slave  = &omap3xxx_l4_wkup_hwmod,
2281         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2282 };
2283
2284 /* L4 CORE -> MMC1 interface */
2285 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2286         .master         = &omap3xxx_l4_core_hwmod,
2287         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2288         .clk            = "mmchs1_ick",
2289         .addr           = omap2430_mmc1_addr_space,
2290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2291         .flags          = OMAP_FIREWALL_L4
2292 };
2293
2294 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2295         .master         = &omap3xxx_l4_core_hwmod,
2296         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2297         .clk            = "mmchs1_ick",
2298         .addr           = omap2430_mmc1_addr_space,
2299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2300         .flags          = OMAP_FIREWALL_L4
2301 };
2302
2303 /* L4 CORE -> MMC2 interface */
2304 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2305         .master         = &omap3xxx_l4_core_hwmod,
2306         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2307         .clk            = "mmchs2_ick",
2308         .addr           = omap2430_mmc2_addr_space,
2309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2310         .flags          = OMAP_FIREWALL_L4
2311 };
2312
2313 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2314         .master         = &omap3xxx_l4_core_hwmod,
2315         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2316         .clk            = "mmchs2_ick",
2317         .addr           = omap2430_mmc2_addr_space,
2318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2319         .flags          = OMAP_FIREWALL_L4
2320 };
2321
2322 /* L4 CORE -> MMC3 interface */
2323 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2324         {
2325                 .pa_start       = 0x480ad000,
2326                 .pa_end         = 0x480ad1ff,
2327                 .flags          = ADDR_TYPE_RT,
2328         },
2329         { }
2330 };
2331
2332 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2333         .master         = &omap3xxx_l4_core_hwmod,
2334         .slave          = &omap3xxx_mmc3_hwmod,
2335         .clk            = "mmchs3_ick",
2336         .addr           = omap3xxx_mmc3_addr_space,
2337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2338         .flags          = OMAP_FIREWALL_L4
2339 };
2340
2341 /* L4 CORE -> UART1 interface */
2342 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2343         {
2344                 .pa_start       = OMAP3_UART1_BASE,
2345                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2346                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2347         },
2348         { }
2349 };
2350
2351 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2352         .master         = &omap3xxx_l4_core_hwmod,
2353         .slave          = &omap3xxx_uart1_hwmod,
2354         .clk            = "uart1_ick",
2355         .addr           = omap3xxx_uart1_addr_space,
2356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2357 };
2358
2359 /* L4 CORE -> UART2 interface */
2360 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2361         {
2362                 .pa_start       = OMAP3_UART2_BASE,
2363                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2364                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2365         },
2366         { }
2367 };
2368
2369 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2370         .master         = &omap3xxx_l4_core_hwmod,
2371         .slave          = &omap3xxx_uart2_hwmod,
2372         .clk            = "uart2_ick",
2373         .addr           = omap3xxx_uart2_addr_space,
2374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2375 };
2376
2377 /* L4 PER -> UART3 interface */
2378 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2379         {
2380                 .pa_start       = OMAP3_UART3_BASE,
2381                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2382                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2383         },
2384         { }
2385 };
2386
2387 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2388         .master         = &omap3xxx_l4_per_hwmod,
2389         .slave          = &omap3xxx_uart3_hwmod,
2390         .clk            = "uart3_ick",
2391         .addr           = omap3xxx_uart3_addr_space,
2392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2393 };
2394
2395 /* L4 PER -> UART4 interface */
2396 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2397         {
2398                 .pa_start       = OMAP3_UART4_BASE,
2399                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2400                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2401         },
2402         { }
2403 };
2404
2405 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2406         .master         = &omap3xxx_l4_per_hwmod,
2407         .slave          = &omap36xx_uart4_hwmod,
2408         .clk            = "uart4_ick",
2409         .addr           = omap36xx_uart4_addr_space,
2410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2411 };
2412
2413 /* AM35xx: L4 CORE -> UART4 interface */
2414 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2415         {
2416                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2417                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2418                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2419         },
2420         { }
2421 };
2422
2423 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2424         .master         = &omap3xxx_l4_core_hwmod,
2425         .slave          = &am35xx_uart4_hwmod,
2426         .clk            = "uart4_ick",
2427         .addr           = am35xx_uart4_addr_space,
2428         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2429 };
2430
2431 /* L4 CORE -> I2C1 interface */
2432 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2433         .master         = &omap3xxx_l4_core_hwmod,
2434         .slave          = &omap3xxx_i2c1_hwmod,
2435         .clk            = "i2c1_ick",
2436         .addr           = omap2_i2c1_addr_space,
2437         .fw = {
2438                 .omap2 = {
2439                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2440                         .l4_prot_group = 7,
2441                         .flags  = OMAP_FIREWALL_L4,
2442                 }
2443         },
2444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2445 };
2446
2447 /* L4 CORE -> I2C2 interface */
2448 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2449         .master         = &omap3xxx_l4_core_hwmod,
2450         .slave          = &omap3xxx_i2c2_hwmod,
2451         .clk            = "i2c2_ick",
2452         .addr           = omap2_i2c2_addr_space,
2453         .fw = {
2454                 .omap2 = {
2455                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2456                         .l4_prot_group = 7,
2457                         .flags = OMAP_FIREWALL_L4,
2458                 }
2459         },
2460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2461 };
2462
2463 /* L4 CORE -> I2C3 interface */
2464 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2465         {
2466                 .pa_start       = 0x48060000,
2467                 .pa_end         = 0x48060000 + SZ_128 - 1,
2468                 .flags          = ADDR_TYPE_RT,
2469         },
2470         { }
2471 };
2472
2473 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2474         .master         = &omap3xxx_l4_core_hwmod,
2475         .slave          = &omap3xxx_i2c3_hwmod,
2476         .clk            = "i2c3_ick",
2477         .addr           = omap3xxx_i2c3_addr_space,
2478         .fw = {
2479                 .omap2 = {
2480                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2481                         .l4_prot_group = 7,
2482                         .flags = OMAP_FIREWALL_L4,
2483                 }
2484         },
2485         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2486 };
2487
2488 /* L4 CORE -> SR1 interface */
2489 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2490         {
2491                 .pa_start       = OMAP34XX_SR1_BASE,
2492                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2493                 .flags          = ADDR_TYPE_RT,
2494         },
2495         { }
2496 };
2497
2498 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2499         .master         = &omap3xxx_l4_core_hwmod,
2500         .slave          = &omap34xx_sr1_hwmod,
2501         .clk            = "sr_l4_ick",
2502         .addr           = omap3_sr1_addr_space,
2503         .user           = OCP_USER_MPU,
2504 };
2505
2506 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2507         .master         = &omap3xxx_l4_core_hwmod,
2508         .slave          = &omap36xx_sr1_hwmod,
2509         .clk            = "sr_l4_ick",
2510         .addr           = omap3_sr1_addr_space,
2511         .user           = OCP_USER_MPU,
2512 };
2513
2514 /* L4 CORE -> SR1 interface */
2515 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2516         {
2517                 .pa_start       = OMAP34XX_SR2_BASE,
2518                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2519                 .flags          = ADDR_TYPE_RT,
2520         },
2521         { }
2522 };
2523
2524 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2525         .master         = &omap3xxx_l4_core_hwmod,
2526         .slave          = &omap34xx_sr2_hwmod,
2527         .clk            = "sr_l4_ick",
2528         .addr           = omap3_sr2_addr_space,
2529         .user           = OCP_USER_MPU,
2530 };
2531
2532 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2533         .master         = &omap3xxx_l4_core_hwmod,
2534         .slave          = &omap36xx_sr2_hwmod,
2535         .clk            = "sr_l4_ick",
2536         .addr           = omap3_sr2_addr_space,
2537         .user           = OCP_USER_MPU,
2538 };
2539
2540 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2541         {
2542                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2543                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2544                 .flags          = ADDR_TYPE_RT
2545         },
2546         { }
2547 };
2548
2549 /* l4_core -> usbhsotg  */
2550 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2551         .master         = &omap3xxx_l4_core_hwmod,
2552         .slave          = &omap3xxx_usbhsotg_hwmod,
2553         .clk            = "l4_ick",
2554         .addr           = omap3xxx_usbhsotg_addrs,
2555         .user           = OCP_USER_MPU,
2556 };
2557
2558 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2559         {
2560                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2561                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2562                 .flags          = ADDR_TYPE_RT
2563         },
2564         { }
2565 };
2566
2567 /* l4_core -> usbhsotg  */
2568 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2569         .master         = &omap3xxx_l4_core_hwmod,
2570         .slave          = &am35xx_usbhsotg_hwmod,
2571         .clk            = "hsotgusb_ick",
2572         .addr           = am35xx_usbhsotg_addrs,
2573         .user           = OCP_USER_MPU,
2574 };
2575
2576 /* L4_WKUP -> L4_SEC interface */
2577 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2578         .master = &omap3xxx_l4_wkup_hwmod,
2579         .slave  = &omap3xxx_l4_sec_hwmod,
2580         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2581 };
2582
2583 /* IVA2 <- L3 interface */
2584 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2585         .master         = &omap3xxx_l3_main_hwmod,
2586         .slave          = &omap3xxx_iva_hwmod,
2587         .clk            = "core_l3_ick",
2588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2589 };
2590
2591 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2592         {
2593                 .pa_start       = 0x48318000,
2594                 .pa_end         = 0x48318000 + SZ_1K - 1,
2595                 .flags          = ADDR_TYPE_RT
2596         },
2597         { }
2598 };
2599
2600 /* l4_wkup -> timer1 */
2601 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2602         .master         = &omap3xxx_l4_wkup_hwmod,
2603         .slave          = &omap3xxx_timer1_hwmod,
2604         .clk            = "gpt1_ick",
2605         .addr           = omap3xxx_timer1_addrs,
2606         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2607 };
2608
2609 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2610         {
2611                 .pa_start       = 0x49032000,
2612                 .pa_end         = 0x49032000 + SZ_1K - 1,
2613                 .flags          = ADDR_TYPE_RT
2614         },
2615         { }
2616 };
2617
2618 /* l4_per -> timer2 */
2619 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2620         .master         = &omap3xxx_l4_per_hwmod,
2621         .slave          = &omap3xxx_timer2_hwmod,
2622         .clk            = "gpt2_ick",
2623         .addr           = omap3xxx_timer2_addrs,
2624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2625 };
2626
2627 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2628         {
2629                 .pa_start       = 0x49034000,
2630                 .pa_end         = 0x49034000 + SZ_1K - 1,
2631                 .flags          = ADDR_TYPE_RT
2632         },
2633         { }
2634 };
2635
2636 /* l4_per -> timer3 */
2637 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2638         .master         = &omap3xxx_l4_per_hwmod,
2639         .slave          = &omap3xxx_timer3_hwmod,
2640         .clk            = "gpt3_ick",
2641         .addr           = omap3xxx_timer3_addrs,
2642         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2643 };
2644
2645 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2646         {
2647                 .pa_start       = 0x49036000,
2648                 .pa_end         = 0x49036000 + SZ_1K - 1,
2649                 .flags          = ADDR_TYPE_RT
2650         },
2651         { }
2652 };
2653
2654 /* l4_per -> timer4 */
2655 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2656         .master         = &omap3xxx_l4_per_hwmod,
2657         .slave          = &omap3xxx_timer4_hwmod,
2658         .clk            = "gpt4_ick",
2659         .addr           = omap3xxx_timer4_addrs,
2660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2661 };
2662
2663 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2664         {
2665                 .pa_start       = 0x49038000,
2666                 .pa_end         = 0x49038000 + SZ_1K - 1,
2667                 .flags          = ADDR_TYPE_RT
2668         },
2669         { }
2670 };
2671
2672 /* l4_per -> timer5 */
2673 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2674         .master         = &omap3xxx_l4_per_hwmod,
2675         .slave          = &omap3xxx_timer5_hwmod,
2676         .clk            = "gpt5_ick",
2677         .addr           = omap3xxx_timer5_addrs,
2678         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2679 };
2680
2681 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2682         {
2683                 .pa_start       = 0x4903A000,
2684                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2685                 .flags          = ADDR_TYPE_RT
2686         },
2687         { }
2688 };
2689
2690 /* l4_per -> timer6 */
2691 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2692         .master         = &omap3xxx_l4_per_hwmod,
2693         .slave          = &omap3xxx_timer6_hwmod,
2694         .clk            = "gpt6_ick",
2695         .addr           = omap3xxx_timer6_addrs,
2696         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2697 };
2698
2699 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2700         {
2701                 .pa_start       = 0x4903C000,
2702                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2703                 .flags          = ADDR_TYPE_RT
2704         },
2705         { }
2706 };
2707
2708 /* l4_per -> timer7 */
2709 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2710         .master         = &omap3xxx_l4_per_hwmod,
2711         .slave          = &omap3xxx_timer7_hwmod,
2712         .clk            = "gpt7_ick",
2713         .addr           = omap3xxx_timer7_addrs,
2714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2715 };
2716
2717 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2718         {
2719                 .pa_start       = 0x4903E000,
2720                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2721                 .flags          = ADDR_TYPE_RT
2722         },
2723         { }
2724 };
2725
2726 /* l4_per -> timer8 */
2727 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2728         .master         = &omap3xxx_l4_per_hwmod,
2729         .slave          = &omap3xxx_timer8_hwmod,
2730         .clk            = "gpt8_ick",
2731         .addr           = omap3xxx_timer8_addrs,
2732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2733 };
2734
2735 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2736         {
2737                 .pa_start       = 0x49040000,
2738                 .pa_end         = 0x49040000 + SZ_1K - 1,
2739                 .flags          = ADDR_TYPE_RT
2740         },
2741         { }
2742 };
2743
2744 /* l4_per -> timer9 */
2745 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2746         .master         = &omap3xxx_l4_per_hwmod,
2747         .slave          = &omap3xxx_timer9_hwmod,
2748         .clk            = "gpt9_ick",
2749         .addr           = omap3xxx_timer9_addrs,
2750         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2751 };
2752
2753 /* l4_core -> timer10 */
2754 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2755         .master         = &omap3xxx_l4_core_hwmod,
2756         .slave          = &omap3xxx_timer10_hwmod,
2757         .clk            = "gpt10_ick",
2758         .addr           = omap2_timer10_addrs,
2759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2760 };
2761
2762 /* l4_core -> timer11 */
2763 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2764         .master         = &omap3xxx_l4_core_hwmod,
2765         .slave          = &omap3xxx_timer11_hwmod,
2766         .clk            = "gpt11_ick",
2767         .addr           = omap2_timer11_addrs,
2768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2769 };
2770
2771 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2772         {
2773                 .pa_start       = 0x48304000,
2774                 .pa_end         = 0x48304000 + SZ_1K - 1,
2775                 .flags          = ADDR_TYPE_RT
2776         },
2777         { }
2778 };
2779
2780 /* l4_core -> timer12 */
2781 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2782         .master         = &omap3xxx_l4_sec_hwmod,
2783         .slave          = &omap3xxx_timer12_hwmod,
2784         .clk            = "gpt12_ick",
2785         .addr           = omap3xxx_timer12_addrs,
2786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2787 };
2788
2789 /* l4_wkup -> wd_timer2 */
2790 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2791         {
2792                 .pa_start       = 0x48314000,
2793                 .pa_end         = 0x4831407f,
2794                 .flags          = ADDR_TYPE_RT
2795         },
2796         { }
2797 };
2798
2799 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2800         .master         = &omap3xxx_l4_wkup_hwmod,
2801         .slave          = &omap3xxx_wd_timer2_hwmod,
2802         .clk            = "wdt2_ick",
2803         .addr           = omap3xxx_wd_timer2_addrs,
2804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2805 };
2806
2807 /* l4_core -> dss */
2808 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2809         .master         = &omap3xxx_l4_core_hwmod,
2810         .slave          = &omap3430es1_dss_core_hwmod,
2811         .clk            = "dss_ick",
2812         .addr           = omap2_dss_addrs,
2813         .fw = {
2814                 .omap2 = {
2815                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2816                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2817                         .flags  = OMAP_FIREWALL_L4,
2818                 }
2819         },
2820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2821 };
2822
2823 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2824         .master         = &omap3xxx_l4_core_hwmod,
2825         .slave          = &omap3xxx_dss_core_hwmod,
2826         .clk            = "dss_ick",
2827         .addr           = omap2_dss_addrs,
2828         .fw = {
2829                 .omap2 = {
2830                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2831                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2832                         .flags  = OMAP_FIREWALL_L4,
2833                 }
2834         },
2835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2836 };
2837
2838 /* l4_core -> dss_dispc */
2839 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2840         .master         = &omap3xxx_l4_core_hwmod,
2841         .slave          = &omap3xxx_dss_dispc_hwmod,
2842         .clk            = "dss_ick",
2843         .addr           = omap2_dss_dispc_addrs,
2844         .fw = {
2845                 .omap2 = {
2846                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2847                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2848                         .flags  = OMAP_FIREWALL_L4,
2849                 }
2850         },
2851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2852 };
2853
2854 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2855         {
2856                 .pa_start       = 0x4804FC00,
2857                 .pa_end         = 0x4804FFFF,
2858                 .flags          = ADDR_TYPE_RT
2859         },
2860         { }
2861 };
2862
2863 /* l4_core -> dss_dsi1 */
2864 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2865         .master         = &omap3xxx_l4_core_hwmod,
2866         .slave          = &omap3xxx_dss_dsi1_hwmod,
2867         .clk            = "dss_ick",
2868         .addr           = omap3xxx_dss_dsi1_addrs,
2869         .fw = {
2870                 .omap2 = {
2871                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2872                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2873                         .flags  = OMAP_FIREWALL_L4,
2874                 }
2875         },
2876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2877 };
2878
2879 /* l4_core -> dss_rfbi */
2880 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2881         .master         = &omap3xxx_l4_core_hwmod,
2882         .slave          = &omap3xxx_dss_rfbi_hwmod,
2883         .clk            = "dss_ick",
2884         .addr           = omap2_dss_rfbi_addrs,
2885         .fw = {
2886                 .omap2 = {
2887                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2888                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2889                         .flags  = OMAP_FIREWALL_L4,
2890                 }
2891         },
2892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2893 };
2894
2895 /* l4_core -> dss_venc */
2896 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2897         .master         = &omap3xxx_l4_core_hwmod,
2898         .slave          = &omap3xxx_dss_venc_hwmod,
2899         .clk            = "dss_ick",
2900         .addr           = omap2_dss_venc_addrs,
2901         .fw = {
2902                 .omap2 = {
2903                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2904                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2905                         .flags  = OMAP_FIREWALL_L4,
2906                 }
2907         },
2908         .flags          = OCPIF_SWSUP_IDLE,
2909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2910 };
2911
2912 /* l4_wkup -> gpio1 */
2913 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2914         {
2915                 .pa_start       = 0x48310000,
2916                 .pa_end         = 0x483101ff,
2917                 .flags          = ADDR_TYPE_RT
2918         },
2919         { }
2920 };
2921
2922 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2923         .master         = &omap3xxx_l4_wkup_hwmod,
2924         .slave          = &omap3xxx_gpio1_hwmod,
2925         .addr           = omap3xxx_gpio1_addrs,
2926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2927 };
2928
2929 /* l4_per -> gpio2 */
2930 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2931         {
2932                 .pa_start       = 0x49050000,
2933                 .pa_end         = 0x490501ff,
2934                 .flags          = ADDR_TYPE_RT
2935         },
2936         { }
2937 };
2938
2939 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2940         .master         = &omap3xxx_l4_per_hwmod,
2941         .slave          = &omap3xxx_gpio2_hwmod,
2942         .addr           = omap3xxx_gpio2_addrs,
2943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2944 };
2945
2946 /* l4_per -> gpio3 */
2947 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2948         {
2949                 .pa_start       = 0x49052000,
2950                 .pa_end         = 0x490521ff,
2951                 .flags          = ADDR_TYPE_RT
2952         },
2953         { }
2954 };
2955
2956 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2957         .master         = &omap3xxx_l4_per_hwmod,
2958         .slave          = &omap3xxx_gpio3_hwmod,
2959         .addr           = omap3xxx_gpio3_addrs,
2960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2961 };
2962
2963 /*
2964  * 'mmu' class
2965  * The memory management unit performs virtual to physical address translation
2966  * for its requestors.
2967  */
2968
2969 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2970         .rev_offs       = 0x000,
2971         .sysc_offs      = 0x010,
2972         .syss_offs      = 0x014,
2973         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2974                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2975         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2976         .sysc_fields    = &omap_hwmod_sysc_type1,
2977 };
2978
2979 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2980         .name = "mmu",
2981         .sysc = &mmu_sysc,
2982 };
2983
2984 /* mmu isp */
2985
2986 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2987         .da_start       = 0x0,
2988         .da_end         = 0xfffff000,
2989         .nr_tlb_entries = 8,
2990 };
2991
2992 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2993 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2994         { .irq = 24 },
2995         { .irq = -1 }
2996 };
2997
2998 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2999         {
3000                 .pa_start       = 0x480bd400,
3001                 .pa_end         = 0x480bd47f,
3002                 .flags          = ADDR_TYPE_RT,
3003         },
3004         { }
3005 };
3006
3007 /* l4_core -> mmu isp */
3008 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3009         .master         = &omap3xxx_l4_core_hwmod,
3010         .slave          = &omap3xxx_mmu_isp_hwmod,
3011         .addr           = omap3xxx_mmu_isp_addrs,
3012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3013 };
3014
3015 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3016         .name           = "mmu_isp",
3017         .class          = &omap3xxx_mmu_hwmod_class,
3018         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
3019         .main_clk       = "cam_ick",
3020         .dev_attr       = &mmu_isp_dev_attr,
3021         .flags          = HWMOD_NO_IDLEST,
3022 };
3023
3024 #ifdef CONFIG_OMAP_IOMMU_IVA2
3025
3026 /* mmu iva */
3027
3028 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3029         .da_start       = 0x11000000,
3030         .da_end         = 0xfffff000,
3031         .nr_tlb_entries = 32,
3032 };
3033
3034 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3035 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3036         { .irq = 28 },
3037         { .irq = -1 }
3038 };
3039
3040 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3041         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3042 };
3043
3044 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3045         {
3046                 .pa_start       = 0x5d000000,
3047                 .pa_end         = 0x5d00007f,
3048                 .flags          = ADDR_TYPE_RT,
3049         },
3050         { }
3051 };
3052
3053 /* l3_main -> iva mmu */
3054 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3055         .master         = &omap3xxx_l3_main_hwmod,
3056         .slave          = &omap3xxx_mmu_iva_hwmod,
3057         .addr           = omap3xxx_mmu_iva_addrs,
3058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3059 };
3060
3061 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3062         .name           = "mmu_iva",
3063         .class          = &omap3xxx_mmu_hwmod_class,
3064         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3065         .rst_lines      = omap3xxx_mmu_iva_resets,
3066         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3067         .main_clk       = "iva2_ck",
3068         .prcm = {
3069                 .omap2 = {
3070                         .module_offs = OMAP3430_IVA2_MOD,
3071                 },
3072         },
3073         .dev_attr       = &mmu_iva_dev_attr,
3074         .flags          = HWMOD_NO_IDLEST,
3075 };
3076
3077 #endif
3078
3079 /* l4_per -> gpio4 */
3080 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3081         {
3082                 .pa_start       = 0x49054000,
3083                 .pa_end         = 0x490541ff,
3084                 .flags          = ADDR_TYPE_RT
3085         },
3086         { }
3087 };
3088
3089 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3090         .master         = &omap3xxx_l4_per_hwmod,
3091         .slave          = &omap3xxx_gpio4_hwmod,
3092         .addr           = omap3xxx_gpio4_addrs,
3093         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3094 };
3095
3096 /* l4_per -> gpio5 */
3097 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3098         {
3099                 .pa_start       = 0x49056000,
3100                 .pa_end         = 0x490561ff,
3101                 .flags          = ADDR_TYPE_RT
3102         },
3103         { }
3104 };
3105
3106 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3107         .master         = &omap3xxx_l4_per_hwmod,
3108         .slave          = &omap3xxx_gpio5_hwmod,
3109         .addr           = omap3xxx_gpio5_addrs,
3110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3111 };
3112
3113 /* l4_per -> gpio6 */
3114 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3115         {
3116                 .pa_start       = 0x49058000,
3117                 .pa_end         = 0x490581ff,
3118                 .flags          = ADDR_TYPE_RT
3119         },
3120         { }
3121 };
3122
3123 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3124         .master         = &omap3xxx_l4_per_hwmod,
3125         .slave          = &omap3xxx_gpio6_hwmod,
3126         .addr           = omap3xxx_gpio6_addrs,
3127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3128 };
3129
3130 /* dma_system -> L3 */
3131 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3132         .master         = &omap3xxx_dma_system_hwmod,
3133         .slave          = &omap3xxx_l3_main_hwmod,
3134         .clk            = "core_l3_ick",
3135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3139         {
3140                 .pa_start       = 0x48056000,
3141                 .pa_end         = 0x48056fff,
3142                 .flags          = ADDR_TYPE_RT
3143         },
3144         { }
3145 };
3146
3147 /* l4_cfg -> dma_system */
3148 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3149         .master         = &omap3xxx_l4_core_hwmod,
3150         .slave          = &omap3xxx_dma_system_hwmod,
3151         .clk            = "core_l4_ick",
3152         .addr           = omap3xxx_dma_system_addrs,
3153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3154 };
3155
3156 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3157         {
3158                 .name           = "mpu",
3159                 .pa_start       = 0x48074000,
3160                 .pa_end         = 0x480740ff,
3161                 .flags          = ADDR_TYPE_RT
3162         },
3163         { }
3164 };
3165
3166 /* l4_core -> mcbsp1 */
3167 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3168         .master         = &omap3xxx_l4_core_hwmod,
3169         .slave          = &omap3xxx_mcbsp1_hwmod,
3170         .clk            = "mcbsp1_ick",
3171         .addr           = omap3xxx_mcbsp1_addrs,
3172         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3173 };
3174
3175 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3176         {
3177                 .name           = "mpu",
3178                 .pa_start       = 0x49022000,
3179                 .pa_end         = 0x490220ff,
3180                 .flags          = ADDR_TYPE_RT
3181         },
3182         { }
3183 };
3184
3185 /* l4_per -> mcbsp2 */
3186 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3187         .master         = &omap3xxx_l4_per_hwmod,
3188         .slave          = &omap3xxx_mcbsp2_hwmod,
3189         .clk            = "mcbsp2_ick",
3190         .addr           = omap3xxx_mcbsp2_addrs,
3191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3192 };
3193
3194 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3195         {
3196                 .name           = "mpu",
3197                 .pa_start       = 0x49024000,
3198                 .pa_end         = 0x490240ff,
3199                 .flags          = ADDR_TYPE_RT
3200         },
3201         { }
3202 };
3203
3204 /* l4_per -> mcbsp3 */
3205 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3206         .master         = &omap3xxx_l4_per_hwmod,
3207         .slave          = &omap3xxx_mcbsp3_hwmod,
3208         .clk            = "mcbsp3_ick",
3209         .addr           = omap3xxx_mcbsp3_addrs,
3210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3211 };
3212
3213 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3214         {
3215                 .name           = "mpu",
3216                 .pa_start       = 0x49026000,
3217                 .pa_end         = 0x490260ff,
3218                 .flags          = ADDR_TYPE_RT
3219         },
3220         { }
3221 };
3222
3223 /* l4_per -> mcbsp4 */
3224 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3225         .master         = &omap3xxx_l4_per_hwmod,
3226         .slave          = &omap3xxx_mcbsp4_hwmod,
3227         .clk            = "mcbsp4_ick",
3228         .addr           = omap3xxx_mcbsp4_addrs,
3229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3230 };
3231
3232 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3233         {
3234                 .name           = "mpu",
3235                 .pa_start       = 0x48096000,
3236                 .pa_end         = 0x480960ff,
3237                 .flags          = ADDR_TYPE_RT
3238         },
3239         { }
3240 };
3241
3242 /* l4_core -> mcbsp5 */
3243 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3244         .master         = &omap3xxx_l4_core_hwmod,
3245         .slave          = &omap3xxx_mcbsp5_hwmod,
3246         .clk            = "mcbsp5_ick",
3247         .addr           = omap3xxx_mcbsp5_addrs,
3248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3249 };
3250
3251 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3252         {
3253                 .name           = "sidetone",
3254                 .pa_start       = 0x49028000,
3255                 .pa_end         = 0x490280ff,
3256                 .flags          = ADDR_TYPE_RT
3257         },
3258         { }
3259 };
3260
3261 /* l4_per -> mcbsp2_sidetone */
3262 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3263         .master         = &omap3xxx_l4_per_hwmod,
3264         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3265         .clk            = "mcbsp2_ick",
3266         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3267         .user           = OCP_USER_MPU,
3268 };
3269
3270 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3271         {
3272                 .name           = "sidetone",
3273                 .pa_start       = 0x4902A000,
3274                 .pa_end         = 0x4902A0ff,
3275                 .flags          = ADDR_TYPE_RT
3276         },
3277         { }
3278 };
3279
3280 /* l4_per -> mcbsp3_sidetone */
3281 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3282         .master         = &omap3xxx_l4_per_hwmod,
3283         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3284         .clk            = "mcbsp3_ick",
3285         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3286         .user           = OCP_USER_MPU,
3287 };
3288
3289 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3290         {
3291                 .pa_start       = 0x48094000,
3292                 .pa_end         = 0x480941ff,
3293                 .flags          = ADDR_TYPE_RT,
3294         },
3295         { }
3296 };
3297
3298 /* l4_core -> mailbox */
3299 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3300         .master         = &omap3xxx_l4_core_hwmod,
3301         .slave          = &omap3xxx_mailbox_hwmod,
3302         .addr           = omap3xxx_mailbox_addrs,
3303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3305
3306 /* l4 core -> mcspi1 interface */
3307 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3308         .master         = &omap3xxx_l4_core_hwmod,
3309         .slave          = &omap34xx_mcspi1,
3310         .clk            = "mcspi1_ick",
3311         .addr           = omap2_mcspi1_addr_space,
3312         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3313 };
3314
3315 /* l4 core -> mcspi2 interface */
3316 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3317         .master         = &omap3xxx_l4_core_hwmod,
3318         .slave          = &omap34xx_mcspi2,
3319         .clk            = "mcspi2_ick",
3320         .addr           = omap2_mcspi2_addr_space,
3321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3322 };
3323
3324 /* l4 core -> mcspi3 interface */
3325 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3326         .master         = &omap3xxx_l4_core_hwmod,
3327         .slave          = &omap34xx_mcspi3,
3328         .clk            = "mcspi3_ick",
3329         .addr           = omap2430_mcspi3_addr_space,
3330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3331 };
3332
3333 /* l4 core -> mcspi4 interface */
3334 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3335         {
3336                 .pa_start       = 0x480ba000,
3337                 .pa_end         = 0x480ba0ff,
3338                 .flags          = ADDR_TYPE_RT,
3339         },
3340         { }
3341 };
3342
3343 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3344         .master         = &omap3xxx_l4_core_hwmod,
3345         .slave          = &omap34xx_mcspi4,
3346         .clk            = "mcspi4_ick",
3347         .addr           = omap34xx_mcspi4_addr_space,
3348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3349 };
3350
3351 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3352         .master         = &omap3xxx_usb_host_hs_hwmod,
3353         .slave          = &omap3xxx_l3_main_hwmod,
3354         .clk            = "core_l3_ick",
3355         .user           = OCP_USER_MPU,
3356 };
3357
3358 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3359         {
3360                 .name           = "uhh",
3361                 .pa_start       = 0x48064000,
3362                 .pa_end         = 0x480643ff,
3363                 .flags          = ADDR_TYPE_RT
3364         },
3365         {
3366                 .name           = "ohci",
3367                 .pa_start       = 0x48064400,
3368                 .pa_end         = 0x480647ff,
3369         },
3370         {
3371                 .name           = "ehci",
3372                 .pa_start       = 0x48064800,
3373                 .pa_end         = 0x48064cff,
3374         },
3375         {}
3376 };
3377
3378 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3379         .master         = &omap3xxx_l4_core_hwmod,
3380         .slave          = &omap3xxx_usb_host_hs_hwmod,
3381         .clk            = "usbhost_ick",
3382         .addr           = omap3xxx_usb_host_hs_addrs,
3383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3384 };
3385
3386 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3387         {
3388                 .name           = "tll",
3389                 .pa_start       = 0x48062000,
3390                 .pa_end         = 0x48062fff,
3391                 .flags          = ADDR_TYPE_RT
3392         },
3393         {}
3394 };
3395
3396 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3397         .master         = &omap3xxx_l4_core_hwmod,
3398         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3399         .clk            = "usbtll_ick",
3400         .addr           = omap3xxx_usb_tll_hs_addrs,
3401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3402 };
3403
3404 /* l4_core -> hdq1w interface */
3405 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3406         .master         = &omap3xxx_l4_core_hwmod,
3407         .slave          = &omap3xxx_hdq1w_hwmod,
3408         .clk            = "hdq_ick",
3409         .addr           = omap2_hdq1w_addr_space,
3410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3411         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3412 };
3413
3414 /* l4_wkup -> 32ksync_counter */
3415 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3416         {
3417                 .pa_start       = 0x48320000,
3418                 .pa_end         = 0x4832001f,
3419                 .flags          = ADDR_TYPE_RT
3420         },
3421         { }
3422 };
3423
3424 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3425         {
3426                 .pa_start       = 0x6e000000,
3427                 .pa_end         = 0x6e000fff,
3428                 .flags          = ADDR_TYPE_RT
3429         },
3430         { }
3431 };
3432
3433 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3434         .master         = &omap3xxx_l4_wkup_hwmod,
3435         .slave          = &omap3xxx_counter_32k_hwmod,
3436         .clk            = "omap_32ksync_ick",
3437         .addr           = omap3xxx_counter_32k_addrs,
3438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3439 };
3440
3441 /* am35xx has Davinci MDIO & EMAC */
3442 static struct omap_hwmod_class am35xx_mdio_class = {
3443         .name = "davinci_mdio",
3444 };
3445
3446 static struct omap_hwmod am35xx_mdio_hwmod = {
3447         .name           = "davinci_mdio",
3448         .class          = &am35xx_mdio_class,
3449         .flags          = HWMOD_NO_IDLEST,
3450 };
3451
3452 /*
3453  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3454  * but this will probably require some additional hwmod core support,
3455  * so is left as a future to-do item.
3456  */
3457 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3458         .master         = &am35xx_mdio_hwmod,
3459         .slave          = &omap3xxx_l3_main_hwmod,
3460         .clk            = "emac_fck",
3461         .user           = OCP_USER_MPU,
3462 };
3463
3464 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3465         {
3466                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3467                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3468                 .flags          = ADDR_TYPE_RT,
3469         },
3470         { }
3471 };
3472
3473 /* l4_core -> davinci mdio  */
3474 /*
3475  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3476  * but this will probably require some additional hwmod core support,
3477  * so is left as a future to-do item.
3478  */
3479 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3480         .master         = &omap3xxx_l4_core_hwmod,
3481         .slave          = &am35xx_mdio_hwmod,
3482         .clk            = "emac_fck",
3483         .addr           = am35xx_mdio_addrs,
3484         .user           = OCP_USER_MPU,
3485 };
3486
3487 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3488         { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
3489         { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
3490         { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
3491         { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3492         { .irq = -1 },
3493 };
3494
3495 static struct omap_hwmod_class am35xx_emac_class = {
3496         .name = "davinci_emac",
3497 };
3498
3499 static struct omap_hwmod am35xx_emac_hwmod = {
3500         .name           = "davinci_emac",
3501         .mpu_irqs       = am35xx_emac_mpu_irqs,
3502         .class          = &am35xx_emac_class,
3503         .flags          = HWMOD_NO_IDLEST,
3504 };
3505
3506 /* l3_core -> davinci emac interface */
3507 /*
3508  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3509  * but this will probably require some additional hwmod core support,
3510  * so is left as a future to-do item.
3511  */
3512 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3513         .master         = &am35xx_emac_hwmod,
3514         .slave          = &omap3xxx_l3_main_hwmod,
3515         .clk            = "emac_ick",
3516         .user           = OCP_USER_MPU,
3517 };
3518
3519 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3520         {
3521                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3522                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3523                 .flags          = ADDR_TYPE_RT,
3524         },
3525         { }
3526 };
3527
3528 /* l4_core -> davinci emac  */
3529 /*
3530  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3531  * but this will probably require some additional hwmod core support,
3532  * so is left as a future to-do item.
3533  */
3534 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3535         .master         = &omap3xxx_l4_core_hwmod,
3536         .slave          = &am35xx_emac_hwmod,
3537         .clk            = "emac_ick",
3538         .addr           = am35xx_emac_addrs,
3539         .user           = OCP_USER_MPU,
3540 };
3541
3542 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3543         .master         = &omap3xxx_l3_main_hwmod,
3544         .slave          = &omap3xxx_gpmc_hwmod,
3545         .clk            = "core_l3_ick",
3546         .addr           = omap3xxx_gpmc_addrs,
3547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3548 };
3549
3550 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3551         &omap3xxx_l3_main__l4_core,
3552         &omap3xxx_l3_main__l4_per,
3553         &omap3xxx_mpu__l3_main,
3554         &omap3xxx_l3_main__l4_debugss,
3555         &omap3xxx_l4_core__l4_wkup,
3556         &omap3xxx_l4_core__mmc3,
3557         &omap3_l4_core__uart1,
3558         &omap3_l4_core__uart2,
3559         &omap3_l4_per__uart3,
3560         &omap3_l4_core__i2c1,
3561         &omap3_l4_core__i2c2,
3562         &omap3_l4_core__i2c3,
3563         &omap3xxx_l4_wkup__l4_sec,
3564         &omap3xxx_l4_wkup__timer1,
3565         &omap3xxx_l4_per__timer2,
3566         &omap3xxx_l4_per__timer3,
3567         &omap3xxx_l4_per__timer4,
3568         &omap3xxx_l4_per__timer5,
3569         &omap3xxx_l4_per__timer6,
3570         &omap3xxx_l4_per__timer7,
3571         &omap3xxx_l4_per__timer8,
3572         &omap3xxx_l4_per__timer9,
3573         &omap3xxx_l4_core__timer10,
3574         &omap3xxx_l4_core__timer11,
3575         &omap3xxx_l4_wkup__wd_timer2,
3576         &omap3xxx_l4_wkup__gpio1,
3577         &omap3xxx_l4_per__gpio2,
3578         &omap3xxx_l4_per__gpio3,
3579         &omap3xxx_l4_per__gpio4,
3580         &omap3xxx_l4_per__gpio5,
3581         &omap3xxx_l4_per__gpio6,
3582         &omap3xxx_dma_system__l3,
3583         &omap3xxx_l4_core__dma_system,
3584         &omap3xxx_l4_core__mcbsp1,
3585         &omap3xxx_l4_per__mcbsp2,
3586         &omap3xxx_l4_per__mcbsp3,
3587         &omap3xxx_l4_per__mcbsp4,
3588         &omap3xxx_l4_core__mcbsp5,
3589         &omap3xxx_l4_per__mcbsp2_sidetone,
3590         &omap3xxx_l4_per__mcbsp3_sidetone,
3591         &omap34xx_l4_core__mcspi1,
3592         &omap34xx_l4_core__mcspi2,
3593         &omap34xx_l4_core__mcspi3,
3594         &omap34xx_l4_core__mcspi4,
3595         &omap3xxx_l4_wkup__counter_32k,
3596         &omap3xxx_l3_main__gpmc,
3597         NULL,
3598 };
3599
3600 /* GP-only hwmod links */
3601 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3602         &omap3xxx_l4_sec__timer12,
3603         NULL
3604 };
3605
3606 /* 3430ES1-only hwmod links */
3607 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3608         &omap3430es1_dss__l3,
3609         &omap3430es1_l4_core__dss,
3610         NULL
3611 };
3612
3613 /* 3430ES2+-only hwmod links */
3614 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3615         &omap3xxx_dss__l3,
3616         &omap3xxx_l4_core__dss,
3617         &omap3xxx_usbhsotg__l3,
3618         &omap3xxx_l4_core__usbhsotg,
3619         &omap3xxx_usb_host_hs__l3_main_2,
3620         &omap3xxx_l4_core__usb_host_hs,
3621         &omap3xxx_l4_core__usb_tll_hs,
3622         NULL
3623 };
3624
3625 /* <= 3430ES3-only hwmod links */
3626 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3627         &omap3xxx_l4_core__pre_es3_mmc1,
3628         &omap3xxx_l4_core__pre_es3_mmc2,
3629         NULL
3630 };
3631
3632 /* 3430ES3+-only hwmod links */
3633 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3634         &omap3xxx_l4_core__es3plus_mmc1,
3635         &omap3xxx_l4_core__es3plus_mmc2,
3636         NULL
3637 };
3638
3639 /* 34xx-only hwmod links (all ES revisions) */
3640 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3641         &omap3xxx_l3__iva,
3642         &omap34xx_l4_core__sr1,
3643         &omap34xx_l4_core__sr2,
3644         &omap3xxx_l4_core__mailbox,
3645         &omap3xxx_l4_core__hdq1w,
3646         &omap3xxx_sad2d__l3,
3647         &omap3xxx_l4_core__mmu_isp,
3648 #ifdef CONFIG_OMAP_IOMMU_IVA2
3649         &omap3xxx_l3_main__mmu_iva,
3650 #endif
3651         NULL
3652 };
3653
3654 /* 36xx-only hwmod links (all ES revisions) */
3655 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3656         &omap3xxx_l3__iva,
3657         &omap36xx_l4_per__uart4,
3658         &omap3xxx_dss__l3,
3659         &omap3xxx_l4_core__dss,
3660         &omap36xx_l4_core__sr1,
3661         &omap36xx_l4_core__sr2,
3662         &omap3xxx_usbhsotg__l3,
3663         &omap3xxx_l4_core__usbhsotg,
3664         &omap3xxx_l4_core__mailbox,
3665         &omap3xxx_usb_host_hs__l3_main_2,
3666         &omap3xxx_l4_core__usb_host_hs,
3667         &omap3xxx_l4_core__usb_tll_hs,
3668         &omap3xxx_l4_core__es3plus_mmc1,
3669         &omap3xxx_l4_core__es3plus_mmc2,
3670         &omap3xxx_l4_core__hdq1w,
3671         &omap3xxx_sad2d__l3,
3672         &omap3xxx_l4_core__mmu_isp,
3673 #ifdef CONFIG_OMAP_IOMMU_IVA2
3674         &omap3xxx_l3_main__mmu_iva,
3675 #endif
3676         NULL
3677 };
3678
3679 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3680         &omap3xxx_dss__l3,
3681         &omap3xxx_l4_core__dss,
3682         &am35xx_usbhsotg__l3,
3683         &am35xx_l4_core__usbhsotg,
3684         &am35xx_l4_core__uart4,
3685         &omap3xxx_usb_host_hs__l3_main_2,
3686         &omap3xxx_l4_core__usb_host_hs,
3687         &omap3xxx_l4_core__usb_tll_hs,
3688         &omap3xxx_l4_core__es3plus_mmc1,
3689         &omap3xxx_l4_core__es3plus_mmc2,
3690         &omap3xxx_l4_core__hdq1w,
3691         &am35xx_mdio__l3,
3692         &am35xx_l4_core__mdio,
3693         &am35xx_emac__l3,
3694         &am35xx_l4_core__emac,
3695         NULL
3696 };
3697
3698 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3699         &omap3xxx_l4_core__dss_dispc,
3700         &omap3xxx_l4_core__dss_dsi1,
3701         &omap3xxx_l4_core__dss_rfbi,
3702         &omap3xxx_l4_core__dss_venc,
3703         NULL
3704 };
3705
3706 int __init omap3xxx_hwmod_init(void)
3707 {
3708         int r;
3709         struct omap_hwmod_ocp_if **h = NULL;
3710         unsigned int rev;
3711
3712         omap_hwmod_init();
3713
3714         /* Register hwmod links common to all OMAP3 */
3715         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3716         if (r < 0)
3717                 return r;
3718
3719         /* Register GP-only hwmod links. */
3720         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3721                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3722                 if (r < 0)
3723                         return r;
3724         }
3725
3726         rev = omap_rev();
3727
3728         /*
3729          * Register hwmod links common to individual OMAP3 families, all
3730          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3731          * All possible revisions should be included in this conditional.
3732          */
3733         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3734             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3735             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3736                 h = omap34xx_hwmod_ocp_ifs;
3737         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3738                 h = am35xx_hwmod_ocp_ifs;
3739         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3740                    rev == OMAP3630_REV_ES1_2) {
3741                 h = omap36xx_hwmod_ocp_ifs;
3742         } else {
3743                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3744                 return -EINVAL;
3745         }
3746
3747         r = omap_hwmod_register_links(h);
3748         if (r < 0)
3749                 return r;
3750
3751         /*
3752          * Register hwmod links specific to certain ES levels of a
3753          * particular family of silicon (e.g., 34xx ES1.0)
3754          */
3755         h = NULL;
3756         if (rev == OMAP3430_REV_ES1_0) {
3757                 h = omap3430es1_hwmod_ocp_ifs;
3758         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3759                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3760                    rev == OMAP3430_REV_ES3_1_2) {
3761                 h = omap3430es2plus_hwmod_ocp_ifs;
3762         }
3763
3764         if (h) {
3765                 r = omap_hwmod_register_links(h);
3766                 if (r < 0)
3767                         return r;
3768         }
3769
3770         h = NULL;
3771         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3772             rev == OMAP3430_REV_ES2_1) {
3773                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3774         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3775                    rev == OMAP3430_REV_ES3_1_2) {
3776                 h = omap3430_es3plus_hwmod_ocp_ifs;
3777         }
3778
3779         if (h)
3780                 r = omap_hwmod_register_links(h);
3781         if (r < 0)
3782                 return r;
3783
3784         /*
3785          * DSS code presumes that dss_core hwmod is handled first,
3786          * _before_ any other DSS related hwmods so register common
3787          * DSS hwmod links last to ensure that dss_core is already
3788          * registered.  Otherwise some change things may happen, for
3789          * ex. if dispc is handled before dss_core and DSS is enabled
3790          * in bootloader DISPC will be reset with outputs enabled
3791          * which sometimes leads to unrecoverable L3 error.  XXX The
3792          * long-term fix to this is to ensure hwmods are set up in
3793          * dependency order in the hwmod core code.
3794          */
3795         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3796
3797         return r;
3798 }