drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  20  * along with this program; if not, write to the Free Software
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77 /* FIXME: need to abstract out TX command (once we know what it looks like) */
  78 #include "dvm/commands.h"
  79
  80 #define SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie)       \
  81         (((1<<trans->cfg->base_params->num_of_queues) - 1) &\
  82         (~(1<<(trans_pcie)->cmd_queue)))
  83
  84 static int iwl_trans_rx_alloc(struct iwl_trans *trans)
  85 {
  86         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  87         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
  88         struct device *dev = trans->dev;
  89
  90         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
  91
  92         spin_lock_init(&rxq->lock);
  93
  94         if (WARN_ON(rxq->bd || rxq->rb_stts))
  95                 return -EINVAL;
  96
  97         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
  98         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
  99                                       &rxq->bd_dma, GFP_KERNEL);
 100         if (!rxq->bd)
 101                 goto err_bd;
 102
 103         /*Allocate the driver's pointer to receive buffer status */
 104         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 105                                            &rxq->rb_stts_dma, GFP_KERNEL);
 106         if (!rxq->rb_stts)
 107                 goto err_rb_stts;
 108
 109         return 0;
 110
 111 err_rb_stts:
 112         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 113                           rxq->bd, rxq->bd_dma);
 114         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 115         rxq->bd = NULL;
 116 err_bd:
 117         return -ENOMEM;
 118 }
 119
 120 static void iwl_trans_rxq_free_rx_bufs(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 124         int i;
 125
 126         /* Fill the rx_used queue with _all_ of the Rx buffers */
 127         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 128                 /* In the reset function, these buffers may have been allocated
 129                  * to an SKB, so we need to unmap and free potential storage */
 130                 if (rxq->pool[i].page != NULL) {
 131                         dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 132                                        PAGE_SIZE << trans_pcie->rx_page_order,
 133                                        DMA_FROM_DEVICE);
 134                         __free_pages(rxq->pool[i].page,
 135                                      trans_pcie->rx_page_order);
 136                         rxq->pool[i].page = NULL;
 137                 }
 138                 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
 139         }
 140 }
 141
 142 static void iwl_trans_rx_hw_init(struct iwl_trans *trans,
 143                                  struct iwl_rx_queue *rxq)
 144 {
 145         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 146         u32 rb_size;
 147         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 148         u32 rb_timeout = RX_RB_TIMEOUT; /* FIXME: RX_RB_TIMEOUT for all devices? */
 149
 150         if (trans_pcie->rx_buf_size_8k)
 151                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 152         else
 153                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 154
 155         /* Stop Rx DMA */
 156         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 157
 158         /* Reset driver's Rx queue write index */
 159         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 160
 161         /* Tell device where to find RBD circular buffer in DRAM */
 162         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 163                            (u32)(rxq->bd_dma >> 8));
 164
 165         /* Tell device where in DRAM to update its Rx status */
 166         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 167                            rxq->rb_stts_dma >> 4);
 168
 169         /* Enable Rx DMA
 170          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 171          *      the credit mechanism in 5000 HW RX FIFO
 172          * Direct rx interrupts to hosts
 173          * Rx buffer size 4 or 8k
 174          * RB timeout 0x10
 175          * 256 RBDs
 176          */
 177         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 178                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 179                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 180                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 181                            rb_size|
 182                            (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 183                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 184
 185         /* Set interrupt coalescing timer to default (2048 usecs) */
 186         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 187 }
 188
 189 static int iwl_rx_init(struct iwl_trans *trans)
 190 {
 191         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 192         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 193
 194         int i, err;
 195         unsigned long flags;
 196
 197         if (!rxq->bd) {
 198                 err = iwl_trans_rx_alloc(trans);
 199                 if (err)
 200                         return err;
 201         }
 202
 203         spin_lock_irqsave(&rxq->lock, flags);
 204         INIT_LIST_HEAD(&rxq->rx_free);
 205         INIT_LIST_HEAD(&rxq->rx_used);
 206
 207         iwl_trans_rxq_free_rx_bufs(trans);
 208
 209         for (i = 0; i < RX_QUEUE_SIZE; i++)
 210                 rxq->queue[i] = NULL;
 211
 212         /* Set us so that we have processed and used all buffers, but have
 213          * not restocked the Rx queue with fresh buffers */
 214         rxq->read = rxq->write = 0;
 215         rxq->write_actual = 0;
 216         rxq->free_count = 0;
 217         spin_unlock_irqrestore(&rxq->lock, flags);
 218
 219         iwl_rx_replenish(trans);
 220
 221         iwl_trans_rx_hw_init(trans, rxq);
 222
 223         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 224         rxq->need_update = 1;
 225         iwl_rx_queue_update_write_ptr(trans, rxq);
 226         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 227
 228         return 0;
 229 }
 230
 231 static void iwl_trans_pcie_rx_free(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 234         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 235         unsigned long flags;
 236
 237         /*if rxq->bd is NULL, it means that nothing has been allocated,
 238          * exit now */
 239         if (!rxq->bd) {
 240                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 241                 return;
 242         }
 243
 244         spin_lock_irqsave(&rxq->lock, flags);
 245         iwl_trans_rxq_free_rx_bufs(trans);
 246         spin_unlock_irqrestore(&rxq->lock, flags);
 247
 248         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 249                           rxq->bd, rxq->bd_dma);
 250         memset(&rxq->bd_dma, 0, sizeof(rxq->bd_dma));
 251         rxq->bd = NULL;
 252
 253         if (rxq->rb_stts)
 254                 dma_free_coherent(trans->dev,
 255                                   sizeof(struct iwl_rb_status),
 256                                   rxq->rb_stts, rxq->rb_stts_dma);
 257         else
 258                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 259         memset(&rxq->rb_stts_dma, 0, sizeof(rxq->rb_stts_dma));
 260         rxq->rb_stts = NULL;
 261 }
 262
 263 static int iwl_trans_rx_stop(struct iwl_trans *trans)
 264 {
 265
 266         /* stop Rx DMA */
 267         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 268         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 269                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 270 }
 271
 272 static int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
 273                                 struct iwl_dma_ptr *ptr, size_t size)
 274 {
 275         if (WARN_ON(ptr->addr))
 276                 return -EINVAL;
 277
 278         ptr->addr = dma_alloc_coherent(trans->dev, size,
 279                                        &ptr->dma, GFP_KERNEL);
 280         if (!ptr->addr)
 281                 return -ENOMEM;
 282         ptr->size = size;
 283         return 0;
 284 }
 285
 286 static void iwlagn_free_dma_ptr(struct iwl_trans *trans,
 287                                 struct iwl_dma_ptr *ptr)
 288 {
 289         if (unlikely(!ptr->addr))
 290                 return;
 291
 292         dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
 293         memset(ptr, 0, sizeof(*ptr));
 294 }
 295
 296 static void iwl_trans_pcie_queue_stuck_timer(unsigned long data)
 297 {
 298         struct iwl_tx_queue *txq = (void *)data;
 299         struct iwl_queue *q = &txq->q;
 300         struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
 301         struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
 302         u32 scd_sram_addr = trans_pcie->scd_base_addr +
 303                                 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 304         u8 buf[16];
 305         int i;
 306
 307         spin_lock(&txq->lock);
 308         /* check if triggered erroneously */
 309         if (txq->q.read_ptr == txq->q.write_ptr) {
 310                 spin_unlock(&txq->lock);
 311                 return;
 312         }
 313         spin_unlock(&txq->lock);
 314
 315         IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
 316                 jiffies_to_msecs(trans_pcie->wd_timeout));
 317         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 318                 txq->q.read_ptr, txq->q.write_ptr);
 319
 320         iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 321
 322         iwl_print_hex_error(trans, buf, sizeof(buf));
 323
 324         for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
 325                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
 326                         iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
 327
 328         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
 329                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
 330                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
 331                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
 332                 u32 tbl_dw =
 333                         iwl_read_targ_mem(trans,
 334                                           trans_pcie->scd_base_addr +
 335                                           SCD_TRANS_TBL_OFFSET_QUEUE(i));
 336
 337                 if (i & 0x1)
 338                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
 339                 else
 340                         tbl_dw = tbl_dw & 0x0000FFFF;
 341
 342                 IWL_ERR(trans,
 343                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
 344                         i, active ? "" : "in", fifo, tbl_dw,
 345                         iwl_read_prph(trans,
 346                                       SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1),
 347                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
 348         }
 349
 350         for (i = q->read_ptr; i != q->write_ptr;
 351              i = iwl_queue_inc_wrap(i, q->n_bd)) {
 352                 struct iwl_tx_cmd *tx_cmd =
 353                         (struct iwl_tx_cmd *)txq->entries[i].cmd->payload;
 354                 IWL_ERR(trans, "scratch %d = 0x%08x\n", i,
 355                         get_unaligned_le32(&tx_cmd->scratch));
 356         }
 357
 358         iwl_op_mode_nic_error(trans->op_mode);
 359 }
 360
 361 static int iwl_trans_txq_alloc(struct iwl_trans *trans,
 362                                struct iwl_tx_queue *txq, int slots_num,
 363                                u32 txq_id)
 364 {
 365         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 366         size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
 367         int i;
 368
 369         if (WARN_ON(txq->entries || txq->tfds))
 370                 return -EINVAL;
 371
 372         setup_timer(&txq->stuck_timer, iwl_trans_pcie_queue_stuck_timer,
 373                     (unsigned long)txq);
 374         txq->trans_pcie = trans_pcie;
 375
 376         txq->q.n_window = slots_num;
 377
 378         txq->entries = kcalloc(slots_num,
 379                                sizeof(struct iwl_pcie_tx_queue_entry),
 380                                GFP_KERNEL);
 381
 382         if (!txq->entries)
 383                 goto error;
 384
 385         if (txq_id == trans_pcie->cmd_queue)
 386                 for (i = 0; i < slots_num; i++) {
 387                         txq->entries[i].cmd =
 388                                 kmalloc(sizeof(struct iwl_device_cmd),
 389                                         GFP_KERNEL);
 390                         if (!txq->entries[i].cmd)
 391                                 goto error;
 392                 }
 393
 394         /* Circular buffer of transmit frame descriptors (TFDs),
 395          * shared with device */
 396         txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
 397                                        &txq->q.dma_addr, GFP_KERNEL);
 398         if (!txq->tfds) {
 399                 IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
 400                 goto error;
 401         }
 402         txq->q.id = txq_id;
 403
 404         return 0;
 405 error:
 406         if (txq->entries && txq_id == trans_pcie->cmd_queue)
 407                 for (i = 0; i < slots_num; i++)
 408                         kfree(txq->entries[i].cmd);
 409         kfree(txq->entries);
 410         txq->entries = NULL;
 411
 412         return -ENOMEM;
 413
 414 }
 415
 416 static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
 417                               int slots_num, u32 txq_id)
 418 {
 419         int ret;
 420
 421         txq->need_update = 0;
 422
 423         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
 424          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
 425         BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
 426
 427         /* Initialize queue's high/low-water marks, and head/tail indexes */
 428         ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
 429                         txq_id);
 430         if (ret)
 431                 return ret;
 432
 433         spin_lock_init(&txq->lock);
 434
 435         /*
 436          * Tell nic where to find circular buffer of Tx Frame Descriptors for
 437          * given Tx queue, and enable the DMA channel used for that queue.
 438          * Circular buffer (TFD queue in DRAM) physical base address */
 439         iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
 440                              txq->q.dma_addr >> 8);
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * iwl_tx_queue_unmap -  Unmap any remaining DMA mappings and free skb's
 447  */
 448 void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
 449 {
 450         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 451         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 452         struct iwl_queue *q = &txq->q;
 453         enum dma_data_direction dma_dir;
 454
 455         if (!q->n_bd)
 456                 return;
 457
 458         /* In the command queue, all the TBs are mapped as BIDI
 459          * so unmap them as such.
 460          */
 461         if (txq_id == trans_pcie->cmd_queue)
 462                 dma_dir = DMA_BIDIRECTIONAL;
 463         else
 464                 dma_dir = DMA_TO_DEVICE;
 465
 466         spin_lock_bh(&txq->lock);
 467         while (q->write_ptr != q->read_ptr) {
 468                 iwl_txq_free_tfd(trans, txq, dma_dir);
 469                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
 470         }
 471         spin_unlock_bh(&txq->lock);
 472 }
 473
 474 /**
 475  * iwl_tx_queue_free - Deallocate DMA queue.
 476  * @txq: Transmit queue to deallocate.
 477  *
 478  * Empty queue by removing and destroying all BD's.
 479  * Free all buffers.
 480  * 0-fill, but do not free "txq" descriptor structure.
 481  */
 482 static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
 483 {
 484         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 485         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
 486         struct device *dev = trans->dev;
 487         int i;
 488
 489         if (WARN_ON(!txq))
 490                 return;
 491
 492         iwl_tx_queue_unmap(trans, txq_id);
 493
 494         /* De-alloc array of command/tx buffers */
 495         if (txq_id == trans_pcie->cmd_queue)
 496                 for (i = 0; i < txq->q.n_window; i++) {
 497                         kfree(txq->entries[i].cmd);
 498                         kfree(txq->entries[i].copy_cmd);
 499                         kfree(txq->entries[i].free_buf);
 500                 }
 501
 502         /* De-alloc circular buffer of TFDs */
 503         if (txq->q.n_bd) {
 504                 dma_free_coherent(dev, sizeof(struct iwl_tfd) *
 505                                   txq->q.n_bd, txq->tfds, txq->q.dma_addr);
 506                 memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
 507         }
 508
 509         kfree(txq->entries);
 510         txq->entries = NULL;
 511
 512         del_timer_sync(&txq->stuck_timer);
 513
 514         /* 0-fill queue descriptor structure */
 515         memset(txq, 0, sizeof(*txq));
 516 }
 517
 518 /**
 519  * iwl_trans_tx_free - Free TXQ Context
 520  *
 521  * Destroy all TX DMA queues and structures
 522  */
 523 static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
 524 {
 525         int txq_id;
 526         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 527
 528         /* Tx queues */
 529         if (trans_pcie->txq) {
 530                 for (txq_id = 0;
 531                      txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
 532                         iwl_tx_queue_free(trans, txq_id);
 533         }
 534
 535         kfree(trans_pcie->txq);
 536         trans_pcie->txq = NULL;
 537
 538         iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
 539
 540         iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
 541 }
 542
 543 /**
 544  * iwl_trans_tx_alloc - allocate TX context
 545  * Allocate all Tx DMA structures and initialize them
 546  *
 547  * @param priv
 548  * @return error code
 549  */
 550 static int iwl_trans_tx_alloc(struct iwl_trans *trans)
 551 {
 552         int ret;
 553         int txq_id, slots_num;
 554         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 555
 556         u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
 557                         sizeof(struct iwlagn_scd_bc_tbl);
 558
 559         /*It is not allowed to alloc twice, so warn when this happens.
 560          * We cannot rely on the previous allocation, so free and fail */
 561         if (WARN_ON(trans_pcie->txq)) {
 562                 ret = -EINVAL;
 563                 goto error;
 564         }
 565
 566         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
 567                                    scd_bc_tbls_size);
 568         if (ret) {
 569                 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
 570                 goto error;
 571         }
 572
 573         /* Alloc keep-warm buffer */
 574         ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
 575         if (ret) {
 576                 IWL_ERR(trans, "Keep Warm allocation failed\n");
 577                 goto error;
 578         }
 579
 580         trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
 581                                   sizeof(struct iwl_tx_queue), GFP_KERNEL);
 582         if (!trans_pcie->txq) {
 583                 IWL_ERR(trans, "Not enough memory for txq\n");
 584                 ret = ENOMEM;
 585                 goto error;
 586         }
 587
 588         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 589         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 590              txq_id++) {
 591                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 592                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 593                 ret = iwl_trans_txq_alloc(trans, &trans_pcie->txq[txq_id],
 594                                           slots_num, txq_id);
 595                 if (ret) {
 596                         IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
 597                         goto error;
 598                 }
 599         }
 600
 601         return 0;
 602
 603 error:
 604         iwl_trans_pcie_tx_free(trans);
 605
 606         return ret;
 607 }
 608 static int iwl_tx_init(struct iwl_trans *trans)
 609 {
 610         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 611         int ret;
 612         int txq_id, slots_num;
 613         unsigned long flags;
 614         bool alloc = false;
 615
 616         if (!trans_pcie->txq) {
 617                 ret = iwl_trans_tx_alloc(trans);
 618                 if (ret)
 619                         goto error;
 620                 alloc = true;
 621         }
 622
 623         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 624
 625         /* Turn off all Tx DMA fifos */
 626         iwl_write_prph(trans, SCD_TXFACT, 0);
 627
 628         /* Tell NIC where to find the "keep warm" buffer */
 629         iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
 630                            trans_pcie->kw.dma >> 4);
 631
 632         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 633
 634         /* Alloc and init all Tx queues, including the command queue (#4/#9) */
 635         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
 636              txq_id++) {
 637                 slots_num = (txq_id == trans_pcie->cmd_queue) ?
 638                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 639                 ret = iwl_trans_txq_init(trans, &trans_pcie->txq[txq_id],
 640                                          slots_num, txq_id);
 641                 if (ret) {
 642                         IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
 643                         goto error;
 644                 }
 645         }
 646
 647         return 0;
 648 error:
 649         /*Upon error, free only if we allocated something */
 650         if (alloc)
 651                 iwl_trans_pcie_tx_free(trans);
 652         return ret;
 653 }
 654
 655 static void iwl_set_pwr_vmain(struct iwl_trans *trans)
 656 {
 657 /*
 658  * (for documentation purposes)
 659  * to set power to V_AUX, do:
 660
 661                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
 662                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 663                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 664                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 665  */
 666
 667         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 668                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 669                                ~APMG_PS_CTRL_MSK_PWR_SRC);
 670 }
 671
 672 /* PCI registers */
 673 #define PCI_CFG_RETRY_TIMEOUT   0x041
 674 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
 675 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
 676
 677 static u16 iwl_pciexp_link_ctrl(struct iwl_trans *trans)
 678 {
 679         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 680         u16 pci_lnk_ctl;
 681
 682         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL,
 683                                   &pci_lnk_ctl);
 684         return pci_lnk_ctl;
 685 }
 686
 687 static void iwl_apm_config(struct iwl_trans *trans)
 688 {
 689         /*
 690          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 691          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 692          * If so (likely), disable L0S, so device moves directly L0->L1;
 693          *    costs negligible amount of power savings.
 694          * If not (unlikely), enable L0S, so there is at least some
 695          *    power savings, even without L1.
 696          */
 697         u16 lctl = iwl_pciexp_link_ctrl(trans);
 698
 699         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 700                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 701                 /* L1-ASPM enabled; disable(!) L0S */
 702                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 703                 dev_printk(KERN_INFO, trans->dev,
 704                            "L1 Enabled; Disabling L0S\n");
 705         } else {
 706                 /* L1-ASPM disabled; enable(!) L0S */
 707                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 708                 dev_printk(KERN_INFO, trans->dev,
 709                            "L1 Disabled; Enabling L0S\n");
 710         }
 711         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 712 }
 713
 714 /*
 715  * Start up NIC's basic functionality after it has been reset
 716  * (e.g. after platform boot, or shutdown via iwl_apm_stop())
 717  * NOTE:  This does not load uCode nor start the embedded processor
 718  */
 719 static int iwl_apm_init(struct iwl_trans *trans)
 720 {
 721         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 722         int ret = 0;
 723         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 724
 725         /*
 726          * Use "set_bit" below rather than "write", to preserve any hardware
 727          * bits already set by default after reset.
 728          */
 729
 730         /* Disable L0S exit timer (platform NMI Work/Around) */
 731         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 732                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 733
 734         /*
 735          * Disable L0s without affecting L1;
 736          *  don't wait for ICH L0s (ICH bug W/A)
 737          */
 738         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 739                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 740
 741         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 742         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 743
 744         /*
 745          * Enable HAP INTA (interrupt from management bus) to
 746          * wake device's PCI Express link L1a -> L0s
 747          */
 748         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 749                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 750
 751         iwl_apm_config(trans);
 752
 753         /* Configure analog phase-lock-loop before activating to D0A */
 754         if (trans->cfg->base_params->pll_cfg_val)
 755                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 756                             trans->cfg->base_params->pll_cfg_val);
 757
 758         /*
 759          * Set "initialization complete" bit to move adapter from
 760          * D0U* --> D0A* (powered-up active) state.
 761          */
 762         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 763
 764         /*
 765          * Wait for clock stabilization; once stabilized, access to
 766          * device-internal resources is supported, e.g. iwl_write_prph()
 767          * and accesses to uCode SRAM.
 768          */
 769         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 770                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 771                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 772         if (ret < 0) {
 773                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 774                 goto out;
 775         }
 776
 777         /*
 778          * Enable DMA clock and wait for it to stabilize.
 779          *
 780          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 781          * do not disable clocks.  This preserves any hardware bits already
 782          * set by default in "CLK_CTRL_REG" after reset.
 783          */
 784         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 785         udelay(20);
 786
 787         /* Disable L1-Active */
 788         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 789                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 790
 791         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 792
 793 out:
 794         return ret;
 795 }
 796
 797 static int iwl_apm_stop_master(struct iwl_trans *trans)
 798 {
 799         int ret = 0;
 800
 801         /* stop device's busmaster DMA activity */
 802         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 803
 804         ret = iwl_poll_bit(trans, CSR_RESET,
 805                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 806                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 807         if (ret)
 808                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 809
 810         IWL_DEBUG_INFO(trans, "stop master\n");
 811
 812         return ret;
 813 }
 814
 815 static void iwl_apm_stop(struct iwl_trans *trans)
 816 {
 817         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 818         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 819
 820         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 821
 822         /* Stop device's DMA activity */
 823         iwl_apm_stop_master(trans);
 824
 825         /* Reset the entire device */
 826         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 827
 828         udelay(10);
 829
 830         /*
 831          * Clear "initialization complete" bit to move adapter from
 832          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 833          */
 834         iwl_clear_bit(trans, CSR_GP_CNTRL,
 835                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 836 }
 837
 838 static int iwl_nic_init(struct iwl_trans *trans)
 839 {
 840         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 841         unsigned long flags;
 842
 843         /* nic_init */
 844         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 845         iwl_apm_init(trans);
 846
 847         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 848         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 849
 850         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 851
 852         iwl_set_pwr_vmain(trans);
 853
 854         iwl_op_mode_nic_config(trans->op_mode);
 855
 856         /* Allocate the RX queue, or reset if it is already allocated */
 857         iwl_rx_init(trans);
 858
 859         /* Allocate or reset and init all Tx and Command queues */
 860         if (iwl_tx_init(trans))
 861                 return -ENOMEM;
 862
 863         if (trans->cfg->base_params->shadow_reg_enable) {
 864                 /* enable shadow regs in HW */
 865                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 866                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 867         }
 868
 869         return 0;
 870 }
 871
 872 #define HW_READY_TIMEOUT (50)
 873
 874 /* Note: returns poll_bit return value, which is >= 0 if success */
 875 static int iwl_set_hw_ready(struct iwl_trans *trans)
 876 {
 877         int ret;
 878
 879         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 880                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 881
 882         /* See if we got it */
 883         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 884                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 885                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 886                            HW_READY_TIMEOUT);
 887
 888         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 889         return ret;
 890 }
 891
 892 /* Note: returns standard 0/-ERROR code */
 893 static int iwl_prepare_card_hw(struct iwl_trans *trans)
 894 {
 895         int ret;
 896         int t = 0;
 897
 898         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 899
 900         ret = iwl_set_hw_ready(trans);
 901         /* If the card is ready, exit 0 */
 902         if (ret >= 0)
 903                 return 0;
 904
 905         /* If HW is not ready, prepare the conditions to check again */
 906         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 907                     CSR_HW_IF_CONFIG_REG_PREPARE);
 908
 909         do {
 910                 ret = iwl_set_hw_ready(trans);
 911                 if (ret >= 0)
 912                         return 0;
 913
 914                 usleep_range(200, 1000);
 915                 t += 200;
 916         } while (t < 150000);
 917
 918         return ret;
 919 }
 920
 921 /*
 922  * ucode
 923  */
 924 static int iwl_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 925                                    dma_addr_t phy_addr, u32 byte_cnt)
 926 {
 927         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 928         int ret;
 929
 930         trans_pcie->ucode_write_complete = false;
 931
 932         iwl_write_direct32(trans,
 933                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 934                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 935
 936         iwl_write_direct32(trans,
 937                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 938                            dst_addr);
 939
 940         iwl_write_direct32(trans,
 941                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 942                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 943
 944         iwl_write_direct32(trans,
 945                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 946                            (iwl_get_dma_hi_addr(phy_addr)
 947                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 948
 949         iwl_write_direct32(trans,
 950                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 951                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 952                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 953                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 954
 955         iwl_write_direct32(trans,
 956                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 957                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 958                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 959                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 960
 961         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 962                                  trans_pcie->ucode_write_complete, 5 * HZ);
 963         if (!ret) {
 964                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 965                 return -ETIMEDOUT;
 966         }
 967
 968         return 0;
 969 }
 970
 971 static int iwl_load_section(struct iwl_trans *trans, u8 section_num,
 972                             const struct fw_desc *section)
 973 {
 974         u8 *v_addr;
 975         dma_addr_t p_addr;
 976         u32 offset;
 977         int ret = 0;
 978
 979         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 980                      section_num);
 981
 982         v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
 983         if (!v_addr)
 984                 return -ENOMEM;
 985
 986         for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
 987                 u32 copy_size;
 988
 989                 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
 990
 991                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 992                 ret = iwl_load_firmware_chunk(trans, section->offset + offset,
 993                                               p_addr, copy_size);
 994                 if (ret) {
 995                         IWL_ERR(trans,
 996                                 "Could not load the [%d] uCode section\n",
 997                                 section_num);
 998                         break;
 999                 }
1000         }
1001
1002         dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
1003         return ret;
1004 }
1005
1006 static int iwl_load_given_ucode(struct iwl_trans *trans,
1007                                 const struct fw_img *image)
1008 {
1009         int i, ret = 0;
1010
1011         for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
1012                 if (!image->sec[i].data)
1013                         break;
1014
1015                 ret = iwl_load_section(trans, i, &image->sec[i]);
1016                 if (ret)
1017                         return ret;
1018         }
1019
1020         /* Remove all resets to allow NIC to operate */
1021         iwl_write32(trans, CSR_RESET, 0);
1022
1023         return 0;
1024 }
1025
1026 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1027                                    const struct fw_img *fw)
1028 {
1029         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1030         int ret;
1031         bool hw_rfkill;
1032
1033         /* This may fail if AMT took ownership of the device */
1034         if (iwl_prepare_card_hw(trans)) {
1035                 IWL_WARN(trans, "Exit HW not ready\n");
1036                 return -EIO;
1037         }
1038
1039         clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
1040
1041         iwl_enable_rfkill_int(trans);
1042
1043         /* If platform's RF_KILL switch is NOT set to KILL */
1044         hw_rfkill = iwl_is_rfkill_set(trans);
1045         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1046         if (hw_rfkill)
1047                 return -ERFKILL;
1048
1049         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1050
1051         ret = iwl_nic_init(trans);
1052         if (ret) {
1053                 IWL_ERR(trans, "Unable to init nic\n");
1054                 return ret;
1055         }
1056
1057         /* make sure rfkill handshake bits are cleared */
1058         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1059         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1060                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1061
1062         /* clear (again), then enable host interrupts */
1063         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1064         iwl_enable_interrupts(trans);
1065
1066         /* really make sure rfkill handshake bits are cleared */
1067         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1068         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1069
1070         /* Load the given image to the HW */
1071         return iwl_load_given_ucode(trans, fw);
1072 }
1073
1074 /*
1075  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1076  */
1077 static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
1078 {
1079         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1080                 IWL_TRANS_GET_PCIE_TRANS(trans);
1081
1082         iwl_write_prph(trans, SCD_TXFACT, mask);
1083 }
1084
1085 static void iwl_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
1086 {
1087         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1088         u32 a;
1089         int chan;
1090         u32 reg_val;
1091
1092         /* make sure all queue are not stopped/used */
1093         memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
1094         memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
1095
1096         trans_pcie->scd_base_addr =
1097                 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
1098
1099         WARN_ON(scd_base_addr != 0 &&
1100                 scd_base_addr != trans_pcie->scd_base_addr);
1101
1102         a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
1103         /* reset conext data memory */
1104         for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
1105                 a += 4)
1106                 iwl_write_targ_mem(trans, a, 0);
1107         /* reset tx status memory */
1108         for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
1109                 a += 4)
1110                 iwl_write_targ_mem(trans, a, 0);
1111         for (; a < trans_pcie->scd_base_addr +
1112                SCD_TRANS_TBL_OFFSET_QUEUE(
1113                                 trans->cfg->base_params->num_of_queues);
1114                a += 4)
1115                 iwl_write_targ_mem(trans, a, 0);
1116
1117         iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1118                        trans_pcie->scd_bc_tbls.dma >> 10);
1119
1120         /* The chain extension of the SCD doesn't work well. This feature is
1121          * enabled by default by the HW, so we need to disable it manually.
1122          */
1123         iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
1124
1125         iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
1126                                 trans_pcie->cmd_fifo);
1127
1128         /* Activate all Tx DMA/FIFO channels */
1129         iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
1130
1131         /* Enable DMA channel */
1132         for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
1133                 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
1134                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1135                                    FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
1136
1137         /* Update FH chicken bits */
1138         reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
1139         iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
1140                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
1141
1142         /* Enable L1-Active */
1143         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
1144                             APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1145 }
1146
1147 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1148 {
1149         iwl_reset_ict(trans);
1150         iwl_tx_start(trans, scd_addr);
1151 }
1152
1153 /**
1154  * iwlagn_txq_ctx_stop - Stop all Tx DMA channels
1155  */
1156 static int iwl_trans_tx_stop(struct iwl_trans *trans)
1157 {
1158         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1159         int ch, txq_id, ret;
1160         unsigned long flags;
1161
1162         /* Turn off all Tx DMA fifos */
1163         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1164
1165         iwl_trans_txq_set_sched(trans, 0);
1166
1167         /* Stop each Tx DMA channel, and wait for it to be idle */
1168         for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
1169                 iwl_write_direct32(trans,
1170                                    FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
1171                 ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG,
1172                         FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000);
1173                 if (ret < 0)
1174                         IWL_ERR(trans,
1175                                 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
1176                                 ch,
1177                                 iwl_read_direct32(trans,
1178                                                   FH_TSSR_TX_STATUS_REG));
1179         }
1180         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1181
1182         if (!trans_pcie->txq) {
1183                 IWL_WARN(trans,
1184                          "Stopping tx queues that aren't allocated...\n");
1185                 return 0;
1186         }
1187
1188         /* Unmap DMA from host system and free skb's */
1189         for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1190              txq_id++)
1191                 iwl_tx_queue_unmap(trans, txq_id);
1192
1193         return 0;
1194 }
1195
1196 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
1197 {
1198         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1199         unsigned long flags;
1200
1201         /* tell the device to stop sending interrupts */
1202         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1203         iwl_disable_interrupts(trans);
1204         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1205
1206         /* device going down, Stop using ICT table */
1207         iwl_disable_ict(trans);
1208
1209         /*
1210          * If a HW restart happens during firmware loading,
1211          * then the firmware loading might call this function
1212          * and later it might be called again due to the
1213          * restart. So don't process again if the device is
1214          * already dead.
1215          */
1216         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
1217                 iwl_trans_tx_stop(trans);
1218                 iwl_trans_rx_stop(trans);
1219
1220                 /* Power-down device's busmaster DMA clocks */
1221                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1222                                APMG_CLK_VAL_DMA_CLK_RQT);
1223                 udelay(5);
1224         }
1225
1226         /* Make sure (redundant) we've released our request to stay awake */
1227         iwl_clear_bit(trans, CSR_GP_CNTRL,
1228                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1229
1230         /* Stop the device, and put it in low power state */
1231         iwl_apm_stop(trans);
1232
1233         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
1234          * Clean again the interrupt here
1235          */
1236         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1237         iwl_disable_interrupts(trans);
1238         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1239
1240         iwl_enable_rfkill_int(trans);
1241
1242         /* wait to make sure we flush pending tasklet*/
1243         synchronize_irq(trans_pcie->irq);
1244         tasklet_kill(&trans_pcie->irq_tasklet);
1245
1246         cancel_work_sync(&trans_pcie->rx_replenish);
1247
1248         /* stop and reset the on-board processor */
1249         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1250
1251         /* clear all status bits */
1252         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
1253         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
1254         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
1255         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1256         clear_bit(STATUS_RFKILL, &trans_pcie->status);
1257 }
1258
1259 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
1260 {
1261         /* let the ucode operate on its own */
1262         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
1263                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
1264
1265         iwl_disable_interrupts(trans);
1266         iwl_clear_bit(trans, CSR_GP_CNTRL,
1267                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1268 }
1269
1270 static int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1271                              struct iwl_device_cmd *dev_cmd, int txq_id)
1272 {
1273         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1274         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1275         struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *) dev_cmd->payload;
1276         struct iwl_cmd_meta *out_meta;
1277         struct iwl_tx_queue *txq;
1278         struct iwl_queue *q;
1279         dma_addr_t phys_addr = 0;
1280         dma_addr_t txcmd_phys;
1281         dma_addr_t scratch_phys;
1282         u16 len, firstlen, secondlen;
1283         u8 wait_write_ptr = 0;
1284         __le16 fc = hdr->frame_control;
1285         u8 hdr_len = ieee80211_hdrlen(fc);
1286         u16 __maybe_unused wifi_seq;
1287
1288         txq = &trans_pcie->txq[txq_id];
1289         q = &txq->q;
1290
1291         if (unlikely(!test_bit(txq_id, trans_pcie->queue_used))) {
1292                 WARN_ON_ONCE(1);
1293                 return -EINVAL;
1294         }
1295
1296         spin_lock(&txq->lock);
1297
1298         /* In AGG mode, the index in the ring must correspond to the WiFi
1299          * sequence number. This is a HW requirements to help the SCD to parse
1300          * the BA.
1301          * Check here that the packets are in the right place on the ring.
1302          */
1303 #ifdef CONFIG_IWLWIFI_DEBUG
1304         wifi_seq = SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1305         WARN_ONCE((iwl_read_prph(trans, SCD_AGGR_SEL) & BIT(txq_id)) &&
1306                   ((wifi_seq & 0xff) != q->write_ptr),
1307                   "Q: %d WiFi Seq %d tfdNum %d",
1308                   txq_id, wifi_seq, q->write_ptr);
1309 #endif
1310
1311         /* Set up driver data for this TFD */
1312         txq->entries[q->write_ptr].skb = skb;
1313         txq->entries[q->write_ptr].cmd = dev_cmd;
1314
1315         dev_cmd->hdr.cmd = REPLY_TX;
1316         dev_cmd->hdr.sequence =
1317                 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1318                             INDEX_TO_SEQ(q->write_ptr)));
1319
1320         /* Set up first empty entry in queue's array of Tx/cmd buffers */
1321         out_meta = &txq->entries[q->write_ptr].meta;
1322
1323         /*
1324          * Use the first empty entry in this queue's command buffer array
1325          * to contain the Tx command and MAC header concatenated together
1326          * (payload data will be in another buffer).
1327          * Size of this varies, due to varying MAC header length.
1328          * If end is not dword aligned, we'll have 2 extra bytes at the end
1329          * of the MAC header (device reads on dword boundaries).
1330          * We'll tell device about this padding later.
1331          */
1332         len = sizeof(struct iwl_tx_cmd) +
1333                 sizeof(struct iwl_cmd_header) + hdr_len;
1334         firstlen = (len + 3) & ~3;
1335
1336         /* Tell NIC about any 2-byte padding after MAC header */
1337         if (firstlen != len)
1338                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1339
1340         /* Physical address of this Tx command's header (not MAC header!),
1341          * within command buffer array. */
1342         txcmd_phys = dma_map_single(trans->dev,
1343                                     &dev_cmd->hdr, firstlen,
1344                                     DMA_BIDIRECTIONAL);
1345         if (unlikely(dma_mapping_error(trans->dev, txcmd_phys)))
1346                 goto out_err;
1347         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
1348         dma_unmap_len_set(out_meta, len, firstlen);
1349
1350         if (!ieee80211_has_morefrags(fc)) {
1351                 txq->need_update = 1;
1352         } else {
1353                 wait_write_ptr = 1;
1354                 txq->need_update = 0;
1355         }
1356
1357         /* Set up TFD's 2nd entry to point directly to remainder of skb,
1358          * if any (802.11 null frames have no payload). */
1359         secondlen = skb->len - hdr_len;
1360         if (secondlen > 0) {
1361                 phys_addr = dma_map_single(trans->dev, skb->data + hdr_len,
1362                                            secondlen, DMA_TO_DEVICE);
1363                 if (unlikely(dma_mapping_error(trans->dev, phys_addr))) {
1364                         dma_unmap_single(trans->dev,
1365                                          dma_unmap_addr(out_meta, mapping),
1366                                          dma_unmap_len(out_meta, len),
1367                                          DMA_BIDIRECTIONAL);
1368                         goto out_err;
1369                 }
1370         }
1371
1372         /* Attach buffers to TFD */
1373         iwlagn_txq_attach_buf_to_tfd(trans, txq, txcmd_phys, firstlen, 1);
1374         if (secondlen > 0)
1375                 iwlagn_txq_attach_buf_to_tfd(trans, txq, phys_addr,
1376                                              secondlen, 0);
1377
1378         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1379                                 offsetof(struct iwl_tx_cmd, scratch);
1380
1381         /* take back ownership of DMA buffer to enable update */
1382         dma_sync_single_for_cpu(trans->dev, txcmd_phys, firstlen,
1383                                 DMA_BIDIRECTIONAL);
1384         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1385         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1386
1387         IWL_DEBUG_TX(trans, "sequence nr = 0X%x\n",
1388                      le16_to_cpu(dev_cmd->hdr.sequence));
1389         IWL_DEBUG_TX(trans, "tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags));
1390
1391         /* Set up entry for this TFD in Tx byte-count array */
1392         iwl_trans_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1393
1394         dma_sync_single_for_device(trans->dev, txcmd_phys, firstlen,
1395                                    DMA_BIDIRECTIONAL);
1396
1397         trace_iwlwifi_dev_tx(trans->dev, skb,
1398                              &txq->tfds[txq->q.write_ptr],
1399                              sizeof(struct iwl_tfd),
1400                              &dev_cmd->hdr, firstlen,
1401                              skb->data + hdr_len, secondlen);
1402         trace_iwlwifi_dev_tx_data(trans->dev, skb,
1403                                   skb->data + hdr_len, secondlen);
1404
1405         /* start timer if queue currently empty */
1406         if (txq->need_update && q->read_ptr == q->write_ptr &&
1407             trans_pcie->wd_timeout)
1408                 mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout);
1409
1410         /* Tell device the write index *just past* this latest filled TFD */
1411         q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1412         iwl_txq_update_write_ptr(trans, txq);
1413
1414         /*
1415          * At this point the frame is "transmitted" successfully
1416          * and we will get a TX status notification eventually,
1417          * regardless of the value of ret. "ret" only indicates
1418          * whether or not we should update the write pointer.
1419          */
1420         if (iwl_queue_space(q) < q->high_mark) {
1421                 if (wait_write_ptr) {
1422                         txq->need_update = 1;
1423                         iwl_txq_update_write_ptr(trans, txq);
1424                 } else {
1425                         iwl_stop_queue(trans, txq);
1426                 }
1427         }
1428         spin_unlock(&txq->lock);
1429         return 0;
1430  out_err:
1431         spin_unlock(&txq->lock);
1432         return -1;
1433 }
1434
1435 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
1436 {
1437         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1438         int err;
1439         bool hw_rfkill;
1440
1441         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1442
1443         if (!trans_pcie->irq_requested) {
1444                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
1445                         iwl_irq_tasklet, (unsigned long)trans);
1446
1447                 iwl_alloc_isr_ict(trans);
1448
1449                 err = request_irq(trans_pcie->irq, iwl_isr_ict, IRQF_SHARED,
1450                                   DRV_NAME, trans);
1451                 if (err) {
1452                         IWL_ERR(trans, "Error allocating IRQ %d\n",
1453                                 trans_pcie->irq);
1454                         goto error;
1455                 }
1456
1457                 INIT_WORK(&trans_pcie->rx_replenish, iwl_bg_rx_replenish);
1458                 trans_pcie->irq_requested = true;
1459         }
1460
1461         err = iwl_prepare_card_hw(trans);
1462         if (err) {
1463                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1464                 goto err_free_irq;
1465         }
1466
1467         iwl_apm_init(trans);
1468
1469         /* From now on, the op_mode will be kept updated about RF kill state */
1470         iwl_enable_rfkill_int(trans);
1471
1472         hw_rfkill = iwl_is_rfkill_set(trans);
1473         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1474
1475         return err;
1476
1477 err_free_irq:
1478         trans_pcie->irq_requested = false;
1479         free_irq(trans_pcie->irq, trans);
1480 error:
1481         iwl_free_isr_ict(trans);
1482         tasklet_kill(&trans_pcie->irq_tasklet);
1483         return err;
1484 }
1485
1486 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
1487                                    bool op_mode_leaving)
1488 {
1489         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1490         bool hw_rfkill;
1491         unsigned long flags;
1492
1493         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1494         iwl_disable_interrupts(trans);
1495         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1496
1497         iwl_apm_stop(trans);
1498
1499         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1500         iwl_disable_interrupts(trans);
1501         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1502
1503         if (!op_mode_leaving) {
1504                 /*
1505                  * Even if we stop the HW, we still want the RF kill
1506                  * interrupt
1507                  */
1508                 iwl_enable_rfkill_int(trans);
1509
1510                 /*
1511                  * Check again since the RF kill state may have changed while
1512                  * all the interrupts were disabled, in this case we couldn't
1513                  * receive the RF kill interrupt and update the state in the
1514                  * op_mode.
1515                  */
1516                 hw_rfkill = iwl_is_rfkill_set(trans);
1517                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1518         }
1519 }
1520
1521 static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1522                                    struct sk_buff_head *skbs)
1523 {
1524         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1525         struct iwl_tx_queue *txq = &trans_pcie->txq[txq_id];
1526         /* n_bd is usually 256 => n_bd - 1 = 0xff */
1527         int tfd_num = ssn & (txq->q.n_bd - 1);
1528
1529         spin_lock(&txq->lock);
1530
1531         if (txq->q.read_ptr != tfd_num) {
1532                 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1533                                    txq_id, txq->q.read_ptr, tfd_num, ssn);
1534                 iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
1535                 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1536                         iwl_wake_queue(trans, txq);
1537         }
1538
1539         spin_unlock(&txq->lock);
1540 }
1541
1542 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1543 {
1544         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1545 }
1546
1547 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1548 {
1549         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1550 }
1551
1552 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1553 {
1554         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1555 }
1556
1557 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1558                                      const struct iwl_trans_config *trans_cfg)
1559 {
1560         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1561
1562         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1563         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1564         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1565                 trans_pcie->n_no_reclaim_cmds = 0;
1566         else
1567                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1568         if (trans_pcie->n_no_reclaim_cmds)
1569                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1570                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1571
1572         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
1573         if (trans_pcie->rx_buf_size_8k)
1574                 trans_pcie->rx_page_order = get_order(8 * 1024);
1575         else
1576                 trans_pcie->rx_page_order = get_order(4 * 1024);
1577
1578         trans_pcie->wd_timeout =
1579                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
1580
1581         trans_pcie->command_names = trans_cfg->command_names;
1582 }
1583
1584 void iwl_trans_pcie_free(struct iwl_trans *trans)
1585 {
1586         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1587
1588         iwl_trans_pcie_tx_free(trans);
1589         iwl_trans_pcie_rx_free(trans);
1590
1591         if (trans_pcie->irq_requested == true) {
1592                 free_irq(trans_pcie->irq, trans);
1593                 iwl_free_isr_ict(trans);
1594         }
1595
1596         pci_disable_msi(trans_pcie->pci_dev);
1597         iounmap(trans_pcie->hw_base);
1598         pci_release_regions(trans_pcie->pci_dev);
1599         pci_disable_device(trans_pcie->pci_dev);
1600         kmem_cache_destroy(trans->dev_cmd_pool);
1601
1602         kfree(trans);
1603 }
1604
1605 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1606 {
1607         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1608
1609         if (state)
1610                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1611         else
1612                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
1613 }
1614
1615 #ifdef CONFIG_PM_SLEEP
1616 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
1617 {
1618         return 0;
1619 }
1620
1621 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
1622 {
1623         bool hw_rfkill;
1624
1625         iwl_enable_rfkill_int(trans);
1626
1627         hw_rfkill = iwl_is_rfkill_set(trans);
1628         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1629
1630         if (!hw_rfkill)
1631                 iwl_enable_interrupts(trans);
1632
1633         return 0;
1634 }
1635 #endif /* CONFIG_PM_SLEEP */
1636
1637 #define IWL_FLUSH_WAIT_MS       2000
1638
1639 static int iwl_trans_pcie_wait_tx_queue_empty(struct iwl_trans *trans)
1640 {
1641         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1642         struct iwl_tx_queue *txq;
1643         struct iwl_queue *q;
1644         int cnt;
1645         unsigned long now = jiffies;
1646         int ret = 0;
1647
1648         /* waiting for all the tx frames complete might take a while */
1649         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1650                 if (cnt == trans_pcie->cmd_queue)
1651                         continue;
1652                 txq = &trans_pcie->txq[cnt];
1653                 q = &txq->q;
1654                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1655                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1656                         msleep(1);
1657
1658                 if (q->read_ptr != q->write_ptr) {
1659                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
1660                         ret = -ETIMEDOUT;
1661                         break;
1662                 }
1663         }
1664         return ret;
1665 }
1666
1667 static const char *get_fh_string(int cmd)
1668 {
1669 #define IWL_CMD(x) case x: return #x
1670         switch (cmd) {
1671         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1672         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1673         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1674         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1675         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1676         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1677         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1678         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1679         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1680         default:
1681                 return "UNKNOWN";
1682         }
1683 #undef IWL_CMD
1684 }
1685
1686 int iwl_dump_fh(struct iwl_trans *trans, char **buf)
1687 {
1688         int i;
1689         static const u32 fh_tbl[] = {
1690                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1691                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1692                 FH_RSCSR_CHNL0_WPTR,
1693                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1694                 FH_MEM_RSSR_SHARED_CTRL_REG,
1695                 FH_MEM_RSSR_RX_STATUS_REG,
1696                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1697                 FH_TSSR_TX_STATUS_REG,
1698                 FH_TSSR_TX_ERROR_REG
1699         };
1700
1701 #ifdef CONFIG_IWLWIFI_DEBUGFS
1702         if (buf) {
1703                 int pos = 0;
1704                 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1705
1706                 *buf = kmalloc(bufsz, GFP_KERNEL);
1707                 if (!*buf)
1708                         return -ENOMEM;
1709
1710                 pos += scnprintf(*buf + pos, bufsz - pos,
1711                                 "FH register values:\n");
1712
1713                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1714                         pos += scnprintf(*buf + pos, bufsz - pos,
1715                                 "  %34s: 0X%08x\n",
1716                                 get_fh_string(fh_tbl[i]),
1717                                 iwl_read_direct32(trans, fh_tbl[i]));
1718
1719                 return pos;
1720         }
1721 #endif
1722
1723         IWL_ERR(trans, "FH register values:\n");
1724         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
1725                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1726                         get_fh_string(fh_tbl[i]),
1727                         iwl_read_direct32(trans, fh_tbl[i]));
1728
1729         return 0;
1730 }
1731
1732 static const char *get_csr_string(int cmd)
1733 {
1734 #define IWL_CMD(x) case x: return #x
1735         switch (cmd) {
1736         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1737         IWL_CMD(CSR_INT_COALESCING);
1738         IWL_CMD(CSR_INT);
1739         IWL_CMD(CSR_INT_MASK);
1740         IWL_CMD(CSR_FH_INT_STATUS);
1741         IWL_CMD(CSR_GPIO_IN);
1742         IWL_CMD(CSR_RESET);
1743         IWL_CMD(CSR_GP_CNTRL);
1744         IWL_CMD(CSR_HW_REV);
1745         IWL_CMD(CSR_EEPROM_REG);
1746         IWL_CMD(CSR_EEPROM_GP);
1747         IWL_CMD(CSR_OTP_GP_REG);
1748         IWL_CMD(CSR_GIO_REG);
1749         IWL_CMD(CSR_GP_UCODE_REG);
1750         IWL_CMD(CSR_GP_DRIVER_REG);
1751         IWL_CMD(CSR_UCODE_DRV_GP1);
1752         IWL_CMD(CSR_UCODE_DRV_GP2);
1753         IWL_CMD(CSR_LED_REG);
1754         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1755         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1756         IWL_CMD(CSR_ANA_PLL_CFG);
1757         IWL_CMD(CSR_HW_REV_WA_REG);
1758         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1759         default:
1760                 return "UNKNOWN";
1761         }
1762 #undef IWL_CMD
1763 }
1764
1765 void iwl_dump_csr(struct iwl_trans *trans)
1766 {
1767         int i;
1768         static const u32 csr_tbl[] = {
1769                 CSR_HW_IF_CONFIG_REG,
1770                 CSR_INT_COALESCING,
1771                 CSR_INT,
1772                 CSR_INT_MASK,
1773                 CSR_FH_INT_STATUS,
1774                 CSR_GPIO_IN,
1775                 CSR_RESET,
1776                 CSR_GP_CNTRL,
1777                 CSR_HW_REV,
1778                 CSR_EEPROM_REG,
1779                 CSR_EEPROM_GP,
1780                 CSR_OTP_GP_REG,
1781                 CSR_GIO_REG,
1782                 CSR_GP_UCODE_REG,
1783                 CSR_GP_DRIVER_REG,
1784                 CSR_UCODE_DRV_GP1,
1785                 CSR_UCODE_DRV_GP2,
1786                 CSR_LED_REG,
1787                 CSR_DRAM_INT_TBL_REG,
1788                 CSR_GIO_CHICKEN_BITS,
1789                 CSR_ANA_PLL_CFG,
1790                 CSR_HW_REV_WA_REG,
1791                 CSR_DBG_HPET_MEM_REG
1792         };
1793         IWL_ERR(trans, "CSR values:\n");
1794         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1795                 "CSR_INT_PERIODIC_REG)\n");
1796         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1797                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1798                         get_csr_string(csr_tbl[i]),
1799                         iwl_read32(trans, csr_tbl[i]));
1800         }
1801 }
1802
1803 #ifdef CONFIG_IWLWIFI_DEBUGFS
1804 /* create and remove of files */
1805 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1806         if (!debugfs_create_file(#name, mode, parent, trans,            \
1807                                  &iwl_dbgfs_##name##_ops))              \
1808                 goto err;                                               \
1809 } while (0)
1810
1811 /* file operation */
1812 #define DEBUGFS_READ_FUNC(name)                                         \
1813 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1814                                         char __user *user_buf,          \
1815                                         size_t count, loff_t *ppos);
1816
1817 #define DEBUGFS_WRITE_FUNC(name)                                        \
1818 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1819                                         const char __user *user_buf,    \
1820                                         size_t count, loff_t *ppos);
1821
1822
1823 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1824         DEBUGFS_READ_FUNC(name);                                        \
1825 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1826         .read = iwl_dbgfs_##name##_read,                                \
1827         .open = simple_open,                                            \
1828         .llseek = generic_file_llseek,                                  \
1829 };
1830
1831 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1832         DEBUGFS_WRITE_FUNC(name);                                       \
1833 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1834         .write = iwl_dbgfs_##name##_write,                              \
1835         .open = simple_open,                                            \
1836         .llseek = generic_file_llseek,                                  \
1837 };
1838
1839 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1840         DEBUGFS_READ_FUNC(name);                                        \
1841         DEBUGFS_WRITE_FUNC(name);                                       \
1842 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1843         .write = iwl_dbgfs_##name##_write,                              \
1844         .read = iwl_dbgfs_##name##_read,                                \
1845         .open = simple_open,                                            \
1846         .llseek = generic_file_llseek,                                  \
1847 };
1848
1849 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1850                                        char __user *user_buf,
1851                                        size_t count, loff_t *ppos)
1852 {
1853         struct iwl_trans *trans = file->private_data;
1854         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1855         struct iwl_tx_queue *txq;
1856         struct iwl_queue *q;
1857         char *buf;
1858         int pos = 0;
1859         int cnt;
1860         int ret;
1861         size_t bufsz;
1862
1863         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1864
1865         if (!trans_pcie->txq)
1866                 return -EAGAIN;
1867
1868         buf = kzalloc(bufsz, GFP_KERNEL);
1869         if (!buf)
1870                 return -ENOMEM;
1871
1872         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1873                 txq = &trans_pcie->txq[cnt];
1874                 q = &txq->q;
1875                 pos += scnprintf(buf + pos, bufsz - pos,
1876                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1877                                 cnt, q->read_ptr, q->write_ptr,
1878                                 !!test_bit(cnt, trans_pcie->queue_used),
1879                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1880         }
1881         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1882         kfree(buf);
1883         return ret;
1884 }
1885
1886 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1887                                        char __user *user_buf,
1888                                        size_t count, loff_t *ppos)
1889 {
1890         struct iwl_trans *trans = file->private_data;
1891         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1892         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
1893         char buf[256];
1894         int pos = 0;
1895         const size_t bufsz = sizeof(buf);
1896
1897         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1898                                                 rxq->read);
1899         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1900                                                 rxq->write);
1901         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1902                                                 rxq->free_count);
1903         if (rxq->rb_stts) {
1904                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1905                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1906         } else {
1907                 pos += scnprintf(buf + pos, bufsz - pos,
1908                                         "closed_rb_num: Not Allocated\n");
1909         }
1910         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1911 }
1912
1913 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1914                                         char __user *user_buf,
1915                                         size_t count, loff_t *ppos)
1916 {
1917         struct iwl_trans *trans = file->private_data;
1918         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1919         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1920
1921         int pos = 0;
1922         char *buf;
1923         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1924         ssize_t ret;
1925
1926         buf = kzalloc(bufsz, GFP_KERNEL);
1927         if (!buf)
1928                 return -ENOMEM;
1929
1930         pos += scnprintf(buf + pos, bufsz - pos,
1931                         "Interrupt Statistics Report:\n");
1932
1933         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1934                 isr_stats->hw);
1935         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1936                 isr_stats->sw);
1937         if (isr_stats->sw || isr_stats->hw) {
1938                 pos += scnprintf(buf + pos, bufsz - pos,
1939                         "\tLast Restarting Code:  0x%X\n",
1940                         isr_stats->err_code);
1941         }
1942 #ifdef CONFIG_IWLWIFI_DEBUG
1943         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1944                 isr_stats->sch);
1945         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1946                 isr_stats->alive);
1947 #endif
1948         pos += scnprintf(buf + pos, bufsz - pos,
1949                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1950
1951         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1952                 isr_stats->ctkill);
1953
1954         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1955                 isr_stats->wakeup);
1956
1957         pos += scnprintf(buf + pos, bufsz - pos,
1958                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1959
1960         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1961                 isr_stats->tx);
1962
1963         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1964                 isr_stats->unhandled);
1965
1966         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1967         kfree(buf);
1968         return ret;
1969 }
1970
1971 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1972                                          const char __user *user_buf,
1973                                          size_t count, loff_t *ppos)
1974 {
1975         struct iwl_trans *trans = file->private_data;
1976         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1977         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1978
1979         char buf[8];
1980         int buf_size;
1981         u32 reset_flag;
1982
1983         memset(buf, 0, sizeof(buf));
1984         buf_size = min(count, sizeof(buf) -  1);
1985         if (copy_from_user(buf, user_buf, buf_size))
1986                 return -EFAULT;
1987         if (sscanf(buf, "%x", &reset_flag) != 1)
1988                 return -EFAULT;
1989         if (reset_flag == 0)
1990                 memset(isr_stats, 0, sizeof(*isr_stats));
1991
1992         return count;
1993 }
1994
1995 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1996                                    const char __user *user_buf,
1997                                    size_t count, loff_t *ppos)
1998 {
1999         struct iwl_trans *trans = file->private_data;
2000         char buf[8];
2001         int buf_size;
2002         int csr;
2003
2004         memset(buf, 0, sizeof(buf));
2005         buf_size = min(count, sizeof(buf) -  1);
2006         if (copy_from_user(buf, user_buf, buf_size))
2007                 return -EFAULT;
2008         if (sscanf(buf, "%d", &csr) != 1)
2009                 return -EFAULT;
2010
2011         iwl_dump_csr(trans);
2012
2013         return count;
2014 }
2015
2016 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2017                                      char __user *user_buf,
2018                                      size_t count, loff_t *ppos)
2019 {
2020         struct iwl_trans *trans = file->private_data;
2021         char *buf = NULL;
2022         int pos = 0;
2023         ssize_t ret = -EFAULT;
2024
2025         ret = pos = iwl_dump_fh(trans, &buf);
2026         if (buf) {
2027                 ret = simple_read_from_buffer(user_buf,
2028                                               count, ppos, buf, pos);
2029                 kfree(buf);
2030         }
2031
2032         return ret;
2033 }
2034
2035 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
2036                                           const char __user *user_buf,
2037                                           size_t count, loff_t *ppos)
2038 {
2039         struct iwl_trans *trans = file->private_data;
2040
2041         if (!trans->op_mode)
2042                 return -EAGAIN;
2043
2044         local_bh_disable();
2045         iwl_op_mode_nic_error(trans->op_mode);
2046         local_bh_enable();
2047
2048         return count;
2049 }
2050
2051 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2052 DEBUGFS_READ_FILE_OPS(fh_reg);
2053 DEBUGFS_READ_FILE_OPS(rx_queue);
2054 DEBUGFS_READ_FILE_OPS(tx_queue);
2055 DEBUGFS_WRITE_FILE_OPS(csr);
2056 DEBUGFS_WRITE_FILE_OPS(fw_restart);
2057
2058 /*
2059  * Create the debugfs files and directories
2060  *
2061  */
2062 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2063                                          struct dentry *dir)
2064 {
2065         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2066         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2067         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2068         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2069         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2070         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
2071         return 0;
2072
2073 err:
2074         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2075         return -ENOMEM;
2076 }
2077 #else
2078 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
2079                                          struct dentry *dir)
2080 {
2081         return 0;
2082 }
2083 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2084
2085 static const struct iwl_trans_ops trans_ops_pcie = {
2086         .start_hw = iwl_trans_pcie_start_hw,
2087         .stop_hw = iwl_trans_pcie_stop_hw,
2088         .fw_alive = iwl_trans_pcie_fw_alive,
2089         .start_fw = iwl_trans_pcie_start_fw,
2090         .stop_device = iwl_trans_pcie_stop_device,
2091
2092         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
2093
2094         .send_cmd = iwl_trans_pcie_send_cmd,
2095
2096         .tx = iwl_trans_pcie_tx,
2097         .reclaim = iwl_trans_pcie_reclaim,
2098
2099         .txq_disable = iwl_trans_pcie_txq_disable,
2100         .txq_enable = iwl_trans_pcie_txq_enable,
2101
2102         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2103
2104         .wait_tx_queue_empty = iwl_trans_pcie_wait_tx_queue_empty,
2105
2106 #ifdef CONFIG_PM_SLEEP
2107         .suspend = iwl_trans_pcie_suspend,
2108         .resume = iwl_trans_pcie_resume,
2109 #endif
2110         .write8 = iwl_trans_pcie_write8,
2111         .write32 = iwl_trans_pcie_write32,
2112         .read32 = iwl_trans_pcie_read32,
2113         .configure = iwl_trans_pcie_configure,
2114         .set_pmi = iwl_trans_pcie_set_pmi,
2115 };
2116
2117 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2118                                        const struct pci_device_id *ent,
2119                                        const struct iwl_cfg *cfg)
2120 {
2121         struct iwl_trans_pcie *trans_pcie;
2122         struct iwl_trans *trans;
2123         u16 pci_cmd;
2124         int err;
2125
2126         trans = kzalloc(sizeof(struct iwl_trans) +
2127                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
2128
2129         if (!trans)
2130                 return NULL;
2131
2132         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2133
2134         trans->ops = &trans_ops_pcie;
2135         trans->cfg = cfg;
2136         trans_pcie->trans = trans;
2137         spin_lock_init(&trans_pcie->irq_lock);
2138         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2139
2140         /* W/A - seems to solve weird behavior. We need to remove this if we
2141          * don't want to stay in L1 all the time. This wastes a lot of power */
2142         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
2143                                PCIE_LINK_STATE_CLKPM);
2144
2145         if (pci_enable_device(pdev)) {
2146                 err = -ENODEV;
2147                 goto out_no_pci;
2148         }
2149
2150         pci_set_master(pdev);
2151
2152         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
2153         if (!err)
2154                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
2155         if (err) {
2156                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2157                 if (!err)
2158                         err = pci_set_consistent_dma_mask(pdev,
2159                                                           DMA_BIT_MASK(32));
2160                 /* both attempts failed: */
2161                 if (err) {
2162                         dev_printk(KERN_ERR, &pdev->dev,
2163                                    "No suitable DMA available.\n");
2164                         goto out_pci_disable_device;
2165                 }
2166         }
2167
2168         err = pci_request_regions(pdev, DRV_NAME);
2169         if (err) {
2170                 dev_printk(KERN_ERR, &pdev->dev,
2171                            "pci_request_regions failed\n");
2172                 goto out_pci_disable_device;
2173         }
2174
2175         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
2176         if (!trans_pcie->hw_base) {
2177                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
2178                 err = -ENODEV;
2179                 goto out_pci_release_regions;
2180         }
2181
2182         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2183          * PCI Tx retries from interfering with C3 CPU state */
2184         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2185
2186         err = pci_enable_msi(pdev);
2187         if (err)
2188                 dev_printk(KERN_ERR, &pdev->dev,
2189                            "pci_enable_msi failed(0X%x)\n", err);
2190
2191         trans->dev = &pdev->dev;
2192         trans_pcie->irq = pdev->irq;
2193         trans_pcie->pci_dev = pdev;
2194         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2195         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
2196         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
2197                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
2198
2199         /* TODO: Move this away, not needed if not MSI */
2200         /* enable rfkill interrupt: hw bug w/a */
2201         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2202         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
2203                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
2204                 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2205         }
2206
2207         /* Initialize the wait queue for commands */
2208         init_waitqueue_head(&trans_pcie->wait_command_queue);
2209         spin_lock_init(&trans->reg_lock);
2210
2211         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
2212                  "iwl_cmd_pool:%s", dev_name(trans->dev));
2213
2214         trans->dev_cmd_headroom = 0;
2215         trans->dev_cmd_pool =
2216                 kmem_cache_create(trans->dev_cmd_pool_name,
2217                                   sizeof(struct iwl_device_cmd)
2218                                   + trans->dev_cmd_headroom,
2219                                   sizeof(void *),
2220                                   SLAB_HWCACHE_ALIGN,
2221                                   NULL);
2222
2223         if (!trans->dev_cmd_pool)
2224                 goto out_pci_disable_msi;
2225
2226         return trans;
2227
2228 out_pci_disable_msi:
2229         pci_disable_msi(pdev);
2230 out_pci_release_regions:
2231         pci_release_regions(pdev);
2232 out_pci_disable_device:
2233         pci_disable_device(pdev);
2234 out_no_pci:
2235         kfree(trans);
2236         return NULL;
2237 }