arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         host1x {
   8                 compatible = "nvidia,tegra20-host1x", "simple-bus";
   9                 reg = <0x50000000 0x00024000>;
  10                 interrupts = <0 65 0x04   /* mpcore syncpt */
  11                               0 67 0x04>; /* mpcore general */
  12
  13                 #address-cells = <1>;
  14                 #size-cells = <1>;
  15
  16                 ranges = <0x54000000 0x54000000 0x04000000>;
  17
  18                 mpe {
  19                         compatible = "nvidia,tegra20-mpe";
  20                         reg = <0x54040000 0x00040000>;
  21                         interrupts = <0 68 0x04>;
  22                 };
  23
  24                 vi {
  25                         compatible = "nvidia,tegra20-vi";
  26                         reg = <0x54080000 0x00040000>;
  27                         interrupts = <0 69 0x04>;
  28                 };
  29
  30                 epp {
  31                         compatible = "nvidia,tegra20-epp";
  32                         reg = <0x540c0000 0x00040000>;
  33                         interrupts = <0 70 0x04>;
  34                 };
  35
  36                 isp {
  37                         compatible = "nvidia,tegra20-isp";
  38                         reg = <0x54100000 0x00040000>;
  39                         interrupts = <0 71 0x04>;
  40                 };
  41
  42                 gr2d {
  43                         compatible = "nvidia,tegra20-gr2d";
  44                         reg = <0x54140000 0x00040000>;
  45                         interrupts = <0 72 0x04>;
  46                 };
  47
  48                 gr3d {
  49                         compatible = "nvidia,tegra20-gr3d";
  50                         reg = <0x54180000 0x00040000>;
  51                 };
  52
  53                 dc@54200000 {
  54                         compatible = "nvidia,tegra20-dc";
  55                         reg = <0x54200000 0x00040000>;
  56                         interrupts = <0 73 0x04>;
  57
  58                         rgb {
  59                                 status = "disabled";
  60                         };
  61                 };
  62
  63                 dc@54240000 {
  64                         compatible = "nvidia,tegra20-dc";
  65                         reg = <0x54240000 0x00040000>;
  66                         interrupts = <0 74 0x04>;
  67
  68                         rgb {
  69                                 status = "disabled";
  70                         };
  71                 };
  72
  73                 hdmi {
  74                         compatible = "nvidia,tegra20-hdmi";
  75                         reg = <0x54280000 0x00040000>;
  76                         interrupts = <0 75 0x04>;
  77                         status = "disabled";
  78                 };
  79
  80                 tvo {
  81                         compatible = "nvidia,tegra20-tvo";
  82                         reg = <0x542c0000 0x00040000>;
  83                         interrupts = <0 76 0x04>;
  84                         status = "disabled";
  85                 };
  86
  87                 dsi {
  88                         compatible = "nvidia,tegra20-dsi";
  89                         reg = <0x54300000 0x00040000>;
  90                         status = "disabled";
  91                 };
  92         };
  93
  94         cache-controller@50043000 {
  95                 compatible = "arm,pl310-cache";
  96                 reg = <0x50043000 0x1000>;
  97                 arm,data-latency = <5 5 2>;
  98                 arm,tag-latency = <4 4 2>;
  99                 cache-unified;
 100                 cache-level = <2>;
 101         };
 102
 103         intc: interrupt-controller {
 104                 compatible = "arm,cortex-a9-gic";
 105                 reg = <0x50041000 0x1000
 106                        0x50040100 0x0100>;
 107                 interrupt-controller;
 108                 #interrupt-cells = <3>;
 109         };
 110
 111         apbdma: dma {
 112                 compatible = "nvidia,tegra20-apbdma";
 113                 reg = <0x6000a000 0x1200>;
 114                 interrupts = <0 104 0x04
 115                               0 105 0x04
 116                               0 106 0x04
 117                               0 107 0x04
 118                               0 108 0x04
 119                               0 109 0x04
 120                               0 110 0x04
 121                               0 111 0x04
 122                               0 112 0x04
 123                               0 113 0x04
 124                               0 114 0x04
 125                               0 115 0x04
 126                               0 116 0x04
 127                               0 117 0x04
 128                               0 118 0x04
 129                               0 119 0x04>;
 130         };
 131
 132         ahb {
 133                 compatible = "nvidia,tegra20-ahb";
 134                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 135         };
 136
 137         gpio: gpio {
 138                 compatible = "nvidia,tegra20-gpio";
 139                 reg = <0x6000d000 0x1000>;
 140                 interrupts = <0 32 0x04
 141                               0 33 0x04
 142                               0 34 0x04
 143                               0 35 0x04
 144                               0 55 0x04
 145                               0 87 0x04
 146                               0 89 0x04>;
 147                 #gpio-cells = <2>;
 148                 gpio-controller;
 149                 #interrupt-cells = <2>;
 150                 interrupt-controller;
 151         };
 152
 153         pinmux: pinmux {
 154                 compatible = "nvidia,tegra20-pinmux";
 155                 reg = <0x70000014 0x10   /* Tri-state registers */
 156                        0x70000080 0x20   /* Mux registers */
 157                        0x700000a0 0x14   /* Pull-up/down registers */
 158                        0x70000868 0xa8>; /* Pad control registers */
 159         };
 160
 161         das {
 162                 compatible = "nvidia,tegra20-das";
 163                 reg = <0x70000c00 0x80>;
 164         };
 165
 166         tegra_i2s1: i2s@70002800 {
 167                 compatible = "nvidia,tegra20-i2s";
 168                 reg = <0x70002800 0x200>;
 169                 interrupts = <0 13 0x04>;
 170                 nvidia,dma-request-selector = <&apbdma 2>;
 171                 status = "disabled";
 172         };
 173
 174         tegra_i2s2: i2s@70002a00 {
 175                 compatible = "nvidia,tegra20-i2s";
 176                 reg = <0x70002a00 0x200>;
 177                 interrupts = <0 3 0x04>;
 178                 nvidia,dma-request-selector = <&apbdma 1>;
 179                 status = "disabled";
 180         };
 181
 182         serial@70006000 {
 183                 compatible = "nvidia,tegra20-uart";
 184                 reg = <0x70006000 0x40>;
 185                 reg-shift = <2>;
 186                 interrupts = <0 36 0x04>;
 187                 status = "disabled";
 188         };
 189
 190         serial@70006040 {
 191                 compatible = "nvidia,tegra20-uart";
 192                 reg = <0x70006040 0x40>;
 193                 reg-shift = <2>;
 194                 interrupts = <0 37 0x04>;
 195                 status = "disabled";
 196         };
 197
 198         serial@70006200 {
 199                 compatible = "nvidia,tegra20-uart";
 200                 reg = <0x70006200 0x100>;
 201                 reg-shift = <2>;
 202                 interrupts = <0 46 0x04>;
 203                 status = "disabled";
 204         };
 205
 206         serial@70006300 {
 207                 compatible = "nvidia,tegra20-uart";
 208                 reg = <0x70006300 0x100>;
 209                 reg-shift = <2>;
 210                 interrupts = <0 90 0x04>;
 211                 status = "disabled";
 212         };
 213
 214         serial@70006400 {
 215                 compatible = "nvidia,tegra20-uart";
 216                 reg = <0x70006400 0x100>;
 217                 reg-shift = <2>;
 218                 interrupts = <0 91 0x04>;
 219                 status = "disabled";
 220         };
 221
 222         pwm: pwm {
 223                 compatible = "nvidia,tegra20-pwm";
 224                 reg = <0x7000a000 0x100>;
 225                 #pwm-cells = <2>;
 226         };
 227
 228         i2c@7000c000 {
 229                 compatible = "nvidia,tegra20-i2c";
 230                 reg = <0x7000c000 0x100>;
 231                 interrupts = <0 38 0x04>;
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 status = "disabled";
 235         };
 236
 237         spi@7000c380 {
 238                 compatible = "nvidia,tegra20-sflash";
 239                 reg = <0x7000c380 0x80>;
 240                 interrupts = <0 39 0x04>;
 241                 nvidia,dma-request-selector = <&apbdma 11>;
 242                 #address-cells = <1>;
 243                 #size-cells = <0>;
 244                 status = "disabled";
 245         };
 246
 247         i2c@7000c400 {
 248                 compatible = "nvidia,tegra20-i2c";
 249                 reg = <0x7000c400 0x100>;
 250                 interrupts = <0 84 0x04>;
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 status = "disabled";
 254         };
 255
 256         i2c@7000c500 {
 257                 compatible = "nvidia,tegra20-i2c";
 258                 reg = <0x7000c500 0x100>;
 259                 interrupts = <0 92 0x04>;
 260                 #address-cells = <1>;
 261                 #size-cells = <0>;
 262                 status = "disabled";
 263         };
 264
 265         i2c@7000d000 {
 266                 compatible = "nvidia,tegra20-i2c-dvc";
 267                 reg = <0x7000d000 0x200>;
 268                 interrupts = <0 53 0x04>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 status = "disabled";
 272         };
 273
 274         spi@7000d400 {
 275                 compatible = "nvidia,tegra20-slink";
 276                 reg = <0x7000d400 0x200>;
 277                 interrupts = <0 59 0x04>;
 278                 nvidia,dma-request-selector = <&apbdma 15>;
 279                 #address-cells = <1>;
 280                 #size-cells = <0>;
 281                 status = "disabled";
 282         };
 283
 284         spi@7000d600 {
 285                 compatible = "nvidia,tegra20-slink";
 286                 reg = <0x7000d600 0x200>;
 287                 interrupts = <0 82 0x04>;
 288                 nvidia,dma-request-selector = <&apbdma 16>;
 289                 #address-cells = <1>;
 290                 #size-cells = <0>;
 291                 status = "disabled";
 292         };
 293
 294         spi@7000d800 {
 295                 compatible = "nvidia,tegra20-slink";
 296                 reg = <0x7000d480 0x200>;
 297                 interrupts = <0 83 0x04>;
 298                 nvidia,dma-request-selector = <&apbdma 17>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 status = "disabled";
 302         };
 303
 304         spi@7000da00 {
 305                 compatible = "nvidia,tegra20-slink";
 306                 reg = <0x7000da00 0x200>;
 307                 interrupts = <0 93 0x04>;
 308                 nvidia,dma-request-selector = <&apbdma 18>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 status = "disabled";
 312         };
 313
 314         pmc {
 315                 compatible = "nvidia,tegra20-pmc";
 316                 reg = <0x7000e400 0x400>;
 317         };
 318
 319         memory-controller@7000f000 {
 320                 compatible = "nvidia,tegra20-mc";
 321                 reg = <0x7000f000 0x024
 322                        0x7000f03c 0x3c4>;
 323                 interrupts = <0 77 0x04>;
 324         };
 325
 326         gart {
 327                 compatible = "nvidia,tegra20-gart";
 328                 reg = <0x7000f024 0x00000018    /* controller registers */
 329                        0x58000000 0x02000000>;  /* GART aperture */
 330         };
 331
 332         memory-controller@7000f400 {
 333                 compatible = "nvidia,tegra20-emc";
 334                 reg = <0x7000f400 0x200>;
 335                 #address-cells = <1>;
 336                 #size-cells = <0>;
 337         };
 338
 339         usb@c5000000 {
 340                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 341                 reg = <0xc5000000 0x4000>;
 342                 interrupts = <0 20 0x04>;
 343                 phy_type = "utmi";
 344                 nvidia,has-legacy-mode;
 345                 status = "disabled";
 346         };
 347
 348         usb@c5004000 {
 349                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 350                 reg = <0xc5004000 0x4000>;
 351                 interrupts = <0 21 0x04>;
 352                 phy_type = "ulpi";
 353                 status = "disabled";
 354         };
 355
 356         usb@c5008000 {
 357                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 358                 reg = <0xc5008000 0x4000>;
 359                 interrupts = <0 97 0x04>;
 360                 phy_type = "utmi";
 361                 status = "disabled";
 362         };
 363
 364         sdhci@c8000000 {
 365                 compatible = "nvidia,tegra20-sdhci";
 366                 reg = <0xc8000000 0x200>;
 367                 interrupts = <0 14 0x04>;
 368                 status = "disabled";
 369         };
 370
 371         sdhci@c8000200 {
 372                 compatible = "nvidia,tegra20-sdhci";
 373                 reg = <0xc8000200 0x200>;
 374                 interrupts = <0 15 0x04>;
 375                 status = "disabled";
 376         };
 377
 378         sdhci@c8000400 {
 379                 compatible = "nvidia,tegra20-sdhci";
 380                 reg = <0xc8000400 0x200>;
 381                 interrupts = <0 19 0x04>;
 382                 status = "disabled";
 383         };
 384
 385         sdhci@c8000600 {
 386                 compatible = "nvidia,tegra20-sdhci";
 387                 reg = <0xc8000600 0x200>;
 388                 interrupts = <0 31 0x04>;
 389                 status = "disabled";
 390         };
 391
 392         pmu {
 393                 compatible = "arm,cortex-a9-pmu";
 394                 interrupts = <0 56 0x04
 395                               0 57 0x04>;
 396         };
 397 };