2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
36 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
42 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
48 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
54 compatible = "arm,cortex-a9";
56 next-level-cache = <&L2>;
60 intc: interrupt-controller@00a01000 {
61 compatible = "arm,cortex-a9-gic";
62 #interrupt-cells = <3>;
66 reg = <0x00a01000 0x1000>,
75 compatible = "fsl,imx-ckil", "fixed-clock";
76 clock-frequency = <32768>;
80 compatible = "fsl,imx-ckih1", "fixed-clock";
81 clock-frequency = <0>;
85 compatible = "fsl,imx-osc", "fixed-clock";
86 clock-frequency = <24000000>;
93 compatible = "simple-bus";
94 interrupt-parent = <&intc>;
98 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
99 reg = <0x00110000 0x2000>;
100 clocks = <&clks 106>;
104 compatible = "fsl,imx6q-gpmi-nand";
105 #address-cells = <1>;
107 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
108 reg-names = "gpmi-nand", "bch";
109 interrupts = <0 13 0x04>, <0 15 0x04>;
110 interrupt-names = "gpmi-dma", "bch";
111 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
112 <&clks 150>, <&clks 149>;
113 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
114 "gpmi_bch_apb", "per1_bch";
115 fsl,gpmi-dma-channel = <0>;
120 compatible = "arm,cortex-a9-twd-timer";
121 reg = <0x00a00600 0x20>;
122 interrupts = <1 13 0xf01>;
125 L2: l2-cache@00a02000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x00a02000 0x1000>;
128 interrupts = <0 92 0x04>;
133 aips-bus@02000000 { /* AIPS1 */
134 compatible = "fsl,aips-bus", "simple-bus";
135 #address-cells = <1>;
137 reg = <0x02000000 0x100000>;
141 compatible = "fsl,spba-bus", "simple-bus";
142 #address-cells = <1>;
144 reg = <0x02000000 0x40000>;
148 reg = <0x02004000 0x4000>;
149 interrupts = <0 52 0x04>;
152 ecspi@02008000 { /* eCSPI1 */
153 #address-cells = <1>;
155 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
156 reg = <0x02008000 0x4000>;
157 interrupts = <0 31 0x04>;
158 clocks = <&clks 112>, <&clks 112>;
159 clock-names = "ipg", "per";
163 ecspi@0200c000 { /* eCSPI2 */
164 #address-cells = <1>;
166 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
167 reg = <0x0200c000 0x4000>;
168 interrupts = <0 32 0x04>;
169 clocks = <&clks 113>, <&clks 113>;
170 clock-names = "ipg", "per";
174 ecspi@02010000 { /* eCSPI3 */
175 #address-cells = <1>;
177 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02010000 0x4000>;
179 interrupts = <0 33 0x04>;
180 clocks = <&clks 114>, <&clks 114>;
181 clock-names = "ipg", "per";
185 ecspi@02014000 { /* eCSPI4 */
186 #address-cells = <1>;
188 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
189 reg = <0x02014000 0x4000>;
190 interrupts = <0 34 0x04>;
191 clocks = <&clks 115>, <&clks 115>;
192 clock-names = "ipg", "per";
196 ecspi@02018000 { /* eCSPI5 */
197 #address-cells = <1>;
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02018000 0x4000>;
201 interrupts = <0 35 0x04>;
202 clocks = <&clks 116>, <&clks 116>;
203 clock-names = "ipg", "per";
207 uart1: serial@02020000 {
208 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
209 reg = <0x02020000 0x4000>;
210 interrupts = <0 26 0x04>;
211 clocks = <&clks 160>, <&clks 161>;
212 clock-names = "ipg", "per";
217 reg = <0x02024000 0x4000>;
218 interrupts = <0 51 0x04>;
222 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
223 reg = <0x02028000 0x4000>;
224 interrupts = <0 46 0x04>;
225 clocks = <&clks 178>;
226 fsl,fifo-depth = <15>;
227 fsl,ssi-dma-events = <38 37>;
232 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
233 reg = <0x0202c000 0x4000>;
234 interrupts = <0 47 0x04>;
235 clocks = <&clks 179>;
236 fsl,fifo-depth = <15>;
237 fsl,ssi-dma-events = <42 41>;
242 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
243 reg = <0x02030000 0x4000>;
244 interrupts = <0 48 0x04>;
245 clocks = <&clks 180>;
246 fsl,fifo-depth = <15>;
247 fsl,ssi-dma-events = <46 45>;
252 reg = <0x02034000 0x4000>;
253 interrupts = <0 50 0x04>;
257 reg = <0x0203c000 0x4000>;
262 reg = <0x02040000 0x3c000>;
263 interrupts = <0 3 0x04 0 12 0x04>;
266 aipstz@0207c000 { /* AIPSTZ1 */
267 reg = <0x0207c000 0x4000>;
270 pwm@02080000 { /* PWM1 */
272 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
273 reg = <0x02080000 0x4000>;
274 interrupts = <0 83 0x04>;
275 clocks = <&clks 62>, <&clks 145>;
276 clock-names = "ipg", "per";
279 pwm@02084000 { /* PWM2 */
281 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
282 reg = <0x02084000 0x4000>;
283 interrupts = <0 84 0x04>;
284 clocks = <&clks 62>, <&clks 146>;
285 clock-names = "ipg", "per";
288 pwm@02088000 { /* PWM3 */
290 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
291 reg = <0x02088000 0x4000>;
292 interrupts = <0 85 0x04>;
293 clocks = <&clks 62>, <&clks 147>;
294 clock-names = "ipg", "per";
297 pwm@0208c000 { /* PWM4 */
299 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
300 reg = <0x0208c000 0x4000>;
301 interrupts = <0 86 0x04>;
302 clocks = <&clks 62>, <&clks 148>;
303 clock-names = "ipg", "per";
306 flexcan@02090000 { /* CAN1 */
307 reg = <0x02090000 0x4000>;
308 interrupts = <0 110 0x04>;
311 flexcan@02094000 { /* CAN2 */
312 reg = <0x02094000 0x4000>;
313 interrupts = <0 111 0x04>;
317 compatible = "fsl,imx6q-gpt";
318 reg = <0x02098000 0x4000>;
319 interrupts = <0 55 0x04>;
322 gpio1: gpio@0209c000 {
323 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
324 reg = <0x0209c000 0x4000>;
325 interrupts = <0 66 0x04 0 67 0x04>;
328 interrupt-controller;
329 #interrupt-cells = <2>;
332 gpio2: gpio@020a0000 {
333 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
334 reg = <0x020a0000 0x4000>;
335 interrupts = <0 68 0x04 0 69 0x04>;
338 interrupt-controller;
339 #interrupt-cells = <2>;
342 gpio3: gpio@020a4000 {
343 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
344 reg = <0x020a4000 0x4000>;
345 interrupts = <0 70 0x04 0 71 0x04>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
352 gpio4: gpio@020a8000 {
353 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
354 reg = <0x020a8000 0x4000>;
355 interrupts = <0 72 0x04 0 73 0x04>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
362 gpio5: gpio@020ac000 {
363 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
364 reg = <0x020ac000 0x4000>;
365 interrupts = <0 74 0x04 0 75 0x04>;
368 interrupt-controller;
369 #interrupt-cells = <2>;
372 gpio6: gpio@020b0000 {
373 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
374 reg = <0x020b0000 0x4000>;
375 interrupts = <0 76 0x04 0 77 0x04>;
378 interrupt-controller;
379 #interrupt-cells = <2>;
382 gpio7: gpio@020b4000 {
383 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
384 reg = <0x020b4000 0x4000>;
385 interrupts = <0 78 0x04 0 79 0x04>;
388 interrupt-controller;
389 #interrupt-cells = <2>;
393 reg = <0x020b8000 0x4000>;
394 interrupts = <0 82 0x04>;
397 wdog@020bc000 { /* WDOG1 */
398 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
399 reg = <0x020bc000 0x4000>;
400 interrupts = <0 80 0x04>;
404 wdog@020c0000 { /* WDOG2 */
405 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
406 reg = <0x020c0000 0x4000>;
407 interrupts = <0 81 0x04>;
413 compatible = "fsl,imx6q-ccm";
414 reg = <0x020c4000 0x4000>;
415 interrupts = <0 87 0x04 0 88 0x04>;
419 anatop: anatop@020c8000 {
420 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
421 reg = <0x020c8000 0x1000>;
422 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
425 compatible = "fsl,anatop-regulator";
426 regulator-name = "vdd1p1";
427 regulator-min-microvolt = <800000>;
428 regulator-max-microvolt = <1375000>;
430 anatop-reg-offset = <0x110>;
431 anatop-vol-bit-shift = <8>;
432 anatop-vol-bit-width = <5>;
433 anatop-min-bit-val = <4>;
434 anatop-min-voltage = <800000>;
435 anatop-max-voltage = <1375000>;
439 compatible = "fsl,anatop-regulator";
440 regulator-name = "vdd3p0";
441 regulator-min-microvolt = <2800000>;
442 regulator-max-microvolt = <3150000>;
444 anatop-reg-offset = <0x120>;
445 anatop-vol-bit-shift = <8>;
446 anatop-vol-bit-width = <5>;
447 anatop-min-bit-val = <0>;
448 anatop-min-voltage = <2625000>;
449 anatop-max-voltage = <3400000>;
453 compatible = "fsl,anatop-regulator";
454 regulator-name = "vdd2p5";
455 regulator-min-microvolt = <2000000>;
456 regulator-max-microvolt = <2750000>;
458 anatop-reg-offset = <0x130>;
459 anatop-vol-bit-shift = <8>;
460 anatop-vol-bit-width = <5>;
461 anatop-min-bit-val = <0>;
462 anatop-min-voltage = <2000000>;
463 anatop-max-voltage = <2750000>;
466 regulator-vddcore@140 {
467 compatible = "fsl,anatop-regulator";
468 regulator-name = "cpu";
469 regulator-min-microvolt = <725000>;
470 regulator-max-microvolt = <1450000>;
472 anatop-reg-offset = <0x140>;
473 anatop-vol-bit-shift = <0>;
474 anatop-vol-bit-width = <5>;
475 anatop-min-bit-val = <1>;
476 anatop-min-voltage = <725000>;
477 anatop-max-voltage = <1450000>;
480 regulator-vddpu@140 {
481 compatible = "fsl,anatop-regulator";
482 regulator-name = "vddpu";
483 regulator-min-microvolt = <725000>;
484 regulator-max-microvolt = <1450000>;
486 anatop-reg-offset = <0x140>;
487 anatop-vol-bit-shift = <9>;
488 anatop-vol-bit-width = <5>;
489 anatop-min-bit-val = <1>;
490 anatop-min-voltage = <725000>;
491 anatop-max-voltage = <1450000>;
494 regulator-vddsoc@140 {
495 compatible = "fsl,anatop-regulator";
496 regulator-name = "vddsoc";
497 regulator-min-microvolt = <725000>;
498 regulator-max-microvolt = <1450000>;
500 anatop-reg-offset = <0x140>;
501 anatop-vol-bit-shift = <18>;
502 anatop-vol-bit-width = <5>;
503 anatop-min-bit-val = <1>;
504 anatop-min-voltage = <725000>;
505 anatop-max-voltage = <1450000>;
509 usbphy1: usbphy@020c9000 {
510 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
511 reg = <0x020c9000 0x1000>;
512 interrupts = <0 44 0x04>;
513 clocks = <&clks 182>;
516 usbphy2: usbphy@020ca000 {
517 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
518 reg = <0x020ca000 0x1000>;
519 interrupts = <0 45 0x04>;
520 clocks = <&clks 183>;
524 reg = <0x020cc000 0x4000>;
525 interrupts = <0 19 0x04 0 20 0x04>;
528 epit@020d0000 { /* EPIT1 */
529 reg = <0x020d0000 0x4000>;
530 interrupts = <0 56 0x04>;
533 epit@020d4000 { /* EPIT2 */
534 reg = <0x020d4000 0x4000>;
535 interrupts = <0 57 0x04>;
539 compatible = "fsl,imx6q-src";
540 reg = <0x020d8000 0x4000>;
541 interrupts = <0 91 0x04 0 96 0x04>;
545 compatible = "fsl,imx6q-gpc";
546 reg = <0x020dc000 0x4000>;
547 interrupts = <0 89 0x04 0 90 0x04>;
550 gpr: iomuxc-gpr@020e0000 {
551 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
552 reg = <0x020e0000 0x38>;
556 compatible = "fsl,imx6q-iomuxc";
557 reg = <0x020e0000 0x4000>;
559 /* shared pinctrl settings */
561 pinctrl_audmux_1: audmux-1 {
563 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
564 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
565 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
566 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
572 pinctrl_ecspi1_1: ecspi1grp-1 {
574 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
575 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
576 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
582 pinctrl_enet_1: enetgrp-1 {
584 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
585 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
586 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
587 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
588 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
589 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
590 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
591 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
592 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
593 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
594 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
595 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
596 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
597 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
598 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
602 pinctrl_enet_2: enetgrp-2 {
604 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
605 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
606 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
607 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
608 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
609 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
610 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
611 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
612 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
613 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
614 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
615 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
616 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
617 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
618 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
624 pinctrl_gpmi_nand_1: gpmi-nand-1 {
626 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
627 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
628 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
629 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
630 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
631 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
632 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
633 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
634 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
635 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
636 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
637 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
638 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
639 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
640 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
641 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
642 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
643 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
644 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
650 pinctrl_i2c1_1: i2c1grp-1 {
652 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
653 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
659 pinctrl_uart1_1: uart1grp-1 {
661 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
662 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
668 pinctrl_uart2_1: uart2grp-1 {
670 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
671 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
677 pinctrl_uart4_1: uart4grp-1 {
679 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
680 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
686 pinctrl_usbotg_1: usbotggrp-1 {
688 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
694 pinctrl_usdhc2_1: usdhc2grp-1 {
696 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
697 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
698 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
699 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
700 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
701 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
702 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
703 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
704 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
705 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
711 pinctrl_usdhc3_1: usdhc3grp-1 {
713 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
714 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
715 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
716 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
717 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
718 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
719 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
720 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
721 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
722 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
726 pinctrl_usdhc3_2: usdhc3grp-2 {
728 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
729 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
730 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
731 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
732 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
733 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
739 pinctrl_usdhc4_1: usdhc4grp-1 {
741 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
742 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
743 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
744 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
745 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
746 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
747 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
748 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
749 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
750 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
754 pinctrl_usdhc4_2: usdhc4grp-2 {
756 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
757 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
758 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
759 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
760 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
761 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
767 dcic@020e4000 { /* DCIC1 */
768 reg = <0x020e4000 0x4000>;
769 interrupts = <0 124 0x04>;
772 dcic@020e8000 { /* DCIC2 */
773 reg = <0x020e8000 0x4000>;
774 interrupts = <0 125 0x04>;
778 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
779 reg = <0x020ec000 0x4000>;
780 interrupts = <0 2 0x04>;
781 clocks = <&clks 155>, <&clks 155>;
782 clock-names = "ipg", "ahb";
783 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
787 aips-bus@02100000 { /* AIPS2 */
788 compatible = "fsl,aips-bus", "simple-bus";
789 #address-cells = <1>;
791 reg = <0x02100000 0x100000>;
795 reg = <0x02100000 0x40000>;
796 interrupts = <0 105 0x04 0 106 0x04>;
799 aipstz@0217c000 { /* AIPSTZ2 */
800 reg = <0x0217c000 0x4000>;
803 usb@02184000 { /* USB OTG */
804 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
805 reg = <0x02184000 0x200>;
806 interrupts = <0 43 0x04>;
807 clocks = <&clks 162>;
808 fsl,usbphy = <&usbphy1>;
809 fsl,usbmisc = <&usbmisc 0>;
813 usb@02184200 { /* USB1 */
814 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
815 reg = <0x02184200 0x200>;
816 interrupts = <0 40 0x04>;
817 clocks = <&clks 162>;
818 fsl,usbphy = <&usbphy2>;
819 fsl,usbmisc = <&usbmisc 1>;
823 usb@02184400 { /* USB2 */
824 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
825 reg = <0x02184400 0x200>;
826 interrupts = <0 41 0x04>;
827 clocks = <&clks 162>;
828 fsl,usbmisc = <&usbmisc 2>;
832 usb@02184600 { /* USB3 */
833 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
834 reg = <0x02184600 0x200>;
835 interrupts = <0 42 0x04>;
836 clocks = <&clks 162>;
837 fsl,usbmisc = <&usbmisc 3>;
841 usbmisc: usbmisc@02184800 {
843 compatible = "fsl,imx6q-usbmisc";
844 reg = <0x02184800 0x200>;
845 clocks = <&clks 162>;
849 compatible = "fsl,imx6q-fec";
850 reg = <0x02188000 0x4000>;
851 interrupts = <0 118 0x04 0 119 0x04>;
852 clocks = <&clks 117>, <&clks 117>;
853 clock-names = "ipg", "ahb";
858 reg = <0x0218c000 0x4000>;
859 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
862 usdhc@02190000 { /* uSDHC1 */
863 compatible = "fsl,imx6q-usdhc";
864 reg = <0x02190000 0x4000>;
865 interrupts = <0 22 0x04>;
866 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
867 clock-names = "ipg", "ahb", "per";
871 usdhc@02194000 { /* uSDHC2 */
872 compatible = "fsl,imx6q-usdhc";
873 reg = <0x02194000 0x4000>;
874 interrupts = <0 23 0x04>;
875 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
876 clock-names = "ipg", "ahb", "per";
880 usdhc@02198000 { /* uSDHC3 */
881 compatible = "fsl,imx6q-usdhc";
882 reg = <0x02198000 0x4000>;
883 interrupts = <0 24 0x04>;
884 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
885 clock-names = "ipg", "ahb", "per";
889 usdhc@0219c000 { /* uSDHC4 */
890 compatible = "fsl,imx6q-usdhc";
891 reg = <0x0219c000 0x4000>;
892 interrupts = <0 25 0x04>;
893 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
894 clock-names = "ipg", "ahb", "per";
898 i2c@021a0000 { /* I2C1 */
899 #address-cells = <1>;
901 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
902 reg = <0x021a0000 0x4000>;
903 interrupts = <0 36 0x04>;
904 clocks = <&clks 125>;
908 i2c@021a4000 { /* I2C2 */
909 #address-cells = <1>;
911 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
912 reg = <0x021a4000 0x4000>;
913 interrupts = <0 37 0x04>;
914 clocks = <&clks 126>;
918 i2c@021a8000 { /* I2C3 */
919 #address-cells = <1>;
921 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
922 reg = <0x021a8000 0x4000>;
923 interrupts = <0 38 0x04>;
924 clocks = <&clks 127>;
929 reg = <0x021ac000 0x4000>;
932 mmdc@021b0000 { /* MMDC0 */
933 compatible = "fsl,imx6q-mmdc";
934 reg = <0x021b0000 0x4000>;
937 mmdc@021b4000 { /* MMDC1 */
938 reg = <0x021b4000 0x4000>;
942 reg = <0x021b8000 0x4000>;
943 interrupts = <0 14 0x04>;
947 reg = <0x021bc000 0x4000>;
951 reg = <0x021c0000 0x4000>;
952 interrupts = <0 21 0x04>;
955 tzasc@021d0000 { /* TZASC1 */
956 reg = <0x021d0000 0x4000>;
957 interrupts = <0 108 0x04>;
960 tzasc@021d4000 { /* TZASC2 */
961 reg = <0x021d4000 0x4000>;
962 interrupts = <0 109 0x04>;
966 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
967 reg = <0x021d8000 0x4000>;
971 mipi@021dc000 { /* MIPI-CSI */
972 reg = <0x021dc000 0x4000>;
975 mipi@021e0000 { /* MIPI-DSI */
976 reg = <0x021e0000 0x4000>;
980 reg = <0x021e4000 0x4000>;
981 interrupts = <0 18 0x04>;
984 uart2: serial@021e8000 {
985 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
986 reg = <0x021e8000 0x4000>;
987 interrupts = <0 27 0x04>;
988 clocks = <&clks 160>, <&clks 161>;
989 clock-names = "ipg", "per";
993 uart3: serial@021ec000 {
994 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
995 reg = <0x021ec000 0x4000>;
996 interrupts = <0 28 0x04>;
997 clocks = <&clks 160>, <&clks 161>;
998 clock-names = "ipg", "per";
1002 uart4: serial@021f0000 {
1003 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1004 reg = <0x021f0000 0x4000>;
1005 interrupts = <0 29 0x04>;
1006 clocks = <&clks 160>, <&clks 161>;
1007 clock-names = "ipg", "per";
1008 status = "disabled";
1011 uart5: serial@021f4000 {
1012 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1013 reg = <0x021f4000 0x4000>;
1014 interrupts = <0 30 0x04>;
1015 clocks = <&clks 160>, <&clks 161>;
1016 clock-names = "ipg", "per";
1017 status = "disabled";
1021 ipu1: ipu@02400000 {
1023 compatible = "fsl,imx6q-ipu";
1024 reg = <0x02400000 0x400000>;
1025 interrupts = <0 6 0x4 0 5 0x4>;
1026 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1027 clock-names = "bus", "di0", "di1";
1030 ipu2: ipu@02800000 {
1032 compatible = "fsl,imx6q-ipu";
1033 reg = <0x02800000 0x400000>;
1034 interrupts = <0 8 0x4 0 7 0x4>;
1035 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
1036 clock-names = "bus", "di0", "di1";