1 /* arch/arm/mach-zynq/include/mach/zynq_soc.h
3 * Copyright (C) 2011 Xilinx
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef __MACH_XILINX_SOC_H__
16 #define __MACH_XILINX_SOC_H__
18 #include <asm/pgtable.h>
20 #define PERIPHERAL_CLOCK_RATE 2500000
22 /* Static peripheral mappings are mapped at the top of the vmalloc region. The
23 * early uart mapping causes intermediate problems/failure at certain
24 * addresses, including the very top of the vmalloc region. Map it at an
25 * address that is known to work.
27 #define UART0_PHYS 0xE0000000
28 #define UART0_SIZE SZ_4K
29 #define UART0_VIRT 0xF0001000
31 #define TTC0_PHYS 0xF8001000
32 #define TTC0_SIZE SZ_4K
33 #define TTC0_VIRT (VMALLOC_END - TTC0_SIZE)
35 #define SCU_PERIPH_PHYS 0xF8F00000
36 #define SCU_PERIPH_SIZE SZ_8K
37 #define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE)
39 /* The following are intended for the devices that are mapped early */
41 #define TTC0_BASE IOMEM(TTC0_VIRT)
42 #define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
44 #define LL_UART_PADDR UART0_PHYS
45 #define LL_UART_VADDR UART0_VIRT