arch/arm/mach-omap2/omap_twl.c

   1 /**
   2  * OMAP and TWL PMIC specific intializations.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated.
   5  * Thara Gopinath
   6  * Copyright (C) 2009 Texas Instruments Incorporated.
   7  * Nishanth Menon
   8  * Copyright (C) 2009 Nokia Corporation
   9  * Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/i2c/twl.h>
  20
  21 #include "soc.h"
  22 #include "voltage.h"
  23
  24 #include "pm.h"
  25
  26 #define OMAP3_SRI2C_SLAVE_ADDR          0x12
  27 #define OMAP3_VDD_MPU_SR_CONTROL_REG    0x00
  28 #define OMAP3_VDD_CORE_SR_CONTROL_REG   0x01
  29 #define OMAP3_VP_CONFIG_ERROROFFSET     0x00
  30 #define OMAP3_VP_VSTEPMIN_VSTEPMIN      0x1
  31 #define OMAP3_VP_VSTEPMAX_VSTEPMAX      0x04
  32 #define OMAP3_VP_VLIMITTO_TIMEOUT_US    200
  33
  34 #define OMAP3430_VP1_VLIMITTO_VDDMIN    0x14
  35 #define OMAP3430_VP1_VLIMITTO_VDDMAX    0x42
  36 #define OMAP3430_VP2_VLIMITTO_VDDMIN    0x18
  37 #define OMAP3430_VP2_VLIMITTO_VDDMAX    0x2c
  38
  39 #define OMAP3630_VP1_VLIMITTO_VDDMIN    0x18
  40 #define OMAP3630_VP1_VLIMITTO_VDDMAX    0x3c
  41 #define OMAP3630_VP2_VLIMITTO_VDDMIN    0x18
  42 #define OMAP3630_VP2_VLIMITTO_VDDMAX    0x30
  43
  44 #define OMAP4_SRI2C_SLAVE_ADDR          0x12
  45 #define OMAP4_VDD_MPU_SR_VOLT_REG       0x55
  46 #define OMAP4_VDD_MPU_SR_CMD_REG        0x56
  47 #define OMAP4_VDD_IVA_SR_VOLT_REG       0x5B
  48 #define OMAP4_VDD_IVA_SR_CMD_REG        0x5C
  49 #define OMAP4_VDD_CORE_SR_VOLT_REG      0x61
  50 #define OMAP4_VDD_CORE_SR_CMD_REG       0x62
  51
  52 #define OMAP4_VP_CONFIG_ERROROFFSET     0x00
  53 #define OMAP4_VP_VSTEPMIN_VSTEPMIN      0x01
  54 #define OMAP4_VP_VSTEPMAX_VSTEPMAX      0x04
  55 #define OMAP4_VP_VLIMITTO_TIMEOUT_US    200
  56
  57 #define OMAP4_VP_MPU_VLIMITTO_VDDMIN    0xA
  58 #define OMAP4_VP_MPU_VLIMITTO_VDDMAX    0x39
  59 #define OMAP4_VP_IVA_VLIMITTO_VDDMIN    0xA
  60 #define OMAP4_VP_IVA_VLIMITTO_VDDMAX    0x2D
  61 #define OMAP4_VP_CORE_VLIMITTO_VDDMIN   0xA
  62 #define OMAP4_VP_CORE_VLIMITTO_VDDMAX   0x28
  63
  64 static bool is_offset_valid;
  65 static u8 smps_offset;
  66 /*
  67  * Flag to ensure Smartreflex bit in TWL
  68  * being cleared in board file is not overwritten.
  69  */
  70 static bool __initdata twl_sr_enable_autoinit;
  71
  72 #define TWL4030_DCDC_GLOBAL_CFG        0x06
  73 #define REG_SMPS_OFFSET         0xE0
  74 #define SMARTREFLEX_ENABLE     BIT(3)
  75
  76 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
  77 {
  78         return (((vsel * 125) + 6000)) * 100;
  79 }
  80
  81 static u8 twl4030_uv_to_vsel(unsigned long uv)
  82 {
  83         return DIV_ROUND_UP(uv - 600000, 12500);
  84 }
  85
  86 static unsigned long twl6030_vsel_to_uv(const u8 vsel)
  87 {
  88         /*
  89          * In TWL6030 depending on the value of SMPS_OFFSET
  90          * efuse register the voltage range supported in
  91          * standard mode can be either between 0.6V - 1.3V or
  92          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
  93          * is programmed to all 0's where as starting from
  94          * TWL6030 ES1.1 the efuse is programmed to 1
  95          */
  96         if (!is_offset_valid) {
  97                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
  98                                 REG_SMPS_OFFSET);
  99                 is_offset_valid = true;
 100         }
 101
 102         if (!vsel)
 103                 return 0;
 104         /*
 105          * There is no specific formula for voltage to vsel
 106          * conversion above 1.3V. There are special hardcoded
 107          * values for voltages above 1.3V. Currently we are
 108          * hardcoding only for 1.35 V which is used for 1GH OPP for
 109          * OMAP4430.
 110          */
 111         if (vsel == 0x3A)
 112                 return 1350000;
 113
 114         if (smps_offset & 0x8)
 115                 return ((((vsel - 1) * 1266) + 70900)) * 10;
 116         else
 117                 return ((((vsel - 1) * 1266) + 60770)) * 10;
 118 }
 119
 120 static u8 twl6030_uv_to_vsel(unsigned long uv)
 121 {
 122         /*
 123          * In TWL6030 depending on the value of SMPS_OFFSET
 124          * efuse register the voltage range supported in
 125          * standard mode can be either between 0.6V - 1.3V or
 126          * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
 127          * is programmed to all 0's where as starting from
 128          * TWL6030 ES1.1 the efuse is programmed to 1
 129          */
 130         if (!is_offset_valid) {
 131                 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
 132                                 REG_SMPS_OFFSET);
 133                 is_offset_valid = true;
 134         }
 135
 136         if (!uv)
 137                 return 0x00;
 138         /*
 139          * There is no specific formula for voltage to vsel
 140          * conversion above 1.3V. There are special hardcoded
 141          * values for voltages above 1.3V. Currently we are
 142          * hardcoding only for 1.35 V which is used for 1GH OPP for
 143          * OMAP4430.
 144          */
 145         if (uv > twl6030_vsel_to_uv(0x39)) {
 146                 if (uv == 1350000)
 147                         return 0x3A;
 148                 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
 149                         __func__, uv, twl6030_vsel_to_uv(0x39));
 150                 return 0x3A;
 151         }
 152
 153         if (smps_offset & 0x8)
 154                 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
 155         else
 156                 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
 157 }
 158
 159 static struct omap_voltdm_pmic omap3_mpu_pmic = {
 160         .slew_rate              = 4000,
 161         .step_size              = 12500,
 162         .on_volt                = 1200000,
 163         .onlp_volt              = 1000000,
 164         .ret_volt               = 975000,
 165         .off_volt               = 600000,
 166         .volt_setup_time        = 0xfff,
 167         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 168         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 169         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 170         .vp_vddmin              = OMAP3430_VP1_VLIMITTO_VDDMIN,
 171         .vp_vddmax              = OMAP3430_VP1_VLIMITTO_VDDMAX,
 172         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 173         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 174         .volt_reg_addr          = OMAP3_VDD_MPU_SR_CONTROL_REG,
 175         .i2c_high_speed         = true,
 176         .vsel_to_uv             = twl4030_vsel_to_uv,
 177         .uv_to_vsel             = twl4030_uv_to_vsel,
 178 };
 179
 180 static struct omap_voltdm_pmic omap3_core_pmic = {
 181         .slew_rate              = 4000,
 182         .step_size              = 12500,
 183         .on_volt                = 1200000,
 184         .onlp_volt              = 1000000,
 185         .ret_volt               = 975000,
 186         .off_volt               = 600000,
 187         .volt_setup_time        = 0xfff,
 188         .vp_erroroffset         = OMAP3_VP_CONFIG_ERROROFFSET,
 189         .vp_vstepmin            = OMAP3_VP_VSTEPMIN_VSTEPMIN,
 190         .vp_vstepmax            = OMAP3_VP_VSTEPMAX_VSTEPMAX,
 191         .vp_vddmin              = OMAP3430_VP2_VLIMITTO_VDDMIN,
 192         .vp_vddmax              = OMAP3430_VP2_VLIMITTO_VDDMAX,
 193         .vp_timeout_us          = OMAP3_VP_VLIMITTO_TIMEOUT_US,
 194         .i2c_slave_addr         = OMAP3_SRI2C_SLAVE_ADDR,
 195         .volt_reg_addr          = OMAP3_VDD_CORE_SR_CONTROL_REG,
 196         .i2c_high_speed         = true,
 197         .vsel_to_uv             = twl4030_vsel_to_uv,
 198         .uv_to_vsel             = twl4030_uv_to_vsel,
 199 };
 200
 201 static struct omap_voltdm_pmic omap4_mpu_pmic = {
 202         .slew_rate              = 4000,
 203         .step_size              = 12660,
 204         .on_volt                = 1375000,
 205         .onlp_volt              = 1375000,
 206         .ret_volt               = 830000,
 207         .off_volt               = 0,
 208         .volt_setup_time        = 0,
 209         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 210         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 211         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 212         .vp_vddmin              = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
 213         .vp_vddmax              = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
 214         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 215         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 216         .volt_reg_addr          = OMAP4_VDD_MPU_SR_VOLT_REG,
 217         .cmd_reg_addr           = OMAP4_VDD_MPU_SR_CMD_REG,
 218         .i2c_high_speed         = true,
 219         .vsel_to_uv             = twl6030_vsel_to_uv,
 220         .uv_to_vsel             = twl6030_uv_to_vsel,
 221 };
 222
 223 static struct omap_voltdm_pmic omap4_iva_pmic = {
 224         .slew_rate              = 4000,
 225         .step_size              = 12660,
 226         .on_volt                = 1188000,
 227         .onlp_volt              = 1188000,
 228         .ret_volt               = 830000,
 229         .off_volt               = 0,
 230         .volt_setup_time        = 0,
 231         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 232         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 233         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 234         .vp_vddmin              = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
 235         .vp_vddmax              = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
 236         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 237         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 238         .volt_reg_addr          = OMAP4_VDD_IVA_SR_VOLT_REG,
 239         .cmd_reg_addr           = OMAP4_VDD_IVA_SR_CMD_REG,
 240         .i2c_high_speed         = true,
 241         .vsel_to_uv             = twl6030_vsel_to_uv,
 242         .uv_to_vsel             = twl6030_uv_to_vsel,
 243 };
 244
 245 static struct omap_voltdm_pmic omap4_core_pmic = {
 246         .slew_rate              = 4000,
 247         .step_size              = 12660,
 248         .on_volt                = 1200000,
 249         .onlp_volt              = 1200000,
 250         .ret_volt               = 830000,
 251         .off_volt               = 0,
 252         .volt_setup_time        = 0,
 253         .vp_erroroffset         = OMAP4_VP_CONFIG_ERROROFFSET,
 254         .vp_vstepmin            = OMAP4_VP_VSTEPMIN_VSTEPMIN,
 255         .vp_vstepmax            = OMAP4_VP_VSTEPMAX_VSTEPMAX,
 256         .vp_vddmin              = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
 257         .vp_vddmax              = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
 258         .vp_timeout_us          = OMAP4_VP_VLIMITTO_TIMEOUT_US,
 259         .i2c_slave_addr         = OMAP4_SRI2C_SLAVE_ADDR,
 260         .volt_reg_addr          = OMAP4_VDD_CORE_SR_VOLT_REG,
 261         .cmd_reg_addr           = OMAP4_VDD_CORE_SR_CMD_REG,
 262         .vsel_to_uv             = twl6030_vsel_to_uv,
 263         .uv_to_vsel             = twl6030_uv_to_vsel,
 264 };
 265
 266 int __init omap4_twl_init(void)
 267 {
 268         struct voltagedomain *voltdm;
 269
 270         if (!cpu_is_omap44xx())
 271                 return -ENODEV;
 272
 273         voltdm = voltdm_lookup("mpu");
 274         omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
 275
 276         voltdm = voltdm_lookup("iva");
 277         omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
 278
 279         voltdm = voltdm_lookup("core");
 280         omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
 281
 282         return 0;
 283 }
 284
 285 int __init omap3_twl_init(void)
 286 {
 287         struct voltagedomain *voltdm;
 288
 289         if (!cpu_is_omap34xx())
 290                 return -ENODEV;
 291
 292         if (cpu_is_omap3630()) {
 293                 omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
 294                 omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
 295                 omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
 296                 omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
 297         }
 298
 299         /*
 300          * The smartreflex bit on twl4030 specifies if the setting of voltage
 301          * is done over the I2C_SR path. Since this setting is independent of
 302          * the actual usage of smartreflex AVS module, we enable TWL SR bit
 303          * by default irrespective of whether smartreflex AVS module is enabled
 304          * on the OMAP side or not. This is because without this bit enabled,
 305          * the voltage scaling through vp forceupdate/bypass mechanism of
 306          * voltage scaling will not function on TWL over I2C_SR.
 307          */
 308         if (!twl_sr_enable_autoinit)
 309                 omap3_twl_set_sr_bit(true);
 310
 311         voltdm = voltdm_lookup("mpu_iva");
 312         omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
 313
 314         voltdm = voltdm_lookup("core");
 315         omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
 316
 317         return 0;
 318 }
 319
 320 /**
 321  * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
 322  * @enable: enable SR mode in twl or not
 323  *
 324  * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
 325  * voltage scaling through OMAP SR works. Else, the smartreflex bit
 326  * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
 327  * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
 328  * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
 329  * in those scenarios this bit is to be cleared (enable = false).
 330  *
 331  * Returns 0 on success, error is returned if I2C read/write fails.
 332  */
 333 int __init omap3_twl_set_sr_bit(bool enable)
 334 {
 335         u8 temp;
 336         int ret;
 337         if (twl_sr_enable_autoinit)
 338                 pr_warning("%s: unexpected multiple calls\n", __func__);
 339
 340         ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
 341                                         TWL4030_DCDC_GLOBAL_CFG);
 342         if (ret)
 343                 goto err;
 344
 345         if (enable)
 346                 temp |= SMARTREFLEX_ENABLE;
 347         else
 348                 temp &= ~SMARTREFLEX_ENABLE;
 349
 350         ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
 351                                 TWL4030_DCDC_GLOBAL_CFG);
 352         if (!ret) {
 353                 twl_sr_enable_autoinit = true;
 354                 return 0;
 355         }
 356 err:
 357         pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
 358         return ret;
 359 }