arch/arm/boot/dts/zynq-ep107.dts

   1 /*
   2  *  Copyright (C) 2011 Xilinx
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /dts-v1/;
  15 / {
  16         model = "Xilinx Zynq EP107";
  17         compatible = "xlnx,zynq-ep107";
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20         interrupt-parent = <&intc>;
  21
  22         memory {
  23                 device_type = "memory";
  24                 reg = <0x0 0x10000000>;
  25         };
  26
  27         chosen {
  28                 bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
  29                 linux,stdout-path = &uart0;
  30         };
  31
  32         amba {
  33                 compatible = "simple-bus";
  34                 #address-cells = <1>;
  35                 #size-cells = <1>;
  36                 ranges;
  37
  38                 intc: interrupt-controller@f8f01000 {
  39                         compatible = "arm,cortex-a9-gic";
  40                         #interrupt-cells = <3>;
  41                         #address-cells = <1>;
  42                         interrupt-controller;
  43                         reg = <0xF8F01000 0x1000>,
  44                               <0xF8F00100 0x100>;
  45                 };
  46
  47                 L2: cache-controller {
  48                         compatible = "arm,pl310-cache";
  49                         reg = <0xF8F02000 0x1000>;
  50                         arm,data-latency = <2 3 2>;
  51                         arm,tag-latency = <2 3 2>;
  52                         cache-unified;
  53                         cache-level = <2>;
  54                 };
  55
  56                 uart0: uart@e0000000 {
  57                         compatible = "xlnx,xuartps";
  58                         reg = <0xE0000000 0x1000>;
  59                         interrupts = <0 27 4>;
  60                         clock = <50000000>;
  61                 };
  62         };
  63 };