2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
72 compatible = "fsl,imx53-ipu";
73 reg = <0x18000000 0x080000000>;
77 aips@50000000 { /* AIPS1 */
78 compatible = "fsl,aips-bus", "simple-bus";
81 reg = <0x50000000 0x10000000>;
85 compatible = "fsl,spba-bus", "simple-bus";
88 reg = <0x50000000 0x40000>;
91 esdhc@50004000 { /* ESDHC1 */
92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50004000 0x4000>;
95 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
96 clock-names = "ipg", "ahb", "per";
100 esdhc@50008000 { /* ESDHC2 */
101 compatible = "fsl,imx53-esdhc";
102 reg = <0x50008000 0x4000>;
104 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
105 clock-names = "ipg", "ahb", "per";
109 uart3: serial@5000c000 {
110 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
111 reg = <0x5000c000 0x4000>;
113 clocks = <&clks 32>, <&clks 33>;
114 clock-names = "ipg", "per";
118 ecspi@50010000 { /* ECSPI1 */
119 #address-cells = <1>;
121 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
122 reg = <0x50010000 0x4000>;
124 clocks = <&clks 51>, <&clks 52>;
125 clock-names = "ipg", "per";
130 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
131 reg = <0x50014000 0x4000>;
134 fsl,fifo-depth = <15>;
135 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
139 esdhc@50020000 { /* ESDHC3 */
140 compatible = "fsl,imx53-esdhc";
141 reg = <0x50020000 0x4000>;
143 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
144 clock-names = "ipg", "ahb", "per";
148 esdhc@50024000 { /* ESDHC4 */
149 compatible = "fsl,imx53-esdhc";
150 reg = <0x50024000 0x4000>;
152 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
153 clock-names = "ipg", "ahb", "per";
159 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
160 reg = <0x53f80000 0x0200>;
166 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
167 reg = <0x53f80200 0x0200>;
173 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
174 reg = <0x53f80400 0x0200>;
180 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
181 reg = <0x53f80600 0x0200>;
186 gpio1: gpio@53f84000 {
187 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
188 reg = <0x53f84000 0x4000>;
189 interrupts = <50 51>;
192 interrupt-controller;
193 #interrupt-cells = <2>;
196 gpio2: gpio@53f88000 {
197 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
198 reg = <0x53f88000 0x4000>;
199 interrupts = <52 53>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
206 gpio3: gpio@53f8c000 {
207 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
208 reg = <0x53f8c000 0x4000>;
209 interrupts = <54 55>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
216 gpio4: gpio@53f90000 {
217 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
218 reg = <0x53f90000 0x4000>;
219 interrupts = <56 57>;
222 interrupt-controller;
223 #interrupt-cells = <2>;
226 wdog@53f98000 { /* WDOG1 */
227 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
228 reg = <0x53f98000 0x4000>;
233 wdog@53f9c000 { /* WDOG2 */
234 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
235 reg = <0x53f9c000 0x4000>;
242 compatible = "fsl,imx53-iomuxc";
243 reg = <0x53fa8000 0x4000>;
246 pinctrl_audmux_1: audmuxgrp-1 {
248 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
249 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
250 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
251 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
257 pinctrl_fec_1: fecgrp-1 {
259 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
260 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
261 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
262 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
263 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
264 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
265 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
266 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
267 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
268 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
274 pinctrl_ecspi1_1: ecspi1grp-1 {
276 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
277 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
278 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
284 pinctrl_esdhc1_1: esdhc1grp-1 {
286 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
287 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
288 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
289 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
290 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
291 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
295 pinctrl_esdhc1_2: esdhc1grp-2 {
297 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
298 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
299 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
300 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
301 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
302 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
303 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
304 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
305 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
306 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
312 pinctrl_esdhc2_1: esdhc2grp-1 {
314 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
315 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
316 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
317 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
318 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
319 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
325 pinctrl_esdhc3_1: esdhc3grp-1 {
327 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
328 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
329 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
330 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
331 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
332 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
333 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
334 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
335 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
336 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
342 pinctrl_i2c1_1: i2c1grp-1 {
344 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
345 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
351 pinctrl_i2c2_1: i2c2grp-1 {
353 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
354 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
360 pinctrl_uart1_1: uart1grp-1 {
362 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
363 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
367 pinctrl_uart1_2: uart1grp-2 {
369 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
370 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
376 pinctrl_uart2_1: uart2grp-1 {
378 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
379 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
385 pinctrl_uart3_1: uart3grp-1 {
387 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
388 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
389 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
390 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
398 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
399 reg = <0x53fb4000 0x4000>;
400 clocks = <&clks 37>, <&clks 38>;
401 clock-names = "ipg", "per";
407 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
408 reg = <0x53fb8000 0x4000>;
409 clocks = <&clks 39>, <&clks 40>;
410 clock-names = "ipg", "per";
414 uart1: serial@53fbc000 {
415 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
416 reg = <0x53fbc000 0x4000>;
418 clocks = <&clks 28>, <&clks 29>;
419 clock-names = "ipg", "per";
423 uart2: serial@53fc0000 {
424 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
425 reg = <0x53fc0000 0x4000>;
427 clocks = <&clks 30>, <&clks 31>;
428 clock-names = "ipg", "per";
433 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
434 reg = <0x53fc8000 0x4000>;
436 clocks = <&clks 158>, <&clks 157>;
437 clock-names = "ipg", "per";
442 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
443 reg = <0x53fcc000 0x4000>;
445 clocks = <&clks 158>, <&clks 157>;
446 clock-names = "ipg", "per";
451 compatible = "fsl,imx53-ccm";
452 reg = <0x53fd4000 0x4000>;
453 interrupts = <0 71 0x04 0 72 0x04>;
457 gpio5: gpio@53fdc000 {
458 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
459 reg = <0x53fdc000 0x4000>;
460 interrupts = <103 104>;
463 interrupt-controller;
464 #interrupt-cells = <2>;
467 gpio6: gpio@53fe0000 {
468 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
469 reg = <0x53fe0000 0x4000>;
470 interrupts = <105 106>;
473 interrupt-controller;
474 #interrupt-cells = <2>;
477 gpio7: gpio@53fe4000 {
478 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
479 reg = <0x53fe4000 0x4000>;
480 interrupts = <107 108>;
483 interrupt-controller;
484 #interrupt-cells = <2>;
487 i2c@53fec000 { /* I2C3 */
488 #address-cells = <1>;
490 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
491 reg = <0x53fec000 0x4000>;
497 uart4: serial@53ff0000 {
498 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
499 reg = <0x53ff0000 0x4000>;
501 clocks = <&clks 65>, <&clks 66>;
502 clock-names = "ipg", "per";
507 aips@60000000 { /* AIPS2 */
508 compatible = "fsl,aips-bus", "simple-bus";
509 #address-cells = <1>;
511 reg = <0x60000000 0x10000000>;
514 uart5: serial@63f90000 {
515 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
516 reg = <0x63f90000 0x4000>;
518 clocks = <&clks 67>, <&clks 68>;
519 clock-names = "ipg", "per";
523 ecspi@63fac000 { /* ECSPI2 */
524 #address-cells = <1>;
526 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
527 reg = <0x63fac000 0x4000>;
529 clocks = <&clks 53>, <&clks 54>;
530 clock-names = "ipg", "per";
535 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
536 reg = <0x63fb0000 0x4000>;
538 clocks = <&clks 56>, <&clks 56>;
539 clock-names = "ipg", "ahb";
540 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
544 #address-cells = <1>;
546 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
547 reg = <0x63fc0000 0x4000>;
549 clocks = <&clks 55>, <&clks 0>;
550 clock-names = "ipg", "per";
554 i2c@63fc4000 { /* I2C2 */
555 #address-cells = <1>;
557 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
558 reg = <0x63fc4000 0x4000>;
564 i2c@63fc8000 { /* I2C1 */
565 #address-cells = <1>;
567 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
568 reg = <0x63fc8000 0x4000>;
575 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
576 reg = <0x63fcc000 0x4000>;
579 fsl,fifo-depth = <15>;
580 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
585 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
586 reg = <0x63fd0000 0x4000>;
591 compatible = "fsl,imx53-nand";
592 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
599 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
600 reg = <0x63fe8000 0x4000>;
603 fsl,fifo-depth = <15>;
604 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
609 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
610 reg = <0x63fec000 0x4000>;
612 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
613 clock-names = "ipg", "ahb", "ptp";