drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2012 Intel Corporation. All rights reserved.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  28  *  Intel Linux Wireless <ilw@linux.intel.com>
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
  49  *
  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
  79 {
  80 /*
  81  * (for documentation purposes)
  82  * to set power to V_AUX, do:
  83
  84                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  85                         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  86                                                APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  87                                                ~APMG_PS_CTRL_MSK_PWR_SRC);
  88  */
  89
  90         iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  91                                APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  92                                ~APMG_PS_CTRL_MSK_PWR_SRC);
  93 }
  94
  95 /* PCI registers */
  96 #define PCI_CFG_RETRY_TIMEOUT   0x041
  97 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN    0x01
  98 #define PCI_CFG_LINK_CTRL_VAL_L1_EN     0x02
  99
 100 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 101 {
 102         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 103         u16 lctl;
 104
 105         /*
 106          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 107          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 108          * If so (likely), disable L0S, so device moves directly L0->L1;
 109          *    costs negligible amount of power savings.
 110          * If not (unlikely), enable L0S, so there is at least some
 111          *    power savings, even without L1.
 112          */
 113         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 114
 115         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
 116                                 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
 117                 /* L1-ASPM enabled; disable(!) L0S */
 118                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 119                 dev_printk(KERN_INFO, trans->dev,
 120                            "L1 Enabled; Disabling L0S\n");
 121         } else {
 122                 /* L1-ASPM disabled; enable(!) L0S */
 123                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 124                 dev_printk(KERN_INFO, trans->dev,
 125                            "L1 Disabled; Enabling L0S\n");
 126         }
 127         trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
 128 }
 129
 130 /*
 131  * Start up NIC's basic functionality after it has been reset
 132  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 133  * NOTE:  This does not load uCode nor start the embedded processor
 134  */
 135 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 136 {
 137         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 138         int ret = 0;
 139         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 140
 141         /*
 142          * Use "set_bit" below rather than "write", to preserve any hardware
 143          * bits already set by default after reset.
 144          */
 145
 146         /* Disable L0S exit timer (platform NMI Work/Around) */
 147         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 148                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 149
 150         /*
 151          * Disable L0s without affecting L1;
 152          *  don't wait for ICH L0s (ICH bug W/A)
 153          */
 154         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 155                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 156
 157         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 158         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 159
 160         /*
 161          * Enable HAP INTA (interrupt from management bus) to
 162          * wake device's PCI Express link L1a -> L0s
 163          */
 164         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 165                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 166
 167         iwl_pcie_apm_config(trans);
 168
 169         /* Configure analog phase-lock-loop before activating to D0A */
 170         if (trans->cfg->base_params->pll_cfg_val)
 171                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 172                             trans->cfg->base_params->pll_cfg_val);
 173
 174         /*
 175          * Set "initialization complete" bit to move adapter from
 176          * D0U* --> D0A* (powered-up active) state.
 177          */
 178         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 179
 180         /*
 181          * Wait for clock stabilization; once stabilized, access to
 182          * device-internal resources is supported, e.g. iwl_write_prph()
 183          * and accesses to uCode SRAM.
 184          */
 185         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 186                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 187                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 188         if (ret < 0) {
 189                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 190                 goto out;
 191         }
 192
 193         /*
 194          * Enable DMA clock and wait for it to stabilize.
 195          *
 196          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 197          * do not disable clocks.  This preserves any hardware bits already
 198          * set by default in "CLK_CTRL_REG" after reset.
 199          */
 200         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 201         udelay(20);
 202
 203         /* Disable L1-Active */
 204         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 205                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 206
 207         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 208
 209 out:
 210         return ret;
 211 }
 212
 213 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 214 {
 215         int ret = 0;
 216
 217         /* stop device's busmaster DMA activity */
 218         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 219
 220         ret = iwl_poll_bit(trans, CSR_RESET,
 221                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 222                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 223         if (ret)
 224                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 225
 226         IWL_DEBUG_INFO(trans, "stop master\n");
 227
 228         return ret;
 229 }
 230
 231 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 232 {
 233         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 234         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 235
 236         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 237
 238         /* Stop device's DMA activity */
 239         iwl_pcie_apm_stop_master(trans);
 240
 241         /* Reset the entire device */
 242         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 243
 244         udelay(10);
 245
 246         /*
 247          * Clear "initialization complete" bit to move adapter from
 248          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 249          */
 250         iwl_clear_bit(trans, CSR_GP_CNTRL,
 251                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 252 }
 253
 254 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 255 {
 256         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 257         unsigned long flags;
 258
 259         /* nic_init */
 260         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 261         iwl_pcie_apm_init(trans);
 262
 263         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 264         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 265
 266         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 267
 268         iwl_pcie_set_pwr_vmain(trans);
 269
 270         iwl_op_mode_nic_config(trans->op_mode);
 271
 272         /* Allocate the RX queue, or reset if it is already allocated */
 273         iwl_pcie_rx_init(trans);
 274
 275         /* Allocate or reset and init all Tx and Command queues */
 276         if (iwl_pcie_tx_init(trans))
 277                 return -ENOMEM;
 278
 279         if (trans->cfg->base_params->shadow_reg_enable) {
 280                 /* enable shadow regs in HW */
 281                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 282                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 283         }
 284
 285         return 0;
 286 }
 287
 288 #define HW_READY_TIMEOUT (50)
 289
 290 /* Note: returns poll_bit return value, which is >= 0 if success */
 291 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 292 {
 293         int ret;
 294
 295         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 296                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 297
 298         /* See if we got it */
 299         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 300                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 301                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 302                            HW_READY_TIMEOUT);
 303
 304         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 305         return ret;
 306 }
 307
 308 /* Note: returns standard 0/-ERROR code */
 309 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 310 {
 311         int ret;
 312         int t = 0;
 313
 314         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 315
 316         ret = iwl_pcie_set_hw_ready(trans);
 317         /* If the card is ready, exit 0 */
 318         if (ret >= 0)
 319                 return 0;
 320
 321         /* If HW is not ready, prepare the conditions to check again */
 322         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 323                     CSR_HW_IF_CONFIG_REG_PREPARE);
 324
 325         do {
 326                 ret = iwl_pcie_set_hw_ready(trans);
 327                 if (ret >= 0)
 328                         return 0;
 329
 330                 usleep_range(200, 1000);
 331                 t += 200;
 332         } while (t < 150000);
 333
 334         return ret;
 335 }
 336
 337 /*
 338  * ucode
 339  */
 340 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 341                                    dma_addr_t phy_addr, u32 byte_cnt)
 342 {
 343         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 344         int ret;
 345
 346         trans_pcie->ucode_write_complete = false;
 347
 348         iwl_write_direct32(trans,
 349                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 350                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 351
 352         iwl_write_direct32(trans,
 353                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 354                            dst_addr);
 355
 356         iwl_write_direct32(trans,
 357                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 358                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 359
 360         iwl_write_direct32(trans,
 361                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 362                            (iwl_get_dma_hi_addr(phy_addr)
 363                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 364
 365         iwl_write_direct32(trans,
 366                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 367                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 368                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 369                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 370
 371         iwl_write_direct32(trans,
 372                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 373                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 374                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 375                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 376
 377         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 378                                  trans_pcie->ucode_write_complete, 5 * HZ);
 379         if (!ret) {
 380                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 381                 return -ETIMEDOUT;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 388                             const struct fw_desc *section)
 389 {
 390         u8 *v_addr;
 391         dma_addr_t p_addr;
 392         u32 offset;
 393         int ret = 0;
 394
 395         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 396                      section_num);
 397
 398         v_addr = dma_alloc_coherent(trans->dev, PAGE_SIZE, &p_addr, GFP_KERNEL);
 399         if (!v_addr)
 400                 return -ENOMEM;
 401
 402         for (offset = 0; offset < section->len; offset += PAGE_SIZE) {
 403                 u32 copy_size;
 404
 405                 copy_size = min_t(u32, PAGE_SIZE, section->len - offset);
 406
 407                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 408                 ret = iwl_pcie_load_firmware_chunk(trans,
 409                                                    section->offset + offset,
 410                                                    p_addr, copy_size);
 411                 if (ret) {
 412                         IWL_ERR(trans,
 413                                 "Could not load the [%d] uCode section\n",
 414                                 section_num);
 415                         break;
 416                 }
 417         }
 418
 419         dma_free_coherent(trans->dev, PAGE_SIZE, v_addr, p_addr);
 420         return ret;
 421 }
 422
 423 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 424                                 const struct fw_img *image)
 425 {
 426         int i, ret = 0;
 427
 428         for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 429                 if (!image->sec[i].data)
 430                         break;
 431
 432                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 433                 if (ret)
 434                         return ret;
 435         }
 436
 437         /* Remove all resets to allow NIC to operate */
 438         iwl_write32(trans, CSR_RESET, 0);
 439
 440         return 0;
 441 }
 442
 443 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 444                                    const struct fw_img *fw)
 445 {
 446         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 447         int ret;
 448         bool hw_rfkill;
 449
 450         /* This may fail if AMT took ownership of the device */
 451         if (iwl_pcie_prepare_card_hw(trans)) {
 452                 IWL_WARN(trans, "Exit HW not ready\n");
 453                 return -EIO;
 454         }
 455
 456         clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
 457
 458         iwl_enable_rfkill_int(trans);
 459
 460         /* If platform's RF_KILL switch is NOT set to KILL */
 461         hw_rfkill = iwl_is_rfkill_set(trans);
 462         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 463         if (hw_rfkill)
 464                 return -ERFKILL;
 465
 466         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 467
 468         ret = iwl_pcie_nic_init(trans);
 469         if (ret) {
 470                 IWL_ERR(trans, "Unable to init nic\n");
 471                 return ret;
 472         }
 473
 474         /* make sure rfkill handshake bits are cleared */
 475         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 476         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 477                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 478
 479         /* clear (again), then enable host interrupts */
 480         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 481         iwl_enable_interrupts(trans);
 482
 483         /* really make sure rfkill handshake bits are cleared */
 484         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 485         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 486
 487         /* Load the given image to the HW */
 488         return iwl_pcie_load_given_ucode(trans, fw);
 489 }
 490
 491 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 492 {
 493         iwl_pcie_reset_ict(trans);
 494         iwl_pcie_tx_start(trans, scd_addr);
 495 }
 496
 497 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 498 {
 499         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 500         unsigned long flags;
 501
 502         /* tell the device to stop sending interrupts */
 503         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 504         iwl_disable_interrupts(trans);
 505         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 506
 507         /* device going down, Stop using ICT table */
 508         iwl_pcie_disable_ict(trans);
 509
 510         /*
 511          * If a HW restart happens during firmware loading,
 512          * then the firmware loading might call this function
 513          * and later it might be called again due to the
 514          * restart. So don't process again if the device is
 515          * already dead.
 516          */
 517         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
 518                 iwl_pcie_tx_stop(trans);
 519                 iwl_pcie_rx_stop(trans);
 520
 521                 /* Power-down device's busmaster DMA clocks */
 522                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 523                                APMG_CLK_VAL_DMA_CLK_RQT);
 524                 udelay(5);
 525         }
 526
 527         /* Make sure (redundant) we've released our request to stay awake */
 528         iwl_clear_bit(trans, CSR_GP_CNTRL,
 529                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 530
 531         /* Stop the device, and put it in low power state */
 532         iwl_pcie_apm_stop(trans);
 533
 534         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 535          * Clean again the interrupt here
 536          */
 537         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 538         iwl_disable_interrupts(trans);
 539         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 540
 541         iwl_enable_rfkill_int(trans);
 542
 543         /* wait to make sure we flush pending tasklet*/
 544         synchronize_irq(trans_pcie->irq);
 545         tasklet_kill(&trans_pcie->irq_tasklet);
 546
 547         cancel_work_sync(&trans_pcie->rx_replenish);
 548
 549         /* stop and reset the on-board processor */
 550         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 551
 552         /* clear all status bits */
 553         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 554         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 555         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 556         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 557         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 558 }
 559
 560 static void iwl_trans_pcie_wowlan_suspend(struct iwl_trans *trans)
 561 {
 562         /* let the ucode operate on its own */
 563         iwl_write32(trans, CSR_UCODE_DRV_GP1_SET,
 564                     CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE);
 565
 566         iwl_disable_interrupts(trans);
 567         iwl_clear_bit(trans, CSR_GP_CNTRL,
 568                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 569 }
 570
 571 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 572 {
 573         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 574         int err;
 575         bool hw_rfkill;
 576
 577         trans_pcie->inta_mask = CSR_INI_SET_MASK;
 578
 579         if (!trans_pcie->irq_requested) {
 580                 tasklet_init(&trans_pcie->irq_tasklet, (void (*)(unsigned long))
 581                         iwl_pcie_tasklet, (unsigned long)trans);
 582
 583                 iwl_pcie_alloc_ict(trans);
 584
 585                 err = request_irq(trans_pcie->irq, iwl_pcie_isr_ict,
 586                                   IRQF_SHARED, DRV_NAME, trans);
 587                 if (err) {
 588                         IWL_ERR(trans, "Error allocating IRQ %d\n",
 589                                 trans_pcie->irq);
 590                         goto error;
 591                 }
 592
 593                 trans_pcie->irq_requested = true;
 594         }
 595
 596         err = iwl_pcie_prepare_card_hw(trans);
 597         if (err) {
 598                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 599                 goto err_free_irq;
 600         }
 601
 602         iwl_pcie_apm_init(trans);
 603
 604         /* From now on, the op_mode will be kept updated about RF kill state */
 605         iwl_enable_rfkill_int(trans);
 606
 607         hw_rfkill = iwl_is_rfkill_set(trans);
 608         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 609
 610         return err;
 611
 612 err_free_irq:
 613         trans_pcie->irq_requested = false;
 614         free_irq(trans_pcie->irq, trans);
 615 error:
 616         iwl_pcie_free_ict(trans);
 617         tasklet_kill(&trans_pcie->irq_tasklet);
 618         return err;
 619 }
 620
 621 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
 622                                    bool op_mode_leaving)
 623 {
 624         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 625         bool hw_rfkill;
 626         unsigned long flags;
 627
 628         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 629         iwl_disable_interrupts(trans);
 630         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 631
 632         iwl_pcie_apm_stop(trans);
 633
 634         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 635         iwl_disable_interrupts(trans);
 636         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 637
 638         iwl_pcie_disable_ict(trans);
 639
 640         if (!op_mode_leaving) {
 641                 /*
 642                  * Even if we stop the HW, we still want the RF kill
 643                  * interrupt
 644                  */
 645                 iwl_enable_rfkill_int(trans);
 646
 647                 /*
 648                  * Check again since the RF kill state may have changed while
 649                  * all the interrupts were disabled, in this case we couldn't
 650                  * receive the RF kill interrupt and update the state in the
 651                  * op_mode.
 652                  */
 653                 hw_rfkill = iwl_is_rfkill_set(trans);
 654                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 655         }
 656 }
 657
 658 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 659 {
 660         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 661 }
 662
 663 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 664 {
 665         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 666 }
 667
 668 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 669 {
 670         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 671 }
 672
 673 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 674 {
 675         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
 676         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 677 }
 678
 679 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 680                                       u32 val)
 681 {
 682         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 683                                ((addr & 0x0000FFFF) | (3 << 24)));
 684         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 685 }
 686
 687 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 688                                      const struct iwl_trans_config *trans_cfg)
 689 {
 690         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 691
 692         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 693         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 694         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 695                 trans_pcie->n_no_reclaim_cmds = 0;
 696         else
 697                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 698         if (trans_pcie->n_no_reclaim_cmds)
 699                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 700                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 701
 702         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 703         if (trans_pcie->rx_buf_size_8k)
 704                 trans_pcie->rx_page_order = get_order(8 * 1024);
 705         else
 706                 trans_pcie->rx_page_order = get_order(4 * 1024);
 707
 708         trans_pcie->wd_timeout =
 709                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 710
 711         trans_pcie->command_names = trans_cfg->command_names;
 712 }
 713
 714 void iwl_trans_pcie_free(struct iwl_trans *trans)
 715 {
 716         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 717
 718         iwl_pcie_tx_free(trans);
 719         iwl_pcie_rx_free(trans);
 720
 721         if (trans_pcie->irq_requested == true) {
 722                 free_irq(trans_pcie->irq, trans);
 723                 iwl_pcie_free_ict(trans);
 724         }
 725
 726         pci_disable_msi(trans_pcie->pci_dev);
 727         iounmap(trans_pcie->hw_base);
 728         pci_release_regions(trans_pcie->pci_dev);
 729         pci_disable_device(trans_pcie->pci_dev);
 730         kmem_cache_destroy(trans->dev_cmd_pool);
 731
 732         kfree(trans);
 733 }
 734
 735 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 736 {
 737         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 738
 739         if (state)
 740                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 741         else
 742                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 743 }
 744
 745 #ifdef CONFIG_PM_SLEEP
 746 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
 747 {
 748         return 0;
 749 }
 750
 751 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
 752 {
 753         bool hw_rfkill;
 754
 755         iwl_enable_rfkill_int(trans);
 756
 757         hw_rfkill = iwl_is_rfkill_set(trans);
 758         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 759
 760         if (!hw_rfkill)
 761                 iwl_enable_interrupts(trans);
 762
 763         return 0;
 764 }
 765 #endif /* CONFIG_PM_SLEEP */
 766
 767 #define IWL_FLUSH_WAIT_MS       2000
 768
 769 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
 770 {
 771         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 772         struct iwl_txq *txq;
 773         struct iwl_queue *q;
 774         int cnt;
 775         unsigned long now = jiffies;
 776         int ret = 0;
 777
 778         /* waiting for all the tx frames complete might take a while */
 779         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
 780                 if (cnt == trans_pcie->cmd_queue)
 781                         continue;
 782                 txq = &trans_pcie->txq[cnt];
 783                 q = &txq->q;
 784                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
 785                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
 786                         msleep(1);
 787
 788                 if (q->read_ptr != q->write_ptr) {
 789                         IWL_ERR(trans, "fail to flush all tx fifo queues\n");
 790                         ret = -ETIMEDOUT;
 791                         break;
 792                 }
 793         }
 794         return ret;
 795 }
 796
 797 static const char *get_fh_string(int cmd)
 798 {
 799 #define IWL_CMD(x) case x: return #x
 800         switch (cmd) {
 801         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
 802         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
 803         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
 804         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
 805         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
 806         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
 807         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
 808         IWL_CMD(FH_TSSR_TX_STATUS_REG);
 809         IWL_CMD(FH_TSSR_TX_ERROR_REG);
 810         default:
 811                 return "UNKNOWN";
 812         }
 813 #undef IWL_CMD
 814 }
 815
 816 int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
 817 {
 818         int i;
 819         static const u32 fh_tbl[] = {
 820                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
 821                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 822                 FH_RSCSR_CHNL0_WPTR,
 823                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
 824                 FH_MEM_RSSR_SHARED_CTRL_REG,
 825                 FH_MEM_RSSR_RX_STATUS_REG,
 826                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
 827                 FH_TSSR_TX_STATUS_REG,
 828                 FH_TSSR_TX_ERROR_REG
 829         };
 830
 831 #ifdef CONFIG_IWLWIFI_DEBUGFS
 832         if (buf) {
 833                 int pos = 0;
 834                 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
 835
 836                 *buf = kmalloc(bufsz, GFP_KERNEL);
 837                 if (!*buf)
 838                         return -ENOMEM;
 839
 840                 pos += scnprintf(*buf + pos, bufsz - pos,
 841                                 "FH register values:\n");
 842
 843                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
 844                         pos += scnprintf(*buf + pos, bufsz - pos,
 845                                 "  %34s: 0X%08x\n",
 846                                 get_fh_string(fh_tbl[i]),
 847                                 iwl_read_direct32(trans, fh_tbl[i]));
 848
 849                 return pos;
 850         }
 851 #endif
 852
 853         IWL_ERR(trans, "FH register values:\n");
 854         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
 855                 IWL_ERR(trans, "  %34s: 0X%08x\n",
 856                         get_fh_string(fh_tbl[i]),
 857                         iwl_read_direct32(trans, fh_tbl[i]));
 858
 859         return 0;
 860 }
 861
 862 static const char *get_csr_string(int cmd)
 863 {
 864 #define IWL_CMD(x) case x: return #x
 865         switch (cmd) {
 866         IWL_CMD(CSR_HW_IF_CONFIG_REG);
 867         IWL_CMD(CSR_INT_COALESCING);
 868         IWL_CMD(CSR_INT);
 869         IWL_CMD(CSR_INT_MASK);
 870         IWL_CMD(CSR_FH_INT_STATUS);
 871         IWL_CMD(CSR_GPIO_IN);
 872         IWL_CMD(CSR_RESET);
 873         IWL_CMD(CSR_GP_CNTRL);
 874         IWL_CMD(CSR_HW_REV);
 875         IWL_CMD(CSR_EEPROM_REG);
 876         IWL_CMD(CSR_EEPROM_GP);
 877         IWL_CMD(CSR_OTP_GP_REG);
 878         IWL_CMD(CSR_GIO_REG);
 879         IWL_CMD(CSR_GP_UCODE_REG);
 880         IWL_CMD(CSR_GP_DRIVER_REG);
 881         IWL_CMD(CSR_UCODE_DRV_GP1);
 882         IWL_CMD(CSR_UCODE_DRV_GP2);
 883         IWL_CMD(CSR_LED_REG);
 884         IWL_CMD(CSR_DRAM_INT_TBL_REG);
 885         IWL_CMD(CSR_GIO_CHICKEN_BITS);
 886         IWL_CMD(CSR_ANA_PLL_CFG);
 887         IWL_CMD(CSR_HW_REV_WA_REG);
 888         IWL_CMD(CSR_DBG_HPET_MEM_REG);
 889         default:
 890                 return "UNKNOWN";
 891         }
 892 #undef IWL_CMD
 893 }
 894
 895 void iwl_pcie_dump_csr(struct iwl_trans *trans)
 896 {
 897         int i;
 898         static const u32 csr_tbl[] = {
 899                 CSR_HW_IF_CONFIG_REG,
 900                 CSR_INT_COALESCING,
 901                 CSR_INT,
 902                 CSR_INT_MASK,
 903                 CSR_FH_INT_STATUS,
 904                 CSR_GPIO_IN,
 905                 CSR_RESET,
 906                 CSR_GP_CNTRL,
 907                 CSR_HW_REV,
 908                 CSR_EEPROM_REG,
 909                 CSR_EEPROM_GP,
 910                 CSR_OTP_GP_REG,
 911                 CSR_GIO_REG,
 912                 CSR_GP_UCODE_REG,
 913                 CSR_GP_DRIVER_REG,
 914                 CSR_UCODE_DRV_GP1,
 915                 CSR_UCODE_DRV_GP2,
 916                 CSR_LED_REG,
 917                 CSR_DRAM_INT_TBL_REG,
 918                 CSR_GIO_CHICKEN_BITS,
 919                 CSR_ANA_PLL_CFG,
 920                 CSR_HW_REV_WA_REG,
 921                 CSR_DBG_HPET_MEM_REG
 922         };
 923         IWL_ERR(trans, "CSR values:\n");
 924         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
 925                 "CSR_INT_PERIODIC_REG)\n");
 926         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
 927                 IWL_ERR(trans, "  %25s: 0X%08x\n",
 928                         get_csr_string(csr_tbl[i]),
 929                         iwl_read32(trans, csr_tbl[i]));
 930         }
 931 }
 932
 933 #ifdef CONFIG_IWLWIFI_DEBUGFS
 934 /* create and remove of files */
 935 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
 936         if (!debugfs_create_file(#name, mode, parent, trans,            \
 937                                  &iwl_dbgfs_##name##_ops))              \
 938                 goto err;                                               \
 939 } while (0)
 940
 941 /* file operation */
 942 #define DEBUGFS_READ_FUNC(name)                                         \
 943 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
 944                                         char __user *user_buf,          \
 945                                         size_t count, loff_t *ppos);
 946
 947 #define DEBUGFS_WRITE_FUNC(name)                                        \
 948 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
 949                                         const char __user *user_buf,    \
 950                                         size_t count, loff_t *ppos);
 951
 952 #define DEBUGFS_READ_FILE_OPS(name)                                     \
 953         DEBUGFS_READ_FUNC(name);                                        \
 954 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
 955         .read = iwl_dbgfs_##name##_read,                                \
 956         .open = simple_open,                                            \
 957         .llseek = generic_file_llseek,                                  \
 958 };
 959
 960 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
 961         DEBUGFS_WRITE_FUNC(name);                                       \
 962 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
 963         .write = iwl_dbgfs_##name##_write,                              \
 964         .open = simple_open,                                            \
 965         .llseek = generic_file_llseek,                                  \
 966 };
 967
 968 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
 969         DEBUGFS_READ_FUNC(name);                                        \
 970         DEBUGFS_WRITE_FUNC(name);                                       \
 971 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
 972         .write = iwl_dbgfs_##name##_write,                              \
 973         .read = iwl_dbgfs_##name##_read,                                \
 974         .open = simple_open,                                            \
 975         .llseek = generic_file_llseek,                                  \
 976 };
 977
 978 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
 979                                        char __user *user_buf,
 980                                        size_t count, loff_t *ppos)
 981 {
 982         struct iwl_trans *trans = file->private_data;
 983         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 984         struct iwl_txq *txq;
 985         struct iwl_queue *q;
 986         char *buf;
 987         int pos = 0;
 988         int cnt;
 989         int ret;
 990         size_t bufsz;
 991
 992         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
 993
 994         if (!trans_pcie->txq)
 995                 return -EAGAIN;
 996
 997         buf = kzalloc(bufsz, GFP_KERNEL);
 998         if (!buf)
 999                 return -ENOMEM;
1000
1001         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1002                 txq = &trans_pcie->txq[cnt];
1003                 q = &txq->q;
1004                 pos += scnprintf(buf + pos, bufsz - pos,
1005                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1006                                 cnt, q->read_ptr, q->write_ptr,
1007                                 !!test_bit(cnt, trans_pcie->queue_used),
1008                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1009         }
1010         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1011         kfree(buf);
1012         return ret;
1013 }
1014
1015 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1016                                        char __user *user_buf,
1017                                        size_t count, loff_t *ppos)
1018 {
1019         struct iwl_trans *trans = file->private_data;
1020         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1021         struct iwl_rxq *rxq = &trans_pcie->rxq;
1022         char buf[256];
1023         int pos = 0;
1024         const size_t bufsz = sizeof(buf);
1025
1026         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1027                                                 rxq->read);
1028         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1029                                                 rxq->write);
1030         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1031                                                 rxq->free_count);
1032         if (rxq->rb_stts) {
1033                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1034                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1035         } else {
1036                 pos += scnprintf(buf + pos, bufsz - pos,
1037                                         "closed_rb_num: Not Allocated\n");
1038         }
1039         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1040 }
1041
1042 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1043                                         char __user *user_buf,
1044                                         size_t count, loff_t *ppos)
1045 {
1046         struct iwl_trans *trans = file->private_data;
1047         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1048         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1049
1050         int pos = 0;
1051         char *buf;
1052         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1053         ssize_t ret;
1054
1055         buf = kzalloc(bufsz, GFP_KERNEL);
1056         if (!buf)
1057                 return -ENOMEM;
1058
1059         pos += scnprintf(buf + pos, bufsz - pos,
1060                         "Interrupt Statistics Report:\n");
1061
1062         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1063                 isr_stats->hw);
1064         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1065                 isr_stats->sw);
1066         if (isr_stats->sw || isr_stats->hw) {
1067                 pos += scnprintf(buf + pos, bufsz - pos,
1068                         "\tLast Restarting Code:  0x%X\n",
1069                         isr_stats->err_code);
1070         }
1071 #ifdef CONFIG_IWLWIFI_DEBUG
1072         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1073                 isr_stats->sch);
1074         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1075                 isr_stats->alive);
1076 #endif
1077         pos += scnprintf(buf + pos, bufsz - pos,
1078                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1079
1080         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1081                 isr_stats->ctkill);
1082
1083         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1084                 isr_stats->wakeup);
1085
1086         pos += scnprintf(buf + pos, bufsz - pos,
1087                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1088
1089         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1090                 isr_stats->tx);
1091
1092         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1093                 isr_stats->unhandled);
1094
1095         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1096         kfree(buf);
1097         return ret;
1098 }
1099
1100 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1101                                          const char __user *user_buf,
1102                                          size_t count, loff_t *ppos)
1103 {
1104         struct iwl_trans *trans = file->private_data;
1105         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1106         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1107
1108         char buf[8];
1109         int buf_size;
1110         u32 reset_flag;
1111
1112         memset(buf, 0, sizeof(buf));
1113         buf_size = min(count, sizeof(buf) -  1);
1114         if (copy_from_user(buf, user_buf, buf_size))
1115                 return -EFAULT;
1116         if (sscanf(buf, "%x", &reset_flag) != 1)
1117                 return -EFAULT;
1118         if (reset_flag == 0)
1119                 memset(isr_stats, 0, sizeof(*isr_stats));
1120
1121         return count;
1122 }
1123
1124 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1125                                    const char __user *user_buf,
1126                                    size_t count, loff_t *ppos)
1127 {
1128         struct iwl_trans *trans = file->private_data;
1129         char buf[8];
1130         int buf_size;
1131         int csr;
1132
1133         memset(buf, 0, sizeof(buf));
1134         buf_size = min(count, sizeof(buf) -  1);
1135         if (copy_from_user(buf, user_buf, buf_size))
1136                 return -EFAULT;
1137         if (sscanf(buf, "%d", &csr) != 1)
1138                 return -EFAULT;
1139
1140         iwl_pcie_dump_csr(trans);
1141
1142         return count;
1143 }
1144
1145 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1146                                      char __user *user_buf,
1147                                      size_t count, loff_t *ppos)
1148 {
1149         struct iwl_trans *trans = file->private_data;
1150         char *buf = NULL;
1151         int pos = 0;
1152         ssize_t ret = -EFAULT;
1153
1154         ret = pos = iwl_pcie_dump_fh(trans, &buf);
1155         if (buf) {
1156                 ret = simple_read_from_buffer(user_buf,
1157                                               count, ppos, buf, pos);
1158                 kfree(buf);
1159         }
1160
1161         return ret;
1162 }
1163
1164 static ssize_t iwl_dbgfs_fw_restart_write(struct file *file,
1165                                           const char __user *user_buf,
1166                                           size_t count, loff_t *ppos)
1167 {
1168         struct iwl_trans *trans = file->private_data;
1169
1170         if (!trans->op_mode)
1171                 return -EAGAIN;
1172
1173         local_bh_disable();
1174         iwl_op_mode_nic_error(trans->op_mode);
1175         local_bh_enable();
1176
1177         return count;
1178 }
1179
1180 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1181 DEBUGFS_READ_FILE_OPS(fh_reg);
1182 DEBUGFS_READ_FILE_OPS(rx_queue);
1183 DEBUGFS_READ_FILE_OPS(tx_queue);
1184 DEBUGFS_WRITE_FILE_OPS(csr);
1185 DEBUGFS_WRITE_FILE_OPS(fw_restart);
1186
1187 /*
1188  * Create the debugfs files and directories
1189  *
1190  */
1191 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1192                                          struct dentry *dir)
1193 {
1194         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1195         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1196         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1197         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1198         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1199         DEBUGFS_ADD_FILE(fw_restart, dir, S_IWUSR);
1200         return 0;
1201
1202 err:
1203         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1204         return -ENOMEM;
1205 }
1206 #else
1207 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1208                                          struct dentry *dir)
1209 {
1210         return 0;
1211 }
1212 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1213
1214 static const struct iwl_trans_ops trans_ops_pcie = {
1215         .start_hw = iwl_trans_pcie_start_hw,
1216         .stop_hw = iwl_trans_pcie_stop_hw,
1217         .fw_alive = iwl_trans_pcie_fw_alive,
1218         .start_fw = iwl_trans_pcie_start_fw,
1219         .stop_device = iwl_trans_pcie_stop_device,
1220
1221         .wowlan_suspend = iwl_trans_pcie_wowlan_suspend,
1222
1223         .send_cmd = iwl_trans_pcie_send_hcmd,
1224
1225         .tx = iwl_trans_pcie_tx,
1226         .reclaim = iwl_trans_pcie_reclaim,
1227
1228         .txq_disable = iwl_trans_pcie_txq_disable,
1229         .txq_enable = iwl_trans_pcie_txq_enable,
1230
1231         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1232
1233         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1234
1235 #ifdef CONFIG_PM_SLEEP
1236         .suspend = iwl_trans_pcie_suspend,
1237         .resume = iwl_trans_pcie_resume,
1238 #endif
1239         .write8 = iwl_trans_pcie_write8,
1240         .write32 = iwl_trans_pcie_write32,
1241         .read32 = iwl_trans_pcie_read32,
1242         .read_prph = iwl_trans_pcie_read_prph,
1243         .write_prph = iwl_trans_pcie_write_prph,
1244         .configure = iwl_trans_pcie_configure,
1245         .set_pmi = iwl_trans_pcie_set_pmi,
1246 };
1247
1248 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1249                                        const struct pci_device_id *ent,
1250                                        const struct iwl_cfg *cfg)
1251 {
1252         struct iwl_trans_pcie *trans_pcie;
1253         struct iwl_trans *trans;
1254         u16 pci_cmd;
1255         int err;
1256
1257         trans = kzalloc(sizeof(struct iwl_trans) +
1258                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1259
1260         if (!trans)
1261                 return NULL;
1262
1263         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1264
1265         trans->ops = &trans_ops_pcie;
1266         trans->cfg = cfg;
1267         trans_pcie->trans = trans;
1268         spin_lock_init(&trans_pcie->irq_lock);
1269         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1270
1271         /* W/A - seems to solve weird behavior. We need to remove this if we
1272          * don't want to stay in L1 all the time. This wastes a lot of power */
1273         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1274                                PCIE_LINK_STATE_CLKPM);
1275
1276         if (pci_enable_device(pdev)) {
1277                 err = -ENODEV;
1278                 goto out_no_pci;
1279         }
1280
1281         pci_set_master(pdev);
1282
1283         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1284         if (!err)
1285                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1286         if (err) {
1287                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1288                 if (!err)
1289                         err = pci_set_consistent_dma_mask(pdev,
1290                                                           DMA_BIT_MASK(32));
1291                 /* both attempts failed: */
1292                 if (err) {
1293                         dev_printk(KERN_ERR, &pdev->dev,
1294                                    "No suitable DMA available.\n");
1295                         goto out_pci_disable_device;
1296                 }
1297         }
1298
1299         err = pci_request_regions(pdev, DRV_NAME);
1300         if (err) {
1301                 dev_printk(KERN_ERR, &pdev->dev,
1302                            "pci_request_regions failed\n");
1303                 goto out_pci_disable_device;
1304         }
1305
1306         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1307         if (!trans_pcie->hw_base) {
1308                 dev_printk(KERN_ERR, &pdev->dev, "pci_ioremap_bar failed\n");
1309                 err = -ENODEV;
1310                 goto out_pci_release_regions;
1311         }
1312
1313         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1314          * PCI Tx retries from interfering with C3 CPU state */
1315         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1316
1317         err = pci_enable_msi(pdev);
1318         if (err) {
1319                 dev_printk(KERN_ERR, &pdev->dev,
1320                            "pci_enable_msi failed(0X%x)\n", err);
1321                 /* enable rfkill interrupt: hw bug w/a */
1322                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1323                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1324                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1325                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1326                 }
1327         }
1328
1329         trans->dev = &pdev->dev;
1330         trans_pcie->irq = pdev->irq;
1331         trans_pcie->pci_dev = pdev;
1332         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1333         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1334         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1335                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1336
1337         /* Initialize the wait queue for commands */
1338         init_waitqueue_head(&trans_pcie->wait_command_queue);
1339         spin_lock_init(&trans->reg_lock);
1340
1341         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1342                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1343
1344         trans->dev_cmd_headroom = 0;
1345         trans->dev_cmd_pool =
1346                 kmem_cache_create(trans->dev_cmd_pool_name,
1347                                   sizeof(struct iwl_device_cmd)
1348                                   + trans->dev_cmd_headroom,
1349                                   sizeof(void *),
1350                                   SLAB_HWCACHE_ALIGN,
1351                                   NULL);
1352
1353         if (!trans->dev_cmd_pool)
1354                 goto out_pci_disable_msi;
1355
1356         return trans;
1357
1358 out_pci_disable_msi:
1359         pci_disable_msi(pdev);
1360 out_pci_release_regions:
1361         pci_release_regions(pdev);
1362 out_pci_disable_device:
1363         pci_disable_device(pdev);
1364 out_no_pci:
1365         kfree(trans);
1366         return NULL;
1367 }