arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/gpio-omap.h>
  21
  22 #include <plat-omap/dma-omap.h>
  23 #include <plat/serial.h>
  24
  25 #include "l3_3xxx.h"
  26 #include "l4_3xxx.h"
  27 #include <linux/platform_data/asoc-ti-mcbsp.h>
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <plat/dmtimer.h>
  30 #include <plat/iommu.h>
  31
  32 #include "am35xx.h"
  33
  34 #include "soc.h"
  35 #include "omap_hwmod.h"
  36 #include "omap_hwmod_common_data.h"
  37 #include "prm-regbits-34xx.h"
  38 #include "cm-regbits-34xx.h"
  39
  40 #include "dma.h"
  41 #include "i2c.h"
  42 #include "mmc.h"
  43 #include "wd_timer.h"
  44
  45 /*
  46  * OMAP3xxx hardware module integration data
  47  *
  48  * All of the data in this section should be autogeneratable from the
  49  * TI hardware database or other technical documentation.  Data that
  50  * is driver-specific or driver-kernel integration-specific belongs
  51  * elsewhere.
  52  */
  53
  54 /*
  55  * IP blocks
  56  */
  57
  58 /* L3 */
  59 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  60         { .irq = 9 + OMAP_INTC_START, },
  61         { .irq = 10 + OMAP_INTC_START, },
  62         { .irq = -1 },
  63 };
  64
  65 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  66         .name           = "l3_main",
  67         .class          = &l3_hwmod_class,
  68         .mpu_irqs       = omap3xxx_l3_main_irqs,
  69         .flags          = HWMOD_NO_IDLEST,
  70 };
  71
  72 /* L4 CORE */
  73 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  74         .name           = "l4_core",
  75         .class          = &l4_hwmod_class,
  76         .flags          = HWMOD_NO_IDLEST,
  77 };
  78
  79 /* L4 PER */
  80 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  81         .name           = "l4_per",
  82         .class          = &l4_hwmod_class,
  83         .flags          = HWMOD_NO_IDLEST,
  84 };
  85
  86 /* L4 WKUP */
  87 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  88         .name           = "l4_wkup",
  89         .class          = &l4_hwmod_class,
  90         .flags          = HWMOD_NO_IDLEST,
  91 };
  92
  93 /* L4 SEC */
  94 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  95         .name           = "l4_sec",
  96         .class          = &l4_hwmod_class,
  97         .flags          = HWMOD_NO_IDLEST,
  98 };
  99
 100 /* MPU */
 101 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
 102         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 103         { .irq = -1 }
 104 };
 105
 106 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 107         .name           = "mpu",
 108         .mpu_irqs       = omap3xxx_mpu_irqs,
 109         .class          = &mpu_hwmod_class,
 110         .main_clk       = "arm_fck",
 111 };
 112
 113 /* IVA2 (IVA2) */
 114 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 115         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 116         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 117         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 118 };
 119
 120 static struct omap_hwmod omap3xxx_iva_hwmod = {
 121         .name           = "iva",
 122         .class          = &iva_hwmod_class,
 123         .clkdm_name     = "iva2_clkdm",
 124         .rst_lines      = omap3xxx_iva_resets,
 125         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 126         .main_clk       = "iva2_ck",
 127         .prcm = {
 128                 .omap2 = {
 129                         .module_offs = OMAP3430_IVA2_MOD,
 130                         .prcm_reg_id = 1,
 131                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 132                         .idlest_reg_id = 1,
 133                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 134                 }
 135         },
 136 };
 137
 138 /*
 139  * 'debugss' class
 140  * debug and emulation sub system
 141  */
 142
 143 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 144         .name   = "debugss",
 145 };
 146
 147 /* debugss */
 148 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 149         .name           = "debugss",
 150         .class          = &omap3xxx_debugss_hwmod_class,
 151         .clkdm_name     = "emu_clkdm",
 152         .main_clk       = "emu_src_ck",
 153         .flags          = HWMOD_NO_IDLEST,
 154 };
 155
 156 /* timer class */
 157 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 158         .rev_offs       = 0x0000,
 159         .sysc_offs      = 0x0010,
 160         .syss_offs      = 0x0014,
 161         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 162                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 163                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 165         .sysc_fields    = &omap_hwmod_sysc_type1,
 166 };
 167
 168 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 169         .name = "timer",
 170         .sysc = &omap3xxx_timer_1ms_sysc,
 171 };
 172
 173 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 174         .rev_offs       = 0x0000,
 175         .sysc_offs      = 0x0010,
 176         .syss_offs      = 0x0014,
 177         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 178                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 179         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 180         .sysc_fields    = &omap_hwmod_sysc_type1,
 181 };
 182
 183 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 184         .name = "timer",
 185         .sysc = &omap3xxx_timer_sysc,
 186 };
 187
 188 /* secure timers dev attribute */
 189 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 190         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 191 };
 192
 193 /* always-on timers dev attribute */
 194 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 195         .timer_capability       = OMAP_TIMER_ALWON,
 196 };
 197
 198 /* pwm timers dev attribute */
 199 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 200         .timer_capability       = OMAP_TIMER_HAS_PWM,
 201 };
 202
 203 /* timers with DSP interrupt dev attribute */
 204 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 205         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 206 };
 207
 208 /* pwm timers with DSP interrupt dev attribute */
 209 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 210         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 211 };
 212
 213 /* timer1 */
 214 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 215         .name           = "timer1",
 216         .mpu_irqs       = omap2_timer1_mpu_irqs,
 217         .main_clk       = "gpt1_fck",
 218         .prcm           = {
 219                 .omap2 = {
 220                         .prcm_reg_id = 1,
 221                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 222                         .module_offs = WKUP_MOD,
 223                         .idlest_reg_id = 1,
 224                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 225                 },
 226         },
 227         .dev_attr       = &capability_alwon_dev_attr,
 228         .class          = &omap3xxx_timer_1ms_hwmod_class,
 229 };
 230
 231 /* timer2 */
 232 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 233         .name           = "timer2",
 234         .mpu_irqs       = omap2_timer2_mpu_irqs,
 235         .main_clk       = "gpt2_fck",
 236         .prcm           = {
 237                 .omap2 = {
 238                         .prcm_reg_id = 1,
 239                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 240                         .module_offs = OMAP3430_PER_MOD,
 241                         .idlest_reg_id = 1,
 242                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 243                 },
 244         },
 245         .class          = &omap3xxx_timer_1ms_hwmod_class,
 246 };
 247
 248 /* timer3 */
 249 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 250         .name           = "timer3",
 251         .mpu_irqs       = omap2_timer3_mpu_irqs,
 252         .main_clk       = "gpt3_fck",
 253         .prcm           = {
 254                 .omap2 = {
 255                         .prcm_reg_id = 1,
 256                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 257                         .module_offs = OMAP3430_PER_MOD,
 258                         .idlest_reg_id = 1,
 259                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 260                 },
 261         },
 262         .class          = &omap3xxx_timer_hwmod_class,
 263 };
 264
 265 /* timer4 */
 266 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 267         .name           = "timer4",
 268         .mpu_irqs       = omap2_timer4_mpu_irqs,
 269         .main_clk       = "gpt4_fck",
 270         .prcm           = {
 271                 .omap2 = {
 272                         .prcm_reg_id = 1,
 273                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 274                         .module_offs = OMAP3430_PER_MOD,
 275                         .idlest_reg_id = 1,
 276                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 277                 },
 278         },
 279         .class          = &omap3xxx_timer_hwmod_class,
 280 };
 281
 282 /* timer5 */
 283 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 284         .name           = "timer5",
 285         .mpu_irqs       = omap2_timer5_mpu_irqs,
 286         .main_clk       = "gpt5_fck",
 287         .prcm           = {
 288                 .omap2 = {
 289                         .prcm_reg_id = 1,
 290                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 291                         .module_offs = OMAP3430_PER_MOD,
 292                         .idlest_reg_id = 1,
 293                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 294                 },
 295         },
 296         .dev_attr       = &capability_dsp_dev_attr,
 297         .class          = &omap3xxx_timer_hwmod_class,
 298 };
 299
 300 /* timer6 */
 301 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 302         .name           = "timer6",
 303         .mpu_irqs       = omap2_timer6_mpu_irqs,
 304         .main_clk       = "gpt6_fck",
 305         .prcm           = {
 306                 .omap2 = {
 307                         .prcm_reg_id = 1,
 308                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 309                         .module_offs = OMAP3430_PER_MOD,
 310                         .idlest_reg_id = 1,
 311                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 312                 },
 313         },
 314         .dev_attr       = &capability_dsp_dev_attr,
 315         .class          = &omap3xxx_timer_hwmod_class,
 316 };
 317
 318 /* timer7 */
 319 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 320         .name           = "timer7",
 321         .mpu_irqs       = omap2_timer7_mpu_irqs,
 322         .main_clk       = "gpt7_fck",
 323         .prcm           = {
 324                 .omap2 = {
 325                         .prcm_reg_id = 1,
 326                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 327                         .module_offs = OMAP3430_PER_MOD,
 328                         .idlest_reg_id = 1,
 329                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 330                 },
 331         },
 332         .dev_attr       = &capability_dsp_dev_attr,
 333         .class          = &omap3xxx_timer_hwmod_class,
 334 };
 335
 336 /* timer8 */
 337 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 338         .name           = "timer8",
 339         .mpu_irqs       = omap2_timer8_mpu_irqs,
 340         .main_clk       = "gpt8_fck",
 341         .prcm           = {
 342                 .omap2 = {
 343                         .prcm_reg_id = 1,
 344                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 345                         .module_offs = OMAP3430_PER_MOD,
 346                         .idlest_reg_id = 1,
 347                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 348                 },
 349         },
 350         .dev_attr       = &capability_dsp_pwm_dev_attr,
 351         .class          = &omap3xxx_timer_hwmod_class,
 352 };
 353
 354 /* timer9 */
 355 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 356         .name           = "timer9",
 357         .mpu_irqs       = omap2_timer9_mpu_irqs,
 358         .main_clk       = "gpt9_fck",
 359         .prcm           = {
 360                 .omap2 = {
 361                         .prcm_reg_id = 1,
 362                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 363                         .module_offs = OMAP3430_PER_MOD,
 364                         .idlest_reg_id = 1,
 365                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 366                 },
 367         },
 368         .dev_attr       = &capability_pwm_dev_attr,
 369         .class          = &omap3xxx_timer_hwmod_class,
 370 };
 371
 372 /* timer10 */
 373 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 374         .name           = "timer10",
 375         .mpu_irqs       = omap2_timer10_mpu_irqs,
 376         .main_clk       = "gpt10_fck",
 377         .prcm           = {
 378                 .omap2 = {
 379                         .prcm_reg_id = 1,
 380                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 381                         .module_offs = CORE_MOD,
 382                         .idlest_reg_id = 1,
 383                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 384                 },
 385         },
 386         .dev_attr       = &capability_pwm_dev_attr,
 387         .class          = &omap3xxx_timer_1ms_hwmod_class,
 388 };
 389
 390 /* timer11 */
 391 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 392         .name           = "timer11",
 393         .mpu_irqs       = omap2_timer11_mpu_irqs,
 394         .main_clk       = "gpt11_fck",
 395         .prcm           = {
 396                 .omap2 = {
 397                         .prcm_reg_id = 1,
 398                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 399                         .module_offs = CORE_MOD,
 400                         .idlest_reg_id = 1,
 401                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 402                 },
 403         },
 404         .dev_attr       = &capability_pwm_dev_attr,
 405         .class          = &omap3xxx_timer_hwmod_class,
 406 };
 407
 408 /* timer12 */
 409 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 410         { .irq = 95 + OMAP_INTC_START, },
 411         { .irq = -1 },
 412 };
 413
 414 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 415         .name           = "timer12",
 416         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 417         .main_clk       = "gpt12_fck",
 418         .prcm           = {
 419                 .omap2 = {
 420                         .prcm_reg_id = 1,
 421                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 422                         .module_offs = WKUP_MOD,
 423                         .idlest_reg_id = 1,
 424                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 425                 },
 426         },
 427         .dev_attr       = &capability_secure_dev_attr,
 428         .class          = &omap3xxx_timer_hwmod_class,
 429 };
 430
 431 /*
 432  * 'wd_timer' class
 433  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 434  * overflow condition
 435  */
 436
 437 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 438         .rev_offs       = 0x0000,
 439         .sysc_offs      = 0x0010,
 440         .syss_offs      = 0x0014,
 441         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 442                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 443                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 444                            SYSS_HAS_RESET_STATUS),
 445         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 446         .sysc_fields    = &omap_hwmod_sysc_type1,
 447 };
 448
 449 /* I2C common */
 450 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 451         .rev_offs       = 0x00,
 452         .sysc_offs      = 0x20,
 453         .syss_offs      = 0x10,
 454         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 455                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 456                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 457         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 458         .clockact       = CLOCKACT_TEST_ICLK,
 459         .sysc_fields    = &omap_hwmod_sysc_type1,
 460 };
 461
 462 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 463         .name           = "wd_timer",
 464         .sysc           = &omap3xxx_wd_timer_sysc,
 465         .pre_shutdown   = &omap2_wd_timer_disable,
 466         .reset          = &omap2_wd_timer_reset,
 467 };
 468
 469 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 470         .name           = "wd_timer2",
 471         .class          = &omap3xxx_wd_timer_hwmod_class,
 472         .main_clk       = "wdt2_fck",
 473         .prcm           = {
 474                 .omap2 = {
 475                         .prcm_reg_id = 1,
 476                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 477                         .module_offs = WKUP_MOD,
 478                         .idlest_reg_id = 1,
 479                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 480                 },
 481         },
 482         /*
 483          * XXX: Use software supervised mode, HW supervised smartidle seems to
 484          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 485          */
 486         .flags          = HWMOD_SWSUP_SIDLE,
 487 };
 488
 489 /* UART1 */
 490 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 491         .name           = "uart1",
 492         .mpu_irqs       = omap2_uart1_mpu_irqs,
 493         .sdma_reqs      = omap2_uart1_sdma_reqs,
 494         .main_clk       = "uart1_fck",
 495         .prcm           = {
 496                 .omap2 = {
 497                         .module_offs = CORE_MOD,
 498                         .prcm_reg_id = 1,
 499                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 500                         .idlest_reg_id = 1,
 501                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 502                 },
 503         },
 504         .class          = &omap2_uart_class,
 505 };
 506
 507 /* UART2 */
 508 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 509         .name           = "uart2",
 510         .mpu_irqs       = omap2_uart2_mpu_irqs,
 511         .sdma_reqs      = omap2_uart2_sdma_reqs,
 512         .main_clk       = "uart2_fck",
 513         .prcm           = {
 514                 .omap2 = {
 515                         .module_offs = CORE_MOD,
 516                         .prcm_reg_id = 1,
 517                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 518                         .idlest_reg_id = 1,
 519                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 520                 },
 521         },
 522         .class          = &omap2_uart_class,
 523 };
 524
 525 /* UART3 */
 526 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 527         .name           = "uart3",
 528         .mpu_irqs       = omap2_uart3_mpu_irqs,
 529         .sdma_reqs      = omap2_uart3_sdma_reqs,
 530         .main_clk       = "uart3_fck",
 531         .prcm           = {
 532                 .omap2 = {
 533                         .module_offs = OMAP3430_PER_MOD,
 534                         .prcm_reg_id = 1,
 535                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 536                         .idlest_reg_id = 1,
 537                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 538                 },
 539         },
 540         .class          = &omap2_uart_class,
 541 };
 542
 543 /* UART4 */
 544 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 545         { .irq = 80 + OMAP_INTC_START, },
 546         { .irq = -1 },
 547 };
 548
 549 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 550         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 551         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 552         { .dma_req = -1 }
 553 };
 554
 555 static struct omap_hwmod omap36xx_uart4_hwmod = {
 556         .name           = "uart4",
 557         .mpu_irqs       = uart4_mpu_irqs,
 558         .sdma_reqs      = uart4_sdma_reqs,
 559         .main_clk       = "uart4_fck",
 560         .prcm           = {
 561                 .omap2 = {
 562                         .module_offs = OMAP3430_PER_MOD,
 563                         .prcm_reg_id = 1,
 564                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 565                         .idlest_reg_id = 1,
 566                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 567                 },
 568         },
 569         .class          = &omap2_uart_class,
 570 };
 571
 572 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 573         { .irq = 84 + OMAP_INTC_START, },
 574         { .irq = -1 },
 575 };
 576
 577 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 578         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 579         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 580         { .dma_req = -1 }
 581 };
 582
 583 /*
 584  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 585  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 586  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 587  * should not be needed.  The functional clock structure of the AM35xx
 588  * UART4 is extremely unclear and opaque; it is unclear what the role
 589  * of uart1/2_fck is for the UART4.  Any clarification from either
 590  * empirical testing or the AM3505/3517 hardware designers would be
 591  * most welcome.
 592  */
 593 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 594         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 595 };
 596
 597 static struct omap_hwmod am35xx_uart4_hwmod = {
 598         .name           = "uart4",
 599         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 600         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 601         .main_clk       = "uart4_fck",
 602         .prcm           = {
 603                 .omap2 = {
 604                         .module_offs = CORE_MOD,
 605                         .prcm_reg_id = 1,
 606                         .module_bit = AM35XX_EN_UART4_SHIFT,
 607                         .idlest_reg_id = 1,
 608                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 609                 },
 610         },
 611         .opt_clks       = am35xx_uart4_opt_clks,
 612         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 613         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 614         .class          = &omap2_uart_class,
 615 };
 616
 617 static struct omap_hwmod_class i2c_class = {
 618         .name   = "i2c",
 619         .sysc   = &i2c_sysc,
 620         .rev    = OMAP_I2C_IP_VERSION_1,
 621         .reset  = &omap_i2c_reset,
 622 };
 623
 624 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 625         { .name = "dispc", .dma_req = 5 },
 626         { .name = "dsi1", .dma_req = 74 },
 627         { .dma_req = -1 }
 628 };
 629
 630 /* dss */
 631 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 632         /*
 633          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 634          * driver does not use these clocks.
 635          */
 636         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 637         { .role = "tv_clk", .clk = "dss_tv_fck" },
 638         /* required only on OMAP3430 */
 639         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 640 };
 641
 642 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 643         .name           = "dss_core",
 644         .class          = &omap2_dss_hwmod_class,
 645         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 646         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 647         .prcm           = {
 648                 .omap2 = {
 649                         .prcm_reg_id = 1,
 650                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 651                         .module_offs = OMAP3430_DSS_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 654                 },
 655         },
 656         .opt_clks       = dss_opt_clks,
 657         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 658         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 659 };
 660
 661 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 662         .name           = "dss_core",
 663         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 664         .class          = &omap2_dss_hwmod_class,
 665         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 666         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 667         .prcm           = {
 668                 .omap2 = {
 669                         .prcm_reg_id = 1,
 670                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 671                         .module_offs = OMAP3430_DSS_MOD,
 672                         .idlest_reg_id = 1,
 673                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 674                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 675                 },
 676         },
 677         .opt_clks       = dss_opt_clks,
 678         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 679 };
 680
 681 /*
 682  * 'dispc' class
 683  * display controller
 684  */
 685
 686 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 687         .rev_offs       = 0x0000,
 688         .sysc_offs      = 0x0010,
 689         .syss_offs      = 0x0014,
 690         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 691                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 692                            SYSC_HAS_ENAWAKEUP),
 693         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 694                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 695         .sysc_fields    = &omap_hwmod_sysc_type1,
 696 };
 697
 698 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 699         .name   = "dispc",
 700         .sysc   = &omap3_dispc_sysc,
 701 };
 702
 703 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 704         .name           = "dss_dispc",
 705         .class          = &omap3_dispc_hwmod_class,
 706         .mpu_irqs       = omap2_dispc_irqs,
 707         .main_clk       = "dss1_alwon_fck",
 708         .prcm           = {
 709                 .omap2 = {
 710                         .prcm_reg_id = 1,
 711                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 712                         .module_offs = OMAP3430_DSS_MOD,
 713                 },
 714         },
 715         .flags          = HWMOD_NO_IDLEST,
 716         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 717 };
 718
 719 /*
 720  * 'dsi' class
 721  * display serial interface controller
 722  */
 723
 724 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 725         .name = "dsi",
 726 };
 727
 728 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 729         { .irq = 25 + OMAP_INTC_START, },
 730         { .irq = -1 },
 731 };
 732
 733 /* dss_dsi1 */
 734 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 735         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 736 };
 737
 738 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 739         .name           = "dss_dsi1",
 740         .class          = &omap3xxx_dsi_hwmod_class,
 741         .mpu_irqs       = omap3xxx_dsi1_irqs,
 742         .main_clk       = "dss1_alwon_fck",
 743         .prcm           = {
 744                 .omap2 = {
 745                         .prcm_reg_id = 1,
 746                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 747                         .module_offs = OMAP3430_DSS_MOD,
 748                 },
 749         },
 750         .opt_clks       = dss_dsi1_opt_clks,
 751         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 752         .flags          = HWMOD_NO_IDLEST,
 753 };
 754
 755 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 756         { .role = "ick", .clk = "dss_ick" },
 757 };
 758
 759 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 760         .name           = "dss_rfbi",
 761         .class          = &omap2_rfbi_hwmod_class,
 762         .main_clk       = "dss1_alwon_fck",
 763         .prcm           = {
 764                 .omap2 = {
 765                         .prcm_reg_id = 1,
 766                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 767                         .module_offs = OMAP3430_DSS_MOD,
 768                 },
 769         },
 770         .opt_clks       = dss_rfbi_opt_clks,
 771         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 772         .flags          = HWMOD_NO_IDLEST,
 773 };
 774
 775 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 776         /* required only on OMAP3430 */
 777         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 778 };
 779
 780 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 781         .name           = "dss_venc",
 782         .class          = &omap2_venc_hwmod_class,
 783         .main_clk       = "dss_tv_fck",
 784         .prcm           = {
 785                 .omap2 = {
 786                         .prcm_reg_id = 1,
 787                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 788                         .module_offs = OMAP3430_DSS_MOD,
 789                 },
 790         },
 791         .opt_clks       = dss_venc_opt_clks,
 792         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 793         .flags          = HWMOD_NO_IDLEST,
 794 };
 795
 796 /* I2C1 */
 797 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 798         .fifo_depth     = 8, /* bytes */
 799         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 800                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 801                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 802 };
 803
 804 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 805         .name           = "i2c1",
 806         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 807         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 808         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 809         .main_clk       = "i2c1_fck",
 810         .prcm           = {
 811                 .omap2 = {
 812                         .module_offs = CORE_MOD,
 813                         .prcm_reg_id = 1,
 814                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 815                         .idlest_reg_id = 1,
 816                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 817                 },
 818         },
 819         .class          = &i2c_class,
 820         .dev_attr       = &i2c1_dev_attr,
 821 };
 822
 823 /* I2C2 */
 824 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 825         .fifo_depth     = 8, /* bytes */
 826         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 827                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 828                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 829 };
 830
 831 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 832         .name           = "i2c2",
 833         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 834         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 835         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 836         .main_clk       = "i2c2_fck",
 837         .prcm           = {
 838                 .omap2 = {
 839                         .module_offs = CORE_MOD,
 840                         .prcm_reg_id = 1,
 841                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 842                         .idlest_reg_id = 1,
 843                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 844                 },
 845         },
 846         .class          = &i2c_class,
 847         .dev_attr       = &i2c2_dev_attr,
 848 };
 849
 850 /* I2C3 */
 851 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 852         .fifo_depth     = 64, /* bytes */
 853         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 854                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 855                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 856 };
 857
 858 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 859         { .irq = 61 + OMAP_INTC_START, },
 860         { .irq = -1 },
 861 };
 862
 863 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 864         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 865         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 866         { .dma_req = -1 }
 867 };
 868
 869 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 870         .name           = "i2c3",
 871         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 872         .mpu_irqs       = i2c3_mpu_irqs,
 873         .sdma_reqs      = i2c3_sdma_reqs,
 874         .main_clk       = "i2c3_fck",
 875         .prcm           = {
 876                 .omap2 = {
 877                         .module_offs = CORE_MOD,
 878                         .prcm_reg_id = 1,
 879                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 880                         .idlest_reg_id = 1,
 881                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 882                 },
 883         },
 884         .class          = &i2c_class,
 885         .dev_attr       = &i2c3_dev_attr,
 886 };
 887
 888 /*
 889  * 'gpio' class
 890  * general purpose io module
 891  */
 892
 893 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 894         .rev_offs       = 0x0000,
 895         .sysc_offs      = 0x0010,
 896         .syss_offs      = 0x0014,
 897         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 898                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 899                            SYSS_HAS_RESET_STATUS),
 900         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 901         .sysc_fields    = &omap_hwmod_sysc_type1,
 902 };
 903
 904 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 905         .name = "gpio",
 906         .sysc = &omap3xxx_gpio_sysc,
 907         .rev = 1,
 908 };
 909
 910 /* gpio_dev_attr */
 911 static struct omap_gpio_dev_attr gpio_dev_attr = {
 912         .bank_width = 32,
 913         .dbck_flag = true,
 914 };
 915
 916 /* gpio1 */
 917 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 918         { .role = "dbclk", .clk = "gpio1_dbck", },
 919 };
 920
 921 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 922         .name           = "gpio1",
 923         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 924         .mpu_irqs       = omap2_gpio1_irqs,
 925         .main_clk       = "gpio1_ick",
 926         .opt_clks       = gpio1_opt_clks,
 927         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 928         .prcm           = {
 929                 .omap2 = {
 930                         .prcm_reg_id = 1,
 931                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 932                         .module_offs = WKUP_MOD,
 933                         .idlest_reg_id = 1,
 934                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 935                 },
 936         },
 937         .class          = &omap3xxx_gpio_hwmod_class,
 938         .dev_attr       = &gpio_dev_attr,
 939 };
 940
 941 /* gpio2 */
 942 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 943         { .role = "dbclk", .clk = "gpio2_dbck", },
 944 };
 945
 946 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 947         .name           = "gpio2",
 948         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 949         .mpu_irqs       = omap2_gpio2_irqs,
 950         .main_clk       = "gpio2_ick",
 951         .opt_clks       = gpio2_opt_clks,
 952         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 953         .prcm           = {
 954                 .omap2 = {
 955                         .prcm_reg_id = 1,
 956                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 957                         .module_offs = OMAP3430_PER_MOD,
 958                         .idlest_reg_id = 1,
 959                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 960                 },
 961         },
 962         .class          = &omap3xxx_gpio_hwmod_class,
 963         .dev_attr       = &gpio_dev_attr,
 964 };
 965
 966 /* gpio3 */
 967 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 968         { .role = "dbclk", .clk = "gpio3_dbck", },
 969 };
 970
 971 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 972         .name           = "gpio3",
 973         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 974         .mpu_irqs       = omap2_gpio3_irqs,
 975         .main_clk       = "gpio3_ick",
 976         .opt_clks       = gpio3_opt_clks,
 977         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 978         .prcm           = {
 979                 .omap2 = {
 980                         .prcm_reg_id = 1,
 981                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 982                         .module_offs = OMAP3430_PER_MOD,
 983                         .idlest_reg_id = 1,
 984                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 985                 },
 986         },
 987         .class          = &omap3xxx_gpio_hwmod_class,
 988         .dev_attr       = &gpio_dev_attr,
 989 };
 990
 991 /* gpio4 */
 992 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 993         { .role = "dbclk", .clk = "gpio4_dbck", },
 994 };
 995
 996 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 997         .name           = "gpio4",
 998         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 999         .mpu_irqs       = omap2_gpio4_irqs,
1000         .main_clk       = "gpio4_ick",
1001         .opt_clks       = gpio4_opt_clks,
1002         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1003         .prcm           = {
1004                 .omap2 = {
1005                         .prcm_reg_id = 1,
1006                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1007                         .module_offs = OMAP3430_PER_MOD,
1008                         .idlest_reg_id = 1,
1009                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1010                 },
1011         },
1012         .class          = &omap3xxx_gpio_hwmod_class,
1013         .dev_attr       = &gpio_dev_attr,
1014 };
1015
1016 /* gpio5 */
1017 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1018         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1019         { .irq = -1 },
1020 };
1021
1022 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1023         { .role = "dbclk", .clk = "gpio5_dbck", },
1024 };
1025
1026 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1027         .name           = "gpio5",
1028         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1029         .mpu_irqs       = omap3xxx_gpio5_irqs,
1030         .main_clk       = "gpio5_ick",
1031         .opt_clks       = gpio5_opt_clks,
1032         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1033         .prcm           = {
1034                 .omap2 = {
1035                         .prcm_reg_id = 1,
1036                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1037                         .module_offs = OMAP3430_PER_MOD,
1038                         .idlest_reg_id = 1,
1039                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1040                 },
1041         },
1042         .class          = &omap3xxx_gpio_hwmod_class,
1043         .dev_attr       = &gpio_dev_attr,
1044 };
1045
1046 /* gpio6 */
1047 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1048         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1049         { .irq = -1 },
1050 };
1051
1052 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1053         { .role = "dbclk", .clk = "gpio6_dbck", },
1054 };
1055
1056 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1057         .name           = "gpio6",
1058         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1059         .mpu_irqs       = omap3xxx_gpio6_irqs,
1060         .main_clk       = "gpio6_ick",
1061         .opt_clks       = gpio6_opt_clks,
1062         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1063         .prcm           = {
1064                 .omap2 = {
1065                         .prcm_reg_id = 1,
1066                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1067                         .module_offs = OMAP3430_PER_MOD,
1068                         .idlest_reg_id = 1,
1069                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1070                 },
1071         },
1072         .class          = &omap3xxx_gpio_hwmod_class,
1073         .dev_attr       = &gpio_dev_attr,
1074 };
1075
1076 /* dma attributes */
1077 static struct omap_dma_dev_attr dma_dev_attr = {
1078         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1079                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1080         .lch_count = 32,
1081 };
1082
1083 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1084         .rev_offs       = 0x0000,
1085         .sysc_offs      = 0x002c,
1086         .syss_offs      = 0x0028,
1087         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1088                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1089                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1090                            SYSS_HAS_RESET_STATUS),
1091         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1092                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1093         .sysc_fields    = &omap_hwmod_sysc_type1,
1094 };
1095
1096 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1097         .name = "dma",
1098         .sysc = &omap3xxx_dma_sysc,
1099 };
1100
1101 /* dma_system */
1102 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1103         .name           = "dma",
1104         .class          = &omap3xxx_dma_hwmod_class,
1105         .mpu_irqs       = omap2_dma_system_irqs,
1106         .main_clk       = "core_l3_ick",
1107         .prcm = {
1108                 .omap2 = {
1109                         .module_offs            = CORE_MOD,
1110                         .prcm_reg_id            = 1,
1111                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1112                         .idlest_reg_id          = 1,
1113                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1114                 },
1115         },
1116         .dev_attr       = &dma_dev_attr,
1117         .flags          = HWMOD_NO_IDLEST,
1118 };
1119
1120 /*
1121  * 'mcbsp' class
1122  * multi channel buffered serial port controller
1123  */
1124
1125 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1126         .sysc_offs      = 0x008c,
1127         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1128                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1129         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1130         .sysc_fields    = &omap_hwmod_sysc_type1,
1131         .clockact       = 0x2,
1132 };
1133
1134 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1135         .name = "mcbsp",
1136         .sysc = &omap3xxx_mcbsp_sysc,
1137         .rev  = MCBSP_CONFIG_TYPE3,
1138 };
1139
1140 /* McBSP functional clock mapping */
1141 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1142         { .role = "pad_fck", .clk = "mcbsp_clks" },
1143         { .role = "prcm_fck", .clk = "core_96m_fck" },
1144 };
1145
1146 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1147         { .role = "pad_fck", .clk = "mcbsp_clks" },
1148         { .role = "prcm_fck", .clk = "per_96m_fck" },
1149 };
1150
1151 /* mcbsp1 */
1152 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1153         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1154         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1155         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1156         { .irq = -1 },
1157 };
1158
1159 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1160         .name           = "mcbsp1",
1161         .class          = &omap3xxx_mcbsp_hwmod_class,
1162         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1163         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1164         .main_clk       = "mcbsp1_fck",
1165         .prcm           = {
1166                 .omap2 = {
1167                         .prcm_reg_id = 1,
1168                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1169                         .module_offs = CORE_MOD,
1170                         .idlest_reg_id = 1,
1171                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1172                 },
1173         },
1174         .opt_clks       = mcbsp15_opt_clks,
1175         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1176 };
1177
1178 /* mcbsp2 */
1179 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1180         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1181         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1182         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1183         { .irq = -1 },
1184 };
1185
1186 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1187         .sidetone       = "mcbsp2_sidetone",
1188 };
1189
1190 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1191         .name           = "mcbsp2",
1192         .class          = &omap3xxx_mcbsp_hwmod_class,
1193         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1194         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1195         .main_clk       = "mcbsp2_fck",
1196         .prcm           = {
1197                 .omap2 = {
1198                         .prcm_reg_id = 1,
1199                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1200                         .module_offs = OMAP3430_PER_MOD,
1201                         .idlest_reg_id = 1,
1202                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1203                 },
1204         },
1205         .opt_clks       = mcbsp234_opt_clks,
1206         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1207         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1208 };
1209
1210 /* mcbsp3 */
1211 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1212         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1213         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1214         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1215         { .irq = -1 },
1216 };
1217
1218 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1219         .sidetone       = "mcbsp3_sidetone",
1220 };
1221
1222 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1223         .name           = "mcbsp3",
1224         .class          = &omap3xxx_mcbsp_hwmod_class,
1225         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1226         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1227         .main_clk       = "mcbsp3_fck",
1228         .prcm           = {
1229                 .omap2 = {
1230                         .prcm_reg_id = 1,
1231                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1232                         .module_offs = OMAP3430_PER_MOD,
1233                         .idlest_reg_id = 1,
1234                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1235                 },
1236         },
1237         .opt_clks       = mcbsp234_opt_clks,
1238         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1239         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1240 };
1241
1242 /* mcbsp4 */
1243 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1244         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1245         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1246         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1247         { .irq = -1 },
1248 };
1249
1250 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1251         { .name = "rx", .dma_req = 20 },
1252         { .name = "tx", .dma_req = 19 },
1253         { .dma_req = -1 }
1254 };
1255
1256 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1257         .name           = "mcbsp4",
1258         .class          = &omap3xxx_mcbsp_hwmod_class,
1259         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1260         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1261         .main_clk       = "mcbsp4_fck",
1262         .prcm           = {
1263                 .omap2 = {
1264                         .prcm_reg_id = 1,
1265                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1266                         .module_offs = OMAP3430_PER_MOD,
1267                         .idlest_reg_id = 1,
1268                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1269                 },
1270         },
1271         .opt_clks       = mcbsp234_opt_clks,
1272         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1273 };
1274
1275 /* mcbsp5 */
1276 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1277         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1278         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1279         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1280         { .irq = -1 },
1281 };
1282
1283 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1284         { .name = "rx", .dma_req = 22 },
1285         { .name = "tx", .dma_req = 21 },
1286         { .dma_req = -1 }
1287 };
1288
1289 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1290         .name           = "mcbsp5",
1291         .class          = &omap3xxx_mcbsp_hwmod_class,
1292         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1293         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1294         .main_clk       = "mcbsp5_fck",
1295         .prcm           = {
1296                 .omap2 = {
1297                         .prcm_reg_id = 1,
1298                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1299                         .module_offs = CORE_MOD,
1300                         .idlest_reg_id = 1,
1301                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1302                 },
1303         },
1304         .opt_clks       = mcbsp15_opt_clks,
1305         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1306 };
1307
1308 /* 'mcbsp sidetone' class */
1309 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1310         .sysc_offs      = 0x0010,
1311         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1312         .sysc_fields    = &omap_hwmod_sysc_type1,
1313 };
1314
1315 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1316         .name = "mcbsp_sidetone",
1317         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1318 };
1319
1320 /* mcbsp2_sidetone */
1321 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1322         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1323         { .irq = -1 },
1324 };
1325
1326 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1327         .name           = "mcbsp2_sidetone",
1328         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1329         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1330         .main_clk       = "mcbsp2_fck",
1331         .prcm           = {
1332                 .omap2 = {
1333                         .prcm_reg_id = 1,
1334                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1335                         .module_offs = OMAP3430_PER_MOD,
1336                         .idlest_reg_id = 1,
1337                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1338                 },
1339         },
1340 };
1341
1342 /* mcbsp3_sidetone */
1343 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1344         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1345         { .irq = -1 },
1346 };
1347
1348 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1349         .name           = "mcbsp3_sidetone",
1350         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1351         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1352         .main_clk       = "mcbsp3_fck",
1353         .prcm           = {
1354                 .omap2 = {
1355                         .prcm_reg_id = 1,
1356                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1357                         .module_offs = OMAP3430_PER_MOD,
1358                         .idlest_reg_id = 1,
1359                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1360                 },
1361         },
1362 };
1363
1364 /* SR common */
1365 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1366         .clkact_shift   = 20,
1367 };
1368
1369 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1370         .sysc_offs      = 0x24,
1371         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1372         .clockact       = CLOCKACT_TEST_ICLK,
1373         .sysc_fields    = &omap34xx_sr_sysc_fields,
1374 };
1375
1376 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1377         .name = "smartreflex",
1378         .sysc = &omap34xx_sr_sysc,
1379         .rev  = 1,
1380 };
1381
1382 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1383         .sidle_shift    = 24,
1384         .enwkup_shift   = 26,
1385 };
1386
1387 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1388         .sysc_offs      = 0x38,
1389         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1390         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1391                         SYSC_NO_CACHE),
1392         .sysc_fields    = &omap36xx_sr_sysc_fields,
1393 };
1394
1395 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1396         .name = "smartreflex",
1397         .sysc = &omap36xx_sr_sysc,
1398         .rev  = 2,
1399 };
1400
1401 /* SR1 */
1402 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1403         .sensor_voltdm_name   = "mpu_iva",
1404 };
1405
1406 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1407         { .irq = 18 + OMAP_INTC_START, },
1408         { .irq = -1 },
1409 };
1410
1411 static struct omap_hwmod omap34xx_sr1_hwmod = {
1412         .name           = "smartreflex_mpu_iva",
1413         .class          = &omap34xx_smartreflex_hwmod_class,
1414         .main_clk       = "sr1_fck",
1415         .prcm           = {
1416                 .omap2 = {
1417                         .prcm_reg_id = 1,
1418                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1419                         .module_offs = WKUP_MOD,
1420                         .idlest_reg_id = 1,
1421                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1422                 },
1423         },
1424         .dev_attr       = &sr1_dev_attr,
1425         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1426         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1427 };
1428
1429 static struct omap_hwmod omap36xx_sr1_hwmod = {
1430         .name           = "smartreflex_mpu_iva",
1431         .class          = &omap36xx_smartreflex_hwmod_class,
1432         .main_clk       = "sr1_fck",
1433         .prcm           = {
1434                 .omap2 = {
1435                         .prcm_reg_id = 1,
1436                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1437                         .module_offs = WKUP_MOD,
1438                         .idlest_reg_id = 1,
1439                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1440                 },
1441         },
1442         .dev_attr       = &sr1_dev_attr,
1443         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1444 };
1445
1446 /* SR2 */
1447 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1448         .sensor_voltdm_name     = "core",
1449 };
1450
1451 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1452         { .irq = 19 + OMAP_INTC_START, },
1453         { .irq = -1 },
1454 };
1455
1456 static struct omap_hwmod omap34xx_sr2_hwmod = {
1457         .name           = "smartreflex_core",
1458         .class          = &omap34xx_smartreflex_hwmod_class,
1459         .main_clk       = "sr2_fck",
1460         .prcm           = {
1461                 .omap2 = {
1462                         .prcm_reg_id = 1,
1463                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1464                         .module_offs = WKUP_MOD,
1465                         .idlest_reg_id = 1,
1466                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1467                 },
1468         },
1469         .dev_attr       = &sr2_dev_attr,
1470         .mpu_irqs       = omap3_smartreflex_core_irqs,
1471         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1472 };
1473
1474 static struct omap_hwmod omap36xx_sr2_hwmod = {
1475         .name           = "smartreflex_core",
1476         .class          = &omap36xx_smartreflex_hwmod_class,
1477         .main_clk       = "sr2_fck",
1478         .prcm           = {
1479                 .omap2 = {
1480                         .prcm_reg_id = 1,
1481                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1482                         .module_offs = WKUP_MOD,
1483                         .idlest_reg_id = 1,
1484                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1485                 },
1486         },
1487         .dev_attr       = &sr2_dev_attr,
1488         .mpu_irqs       = omap3_smartreflex_core_irqs,
1489 };
1490
1491 /*
1492  * 'mailbox' class
1493  * mailbox module allowing communication between the on-chip processors
1494  * using a queued mailbox-interrupt mechanism.
1495  */
1496
1497 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1498         .rev_offs       = 0x000,
1499         .sysc_offs      = 0x010,
1500         .syss_offs      = 0x014,
1501         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1502                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1503         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1504         .sysc_fields    = &omap_hwmod_sysc_type1,
1505 };
1506
1507 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1508         .name = "mailbox",
1509         .sysc = &omap3xxx_mailbox_sysc,
1510 };
1511
1512 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1513         { .irq = 26 + OMAP_INTC_START, },
1514         { .irq = -1 },
1515 };
1516
1517 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1518         .name           = "mailbox",
1519         .class          = &omap3xxx_mailbox_hwmod_class,
1520         .mpu_irqs       = omap3xxx_mailbox_irqs,
1521         .main_clk       = "mailboxes_ick",
1522         .prcm           = {
1523                 .omap2 = {
1524                         .prcm_reg_id = 1,
1525                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1526                         .module_offs = CORE_MOD,
1527                         .idlest_reg_id = 1,
1528                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1529                 },
1530         },
1531 };
1532
1533 /*
1534  * 'mcspi' class
1535  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1536  * bus
1537  */
1538
1539 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1540         .rev_offs       = 0x0000,
1541         .sysc_offs      = 0x0010,
1542         .syss_offs      = 0x0014,
1543         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1544                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1545                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1546         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1547         .sysc_fields    = &omap_hwmod_sysc_type1,
1548 };
1549
1550 static struct omap_hwmod_class omap34xx_mcspi_class = {
1551         .name = "mcspi",
1552         .sysc = &omap34xx_mcspi_sysc,
1553         .rev = OMAP3_MCSPI_REV,
1554 };
1555
1556 /* mcspi1 */
1557 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1558         .num_chipselect = 4,
1559 };
1560
1561 static struct omap_hwmod omap34xx_mcspi1 = {
1562         .name           = "mcspi1",
1563         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1564         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1565         .main_clk       = "mcspi1_fck",
1566         .prcm           = {
1567                 .omap2 = {
1568                         .module_offs = CORE_MOD,
1569                         .prcm_reg_id = 1,
1570                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1571                         .idlest_reg_id = 1,
1572                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1573                 },
1574         },
1575         .class          = &omap34xx_mcspi_class,
1576         .dev_attr       = &omap_mcspi1_dev_attr,
1577 };
1578
1579 /* mcspi2 */
1580 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1581         .num_chipselect = 2,
1582 };
1583
1584 static struct omap_hwmod omap34xx_mcspi2 = {
1585         .name           = "mcspi2",
1586         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1587         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1588         .main_clk       = "mcspi2_fck",
1589         .prcm           = {
1590                 .omap2 = {
1591                         .module_offs = CORE_MOD,
1592                         .prcm_reg_id = 1,
1593                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1594                         .idlest_reg_id = 1,
1595                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1596                 },
1597         },
1598         .class          = &omap34xx_mcspi_class,
1599         .dev_attr       = &omap_mcspi2_dev_attr,
1600 };
1601
1602 /* mcspi3 */
1603 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1604         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1605         { .irq = -1 },
1606 };
1607
1608 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1609         { .name = "tx0", .dma_req = 15 },
1610         { .name = "rx0", .dma_req = 16 },
1611         { .name = "tx1", .dma_req = 23 },
1612         { .name = "rx1", .dma_req = 24 },
1613         { .dma_req = -1 }
1614 };
1615
1616 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1617         .num_chipselect = 2,
1618 };
1619
1620 static struct omap_hwmod omap34xx_mcspi3 = {
1621         .name           = "mcspi3",
1622         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1623         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1624         .main_clk       = "mcspi3_fck",
1625         .prcm           = {
1626                 .omap2 = {
1627                         .module_offs = CORE_MOD,
1628                         .prcm_reg_id = 1,
1629                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1630                         .idlest_reg_id = 1,
1631                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1632                 },
1633         },
1634         .class          = &omap34xx_mcspi_class,
1635         .dev_attr       = &omap_mcspi3_dev_attr,
1636 };
1637
1638 /* mcspi4 */
1639 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1640         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1641         { .irq = -1 },
1642 };
1643
1644 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1645         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1646         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1647         { .dma_req = -1 }
1648 };
1649
1650 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1651         .num_chipselect = 1,
1652 };
1653
1654 static struct omap_hwmod omap34xx_mcspi4 = {
1655         .name           = "mcspi4",
1656         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1657         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1658         .main_clk       = "mcspi4_fck",
1659         .prcm           = {
1660                 .omap2 = {
1661                         .module_offs = CORE_MOD,
1662                         .prcm_reg_id = 1,
1663                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1664                         .idlest_reg_id = 1,
1665                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1666                 },
1667         },
1668         .class          = &omap34xx_mcspi_class,
1669         .dev_attr       = &omap_mcspi4_dev_attr,
1670 };
1671
1672 /* usbhsotg */
1673 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1674         .rev_offs       = 0x0400,
1675         .sysc_offs      = 0x0404,
1676         .syss_offs      = 0x0408,
1677         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1678                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1679                           SYSC_HAS_AUTOIDLE),
1680         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1681                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1682         .sysc_fields    = &omap_hwmod_sysc_type1,
1683 };
1684
1685 static struct omap_hwmod_class usbotg_class = {
1686         .name = "usbotg",
1687         .sysc = &omap3xxx_usbhsotg_sysc,
1688 };
1689
1690 /* usb_otg_hs */
1691 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1692
1693         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1694         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1695         { .irq = -1 },
1696 };
1697
1698 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1699         .name           = "usb_otg_hs",
1700         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1701         .main_clk       = "hsotgusb_ick",
1702         .prcm           = {
1703                 .omap2 = {
1704                         .prcm_reg_id = 1,
1705                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1706                         .module_offs = CORE_MOD,
1707                         .idlest_reg_id = 1,
1708                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1709                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1710                 },
1711         },
1712         .class          = &usbotg_class,
1713
1714         /*
1715          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1716          * broken when autoidle is enabled
1717          * workaround is to disable the autoidle bit at module level.
1718          */
1719         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1720                                 | HWMOD_SWSUP_MSTANDBY,
1721 };
1722
1723 /* usb_otg_hs */
1724 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1725         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1726         { .irq = -1 },
1727 };
1728
1729 static struct omap_hwmod_class am35xx_usbotg_class = {
1730         .name = "am35xx_usbotg",
1731 };
1732
1733 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1734         .name           = "am35x_otg_hs",
1735         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1736         .main_clk       = "hsotgusb_fck",
1737         .class          = &am35xx_usbotg_class,
1738         .flags          = HWMOD_NO_IDLEST,
1739 };
1740
1741 /* MMC/SD/SDIO common */
1742 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1743         .rev_offs       = 0x1fc,
1744         .sysc_offs      = 0x10,
1745         .syss_offs      = 0x14,
1746         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1747                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1748                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1749         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1750         .sysc_fields    = &omap_hwmod_sysc_type1,
1751 };
1752
1753 static struct omap_hwmod_class omap34xx_mmc_class = {
1754         .name = "mmc",
1755         .sysc = &omap34xx_mmc_sysc,
1756 };
1757
1758 /* MMC/SD/SDIO1 */
1759
1760 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1761         { .irq = 83 + OMAP_INTC_START, },
1762         { .irq = -1 },
1763 };
1764
1765 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1766         { .name = "tx", .dma_req = 61, },
1767         { .name = "rx", .dma_req = 62, },
1768         { .dma_req = -1 }
1769 };
1770
1771 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1772         { .role = "dbck", .clk = "omap_32k_fck", },
1773 };
1774
1775 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1776         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1777 };
1778
1779 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1780 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1781         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1782                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1783 };
1784
1785 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1786         .name           = "mmc1",
1787         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1788         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1789         .opt_clks       = omap34xx_mmc1_opt_clks,
1790         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1791         .main_clk       = "mmchs1_fck",
1792         .prcm           = {
1793                 .omap2 = {
1794                         .module_offs = CORE_MOD,
1795                         .prcm_reg_id = 1,
1796                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1797                         .idlest_reg_id = 1,
1798                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1799                 },
1800         },
1801         .dev_attr       = &mmc1_pre_es3_dev_attr,
1802         .class          = &omap34xx_mmc_class,
1803 };
1804
1805 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1806         .name           = "mmc1",
1807         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1808         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1809         .opt_clks       = omap34xx_mmc1_opt_clks,
1810         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1811         .main_clk       = "mmchs1_fck",
1812         .prcm           = {
1813                 .omap2 = {
1814                         .module_offs = CORE_MOD,
1815                         .prcm_reg_id = 1,
1816                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1817                         .idlest_reg_id = 1,
1818                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1819                 },
1820         },
1821         .dev_attr       = &mmc1_dev_attr,
1822         .class          = &omap34xx_mmc_class,
1823 };
1824
1825 /* MMC/SD/SDIO2 */
1826
1827 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1828         { .irq = 86 + OMAP_INTC_START, },
1829         { .irq = -1 },
1830 };
1831
1832 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1833         { .name = "tx", .dma_req = 47, },
1834         { .name = "rx", .dma_req = 48, },
1835         { .dma_req = -1 }
1836 };
1837
1838 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1839         { .role = "dbck", .clk = "omap_32k_fck", },
1840 };
1841
1842 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1843 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1844         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1845 };
1846
1847 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1848         .name           = "mmc2",
1849         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1850         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1851         .opt_clks       = omap34xx_mmc2_opt_clks,
1852         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1853         .main_clk       = "mmchs2_fck",
1854         .prcm           = {
1855                 .omap2 = {
1856                         .module_offs = CORE_MOD,
1857                         .prcm_reg_id = 1,
1858                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1859                         .idlest_reg_id = 1,
1860                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1861                 },
1862         },
1863         .dev_attr       = &mmc2_pre_es3_dev_attr,
1864         .class          = &omap34xx_mmc_class,
1865 };
1866
1867 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1868         .name           = "mmc2",
1869         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1870         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1871         .opt_clks       = omap34xx_mmc2_opt_clks,
1872         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1873         .main_clk       = "mmchs2_fck",
1874         .prcm           = {
1875                 .omap2 = {
1876                         .module_offs = CORE_MOD,
1877                         .prcm_reg_id = 1,
1878                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1879                         .idlest_reg_id = 1,
1880                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1881                 },
1882         },
1883         .class          = &omap34xx_mmc_class,
1884 };
1885
1886 /* MMC/SD/SDIO3 */
1887
1888 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1889         { .irq = 94 + OMAP_INTC_START, },
1890         { .irq = -1 },
1891 };
1892
1893 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1894         { .name = "tx", .dma_req = 77, },
1895         { .name = "rx", .dma_req = 78, },
1896         { .dma_req = -1 }
1897 };
1898
1899 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1900         { .role = "dbck", .clk = "omap_32k_fck", },
1901 };
1902
1903 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1904         .name           = "mmc3",
1905         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1906         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1907         .opt_clks       = omap34xx_mmc3_opt_clks,
1908         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1909         .main_clk       = "mmchs3_fck",
1910         .prcm           = {
1911                 .omap2 = {
1912                         .prcm_reg_id = 1,
1913                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1914                         .idlest_reg_id = 1,
1915                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1916                 },
1917         },
1918         .class          = &omap34xx_mmc_class,
1919 };
1920
1921 /*
1922  * 'usb_host_hs' class
1923  * high-speed multi-port usb host controller
1924  */
1925
1926 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1927         .rev_offs       = 0x0000,
1928         .sysc_offs      = 0x0010,
1929         .syss_offs      = 0x0014,
1930         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1931                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1932                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1933         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1934                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1935         .sysc_fields    = &omap_hwmod_sysc_type1,
1936 };
1937
1938 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1939         .name = "usb_host_hs",
1940         .sysc = &omap3xxx_usb_host_hs_sysc,
1941 };
1942
1943 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1944           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1945 };
1946
1947 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1948         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1949         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1950         { .irq = -1 },
1951 };
1952
1953 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1954         .name           = "usb_host_hs",
1955         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1956         .clkdm_name     = "l3_init_clkdm",
1957         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1958         .main_clk       = "usbhost_48m_fck",
1959         .prcm = {
1960                 .omap2 = {
1961                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1962                         .prcm_reg_id = 1,
1963                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1964                         .idlest_reg_id = 1,
1965                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1966                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1967                 },
1968         },
1969         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1970         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1971
1972         /*
1973          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1974          * id: i660
1975          *
1976          * Description:
1977          * In the following configuration :
1978          * - USBHOST module is set to smart-idle mode
1979          * - PRCM asserts idle_req to the USBHOST module ( This typically
1980          *   happens when the system is going to a low power mode : all ports
1981          *   have been suspended, the master part of the USBHOST module has
1982          *   entered the standby state, and SW has cut the functional clocks)
1983          * - an USBHOST interrupt occurs before the module is able to answer
1984          *   idle_ack, typically a remote wakeup IRQ.
1985          * Then the USB HOST module will enter a deadlock situation where it
1986          * is no more accessible nor functional.
1987          *
1988          * Workaround:
1989          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1990          */
1991
1992         /*
1993          * Errata: USB host EHCI may stall when entering smart-standby mode
1994          * Id: i571
1995          *
1996          * Description:
1997          * When the USBHOST module is set to smart-standby mode, and when it is
1998          * ready to enter the standby state (i.e. all ports are suspended and
1999          * all attached devices are in suspend mode), then it can wrongly assert
2000          * the Mstandby signal too early while there are still some residual OCP
2001          * transactions ongoing. If this condition occurs, the internal state
2002          * machine may go to an undefined state and the USB link may be stuck
2003          * upon the next resume.
2004          *
2005          * Workaround:
2006          * Don't use smart standby; use only force standby,
2007          * hence HWMOD_SWSUP_MSTANDBY
2008          */
2009
2010         /*
2011          * During system boot; If the hwmod framework resets the module
2012          * the module will have smart idle settings; which can lead to deadlock
2013          * (above Errata Id:i660); so, dont reset the module during boot;
2014          * Use HWMOD_INIT_NO_RESET.
2015          */
2016
2017         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2018                           HWMOD_INIT_NO_RESET,
2019 };
2020
2021 /*
2022  * 'usb_tll_hs' class
2023  * usb_tll_hs module is the adapter on the usb_host_hs ports
2024  */
2025 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2026         .rev_offs       = 0x0000,
2027         .sysc_offs      = 0x0010,
2028         .syss_offs      = 0x0014,
2029         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2030                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2031                            SYSC_HAS_AUTOIDLE),
2032         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2033         .sysc_fields    = &omap_hwmod_sysc_type1,
2034 };
2035
2036 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2037         .name = "usb_tll_hs",
2038         .sysc = &omap3xxx_usb_tll_hs_sysc,
2039 };
2040
2041 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2042         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2043         { .irq = -1 },
2044 };
2045
2046 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2047         .name           = "usb_tll_hs",
2048         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2049         .clkdm_name     = "l3_init_clkdm",
2050         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2051         .main_clk       = "usbtll_fck",
2052         .prcm = {
2053                 .omap2 = {
2054                         .module_offs = CORE_MOD,
2055                         .prcm_reg_id = 3,
2056                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2057                         .idlest_reg_id = 3,
2058                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2059                 },
2060         },
2061 };
2062
2063 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2064         .name           = "hdq1w",
2065         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2066         .main_clk       = "hdq_fck",
2067         .prcm           = {
2068                 .omap2 = {
2069                         .module_offs = CORE_MOD,
2070                         .prcm_reg_id = 1,
2071                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2072                         .idlest_reg_id = 1,
2073                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2074                 },
2075         },
2076         .class          = &omap2_hdq1w_class,
2077 };
2078
2079 /* SAD2D */
2080 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2081         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2082         { .name = "rst_modem_sw", .rst_shift = 1 },
2083 };
2084
2085 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2086         .name                   = "sad2d",
2087 };
2088
2089 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2090         .name           = "sad2d",
2091         .rst_lines      = omap3xxx_sad2d_resets,
2092         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2093         .main_clk       = "sad2d_ick",
2094         .prcm           = {
2095                 .omap2 = {
2096                         .module_offs = CORE_MOD,
2097                         .prcm_reg_id = 1,
2098                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2099                         .idlest_reg_id = 1,
2100                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2101                 },
2102         },
2103         .class          = &omap3xxx_sad2d_class,
2104 };
2105
2106 /*
2107  * '32K sync counter' class
2108  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2109  */
2110 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2111         .rev_offs       = 0x0000,
2112         .sysc_offs      = 0x0004,
2113         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2114         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2115         .sysc_fields    = &omap_hwmod_sysc_type1,
2116 };
2117
2118 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2119         .name   = "counter",
2120         .sysc   = &omap3xxx_counter_sysc,
2121 };
2122
2123 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2124         .name           = "counter_32k",
2125         .class          = &omap3xxx_counter_hwmod_class,
2126         .clkdm_name     = "wkup_clkdm",
2127         .flags          = HWMOD_SWSUP_SIDLE,
2128         .main_clk       = "wkup_32k_fck",
2129         .prcm           = {
2130                 .omap2  = {
2131                         .module_offs = WKUP_MOD,
2132                         .prcm_reg_id = 1,
2133                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2134                         .idlest_reg_id = 1,
2135                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2136                 },
2137         },
2138 };
2139
2140 /*
2141  * 'gpmc' class
2142  * general purpose memory controller
2143  */
2144
2145 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2146         .rev_offs       = 0x0000,
2147         .sysc_offs      = 0x0010,
2148         .syss_offs      = 0x0014,
2149         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2150                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2151         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2152         .sysc_fields    = &omap_hwmod_sysc_type1,
2153 };
2154
2155 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2156         .name   = "gpmc",
2157         .sysc   = &omap3xxx_gpmc_sysc,
2158 };
2159
2160 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2161         { .irq = 20 },
2162         { .irq = -1 }
2163 };
2164
2165 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2166         .name           = "gpmc",
2167         .class          = &omap3xxx_gpmc_hwmod_class,
2168         .clkdm_name     = "core_l3_clkdm",
2169         .mpu_irqs       = omap3xxx_gpmc_irqs,
2170         .main_clk       = "gpmc_fck",
2171         /*
2172          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2173          * block.  It is not being added due to any known bugs with
2174          * resetting the GPMC IP block, but rather because any timings
2175          * set by the bootloader are not being correctly programmed by
2176          * the kernel from the board file or DT data.
2177          * HWMOD_INIT_NO_RESET should be removed ASAP.
2178          */
2179         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2180                            HWMOD_NO_IDLEST),
2181 };
2182
2183 /*
2184  * interfaces
2185  */
2186
2187 /* L3 -> L4_CORE interface */
2188 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2189         .master = &omap3xxx_l3_main_hwmod,
2190         .slave  = &omap3xxx_l4_core_hwmod,
2191         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2192 };
2193
2194 /* L3 -> L4_PER interface */
2195 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2196         .master = &omap3xxx_l3_main_hwmod,
2197         .slave  = &omap3xxx_l4_per_hwmod,
2198         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2199 };
2200
2201 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2202         {
2203                 .pa_start       = 0x68000000,
2204                 .pa_end         = 0x6800ffff,
2205                 .flags          = ADDR_TYPE_RT,
2206         },
2207         { }
2208 };
2209
2210 /* MPU -> L3 interface */
2211 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2212         .master   = &omap3xxx_mpu_hwmod,
2213         .slave    = &omap3xxx_l3_main_hwmod,
2214         .addr     = omap3xxx_l3_main_addrs,
2215         .user   = OCP_USER_MPU,
2216 };
2217
2218 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2219         {
2220                 .pa_start       = 0x54000000,
2221                 .pa_end         = 0x547fffff,
2222                 .flags          = ADDR_TYPE_RT,
2223         },
2224         { }
2225 };
2226
2227 /* l3 -> debugss */
2228 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2229         .master         = &omap3xxx_l3_main_hwmod,
2230         .slave          = &omap3xxx_debugss_hwmod,
2231         .addr           = omap3xxx_l4_emu_addrs,
2232         .user           = OCP_USER_MPU,
2233 };
2234
2235 /* DSS -> l3 */
2236 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2237         .master         = &omap3430es1_dss_core_hwmod,
2238         .slave          = &omap3xxx_l3_main_hwmod,
2239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2240 };
2241
2242 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2243         .master         = &omap3xxx_dss_core_hwmod,
2244         .slave          = &omap3xxx_l3_main_hwmod,
2245         .fw = {
2246                 .omap2 = {
2247                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2248                         .flags  = OMAP_FIREWALL_L3,
2249                 }
2250         },
2251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2252 };
2253
2254 /* l3_core -> usbhsotg interface */
2255 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2256         .master         = &omap3xxx_usbhsotg_hwmod,
2257         .slave          = &omap3xxx_l3_main_hwmod,
2258         .clk            = "core_l3_ick",
2259         .user           = OCP_USER_MPU,
2260 };
2261
2262 /* l3_core -> am35xx_usbhsotg interface */
2263 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2264         .master         = &am35xx_usbhsotg_hwmod,
2265         .slave          = &omap3xxx_l3_main_hwmod,
2266         .clk            = "hsotgusb_ick",
2267         .user           = OCP_USER_MPU,
2268 };
2269
2270 /* l3_core -> sad2d interface */
2271 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2272         .master         = &omap3xxx_sad2d_hwmod,
2273         .slave          = &omap3xxx_l3_main_hwmod,
2274         .clk            = "core_l3_ick",
2275         .user           = OCP_USER_MPU,
2276 };
2277
2278 /* L4_CORE -> L4_WKUP interface */
2279 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2280         .master = &omap3xxx_l4_core_hwmod,
2281         .slave  = &omap3xxx_l4_wkup_hwmod,
2282         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2283 };
2284
2285 /* L4 CORE -> MMC1 interface */
2286 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2287         .master         = &omap3xxx_l4_core_hwmod,
2288         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2289         .clk            = "mmchs1_ick",
2290         .addr           = omap2430_mmc1_addr_space,
2291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2292         .flags          = OMAP_FIREWALL_L4
2293 };
2294
2295 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2296         .master         = &omap3xxx_l4_core_hwmod,
2297         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2298         .clk            = "mmchs1_ick",
2299         .addr           = omap2430_mmc1_addr_space,
2300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2301         .flags          = OMAP_FIREWALL_L4
2302 };
2303
2304 /* L4 CORE -> MMC2 interface */
2305 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2306         .master         = &omap3xxx_l4_core_hwmod,
2307         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2308         .clk            = "mmchs2_ick",
2309         .addr           = omap2430_mmc2_addr_space,
2310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2311         .flags          = OMAP_FIREWALL_L4
2312 };
2313
2314 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2315         .master         = &omap3xxx_l4_core_hwmod,
2316         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2317         .clk            = "mmchs2_ick",
2318         .addr           = omap2430_mmc2_addr_space,
2319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2320         .flags          = OMAP_FIREWALL_L4
2321 };
2322
2323 /* L4 CORE -> MMC3 interface */
2324 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2325         {
2326                 .pa_start       = 0x480ad000,
2327                 .pa_end         = 0x480ad1ff,
2328                 .flags          = ADDR_TYPE_RT,
2329         },
2330         { }
2331 };
2332
2333 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2334         .master         = &omap3xxx_l4_core_hwmod,
2335         .slave          = &omap3xxx_mmc3_hwmod,
2336         .clk            = "mmchs3_ick",
2337         .addr           = omap3xxx_mmc3_addr_space,
2338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2339         .flags          = OMAP_FIREWALL_L4
2340 };
2341
2342 /* L4 CORE -> UART1 interface */
2343 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2344         {
2345                 .pa_start       = OMAP3_UART1_BASE,
2346                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2347                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2348         },
2349         { }
2350 };
2351
2352 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2353         .master         = &omap3xxx_l4_core_hwmod,
2354         .slave          = &omap3xxx_uart1_hwmod,
2355         .clk            = "uart1_ick",
2356         .addr           = omap3xxx_uart1_addr_space,
2357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2358 };
2359
2360 /* L4 CORE -> UART2 interface */
2361 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2362         {
2363                 .pa_start       = OMAP3_UART2_BASE,
2364                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2365                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2366         },
2367         { }
2368 };
2369
2370 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2371         .master         = &omap3xxx_l4_core_hwmod,
2372         .slave          = &omap3xxx_uart2_hwmod,
2373         .clk            = "uart2_ick",
2374         .addr           = omap3xxx_uart2_addr_space,
2375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2376 };
2377
2378 /* L4 PER -> UART3 interface */
2379 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2380         {
2381                 .pa_start       = OMAP3_UART3_BASE,
2382                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2383                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2384         },
2385         { }
2386 };
2387
2388 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2389         .master         = &omap3xxx_l4_per_hwmod,
2390         .slave          = &omap3xxx_uart3_hwmod,
2391         .clk            = "uart3_ick",
2392         .addr           = omap3xxx_uart3_addr_space,
2393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2394 };
2395
2396 /* L4 PER -> UART4 interface */
2397 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2398         {
2399                 .pa_start       = OMAP3_UART4_BASE,
2400                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2401                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2402         },
2403         { }
2404 };
2405
2406 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2407         .master         = &omap3xxx_l4_per_hwmod,
2408         .slave          = &omap36xx_uart4_hwmod,
2409         .clk            = "uart4_ick",
2410         .addr           = omap36xx_uart4_addr_space,
2411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2412 };
2413
2414 /* AM35xx: L4 CORE -> UART4 interface */
2415 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2416         {
2417                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2418                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2419                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2420         },
2421         { }
2422 };
2423
2424 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2425         .master         = &omap3xxx_l4_core_hwmod,
2426         .slave          = &am35xx_uart4_hwmod,
2427         .clk            = "uart4_ick",
2428         .addr           = am35xx_uart4_addr_space,
2429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2430 };
2431
2432 /* L4 CORE -> I2C1 interface */
2433 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2434         .master         = &omap3xxx_l4_core_hwmod,
2435         .slave          = &omap3xxx_i2c1_hwmod,
2436         .clk            = "i2c1_ick",
2437         .addr           = omap2_i2c1_addr_space,
2438         .fw = {
2439                 .omap2 = {
2440                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2441                         .l4_prot_group = 7,
2442                         .flags  = OMAP_FIREWALL_L4,
2443                 }
2444         },
2445         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2446 };
2447
2448 /* L4 CORE -> I2C2 interface */
2449 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2450         .master         = &omap3xxx_l4_core_hwmod,
2451         .slave          = &omap3xxx_i2c2_hwmod,
2452         .clk            = "i2c2_ick",
2453         .addr           = omap2_i2c2_addr_space,
2454         .fw = {
2455                 .omap2 = {
2456                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2457                         .l4_prot_group = 7,
2458                         .flags = OMAP_FIREWALL_L4,
2459                 }
2460         },
2461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2462 };
2463
2464 /* L4 CORE -> I2C3 interface */
2465 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2466         {
2467                 .pa_start       = 0x48060000,
2468                 .pa_end         = 0x48060000 + SZ_128 - 1,
2469                 .flags          = ADDR_TYPE_RT,
2470         },
2471         { }
2472 };
2473
2474 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2475         .master         = &omap3xxx_l4_core_hwmod,
2476         .slave          = &omap3xxx_i2c3_hwmod,
2477         .clk            = "i2c3_ick",
2478         .addr           = omap3xxx_i2c3_addr_space,
2479         .fw = {
2480                 .omap2 = {
2481                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2482                         .l4_prot_group = 7,
2483                         .flags = OMAP_FIREWALL_L4,
2484                 }
2485         },
2486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2487 };
2488
2489 /* L4 CORE -> SR1 interface */
2490 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2491         {
2492                 .pa_start       = OMAP34XX_SR1_BASE,
2493                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2494                 .flags          = ADDR_TYPE_RT,
2495         },
2496         { }
2497 };
2498
2499 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2500         .master         = &omap3xxx_l4_core_hwmod,
2501         .slave          = &omap34xx_sr1_hwmod,
2502         .clk            = "sr_l4_ick",
2503         .addr           = omap3_sr1_addr_space,
2504         .user           = OCP_USER_MPU,
2505 };
2506
2507 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2508         .master         = &omap3xxx_l4_core_hwmod,
2509         .slave          = &omap36xx_sr1_hwmod,
2510         .clk            = "sr_l4_ick",
2511         .addr           = omap3_sr1_addr_space,
2512         .user           = OCP_USER_MPU,
2513 };
2514
2515 /* L4 CORE -> SR1 interface */
2516 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2517         {
2518                 .pa_start       = OMAP34XX_SR2_BASE,
2519                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2520                 .flags          = ADDR_TYPE_RT,
2521         },
2522         { }
2523 };
2524
2525 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2526         .master         = &omap3xxx_l4_core_hwmod,
2527         .slave          = &omap34xx_sr2_hwmod,
2528         .clk            = "sr_l4_ick",
2529         .addr           = omap3_sr2_addr_space,
2530         .user           = OCP_USER_MPU,
2531 };
2532
2533 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2534         .master         = &omap3xxx_l4_core_hwmod,
2535         .slave          = &omap36xx_sr2_hwmod,
2536         .clk            = "sr_l4_ick",
2537         .addr           = omap3_sr2_addr_space,
2538         .user           = OCP_USER_MPU,
2539 };
2540
2541 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2542         {
2543                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2544                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2545                 .flags          = ADDR_TYPE_RT
2546         },
2547         { }
2548 };
2549
2550 /* l4_core -> usbhsotg  */
2551 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2552         .master         = &omap3xxx_l4_core_hwmod,
2553         .slave          = &omap3xxx_usbhsotg_hwmod,
2554         .clk            = "l4_ick",
2555         .addr           = omap3xxx_usbhsotg_addrs,
2556         .user           = OCP_USER_MPU,
2557 };
2558
2559 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2560         {
2561                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2562                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2563                 .flags          = ADDR_TYPE_RT
2564         },
2565         { }
2566 };
2567
2568 /* l4_core -> usbhsotg  */
2569 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2570         .master         = &omap3xxx_l4_core_hwmod,
2571         .slave          = &am35xx_usbhsotg_hwmod,
2572         .clk            = "hsotgusb_ick",
2573         .addr           = am35xx_usbhsotg_addrs,
2574         .user           = OCP_USER_MPU,
2575 };
2576
2577 /* L4_WKUP -> L4_SEC interface */
2578 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2579         .master = &omap3xxx_l4_wkup_hwmod,
2580         .slave  = &omap3xxx_l4_sec_hwmod,
2581         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2582 };
2583
2584 /* IVA2 <- L3 interface */
2585 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2586         .master         = &omap3xxx_l3_main_hwmod,
2587         .slave          = &omap3xxx_iva_hwmod,
2588         .clk            = "core_l3_ick",
2589         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2590 };
2591
2592 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2593         {
2594                 .pa_start       = 0x48318000,
2595                 .pa_end         = 0x48318000 + SZ_1K - 1,
2596                 .flags          = ADDR_TYPE_RT
2597         },
2598         { }
2599 };
2600
2601 /* l4_wkup -> timer1 */
2602 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2603         .master         = &omap3xxx_l4_wkup_hwmod,
2604         .slave          = &omap3xxx_timer1_hwmod,
2605         .clk            = "gpt1_ick",
2606         .addr           = omap3xxx_timer1_addrs,
2607         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2608 };
2609
2610 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2611         {
2612                 .pa_start       = 0x49032000,
2613                 .pa_end         = 0x49032000 + SZ_1K - 1,
2614                 .flags          = ADDR_TYPE_RT
2615         },
2616         { }
2617 };
2618
2619 /* l4_per -> timer2 */
2620 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2621         .master         = &omap3xxx_l4_per_hwmod,
2622         .slave          = &omap3xxx_timer2_hwmod,
2623         .clk            = "gpt2_ick",
2624         .addr           = omap3xxx_timer2_addrs,
2625         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2626 };
2627
2628 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2629         {
2630                 .pa_start       = 0x49034000,
2631                 .pa_end         = 0x49034000 + SZ_1K - 1,
2632                 .flags          = ADDR_TYPE_RT
2633         },
2634         { }
2635 };
2636
2637 /* l4_per -> timer3 */
2638 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2639         .master         = &omap3xxx_l4_per_hwmod,
2640         .slave          = &omap3xxx_timer3_hwmod,
2641         .clk            = "gpt3_ick",
2642         .addr           = omap3xxx_timer3_addrs,
2643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2644 };
2645
2646 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2647         {
2648                 .pa_start       = 0x49036000,
2649                 .pa_end         = 0x49036000 + SZ_1K - 1,
2650                 .flags          = ADDR_TYPE_RT
2651         },
2652         { }
2653 };
2654
2655 /* l4_per -> timer4 */
2656 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2657         .master         = &omap3xxx_l4_per_hwmod,
2658         .slave          = &omap3xxx_timer4_hwmod,
2659         .clk            = "gpt4_ick",
2660         .addr           = omap3xxx_timer4_addrs,
2661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2662 };
2663
2664 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2665         {
2666                 .pa_start       = 0x49038000,
2667                 .pa_end         = 0x49038000 + SZ_1K - 1,
2668                 .flags          = ADDR_TYPE_RT
2669         },
2670         { }
2671 };
2672
2673 /* l4_per -> timer5 */
2674 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2675         .master         = &omap3xxx_l4_per_hwmod,
2676         .slave          = &omap3xxx_timer5_hwmod,
2677         .clk            = "gpt5_ick",
2678         .addr           = omap3xxx_timer5_addrs,
2679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2680 };
2681
2682 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2683         {
2684                 .pa_start       = 0x4903A000,
2685                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2686                 .flags          = ADDR_TYPE_RT
2687         },
2688         { }
2689 };
2690
2691 /* l4_per -> timer6 */
2692 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2693         .master         = &omap3xxx_l4_per_hwmod,
2694         .slave          = &omap3xxx_timer6_hwmod,
2695         .clk            = "gpt6_ick",
2696         .addr           = omap3xxx_timer6_addrs,
2697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2698 };
2699
2700 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2701         {
2702                 .pa_start       = 0x4903C000,
2703                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2704                 .flags          = ADDR_TYPE_RT
2705         },
2706         { }
2707 };
2708
2709 /* l4_per -> timer7 */
2710 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2711         .master         = &omap3xxx_l4_per_hwmod,
2712         .slave          = &omap3xxx_timer7_hwmod,
2713         .clk            = "gpt7_ick",
2714         .addr           = omap3xxx_timer7_addrs,
2715         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2716 };
2717
2718 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2719         {
2720                 .pa_start       = 0x4903E000,
2721                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2722                 .flags          = ADDR_TYPE_RT
2723         },
2724         { }
2725 };
2726
2727 /* l4_per -> timer8 */
2728 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2729         .master         = &omap3xxx_l4_per_hwmod,
2730         .slave          = &omap3xxx_timer8_hwmod,
2731         .clk            = "gpt8_ick",
2732         .addr           = omap3xxx_timer8_addrs,
2733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2734 };
2735
2736 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2737         {
2738                 .pa_start       = 0x49040000,
2739                 .pa_end         = 0x49040000 + SZ_1K - 1,
2740                 .flags          = ADDR_TYPE_RT
2741         },
2742         { }
2743 };
2744
2745 /* l4_per -> timer9 */
2746 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2747         .master         = &omap3xxx_l4_per_hwmod,
2748         .slave          = &omap3xxx_timer9_hwmod,
2749         .clk            = "gpt9_ick",
2750         .addr           = omap3xxx_timer9_addrs,
2751         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2752 };
2753
2754 /* l4_core -> timer10 */
2755 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2756         .master         = &omap3xxx_l4_core_hwmod,
2757         .slave          = &omap3xxx_timer10_hwmod,
2758         .clk            = "gpt10_ick",
2759         .addr           = omap2_timer10_addrs,
2760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2761 };
2762
2763 /* l4_core -> timer11 */
2764 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2765         .master         = &omap3xxx_l4_core_hwmod,
2766         .slave          = &omap3xxx_timer11_hwmod,
2767         .clk            = "gpt11_ick",
2768         .addr           = omap2_timer11_addrs,
2769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2770 };
2771
2772 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2773         {
2774                 .pa_start       = 0x48304000,
2775                 .pa_end         = 0x48304000 + SZ_1K - 1,
2776                 .flags          = ADDR_TYPE_RT
2777         },
2778         { }
2779 };
2780
2781 /* l4_core -> timer12 */
2782 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2783         .master         = &omap3xxx_l4_sec_hwmod,
2784         .slave          = &omap3xxx_timer12_hwmod,
2785         .clk            = "gpt12_ick",
2786         .addr           = omap3xxx_timer12_addrs,
2787         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2788 };
2789
2790 /* l4_wkup -> wd_timer2 */
2791 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2792         {
2793                 .pa_start       = 0x48314000,
2794                 .pa_end         = 0x4831407f,
2795                 .flags          = ADDR_TYPE_RT
2796         },
2797         { }
2798 };
2799
2800 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2801         .master         = &omap3xxx_l4_wkup_hwmod,
2802         .slave          = &omap3xxx_wd_timer2_hwmod,
2803         .clk            = "wdt2_ick",
2804         .addr           = omap3xxx_wd_timer2_addrs,
2805         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2806 };
2807
2808 /* l4_core -> dss */
2809 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2810         .master         = &omap3xxx_l4_core_hwmod,
2811         .slave          = &omap3430es1_dss_core_hwmod,
2812         .clk            = "dss_ick",
2813         .addr           = omap2_dss_addrs,
2814         .fw = {
2815                 .omap2 = {
2816                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2817                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2818                         .flags  = OMAP_FIREWALL_L4,
2819                 }
2820         },
2821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2822 };
2823
2824 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2825         .master         = &omap3xxx_l4_core_hwmod,
2826         .slave          = &omap3xxx_dss_core_hwmod,
2827         .clk            = "dss_ick",
2828         .addr           = omap2_dss_addrs,
2829         .fw = {
2830                 .omap2 = {
2831                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2832                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2833                         .flags  = OMAP_FIREWALL_L4,
2834                 }
2835         },
2836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2837 };
2838
2839 /* l4_core -> dss_dispc */
2840 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2841         .master         = &omap3xxx_l4_core_hwmod,
2842         .slave          = &omap3xxx_dss_dispc_hwmod,
2843         .clk            = "dss_ick",
2844         .addr           = omap2_dss_dispc_addrs,
2845         .fw = {
2846                 .omap2 = {
2847                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2848                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2849                         .flags  = OMAP_FIREWALL_L4,
2850                 }
2851         },
2852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2853 };
2854
2855 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2856         {
2857                 .pa_start       = 0x4804FC00,
2858                 .pa_end         = 0x4804FFFF,
2859                 .flags          = ADDR_TYPE_RT
2860         },
2861         { }
2862 };
2863
2864 /* l4_core -> dss_dsi1 */
2865 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2866         .master         = &omap3xxx_l4_core_hwmod,
2867         .slave          = &omap3xxx_dss_dsi1_hwmod,
2868         .clk            = "dss_ick",
2869         .addr           = omap3xxx_dss_dsi1_addrs,
2870         .fw = {
2871                 .omap2 = {
2872                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2873                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2874                         .flags  = OMAP_FIREWALL_L4,
2875                 }
2876         },
2877         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2878 };
2879
2880 /* l4_core -> dss_rfbi */
2881 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2882         .master         = &omap3xxx_l4_core_hwmod,
2883         .slave          = &omap3xxx_dss_rfbi_hwmod,
2884         .clk            = "dss_ick",
2885         .addr           = omap2_dss_rfbi_addrs,
2886         .fw = {
2887                 .omap2 = {
2888                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2889                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2890                         .flags  = OMAP_FIREWALL_L4,
2891                 }
2892         },
2893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2894 };
2895
2896 /* l4_core -> dss_venc */
2897 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2898         .master         = &omap3xxx_l4_core_hwmod,
2899         .slave          = &omap3xxx_dss_venc_hwmod,
2900         .clk            = "dss_ick",
2901         .addr           = omap2_dss_venc_addrs,
2902         .fw = {
2903                 .omap2 = {
2904                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2905                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2906                         .flags  = OMAP_FIREWALL_L4,
2907                 }
2908         },
2909         .flags          = OCPIF_SWSUP_IDLE,
2910         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2911 };
2912
2913 /* l4_wkup -> gpio1 */
2914 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2915         {
2916                 .pa_start       = 0x48310000,
2917                 .pa_end         = 0x483101ff,
2918                 .flags          = ADDR_TYPE_RT
2919         },
2920         { }
2921 };
2922
2923 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2924         .master         = &omap3xxx_l4_wkup_hwmod,
2925         .slave          = &omap3xxx_gpio1_hwmod,
2926         .addr           = omap3xxx_gpio1_addrs,
2927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2928 };
2929
2930 /* l4_per -> gpio2 */
2931 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2932         {
2933                 .pa_start       = 0x49050000,
2934                 .pa_end         = 0x490501ff,
2935                 .flags          = ADDR_TYPE_RT
2936         },
2937         { }
2938 };
2939
2940 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2941         .master         = &omap3xxx_l4_per_hwmod,
2942         .slave          = &omap3xxx_gpio2_hwmod,
2943         .addr           = omap3xxx_gpio2_addrs,
2944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2945 };
2946
2947 /* l4_per -> gpio3 */
2948 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2949         {
2950                 .pa_start       = 0x49052000,
2951                 .pa_end         = 0x490521ff,
2952                 .flags          = ADDR_TYPE_RT
2953         },
2954         { }
2955 };
2956
2957 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2958         .master         = &omap3xxx_l4_per_hwmod,
2959         .slave          = &omap3xxx_gpio3_hwmod,
2960         .addr           = omap3xxx_gpio3_addrs,
2961         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2962 };
2963
2964 /*
2965  * 'mmu' class
2966  * The memory management unit performs virtual to physical address translation
2967  * for its requestors.
2968  */
2969
2970 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2971         .rev_offs       = 0x000,
2972         .sysc_offs      = 0x010,
2973         .syss_offs      = 0x014,
2974         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2975                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2976         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2977         .sysc_fields    = &omap_hwmod_sysc_type1,
2978 };
2979
2980 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2981         .name = "mmu",
2982         .sysc = &mmu_sysc,
2983 };
2984
2985 /* mmu isp */
2986
2987 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2988         .da_start       = 0x0,
2989         .da_end         = 0xfffff000,
2990         .nr_tlb_entries = 8,
2991 };
2992
2993 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2994 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2995         { .irq = 24 },
2996         { .irq = -1 }
2997 };
2998
2999 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
3000         {
3001                 .pa_start       = 0x480bd400,
3002                 .pa_end         = 0x480bd47f,
3003                 .flags          = ADDR_TYPE_RT,
3004         },
3005         { }
3006 };
3007
3008 /* l4_core -> mmu isp */
3009 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3010         .master         = &omap3xxx_l4_core_hwmod,
3011         .slave          = &omap3xxx_mmu_isp_hwmod,
3012         .addr           = omap3xxx_mmu_isp_addrs,
3013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3014 };
3015
3016 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3017         .name           = "mmu_isp",
3018         .class          = &omap3xxx_mmu_hwmod_class,
3019         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
3020         .main_clk       = "cam_ick",
3021         .dev_attr       = &mmu_isp_dev_attr,
3022         .flags          = HWMOD_NO_IDLEST,
3023 };
3024
3025 #ifdef CONFIG_OMAP_IOMMU_IVA2
3026
3027 /* mmu iva */
3028
3029 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3030         .da_start       = 0x11000000,
3031         .da_end         = 0xfffff000,
3032         .nr_tlb_entries = 32,
3033 };
3034
3035 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3036 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3037         { .irq = 28 },
3038         { .irq = -1 }
3039 };
3040
3041 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3042         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3043 };
3044
3045 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3046         {
3047                 .pa_start       = 0x5d000000,
3048                 .pa_end         = 0x5d00007f,
3049                 .flags          = ADDR_TYPE_RT,
3050         },
3051         { }
3052 };
3053
3054 /* l3_main -> iva mmu */
3055 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3056         .master         = &omap3xxx_l3_main_hwmod,
3057         .slave          = &omap3xxx_mmu_iva_hwmod,
3058         .addr           = omap3xxx_mmu_iva_addrs,
3059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3060 };
3061
3062 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3063         .name           = "mmu_iva",
3064         .class          = &omap3xxx_mmu_hwmod_class,
3065         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3066         .rst_lines      = omap3xxx_mmu_iva_resets,
3067         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3068         .main_clk       = "iva2_ck",
3069         .prcm = {
3070                 .omap2 = {
3071                         .module_offs = OMAP3430_IVA2_MOD,
3072                 },
3073         },
3074         .dev_attr       = &mmu_iva_dev_attr,
3075         .flags          = HWMOD_NO_IDLEST,
3076 };
3077
3078 #endif
3079
3080 /* l4_per -> gpio4 */
3081 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3082         {
3083                 .pa_start       = 0x49054000,
3084                 .pa_end         = 0x490541ff,
3085                 .flags          = ADDR_TYPE_RT
3086         },
3087         { }
3088 };
3089
3090 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3091         .master         = &omap3xxx_l4_per_hwmod,
3092         .slave          = &omap3xxx_gpio4_hwmod,
3093         .addr           = omap3xxx_gpio4_addrs,
3094         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3095 };
3096
3097 /* l4_per -> gpio5 */
3098 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3099         {
3100                 .pa_start       = 0x49056000,
3101                 .pa_end         = 0x490561ff,
3102                 .flags          = ADDR_TYPE_RT
3103         },
3104         { }
3105 };
3106
3107 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3108         .master         = &omap3xxx_l4_per_hwmod,
3109         .slave          = &omap3xxx_gpio5_hwmod,
3110         .addr           = omap3xxx_gpio5_addrs,
3111         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3112 };
3113
3114 /* l4_per -> gpio6 */
3115 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3116         {
3117                 .pa_start       = 0x49058000,
3118                 .pa_end         = 0x490581ff,
3119                 .flags          = ADDR_TYPE_RT
3120         },
3121         { }
3122 };
3123
3124 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3125         .master         = &omap3xxx_l4_per_hwmod,
3126         .slave          = &omap3xxx_gpio6_hwmod,
3127         .addr           = omap3xxx_gpio6_addrs,
3128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 /* dma_system -> L3 */
3132 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3133         .master         = &omap3xxx_dma_system_hwmod,
3134         .slave          = &omap3xxx_l3_main_hwmod,
3135         .clk            = "core_l3_ick",
3136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3137 };
3138
3139 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3140         {
3141                 .pa_start       = 0x48056000,
3142                 .pa_end         = 0x48056fff,
3143                 .flags          = ADDR_TYPE_RT
3144         },
3145         { }
3146 };
3147
3148 /* l4_cfg -> dma_system */
3149 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3150         .master         = &omap3xxx_l4_core_hwmod,
3151         .slave          = &omap3xxx_dma_system_hwmod,
3152         .clk            = "core_l4_ick",
3153         .addr           = omap3xxx_dma_system_addrs,
3154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3155 };
3156
3157 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3158         {
3159                 .name           = "mpu",
3160                 .pa_start       = 0x48074000,
3161                 .pa_end         = 0x480740ff,
3162                 .flags          = ADDR_TYPE_RT
3163         },
3164         { }
3165 };
3166
3167 /* l4_core -> mcbsp1 */
3168 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3169         .master         = &omap3xxx_l4_core_hwmod,
3170         .slave          = &omap3xxx_mcbsp1_hwmod,
3171         .clk            = "mcbsp1_ick",
3172         .addr           = omap3xxx_mcbsp1_addrs,
3173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3174 };
3175
3176 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3177         {
3178                 .name           = "mpu",
3179                 .pa_start       = 0x49022000,
3180                 .pa_end         = 0x490220ff,
3181                 .flags          = ADDR_TYPE_RT
3182         },
3183         { }
3184 };
3185
3186 /* l4_per -> mcbsp2 */
3187 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3188         .master         = &omap3xxx_l4_per_hwmod,
3189         .slave          = &omap3xxx_mcbsp2_hwmod,
3190         .clk            = "mcbsp2_ick",
3191         .addr           = omap3xxx_mcbsp2_addrs,
3192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3193 };
3194
3195 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3196         {
3197                 .name           = "mpu",
3198                 .pa_start       = 0x49024000,
3199                 .pa_end         = 0x490240ff,
3200                 .flags          = ADDR_TYPE_RT
3201         },
3202         { }
3203 };
3204
3205 /* l4_per -> mcbsp3 */
3206 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3207         .master         = &omap3xxx_l4_per_hwmod,
3208         .slave          = &omap3xxx_mcbsp3_hwmod,
3209         .clk            = "mcbsp3_ick",
3210         .addr           = omap3xxx_mcbsp3_addrs,
3211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3212 };
3213
3214 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3215         {
3216                 .name           = "mpu",
3217                 .pa_start       = 0x49026000,
3218                 .pa_end         = 0x490260ff,
3219                 .flags          = ADDR_TYPE_RT
3220         },
3221         { }
3222 };
3223
3224 /* l4_per -> mcbsp4 */
3225 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3226         .master         = &omap3xxx_l4_per_hwmod,
3227         .slave          = &omap3xxx_mcbsp4_hwmod,
3228         .clk            = "mcbsp4_ick",
3229         .addr           = omap3xxx_mcbsp4_addrs,
3230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3231 };
3232
3233 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3234         {
3235                 .name           = "mpu",
3236                 .pa_start       = 0x48096000,
3237                 .pa_end         = 0x480960ff,
3238                 .flags          = ADDR_TYPE_RT
3239         },
3240         { }
3241 };
3242
3243 /* l4_core -> mcbsp5 */
3244 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3245         .master         = &omap3xxx_l4_core_hwmod,
3246         .slave          = &omap3xxx_mcbsp5_hwmod,
3247         .clk            = "mcbsp5_ick",
3248         .addr           = omap3xxx_mcbsp5_addrs,
3249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3250 };
3251
3252 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3253         {
3254                 .name           = "sidetone",
3255                 .pa_start       = 0x49028000,
3256                 .pa_end         = 0x490280ff,
3257                 .flags          = ADDR_TYPE_RT
3258         },
3259         { }
3260 };
3261
3262 /* l4_per -> mcbsp2_sidetone */
3263 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3264         .master         = &omap3xxx_l4_per_hwmod,
3265         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3266         .clk            = "mcbsp2_ick",
3267         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3268         .user           = OCP_USER_MPU,
3269 };
3270
3271 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3272         {
3273                 .name           = "sidetone",
3274                 .pa_start       = 0x4902A000,
3275                 .pa_end         = 0x4902A0ff,
3276                 .flags          = ADDR_TYPE_RT
3277         },
3278         { }
3279 };
3280
3281 /* l4_per -> mcbsp3_sidetone */
3282 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3283         .master         = &omap3xxx_l4_per_hwmod,
3284         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3285         .clk            = "mcbsp3_ick",
3286         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3287         .user           = OCP_USER_MPU,
3288 };
3289
3290 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3291         {
3292                 .pa_start       = 0x48094000,
3293                 .pa_end         = 0x480941ff,
3294                 .flags          = ADDR_TYPE_RT,
3295         },
3296         { }
3297 };
3298
3299 /* l4_core -> mailbox */
3300 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3301         .master         = &omap3xxx_l4_core_hwmod,
3302         .slave          = &omap3xxx_mailbox_hwmod,
3303         .addr           = omap3xxx_mailbox_addrs,
3304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3305 };
3306
3307 /* l4 core -> mcspi1 interface */
3308 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3309         .master         = &omap3xxx_l4_core_hwmod,
3310         .slave          = &omap34xx_mcspi1,
3311         .clk            = "mcspi1_ick",
3312         .addr           = omap2_mcspi1_addr_space,
3313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3314 };
3315
3316 /* l4 core -> mcspi2 interface */
3317 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3318         .master         = &omap3xxx_l4_core_hwmod,
3319         .slave          = &omap34xx_mcspi2,
3320         .clk            = "mcspi2_ick",
3321         .addr           = omap2_mcspi2_addr_space,
3322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3323 };
3324
3325 /* l4 core -> mcspi3 interface */
3326 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3327         .master         = &omap3xxx_l4_core_hwmod,
3328         .slave          = &omap34xx_mcspi3,
3329         .clk            = "mcspi3_ick",
3330         .addr           = omap2430_mcspi3_addr_space,
3331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3332 };
3333
3334 /* l4 core -> mcspi4 interface */
3335 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3336         {
3337                 .pa_start       = 0x480ba000,
3338                 .pa_end         = 0x480ba0ff,
3339                 .flags          = ADDR_TYPE_RT,
3340         },
3341         { }
3342 };
3343
3344 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3345         .master         = &omap3xxx_l4_core_hwmod,
3346         .slave          = &omap34xx_mcspi4,
3347         .clk            = "mcspi4_ick",
3348         .addr           = omap34xx_mcspi4_addr_space,
3349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3350 };
3351
3352 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3353         .master         = &omap3xxx_usb_host_hs_hwmod,
3354         .slave          = &omap3xxx_l3_main_hwmod,
3355         .clk            = "core_l3_ick",
3356         .user           = OCP_USER_MPU,
3357 };
3358
3359 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3360         {
3361                 .name           = "uhh",
3362                 .pa_start       = 0x48064000,
3363                 .pa_end         = 0x480643ff,
3364                 .flags          = ADDR_TYPE_RT
3365         },
3366         {
3367                 .name           = "ohci",
3368                 .pa_start       = 0x48064400,
3369                 .pa_end         = 0x480647ff,
3370         },
3371         {
3372                 .name           = "ehci",
3373                 .pa_start       = 0x48064800,
3374                 .pa_end         = 0x48064cff,
3375         },
3376         {}
3377 };
3378
3379 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3380         .master         = &omap3xxx_l4_core_hwmod,
3381         .slave          = &omap3xxx_usb_host_hs_hwmod,
3382         .clk            = "usbhost_ick",
3383         .addr           = omap3xxx_usb_host_hs_addrs,
3384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3385 };
3386
3387 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3388         {
3389                 .name           = "tll",
3390                 .pa_start       = 0x48062000,
3391                 .pa_end         = 0x48062fff,
3392                 .flags          = ADDR_TYPE_RT
3393         },
3394         {}
3395 };
3396
3397 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3398         .master         = &omap3xxx_l4_core_hwmod,
3399         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3400         .clk            = "usbtll_ick",
3401         .addr           = omap3xxx_usb_tll_hs_addrs,
3402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3403 };
3404
3405 /* l4_core -> hdq1w interface */
3406 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3407         .master         = &omap3xxx_l4_core_hwmod,
3408         .slave          = &omap3xxx_hdq1w_hwmod,
3409         .clk            = "hdq_ick",
3410         .addr           = omap2_hdq1w_addr_space,
3411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3412         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3413 };
3414
3415 /* l4_wkup -> 32ksync_counter */
3416 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3417         {
3418                 .pa_start       = 0x48320000,
3419                 .pa_end         = 0x4832001f,
3420                 .flags          = ADDR_TYPE_RT
3421         },
3422         { }
3423 };
3424
3425 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3426         {
3427                 .pa_start       = 0x6e000000,
3428                 .pa_end         = 0x6e000fff,
3429                 .flags          = ADDR_TYPE_RT
3430         },
3431         { }
3432 };
3433
3434 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3435         .master         = &omap3xxx_l4_wkup_hwmod,
3436         .slave          = &omap3xxx_counter_32k_hwmod,
3437         .clk            = "omap_32ksync_ick",
3438         .addr           = omap3xxx_counter_32k_addrs,
3439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3440 };
3441
3442 /* am35xx has Davinci MDIO & EMAC */
3443 static struct omap_hwmod_class am35xx_mdio_class = {
3444         .name = "davinci_mdio",
3445 };
3446
3447 static struct omap_hwmod am35xx_mdio_hwmod = {
3448         .name           = "davinci_mdio",
3449         .class          = &am35xx_mdio_class,
3450         .flags          = HWMOD_NO_IDLEST,
3451 };
3452
3453 /*
3454  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3455  * but this will probably require some additional hwmod core support,
3456  * so is left as a future to-do item.
3457  */
3458 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3459         .master         = &am35xx_mdio_hwmod,
3460         .slave          = &omap3xxx_l3_main_hwmod,
3461         .clk            = "emac_fck",
3462         .user           = OCP_USER_MPU,
3463 };
3464
3465 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3466         {
3467                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3468                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3469                 .flags          = ADDR_TYPE_RT,
3470         },
3471         { }
3472 };
3473
3474 /* l4_core -> davinci mdio  */
3475 /*
3476  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3477  * but this will probably require some additional hwmod core support,
3478  * so is left as a future to-do item.
3479  */
3480 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3481         .master         = &omap3xxx_l4_core_hwmod,
3482         .slave          = &am35xx_mdio_hwmod,
3483         .clk            = "emac_fck",
3484         .addr           = am35xx_mdio_addrs,
3485         .user           = OCP_USER_MPU,
3486 };
3487
3488 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3489         { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
3490         { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
3491         { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
3492         { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3493         { .irq = -1 },
3494 };
3495
3496 static struct omap_hwmod_class am35xx_emac_class = {
3497         .name = "davinci_emac",
3498 };
3499
3500 static struct omap_hwmod am35xx_emac_hwmod = {
3501         .name           = "davinci_emac",
3502         .mpu_irqs       = am35xx_emac_mpu_irqs,
3503         .class          = &am35xx_emac_class,
3504         .flags          = HWMOD_NO_IDLEST,
3505 };
3506
3507 /* l3_core -> davinci emac interface */
3508 /*
3509  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3510  * but this will probably require some additional hwmod core support,
3511  * so is left as a future to-do item.
3512  */
3513 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3514         .master         = &am35xx_emac_hwmod,
3515         .slave          = &omap3xxx_l3_main_hwmod,
3516         .clk            = "emac_ick",
3517         .user           = OCP_USER_MPU,
3518 };
3519
3520 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3521         {
3522                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3523                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3524                 .flags          = ADDR_TYPE_RT,
3525         },
3526         { }
3527 };
3528
3529 /* l4_core -> davinci emac  */
3530 /*
3531  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3532  * but this will probably require some additional hwmod core support,
3533  * so is left as a future to-do item.
3534  */
3535 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3536         .master         = &omap3xxx_l4_core_hwmod,
3537         .slave          = &am35xx_emac_hwmod,
3538         .clk            = "emac_ick",
3539         .addr           = am35xx_emac_addrs,
3540         .user           = OCP_USER_MPU,
3541 };
3542
3543 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3544         .master         = &omap3xxx_l3_main_hwmod,
3545         .slave          = &omap3xxx_gpmc_hwmod,
3546         .clk            = "core_l3_ick",
3547         .addr           = omap3xxx_gpmc_addrs,
3548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3549 };
3550
3551 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3552         &omap3xxx_l3_main__l4_core,
3553         &omap3xxx_l3_main__l4_per,
3554         &omap3xxx_mpu__l3_main,
3555         &omap3xxx_l3_main__l4_debugss,
3556         &omap3xxx_l4_core__l4_wkup,
3557         &omap3xxx_l4_core__mmc3,
3558         &omap3_l4_core__uart1,
3559         &omap3_l4_core__uart2,
3560         &omap3_l4_per__uart3,
3561         &omap3_l4_core__i2c1,
3562         &omap3_l4_core__i2c2,
3563         &omap3_l4_core__i2c3,
3564         &omap3xxx_l4_wkup__l4_sec,
3565         &omap3xxx_l4_wkup__timer1,
3566         &omap3xxx_l4_per__timer2,
3567         &omap3xxx_l4_per__timer3,
3568         &omap3xxx_l4_per__timer4,
3569         &omap3xxx_l4_per__timer5,
3570         &omap3xxx_l4_per__timer6,
3571         &omap3xxx_l4_per__timer7,
3572         &omap3xxx_l4_per__timer8,
3573         &omap3xxx_l4_per__timer9,
3574         &omap3xxx_l4_core__timer10,
3575         &omap3xxx_l4_core__timer11,
3576         &omap3xxx_l4_wkup__wd_timer2,
3577         &omap3xxx_l4_wkup__gpio1,
3578         &omap3xxx_l4_per__gpio2,
3579         &omap3xxx_l4_per__gpio3,
3580         &omap3xxx_l4_per__gpio4,
3581         &omap3xxx_l4_per__gpio5,
3582         &omap3xxx_l4_per__gpio6,
3583         &omap3xxx_dma_system__l3,
3584         &omap3xxx_l4_core__dma_system,
3585         &omap3xxx_l4_core__mcbsp1,
3586         &omap3xxx_l4_per__mcbsp2,
3587         &omap3xxx_l4_per__mcbsp3,
3588         &omap3xxx_l4_per__mcbsp4,
3589         &omap3xxx_l4_core__mcbsp5,
3590         &omap3xxx_l4_per__mcbsp2_sidetone,
3591         &omap3xxx_l4_per__mcbsp3_sidetone,
3592         &omap34xx_l4_core__mcspi1,
3593         &omap34xx_l4_core__mcspi2,
3594         &omap34xx_l4_core__mcspi3,
3595         &omap34xx_l4_core__mcspi4,
3596         &omap3xxx_l4_wkup__counter_32k,
3597         &omap3xxx_l3_main__gpmc,
3598         NULL,
3599 };
3600
3601 /* GP-only hwmod links */
3602 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3603         &omap3xxx_l4_sec__timer12,
3604         NULL
3605 };
3606
3607 /* 3430ES1-only hwmod links */
3608 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3609         &omap3430es1_dss__l3,
3610         &omap3430es1_l4_core__dss,
3611         NULL
3612 };
3613
3614 /* 3430ES2+-only hwmod links */
3615 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3616         &omap3xxx_dss__l3,
3617         &omap3xxx_l4_core__dss,
3618         &omap3xxx_usbhsotg__l3,
3619         &omap3xxx_l4_core__usbhsotg,
3620         &omap3xxx_usb_host_hs__l3_main_2,
3621         &omap3xxx_l4_core__usb_host_hs,
3622         &omap3xxx_l4_core__usb_tll_hs,
3623         NULL
3624 };
3625
3626 /* <= 3430ES3-only hwmod links */
3627 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3628         &omap3xxx_l4_core__pre_es3_mmc1,
3629         &omap3xxx_l4_core__pre_es3_mmc2,
3630         NULL
3631 };
3632
3633 /* 3430ES3+-only hwmod links */
3634 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3635         &omap3xxx_l4_core__es3plus_mmc1,
3636         &omap3xxx_l4_core__es3plus_mmc2,
3637         NULL
3638 };
3639
3640 /* 34xx-only hwmod links (all ES revisions) */
3641 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3642         &omap3xxx_l3__iva,
3643         &omap34xx_l4_core__sr1,
3644         &omap34xx_l4_core__sr2,
3645         &omap3xxx_l4_core__mailbox,
3646         &omap3xxx_l4_core__hdq1w,
3647         &omap3xxx_sad2d__l3,
3648         &omap3xxx_l4_core__mmu_isp,
3649 #ifdef CONFIG_OMAP_IOMMU_IVA2
3650         &omap3xxx_l3_main__mmu_iva,
3651 #endif
3652         NULL
3653 };
3654
3655 /* 36xx-only hwmod links (all ES revisions) */
3656 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3657         &omap3xxx_l3__iva,
3658         &omap36xx_l4_per__uart4,
3659         &omap3xxx_dss__l3,
3660         &omap3xxx_l4_core__dss,
3661         &omap36xx_l4_core__sr1,
3662         &omap36xx_l4_core__sr2,
3663         &omap3xxx_usbhsotg__l3,
3664         &omap3xxx_l4_core__usbhsotg,
3665         &omap3xxx_l4_core__mailbox,
3666         &omap3xxx_usb_host_hs__l3_main_2,
3667         &omap3xxx_l4_core__usb_host_hs,
3668         &omap3xxx_l4_core__usb_tll_hs,
3669         &omap3xxx_l4_core__es3plus_mmc1,
3670         &omap3xxx_l4_core__es3plus_mmc2,
3671         &omap3xxx_l4_core__hdq1w,
3672         &omap3xxx_sad2d__l3,
3673         &omap3xxx_l4_core__mmu_isp,
3674 #ifdef CONFIG_OMAP_IOMMU_IVA2
3675         &omap3xxx_l3_main__mmu_iva,
3676 #endif
3677         NULL
3678 };
3679
3680 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3681         &omap3xxx_dss__l3,
3682         &omap3xxx_l4_core__dss,
3683         &am35xx_usbhsotg__l3,
3684         &am35xx_l4_core__usbhsotg,
3685         &am35xx_l4_core__uart4,
3686         &omap3xxx_usb_host_hs__l3_main_2,
3687         &omap3xxx_l4_core__usb_host_hs,
3688         &omap3xxx_l4_core__usb_tll_hs,
3689         &omap3xxx_l4_core__es3plus_mmc1,
3690         &omap3xxx_l4_core__es3plus_mmc2,
3691         &omap3xxx_l4_core__hdq1w,
3692         &am35xx_mdio__l3,
3693         &am35xx_l4_core__mdio,
3694         &am35xx_emac__l3,
3695         &am35xx_l4_core__emac,
3696         NULL
3697 };
3698
3699 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3700         &omap3xxx_l4_core__dss_dispc,
3701         &omap3xxx_l4_core__dss_dsi1,
3702         &omap3xxx_l4_core__dss_rfbi,
3703         &omap3xxx_l4_core__dss_venc,
3704         NULL
3705 };
3706
3707 int __init omap3xxx_hwmod_init(void)
3708 {
3709         int r;
3710         struct omap_hwmod_ocp_if **h = NULL;
3711         unsigned int rev;
3712
3713         omap_hwmod_init();
3714
3715         /* Register hwmod links common to all OMAP3 */
3716         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3717         if (r < 0)
3718                 return r;
3719
3720         /* Register GP-only hwmod links. */
3721         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3722                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3723                 if (r < 0)
3724                         return r;
3725         }
3726
3727         rev = omap_rev();
3728
3729         /*
3730          * Register hwmod links common to individual OMAP3 families, all
3731          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3732          * All possible revisions should be included in this conditional.
3733          */
3734         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3735             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3736             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3737                 h = omap34xx_hwmod_ocp_ifs;
3738         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3739                 h = am35xx_hwmod_ocp_ifs;
3740         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3741                    rev == OMAP3630_REV_ES1_2) {
3742                 h = omap36xx_hwmod_ocp_ifs;
3743         } else {
3744                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3745                 return -EINVAL;
3746         }
3747
3748         r = omap_hwmod_register_links(h);
3749         if (r < 0)
3750                 return r;
3751
3752         /*
3753          * Register hwmod links specific to certain ES levels of a
3754          * particular family of silicon (e.g., 34xx ES1.0)
3755          */
3756         h = NULL;
3757         if (rev == OMAP3430_REV_ES1_0) {
3758                 h = omap3430es1_hwmod_ocp_ifs;
3759         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3760                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3761                    rev == OMAP3430_REV_ES3_1_2) {
3762                 h = omap3430es2plus_hwmod_ocp_ifs;
3763         }
3764
3765         if (h) {
3766                 r = omap_hwmod_register_links(h);
3767                 if (r < 0)
3768                         return r;
3769         }
3770
3771         h = NULL;
3772         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3773             rev == OMAP3430_REV_ES2_1) {
3774                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3775         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3776                    rev == OMAP3430_REV_ES3_1_2) {
3777                 h = omap3430_es3plus_hwmod_ocp_ifs;
3778         }
3779
3780         if (h)
3781                 r = omap_hwmod_register_links(h);
3782         if (r < 0)
3783                 return r;
3784
3785         /*
3786          * DSS code presumes that dss_core hwmod is handled first,
3787          * _before_ any other DSS related hwmods so register common
3788          * DSS hwmod links last to ensure that dss_core is already
3789          * registered.  Otherwise some change things may happen, for
3790          * ex. if dispc is handled before dss_core and DSS is enabled
3791          * in bootloader DISPC will be reset with outputs enabled
3792          * which sometimes leads to unrecoverable L3 error.  XXX The
3793          * long-term fix to this is to ensure hwmods are set up in
3794          * dependency order in the hwmod core code.
3795          */
3796         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3797
3798         return r;
3799 }