drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8192c/fw_common.h"
  41 #include "dm.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 #define LLT_CONFIG      5
  46
  47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  48                                       u8 set_bits, u8 clear_bits)
  49 {
  50         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52
  53         rtlpci->reg_bcn_ctrl_val |= set_bits;
  54         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  55
  56         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  57 }
  58
  59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  60 {
  61         struct rtl_priv *rtlpriv = rtl_priv(hw);
  62         u8 tmp1byte;
  63
  64         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  65         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  66         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  67         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  68         tmp1byte &= ~(BIT(0));
  69         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  70 }
  71
  72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  73 {
  74         struct rtl_priv *rtlpriv = rtl_priv(hw);
  75         u8 tmp1byte;
  76
  77         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  78         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  79         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  80         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  81         tmp1byte |= BIT(0);
  82         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  83 }
  84
  85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  86 {
  87         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  88 }
  89
  90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  91 {
  92         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  93 }
  94
  95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  96 {
  97         struct rtl_priv *rtlpriv = rtl_priv(hw);
  98         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  99         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 100
 101         switch (variable) {
 102         case HW_VAR_RCR:
 103                 *((u32 *) (val)) = rtlpci->receive_config;
 104                 break;
 105         case HW_VAR_RF_STATE:
 106                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 107                 break;
 108         case HW_VAR_FWLPS_RF_ON:{
 109                         enum rf_pwrstate rfState;
 110                         u32 val_rcr;
 111
 112                         rtlpriv->cfg->ops->get_hw_reg(hw,
 113                                                       HW_VAR_RF_STATE,
 114                                                       (u8 *) (&rfState));
 115                         if (rfState == ERFOFF) {
 116                                 *((bool *) (val)) = true;
 117                         } else {
 118                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 119                                 val_rcr &= 0x00070000;
 120                                 if (val_rcr)
 121                                         *((bool *) (val)) = false;
 122                                 else
 123                                         *((bool *) (val)) = true;
 124                         }
 125                         break;
 126                 }
 127         case HW_VAR_FW_PSMODE_STATUS:
 128                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
 129                 break;
 130         case HW_VAR_CORRECT_TSF:{
 131                 u64 tsf;
 132                 u32 *ptsf_low = (u32 *)&tsf;
 133                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 134
 135                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 136                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 137
 138                 *((u64 *) (val)) = tsf;
 139
 140                 break;
 141                 }
 142         default:
 143                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 144                          "switch case not processed\n");
 145                 break;
 146         }
 147 }
 148
 149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 150 {
 151         struct rtl_priv *rtlpriv = rtl_priv(hw);
 152         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 153         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 154         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 155         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 156         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 157         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 158         u8 idx;
 159
 160         switch (variable) {
 161         case HW_VAR_ETHER_ADDR:{
 162                         for (idx = 0; idx < ETH_ALEN; idx++) {
 163                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 164                                                val[idx]);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_BASIC_RATE:{
 169                         u16 rate_cfg = ((u16 *) val)[0];
 170                         u8 rate_index = 0;
 171                         rate_cfg &= 0x15f;
 172                         rate_cfg |= 0x01;
 173                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
 174                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 175                                        (rate_cfg >> 8) & 0xff);
 176                         while (rate_cfg > 0x1) {
 177                                 rate_cfg = (rate_cfg >> 1);
 178                                 rate_index++;
 179                         }
 180                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 181                                        rate_index);
 182                         break;
 183                 }
 184         case HW_VAR_BSSID:{
 185                         for (idx = 0; idx < ETH_ALEN; idx++) {
 186                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 187                                                val[idx]);
 188                         }
 189                         break;
 190                 }
 191         case HW_VAR_SIFS:{
 192                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 193                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 194
 195                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 196                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 197
 198                         if (!mac->ht_enable)
 199                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 200                                                0x0e0e);
 201                         else
 202                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 203                                                *((u16 *) val));
 204                         break;
 205                 }
 206         case HW_VAR_SLOT_TIME:{
 207                         u8 e_aci;
 208
 209                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 210                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 211
 212                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 213
 214                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 215                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 216                                                               HW_VAR_AC_PARAM,
 217                                                               &e_aci);
 218                         }
 219                         break;
 220                 }
 221         case HW_VAR_ACK_PREAMBLE:{
 222                         u8 reg_tmp;
 223                         u8 short_preamble = (bool)*val;
 224                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 225                         if (short_preamble)
 226                                 reg_tmp |= 0x80;
 227
 228                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 229                         break;
 230                 }
 231         case HW_VAR_AMPDU_MIN_SPACE:{
 232                         u8 min_spacing_to_set;
 233                         u8 sec_min_space;
 234
 235                         min_spacing_to_set = *val;
 236                         if (min_spacing_to_set <= 7) {
 237                                 sec_min_space = 0;
 238
 239                                 if (min_spacing_to_set < sec_min_space)
 240                                         min_spacing_to_set = sec_min_space;
 241
 242                                 mac->min_space_cfg = ((mac->min_space_cfg &
 243                                                        0xf8) |
 244                                                       min_spacing_to_set);
 245
 246                                 *val = min_spacing_to_set;
 247
 248                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 249                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 250                                          mac->min_space_cfg);
 251
 252                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 253                                                mac->min_space_cfg);
 254                         }
 255                         break;
 256                 }
 257         case HW_VAR_SHORTGI_DENSITY:{
 258                         u8 density_to_set;
 259
 260                         density_to_set = *val;
 261                         mac->min_space_cfg |= (density_to_set << 3);
 262
 263                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 264                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 265                                  mac->min_space_cfg);
 266
 267                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 268                                        mac->min_space_cfg);
 269
 270                         break;
 271                 }
 272         case HW_VAR_AMPDU_FACTOR:{
 273                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 274                         u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
 275
 276                         u8 factor_toset;
 277                         u8 *p_regtoset = NULL;
 278                         u8 index = 0;
 279
 280                         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 281                             (rtlpcipriv->bt_coexist.bt_coexist_type ==
 282                             BT_CSR_BC4))
 283                                 p_regtoset = regtoset_bt;
 284                         else
 285                                 p_regtoset = regtoset_normal;
 286
 287                         factor_toset = *(val);
 288                         if (factor_toset <= 3) {
 289                                 factor_toset = (1 << (factor_toset + 2));
 290                                 if (factor_toset > 0xf)
 291                                         factor_toset = 0xf;
 292
 293                                 for (index = 0; index < 4; index++) {
 294                                         if ((p_regtoset[index] & 0xf0) >
 295                                             (factor_toset << 4))
 296                                                 p_regtoset[index] =
 297                                                     (p_regtoset[index] & 0x0f) |
 298                                                     (factor_toset << 4);
 299
 300                                         if ((p_regtoset[index] & 0x0f) >
 301                                             factor_toset)
 302                                                 p_regtoset[index] =
 303                                                     (p_regtoset[index] & 0xf0) |
 304                                                     (factor_toset);
 305
 306                                         rtl_write_byte(rtlpriv,
 307                                                        (REG_AGGLEN_LMT + index),
 308                                                        p_regtoset[index]);
 309
 310                                 }
 311
 312                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 313                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 314                                          factor_toset);
 315                         }
 316                         break;
 317                 }
 318         case HW_VAR_AC_PARAM:{
 319                         u8 e_aci = *(val);
 320                         rtl92c_dm_init_edca_turbo(hw);
 321
 322                         if (rtlpci->acm_method != eAcmWay2_SW)
 323                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 324                                                               HW_VAR_ACM_CTRL,
 325                                                               (&e_aci));
 326                         break;
 327                 }
 328         case HW_VAR_ACM_CTRL:{
 329                         u8 e_aci = *(val);
 330                         union aci_aifsn *p_aci_aifsn =
 331                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 332                         u8 acm = p_aci_aifsn->f.acm;
 333                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 334
 335                         acm_ctrl =
 336                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 337
 338                         if (acm) {
 339                                 switch (e_aci) {
 340                                 case AC0_BE:
 341                                         acm_ctrl |= AcmHw_BeqEn;
 342                                         break;
 343                                 case AC2_VI:
 344                                         acm_ctrl |= AcmHw_ViqEn;
 345                                         break;
 346                                 case AC3_VO:
 347                                         acm_ctrl |= AcmHw_VoqEn;
 348                                         break;
 349                                 default:
 350                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 351                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 352                                                  acm);
 353                                         break;
 354                                 }
 355                         } else {
 356                                 switch (e_aci) {
 357                                 case AC0_BE:
 358                                         acm_ctrl &= (~AcmHw_BeqEn);
 359                                         break;
 360                                 case AC2_VI:
 361                                         acm_ctrl &= (~AcmHw_ViqEn);
 362                                         break;
 363                                 case AC3_VO:
 364                                         acm_ctrl &= (~AcmHw_BeqEn);
 365                                         break;
 366                                 default:
 367                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 368                                                  "switch case not processed\n");
 369                                         break;
 370                                 }
 371                         }
 372
 373                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 374                                  "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 375                                  acm_ctrl);
 376                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 377                         break;
 378                 }
 379         case HW_VAR_RCR:{
 380                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 381                         rtlpci->receive_config = ((u32 *) (val))[0];
 382                         break;
 383                 }
 384         case HW_VAR_RETRY_LIMIT:{
 385                         u8 retry_limit = val[0];
 386
 387                         rtl_write_word(rtlpriv, REG_RL,
 388                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 389                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 390                         break;
 391                 }
 392         case HW_VAR_DUAL_TSF_RST:
 393                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 394                 break;
 395         case HW_VAR_EFUSE_BYTES:
 396                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 397                 break;
 398         case HW_VAR_EFUSE_USAGE:
 399                 rtlefuse->efuse_usedpercentage = *val;
 400                 break;
 401         case HW_VAR_IO_CMD:
 402                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 403                 break;
 404         case HW_VAR_WPA_CONFIG:
 405                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 406                 break;
 407         case HW_VAR_SET_RPWM:{
 408                         u8 rpwm_val;
 409
 410                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 411                         udelay(1);
 412
 413                         if (rpwm_val & BIT(7)) {
 414                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 415                         } else {
 416                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 417                                                *val | BIT(7));
 418                         }
 419
 420                         break;
 421                 }
 422         case HW_VAR_H2C_FW_PWRMODE:{
 423                         u8 psmode = *val;
 424
 425                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 426                             (!IS_92C_SERIAL(rtlhal->version))) {
 427                                 rtl92c_dm_rf_saving(hw, true);
 428                         }
 429
 430                         rtl92c_set_fw_pwrmode_cmd(hw, *val);
 431                         break;
 432                 }
 433         case HW_VAR_FW_PSMODE_STATUS:
 434                 ppsc->fw_current_inpsmode = *((bool *) val);
 435                 break;
 436         case HW_VAR_H2C_FW_JOINBSSRPT:{
 437                         u8 mstatus = *val;
 438                         u8 tmp_regcr, tmp_reg422;
 439                         bool recover = false;
 440
 441                         if (mstatus == RT_MEDIA_CONNECT) {
 442                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 443                                                               NULL);
 444
 445                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 446                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 447                                                (tmp_regcr | BIT(0)));
 448
 449                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 450                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 451
 452                                 tmp_reg422 =
 453                                     rtl_read_byte(rtlpriv,
 454                                                   REG_FWHW_TXQ_CTRL + 2);
 455                                 if (tmp_reg422 & BIT(6))
 456                                         recover = true;
 457                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 458                                                tmp_reg422 & (~BIT(6)));
 459
 460                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 461
 462                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 463                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 464
 465                                 if (recover) {
 466                                         rtl_write_byte(rtlpriv,
 467                                                        REG_FWHW_TXQ_CTRL + 2,
 468                                                        tmp_reg422);
 469                                 }
 470
 471                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 472                                                (tmp_regcr & ~(BIT(0))));
 473                         }
 474                         rtl92c_set_fw_joinbss_report_cmd(hw, *val);
 475
 476                         break;
 477                 }
 478         case HW_VAR_AID:{
 479                         u16 u2btmp;
 480                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 481                         u2btmp &= 0xC000;
 482                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 483                                                 mac->assoc_id));
 484
 485                         break;
 486                 }
 487         case HW_VAR_CORRECT_TSF:{
 488                         u8 btype_ibss = val[0];
 489
 490                         if (btype_ibss)
 491                                 _rtl92ce_stop_tx_beacon(hw);
 492
 493                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 494
 495                         rtl_write_dword(rtlpriv, REG_TSFTR,
 496                                         (u32) (mac->tsf & 0xffffffff));
 497                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 498                                         (u32) ((mac->tsf >> 32) & 0xffffffff));
 499
 500                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 501
 502                         if (btype_ibss)
 503                                 _rtl92ce_resume_tx_beacon(hw);
 504
 505                         break;
 506
 507                 }
 508         default:
 509                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 510                          "switch case not processed\n");
 511                 break;
 512         }
 513 }
 514
 515 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 516 {
 517         struct rtl_priv *rtlpriv = rtl_priv(hw);
 518         bool status = true;
 519         long count = 0;
 520         u32 value = _LLT_INIT_ADDR(address) |
 521             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 522
 523         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 524
 525         do {
 526                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 527                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 528                         break;
 529
 530                 if (count > POLLING_LLT_THRESHOLD) {
 531                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 532                                  "Failed to polling write LLT done at address %d!\n",
 533                                  address);
 534                         status = false;
 535                         break;
 536                 }
 537         } while (++count);
 538
 539         return status;
 540 }
 541
 542 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 543 {
 544         struct rtl_priv *rtlpriv = rtl_priv(hw);
 545         unsigned short i;
 546         u8 txpktbuf_bndy;
 547         u8 maxPage;
 548         bool status;
 549
 550 #if LLT_CONFIG == 1
 551         maxPage = 255;
 552         txpktbuf_bndy = 252;
 553 #elif LLT_CONFIG == 2
 554         maxPage = 127;
 555         txpktbuf_bndy = 124;
 556 #elif LLT_CONFIG == 3
 557         maxPage = 255;
 558         txpktbuf_bndy = 174;
 559 #elif LLT_CONFIG == 4
 560         maxPage = 255;
 561         txpktbuf_bndy = 246;
 562 #elif LLT_CONFIG == 5
 563         maxPage = 255;
 564         txpktbuf_bndy = 246;
 565 #endif
 566
 567 #if LLT_CONFIG == 1
 568         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 569         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 570 #elif LLT_CONFIG == 2
 571         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 572 #elif LLT_CONFIG == 3
 573         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 574 #elif LLT_CONFIG == 4
 575         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 576 #elif LLT_CONFIG == 5
 577         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 578
 579         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 580 #endif
 581
 582         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 583         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 584
 585         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 586         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 587
 588         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 589         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 590         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 591
 592         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 593                 status = _rtl92ce_llt_write(hw, i, i + 1);
 594                 if (true != status)
 595                         return status;
 596         }
 597
 598         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 599         if (true != status)
 600                 return status;
 601
 602         for (i = txpktbuf_bndy; i < maxPage; i++) {
 603                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 604                 if (true != status)
 605                         return status;
 606         }
 607
 608         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 609         if (true != status)
 610                 return status;
 611
 612         return true;
 613 }
 614
 615 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 616 {
 617         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 618         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 619         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 620         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 621
 622         if (rtlpci->up_first_time)
 623                 return;
 624
 625         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 626                 rtl92ce_sw_led_on(hw, pLed0);
 627         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 628                 rtl92ce_sw_led_on(hw, pLed0);
 629         else
 630                 rtl92ce_sw_led_off(hw, pLed0);
 631 }
 632
 633 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 634 {
 635         struct rtl_priv *rtlpriv = rtl_priv(hw);
 636         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 637         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 638         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 639
 640         unsigned char bytetmp;
 641         unsigned short wordtmp;
 642         u16 retry;
 643
 644         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 645         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 646                 u32 value32;
 647                 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
 648                 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
 649                 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
 650         }
 651         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 652         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 653
 654         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 655                 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
 656
 657                 u4b_tmp &= (~0x00024800);
 658                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
 659         }
 660
 661         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 662         udelay(2);
 663
 664         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 665         udelay(2);
 666
 667         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 668         udelay(2);
 669
 670         retry = 0;
 671         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 672                  rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 673
 674         while ((bytetmp & BIT(0)) && retry < 1000) {
 675                 retry++;
 676                 udelay(50);
 677                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 678                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
 679                          rtl_read_dword(rtlpriv, 0xEC), bytetmp);
 680                 udelay(50);
 681         }
 682
 683         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 684
 685         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 686         udelay(2);
 687
 688         if (rtlpcipriv->bt_coexist.bt_coexistence) {
 689                 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
 690                 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
 691         }
 692
 693         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 694
 695         if (!_rtl92ce_llt_table_init(hw))
 696                 return false;
 697
 698         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 699         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 700
 701         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 702
 703         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 704         wordtmp &= 0xf;
 705         wordtmp |= 0xF771;
 706         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 707
 708         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 709         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 710         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 711
 712         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 713
 714         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 715                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 716                         DMA_BIT_MASK(32));
 717         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 718                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 719                         DMA_BIT_MASK(32));
 720         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 721                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 722         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 723                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 724         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 725                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 726         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 727                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 728         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 729                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 730                         DMA_BIT_MASK(32));
 731         rtl_write_dword(rtlpriv, REG_RX_DESA,
 732                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 733                         DMA_BIT_MASK(32));
 734
 735         if (IS_92C_SERIAL(rtlhal->version))
 736                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 737         else
 738                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 739
 740         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 741
 742         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 743         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 744         do {
 745                 retry++;
 746                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 747         } while ((retry < 200) && (bytetmp & BIT(7)));
 748
 749         _rtl92ce_gen_refresh_led_state(hw);
 750
 751         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 752
 753         return true;
 754 }
 755
 756 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 757 {
 758         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 759         struct rtl_priv *rtlpriv = rtl_priv(hw);
 760         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 761         u8 reg_bw_opmode;
 762         u32 reg_prsr;
 763
 764         reg_bw_opmode = BW_OPMODE_20MHZ;
 765         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 766
 767         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 768
 769         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 770
 771         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 772
 773         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 774
 775         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 776
 777         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 778
 779         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 780
 781         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 782
 783         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 784
 785         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 786         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 787         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 788         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 789
 790         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 791             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 792                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
 793         else
 794                 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 795
 796         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 797
 798         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 799
 800         rtlpci->reg_bcn_ctrl_val = 0x1f;
 801         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 802
 803         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 804
 805         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 806
 807         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 808         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 809
 810         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 811             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
 812                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 813                 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
 814         } else {
 815                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 816                 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 817         }
 818
 819         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
 820              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
 821                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 822         else
 823                 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 824
 825         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 826
 827         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 828         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 829
 830         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 831
 832         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 833
 834         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 835         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 836
 837 }
 838
 839 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 840 {
 841         struct rtl_priv *rtlpriv = rtl_priv(hw);
 842         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 843
 844         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 845         rtl_write_word(rtlpriv, 0x350, 0x870c);
 846         rtl_write_byte(rtlpriv, 0x352, 0x1);
 847
 848         if (ppsc->support_backdoor)
 849                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 850         else
 851                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 852
 853         rtl_write_word(rtlpriv, 0x350, 0x2718);
 854         rtl_write_byte(rtlpriv, 0x352, 0x1);
 855 }
 856
 857 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 858 {
 859         struct rtl_priv *rtlpriv = rtl_priv(hw);
 860         u8 sec_reg_value;
 861
 862         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 863                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 864                  rtlpriv->sec.pairwise_enc_algorithm,
 865                  rtlpriv->sec.group_enc_algorithm);
 866
 867         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 868                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 869                          "not open hw encryption\n");
 870                 return;
 871         }
 872
 873         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 874
 875         if (rtlpriv->sec.use_defaultkey) {
 876                 sec_reg_value |= SCR_TxUseDK;
 877                 sec_reg_value |= SCR_RxUseDK;
 878         }
 879
 880         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 881
 882         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 883
 884         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 885                  "The SECR-value %x\n", sec_reg_value);
 886
 887         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 888
 889 }
 890
 891 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 892 {
 893         struct rtl_priv *rtlpriv = rtl_priv(hw);
 894         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 895         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 896         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 897         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 898         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 899         bool rtstatus = true;
 900         bool is92c;
 901         int err;
 902         u8 tmp_u1b;
 903
 904         rtlpci->being_init_adapter = true;
 905         rtlpriv->intf_ops->disable_aspm(hw);
 906         rtstatus = _rtl92ce_init_mac(hw);
 907         if (!rtstatus) {
 908                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
 909                 err = 1;
 910                 return err;
 911         }
 912
 913         err = rtl92c_download_fw(hw);
 914         if (err) {
 915                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 916                          "Failed to download FW. Init HW without FW now..\n");
 917                 err = 1;
 918                 return err;
 919         }
 920
 921         rtlhal->last_hmeboxnum = 0;
 922         rtl92c_phy_mac_config(hw);
 923         /* because last function modify RCR, so we update
 924          * rcr var here, or TP will unstable for receive_config
 925          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
 926          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
 927         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
 928         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
 929         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 930         rtl92c_phy_bb_config(hw);
 931         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 932         rtl92c_phy_rf_config(hw);
 933         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
 934             !IS_92C_SERIAL(rtlhal->version)) {
 935                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
 936                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
 937         } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
 938                 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
 939                 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
 940                 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
 941                 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
 942                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
 943                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
 944         }
 945         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 946                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 947         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 948                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 949         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 950         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 951         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 952         _rtl92ce_hw_configure(hw);
 953         rtl_cam_reset_all_entry(hw);
 954         rtl92ce_enable_hw_security_config(hw);
 955
 956         ppsc->rfpwr_state = ERFON;
 957
 958         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 959         _rtl92ce_enable_aspm_back_door(hw);
 960         rtlpriv->intf_ops->enable_aspm(hw);
 961
 962         rtl8192ce_bt_hw_init(hw);
 963
 964         if (ppsc->rfpwr_state == ERFON) {
 965                 rtl92c_phy_set_rfpath_switch(hw, 1);
 966                 if (rtlphy->iqk_initialized) {
 967                         rtl92c_phy_iq_calibrate(hw, true);
 968                 } else {
 969                         rtl92c_phy_iq_calibrate(hw, false);
 970                         rtlphy->iqk_initialized = true;
 971                 }
 972
 973                 rtl92c_dm_check_txpower_tracking(hw);
 974                 rtl92c_phy_lc_calibrate(hw);
 975         }
 976
 977         is92c = IS_92C_SERIAL(rtlhal->version);
 978         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 979         if (!(tmp_u1b & BIT(0))) {
 980                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 981                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
 982         }
 983
 984         if (!(tmp_u1b & BIT(1)) && is92c) {
 985                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 986                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
 987         }
 988
 989         if (!(tmp_u1b & BIT(4))) {
 990                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 991                 tmp_u1b &= 0x0F;
 992                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 993                 udelay(10);
 994                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
 995                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
 996         }
 997         rtl92c_dm_init(hw);
 998         rtlpci->being_init_adapter = false;
 999         return err;
1000 }
1001
1002 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1003 {
1004         struct rtl_priv *rtlpriv = rtl_priv(hw);
1005         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1006         enum version_8192c version = VERSION_UNKNOWN;
1007         u32 value32;
1008         const char *versionid;
1009
1010         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1011         if (value32 & TRP_VAUX_EN) {
1012                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1013                            VERSION_A_CHIP_88C;
1014         } else {
1015                 version = (enum version_8192c) (CHIP_VER_B |
1016                                 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1017                                 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1018                 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1019                      CHIP_VER_RTL_MASK)) {
1020                         version = (enum version_8192c)(version |
1021                                    ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1022                                    ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1023                                    CHIP_VENDOR_UMC));
1024                 }
1025                 if (IS_92C_SERIAL(version)) {
1026                         value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1027                         version = (enum version_8192c)(version |
1028                                    ((CHIP_BONDING_IDENTIFIER(value32)
1029                                    == CHIP_BONDING_92C_1T2R) ?
1030                                    RF_TYPE_1T2R : 0));
1031                 }
1032         }
1033
1034         switch (version) {
1035         case VERSION_B_CHIP_92C:
1036                 versionid = "B_CHIP_92C";
1037                 break;
1038         case VERSION_B_CHIP_88C:
1039                 versionid = "B_CHIP_88C";
1040                 break;
1041         case VERSION_A_CHIP_92C:
1042                 versionid = "A_CHIP_92C";
1043                 break;
1044         case VERSION_A_CHIP_88C:
1045                 versionid = "A_CHIP_88C";
1046                 break;
1047         case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1048                 versionid = "A_CUT_92C_1T2R";
1049                 break;
1050         case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1051                 versionid = "A_CUT_92C";
1052                 break;
1053         case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1054                 versionid = "A_CUT_88C";
1055                 break;
1056         case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1057                 versionid = "B_CUT_92C_1T2R";
1058                 break;
1059         case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1060                 versionid = "B_CUT_92C";
1061                 break;
1062         case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1063                 versionid = "B_CUT_88C";
1064                 break;
1065         default:
1066                 versionid = "Unknown. Bug?";
1067                 break;
1068         }
1069
1070         RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1071                  "Chip Version ID: %s\n", versionid);
1072
1073         switch (version & 0x3) {
1074         case CHIP_88C:
1075                 rtlphy->rf_type = RF_1T1R;
1076                 break;
1077         case CHIP_92C:
1078                 rtlphy->rf_type = RF_2T2R;
1079                 break;
1080         case CHIP_92C_1T2R:
1081                 rtlphy->rf_type = RF_1T2R;
1082                 break;
1083         default:
1084                 rtlphy->rf_type = RF_1T1R;
1085                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1086                          "ERROR RF_Type is set!!\n");
1087                 break;
1088         }
1089
1090         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1091                  rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1092
1093         return version;
1094 }
1095
1096 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1097                                      enum nl80211_iftype type)
1098 {
1099         struct rtl_priv *rtlpriv = rtl_priv(hw);
1100         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1101         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1102         bt_msr &= 0xfc;
1103
1104         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1105             type == NL80211_IFTYPE_STATION) {
1106                 _rtl92ce_stop_tx_beacon(hw);
1107                 _rtl92ce_enable_bcn_sub_func(hw);
1108         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1109                 _rtl92ce_resume_tx_beacon(hw);
1110                 _rtl92ce_disable_bcn_sub_func(hw);
1111         } else {
1112                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1113                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1114                          type);
1115         }
1116
1117         switch (type) {
1118         case NL80211_IFTYPE_UNSPECIFIED:
1119                 bt_msr |= MSR_NOLINK;
1120                 ledaction = LED_CTL_LINK;
1121                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1122                          "Set Network type to NO LINK!\n");
1123                 break;
1124         case NL80211_IFTYPE_ADHOC:
1125                 bt_msr |= MSR_ADHOC;
1126                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1127                          "Set Network type to Ad Hoc!\n");
1128                 break;
1129         case NL80211_IFTYPE_STATION:
1130                 bt_msr |= MSR_INFRA;
1131                 ledaction = LED_CTL_LINK;
1132                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1133                          "Set Network type to STA!\n");
1134                 break;
1135         case NL80211_IFTYPE_AP:
1136                 bt_msr |= MSR_AP;
1137                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1138                          "Set Network type to AP!\n");
1139                 break;
1140         default:
1141                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1142                          "Network type %d not supported!\n", type);
1143                 return 1;
1144                 break;
1145
1146         }
1147
1148         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1149         rtlpriv->cfg->ops->led_control(hw, ledaction);
1150         if ((bt_msr & 0xfc) == MSR_AP)
1151                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1152         else
1153                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1154         return 0;
1155 }
1156
1157 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1158 {
1159         struct rtl_priv *rtlpriv = rtl_priv(hw);
1160         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1161
1162         if (rtlpriv->psc.rfpwr_state != ERFON)
1163                 return;
1164
1165         if (check_bssid) {
1166                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1167                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1168                                               (u8 *) (&reg_rcr));
1169                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1170         } else if (!check_bssid) {
1171                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1172                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1173                 rtlpriv->cfg->ops->set_hw_reg(hw,
1174                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1175         }
1176
1177 }
1178
1179 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1180 {
1181         struct rtl_priv *rtlpriv = rtl_priv(hw);
1182
1183         if (_rtl92ce_set_media_status(hw, type))
1184                 return -EOPNOTSUPP;
1185
1186         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1187                 if (type != NL80211_IFTYPE_AP)
1188                         rtl92ce_set_check_bssid(hw, true);
1189         } else {
1190                 rtl92ce_set_check_bssid(hw, false);
1191         }
1192
1193         return 0;
1194 }
1195
1196 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1197 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1198 {
1199         struct rtl_priv *rtlpriv = rtl_priv(hw);
1200         rtl92c_dm_init_edca_turbo(hw);
1201         switch (aci) {
1202         case AC1_BK:
1203                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1204                 break;
1205         case AC0_BE:
1206                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1207                 break;
1208         case AC2_VI:
1209                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1210                 break;
1211         case AC3_VO:
1212                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1213                 break;
1214         default:
1215                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1216                 break;
1217         }
1218 }
1219
1220 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1221 {
1222         struct rtl_priv *rtlpriv = rtl_priv(hw);
1223         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1224
1225         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1226         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1227 }
1228
1229 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1230 {
1231         struct rtl_priv *rtlpriv = rtl_priv(hw);
1232         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1233
1234         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1235         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1236         synchronize_irq(rtlpci->pdev->irq);
1237 }
1238
1239 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1240 {
1241         struct rtl_priv *rtlpriv = rtl_priv(hw);
1242         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1243         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1244         u8 u1b_tmp;
1245         u32 u4b_tmp;
1246
1247         rtlpriv->intf_ops->enable_aspm(hw);
1248         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1249         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1250         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1251         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1252         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1253         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1254         if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1255                 rtl92c_firmware_selfreset(hw);
1256         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1257         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1258         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1259         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1260         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1261              ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1262              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1263                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1264                                 (u1b_tmp << 8));
1265         } else {
1266                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1267                                 (u1b_tmp << 8));
1268         }
1269         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1270         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1271         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1272         if (!IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
1273                 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1274         if (rtlpcipriv->bt_coexist.bt_coexistence) {
1275                 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1276                 u4b_tmp |= 0x03824800;
1277                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1278         } else {
1279                 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1280         }
1281
1282         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1283         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1284 }
1285
1286 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1287 {
1288         struct rtl_priv *rtlpriv = rtl_priv(hw);
1289         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1290         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1291         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1292         enum nl80211_iftype opmode;
1293
1294         mac->link_state = MAC80211_NOLINK;
1295         opmode = NL80211_IFTYPE_UNSPECIFIED;
1296         _rtl92ce_set_media_status(hw, opmode);
1297         if (rtlpci->driver_is_goingto_unload ||
1298             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1299                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1300         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1301         _rtl92ce_poweroff_adapter(hw);
1302
1303         /* after power off we should do iqk again */
1304         rtlpriv->phy.iqk_initialized = false;
1305 }
1306
1307 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1308                                   u32 *p_inta, u32 *p_intb)
1309 {
1310         struct rtl_priv *rtlpriv = rtl_priv(hw);
1311         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1312
1313         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1314         rtl_write_dword(rtlpriv, ISR, *p_inta);
1315
1316         /*
1317          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1318          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1319          */
1320 }
1321
1322 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1323 {
1324
1325         struct rtl_priv *rtlpriv = rtl_priv(hw);
1326         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1327         u16 bcn_interval, atim_window;
1328
1329         bcn_interval = mac->beacon_interval;
1330         atim_window = 2;        /*FIX MERGE */
1331         rtl92ce_disable_interrupt(hw);
1332         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1333         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1334         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1335         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1336         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1337         rtl_write_byte(rtlpriv, 0x606, 0x30);
1338         rtl92ce_enable_interrupt(hw);
1339 }
1340
1341 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1342 {
1343         struct rtl_priv *rtlpriv = rtl_priv(hw);
1344         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1345         u16 bcn_interval = mac->beacon_interval;
1346
1347         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1348                  "beacon_interval:%d\n", bcn_interval);
1349         rtl92ce_disable_interrupt(hw);
1350         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1351         rtl92ce_enable_interrupt(hw);
1352 }
1353
1354 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1355                                    u32 add_msr, u32 rm_msr)
1356 {
1357         struct rtl_priv *rtlpriv = rtl_priv(hw);
1358         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1359
1360         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1361                  add_msr, rm_msr);
1362
1363         if (add_msr)
1364                 rtlpci->irq_mask[0] |= add_msr;
1365         if (rm_msr)
1366                 rtlpci->irq_mask[0] &= (~rm_msr);
1367         rtl92ce_disable_interrupt(hw);
1368         rtl92ce_enable_interrupt(hw);
1369 }
1370
1371 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1372                                                  bool autoload_fail,
1373                                                  u8 *hwinfo)
1374 {
1375         struct rtl_priv *rtlpriv = rtl_priv(hw);
1376         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1377         u8 rf_path, index, tempval;
1378         u16 i;
1379
1380         for (rf_path = 0; rf_path < 2; rf_path++) {
1381                 for (i = 0; i < 3; i++) {
1382                         if (!autoload_fail) {
1383                                 rtlefuse->
1384                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1385                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1386                                 rtlefuse->
1387                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1388                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1389                                            i];
1390                         } else {
1391                                 rtlefuse->
1392                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1393                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1394                                 rtlefuse->
1395                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1396                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1397                         }
1398                 }
1399         }
1400
1401         for (i = 0; i < 3; i++) {
1402                 if (!autoload_fail)
1403                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1404                 else
1405                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1406                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1407                     (tempval & 0xf);
1408                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1409                     ((tempval & 0xf0) >> 4);
1410         }
1411
1412         for (rf_path = 0; rf_path < 2; rf_path++)
1413                 for (i = 0; i < 3; i++)
1414                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1415                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1416                                 rf_path, i,
1417                                 rtlefuse->
1418                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1419         for (rf_path = 0; rf_path < 2; rf_path++)
1420                 for (i = 0; i < 3; i++)
1421                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1422                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1423                                 rf_path, i,
1424                                 rtlefuse->
1425                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1426         for (rf_path = 0; rf_path < 2; rf_path++)
1427                 for (i = 0; i < 3; i++)
1428                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1429                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1430                                 rf_path, i,
1431                                 rtlefuse->
1432                                 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1433
1434         for (rf_path = 0; rf_path < 2; rf_path++) {
1435                 for (i = 0; i < 14; i++) {
1436                         index = _rtl92c_get_chnl_group((u8) i);
1437
1438                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1439                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1440                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1441                             rtlefuse->
1442                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1443
1444                         if ((rtlefuse->
1445                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1446                              rtlefuse->
1447                              eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1448                             > 0) {
1449                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1450                                     rtlefuse->
1451                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1452                                     [index] -
1453                                     rtlefuse->
1454                                     eprom_chnl_txpwr_ht40_2sdf[rf_path]
1455                                     [index];
1456                         } else {
1457                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1458                         }
1459                 }
1460
1461                 for (i = 0; i < 14; i++) {
1462                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1463                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1464                                 rf_path, i,
1465                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1466                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1467                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1468                 }
1469         }
1470
1471         for (i = 0; i < 3; i++) {
1472                 if (!autoload_fail) {
1473                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1474                             hwinfo[EEPROM_TXPWR_GROUP + i];
1475                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1476                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1477                 } else {
1478                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1479                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1480                 }
1481         }
1482
1483         for (rf_path = 0; rf_path < 2; rf_path++) {
1484                 for (i = 0; i < 14; i++) {
1485                         index = _rtl92c_get_chnl_group((u8) i);
1486
1487                         if (rf_path == RF90_PATH_A) {
1488                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1489                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1490                                      & 0xf);
1491                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1492                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1493                                      & 0xf);
1494                         } else if (rf_path == RF90_PATH_B) {
1495                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1496                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1497                                       & 0xf0) >> 4);
1498                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1499                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1500                                       & 0xf0) >> 4);
1501                         }
1502
1503                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1504                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1505                                 rf_path, i,
1506                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1507                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1508                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1509                                 rf_path, i,
1510                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1511                 }
1512         }
1513
1514         for (i = 0; i < 14; i++) {
1515                 index = _rtl92c_get_chnl_group((u8) i);
1516
1517                 if (!autoload_fail)
1518                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1519                 else
1520                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1521
1522                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1523                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1524                     ((tempval >> 4) & 0xF);
1525
1526                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1527                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1528
1529                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1530                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1531
1532                 index = _rtl92c_get_chnl_group((u8) i);
1533
1534                 if (!autoload_fail)
1535                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1536                 else
1537                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1538
1539                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1540                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1541                     ((tempval >> 4) & 0xF);
1542         }
1543
1544         rtlefuse->legacy_ht_txpowerdiff =
1545             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1546
1547         for (i = 0; i < 14; i++)
1548                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1549                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1550                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1551         for (i = 0; i < 14; i++)
1552                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1553                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1554                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1555         for (i = 0; i < 14; i++)
1556                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1557                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1558                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1559         for (i = 0; i < 14; i++)
1560                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1561                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1562                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1563
1564         if (!autoload_fail)
1565                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1566         else
1567                 rtlefuse->eeprom_regulatory = 0;
1568         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1569                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1570
1571         if (!autoload_fail) {
1572                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1573                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1574         } else {
1575                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1576                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1577         }
1578         RTPRINT(rtlpriv, FINIT, INIT_TxPower, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1579                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1580                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1581
1582         if (!autoload_fail)
1583                 tempval = hwinfo[EEPROM_THERMAL_METER];
1584         else
1585                 tempval = EEPROM_DEFAULT_THERMALMETER;
1586         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1587
1588         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1589                 rtlefuse->apk_thermalmeterignore = true;
1590
1591         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1592         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1593                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1594 }
1595
1596 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1597 {
1598         struct rtl_priv *rtlpriv = rtl_priv(hw);
1599         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1600         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1601         u16 i, usvalue;
1602         u8 hwinfo[HWSET_MAX_SIZE];
1603         u16 eeprom_id;
1604
1605         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1606                 rtl_efuse_shadow_map_update(hw);
1607
1608                 memcpy((void *)hwinfo,
1609                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1610                        HWSET_MAX_SIZE);
1611         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1612                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1613                          "RTL819X Not boot from eeprom, check it !!");
1614         }
1615
1616         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1617                       hwinfo, HWSET_MAX_SIZE);
1618
1619         eeprom_id = *((u16 *)&hwinfo[0]);
1620         if (eeprom_id != RTL8190_EEPROM_ID) {
1621                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1622                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1623                 rtlefuse->autoload_failflag = true;
1624         } else {
1625                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1626                 rtlefuse->autoload_failflag = false;
1627         }
1628
1629         if (rtlefuse->autoload_failflag)
1630                 return;
1631
1632         for (i = 0; i < 6; i += 2) {
1633                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1634                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1635         }
1636
1637         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1638
1639         _rtl92ce_read_txpower_info_from_hwpg(hw,
1640                                              rtlefuse->autoload_failflag,
1641                                              hwinfo);
1642
1643         rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1644                                                  rtlefuse->autoload_failflag,
1645                                                  hwinfo);
1646
1647         rtlefuse->eeprom_channelplan = *&hwinfo[EEPROM_CHANNELPLAN];
1648         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1649         rtlefuse->txpwr_fromeprom = true;
1650         rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMER_ID];
1651
1652         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1653                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1654
1655         /* set channel paln to world wide 13 */
1656         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1657
1658         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1659                 switch (rtlefuse->eeprom_oemid) {
1660                 case EEPROM_CID_DEFAULT:
1661                         if (rtlefuse->eeprom_did == 0x8176) {
1662                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1663                                      rtlefuse->eeprom_smid == 0x1629))
1664                                         rtlhal->oem_id = RT_CID_819x_HP;
1665                                 else
1666                                         rtlhal->oem_id = RT_CID_DEFAULT;
1667                         } else {
1668                                 rtlhal->oem_id = RT_CID_DEFAULT;
1669                         }
1670                         break;
1671                 case EEPROM_CID_TOSHIBA:
1672                         rtlhal->oem_id = RT_CID_TOSHIBA;
1673                         break;
1674                 case EEPROM_CID_QMI:
1675                         rtlhal->oem_id = RT_CID_819x_QMI;
1676                         break;
1677                 case EEPROM_CID_WHQL:
1678                 default:
1679                         rtlhal->oem_id = RT_CID_DEFAULT;
1680                         break;
1681
1682                 }
1683         }
1684
1685 }
1686
1687 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1688 {
1689         struct rtl_priv *rtlpriv = rtl_priv(hw);
1690         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1691         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1692
1693         switch (rtlhal->oem_id) {
1694         case RT_CID_819x_HP:
1695                 pcipriv->ledctl.led_opendrain = true;
1696                 break;
1697         case RT_CID_819x_Lenovo:
1698         case RT_CID_DEFAULT:
1699         case RT_CID_TOSHIBA:
1700         case RT_CID_CCX:
1701         case RT_CID_819x_Acer:
1702         case RT_CID_WHQL:
1703         default:
1704                 break;
1705         }
1706         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1707                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1708 }
1709
1710 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1711 {
1712         struct rtl_priv *rtlpriv = rtl_priv(hw);
1713         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1714         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1715         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1716         u8 tmp_u1b;
1717
1718         rtlhal->version = _rtl92ce_read_chip_version(hw);
1719         if (get_rf_type(rtlphy) == RF_1T1R)
1720                 rtlpriv->dm.rfpath_rxenable[0] = true;
1721         else
1722                 rtlpriv->dm.rfpath_rxenable[0] =
1723                     rtlpriv->dm.rfpath_rxenable[1] = true;
1724         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1725                  rtlhal->version);
1726         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1727         if (tmp_u1b & BIT(4)) {
1728                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1729                 rtlefuse->epromtype = EEPROM_93C46;
1730         } else {
1731                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1732                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1733         }
1734         if (tmp_u1b & BIT(5)) {
1735                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1736                 rtlefuse->autoload_failflag = false;
1737                 _rtl92ce_read_adapter_info(hw);
1738         } else {
1739                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1740         }
1741         _rtl92ce_hal_customized_behavior(hw);
1742 }
1743
1744 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1745                 struct ieee80211_sta *sta)
1746 {
1747         struct rtl_priv *rtlpriv = rtl_priv(hw);
1748         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1749         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1750         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1751         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1752         u32 ratr_value;
1753         u8 ratr_index = 0;
1754         u8 nmode = mac->ht_enable;
1755         u8 mimo_ps = IEEE80211_SMPS_OFF;
1756         u16 shortgi_rate;
1757         u32 tmp_ratr_value;
1758         u8 curtxbw_40mhz = mac->bw_40;
1759         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1760                                1 : 0;
1761         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1762                                1 : 0;
1763         enum wireless_mode wirelessmode = mac->mode;
1764
1765         if (rtlhal->current_bandtype == BAND_ON_5G)
1766                 ratr_value = sta->supp_rates[1] << 4;
1767         else
1768                 ratr_value = sta->supp_rates[0];
1769         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1770                         sta->ht_cap.mcs.rx_mask[0] << 12);
1771         switch (wirelessmode) {
1772         case WIRELESS_MODE_B:
1773                 if (ratr_value & 0x0000000c)
1774                         ratr_value &= 0x0000000d;
1775                 else
1776                         ratr_value &= 0x0000000f;
1777                 break;
1778         case WIRELESS_MODE_G:
1779                 ratr_value &= 0x00000FF5;
1780                 break;
1781         case WIRELESS_MODE_N_24G:
1782         case WIRELESS_MODE_N_5G:
1783                 nmode = 1;
1784                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1785                         ratr_value &= 0x0007F005;
1786                 } else {
1787                         u32 ratr_mask;
1788
1789                         if (get_rf_type(rtlphy) == RF_1T2R ||
1790                             get_rf_type(rtlphy) == RF_1T1R)
1791                                 ratr_mask = 0x000ff005;
1792                         else
1793                                 ratr_mask = 0x0f0ff005;
1794
1795                         ratr_value &= ratr_mask;
1796                 }
1797                 break;
1798         default:
1799                 if (rtlphy->rf_type == RF_1T2R)
1800                         ratr_value &= 0x000ff0ff;
1801                 else
1802                         ratr_value &= 0x0f0ff0ff;
1803
1804                 break;
1805         }
1806
1807         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1808             (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1809             (rtlpcipriv->bt_coexist.bt_cur_state) &&
1810             (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1811             ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1812             (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1813                 ratr_value &= 0x0fffcfc0;
1814         else
1815                 ratr_value &= 0x0FFFFFFF;
1816
1817         if (nmode && ((curtxbw_40mhz &&
1818                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1819                                                curshortgi_20mhz))) {
1820
1821                 ratr_value |= 0x10000000;
1822                 tmp_ratr_value = (ratr_value >> 12);
1823
1824                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1825                         if ((1 << shortgi_rate) & tmp_ratr_value)
1826                                 break;
1827                 }
1828
1829                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1830                     (shortgi_rate << 4) | (shortgi_rate);
1831         }
1832
1833         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1834
1835         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1836                  rtl_read_dword(rtlpriv, REG_ARFR0));
1837 }
1838
1839 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1840                 struct ieee80211_sta *sta, u8 rssi_level)
1841 {
1842         struct rtl_priv *rtlpriv = rtl_priv(hw);
1843         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1844         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1845         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1846         struct rtl_sta_info *sta_entry = NULL;
1847         u32 ratr_bitmap;
1848         u8 ratr_index;
1849         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1850                                 ? 1 : 0;
1851         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1852                                 1 : 0;
1853         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1854                                 1 : 0;
1855         enum wireless_mode wirelessmode = 0;
1856         bool shortgi = false;
1857         u8 rate_mask[5];
1858         u8 macid = 0;
1859         u8 mimo_ps = IEEE80211_SMPS_OFF;
1860
1861         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1862         wirelessmode = sta_entry->wireless_mode;
1863         if (mac->opmode == NL80211_IFTYPE_STATION)
1864                 curtxbw_40mhz = mac->bw_40;
1865         else if (mac->opmode == NL80211_IFTYPE_AP ||
1866                 mac->opmode == NL80211_IFTYPE_ADHOC)
1867                 macid = sta->aid + 1;
1868
1869         if (rtlhal->current_bandtype == BAND_ON_5G)
1870                 ratr_bitmap = sta->supp_rates[1] << 4;
1871         else
1872                 ratr_bitmap = sta->supp_rates[0];
1873         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1874                         sta->ht_cap.mcs.rx_mask[0] << 12);
1875         switch (wirelessmode) {
1876         case WIRELESS_MODE_B:
1877                 ratr_index = RATR_INX_WIRELESS_B;
1878                 if (ratr_bitmap & 0x0000000c)
1879                         ratr_bitmap &= 0x0000000d;
1880                 else
1881                         ratr_bitmap &= 0x0000000f;
1882                 break;
1883         case WIRELESS_MODE_G:
1884                 ratr_index = RATR_INX_WIRELESS_GB;
1885
1886                 if (rssi_level == 1)
1887                         ratr_bitmap &= 0x00000f00;
1888                 else if (rssi_level == 2)
1889                         ratr_bitmap &= 0x00000ff0;
1890                 else
1891                         ratr_bitmap &= 0x00000ff5;
1892                 break;
1893         case WIRELESS_MODE_A:
1894                 ratr_index = RATR_INX_WIRELESS_A;
1895                 ratr_bitmap &= 0x00000ff0;
1896                 break;
1897         case WIRELESS_MODE_N_24G:
1898         case WIRELESS_MODE_N_5G:
1899                 ratr_index = RATR_INX_WIRELESS_NGB;
1900
1901                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1902                         if (rssi_level == 1)
1903                                 ratr_bitmap &= 0x00070000;
1904                         else if (rssi_level == 2)
1905                                 ratr_bitmap &= 0x0007f000;
1906                         else
1907                                 ratr_bitmap &= 0x0007f005;
1908                 } else {
1909                         if (rtlphy->rf_type == RF_1T2R ||
1910                             rtlphy->rf_type == RF_1T1R) {
1911                                 if (curtxbw_40mhz) {
1912                                         if (rssi_level == 1)
1913                                                 ratr_bitmap &= 0x000f0000;
1914                                         else if (rssi_level == 2)
1915                                                 ratr_bitmap &= 0x000ff000;
1916                                         else
1917                                                 ratr_bitmap &= 0x000ff015;
1918                                 } else {
1919                                         if (rssi_level == 1)
1920                                                 ratr_bitmap &= 0x000f0000;
1921                                         else if (rssi_level == 2)
1922                                                 ratr_bitmap &= 0x000ff000;
1923                                         else
1924                                                 ratr_bitmap &= 0x000ff005;
1925                                 }
1926                         } else {
1927                                 if (curtxbw_40mhz) {
1928                                         if (rssi_level == 1)
1929                                                 ratr_bitmap &= 0x0f0f0000;
1930                                         else if (rssi_level == 2)
1931                                                 ratr_bitmap &= 0x0f0ff000;
1932                                         else
1933                                                 ratr_bitmap &= 0x0f0ff015;
1934                                 } else {
1935                                         if (rssi_level == 1)
1936                                                 ratr_bitmap &= 0x0f0f0000;
1937                                         else if (rssi_level == 2)
1938                                                 ratr_bitmap &= 0x0f0ff000;
1939                                         else
1940                                                 ratr_bitmap &= 0x0f0ff005;
1941                                 }
1942                         }
1943                 }
1944
1945                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1946                     (!curtxbw_40mhz && curshortgi_20mhz)) {
1947
1948                         if (macid == 0)
1949                                 shortgi = true;
1950                         else if (macid == 1)
1951                                 shortgi = false;
1952                 }
1953                 break;
1954         default:
1955                 ratr_index = RATR_INX_WIRELESS_NGB;
1956
1957                 if (rtlphy->rf_type == RF_1T2R)
1958                         ratr_bitmap &= 0x000ff0ff;
1959                 else
1960                         ratr_bitmap &= 0x0f0ff0ff;
1961                 break;
1962         }
1963         sta_entry->ratr_index = ratr_index;
1964
1965         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1966                  "ratr_bitmap :%x\n", ratr_bitmap);
1967         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1968                                      (ratr_index << 28);
1969         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1970         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1971                  "Rate_index:%x, ratr_val:%x, %5phC\n",
1972                  ratr_index, ratr_bitmap, rate_mask);
1973         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1974
1975         if (macid != 0)
1976                 sta_entry->ratr_index = ratr_index;
1977 }
1978
1979 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
1980                 struct ieee80211_sta *sta, u8 rssi_level)
1981 {
1982         struct rtl_priv *rtlpriv = rtl_priv(hw);
1983
1984         if (rtlpriv->dm.useramask)
1985                 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
1986         else
1987                 rtl92ce_update_hal_rate_table(hw, sta);
1988 }
1989
1990 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1991 {
1992         struct rtl_priv *rtlpriv = rtl_priv(hw);
1993         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1994         u16 sifs_timer;
1995
1996         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1997                                       &mac->slot_time);
1998         if (!mac->ht_enable)
1999                 sifs_timer = 0x0a0a;
2000         else
2001                 sifs_timer = 0x1010;
2002         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2003 }
2004
2005 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2006 {
2007         struct rtl_priv *rtlpriv = rtl_priv(hw);
2008         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2009         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2010         enum rf_pwrstate e_rfpowerstate_toset;
2011         u8 u1tmp;
2012         bool actuallyset = false;
2013         unsigned long flag;
2014
2015         if (rtlpci->being_init_adapter)
2016                 return false;
2017
2018         if (ppsc->swrf_processing)
2019                 return false;
2020
2021         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2022         if (ppsc->rfchange_inprogress) {
2023                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2024                 return false;
2025         } else {
2026                 ppsc->rfchange_inprogress = true;
2027                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2028         }
2029
2030         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2031                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
2032
2033         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2034         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2035
2036         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2037                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2038                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2039
2040                 e_rfpowerstate_toset = ERFON;
2041                 ppsc->hwradiooff = false;
2042                 actuallyset = true;
2043         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2044                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2045                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2046
2047                 e_rfpowerstate_toset = ERFOFF;
2048                 ppsc->hwradiooff = true;
2049                 actuallyset = true;
2050         }
2051
2052         if (actuallyset) {
2053                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2054                 ppsc->rfchange_inprogress = false;
2055                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2056         } else {
2057                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2058                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2059
2060                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2061                 ppsc->rfchange_inprogress = false;
2062                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2063         }
2064
2065         *valid = 1;
2066         return !ppsc->hwradiooff;
2067
2068 }
2069
2070 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2071                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2072                      bool is_wepkey, bool clear_all)
2073 {
2074         struct rtl_priv *rtlpriv = rtl_priv(hw);
2075         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2076         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2077         u8 *macaddr = p_macaddr;
2078         u32 entry_id = 0;
2079         bool is_pairwise = false;
2080
2081         static u8 cam_const_addr[4][6] = {
2082                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2083                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2084                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2085                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2086         };
2087         static u8 cam_const_broad[] = {
2088                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2089         };
2090
2091         if (clear_all) {
2092                 u8 idx = 0;
2093                 u8 cam_offset = 0;
2094                 u8 clear_number = 5;
2095
2096                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2097
2098                 for (idx = 0; idx < clear_number; idx++) {
2099                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2100                         rtl_cam_empty_entry(hw, cam_offset + idx);
2101
2102                         if (idx < 5) {
2103                                 memset(rtlpriv->sec.key_buf[idx], 0,
2104                                        MAX_KEY_LEN);
2105                                 rtlpriv->sec.key_len[idx] = 0;
2106                         }
2107                 }
2108
2109         } else {
2110                 switch (enc_algo) {
2111                 case WEP40_ENCRYPTION:
2112                         enc_algo = CAM_WEP40;
2113                         break;
2114                 case WEP104_ENCRYPTION:
2115                         enc_algo = CAM_WEP104;
2116                         break;
2117                 case TKIP_ENCRYPTION:
2118                         enc_algo = CAM_TKIP;
2119                         break;
2120                 case AESCCMP_ENCRYPTION:
2121                         enc_algo = CAM_AES;
2122                         break;
2123                 default:
2124                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2125                                  "switch case not processed\n");
2126                         enc_algo = CAM_TKIP;
2127                         break;
2128                 }
2129
2130                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2131                         macaddr = cam_const_addr[key_index];
2132                         entry_id = key_index;
2133                 } else {
2134                         if (is_group) {
2135                                 macaddr = cam_const_broad;
2136                                 entry_id = key_index;
2137                         } else {
2138                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2139                                         entry_id = rtl_cam_get_free_entry(hw,
2140                                                                  p_macaddr);
2141                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2142                                                 RT_TRACE(rtlpriv, COMP_SEC,
2143                                                          DBG_EMERG,
2144                                                          "Can not find free hw security cam entry\n");
2145                                                 return;
2146                                         }
2147                                 } else {
2148                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2149                                 }
2150
2151                                 key_index = PAIRWISE_KEYIDX;
2152                                 is_pairwise = true;
2153                         }
2154                 }
2155
2156                 if (rtlpriv->sec.key_len[key_index] == 0) {
2157                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2158                                  "delete one entry, entry_id is %d\n",
2159                                  entry_id);
2160                         if (mac->opmode == NL80211_IFTYPE_AP)
2161                                 rtl_cam_del_entry(hw, p_macaddr);
2162                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2163                 } else {
2164                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2165                                  "The insert KEY length is %d\n",
2166                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2167                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2168                                  "The insert KEY is %x %x\n",
2169                                  rtlpriv->sec.key_buf[0][0],
2170                                  rtlpriv->sec.key_buf[0][1]);
2171
2172                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2173                                  "add one entry\n");
2174                         if (is_pairwise) {
2175                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2176                                               "Pairwise Key content",
2177                                               rtlpriv->sec.pairwise_key,
2178                                               rtlpriv->sec.
2179                                               key_len[PAIRWISE_KEYIDX]);
2180
2181                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2182                                          "set Pairwise key\n");
2183
2184                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2185                                                       entry_id, enc_algo,
2186                                                       CAM_CONFIG_NO_USEDK,
2187                                                       rtlpriv->sec.
2188                                                       key_buf[key_index]);
2189                         } else {
2190                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2191                                          "set group key\n");
2192
2193                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2194                                         rtl_cam_add_one_entry(hw,
2195                                                 rtlefuse->dev_addr,
2196                                                 PAIRWISE_KEYIDX,
2197                                                 CAM_PAIRWISE_KEY_POSITION,
2198                                                 enc_algo,
2199                                                 CAM_CONFIG_NO_USEDK,
2200                                                 rtlpriv->sec.key_buf
2201                                                 [entry_id]);
2202                                 }
2203
2204                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2205                                                 entry_id, enc_algo,
2206                                                 CAM_CONFIG_NO_USEDK,
2207                                                 rtlpriv->sec.key_buf[entry_id]);
2208                         }
2209
2210                 }
2211         }
2212 }
2213
2214 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2215 {
2216         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2217
2218         rtlpcipriv->bt_coexist.bt_coexistence =
2219                         rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2220         rtlpcipriv->bt_coexist.bt_ant_num =
2221                         rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2222         rtlpcipriv->bt_coexist.bt_coexist_type =
2223                         rtlpcipriv->bt_coexist.eeprom_bt_type;
2224
2225         if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2226                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2227                         rtlpcipriv->bt_coexist.eeprom_bt_ant_isol;
2228         else
2229                 rtlpcipriv->bt_coexist.bt_ant_isolation =
2230                         rtlpcipriv->bt_coexist.reg_bt_iso;
2231
2232         rtlpcipriv->bt_coexist.bt_radio_shared_type =
2233                         rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2234
2235         if (rtlpcipriv->bt_coexist.bt_coexistence) {
2236
2237                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2238                         rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2239                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2240                         rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2241                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2242                         rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2243                 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2244                         rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2245                 else
2246                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2247
2248                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2249                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2250                 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2251         }
2252 }
2253
2254 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2255                                               bool auto_load_fail, u8 *hwinfo)
2256 {
2257         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2258         u8 val;
2259
2260         if (!auto_load_fail) {
2261                 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2262                                         ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2263                 val = hwinfo[RF_OPTION4];
2264                 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1);
2265                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1);
2266                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2267                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2268                                                          ((val & 0x20) >> 5);
2269         } else {
2270                 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2271                 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2272                 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2273                 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2274                 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2275         }
2276
2277         rtl8192ce_bt_var_init(hw);
2278 }
2279
2280 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2281 {
2282         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2283
2284         /* 0:Low, 1:High, 2:From Efuse. */
2285         rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2286         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2287         rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2288         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2289         rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2290 }
2291
2292
2293 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2294 {
2295         struct rtl_priv *rtlpriv = rtl_priv(hw);
2296         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2297         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2298
2299         u8 u1_tmp;
2300
2301         if (rtlpcipriv->bt_coexist.bt_coexistence &&
2302             ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2303               rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2304
2305                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2306                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2307
2308                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2309                          BIT_OFFSET_LEN_MASK_32(0, 1);
2310                 u1_tmp = u1_tmp |
2311                          ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2312                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2313                          ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2314                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2315                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2316
2317                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2318                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2319                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2320
2321                 /* Config to 1T1R. */
2322                 if (rtlphy->rf_type == RF_1T1R) {
2323                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2324                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2325                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2326
2327                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2328                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2329                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2330                 }
2331         }
2332 }
2333
2334 void rtl92ce_suspend(struct ieee80211_hw *hw)
2335 {
2336 }
2337
2338 void rtl92ce_resume(struct ieee80211_hw *hw)
2339 {
2340 }