drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include <linux/export.h>
  31 #include "dm_common.h"
  32 #include "phy_common.h"
  33 #include "../pci.h"
  34 #include "../base.h"
  35
  36 #define BT_RSSI_STATE_NORMAL_POWER      BIT_OFFSET_LEN_MASK_32(0, 1)
  37 #define BT_RSSI_STATE_AMDPU_OFF         BIT_OFFSET_LEN_MASK_32(1, 1)
  38 #define BT_RSSI_STATE_SPECIAL_LOW       BIT_OFFSET_LEN_MASK_32(2, 1)
  39 #define BT_RSSI_STATE_BG_EDCA_LOW       BIT_OFFSET_LEN_MASK_32(3, 1)
  40 #define BT_RSSI_STATE_TXPOWER_LOW       BIT_OFFSET_LEN_MASK_32(4, 1)
  41
  42 #define RTLPRIV                 (struct rtl_priv *)
  43 #define GET_UNDECORATED_AVERAGE_RSSI(_priv)     \
  44         ((RTLPRIV(_priv))->mac80211.opmode == \
  45                              NL80211_IFTYPE_ADHOC) ?    \
  46         ((RTLPRIV(_priv))->dm.entry_min_undec_sm_pwdb) : \
  47         ((RTLPRIV(_priv))->dm.undec_sm_pwdb)
  48
  49 static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  50         0x7f8001fe,
  51         0x788001e2,
  52         0x71c001c7,
  53         0x6b8001ae,
  54         0x65400195,
  55         0x5fc0017f,
  56         0x5a400169,
  57         0x55400155,
  58         0x50800142,
  59         0x4c000130,
  60         0x47c0011f,
  61         0x43c0010f,
  62         0x40000100,
  63         0x3c8000f2,
  64         0x390000e4,
  65         0x35c000d7,
  66         0x32c000cb,
  67         0x300000c0,
  68         0x2d4000b5,
  69         0x2ac000ab,
  70         0x288000a2,
  71         0x26000098,
  72         0x24000090,
  73         0x22000088,
  74         0x20000080,
  75         0x1e400079,
  76         0x1c800072,
  77         0x1b00006c,
  78         0x19800066,
  79         0x18000060,
  80         0x16c0005b,
  81         0x15800056,
  82         0x14400051,
  83         0x1300004c,
  84         0x12000048,
  85         0x11000044,
  86         0x10000040,
  87 };
  88
  89 static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  90         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  91         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  92         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  93         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  94         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  95         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  96         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  97         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  98         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  99         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
 100         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
 101         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
 102         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
 103         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
 104         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
 105         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
 106         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
 107         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
 108         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
 109         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
 110         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
 111         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
 112         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
 113         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
 114         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
 115         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
 116         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
 117         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
 118         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
 119         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
 120         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
 121         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
 122         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
 123 };
 124
 125 static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
 126         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
 127         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
 128         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
 129         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
 130         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
 131         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
 132         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
 133         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
 134         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
 135         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
 136         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
 137         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
 138         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
 139         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
 140         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
 141         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
 142         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
 143         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
 144         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
 145         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 146         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
 147         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
 148         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
 149         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
 150         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
 151         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
 152         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
 153         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
 154         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
 155         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
 156         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
 157         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
 158         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
 159 };
 160
 161 static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
 162 {
 163         struct rtl_priv *rtlpriv = rtl_priv(hw);
 164         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 165
 166         dm_digtable->dig_enable_flag = true;
 167         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 168         dm_digtable->cur_igvalue = 0x20;
 169         dm_digtable->pre_igvalue = 0x0;
 170         dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
 171         dm_digtable->presta_cstate = DIG_STA_DISCONNECT;
 172         dm_digtable->curmultista_cstate = DIG_MULTISTA_DISCONNECT;
 173         dm_digtable->rssi_lowthresh = DM_DIG_THRESH_LOW;
 174         dm_digtable->rssi_highthresh = DM_DIG_THRESH_HIGH;
 175         dm_digtable->fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
 176         dm_digtable->fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
 177         dm_digtable->rx_gain_range_max = DM_DIG_MAX;
 178         dm_digtable->rx_gain_range_min = DM_DIG_MIN;
 179         dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
 180         dm_digtable->back_range_max = DM_DIG_BACKOFF_MAX;
 181         dm_digtable->back_range_min = DM_DIG_BACKOFF_MIN;
 182         dm_digtable->pre_cck_pd_state = CCK_PD_STAGE_MAX;
 183         dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
 184 }
 185
 186 static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
 187 {
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 190         long rssi_val_min = 0;
 191
 192         if ((dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) &&
 193             (dm_digtable->cursta_cstate == DIG_STA_CONNECT)) {
 194                 if (rtlpriv->dm.entry_min_undec_sm_pwdb != 0)
 195                         rssi_val_min =
 196                             (rtlpriv->dm.entry_min_undec_sm_pwdb >
 197                              rtlpriv->dm.undec_sm_pwdb) ?
 198                             rtlpriv->dm.undec_sm_pwdb :
 199                             rtlpriv->dm.entry_min_undec_sm_pwdb;
 200                 else
 201                         rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 202         } else if (dm_digtable->cursta_cstate == DIG_STA_CONNECT ||
 203                    dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT) {
 204                 rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
 205         } else if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
 206                 rssi_val_min = rtlpriv->dm.entry_min_undec_sm_pwdb;
 207         }
 208
 209         return (u8) rssi_val_min;
 210 }
 211
 212 static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
 213 {
 214         u32 ret_value;
 215         struct rtl_priv *rtlpriv = rtl_priv(hw);
 216         struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
 217
 218         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
 219         falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
 220
 221         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
 222         falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
 223         falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
 224
 225         ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
 226         falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
 227         falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
 228             falsealm_cnt->cnt_rate_illegal +
 229             falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
 230
 231         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
 232         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
 233         falsealm_cnt->cnt_cck_fail = ret_value;
 234
 235         ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
 236         falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
 237         falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
 238                                  falsealm_cnt->cnt_rate_illegal +
 239                                  falsealm_cnt->cnt_crc8_fail +
 240                                  falsealm_cnt->cnt_mcs_fail +
 241                                  falsealm_cnt->cnt_cck_fail);
 242
 243         rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
 244         rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
 245         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
 246         rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
 247
 248         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 249                  "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
 250                  falsealm_cnt->cnt_parity_fail,
 251                  falsealm_cnt->cnt_rate_illegal,
 252                  falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
 253
 254         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 255                  "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
 256                  falsealm_cnt->cnt_ofdm_fail,
 257                  falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
 258 }
 259
 260 static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
 261 {
 262         struct rtl_priv *rtlpriv = rtl_priv(hw);
 263         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 264         u8 value_igi = dm_digtable->cur_igvalue;
 265
 266         if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
 267                 value_igi--;
 268         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
 269                 value_igi += 0;
 270         else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
 271                 value_igi++;
 272         else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
 273                 value_igi += 2;
 274         if (value_igi > DM_DIG_FA_UPPER)
 275                 value_igi = DM_DIG_FA_UPPER;
 276         else if (value_igi < DM_DIG_FA_LOWER)
 277                 value_igi = DM_DIG_FA_LOWER;
 278         if (rtlpriv->falsealm_cnt.cnt_all > 10000)
 279                 value_igi = 0x32;
 280
 281         dm_digtable->cur_igvalue = value_igi;
 282         rtl92c_dm_write_dig(hw);
 283 }
 284
 285 static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
 286 {
 287         struct rtl_priv *rtlpriv = rtl_priv(hw);
 288         struct dig_t *digtable = &rtlpriv->dm_digtable;
 289
 290         if (rtlpriv->falsealm_cnt.cnt_all > digtable->fa_highthresh) {
 291                 if ((digtable->back_val - 2) < digtable->back_range_min)
 292                         digtable->back_val = digtable->back_range_min;
 293                 else
 294                         digtable->back_val -= 2;
 295         } else if (rtlpriv->falsealm_cnt.cnt_all < digtable->fa_lowthresh) {
 296                 if ((digtable->back_val + 2) > digtable->back_range_max)
 297                         digtable->back_val = digtable->back_range_max;
 298                 else
 299                         digtable->back_val += 2;
 300         }
 301
 302         if ((digtable->rssi_val_min + 10 - digtable->back_val) >
 303             digtable->rx_gain_range_max)
 304                 digtable->cur_igvalue = digtable->rx_gain_range_max;
 305         else if ((digtable->rssi_val_min + 10 -
 306                   digtable->back_val) < digtable->rx_gain_range_min)
 307                 digtable->cur_igvalue = digtable->rx_gain_range_min;
 308         else
 309                 digtable->cur_igvalue = digtable->rssi_val_min + 10 -
 310                     digtable->back_val;
 311
 312         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 313                  "rssi_val_min = %x back_val %x\n",
 314                  digtable->rssi_val_min, digtable->back_val);
 315
 316         rtl92c_dm_write_dig(hw);
 317 }
 318
 319 static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
 320 {
 321         static u8 initialized; /* initialized to false */
 322         struct rtl_priv *rtlpriv = rtl_priv(hw);
 323         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 324         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 325         long rssi_strength = rtlpriv->dm.entry_min_undec_sm_pwdb;
 326         bool multi_sta = false;
 327
 328         if (mac->opmode == NL80211_IFTYPE_ADHOC)
 329                 multi_sta = true;
 330
 331         if (!multi_sta ||
 332             dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
 333                 initialized = false;
 334                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 335                 return;
 336         } else if (initialized == false) {
 337                 initialized = true;
 338                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
 339                 dm_digtable->cur_igvalue = 0x20;
 340                 rtl92c_dm_write_dig(hw);
 341         }
 342
 343         if (dm_digtable->curmultista_cstate == DIG_MULTISTA_CONNECT) {
 344                 if ((rssi_strength < dm_digtable->rssi_lowthresh) &&
 345                     (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
 346
 347                         if (dm_digtable->dig_ext_port_stage ==
 348                             DIG_EXT_PORT_STAGE_2) {
 349                                 dm_digtable->cur_igvalue = 0x20;
 350                                 rtl92c_dm_write_dig(hw);
 351                         }
 352
 353                         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
 354                 } else if (rssi_strength > dm_digtable->rssi_highthresh) {
 355                         dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
 356                         rtl92c_dm_ctrl_initgain_by_fa(hw);
 357                 }
 358         } else if (dm_digtable->dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
 359                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
 360                 dm_digtable->cur_igvalue = 0x20;
 361                 rtl92c_dm_write_dig(hw);
 362         }
 363
 364         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 365                  "curmultista_cstate = %x dig_ext_port_stage %x\n",
 366                  dm_digtable->curmultista_cstate,
 367                  dm_digtable->dig_ext_port_stage);
 368 }
 369
 370 static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
 371 {
 372         struct rtl_priv *rtlpriv = rtl_priv(hw);
 373         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 374
 375         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
 376                  "presta_cstate = %x, cursta_cstate = %x\n",
 377                  dm_digtable->presta_cstate, dm_digtable->cursta_cstate);
 378
 379         if (dm_digtable->presta_cstate == dm_digtable->cursta_cstate ||
 380             dm_digtable->cursta_cstate == DIG_STA_BEFORE_CONNECT ||
 381             dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
 382
 383                 if (dm_digtable->cursta_cstate != DIG_STA_DISCONNECT) {
 384                         dm_digtable->rssi_val_min =
 385                             rtl92c_dm_initial_gain_min_pwdb(hw);
 386                         rtl92c_dm_ctrl_initgain_by_rssi(hw);
 387                 }
 388         } else {
 389                 dm_digtable->rssi_val_min = 0;
 390                 dm_digtable->dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
 391                 dm_digtable->back_val = DM_DIG_BACKOFF_DEFAULT;
 392                 dm_digtable->cur_igvalue = 0x20;
 393                 dm_digtable->pre_igvalue = 0;
 394                 rtl92c_dm_write_dig(hw);
 395         }
 396 }
 397
 398 static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
 399 {
 400         struct rtl_priv *rtlpriv = rtl_priv(hw);
 401         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 402         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 403
 404         if (dm_digtable->cursta_cstate == DIG_STA_CONNECT) {
 405                 dm_digtable->rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
 406
 407                 if (dm_digtable->pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
 408                         if (dm_digtable->rssi_val_min <= 25)
 409                                 dm_digtable->cur_cck_pd_state =
 410                                     CCK_PD_STAGE_LowRssi;
 411                         else
 412                                 dm_digtable->cur_cck_pd_state =
 413                                     CCK_PD_STAGE_HighRssi;
 414                 } else {
 415                         if (dm_digtable->rssi_val_min <= 20)
 416                                 dm_digtable->cur_cck_pd_state =
 417                                     CCK_PD_STAGE_LowRssi;
 418                         else
 419                                 dm_digtable->cur_cck_pd_state =
 420                                     CCK_PD_STAGE_HighRssi;
 421                 }
 422         } else {
 423                 dm_digtable->cur_cck_pd_state = CCK_PD_STAGE_MAX;
 424         }
 425
 426         if (dm_digtable->pre_cck_pd_state != dm_digtable->cur_cck_pd_state) {
 427                 if (dm_digtable->cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
 428                         if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
 429                                 dm_digtable->cur_cck_fa_state =
 430                                     CCK_FA_STAGE_High;
 431                         else
 432                                 dm_digtable->cur_cck_fa_state = CCK_FA_STAGE_Low;
 433
 434                         if (dm_digtable->pre_cck_fa_state !=
 435                             dm_digtable->cur_cck_fa_state) {
 436                                 if (dm_digtable->cur_cck_fa_state ==
 437                                     CCK_FA_STAGE_Low)
 438                                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
 439                                                       0x83);
 440                                 else
 441                                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
 442                                                       0xcd);
 443
 444                                 dm_digtable->pre_cck_fa_state =
 445                                     dm_digtable->cur_cck_fa_state;
 446                         }
 447
 448                         rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
 449
 450                         if (IS_92C_SERIAL(rtlhal->version))
 451                                 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
 452                                               MASKBYTE2, 0xd7);
 453                 } else {
 454                         rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
 455                         rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
 456
 457                         if (IS_92C_SERIAL(rtlhal->version))
 458                                 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
 459                                               MASKBYTE2, 0xd3);
 460                 }
 461                 dm_digtable->pre_cck_pd_state = dm_digtable->cur_cck_pd_state;
 462         }
 463
 464         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
 465                  dm_digtable->cur_cck_pd_state);
 466
 467         RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
 468                  IS_92C_SERIAL(rtlhal->version));
 469 }
 470
 471 static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
 472 {
 473         struct rtl_priv *rtlpriv = rtl_priv(hw);
 474         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 475         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 476
 477         if (mac->act_scanning)
 478                 return;
 479
 480         if (mac->link_state >= MAC80211_LINKED)
 481                 dm_digtable->cursta_cstate = DIG_STA_CONNECT;
 482         else
 483                 dm_digtable->cursta_cstate = DIG_STA_DISCONNECT;
 484
 485         rtl92c_dm_initial_gain_sta(hw);
 486         rtl92c_dm_initial_gain_multi_sta(hw);
 487         rtl92c_dm_cck_packet_detection_thresh(hw);
 488
 489         dm_digtable->presta_cstate = dm_digtable->cursta_cstate;
 490
 491 }
 492
 493 static void rtl92c_dm_dig(struct ieee80211_hw *hw)
 494 {
 495         struct rtl_priv *rtlpriv = rtl_priv(hw);
 496         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 497
 498         if (rtlpriv->dm.dm_initialgain_enable == false)
 499                 return;
 500         if (dm_digtable->dig_enable_flag == false)
 501                 return;
 502
 503         rtl92c_dm_ctrl_initgain_by_twoport(hw);
 504
 505 }
 506
 507 static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
 508 {
 509         struct rtl_priv *rtlpriv = rtl_priv(hw);
 510
 511         rtlpriv->dm.dynamic_txpower_enable = false;
 512
 513         rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
 514         rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
 515 }
 516
 517 void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
 518 {
 519         struct rtl_priv *rtlpriv = rtl_priv(hw);
 520         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
 521
 522         RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
 523                  "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
 524                  dm_digtable->cur_igvalue, dm_digtable->pre_igvalue,
 525                  dm_digtable->back_val);
 526
 527         dm_digtable->cur_igvalue += 2;
 528         if (dm_digtable->cur_igvalue > 0x3f)
 529                 dm_digtable->cur_igvalue = 0x3f;
 530
 531         if (dm_digtable->pre_igvalue != dm_digtable->cur_igvalue) {
 532                 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
 533                               dm_digtable->cur_igvalue);
 534                 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
 535                               dm_digtable->cur_igvalue);
 536
 537                 dm_digtable->pre_igvalue = dm_digtable->cur_igvalue;
 538         }
 539 }
 540 EXPORT_SYMBOL(rtl92c_dm_write_dig);
 541
 542 static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
 543 {
 544         struct rtl_priv *rtlpriv = rtl_priv(hw);
 545         long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
 546
 547         u8 h2c_parameter[3] = { 0 };
 548
 549         return;
 550
 551         if (tmpentry_max_pwdb != 0) {
 552                 rtlpriv->dm.entry_max_undec_sm_pwdb = tmpentry_max_pwdb;
 553         } else {
 554                 rtlpriv->dm.entry_max_undec_sm_pwdb = 0;
 555         }
 556
 557         if (tmpentry_min_pwdb != 0xff) {
 558                 rtlpriv->dm.entry_min_undec_sm_pwdb = tmpentry_min_pwdb;
 559         } else {
 560                 rtlpriv->dm.entry_min_undec_sm_pwdb = 0;
 561         }
 562
 563         h2c_parameter[2] = (u8) (rtlpriv->dm.undec_sm_pwdb & 0xFF);
 564         h2c_parameter[0] = 0;
 565
 566         rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
 567 }
 568
 569 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
 570 {
 571         struct rtl_priv *rtlpriv = rtl_priv(hw);
 572         rtlpriv->dm.current_turbo_edca = false;
 573         rtlpriv->dm.is_any_nonbepkts = false;
 574         rtlpriv->dm.is_cur_rdlstate = false;
 575 }
 576 EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
 577
 578 static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
 579 {
 580         struct rtl_priv *rtlpriv = rtl_priv(hw);
 581         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
 582         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 583
 584         static u64 last_txok_cnt;
 585         static u64 last_rxok_cnt;
 586         static u32 last_bt_edca_ul;
 587         static u32 last_bt_edca_dl;
 588         u64 cur_txok_cnt = 0;
 589         u64 cur_rxok_cnt = 0;
 590         u32 edca_be_ul = 0x5ea42b;
 591         u32 edca_be_dl = 0x5ea42b;
 592         bool bt_change_edca = false;
 593
 594         if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
 595             (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
 596                 rtlpriv->dm.current_turbo_edca = false;
 597                 last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
 598                 last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
 599         }
 600
 601         if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
 602                 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
 603                 bt_change_edca = true;
 604         }
 605
 606         if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
 607                 edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
 608                 bt_change_edca = true;
 609         }
 610
 611         if (mac->link_state != MAC80211_LINKED) {
 612                 rtlpriv->dm.current_turbo_edca = false;
 613                 return;
 614         }
 615
 616         if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
 617                 if (!(edca_be_ul & 0xffff0000))
 618                         edca_be_ul |= 0x005e0000;
 619
 620                 if (!(edca_be_dl & 0xffff0000))
 621                         edca_be_dl |= 0x005e0000;
 622         }
 623
 624         if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
 625              (!rtlpriv->dm.disable_framebursting))) {
 626
 627                 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
 628                 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
 629
 630                 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
 631                         if (!rtlpriv->dm.is_cur_rdlstate ||
 632                             !rtlpriv->dm.current_turbo_edca) {
 633                                 rtl_write_dword(rtlpriv,
 634                                                 REG_EDCA_BE_PARAM,
 635                                                 edca_be_dl);
 636                                 rtlpriv->dm.is_cur_rdlstate = true;
 637                         }
 638                 } else {
 639                         if (rtlpriv->dm.is_cur_rdlstate ||
 640                             !rtlpriv->dm.current_turbo_edca) {
 641                                 rtl_write_dword(rtlpriv,
 642                                                 REG_EDCA_BE_PARAM,
 643                                                 edca_be_ul);
 644                                 rtlpriv->dm.is_cur_rdlstate = false;
 645                         }
 646                 }
 647                 rtlpriv->dm.current_turbo_edca = true;
 648         } else {
 649                 if (rtlpriv->dm.current_turbo_edca) {
 650                         u8 tmp = AC0_BE;
 651                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 652                                                       &tmp);
 653                         rtlpriv->dm.current_turbo_edca = false;
 654                 }
 655         }
 656
 657         rtlpriv->dm.is_any_nonbepkts = false;
 658         last_txok_cnt = rtlpriv->stats.txbytesunicast;
 659         last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
 660 }
 661
 662 static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
 663                                                              *hw)
 664 {
 665         struct rtl_priv *rtlpriv = rtl_priv(hw);
 666         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 667         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 668         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 669         u8 thermalvalue, delta, delta_lck, delta_iqk;
 670         long ele_a, ele_d, temp_cck, val_x, value32;
 671         long val_y, ele_c = 0;
 672         u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
 673         int i;
 674         bool is2t = IS_92C_SERIAL(rtlhal->version);
 675         s8 txpwr_level[2] = {0, 0};
 676         u8 ofdm_min_index = 6, rf;
 677
 678         rtlpriv->dm.txpower_trackinginit = true;
 679         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 680                  "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
 681
 682         thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
 683
 684         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 685                  "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
 686                  thermalvalue, rtlpriv->dm.thermalvalue,
 687                  rtlefuse->eeprom_thermalmeter);
 688
 689         rtl92c_phy_ap_calibrate(hw, (thermalvalue -
 690                                      rtlefuse->eeprom_thermalmeter));
 691         if (is2t)
 692                 rf = 2;
 693         else
 694                 rf = 1;
 695
 696         if (thermalvalue) {
 697                 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 698                                       MASKDWORD) & MASKOFDM_D;
 699
 700                 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
 701                         if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
 702                                 ofdm_index_old[0] = (u8) i;
 703
 704                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 705                                          "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
 706                                          ROFDM0_XATXIQIMBALANCE,
 707                                          ele_d, ofdm_index_old[0]);
 708                                 break;
 709                         }
 710                 }
 711
 712                 if (is2t) {
 713                         ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
 714                                               MASKDWORD) & MASKOFDM_D;
 715
 716                         for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
 717                                 if (ele_d == (ofdmswing_table[i] &
 718                                     MASKOFDM_D)) {
 719
 720                                         RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 721                                                  DBG_LOUD,
 722                                                  "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
 723                                                  ROFDM0_XBTXIQIMBALANCE, ele_d,
 724                                                  ofdm_index_old[1]);
 725                                         break;
 726                                 }
 727                         }
 728                 }
 729
 730                 temp_cck =
 731                     rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
 732
 733                 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
 734                         if (rtlpriv->dm.cck_inch14) {
 735                                 if (memcmp((void *)&temp_cck,
 736                                            (void *)&cckswing_table_ch14[i][2],
 737                                            4) == 0) {
 738                                         cck_index_old = (u8) i;
 739
 740                                         RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 741                                                  DBG_LOUD,
 742                                                  "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
 743                                                  RCCK0_TXFILTER2, temp_cck,
 744                                                  cck_index_old,
 745                                                  rtlpriv->dm.cck_inch14);
 746                                         break;
 747                                 }
 748                         } else {
 749                                 if (memcmp((void *)&temp_cck,
 750                                            (void *)
 751                                            &cckswing_table_ch1ch13[i][2],
 752                                            4) == 0) {
 753                                         cck_index_old = (u8) i;
 754
 755                                         RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
 756                                                  DBG_LOUD,
 757                                                  "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
 758                                                  RCCK0_TXFILTER2, temp_cck,
 759                                                  cck_index_old,
 760                                                  rtlpriv->dm.cck_inch14);
 761                                         break;
 762                                 }
 763                         }
 764                 }
 765
 766                 if (!rtlpriv->dm.thermalvalue) {
 767                         rtlpriv->dm.thermalvalue =
 768                             rtlefuse->eeprom_thermalmeter;
 769                         rtlpriv->dm.thermalvalue_lck = thermalvalue;
 770                         rtlpriv->dm.thermalvalue_iqk = thermalvalue;
 771                         for (i = 0; i < rf; i++)
 772                                 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
 773                         rtlpriv->dm.cck_index = cck_index_old;
 774                 }
 775
 776                 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
 777                     (thermalvalue - rtlpriv->dm.thermalvalue) :
 778                     (rtlpriv->dm.thermalvalue - thermalvalue);
 779
 780                 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
 781                     (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
 782                     (rtlpriv->dm.thermalvalue_lck - thermalvalue);
 783
 784                 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
 785                     (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
 786                     (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
 787
 788                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 789                          "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
 790                          thermalvalue, rtlpriv->dm.thermalvalue,
 791                          rtlefuse->eeprom_thermalmeter, delta, delta_lck,
 792                          delta_iqk);
 793
 794                 if (delta_lck > 1) {
 795                         rtlpriv->dm.thermalvalue_lck = thermalvalue;
 796                         rtl92c_phy_lc_calibrate(hw);
 797                 }
 798
 799                 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
 800                         if (thermalvalue > rtlpriv->dm.thermalvalue) {
 801                                 for (i = 0; i < rf; i++)
 802                                         rtlpriv->dm.ofdm_index[i] -= delta;
 803                                 rtlpriv->dm.cck_index -= delta;
 804                         } else {
 805                                 for (i = 0; i < rf; i++)
 806                                         rtlpriv->dm.ofdm_index[i] += delta;
 807                                 rtlpriv->dm.cck_index += delta;
 808                         }
 809
 810                         if (is2t) {
 811                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 812                                          "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
 813                                          rtlpriv->dm.ofdm_index[0],
 814                                          rtlpriv->dm.ofdm_index[1],
 815                                          rtlpriv->dm.cck_index);
 816                         } else {
 817                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 818                                          "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
 819                                          rtlpriv->dm.ofdm_index[0],
 820                                          rtlpriv->dm.cck_index);
 821                         }
 822
 823                         if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
 824                                 for (i = 0; i < rf; i++)
 825                                         ofdm_index[i] =
 826                                             rtlpriv->dm.ofdm_index[i]
 827                                             + 1;
 828                                 cck_index = rtlpriv->dm.cck_index + 1;
 829                         } else {
 830                                 for (i = 0; i < rf; i++)
 831                                         ofdm_index[i] =
 832                                             rtlpriv->dm.ofdm_index[i];
 833                                 cck_index = rtlpriv->dm.cck_index;
 834                         }
 835
 836                         for (i = 0; i < rf; i++) {
 837                                 if (txpwr_level[i] >= 0 &&
 838                                     txpwr_level[i] <= 26) {
 839                                         if (thermalvalue >
 840                                             rtlefuse->eeprom_thermalmeter) {
 841                                                 if (delta < 5)
 842                                                         ofdm_index[i] -= 1;
 843
 844                                                 else
 845                                                         ofdm_index[i] -= 2;
 846                                         } else if (delta > 5 && thermalvalue <
 847                                                    rtlefuse->
 848                                                    eeprom_thermalmeter) {
 849                                                 ofdm_index[i] += 1;
 850                                         }
 851                                 } else if (txpwr_level[i] >= 27 &&
 852                                            txpwr_level[i] <= 32
 853                                            && thermalvalue >
 854                                            rtlefuse->eeprom_thermalmeter) {
 855                                         if (delta < 5)
 856                                                 ofdm_index[i] -= 1;
 857
 858                                         else
 859                                                 ofdm_index[i] -= 2;
 860                                 } else if (txpwr_level[i] >= 32 &&
 861                                            txpwr_level[i] <= 38 &&
 862                                            thermalvalue >
 863                                            rtlefuse->eeprom_thermalmeter
 864                                            && delta > 5) {
 865                                         ofdm_index[i] -= 1;
 866                                 }
 867                         }
 868
 869                         if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
 870                                 if (thermalvalue >
 871                                     rtlefuse->eeprom_thermalmeter) {
 872                                         if (delta < 5)
 873                                                 cck_index -= 1;
 874
 875                                         else
 876                                                 cck_index -= 2;
 877                                 } else if (delta > 5 && thermalvalue <
 878                                            rtlefuse->eeprom_thermalmeter) {
 879                                         cck_index += 1;
 880                                 }
 881                         } else if (txpwr_level[i] >= 27 &&
 882                                    txpwr_level[i] <= 32 &&
 883                                    thermalvalue >
 884                                    rtlefuse->eeprom_thermalmeter) {
 885                                 if (delta < 5)
 886                                         cck_index -= 1;
 887
 888                                 else
 889                                         cck_index -= 2;
 890                         } else if (txpwr_level[i] >= 32 &&
 891                                    txpwr_level[i] <= 38 &&
 892                                    thermalvalue > rtlefuse->eeprom_thermalmeter
 893                                    && delta > 5) {
 894                                 cck_index -= 1;
 895                         }
 896
 897                         for (i = 0; i < rf; i++) {
 898                                 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
 899                                         ofdm_index[i] = OFDM_TABLE_SIZE - 1;
 900
 901                                 else if (ofdm_index[i] < ofdm_min_index)
 902                                         ofdm_index[i] = ofdm_min_index;
 903                         }
 904
 905                         if (cck_index > CCK_TABLE_SIZE - 1)
 906                                 cck_index = CCK_TABLE_SIZE - 1;
 907                         else if (cck_index < 0)
 908                                 cck_index = 0;
 909
 910                         if (is2t) {
 911                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 912                                          "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
 913                                          ofdm_index[0], ofdm_index[1],
 914                                          cck_index);
 915                         } else {
 916                                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
 917                                          "new OFDM_A_index=0x%x, cck_index=0x%x\n",
 918                                          ofdm_index[0], cck_index);
 919                         }
 920                 }
 921
 922                 if (rtlpriv->dm.txpower_track_control && delta != 0) {
 923                         ele_d =
 924                             (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
 925                         val_x = rtlphy->reg_e94;
 926                         val_y = rtlphy->reg_e9c;
 927
 928                         if (val_x != 0) {
 929                                 if ((val_x & 0x00000200) != 0)
 930                                         val_x = val_x | 0xFFFFFC00;
 931                                 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
 932
 933                                 if ((val_y & 0x00000200) != 0)
 934                                         val_y = val_y | 0xFFFFFC00;
 935                                 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
 936
 937                                 value32 = (ele_d << 22) |
 938                                     ((ele_c & 0x3F) << 16) | ele_a;
 939
 940                                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 941                                               MASKDWORD, value32);
 942
 943                                 value32 = (ele_c & 0x000003C0) >> 6;
 944                                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
 945                                               value32);
 946
 947                                 value32 = ((val_x * ele_d) >> 7) & 0x01;
 948                                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 949                                               BIT(31), value32);
 950
 951                                 value32 = ((val_y * ele_d) >> 7) & 0x01;
 952                                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 953                                               BIT(29), value32);
 954                         } else {
 955                                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
 956                                               MASKDWORD,
 957                                               ofdmswing_table[ofdm_index[0]]);
 958
 959                                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
 960                                               0x00);
 961                                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
 962                                               BIT(31) | BIT(29), 0x00);
 963                         }
 964
 965                         if (!rtlpriv->dm.cck_inch14) {
 966                                 rtl_write_byte(rtlpriv, 0xa22,
 967                                                cckswing_table_ch1ch13[cck_index]
 968                                                [0]);
 969                                 rtl_write_byte(rtlpriv, 0xa23,
 970                                                cckswing_table_ch1ch13[cck_index]
 971                                                [1]);
 972                                 rtl_write_byte(rtlpriv, 0xa24,
 973                                                cckswing_table_ch1ch13[cck_index]
 974                                                [2]);
 975                                 rtl_write_byte(rtlpriv, 0xa25,
 976                                                cckswing_table_ch1ch13[cck_index]
 977                                                [3]);
 978                                 rtl_write_byte(rtlpriv, 0xa26,
 979                                                cckswing_table_ch1ch13[cck_index]
 980                                                [4]);
 981                                 rtl_write_byte(rtlpriv, 0xa27,
 982                                                cckswing_table_ch1ch13[cck_index]
 983                                                [5]);
 984                                 rtl_write_byte(rtlpriv, 0xa28,
 985                                                cckswing_table_ch1ch13[cck_index]
 986                                                [6]);
 987                                 rtl_write_byte(rtlpriv, 0xa29,
 988                                                cckswing_table_ch1ch13[cck_index]
 989                                                [7]);
 990                         } else {
 991                                 rtl_write_byte(rtlpriv, 0xa22,
 992                                                cckswing_table_ch14[cck_index]
 993                                                [0]);
 994                                 rtl_write_byte(rtlpriv, 0xa23,
 995                                                cckswing_table_ch14[cck_index]
 996                                                [1]);
 997                                 rtl_write_byte(rtlpriv, 0xa24,
 998                                                cckswing_table_ch14[cck_index]
 999                                                [2]);
1000                                 rtl_write_byte(rtlpriv, 0xa25,
1001                                                cckswing_table_ch14[cck_index]
1002                                                [3]);
1003                                 rtl_write_byte(rtlpriv, 0xa26,
1004                                                cckswing_table_ch14[cck_index]
1005                                                [4]);
1006                                 rtl_write_byte(rtlpriv, 0xa27,
1007                                                cckswing_table_ch14[cck_index]
1008                                                [5]);
1009                                 rtl_write_byte(rtlpriv, 0xa28,
1010                                                cckswing_table_ch14[cck_index]
1011                                                [6]);
1012                                 rtl_write_byte(rtlpriv, 0xa29,
1013                                                cckswing_table_ch14[cck_index]
1014                                                [7]);
1015                         }
1016
1017                         if (is2t) {
1018                                 ele_d = (ofdmswing_table[ofdm_index[1]] &
1019                                          0xFFC00000) >> 22;
1020
1021                                 val_x = rtlphy->reg_eb4;
1022                                 val_y = rtlphy->reg_ebc;
1023
1024                                 if (val_x != 0) {
1025                                         if ((val_x & 0x00000200) != 0)
1026                                                 val_x = val_x | 0xFFFFFC00;
1027                                         ele_a = ((val_x * ele_d) >> 8) &
1028                                             0x000003FF;
1029
1030                                         if ((val_y & 0x00000200) != 0)
1031                                                 val_y = val_y | 0xFFFFFC00;
1032                                         ele_c = ((val_y * ele_d) >> 8) &
1033                                             0x00003FF;
1034
1035                                         value32 = (ele_d << 22) |
1036                                             ((ele_c & 0x3F) << 16) | ele_a;
1037                                         rtl_set_bbreg(hw,
1038                                                       ROFDM0_XBTXIQIMBALANCE,
1039                                                       MASKDWORD, value32);
1040
1041                                         value32 = (ele_c & 0x000003C0) >> 6;
1042                                         rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1043                                                       MASKH4BITS, value32);
1044
1045                                         value32 = ((val_x * ele_d) >> 7) & 0x01;
1046                                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1047                                                       BIT(27), value32);
1048
1049                                         value32 = ((val_y * ele_d) >> 7) & 0x01;
1050                                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1051                                                       BIT(25), value32);
1052                                 } else {
1053                                         rtl_set_bbreg(hw,
1054                                                       ROFDM0_XBTXIQIMBALANCE,
1055                                                       MASKDWORD,
1056                                                       ofdmswing_table[ofdm_index
1057                                                                       [1]]);
1058                                         rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1059                                                       MASKH4BITS, 0x00);
1060                                         rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1061                                                       BIT(27) | BIT(25), 0x00);
1062                                 }
1063
1064                         }
1065                 }
1066
1067                 if (delta_iqk > 3) {
1068                         rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1069                         rtl92c_phy_iq_calibrate(hw, false);
1070                 }
1071
1072                 if (rtlpriv->dm.txpower_track_control)
1073                         rtlpriv->dm.thermalvalue = thermalvalue;
1074         }
1075
1076         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
1077
1078 }
1079
1080 static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1081                                                 struct ieee80211_hw *hw)
1082 {
1083         struct rtl_priv *rtlpriv = rtl_priv(hw);
1084
1085         rtlpriv->dm.txpower_tracking = true;
1086         rtlpriv->dm.txpower_trackinginit = false;
1087
1088         RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1089                  "pMgntInfo->txpower_tracking = %d\n",
1090                  rtlpriv->dm.txpower_tracking);
1091 }
1092
1093 static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1094 {
1095         rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1096 }
1097
1098 static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1099 {
1100         rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1101 }
1102
1103 static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1104                                                 struct ieee80211_hw *hw)
1105 {
1106         struct rtl_priv *rtlpriv = rtl_priv(hw);
1107         static u8 tm_trigger;
1108
1109         if (!rtlpriv->dm.txpower_tracking)
1110                 return;
1111
1112         if (!tm_trigger) {
1113                 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1114                               0x60);
1115                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1116                          "Trigger 92S Thermal Meter!!\n");
1117                 tm_trigger = 1;
1118                 return;
1119         } else {
1120                 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1121                          "Schedule TxPowerTracking direct call!!\n");
1122                 rtl92c_dm_txpower_tracking_directcall(hw);
1123                 tm_trigger = 0;
1124         }
1125 }
1126
1127 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1128 {
1129         rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1130 }
1131 EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
1132
1133 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1134 {
1135         struct rtl_priv *rtlpriv = rtl_priv(hw);
1136         struct rate_adaptive *p_ra = &(rtlpriv->ra);
1137
1138         p_ra->ratr_state = DM_RATR_STA_INIT;
1139         p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1140
1141         if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1142                 rtlpriv->dm.useramask = true;
1143         else
1144                 rtlpriv->dm.useramask = false;
1145
1146 }
1147 EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
1148
1149 static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1150 {
1151         struct rtl_priv *rtlpriv = rtl_priv(hw);
1152         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1153         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1154         struct rate_adaptive *p_ra = &(rtlpriv->ra);
1155         u32 low_rssi_thresh, high_rssi_thresh;
1156         struct ieee80211_sta *sta = NULL;
1157
1158         if (is_hal_stop(rtlhal)) {
1159                 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1160                          "<---- driver is going to unload\n");
1161                 return;
1162         }
1163
1164         if (!rtlpriv->dm.useramask) {
1165                 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1166                          "<---- driver does not control rate adaptive mask\n");
1167                 return;
1168         }
1169
1170         if (mac->link_state == MAC80211_LINKED &&
1171             mac->opmode == NL80211_IFTYPE_STATION) {
1172                 switch (p_ra->pre_ratr_state) {
1173                 case DM_RATR_STA_HIGH:
1174                         high_rssi_thresh = 50;
1175                         low_rssi_thresh = 20;
1176                         break;
1177                 case DM_RATR_STA_MIDDLE:
1178                         high_rssi_thresh = 55;
1179                         low_rssi_thresh = 20;
1180                         break;
1181                 case DM_RATR_STA_LOW:
1182                         high_rssi_thresh = 50;
1183                         low_rssi_thresh = 25;
1184                         break;
1185                 default:
1186                         high_rssi_thresh = 50;
1187                         low_rssi_thresh = 20;
1188                         break;
1189                 }
1190
1191                 if (rtlpriv->dm.undec_sm_pwdb > (long)high_rssi_thresh)
1192                         p_ra->ratr_state = DM_RATR_STA_HIGH;
1193                 else if (rtlpriv->dm.undec_sm_pwdb > (long)low_rssi_thresh)
1194                         p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1195                 else
1196                         p_ra->ratr_state = DM_RATR_STA_LOW;
1197
1198                 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1199                         RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, "RSSI = %ld\n",
1200                                  rtlpriv->dm.undec_sm_pwdb);
1201                         RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1202                                  "RSSI_LEVEL = %d\n", p_ra->ratr_state);
1203                         RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1204                                  "PreState = %d, CurState = %d\n",
1205                                  p_ra->pre_ratr_state, p_ra->ratr_state);
1206
1207                         rcu_read_lock();
1208                         sta = ieee80211_find_sta(mac->vif, mac->bssid);
1209                         rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
1210                                         p_ra->ratr_state);
1211
1212                         p_ra->pre_ratr_state = p_ra->ratr_state;
1213                         rcu_read_unlock();
1214                 }
1215         }
1216 }
1217
1218 static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1219 {
1220         struct rtl_priv *rtlpriv = rtl_priv(hw);
1221         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1222
1223         dm_pstable->pre_ccastate = CCA_MAX;
1224         dm_pstable->cur_ccasate = CCA_MAX;
1225         dm_pstable->pre_rfstate = RF_MAX;
1226         dm_pstable->cur_rfstate = RF_MAX;
1227         dm_pstable->rssi_val_min = 0;
1228 }
1229
1230 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1231 {
1232         struct rtl_priv *rtlpriv = rtl_priv(hw);
1233         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1234         static u8 initialize;
1235         static u32 reg_874, reg_c70, reg_85c, reg_a74;
1236
1237         if (initialize == 0) {
1238                 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1239                                          MASKDWORD) & 0x1CC000) >> 14;
1240
1241                 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1242                                          MASKDWORD) & BIT(3)) >> 3;
1243
1244                 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1245                                          MASKDWORD) & 0xFF000000) >> 24;
1246
1247                 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1248
1249                 initialize = 1;
1250         }
1251
1252         if (!bforce_in_normal) {
1253                 if (dm_pstable->rssi_val_min != 0) {
1254                         if (dm_pstable->pre_rfstate == RF_NORMAL) {
1255                                 if (dm_pstable->rssi_val_min >= 30)
1256                                         dm_pstable->cur_rfstate = RF_SAVE;
1257                                 else
1258                                         dm_pstable->cur_rfstate = RF_NORMAL;
1259                         } else {
1260                                 if (dm_pstable->rssi_val_min <= 25)
1261                                         dm_pstable->cur_rfstate = RF_NORMAL;
1262                                 else
1263                                         dm_pstable->cur_rfstate = RF_SAVE;
1264                         }
1265                 } else {
1266                         dm_pstable->cur_rfstate = RF_MAX;
1267                 }
1268         } else {
1269                 dm_pstable->cur_rfstate = RF_NORMAL;
1270         }
1271
1272         if (dm_pstable->pre_rfstate != dm_pstable->cur_rfstate) {
1273                 if (dm_pstable->cur_rfstate == RF_SAVE) {
1274                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1275                                       0x1C0000, 0x2);
1276                         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1277                         rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1278                                       0xFF000000, 0x63);
1279                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1280                                       0xC000, 0x2);
1281                         rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1282                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1283                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1284                 } else {
1285                         rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1286                                       0x1CC000, reg_874);
1287                         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1288                                       reg_c70);
1289                         rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1290                                       reg_85c);
1291                         rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1292                         rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1293                 }
1294
1295                 dm_pstable->pre_rfstate = dm_pstable->cur_rfstate;
1296         }
1297 }
1298 EXPORT_SYMBOL(rtl92c_dm_rf_saving);
1299
1300 static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1301 {
1302         struct rtl_priv *rtlpriv = rtl_priv(hw);
1303         struct ps_t *dm_pstable = &rtlpriv->dm_pstable;
1304         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1305         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1306
1307         if (((mac->link_state == MAC80211_NOLINK)) &&
1308             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1309                 dm_pstable->rssi_val_min = 0;
1310                 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
1311         }
1312
1313         if (mac->link_state == MAC80211_LINKED) {
1314                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1315                         dm_pstable->rssi_val_min =
1316                             rtlpriv->dm.entry_min_undec_sm_pwdb;
1317                         RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1318                                  "AP Client PWDB = 0x%lx\n",
1319                                  dm_pstable->rssi_val_min);
1320                 } else {
1321                         dm_pstable->rssi_val_min = rtlpriv->dm.undec_sm_pwdb;
1322                         RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1323                                  "STA Default Port PWDB = 0x%lx\n",
1324                                  dm_pstable->rssi_val_min);
1325                 }
1326         } else {
1327                 dm_pstable->rssi_val_min =
1328                     rtlpriv->dm.entry_min_undec_sm_pwdb;
1329
1330                 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1331                          "AP Ext Port PWDB = 0x%lx\n",
1332                          dm_pstable->rssi_val_min);
1333         }
1334
1335         if (IS_92C_SERIAL(rtlhal->version))
1336                 ;/* rtl92c_dm_1r_cca(hw); */
1337         else
1338                 rtl92c_dm_rf_saving(hw, false);
1339 }
1340
1341 void rtl92c_dm_init(struct ieee80211_hw *hw)
1342 {
1343         struct rtl_priv *rtlpriv = rtl_priv(hw);
1344
1345         rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1346         rtl92c_dm_diginit(hw);
1347         rtl92c_dm_init_dynamic_txpower(hw);
1348         rtl92c_dm_init_edca_turbo(hw);
1349         rtl92c_dm_init_rate_adaptive_mask(hw);
1350         rtl92c_dm_initialize_txpower_tracking(hw);
1351         rtl92c_dm_init_dynamic_bb_powersaving(hw);
1352 }
1353 EXPORT_SYMBOL(rtl92c_dm_init);
1354
1355 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
1356 {
1357         struct rtl_priv *rtlpriv = rtl_priv(hw);
1358         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1359         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1360         long undec_sm_pwdb;
1361
1362         if (!rtlpriv->dm.dynamic_txpower_enable)
1363                 return;
1364
1365         if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
1366                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1367                 return;
1368         }
1369
1370         if ((mac->link_state < MAC80211_LINKED) &&
1371             (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)) {
1372                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1373                          "Not connected to any\n");
1374
1375                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1376
1377                 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
1378                 return;
1379         }
1380
1381         if (mac->link_state >= MAC80211_LINKED) {
1382                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1383                         undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1384                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1385                                  "AP Client PWDB = 0x%lx\n",
1386                                  undec_sm_pwdb);
1387                 } else {
1388                         undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb;
1389                         RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1390                                  "STA Default Port PWDB = 0x%lx\n",
1391                                  undec_sm_pwdb);
1392                 }
1393         } else {
1394                 undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1395
1396                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1397                          "AP Ext Port PWDB = 0x%lx\n",
1398                          undec_sm_pwdb);
1399         }
1400
1401         if (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
1402                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1403                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1404                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
1405         } else if ((undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
1406                    (undec_sm_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
1407
1408                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
1409                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1410                          "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
1411         } else if (undec_sm_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
1412                 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
1413                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1414                          "TXHIGHPWRLEVEL_NORMAL\n");
1415         }
1416
1417         if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
1418                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1419                          "PHY_SetTxPowerLevel8192S() Channel = %d\n",
1420                          rtlphy->current_channel);
1421                 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1422         }
1423
1424         rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
1425 }
1426
1427 void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1428 {
1429         struct rtl_priv *rtlpriv = rtl_priv(hw);
1430         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1431         bool fw_current_inpsmode = false;
1432         bool fw_ps_awake = true;
1433
1434         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1435                                       (u8 *) (&fw_current_inpsmode));
1436         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1437                                       (u8 *) (&fw_ps_awake));
1438
1439         if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1440                                              fw_ps_awake)
1441             && (!ppsc->rfchange_inprogress)) {
1442                 rtl92c_dm_pwdb_monitor(hw);
1443                 rtl92c_dm_dig(hw);
1444                 rtl92c_dm_false_alarm_counter_statistics(hw);
1445                 rtl92c_dm_dynamic_bb_powersaving(hw);
1446                 rtl92c_dm_dynamic_txpower(hw);
1447                 rtl92c_dm_check_txpower_tracking(hw);
1448                 rtl92c_dm_refresh_rate_adaptive_mask(hw);
1449                 rtl92c_dm_bt_coexist(hw);
1450                 rtl92c_dm_check_edca_turbo(hw);
1451         }
1452 }
1453 EXPORT_SYMBOL(rtl92c_dm_watchdog);
1454
1455 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
1456 {
1457         struct rtl_priv *rtlpriv = rtl_priv(hw);
1458         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1459         long undec_sm_pwdb;
1460         u8 curr_bt_rssi_state = 0x00;
1461
1462         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1463                 undec_sm_pwdb = GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
1464         } else {
1465                 if (rtlpriv->dm.entry_min_undec_sm_pwdb == 0)
1466                         undec_sm_pwdb = 100;
1467                 else
1468                         undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb;
1469         }
1470
1471         /* Check RSSI to determine HighPower/NormalPower state for
1472          * BT coexistence. */
1473         if (undec_sm_pwdb >= 67)
1474                 curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
1475         else if (undec_sm_pwdb < 62)
1476                 curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
1477
1478         /* Check RSSI to determine AMPDU setting for BT coexistence. */
1479         if (undec_sm_pwdb >= 40)
1480                 curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
1481         else if (undec_sm_pwdb <= 32)
1482                 curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
1483
1484         /* Marked RSSI state. It will be used to determine BT coexistence
1485          * setting later. */
1486         if (undec_sm_pwdb < 35)
1487                 curr_bt_rssi_state |=  BT_RSSI_STATE_SPECIAL_LOW;
1488         else
1489                 curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
1490
1491         /* Set Tx Power according to BT status. */
1492         if (undec_sm_pwdb >= 30)
1493                 curr_bt_rssi_state |=  BT_RSSI_STATE_TXPOWER_LOW;
1494         else if (undec_sm_pwdb < 25)
1495                 curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
1496
1497         /* Check BT state related to BT_Idle in B/G mode. */
1498         if (undec_sm_pwdb < 15)
1499                 curr_bt_rssi_state |=  BT_RSSI_STATE_BG_EDCA_LOW;
1500         else
1501                 curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
1502
1503         if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
1504                 rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
1505                 return true;
1506         } else {
1507                 return false;
1508         }
1509 }
1510 EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
1511
1512 static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
1513 {
1514         struct rtl_priv *rtlpriv = rtl_priv(hw);
1515         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1516
1517         u32 polling, ratio_tx, ratio_pri;
1518         u32 bt_tx, bt_pri;
1519         u8 bt_state;
1520         u8 cur_service_type;
1521
1522         if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
1523                 return false;
1524
1525         bt_state = rtl_read_byte(rtlpriv, 0x4fd);
1526         bt_tx = rtl_read_dword(rtlpriv, 0x488);
1527         bt_tx = bt_tx & 0x00ffffff;
1528         bt_pri = rtl_read_dword(rtlpriv, 0x48c);
1529         bt_pri = bt_pri & 0x00ffffff;
1530         polling = rtl_read_dword(rtlpriv, 0x490);
1531
1532         if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
1533             polling == 0xffffffff && bt_state == 0xff)
1534                 return false;
1535
1536         bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
1537         if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
1538                 rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
1539
1540                 if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1541                         rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
1542
1543                         bt_state = bt_state |
1544                           ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1545                           0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1546                           BIT_OFFSET_LEN_MASK_32(2, 1);
1547                         rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1548                 }
1549                 return true;
1550         }
1551
1552         ratio_tx = bt_tx * 1000 / polling;
1553         ratio_pri = bt_pri * 1000 / polling;
1554         rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
1555         rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
1556
1557         if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
1558
1559                 if ((ratio_tx < 30)  && (ratio_pri < 30))
1560                         cur_service_type = BT_IDLE;
1561                 else if ((ratio_pri > 110) && (ratio_pri < 250))
1562                         cur_service_type = BT_SCO;
1563                 else if ((ratio_tx >= 200) && (ratio_pri >= 200))
1564                         cur_service_type = BT_BUSY;
1565                 else if ((ratio_tx >= 350) && (ratio_tx < 500))
1566                         cur_service_type = BT_OTHERBUSY;
1567                 else if (ratio_tx >= 500)
1568                         cur_service_type = BT_PAN;
1569                 else
1570                         cur_service_type = BT_OTHER_ACTION;
1571
1572                 if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
1573                         rtlpcipriv->bt_coexist.bt_service = cur_service_type;
1574                         bt_state = bt_state |
1575                            ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
1576                            0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
1577                            ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
1578                            0 : BIT_OFFSET_LEN_MASK_32(2, 1));
1579
1580                         /* Add interrupt migration when bt is not ini
1581                          * idle state (no traffic). */
1582                         if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1583                                 rtl_write_word(rtlpriv, 0x504, 0x0ccc);
1584                                 rtl_write_byte(rtlpriv, 0x506, 0x54);
1585                                 rtl_write_byte(rtlpriv, 0x507, 0x54);
1586                         } else {
1587                                 rtl_write_byte(rtlpriv, 0x506, 0x00);
1588                                 rtl_write_byte(rtlpriv, 0x507, 0x00);
1589                         }
1590
1591                         rtl_write_byte(rtlpriv, 0x4fd, bt_state);
1592                         return true;
1593                 }
1594         }
1595
1596         return false;
1597
1598 }
1599
1600 static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
1601 {
1602         struct rtl_priv *rtlpriv = rtl_priv(hw);
1603         static bool media_connect;
1604
1605         if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1606                 media_connect = false;
1607         } else {
1608                 if (!media_connect) {
1609                         media_connect = true;
1610                         return true;
1611                 }
1612                 media_connect = true;
1613         }
1614
1615         return false;
1616 }
1617
1618 static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
1619 {
1620         struct rtl_priv *rtlpriv = rtl_priv(hw);
1621         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1622
1623
1624         if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
1625                 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
1626                 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
1627         } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
1628                 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
1629                 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
1630         } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
1631                 if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
1632                         rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
1633                         rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
1634                 } else {
1635                         rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
1636                         rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
1637                 }
1638         } else {
1639                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1640                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1641         }
1642
1643         if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
1644              (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
1645              (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
1646              (rtlpcipriv->bt_coexist.bt_rssi_state &
1647              BT_RSSI_STATE_BG_EDCA_LOW)) {
1648                 rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
1649                 rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
1650         }
1651 }
1652
1653 static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw)
1654 {
1655         struct rtl_priv *rtlpriv = rtl_priv(hw);
1656         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1657
1658
1659         /* Only enable HW BT coexist when BT in "Busy" state. */
1660         if (rtlpriv->mac80211.vendor == PEER_CISCO &&
1661             rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
1662                 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1663         } else {
1664                 if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
1665                     (rtlpcipriv->bt_coexist.bt_rssi_state &
1666                      BT_RSSI_STATE_NORMAL_POWER)) {
1667                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1668                 } else if ((rtlpcipriv->bt_coexist.bt_service ==
1669                             BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
1670                             WIRELESS_MODE_N_24G) &&
1671                             (rtlpcipriv->bt_coexist.bt_rssi_state &
1672                             BT_RSSI_STATE_SPECIAL_LOW)) {
1673                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
1674                 } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
1675                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1676                 } else {
1677                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1678                 }
1679         }
1680
1681         if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
1682                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
1683         else
1684                 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
1685
1686         if (rtlpcipriv->bt_coexist.bt_rssi_state &
1687             BT_RSSI_STATE_NORMAL_POWER) {
1688                 rtl92c_bt_set_normal(hw);
1689         } else {
1690                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1691                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1692         }
1693
1694         if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1695                 rtlpriv->cfg->ops->set_rfreg(hw,
1696                                  RF90_PATH_A,
1697                                  0x1e,
1698                                  0xf0, 0xf);
1699         } else {
1700                 rtlpriv->cfg->ops->set_rfreg(hw,
1701                      RF90_PATH_A, 0x1e, 0xf0,
1702                      rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1703         }
1704
1705         if (!rtlpriv->dm.dynamic_txpower_enable) {
1706                 if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
1707                         if (rtlpcipriv->bt_coexist.bt_rssi_state &
1708                                 BT_RSSI_STATE_TXPOWER_LOW) {
1709                                 rtlpriv->dm.dynamic_txhighpower_lvl =
1710                                                         TXHIGHPWRLEVEL_BT2;
1711                         } else {
1712                                 rtlpriv->dm.dynamic_txhighpower_lvl =
1713                                         TXHIGHPWRLEVEL_BT1;
1714                         }
1715                 } else {
1716                         rtlpriv->dm.dynamic_txhighpower_lvl =
1717                                 TXHIGHPWRLEVEL_NORMAL;
1718                 }
1719                 rtl92c_phy_set_txpower_level(hw,
1720                         rtlpriv->phy.current_channel);
1721         }
1722 }
1723
1724 static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
1725 {
1726         struct rtl_priv *rtlpriv = rtl_priv(hw);
1727         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1728
1729         if (rtlpcipriv->bt_coexist.bt_cur_state) {
1730                 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
1731                         rtl92c_bt_ant_isolation(hw);
1732         } else {
1733                 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
1734                 rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
1735                                 rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
1736
1737                 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
1738                 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
1739         }
1740 }
1741
1742 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
1743 {
1744         struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1745
1746         bool wifi_connect_change;
1747         bool bt_state_change;
1748         bool rssi_state_change;
1749
1750         if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1751              (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
1752
1753                 wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
1754                 bt_state_change = rtl92c_bt_state_change(hw);
1755                 rssi_state_change = rtl92c_bt_rssi_state_change(hw);
1756
1757                 if (wifi_connect_change || bt_state_change || rssi_state_change)
1758                         rtl92c_check_bt_change(hw);
1759         }
1760 }
1761 EXPORT_SYMBOL(rtl92c_dm_bt_coexist);