drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00pci.h"
  45 #include "rt2x00soc.h"
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800pci.h"
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static bool modparam_nohwcrypt = false;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
  58 {
  59         return modparam_nohwcrypt;
  60 }
  61
  62 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  63 {
  64         unsigned int i;
  65         u32 reg;
  66
  67         /*
  68          * SOC devices don't support MCU requests.
  69          */
  70         if (rt2x00_is_soc(rt2x00dev))
  71                 return;
  72
  73         for (i = 0; i < 200; i++) {
  74                 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  75
  76                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  77                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  78                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  79                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  80                         break;
  81
  82                 udelay(REGISTER_BUSY_DELAY);
  83         }
  84
  85         if (i == 200)
  86                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  87
  88         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  89         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  90 }
  91
  92 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  93 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  94 {
  95         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
  96
  97         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  98
  99         iounmap(base_addr);
 100 }
 101 #else
 102 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 103 {
 104 }
 105 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
 106
 107 #ifdef CONFIG_PCI
 108 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 109 {
 110         struct rt2x00_dev *rt2x00dev = eeprom->data;
 111         u32 reg;
 112
 113         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 114
 115         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 116         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 117         eeprom->reg_data_clock =
 118             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 119         eeprom->reg_chip_select =
 120             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 121 }
 122
 123 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 124 {
 125         struct rt2x00_dev *rt2x00dev = eeprom->data;
 126         u32 reg = 0;
 127
 128         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 129         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 130         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 131                            !!eeprom->reg_data_clock);
 132         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 133                            !!eeprom->reg_chip_select);
 134
 135         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 136 }
 137
 138 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 139 {
 140         struct eeprom_93cx6 eeprom;
 141         u32 reg;
 142
 143         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 144
 145         eeprom.data = rt2x00dev;
 146         eeprom.register_read = rt2800pci_eepromregister_read;
 147         eeprom.register_write = rt2800pci_eepromregister_write;
 148         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 149         {
 150         case 0:
 151                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 152                 break;
 153         case 1:
 154                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 155                 break;
 156         default:
 157                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 158                 break;
 159         }
 160         eeprom.reg_data_in = 0;
 161         eeprom.reg_data_out = 0;
 162         eeprom.reg_data_clock = 0;
 163         eeprom.reg_chip_select = 0;
 164
 165         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 166                                EEPROM_SIZE / sizeof(u16));
 167 }
 168
 169 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 170 {
 171         return rt2800_efuse_detect(rt2x00dev);
 172 }
 173
 174 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 175 {
 176         rt2800_read_eeprom_efuse(rt2x00dev);
 177 }
 178 #else
 179 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 180 {
 181 }
 182
 183 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 184 {
 185         return 0;
 186 }
 187
 188 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 189 {
 190 }
 191 #endif /* CONFIG_PCI */
 192
 193 /*
 194  * Queue handlers.
 195  */
 196 static void rt2800pci_start_queue(struct data_queue *queue)
 197 {
 198         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 199         u32 reg;
 200
 201         switch (queue->qid) {
 202         case QID_RX:
 203                 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 204                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 205                 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 206                 break;
 207         case QID_BEACON:
 208                 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 209                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 210                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 211                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 212                 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 213
 214                 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 215                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
 216                 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
 217                 break;
 218         default:
 219                 break;
 220         }
 221 }
 222
 223 static void rt2800pci_kick_queue(struct data_queue *queue)
 224 {
 225         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 226         struct queue_entry *entry;
 227
 228         switch (queue->qid) {
 229         case QID_AC_VO:
 230         case QID_AC_VI:
 231         case QID_AC_BE:
 232         case QID_AC_BK:
 233                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 234                 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
 235                                          entry->entry_idx);
 236                 break;
 237         case QID_MGMT:
 238                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 239                 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
 240                                          entry->entry_idx);
 241                 break;
 242         default:
 243                 break;
 244         }
 245 }
 246
 247 static void rt2800pci_stop_queue(struct data_queue *queue)
 248 {
 249         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 250         u32 reg;
 251
 252         switch (queue->qid) {
 253         case QID_RX:
 254                 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 255                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 256                 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 257                 break;
 258         case QID_BEACON:
 259                 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 260                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
 261                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
 262                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 263                 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 264
 265                 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 266                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
 267                 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
 268
 269                 /*
 270                  * Wait for current invocation to finish. The tasklet
 271                  * won't be scheduled anymore afterwards since we disabled
 272                  * the TBTT and PRE TBTT timer.
 273                  */
 274                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 275                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 276
 277                 break;
 278         default:
 279                 break;
 280         }
 281 }
 282
 283 /*
 284  * Firmware functions
 285  */
 286 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 287 {
 288         /*
 289          * Chip rt3290 use specific 4KB firmware named rt3290.bin.
 290          */
 291         if (rt2x00_rt(rt2x00dev, RT3290))
 292                 return FIRMWARE_RT3290;
 293         else
 294                 return FIRMWARE_RT2860;
 295 }
 296
 297 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 298                                     const u8 *data, const size_t len)
 299 {
 300         u32 reg;
 301
 302         /*
 303          * enable Host program ram write selection
 304          */
 305         reg = 0;
 306         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 307         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 308
 309         /*
 310          * Write firmware to device.
 311          */
 312         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 313                                       data, len);
 314
 315         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 316         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 317
 318         rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 319         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 320
 321         return 0;
 322 }
 323
 324 /*
 325  * Initialization functions.
 326  */
 327 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 328 {
 329         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 330         u32 word;
 331
 332         if (entry->queue->qid == QID_RX) {
 333                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 334
 335                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 336         } else {
 337                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 338
 339                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 340         }
 341 }
 342
 343 static void rt2800pci_clear_entry(struct queue_entry *entry)
 344 {
 345         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 346         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 347         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 348         u32 word;
 349
 350         if (entry->queue->qid == QID_RX) {
 351                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 352                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 353                 rt2x00_desc_write(entry_priv->desc, 0, word);
 354
 355                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 356                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 357                 rt2x00_desc_write(entry_priv->desc, 1, word);
 358
 359                 /*
 360                  * Set RX IDX in register to inform hardware that we have
 361                  * handled this entry and it is available for reuse again.
 362                  */
 363                 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
 364                                       entry->entry_idx);
 365         } else {
 366                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 367                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 368                 rt2x00_desc_write(entry_priv->desc, 1, word);
 369         }
 370 }
 371
 372 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 373 {
 374         struct queue_entry_priv_pci *entry_priv;
 375
 376         /*
 377          * Initialize registers.
 378          */
 379         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 380         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 381         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
 382                                  rt2x00dev->tx[0].limit);
 383         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 384         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 385
 386         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 387         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 388         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
 389                                  rt2x00dev->tx[1].limit);
 390         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 391         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 392
 393         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 394         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 395         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
 396                                  rt2x00dev->tx[2].limit);
 397         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 398         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 399
 400         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 401         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 402         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
 403                                  rt2x00dev->tx[3].limit);
 404         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 405         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 406
 407         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
 408         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
 409         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
 410         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
 411
 412         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
 413         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
 414         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
 415         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
 416
 417         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 418         rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 419         rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
 420                                  rt2x00dev->rx[0].limit);
 421         rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
 422                                  rt2x00dev->rx[0].limit - 1);
 423         rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
 424
 425         rt2800_disable_wpdma(rt2x00dev);
 426
 427         rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 428
 429         return 0;
 430 }
 431
 432 /*
 433  * Device state switch handlers.
 434  */
 435 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 436                                  enum dev_state state)
 437 {
 438         u32 reg;
 439         unsigned long flags;
 440
 441         /*
 442          * When interrupts are being enabled, the interrupt registers
 443          * should clear the register to assure a clean state.
 444          */
 445         if (state == STATE_RADIO_IRQ_ON) {
 446                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 447                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 448         }
 449
 450         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 451         reg = 0;
 452         if (state == STATE_RADIO_IRQ_ON) {
 453                 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
 454                 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
 455                 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
 456                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 457                 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
 458         }
 459         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 460         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 461
 462         if (state == STATE_RADIO_IRQ_OFF) {
 463                 /*
 464                  * Wait for possibly running tasklets to finish.
 465                  */
 466                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
 467                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
 468                 tasklet_kill(&rt2x00dev->autowake_tasklet);
 469                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 470                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 471         }
 472 }
 473
 474 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 475 {
 476         u32 reg;
 477
 478         /*
 479          * Reset DMA indexes
 480          */
 481         rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 482         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 483         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 484         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 485         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 486         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 487         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 488         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 489         rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 490
 491         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 492         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 493
 494         if (rt2x00_is_pcie(rt2x00dev) &&
 495             (rt2x00_rt(rt2x00dev, RT3572) ||
 496              rt2x00_rt(rt2x00dev, RT5390) ||
 497              rt2x00_rt(rt2x00dev, RT5392))) {
 498                 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
 499                 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 500                 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 501                 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
 502         }
 503
 504         rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 505
 506         reg = 0;
 507         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 508         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 509         rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 510
 511         rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 512
 513         return 0;
 514 }
 515
 516 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 517 {
 518         int retval;
 519
 520         /* Wait for DMA, ignore error until we initialize queues. */
 521         rt2800_wait_wpdma_ready(rt2x00dev);
 522
 523         if (unlikely(rt2800pci_init_queues(rt2x00dev)))
 524                 return -EIO;
 525
 526         retval = rt2800_enable_radio(rt2x00dev);
 527         if (retval)
 528                 return retval;
 529
 530         /* After resume MCU_BOOT_SIGNAL will trash these. */
 531         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
 532         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
 533
 534         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
 535         rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
 536
 537         rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
 538         rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
 539
 540         return retval;
 541 }
 542
 543 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 544 {
 545         if (rt2x00_is_soc(rt2x00dev)) {
 546                 rt2800_disable_radio(rt2x00dev);
 547                 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 548                 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
 549         }
 550 }
 551
 552 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 553                                enum dev_state state)
 554 {
 555         if (state == STATE_AWAKE) {
 556                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
 557                                    0, 0x02);
 558                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
 559         } else if (state == STATE_SLEEP) {
 560                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
 561                                          0xffffffff);
 562                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
 563                                          0xffffffff);
 564                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
 565                                    0xff, 0x01);
 566         }
 567
 568         return 0;
 569 }
 570
 571 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 572                                       enum dev_state state)
 573 {
 574         int retval = 0;
 575
 576         switch (state) {
 577         case STATE_RADIO_ON:
 578                 retval = rt2800pci_enable_radio(rt2x00dev);
 579                 break;
 580         case STATE_RADIO_OFF:
 581                 /*
 582                  * After the radio has been disabled, the device should
 583                  * be put to sleep for powersaving.
 584                  */
 585                 rt2800pci_disable_radio(rt2x00dev);
 586                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 587                 break;
 588         case STATE_RADIO_IRQ_ON:
 589         case STATE_RADIO_IRQ_OFF:
 590                 rt2800pci_toggle_irq(rt2x00dev, state);
 591                 break;
 592         case STATE_DEEP_SLEEP:
 593         case STATE_SLEEP:
 594         case STATE_STANDBY:
 595         case STATE_AWAKE:
 596                 retval = rt2800pci_set_state(rt2x00dev, state);
 597                 break;
 598         default:
 599                 retval = -ENOTSUPP;
 600                 break;
 601         }
 602
 603         if (unlikely(retval))
 604                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 605                       state, retval);
 606
 607         return retval;
 608 }
 609
 610 /*
 611  * TX descriptor initialization
 612  */
 613 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 614 {
 615         return (__le32 *) entry->skb->data;
 616 }
 617
 618 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 619                                     struct txentry_desc *txdesc)
 620 {
 621         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 622         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 623         __le32 *txd = entry_priv->desc;
 624         u32 word;
 625
 626         /*
 627          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 628          * must contains a TXWI structure + 802.11 header + padding + 802.11
 629          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 630          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 631          * data. It means that LAST_SEC0 is always 0.
 632          */
 633
 634         /*
 635          * Initialize TX descriptor
 636          */
 637         word = 0;
 638         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 639         rt2x00_desc_write(txd, 0, word);
 640
 641         word = 0;
 642         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
 643         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 644                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 645         rt2x00_set_field32(&word, TXD_W1_BURST,
 646                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 647         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 648         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 649         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 650         rt2x00_desc_write(txd, 1, word);
 651
 652         word = 0;
 653         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 654                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 655         rt2x00_desc_write(txd, 2, word);
 656
 657         word = 0;
 658         rt2x00_set_field32(&word, TXD_W3_WIV,
 659                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 660         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 661         rt2x00_desc_write(txd, 3, word);
 662
 663         /*
 664          * Register descriptor details in skb frame descriptor.
 665          */
 666         skbdesc->desc = txd;
 667         skbdesc->desc_len = TXD_DESC_SIZE;
 668 }
 669
 670 /*
 671  * RX control handlers
 672  */
 673 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 674                                   struct rxdone_entry_desc *rxdesc)
 675 {
 676         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 677         __le32 *rxd = entry_priv->desc;
 678         u32 word;
 679
 680         rt2x00_desc_read(rxd, 3, &word);
 681
 682         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 683                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 684
 685         /*
 686          * Unfortunately we don't know the cipher type used during
 687          * decryption. This prevents us from correct providing
 688          * correct statistics through debugfs.
 689          */
 690         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 691
 692         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 693                 /*
 694                  * Hardware has stripped IV/EIV data from 802.11 frame during
 695                  * decryption. Unfortunately the descriptor doesn't contain
 696                  * any fields with the EIV/IV data either, so they can't
 697                  * be restored by rt2x00lib.
 698                  */
 699                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 700
 701                 /*
 702                  * The hardware has already checked the Michael Mic and has
 703                  * stripped it from the frame. Signal this to mac80211.
 704                  */
 705                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
 706
 707                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 708                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 709                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 710                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 711         }
 712
 713         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 714                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 715
 716         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 717                 rxdesc->dev_flags |= RXDONE_L2PAD;
 718
 719         /*
 720          * Process the RXWI structure that is at the start of the buffer.
 721          */
 722         rt2800_process_rxwi(entry, rxdesc);
 723 }
 724
 725 /*
 726  * Interrupt functions.
 727  */
 728 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 729 {
 730         struct ieee80211_conf conf = { .flags = 0 };
 731         struct rt2x00lib_conf libconf = { .conf = &conf };
 732
 733         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 734 }
 735
 736 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 737 {
 738         struct data_queue *queue;
 739         struct queue_entry *entry;
 740         u32 status;
 741         u8 qid;
 742         int max_tx_done = 16;
 743
 744         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
 745                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
 746                 if (unlikely(qid >= QID_RX)) {
 747                         /*
 748                          * Unknown queue, this shouldn't happen. Just drop
 749                          * this tx status.
 750                          */
 751                         WARNING(rt2x00dev, "Got TX status report with "
 752                                            "unexpected pid %u, dropping\n", qid);
 753                         break;
 754                 }
 755
 756                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
 757                 if (unlikely(queue == NULL)) {
 758                         /*
 759                          * The queue is NULL, this shouldn't happen. Stop
 760                          * processing here and drop the tx status
 761                          */
 762                         WARNING(rt2x00dev, "Got TX status for an unavailable "
 763                                            "queue %u, dropping\n", qid);
 764                         break;
 765                 }
 766
 767                 if (unlikely(rt2x00queue_empty(queue))) {
 768                         /*
 769                          * The queue is empty. Stop processing here
 770                          * and drop the tx status.
 771                          */
 772                         WARNING(rt2x00dev, "Got TX status for an empty "
 773                                            "queue %u, dropping\n", qid);
 774                         break;
 775                 }
 776
 777                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 778                 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
 779
 780                 if (--max_tx_done == 0)
 781                         break;
 782         }
 783
 784         return !max_tx_done;
 785 }
 786
 787 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
 788                                               struct rt2x00_field32 irq_field)
 789 {
 790         u32 reg;
 791
 792         /*
 793          * Enable a single interrupt. The interrupt mask register
 794          * access needs locking.
 795          */
 796         spin_lock_irq(&rt2x00dev->irqmask_lock);
 797         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 798         rt2x00_set_field32(&reg, irq_field, 1);
 799         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 800         spin_unlock_irq(&rt2x00dev->irqmask_lock);
 801 }
 802
 803 static void rt2800pci_txstatus_tasklet(unsigned long data)
 804 {
 805         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 806         if (rt2800pci_txdone(rt2x00dev))
 807                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 808
 809         /*
 810          * No need to enable the tx status interrupt here as we always
 811          * leave it enabled to minimize the possibility of a tx status
 812          * register overflow. See comment in interrupt handler.
 813          */
 814 }
 815
 816 static void rt2800pci_pretbtt_tasklet(unsigned long data)
 817 {
 818         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 819         rt2x00lib_pretbtt(rt2x00dev);
 820         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 821                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
 822 }
 823
 824 static void rt2800pci_tbtt_tasklet(unsigned long data)
 825 {
 826         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 827         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 828         u32 reg;
 829
 830         rt2x00lib_beacondone(rt2x00dev);
 831
 832         if (rt2x00dev->intf_ap_count) {
 833                 /*
 834                  * The rt2800pci hardware tbtt timer is off by 1us per tbtt
 835                  * causing beacon skew and as a result causing problems with
 836                  * some powersaving clients over time. Shorten the beacon
 837                  * interval every 64 beacons by 64us to mitigate this effect.
 838                  */
 839                 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
 840                         rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 841                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 842                                            (rt2x00dev->beacon_int * 16) - 1);
 843                         rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 844                 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
 845                         rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 846                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 847                                            (rt2x00dev->beacon_int * 16));
 848                         rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 849                 }
 850                 drv_data->tbtt_tick++;
 851                 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
 852         }
 853
 854         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 855                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
 856 }
 857
 858 static void rt2800pci_rxdone_tasklet(unsigned long data)
 859 {
 860         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 861         if (rt2x00pci_rxdone(rt2x00dev))
 862                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 863         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 864                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
 865 }
 866
 867 static void rt2800pci_autowake_tasklet(unsigned long data)
 868 {
 869         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 870         rt2800pci_wakeup(rt2x00dev);
 871         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 872                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
 873 }
 874
 875 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
 876 {
 877         u32 status;
 878         int i;
 879
 880         /*
 881          * The TX_FIFO_STATUS interrupt needs special care. We should
 882          * read TX_STA_FIFO but we should do it immediately as otherwise
 883          * the register can overflow and we would lose status reports.
 884          *
 885          * Hence, read the TX_STA_FIFO register and copy all tx status
 886          * reports into a kernel FIFO which is handled in the txstatus
 887          * tasklet. We use a tasklet to process the tx status reports
 888          * because we can schedule the tasklet multiple times (when the
 889          * interrupt fires again during tx status processing).
 890          *
 891          * Furthermore we don't disable the TX_FIFO_STATUS
 892          * interrupt here but leave it enabled so that the TX_STA_FIFO
 893          * can also be read while the tx status tasklet gets executed.
 894          *
 895          * Since we have only one producer and one consumer we don't
 896          * need to lock the kfifo.
 897          */
 898         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 899                 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
 900
 901                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
 902                         break;
 903
 904                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
 905                         WARNING(rt2x00dev, "TX status FIFO overrun,"
 906                                 "drop tx status report.\n");
 907                         break;
 908                 }
 909         }
 910
 911         /* Schedule the tasklet for processing the tx status. */
 912         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 913 }
 914
 915 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 916 {
 917         struct rt2x00_dev *rt2x00dev = dev_instance;
 918         u32 reg, mask;
 919
 920         /* Read status and ACK all interrupts */
 921         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 922         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 923
 924         if (!reg)
 925                 return IRQ_NONE;
 926
 927         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 928                 return IRQ_HANDLED;
 929
 930         /*
 931          * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
 932          * for interrupts and interrupt masks we can just use the value of
 933          * INT_SOURCE_CSR to create the interrupt mask.
 934          */
 935         mask = ~reg;
 936
 937         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
 938                 rt2800pci_txstatus_interrupt(rt2x00dev);
 939                 /*
 940                  * Never disable the TX_FIFO_STATUS interrupt.
 941                  */
 942                 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 943         }
 944
 945         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 946                 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
 947
 948         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 949                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
 950
 951         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 952                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 953
 954         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 955                 tasklet_schedule(&rt2x00dev->autowake_tasklet);
 956
 957         /*
 958          * Disable all interrupts for which a tasklet was scheduled right now,
 959          * the tasklet will reenable the appropriate interrupts.
 960          */
 961         spin_lock(&rt2x00dev->irqmask_lock);
 962         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 963         reg &= mask;
 964         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 965         spin_unlock(&rt2x00dev->irqmask_lock);
 966
 967         return IRQ_HANDLED;
 968 }
 969
 970 /*
 971  * Device probe functions.
 972  */
 973 static void rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
 974 {
 975         if (rt2x00_is_soc(rt2x00dev))
 976                 rt2800pci_read_eeprom_soc(rt2x00dev);
 977         else if (rt2800pci_efuse_detect(rt2x00dev))
 978                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 979         else
 980                 rt2800pci_read_eeprom_pci(rt2x00dev);
 981 }
 982
 983 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
 984         .tx                     = rt2x00mac_tx,
 985         .start                  = rt2x00mac_start,
 986         .stop                   = rt2x00mac_stop,
 987         .add_interface          = rt2x00mac_add_interface,
 988         .remove_interface       = rt2x00mac_remove_interface,
 989         .config                 = rt2x00mac_config,
 990         .configure_filter       = rt2x00mac_configure_filter,
 991         .set_key                = rt2x00mac_set_key,
 992         .sw_scan_start          = rt2x00mac_sw_scan_start,
 993         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
 994         .get_stats              = rt2x00mac_get_stats,
 995         .get_tkip_seq           = rt2800_get_tkip_seq,
 996         .set_rts_threshold      = rt2800_set_rts_threshold,
 997         .sta_add                = rt2x00mac_sta_add,
 998         .sta_remove             = rt2x00mac_sta_remove,
 999         .bss_info_changed       = rt2x00mac_bss_info_changed,
1000         .conf_tx                = rt2800_conf_tx,
1001         .get_tsf                = rt2800_get_tsf,
1002         .rfkill_poll            = rt2x00mac_rfkill_poll,
1003         .ampdu_action           = rt2800_ampdu_action,
1004         .flush                  = rt2x00mac_flush,
1005         .get_survey             = rt2800_get_survey,
1006         .get_ringparam          = rt2x00mac_get_ringparam,
1007         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
1008 };
1009
1010 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1011         .register_read          = rt2x00pci_register_read,
1012         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1013         .register_write         = rt2x00pci_register_write,
1014         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1015         .register_multiread     = rt2x00pci_register_multiread,
1016         .register_multiwrite    = rt2x00pci_register_multiwrite,
1017         .regbusy_read           = rt2x00pci_regbusy_read,
1018         .read_eeprom            = rt2800pci_read_eeprom,
1019         .hwcrypt_disabled       = rt2800pci_hwcrypt_disabled,
1020         .drv_write_firmware     = rt2800pci_write_firmware,
1021         .drv_init_registers     = rt2800pci_init_registers,
1022         .drv_get_txwi           = rt2800pci_get_txwi,
1023 };
1024
1025 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1026         .irq_handler            = rt2800pci_interrupt,
1027         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
1028         .pretbtt_tasklet        = rt2800pci_pretbtt_tasklet,
1029         .tbtt_tasklet           = rt2800pci_tbtt_tasklet,
1030         .rxdone_tasklet         = rt2800pci_rxdone_tasklet,
1031         .autowake_tasklet       = rt2800pci_autowake_tasklet,
1032         .probe_hw               = rt2800_probe_hw,
1033         .get_firmware_name      = rt2800pci_get_firmware_name,
1034         .check_firmware         = rt2800_check_firmware,
1035         .load_firmware          = rt2800_load_firmware,
1036         .initialize             = rt2x00pci_initialize,
1037         .uninitialize           = rt2x00pci_uninitialize,
1038         .get_entry_state        = rt2800pci_get_entry_state,
1039         .clear_entry            = rt2800pci_clear_entry,
1040         .set_device_state       = rt2800pci_set_device_state,
1041         .rfkill_poll            = rt2800_rfkill_poll,
1042         .link_stats             = rt2800_link_stats,
1043         .reset_tuner            = rt2800_reset_tuner,
1044         .link_tuner             = rt2800_link_tuner,
1045         .gain_calibration       = rt2800_gain_calibration,
1046         .vco_calibration        = rt2800_vco_calibration,
1047         .start_queue            = rt2800pci_start_queue,
1048         .kick_queue             = rt2800pci_kick_queue,
1049         .stop_queue             = rt2800pci_stop_queue,
1050         .flush_queue            = rt2x00pci_flush_queue,
1051         .write_tx_desc          = rt2800pci_write_tx_desc,
1052         .write_tx_data          = rt2800_write_tx_data,
1053         .write_beacon           = rt2800_write_beacon,
1054         .clear_beacon           = rt2800_clear_beacon,
1055         .fill_rxdone            = rt2800pci_fill_rxdone,
1056         .config_shared_key      = rt2800_config_shared_key,
1057         .config_pairwise_key    = rt2800_config_pairwise_key,
1058         .config_filter          = rt2800_config_filter,
1059         .config_intf            = rt2800_config_intf,
1060         .config_erp             = rt2800_config_erp,
1061         .config_ant             = rt2800_config_ant,
1062         .config                 = rt2800_config,
1063         .sta_add                = rt2800_sta_add,
1064         .sta_remove             = rt2800_sta_remove,
1065 };
1066
1067 static const struct data_queue_desc rt2800pci_queue_rx = {
1068         .entry_num              = 128,
1069         .data_size              = AGGREGATION_SIZE,
1070         .desc_size              = RXD_DESC_SIZE,
1071         .priv_size              = sizeof(struct queue_entry_priv_pci),
1072 };
1073
1074 static const struct data_queue_desc rt2800pci_queue_tx = {
1075         .entry_num              = 64,
1076         .data_size              = AGGREGATION_SIZE,
1077         .desc_size              = TXD_DESC_SIZE,
1078         .priv_size              = sizeof(struct queue_entry_priv_pci),
1079 };
1080
1081 static const struct data_queue_desc rt2800pci_queue_bcn = {
1082         .entry_num              = 8,
1083         .data_size              = 0, /* No DMA required for beacons */
1084         .desc_size              = TXWI_DESC_SIZE,
1085         .priv_size              = sizeof(struct queue_entry_priv_pci),
1086 };
1087
1088 static const struct rt2x00_ops rt2800pci_ops = {
1089         .name                   = KBUILD_MODNAME,
1090         .drv_data_size          = sizeof(struct rt2800_drv_data),
1091         .max_ap_intf            = 8,
1092         .eeprom_size            = EEPROM_SIZE,
1093         .rf_size                = RF_SIZE,
1094         .tx_queues              = NUM_TX_QUEUES,
1095         .extra_tx_headroom      = TXWI_DESC_SIZE,
1096         .rx                     = &rt2800pci_queue_rx,
1097         .tx                     = &rt2800pci_queue_tx,
1098         .bcn                    = &rt2800pci_queue_bcn,
1099         .lib                    = &rt2800pci_rt2x00_ops,
1100         .drv                    = &rt2800pci_rt2800_ops,
1101         .hw                     = &rt2800pci_mac80211_ops,
1102 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1103         .debugfs                = &rt2800_rt2x00debug,
1104 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1105 };
1106
1107 /*
1108  * RT2800pci module information.
1109  */
1110 #ifdef CONFIG_PCI
1111 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1112         { PCI_DEVICE(0x1814, 0x0601) },
1113         { PCI_DEVICE(0x1814, 0x0681) },
1114         { PCI_DEVICE(0x1814, 0x0701) },
1115         { PCI_DEVICE(0x1814, 0x0781) },
1116         { PCI_DEVICE(0x1814, 0x3090) },
1117         { PCI_DEVICE(0x1814, 0x3091) },
1118         { PCI_DEVICE(0x1814, 0x3092) },
1119         { PCI_DEVICE(0x1432, 0x7708) },
1120         { PCI_DEVICE(0x1432, 0x7727) },
1121         { PCI_DEVICE(0x1432, 0x7728) },
1122         { PCI_DEVICE(0x1432, 0x7738) },
1123         { PCI_DEVICE(0x1432, 0x7748) },
1124         { PCI_DEVICE(0x1432, 0x7758) },
1125         { PCI_DEVICE(0x1432, 0x7768) },
1126         { PCI_DEVICE(0x1462, 0x891a) },
1127         { PCI_DEVICE(0x1a3b, 0x1059) },
1128 #ifdef CONFIG_RT2800PCI_RT3290
1129         { PCI_DEVICE(0x1814, 0x3290) },
1130 #endif
1131 #ifdef CONFIG_RT2800PCI_RT33XX
1132         { PCI_DEVICE(0x1814, 0x3390) },
1133 #endif
1134 #ifdef CONFIG_RT2800PCI_RT35XX
1135         { PCI_DEVICE(0x1432, 0x7711) },
1136         { PCI_DEVICE(0x1432, 0x7722) },
1137         { PCI_DEVICE(0x1814, 0x3060) },
1138         { PCI_DEVICE(0x1814, 0x3062) },
1139         { PCI_DEVICE(0x1814, 0x3562) },
1140         { PCI_DEVICE(0x1814, 0x3592) },
1141         { PCI_DEVICE(0x1814, 0x3593) },
1142 #endif
1143 #ifdef CONFIG_RT2800PCI_RT53XX
1144         { PCI_DEVICE(0x1814, 0x5360) },
1145         { PCI_DEVICE(0x1814, 0x5362) },
1146         { PCI_DEVICE(0x1814, 0x5390) },
1147         { PCI_DEVICE(0x1814, 0x5392) },
1148         { PCI_DEVICE(0x1814, 0x539a) },
1149         { PCI_DEVICE(0x1814, 0x539b) },
1150         { PCI_DEVICE(0x1814, 0x539f) },
1151 #endif
1152         { 0, }
1153 };
1154 #endif /* CONFIG_PCI */
1155
1156 MODULE_AUTHOR(DRV_PROJECT);
1157 MODULE_VERSION(DRV_VERSION);
1158 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1159 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1160 #ifdef CONFIG_PCI
1161 MODULE_FIRMWARE(FIRMWARE_RT2860);
1162 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1163 #endif /* CONFIG_PCI */
1164 MODULE_LICENSE("GPL");
1165
1166 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1167 static int rt2800soc_probe(struct platform_device *pdev)
1168 {
1169         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1170 }
1171
1172 static struct platform_driver rt2800soc_driver = {
1173         .driver         = {
1174                 .name           = "rt2800_wmac",
1175                 .owner          = THIS_MODULE,
1176                 .mod_name       = KBUILD_MODNAME,
1177         },
1178         .probe          = rt2800soc_probe,
1179         .remove         = rt2x00soc_remove,
1180         .suspend        = rt2x00soc_suspend,
1181         .resume         = rt2x00soc_resume,
1182 };
1183 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1184
1185 #ifdef CONFIG_PCI
1186 static int rt2800pci_probe(struct pci_dev *pci_dev,
1187                            const struct pci_device_id *id)
1188 {
1189         return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1190 }
1191
1192 static struct pci_driver rt2800pci_driver = {
1193         .name           = KBUILD_MODNAME,
1194         .id_table       = rt2800pci_device_table,
1195         .probe          = rt2800pci_probe,
1196         .remove         = rt2x00pci_remove,
1197         .suspend        = rt2x00pci_suspend,
1198         .resume         = rt2x00pci_resume,
1199 };
1200 #endif /* CONFIG_PCI */
1201
1202 static int __init rt2800pci_init(void)
1203 {
1204         int ret = 0;
1205
1206 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1207         ret = platform_driver_register(&rt2800soc_driver);
1208         if (ret)
1209                 return ret;
1210 #endif
1211 #ifdef CONFIG_PCI
1212         ret = pci_register_driver(&rt2800pci_driver);
1213         if (ret) {
1214 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1215                 platform_driver_unregister(&rt2800soc_driver);
1216 #endif
1217                 return ret;
1218         }
1219 #endif
1220
1221         return ret;
1222 }
1223
1224 static void __exit rt2800pci_exit(void)
1225 {
1226 #ifdef CONFIG_PCI
1227         pci_unregister_driver(&rt2800pci_driver);
1228 #endif
1229 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1230         platform_driver_unregister(&rt2800soc_driver);
1231 #endif
1232 }
1233
1234 module_init(rt2800pci_init);
1235 module_exit(rt2800pci_exit);