drivers/net/ethernet/nvidia/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42
  43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  44
  45 #define FORCEDETH_VERSION               "0.64"
  46 #define DRV_NAME                        "forcedeth"
  47
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/pci.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/etherdevice.h>
  54 #include <linux/delay.h>
  55 #include <linux/sched.h>
  56 #include <linux/spinlock.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/timer.h>
  59 #include <linux/skbuff.h>
  60 #include <linux/mii.h>
  61 #include <linux/random.h>
  62 #include <linux/init.h>
  63 #include <linux/if_vlan.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/slab.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/prefetch.h>
  68 #include <linux/u64_stats_sync.h>
  69 #include <linux/io.h>
  70
  71 #include <asm/irq.h>
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  93 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  94 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  95 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  96 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  97 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  98 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  99 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 100 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 101 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 102 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 103 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 104 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 105 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 106 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 107
 108 enum {
 109         NvRegIrqStatus = 0x000,
 110 #define NVREG_IRQSTAT_MIIEVENT  0x040
 111 #define NVREG_IRQSTAT_MASK              0x83ff
 112         NvRegIrqMask = 0x004,
 113 #define NVREG_IRQ_RX_ERROR              0x0001
 114 #define NVREG_IRQ_RX                    0x0002
 115 #define NVREG_IRQ_RX_NOBUF              0x0004
 116 #define NVREG_IRQ_TX_ERR                0x0008
 117 #define NVREG_IRQ_TX_OK                 0x0010
 118 #define NVREG_IRQ_TIMER                 0x0020
 119 #define NVREG_IRQ_LINK                  0x0040
 120 #define NVREG_IRQ_RX_FORCED             0x0080
 121 #define NVREG_IRQ_TX_FORCED             0x0100
 122 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 123 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 124 #define NVREG_IRQMASK_CPU               0x0060
 125 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 126 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 127 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 128
 129         NvRegUnknownSetupReg6 = 0x008,
 130 #define NVREG_UNKSETUP6_VAL             3
 131
 132 /*
 133  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 134  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 135  */
 136         NvRegPollingInterval = 0x00c,
 137 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 138 #define NVREG_POLL_DEFAULT_CPU  13
 139         NvRegMSIMap0 = 0x020,
 140         NvRegMSIMap1 = 0x024,
 141         NvRegMSIIrqMask = 0x030,
 142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 143         NvRegMisc1 = 0x080,
 144 #define NVREG_MISC1_PAUSE_TX    0x01
 145 #define NVREG_MISC1_HD          0x02
 146 #define NVREG_MISC1_FORCE       0x3b0f3c
 147
 148         NvRegMacReset = 0x34,
 149 #define NVREG_MAC_RESET_ASSERT  0x0F3
 150         NvRegTransmitterControl = 0x084,
 151 #define NVREG_XMITCTL_START     0x01
 152 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 153 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 154 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 155 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 156 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 157 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 158 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 159 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 160 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 161 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 162 #define NVREG_XMITCTL_DATA_START        0x00100000
 163 #define NVREG_XMITCTL_DATA_READY        0x00010000
 164 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 165         NvRegTransmitterStatus = 0x088,
 166 #define NVREG_XMITSTAT_BUSY     0x01
 167
 168         NvRegPacketFilterFlags = 0x8c,
 169 #define NVREG_PFF_PAUSE_RX      0x08
 170 #define NVREG_PFF_ALWAYS        0x7F0000
 171 #define NVREG_PFF_PROMISC       0x80
 172 #define NVREG_PFF_MYADDR        0x20
 173 #define NVREG_PFF_LOOPBACK      0x10
 174
 175         NvRegOffloadConfig = 0x90,
 176 #define NVREG_OFFLOAD_HOMEPHY   0x601
 177 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 178         NvRegReceiverControl = 0x094,
 179 #define NVREG_RCVCTL_START      0x01
 180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 181         NvRegReceiverStatus = 0x98,
 182 #define NVREG_RCVSTAT_BUSY      0x01
 183
 184         NvRegSlotTime = 0x9c,
 185 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 186 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 187 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 188 #define NVREG_SLOTTIME_HALF             0x0000ff00
 189 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 190 #define NVREG_SLOTTIME_MASK             0x000000ff
 191
 192         NvRegTxDeferral = 0xA0,
 193 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 194 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 195 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 198 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 199         NvRegRxDeferral = 0xA4,
 200 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 201         NvRegMacAddrA = 0xA8,
 202         NvRegMacAddrB = 0xAC,
 203         NvRegMulticastAddrA = 0xB0,
 204 #define NVREG_MCASTADDRA_FORCE  0x01
 205         NvRegMulticastAddrB = 0xB4,
 206         NvRegMulticastMaskA = 0xB8,
 207 #define NVREG_MCASTMASKA_NONE           0xffffffff
 208         NvRegMulticastMaskB = 0xBC,
 209 #define NVREG_MCASTMASKB_NONE           0xffff
 210
 211         NvRegPhyInterface = 0xC0,
 212 #define PHY_RGMII               0x10000000
 213         NvRegBackOffControl = 0xC4,
 214 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 215 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 216 #define NVREG_BKOFFCTRL_SELECT                  24
 217 #define NVREG_BKOFFCTRL_GEAR                    12
 218
 219         NvRegTxRingPhysAddr = 0x100,
 220         NvRegRxRingPhysAddr = 0x104,
 221         NvRegRingSizes = 0x108,
 222 #define NVREG_RINGSZ_TXSHIFT 0
 223 #define NVREG_RINGSZ_RXSHIFT 16
 224         NvRegTransmitPoll = 0x10c,
 225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 226         NvRegLinkSpeed = 0x110,
 227 #define NVREG_LINKSPEED_FORCE 0x10000
 228 #define NVREG_LINKSPEED_10      1000
 229 #define NVREG_LINKSPEED_100     100
 230 #define NVREG_LINKSPEED_1000    50
 231 #define NVREG_LINKSPEED_MASK    (0xFFF)
 232         NvRegUnknownSetupReg5 = 0x130,
 233 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 234         NvRegTxWatermark = 0x13c,
 235 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 236 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 237 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 238         NvRegTxRxControl = 0x144,
 239 #define NVREG_TXRXCTL_KICK      0x0001
 240 #define NVREG_TXRXCTL_BIT1      0x0002
 241 #define NVREG_TXRXCTL_BIT2      0x0004
 242 #define NVREG_TXRXCTL_IDLE      0x0008
 243 #define NVREG_TXRXCTL_RESET     0x0010
 244 #define NVREG_TXRXCTL_RXCHECK   0x0400
 245 #define NVREG_TXRXCTL_DESC_1    0
 246 #define NVREG_TXRXCTL_DESC_2    0x002100
 247 #define NVREG_TXRXCTL_DESC_3    0xc02200
 248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 249 #define NVREG_TXRXCTL_VLANINS   0x00080
 250         NvRegTxRingPhysAddrHigh = 0x148,
 251         NvRegRxRingPhysAddrHigh = 0x14C,
 252         NvRegTxPauseFrame = 0x170,
 253 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 257         NvRegTxPauseFrameLimit = 0x174,
 258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 259         NvRegMIIStatus = 0x180,
 260 #define NVREG_MIISTAT_ERROR             0x0001
 261 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 262 #define NVREG_MIISTAT_MASK_RW           0x0007
 263 #define NVREG_MIISTAT_MASK_ALL          0x000f
 264         NvRegMIIMask = 0x184,
 265 #define NVREG_MII_LINKCHANGE            0x0008
 266
 267         NvRegAdapterControl = 0x188,
 268 #define NVREG_ADAPTCTL_START    0x02
 269 #define NVREG_ADAPTCTL_LINKUP   0x04
 270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 271 #define NVREG_ADAPTCTL_RUNNING  0x100000
 272 #define NVREG_ADAPTCTL_PHYSHIFT 24
 273         NvRegMIISpeed = 0x18c,
 274 #define NVREG_MIISPEED_BIT8     (1<<8)
 275 #define NVREG_MIIDELAY  5
 276         NvRegMIIControl = 0x190,
 277 #define NVREG_MIICTL_INUSE      0x08000
 278 #define NVREG_MIICTL_WRITE      0x00400
 279 #define NVREG_MIICTL_ADDRSHIFT  5
 280         NvRegMIIData = 0x194,
 281         NvRegTxUnicast = 0x1a0,
 282         NvRegTxMulticast = 0x1a4,
 283         NvRegTxBroadcast = 0x1a8,
 284         NvRegWakeUpFlags = 0x200,
 285 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 288 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 289 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 290 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 291 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 295 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 296
 297         NvRegMgmtUnitGetVersion = 0x204,
 298 #define NVREG_MGMTUNITGETVERSION        0x01
 299         NvRegMgmtUnitVersion = 0x208,
 300 #define NVREG_MGMTUNITVERSION           0x08
 301         NvRegPowerCap = 0x268,
 302 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 303 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 304 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 305         NvRegPowerState = 0x26c,
 306 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 307 #define NVREG_POWERSTATE_VALID          0x0100
 308 #define NVREG_POWERSTATE_MASK           0x0003
 309 #define NVREG_POWERSTATE_D0             0x0000
 310 #define NVREG_POWERSTATE_D1             0x0001
 311 #define NVREG_POWERSTATE_D2             0x0002
 312 #define NVREG_POWERSTATE_D3             0x0003
 313         NvRegMgmtUnitControl = 0x278,
 314 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 315         NvRegTxCnt = 0x280,
 316         NvRegTxZeroReXmt = 0x284,
 317         NvRegTxOneReXmt = 0x288,
 318         NvRegTxManyReXmt = 0x28c,
 319         NvRegTxLateCol = 0x290,
 320         NvRegTxUnderflow = 0x294,
 321         NvRegTxLossCarrier = 0x298,
 322         NvRegTxExcessDef = 0x29c,
 323         NvRegTxRetryErr = 0x2a0,
 324         NvRegRxFrameErr = 0x2a4,
 325         NvRegRxExtraByte = 0x2a8,
 326         NvRegRxLateCol = 0x2ac,
 327         NvRegRxRunt = 0x2b0,
 328         NvRegRxFrameTooLong = 0x2b4,
 329         NvRegRxOverflow = 0x2b8,
 330         NvRegRxFCSErr = 0x2bc,
 331         NvRegRxFrameAlignErr = 0x2c0,
 332         NvRegRxLenErr = 0x2c4,
 333         NvRegRxUnicast = 0x2c8,
 334         NvRegRxMulticast = 0x2cc,
 335         NvRegRxBroadcast = 0x2d0,
 336         NvRegTxDef = 0x2d4,
 337         NvRegTxFrame = 0x2d8,
 338         NvRegRxCnt = 0x2dc,
 339         NvRegTxPause = 0x2e0,
 340         NvRegRxPause = 0x2e4,
 341         NvRegRxDropFrame = 0x2e8,
 342         NvRegVlanControl = 0x300,
 343 #define NVREG_VLANCONTROL_ENABLE        0x2000
 344         NvRegMSIXMap0 = 0x3e0,
 345         NvRegMSIXMap1 = 0x3e4,
 346         NvRegMSIXIrqStatus = 0x3f0,
 347
 348         NvRegPowerState2 = 0x600,
 349 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 350 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 351 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 352 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 353 };
 354
 355 /* Big endian: should work, but is untested */
 356 struct ring_desc {
 357         __le32 buf;
 358         __le32 flaglen;
 359 };
 360
 361 struct ring_desc_ex {
 362         __le32 bufhigh;
 363         __le32 buflow;
 364         __le32 txvlan;
 365         __le32 flaglen;
 366 };
 367
 368 union ring_type {
 369         struct ring_desc *orig;
 370         struct ring_desc_ex *ex;
 371 };
 372
 373 #define FLAG_MASK_V1 0xffff0000
 374 #define FLAG_MASK_V2 0xffffc000
 375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 377
 378 #define NV_TX_LASTPACKET        (1<<16)
 379 #define NV_TX_RETRYERROR        (1<<19)
 380 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 381 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 382 #define NV_TX_DEFERRED          (1<<26)
 383 #define NV_TX_CARRIERLOST       (1<<27)
 384 #define NV_TX_LATECOLLISION     (1<<28)
 385 #define NV_TX_UNDERFLOW         (1<<29)
 386 #define NV_TX_ERROR             (1<<30)
 387 #define NV_TX_VALID             (1<<31)
 388
 389 #define NV_TX2_LASTPACKET       (1<<29)
 390 #define NV_TX2_RETRYERROR       (1<<18)
 391 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 393 #define NV_TX2_DEFERRED         (1<<25)
 394 #define NV_TX2_CARRIERLOST      (1<<26)
 395 #define NV_TX2_LATECOLLISION    (1<<27)
 396 #define NV_TX2_UNDERFLOW        (1<<28)
 397 /* error and valid are the same for both */
 398 #define NV_TX2_ERROR            (1<<30)
 399 #define NV_TX2_VALID            (1<<31)
 400 #define NV_TX2_TSO              (1<<28)
 401 #define NV_TX2_TSO_SHIFT        14
 402 #define NV_TX2_TSO_MAX_SHIFT    14
 403 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 404 #define NV_TX2_CHECKSUM_L3      (1<<27)
 405 #define NV_TX2_CHECKSUM_L4      (1<<26)
 406
 407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 408
 409 #define NV_RX_DESCRIPTORVALID   (1<<16)
 410 #define NV_RX_MISSEDFRAME       (1<<17)
 411 #define NV_RX_SUBSTRACT1        (1<<18)
 412 #define NV_RX_ERROR1            (1<<23)
 413 #define NV_RX_ERROR2            (1<<24)
 414 #define NV_RX_ERROR3            (1<<25)
 415 #define NV_RX_ERROR4            (1<<26)
 416 #define NV_RX_CRCERR            (1<<27)
 417 #define NV_RX_OVERFLOW          (1<<28)
 418 #define NV_RX_FRAMINGERR        (1<<29)
 419 #define NV_RX_ERROR             (1<<30)
 420 #define NV_RX_AVAIL             (1<<31)
 421 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 422
 423 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 424 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 425 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 426 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 427 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 428 #define NV_RX2_SUBSTRACT1       (1<<25)
 429 #define NV_RX2_ERROR1           (1<<18)
 430 #define NV_RX2_ERROR2           (1<<19)
 431 #define NV_RX2_ERROR3           (1<<20)
 432 #define NV_RX2_ERROR4           (1<<21)
 433 #define NV_RX2_CRCERR           (1<<22)
 434 #define NV_RX2_OVERFLOW         (1<<23)
 435 #define NV_RX2_FRAMINGERR       (1<<24)
 436 /* error and avail are the same for both */
 437 #define NV_RX2_ERROR            (1<<30)
 438 #define NV_RX2_AVAIL            (1<<31)
 439 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 440
 441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 442 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 443
 444 /* Miscellaneous hardware related defines: */
 445 #define NV_PCI_REGSZ_VER1       0x270
 446 #define NV_PCI_REGSZ_VER2       0x2d4
 447 #define NV_PCI_REGSZ_VER3       0x604
 448 #define NV_PCI_REGSZ_MAX        0x604
 449
 450 /* various timeout delays: all in usec */
 451 #define NV_TXRX_RESET_DELAY     4
 452 #define NV_TXSTOP_DELAY1        10
 453 #define NV_TXSTOP_DELAY1MAX     500000
 454 #define NV_TXSTOP_DELAY2        100
 455 #define NV_RXSTOP_DELAY1        10
 456 #define NV_RXSTOP_DELAY1MAX     500000
 457 #define NV_RXSTOP_DELAY2        100
 458 #define NV_SETUP5_DELAY         5
 459 #define NV_SETUP5_DELAYMAX      50000
 460 #define NV_POWERUP_DELAY        5
 461 #define NV_POWERUP_DELAYMAX     5000
 462 #define NV_MIIBUSY_DELAY        50
 463 #define NV_MIIPHY_DELAY 10
 464 #define NV_MIIPHY_DELAYMAX      10000
 465 #define NV_MAC_RESET_DELAY      64
 466
 467 #define NV_WAKEUPPATTERNS       5
 468 #define NV_WAKEUPMASKENTRIES    4
 469
 470 /* General driver defaults */
 471 #define NV_WATCHDOG_TIMEO       (5*HZ)
 472
 473 #define RX_RING_DEFAULT         512
 474 #define TX_RING_DEFAULT         256
 475 #define RX_RING_MIN             128
 476 #define TX_RING_MIN             64
 477 #define RING_MAX_DESC_VER_1     1024
 478 #define RING_MAX_DESC_VER_2_3   16384
 479
 480 /* rx/tx mac addr + type + vlan + align + slack*/
 481 #define NV_RX_HEADERS           (64)
 482 /* even more slack. */
 483 #define NV_RX_ALLOC_PAD         (64)
 484
 485 /* maximum mtu size */
 486 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 487 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 488
 489 #define OOM_REFILL      (1+HZ/20)
 490 #define POLL_WAIT       (1+HZ/100)
 491 #define LINK_TIMEOUT    (3*HZ)
 492 #define STATS_INTERVAL  (10*HZ)
 493
 494 /*
 495  * desc_ver values:
 496  * The nic supports three different descriptor types:
 497  * - DESC_VER_1: Original
 498  * - DESC_VER_2: support for jumbo frames.
 499  * - DESC_VER_3: 64-bit format.
 500  */
 501 #define DESC_VER_1      1
 502 #define DESC_VER_2      2
 503 #define DESC_VER_3      3
 504
 505 /* PHY defines */
 506 #define PHY_OUI_MARVELL         0x5043
 507 #define PHY_OUI_CICADA          0x03f1
 508 #define PHY_OUI_VITESSE         0x01c1
 509 #define PHY_OUI_REALTEK         0x0732
 510 #define PHY_OUI_REALTEK2        0x0020
 511 #define PHYID1_OUI_MASK 0x03ff
 512 #define PHYID1_OUI_SHFT 6
 513 #define PHYID2_OUI_MASK 0xfc00
 514 #define PHYID2_OUI_SHFT 10
 515 #define PHYID2_MODEL_MASK               0x03f0
 516 #define PHY_MODEL_REALTEK_8211          0x0110
 517 #define PHY_REV_MASK                    0x0001
 518 #define PHY_REV_REALTEK_8211B           0x0000
 519 #define PHY_REV_REALTEK_8211C           0x0001
 520 #define PHY_MODEL_REALTEK_8201          0x0200
 521 #define PHY_MODEL_MARVELL_E3016         0x0220
 522 #define PHY_MARVELL_E3016_INITMASK      0x0300
 523 #define PHY_CICADA_INIT1        0x0f000
 524 #define PHY_CICADA_INIT2        0x0e00
 525 #define PHY_CICADA_INIT3        0x01000
 526 #define PHY_CICADA_INIT4        0x0200
 527 #define PHY_CICADA_INIT5        0x0004
 528 #define PHY_CICADA_INIT6        0x02000
 529 #define PHY_VITESSE_INIT_REG1   0x1f
 530 #define PHY_VITESSE_INIT_REG2   0x10
 531 #define PHY_VITESSE_INIT_REG3   0x11
 532 #define PHY_VITESSE_INIT_REG4   0x12
 533 #define PHY_VITESSE_INIT_MSK1   0xc
 534 #define PHY_VITESSE_INIT_MSK2   0x0180
 535 #define PHY_VITESSE_INIT1       0x52b5
 536 #define PHY_VITESSE_INIT2       0xaf8a
 537 #define PHY_VITESSE_INIT3       0x8
 538 #define PHY_VITESSE_INIT4       0x8f8a
 539 #define PHY_VITESSE_INIT5       0xaf86
 540 #define PHY_VITESSE_INIT6       0x8f86
 541 #define PHY_VITESSE_INIT7       0xaf82
 542 #define PHY_VITESSE_INIT8       0x0100
 543 #define PHY_VITESSE_INIT9       0x8f82
 544 #define PHY_VITESSE_INIT10      0x0
 545 #define PHY_REALTEK_INIT_REG1   0x1f
 546 #define PHY_REALTEK_INIT_REG2   0x19
 547 #define PHY_REALTEK_INIT_REG3   0x13
 548 #define PHY_REALTEK_INIT_REG4   0x14
 549 #define PHY_REALTEK_INIT_REG5   0x18
 550 #define PHY_REALTEK_INIT_REG6   0x11
 551 #define PHY_REALTEK_INIT_REG7   0x01
 552 #define PHY_REALTEK_INIT1       0x0000
 553 #define PHY_REALTEK_INIT2       0x8e00
 554 #define PHY_REALTEK_INIT3       0x0001
 555 #define PHY_REALTEK_INIT4       0xad17
 556 #define PHY_REALTEK_INIT5       0xfb54
 557 #define PHY_REALTEK_INIT6       0xf5c7
 558 #define PHY_REALTEK_INIT7       0x1000
 559 #define PHY_REALTEK_INIT8       0x0003
 560 #define PHY_REALTEK_INIT9       0x0008
 561 #define PHY_REALTEK_INIT10      0x0005
 562 #define PHY_REALTEK_INIT11      0x0200
 563 #define PHY_REALTEK_INIT_MSK1   0x0003
 564
 565 #define PHY_GIGABIT     0x0100
 566
 567 #define PHY_TIMEOUT     0x1
 568 #define PHY_ERROR       0x2
 569
 570 #define PHY_100 0x1
 571 #define PHY_1000        0x2
 572 #define PHY_HALF        0x100
 573
 574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 576 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 577 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 578 #define NV_PAUSEFRAME_RX_REQ     0x0010
 579 #define NV_PAUSEFRAME_TX_REQ     0x0020
 580 #define NV_PAUSEFRAME_AUTONEG    0x0040
 581
 582 /* MSI/MSI-X defines */
 583 #define NV_MSI_X_MAX_VECTORS  8
 584 #define NV_MSI_X_VECTORS_MASK 0x000f
 585 #define NV_MSI_CAPABLE        0x0010
 586 #define NV_MSI_X_CAPABLE      0x0020
 587 #define NV_MSI_ENABLED        0x0040
 588 #define NV_MSI_X_ENABLED      0x0080
 589
 590 #define NV_MSI_X_VECTOR_ALL   0x0
 591 #define NV_MSI_X_VECTOR_RX    0x0
 592 #define NV_MSI_X_VECTOR_TX    0x1
 593 #define NV_MSI_X_VECTOR_OTHER 0x2
 594
 595 #define NV_MSI_PRIV_OFFSET 0x68
 596 #define NV_MSI_PRIV_VALUE  0xffffffff
 597
 598 #define NV_RESTART_TX         0x1
 599 #define NV_RESTART_RX         0x2
 600
 601 #define NV_TX_LIMIT_COUNT     16
 602
 603 #define NV_DYNAMIC_THRESHOLD        4
 604 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 605
 606 /* statistics */
 607 struct nv_ethtool_str {
 608         char name[ETH_GSTRING_LEN];
 609 };
 610
 611 static const struct nv_ethtool_str nv_estats_str[] = {
 612         { "tx_bytes" }, /* includes Ethernet FCS CRC */
 613         { "tx_zero_rexmt" },
 614         { "tx_one_rexmt" },
 615         { "tx_many_rexmt" },
 616         { "tx_late_collision" },
 617         { "tx_fifo_errors" },
 618         { "tx_carrier_errors" },
 619         { "tx_excess_deferral" },
 620         { "tx_retry_error" },
 621         { "rx_frame_error" },
 622         { "rx_extra_byte" },
 623         { "rx_late_collision" },
 624         { "rx_runt" },
 625         { "rx_frame_too_long" },
 626         { "rx_over_errors" },
 627         { "rx_crc_errors" },
 628         { "rx_frame_align_error" },
 629         { "rx_length_error" },
 630         { "rx_unicast" },
 631         { "rx_multicast" },
 632         { "rx_broadcast" },
 633         { "rx_packets" },
 634         { "rx_errors_total" },
 635         { "tx_errors_total" },
 636
 637         /* version 2 stats */
 638         { "tx_deferral" },
 639         { "tx_packets" },
 640         { "rx_bytes" }, /* includes Ethernet FCS CRC */
 641         { "tx_pause" },
 642         { "rx_pause" },
 643         { "rx_drop_frame" },
 644
 645         /* version 3 stats */
 646         { "tx_unicast" },
 647         { "tx_multicast" },
 648         { "tx_broadcast" }
 649 };
 650
 651 struct nv_ethtool_stats {
 652         u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
 653         u64 tx_zero_rexmt;
 654         u64 tx_one_rexmt;
 655         u64 tx_many_rexmt;
 656         u64 tx_late_collision;
 657         u64 tx_fifo_errors;
 658         u64 tx_carrier_errors;
 659         u64 tx_excess_deferral;
 660         u64 tx_retry_error;
 661         u64 rx_frame_error;
 662         u64 rx_extra_byte;
 663         u64 rx_late_collision;
 664         u64 rx_runt;
 665         u64 rx_frame_too_long;
 666         u64 rx_over_errors;
 667         u64 rx_crc_errors;
 668         u64 rx_frame_align_error;
 669         u64 rx_length_error;
 670         u64 rx_unicast;
 671         u64 rx_multicast;
 672         u64 rx_broadcast;
 673         u64 rx_packets; /* should be ifconfig->rx_packets */
 674         u64 rx_errors_total;
 675         u64 tx_errors_total;
 676
 677         /* version 2 stats */
 678         u64 tx_deferral;
 679         u64 tx_packets; /* should be ifconfig->tx_packets */
 680         u64 rx_bytes;   /* should be ifconfig->rx_bytes + 4*rx_packets */
 681         u64 tx_pause;
 682         u64 rx_pause;
 683         u64 rx_drop_frame;
 684
 685         /* version 3 stats */
 686         u64 tx_unicast;
 687         u64 tx_multicast;
 688         u64 tx_broadcast;
 689 };
 690
 691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 694
 695 /* diagnostics */
 696 #define NV_TEST_COUNT_BASE 3
 697 #define NV_TEST_COUNT_EXTENDED 4
 698
 699 static const struct nv_ethtool_str nv_etests_str[] = {
 700         { "link      (online/offline)" },
 701         { "register  (offline)       " },
 702         { "interrupt (offline)       " },
 703         { "loopback  (offline)       " }
 704 };
 705
 706 struct register_test {
 707         __u32 reg;
 708         __u32 mask;
 709 };
 710
 711 static const struct register_test nv_registers_test[] = {
 712         { NvRegUnknownSetupReg6, 0x01 },
 713         { NvRegMisc1, 0x03c },
 714         { NvRegOffloadConfig, 0x03ff },
 715         { NvRegMulticastAddrA, 0xffffffff },
 716         { NvRegTxWatermark, 0x0ff },
 717         { NvRegWakeUpFlags, 0x07777 },
 718         { 0, 0 }
 719 };
 720
 721 struct nv_skb_map {
 722         struct sk_buff *skb;
 723         dma_addr_t dma;
 724         unsigned int dma_len:31;
 725         unsigned int dma_single:1;
 726         struct ring_desc_ex *first_tx_desc;
 727         struct nv_skb_map *next_tx_ctx;
 728 };
 729
 730 /*
 731  * SMP locking:
 732  * All hardware access under netdev_priv(dev)->lock, except the performance
 733  * critical parts:
 734  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 735  *      by the arch code for interrupts.
 736  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 737  *      needs netdev_priv(dev)->lock :-(
 738  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 739  *
 740  * Hardware stats updates are protected by hwstats_lock:
 741  * - updated by nv_do_stats_poll (timer). This is meant to avoid
 742  *   integer wraparound in the NIC stats registers, at low frequency
 743  *   (0.1 Hz)
 744  * - updated by nv_get_ethtool_stats + nv_get_stats64
 745  *
 746  * Software stats are accessed only through 64b synchronization points
 747  * and are not subject to other synchronization techniques (single
 748  * update thread on the TX or RX paths).
 749  */
 750
 751 /* in dev: base, irq */
 752 struct fe_priv {
 753         spinlock_t lock;
 754
 755         struct net_device *dev;
 756         struct napi_struct napi;
 757
 758         /* hardware stats are updated in syscall and timer */
 759         spinlock_t hwstats_lock;
 760         struct nv_ethtool_stats estats;
 761
 762         int in_shutdown;
 763         u32 linkspeed;
 764         int duplex;
 765         int autoneg;
 766         int fixed_mode;
 767         int phyaddr;
 768         int wolenabled;
 769         unsigned int phy_oui;
 770         unsigned int phy_model;
 771         unsigned int phy_rev;
 772         u16 gigabit;
 773         int intr_test;
 774         int recover_error;
 775         int quiet_count;
 776
 777         /* General data: RO fields */
 778         dma_addr_t ring_addr;
 779         struct pci_dev *pci_dev;
 780         u32 orig_mac[2];
 781         u32 events;
 782         u32 irqmask;
 783         u32 desc_ver;
 784         u32 txrxctl_bits;
 785         u32 vlanctl_bits;
 786         u32 driver_data;
 787         u32 device_id;
 788         u32 register_size;
 789         u32 mac_in_use;
 790         int mgmt_version;
 791         int mgmt_sema;
 792
 793         void __iomem *base;
 794
 795         /* rx specific fields.
 796          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 797          */
 798         union ring_type get_rx, put_rx, first_rx, last_rx;
 799         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 800         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 801         struct nv_skb_map *rx_skb;
 802
 803         union ring_type rx_ring;
 804         unsigned int rx_buf_sz;
 805         unsigned int pkt_limit;
 806         struct timer_list oom_kick;
 807         struct timer_list nic_poll;
 808         struct timer_list stats_poll;
 809         u32 nic_poll_irq;
 810         int rx_ring_size;
 811
 812         /* RX software stats */
 813         struct u64_stats_sync swstats_rx_syncp;
 814         u64 stat_rx_packets;
 815         u64 stat_rx_bytes; /* not always available in HW */
 816         u64 stat_rx_missed_errors;
 817         u64 stat_rx_dropped;
 818
 819         /* media detection workaround.
 820          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 821          */
 822         int need_linktimer;
 823         unsigned long link_timeout;
 824         /*
 825          * tx specific fields.
 826          */
 827         union ring_type get_tx, put_tx, first_tx, last_tx;
 828         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 829         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 830         struct nv_skb_map *tx_skb;
 831
 832         union ring_type tx_ring;
 833         u32 tx_flags;
 834         int tx_ring_size;
 835         int tx_limit;
 836         u32 tx_pkts_in_progress;
 837         struct nv_skb_map *tx_change_owner;
 838         struct nv_skb_map *tx_end_flip;
 839         int tx_stop;
 840
 841         /* TX software stats */
 842         struct u64_stats_sync swstats_tx_syncp;
 843         u64 stat_tx_packets; /* not always available in HW */
 844         u64 stat_tx_bytes;
 845         u64 stat_tx_dropped;
 846
 847         /* msi/msi-x fields */
 848         u32 msi_flags;
 849         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 850
 851         /* flow control */
 852         u32 pause_flags;
 853
 854         /* power saved state */
 855         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 856
 857         /* for different msi-x irq type */
 858         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 859         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 860         char name_other[IFNAMSIZ + 6];    /* -other */
 861 };
 862
 863 /*
 864  * Maximum number of loops until we assume that a bit in the irq mask
 865  * is stuck. Overridable with module param.
 866  */
 867 static int max_interrupt_work = 4;
 868
 869 /*
 870  * Optimization can be either throuput mode or cpu mode
 871  *
 872  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 873  * CPU Mode: Interrupts are controlled by a timer.
 874  */
 875 enum {
 876         NV_OPTIMIZATION_MODE_THROUGHPUT,
 877         NV_OPTIMIZATION_MODE_CPU,
 878         NV_OPTIMIZATION_MODE_DYNAMIC
 879 };
 880 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 881
 882 /*
 883  * Poll interval for timer irq
 884  *
 885  * This interval determines how frequent an interrupt is generated.
 886  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 887  * Min = 0, and Max = 65535
 888  */
 889 static int poll_interval = -1;
 890
 891 /*
 892  * MSI interrupts
 893  */
 894 enum {
 895         NV_MSI_INT_DISABLED,
 896         NV_MSI_INT_ENABLED
 897 };
 898 static int msi = NV_MSI_INT_ENABLED;
 899
 900 /*
 901  * MSIX interrupts
 902  */
 903 enum {
 904         NV_MSIX_INT_DISABLED,
 905         NV_MSIX_INT_ENABLED
 906 };
 907 static int msix = NV_MSIX_INT_ENABLED;
 908
 909 /*
 910  * DMA 64bit
 911  */
 912 enum {
 913         NV_DMA_64BIT_DISABLED,
 914         NV_DMA_64BIT_ENABLED
 915 };
 916 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 917
 918 /*
 919  * Debug output control for tx_timeout
 920  */
 921 static bool debug_tx_timeout = false;
 922
 923 /*
 924  * Crossover Detection
 925  * Realtek 8201 phy + some OEM boards do not work properly.
 926  */
 927 enum {
 928         NV_CROSSOVER_DETECTION_DISABLED,
 929         NV_CROSSOVER_DETECTION_ENABLED
 930 };
 931 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 932
 933 /*
 934  * Power down phy when interface is down (persists through reboot;
 935  * older Linux and other OSes may not power it up again)
 936  */
 937 static int phy_power_down;
 938
 939 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 940 {
 941         return netdev_priv(dev);
 942 }
 943
 944 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 945 {
 946         return ((struct fe_priv *)netdev_priv(dev))->base;
 947 }
 948
 949 static inline void pci_push(u8 __iomem *base)
 950 {
 951         /* force out pending posted writes */
 952         readl(base);
 953 }
 954
 955 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 956 {
 957         return le32_to_cpu(prd->flaglen)
 958                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 959 }
 960
 961 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 962 {
 963         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 964 }
 965
 966 static bool nv_optimized(struct fe_priv *np)
 967 {
 968         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 969                 return false;
 970         return true;
 971 }
 972
 973 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 974                      int delay, int delaymax)
 975 {
 976         u8 __iomem *base = get_hwbase(dev);
 977
 978         pci_push(base);
 979         do {
 980                 udelay(delay);
 981                 delaymax -= delay;
 982                 if (delaymax < 0)
 983                         return 1;
 984         } while ((readl(base + offset) & mask) != target);
 985         return 0;
 986 }
 987
 988 #define NV_SETUP_RX_RING 0x01
 989 #define NV_SETUP_TX_RING 0x02
 990
 991 static inline u32 dma_low(dma_addr_t addr)
 992 {
 993         return addr;
 994 }
 995
 996 static inline u32 dma_high(dma_addr_t addr)
 997 {
 998         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 999 }
1000
1001 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1002 {
1003         struct fe_priv *np = get_nvpriv(dev);
1004         u8 __iomem *base = get_hwbase(dev);
1005
1006         if (!nv_optimized(np)) {
1007                 if (rxtx_flags & NV_SETUP_RX_RING)
1008                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1009                 if (rxtx_flags & NV_SETUP_TX_RING)
1010                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1011         } else {
1012                 if (rxtx_flags & NV_SETUP_RX_RING) {
1013                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1014                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1015                 }
1016                 if (rxtx_flags & NV_SETUP_TX_RING) {
1017                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1018                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1019                 }
1020         }
1021 }
1022
1023 static void free_rings(struct net_device *dev)
1024 {
1025         struct fe_priv *np = get_nvpriv(dev);
1026
1027         if (!nv_optimized(np)) {
1028                 if (np->rx_ring.orig)
1029                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1030                                             np->rx_ring.orig, np->ring_addr);
1031         } else {
1032                 if (np->rx_ring.ex)
1033                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1034                                             np->rx_ring.ex, np->ring_addr);
1035         }
1036         kfree(np->rx_skb);
1037         kfree(np->tx_skb);
1038 }
1039
1040 static int using_multi_irqs(struct net_device *dev)
1041 {
1042         struct fe_priv *np = get_nvpriv(dev);
1043
1044         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1045             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1046              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1047                 return 0;
1048         else
1049                 return 1;
1050 }
1051
1052 static void nv_txrx_gate(struct net_device *dev, bool gate)
1053 {
1054         struct fe_priv *np = get_nvpriv(dev);
1055         u8 __iomem *base = get_hwbase(dev);
1056         u32 powerstate;
1057
1058         if (!np->mac_in_use &&
1059             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1060                 powerstate = readl(base + NvRegPowerState2);
1061                 if (gate)
1062                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1063                 else
1064                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1065                 writel(powerstate, base + NvRegPowerState2);
1066         }
1067 }
1068
1069 static void nv_enable_irq(struct net_device *dev)
1070 {
1071         struct fe_priv *np = get_nvpriv(dev);
1072
1073         if (!using_multi_irqs(dev)) {
1074                 if (np->msi_flags & NV_MSI_X_ENABLED)
1075                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1076                 else
1077                         enable_irq(np->pci_dev->irq);
1078         } else {
1079                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1080                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1081                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1082         }
1083 }
1084
1085 static void nv_disable_irq(struct net_device *dev)
1086 {
1087         struct fe_priv *np = get_nvpriv(dev);
1088
1089         if (!using_multi_irqs(dev)) {
1090                 if (np->msi_flags & NV_MSI_X_ENABLED)
1091                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1092                 else
1093                         disable_irq(np->pci_dev->irq);
1094         } else {
1095                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1096                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1097                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1098         }
1099 }
1100
1101 /* In MSIX mode, a write to irqmask behaves as XOR */
1102 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1103 {
1104         u8 __iomem *base = get_hwbase(dev);
1105
1106         writel(mask, base + NvRegIrqMask);
1107 }
1108
1109 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1110 {
1111         struct fe_priv *np = get_nvpriv(dev);
1112         u8 __iomem *base = get_hwbase(dev);
1113
1114         if (np->msi_flags & NV_MSI_X_ENABLED) {
1115                 writel(mask, base + NvRegIrqMask);
1116         } else {
1117                 if (np->msi_flags & NV_MSI_ENABLED)
1118                         writel(0, base + NvRegMSIIrqMask);
1119                 writel(0, base + NvRegIrqMask);
1120         }
1121 }
1122
1123 static void nv_napi_enable(struct net_device *dev)
1124 {
1125         struct fe_priv *np = get_nvpriv(dev);
1126
1127         napi_enable(&np->napi);
1128 }
1129
1130 static void nv_napi_disable(struct net_device *dev)
1131 {
1132         struct fe_priv *np = get_nvpriv(dev);
1133
1134         napi_disable(&np->napi);
1135 }
1136
1137 #define MII_READ        (-1)
1138 /* mii_rw: read/write a register on the PHY.
1139  *
1140  * Caller must guarantee serialization
1141  */
1142 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1143 {
1144         u8 __iomem *base = get_hwbase(dev);
1145         u32 reg;
1146         int retval;
1147
1148         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1149
1150         reg = readl(base + NvRegMIIControl);
1151         if (reg & NVREG_MIICTL_INUSE) {
1152                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1153                 udelay(NV_MIIBUSY_DELAY);
1154         }
1155
1156         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1157         if (value != MII_READ) {
1158                 writel(value, base + NvRegMIIData);
1159                 reg |= NVREG_MIICTL_WRITE;
1160         }
1161         writel(reg, base + NvRegMIIControl);
1162
1163         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1164                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1165                 retval = -1;
1166         } else if (value != MII_READ) {
1167                 /* it was a write operation - fewer failures are detectable */
1168                 retval = 0;
1169         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1170                 retval = -1;
1171         } else {
1172                 retval = readl(base + NvRegMIIData);
1173         }
1174
1175         return retval;
1176 }
1177
1178 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1179 {
1180         struct fe_priv *np = netdev_priv(dev);
1181         u32 miicontrol;
1182         unsigned int tries = 0;
1183
1184         miicontrol = BMCR_RESET | bmcr_setup;
1185         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1186                 return -1;
1187
1188         /* wait for 500ms */
1189         msleep(500);
1190
1191         /* must wait till reset is deasserted */
1192         while (miicontrol & BMCR_RESET) {
1193                 usleep_range(10000, 20000);
1194                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1195                 /* FIXME: 100 tries seem excessive */
1196                 if (tries++ > 100)
1197                         return -1;
1198         }
1199         return 0;
1200 }
1201
1202 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1203 {
1204         static const struct {
1205                 int reg;
1206                 int init;
1207         } ri[] = {
1208                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1209                 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1210                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1211                 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1212                 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1213                 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1214                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1215         };
1216         int i;
1217
1218         for (i = 0; i < ARRAY_SIZE(ri); i++) {
1219                 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1220                         return PHY_ERROR;
1221         }
1222
1223         return 0;
1224 }
1225
1226 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1227 {
1228         u32 reg;
1229         u8 __iomem *base = get_hwbase(dev);
1230         u32 powerstate = readl(base + NvRegPowerState2);
1231
1232         /* need to perform hw phy reset */
1233         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1234         writel(powerstate, base + NvRegPowerState2);
1235         msleep(25);
1236
1237         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1238         writel(powerstate, base + NvRegPowerState2);
1239         msleep(25);
1240
1241         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1242         reg |= PHY_REALTEK_INIT9;
1243         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1244                 return PHY_ERROR;
1245         if (mii_rw(dev, np->phyaddr,
1246                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1247                 return PHY_ERROR;
1248         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1249         if (!(reg & PHY_REALTEK_INIT11)) {
1250                 reg |= PHY_REALTEK_INIT11;
1251                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1252                         return PHY_ERROR;
1253         }
1254         if (mii_rw(dev, np->phyaddr,
1255                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1256                 return PHY_ERROR;
1257
1258         return 0;
1259 }
1260
1261 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1262 {
1263         u32 phy_reserved;
1264
1265         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1266                 phy_reserved = mii_rw(dev, np->phyaddr,
1267                                       PHY_REALTEK_INIT_REG6, MII_READ);
1268                 phy_reserved |= PHY_REALTEK_INIT7;
1269                 if (mii_rw(dev, np->phyaddr,
1270                            PHY_REALTEK_INIT_REG6, phy_reserved))
1271                         return PHY_ERROR;
1272         }
1273
1274         return 0;
1275 }
1276
1277 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1278 {
1279         u32 phy_reserved;
1280
1281         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1282                 if (mii_rw(dev, np->phyaddr,
1283                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1284                         return PHY_ERROR;
1285                 phy_reserved = mii_rw(dev, np->phyaddr,
1286                                       PHY_REALTEK_INIT_REG2, MII_READ);
1287                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1288                 phy_reserved |= PHY_REALTEK_INIT3;
1289                 if (mii_rw(dev, np->phyaddr,
1290                            PHY_REALTEK_INIT_REG2, phy_reserved))
1291                         return PHY_ERROR;
1292                 if (mii_rw(dev, np->phyaddr,
1293                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1294                         return PHY_ERROR;
1295         }
1296
1297         return 0;
1298 }
1299
1300 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1301                        u32 phyinterface)
1302 {
1303         u32 phy_reserved;
1304
1305         if (phyinterface & PHY_RGMII) {
1306                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1307                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1308                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1309                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1310                         return PHY_ERROR;
1311                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1312                 phy_reserved |= PHY_CICADA_INIT5;
1313                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1314                         return PHY_ERROR;
1315         }
1316         phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1317         phy_reserved |= PHY_CICADA_INIT6;
1318         if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1319                 return PHY_ERROR;
1320
1321         return 0;
1322 }
1323
1324 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1325 {
1326         u32 phy_reserved;
1327
1328         if (mii_rw(dev, np->phyaddr,
1329                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1330                 return PHY_ERROR;
1331         if (mii_rw(dev, np->phyaddr,
1332                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1333                 return PHY_ERROR;
1334         phy_reserved = mii_rw(dev, np->phyaddr,
1335                               PHY_VITESSE_INIT_REG4, MII_READ);
1336         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1337                 return PHY_ERROR;
1338         phy_reserved = mii_rw(dev, np->phyaddr,
1339                               PHY_VITESSE_INIT_REG3, MII_READ);
1340         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1341         phy_reserved |= PHY_VITESSE_INIT3;
1342         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1343                 return PHY_ERROR;
1344         if (mii_rw(dev, np->phyaddr,
1345                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1346                 return PHY_ERROR;
1347         if (mii_rw(dev, np->phyaddr,
1348                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1349                 return PHY_ERROR;
1350         phy_reserved = mii_rw(dev, np->phyaddr,
1351                               PHY_VITESSE_INIT_REG4, MII_READ);
1352         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1353         phy_reserved |= PHY_VITESSE_INIT3;
1354         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1355                 return PHY_ERROR;
1356         phy_reserved = mii_rw(dev, np->phyaddr,
1357                               PHY_VITESSE_INIT_REG3, MII_READ);
1358         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1359                 return PHY_ERROR;
1360         if (mii_rw(dev, np->phyaddr,
1361                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1362                 return PHY_ERROR;
1363         if (mii_rw(dev, np->phyaddr,
1364                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1365                 return PHY_ERROR;
1366         phy_reserved = mii_rw(dev, np->phyaddr,
1367                               PHY_VITESSE_INIT_REG4, MII_READ);
1368         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1369                 return PHY_ERROR;
1370         phy_reserved = mii_rw(dev, np->phyaddr,
1371                               PHY_VITESSE_INIT_REG3, MII_READ);
1372         phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1373         phy_reserved |= PHY_VITESSE_INIT8;
1374         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1375                 return PHY_ERROR;
1376         if (mii_rw(dev, np->phyaddr,
1377                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1378                 return PHY_ERROR;
1379         if (mii_rw(dev, np->phyaddr,
1380                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1381                 return PHY_ERROR;
1382
1383         return 0;
1384 }
1385
1386 static int phy_init(struct net_device *dev)
1387 {
1388         struct fe_priv *np = get_nvpriv(dev);
1389         u8 __iomem *base = get_hwbase(dev);
1390         u32 phyinterface;
1391         u32 mii_status, mii_control, mii_control_1000, reg;
1392
1393         /* phy errata for E3016 phy */
1394         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1395                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1396                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1397                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1398                         netdev_info(dev, "%s: phy write to errata reg failed\n",
1399                                     pci_name(np->pci_dev));
1400                         return PHY_ERROR;
1401                 }
1402         }
1403         if (np->phy_oui == PHY_OUI_REALTEK) {
1404                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1405                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1406                         if (init_realtek_8211b(dev, np)) {
1407                                 netdev_info(dev, "%s: phy init failed\n",
1408                                             pci_name(np->pci_dev));
1409                                 return PHY_ERROR;
1410                         }
1411                 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1412                            np->phy_rev == PHY_REV_REALTEK_8211C) {
1413                         if (init_realtek_8211c(dev, np)) {
1414                                 netdev_info(dev, "%s: phy init failed\n",
1415                                             pci_name(np->pci_dev));
1416                                 return PHY_ERROR;
1417                         }
1418                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1419                         if (init_realtek_8201(dev, np)) {
1420                                 netdev_info(dev, "%s: phy init failed\n",
1421                                             pci_name(np->pci_dev));
1422                                 return PHY_ERROR;
1423                         }
1424                 }
1425         }
1426
1427         /* set advertise register */
1428         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1429         reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1430                 ADVERTISE_100HALF | ADVERTISE_100FULL |
1431                 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1432         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1433                 netdev_info(dev, "%s: phy write to advertise failed\n",
1434                             pci_name(np->pci_dev));
1435                 return PHY_ERROR;
1436         }
1437
1438         /* get phy interface type */
1439         phyinterface = readl(base + NvRegPhyInterface);
1440
1441         /* see if gigabit phy */
1442         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1443         if (mii_status & PHY_GIGABIT) {
1444                 np->gigabit = PHY_GIGABIT;
1445                 mii_control_1000 = mii_rw(dev, np->phyaddr,
1446                                           MII_CTRL1000, MII_READ);
1447                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1448                 if (phyinterface & PHY_RGMII)
1449                         mii_control_1000 |= ADVERTISE_1000FULL;
1450                 else
1451                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1452
1453                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1454                         netdev_info(dev, "%s: phy init failed\n",
1455                                     pci_name(np->pci_dev));
1456                         return PHY_ERROR;
1457                 }
1458         } else
1459                 np->gigabit = 0;
1460
1461         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1462         mii_control |= BMCR_ANENABLE;
1463
1464         if (np->phy_oui == PHY_OUI_REALTEK &&
1465             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1466             np->phy_rev == PHY_REV_REALTEK_8211C) {
1467                 /* start autoneg since we already performed hw reset above */
1468                 mii_control |= BMCR_ANRESTART;
1469                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1470                         netdev_info(dev, "%s: phy init failed\n",
1471                                     pci_name(np->pci_dev));
1472                         return PHY_ERROR;
1473                 }
1474         } else {
1475                 /* reset the phy
1476                  * (certain phys need bmcr to be setup with reset)
1477                  */
1478                 if (phy_reset(dev, mii_control)) {
1479                         netdev_info(dev, "%s: phy reset failed\n",
1480                                     pci_name(np->pci_dev));
1481                         return PHY_ERROR;
1482                 }
1483         }
1484
1485         /* phy vendor specific configuration */
1486         if ((np->phy_oui == PHY_OUI_CICADA)) {
1487                 if (init_cicada(dev, np, phyinterface)) {
1488                         netdev_info(dev, "%s: phy init failed\n",
1489                                     pci_name(np->pci_dev));
1490                         return PHY_ERROR;
1491                 }
1492         } else if (np->phy_oui == PHY_OUI_VITESSE) {
1493                 if (init_vitesse(dev, np)) {
1494                         netdev_info(dev, "%s: phy init failed\n",
1495                                     pci_name(np->pci_dev));
1496                         return PHY_ERROR;
1497                 }
1498         } else if (np->phy_oui == PHY_OUI_REALTEK) {
1499                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1500                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1501                         /* reset could have cleared these out, set them back */
1502                         if (init_realtek_8211b(dev, np)) {
1503                                 netdev_info(dev, "%s: phy init failed\n",
1504                                             pci_name(np->pci_dev));
1505                                 return PHY_ERROR;
1506                         }
1507                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1508                         if (init_realtek_8201(dev, np) ||
1509                             init_realtek_8201_cross(dev, np)) {
1510                                 netdev_info(dev, "%s: phy init failed\n",
1511                                             pci_name(np->pci_dev));
1512                                 return PHY_ERROR;
1513                         }
1514                 }
1515         }
1516
1517         /* some phys clear out pause advertisement on reset, set it back */
1518         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1519
1520         /* restart auto negotiation, power down phy */
1521         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1522         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1523         if (phy_power_down)
1524                 mii_control |= BMCR_PDOWN;
1525         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1526                 return PHY_ERROR;
1527
1528         return 0;
1529 }
1530
1531 static void nv_start_rx(struct net_device *dev)
1532 {
1533         struct fe_priv *np = netdev_priv(dev);
1534         u8 __iomem *base = get_hwbase(dev);
1535         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1536
1537         /* Already running? Stop it. */
1538         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1539                 rx_ctrl &= ~NVREG_RCVCTL_START;
1540                 writel(rx_ctrl, base + NvRegReceiverControl);
1541                 pci_push(base);
1542         }
1543         writel(np->linkspeed, base + NvRegLinkSpeed);
1544         pci_push(base);
1545         rx_ctrl |= NVREG_RCVCTL_START;
1546         if (np->mac_in_use)
1547                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1548         writel(rx_ctrl, base + NvRegReceiverControl);
1549         pci_push(base);
1550 }
1551
1552 static void nv_stop_rx(struct net_device *dev)
1553 {
1554         struct fe_priv *np = netdev_priv(dev);
1555         u8 __iomem *base = get_hwbase(dev);
1556         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1557
1558         if (!np->mac_in_use)
1559                 rx_ctrl &= ~NVREG_RCVCTL_START;
1560         else
1561                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1562         writel(rx_ctrl, base + NvRegReceiverControl);
1563         if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1564                       NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1565                 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1566                             __func__);
1567
1568         udelay(NV_RXSTOP_DELAY2);
1569         if (!np->mac_in_use)
1570                 writel(0, base + NvRegLinkSpeed);
1571 }
1572
1573 static void nv_start_tx(struct net_device *dev)
1574 {
1575         struct fe_priv *np = netdev_priv(dev);
1576         u8 __iomem *base = get_hwbase(dev);
1577         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1578
1579         tx_ctrl |= NVREG_XMITCTL_START;
1580         if (np->mac_in_use)
1581                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1582         writel(tx_ctrl, base + NvRegTransmitterControl);
1583         pci_push(base);
1584 }
1585
1586 static void nv_stop_tx(struct net_device *dev)
1587 {
1588         struct fe_priv *np = netdev_priv(dev);
1589         u8 __iomem *base = get_hwbase(dev);
1590         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1591
1592         if (!np->mac_in_use)
1593                 tx_ctrl &= ~NVREG_XMITCTL_START;
1594         else
1595                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1596         writel(tx_ctrl, base + NvRegTransmitterControl);
1597         if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1598                       NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1599                 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1600                             __func__);
1601
1602         udelay(NV_TXSTOP_DELAY2);
1603         if (!np->mac_in_use)
1604                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1605                        base + NvRegTransmitPoll);
1606 }
1607
1608 static void nv_start_rxtx(struct net_device *dev)
1609 {
1610         nv_start_rx(dev);
1611         nv_start_tx(dev);
1612 }
1613
1614 static void nv_stop_rxtx(struct net_device *dev)
1615 {
1616         nv_stop_rx(dev);
1617         nv_stop_tx(dev);
1618 }
1619
1620 static void nv_txrx_reset(struct net_device *dev)
1621 {
1622         struct fe_priv *np = netdev_priv(dev);
1623         u8 __iomem *base = get_hwbase(dev);
1624
1625         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1626         pci_push(base);
1627         udelay(NV_TXRX_RESET_DELAY);
1628         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1629         pci_push(base);
1630 }
1631
1632 static void nv_mac_reset(struct net_device *dev)
1633 {
1634         struct fe_priv *np = netdev_priv(dev);
1635         u8 __iomem *base = get_hwbase(dev);
1636         u32 temp1, temp2, temp3;
1637
1638         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1639         pci_push(base);
1640
1641         /* save registers since they will be cleared on reset */
1642         temp1 = readl(base + NvRegMacAddrA);
1643         temp2 = readl(base + NvRegMacAddrB);
1644         temp3 = readl(base + NvRegTransmitPoll);
1645
1646         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1647         pci_push(base);
1648         udelay(NV_MAC_RESET_DELAY);
1649         writel(0, base + NvRegMacReset);
1650         pci_push(base);
1651         udelay(NV_MAC_RESET_DELAY);
1652
1653         /* restore saved registers */
1654         writel(temp1, base + NvRegMacAddrA);
1655         writel(temp2, base + NvRegMacAddrB);
1656         writel(temp3, base + NvRegTransmitPoll);
1657
1658         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1659         pci_push(base);
1660 }
1661
1662 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1663 static void nv_update_stats(struct net_device *dev)
1664 {
1665         struct fe_priv *np = netdev_priv(dev);
1666         u8 __iomem *base = get_hwbase(dev);
1667
1668         /* If it happens that this is run in top-half context, then
1669          * replace the spin_lock of hwstats_lock with
1670          * spin_lock_irqsave() in calling functions. */
1671         WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1672         assert_spin_locked(&np->hwstats_lock);
1673
1674         /* query hardware */
1675         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1676         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1677         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1678         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1679         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1680         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1681         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1682         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1683         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1684         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1685         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1686         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1687         np->estats.rx_runt += readl(base + NvRegRxRunt);
1688         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1689         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1690         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1691         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1692         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1693         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1694         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1695         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1696         np->estats.rx_packets =
1697                 np->estats.rx_unicast +
1698                 np->estats.rx_multicast +
1699                 np->estats.rx_broadcast;
1700         np->estats.rx_errors_total =
1701                 np->estats.rx_crc_errors +
1702                 np->estats.rx_over_errors +
1703                 np->estats.rx_frame_error +
1704                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1705                 np->estats.rx_late_collision +
1706                 np->estats.rx_runt +
1707                 np->estats.rx_frame_too_long;
1708         np->estats.tx_errors_total =
1709                 np->estats.tx_late_collision +
1710                 np->estats.tx_fifo_errors +
1711                 np->estats.tx_carrier_errors +
1712                 np->estats.tx_excess_deferral +
1713                 np->estats.tx_retry_error;
1714
1715         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1716                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1717                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1718                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1719                 np->estats.tx_pause += readl(base + NvRegTxPause);
1720                 np->estats.rx_pause += readl(base + NvRegRxPause);
1721                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1722                 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1723         }
1724
1725         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1726                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1727                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1728                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1729         }
1730 }
1731
1732 /*
1733  * nv_get_stats64: dev->ndo_get_stats64 function
1734  * Get latest stats value from the nic.
1735  * Called with read_lock(&dev_base_lock) held for read -
1736  * only synchronized against unregister_netdevice.
1737  */
1738 static struct rtnl_link_stats64*
1739 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1740         __acquires(&netdev_priv(dev)->hwstats_lock)
1741         __releases(&netdev_priv(dev)->hwstats_lock)
1742 {
1743         struct fe_priv *np = netdev_priv(dev);
1744         unsigned int syncp_start;
1745
1746         /*
1747          * Note: because HW stats are not always available and for
1748          * consistency reasons, the following ifconfig stats are
1749          * managed by software: rx_bytes, tx_bytes, rx_packets and
1750          * tx_packets. The related hardware stats reported by ethtool
1751          * should be equivalent to these ifconfig stats, with 4
1752          * additional bytes per packet (Ethernet FCS CRC), except for
1753          * tx_packets when TSO kicks in.
1754          */
1755
1756         /* software stats */
1757         do {
1758                 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_rx_syncp);
1759                 storage->rx_packets       = np->stat_rx_packets;
1760                 storage->rx_bytes         = np->stat_rx_bytes;
1761                 storage->rx_dropped       = np->stat_rx_dropped;
1762                 storage->rx_missed_errors = np->stat_rx_missed_errors;
1763         } while (u64_stats_fetch_retry_bh(&np->swstats_rx_syncp, syncp_start));
1764
1765         do {
1766                 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_tx_syncp);
1767                 storage->tx_packets = np->stat_tx_packets;
1768                 storage->tx_bytes   = np->stat_tx_bytes;
1769                 storage->tx_dropped = np->stat_tx_dropped;
1770         } while (u64_stats_fetch_retry_bh(&np->swstats_tx_syncp, syncp_start));
1771
1772         /* If the nic supports hw counters then retrieve latest values */
1773         if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1774                 spin_lock_bh(&np->hwstats_lock);
1775
1776                 nv_update_stats(dev);
1777
1778                 /* generic stats */
1779                 storage->rx_errors = np->estats.rx_errors_total;
1780                 storage->tx_errors = np->estats.tx_errors_total;
1781
1782                 /* meaningful only when NIC supports stats v3 */
1783                 storage->multicast = np->estats.rx_multicast;
1784
1785                 /* detailed rx_errors */
1786                 storage->rx_length_errors = np->estats.rx_length_error;
1787                 storage->rx_over_errors   = np->estats.rx_over_errors;
1788                 storage->rx_crc_errors    = np->estats.rx_crc_errors;
1789                 storage->rx_frame_errors  = np->estats.rx_frame_align_error;
1790                 storage->rx_fifo_errors   = np->estats.rx_drop_frame;
1791
1792                 /* detailed tx_errors */
1793                 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1794                 storage->tx_fifo_errors    = np->estats.tx_fifo_errors;
1795
1796                 spin_unlock_bh(&np->hwstats_lock);
1797         }
1798
1799         return storage;
1800 }
1801
1802 /*
1803  * nv_alloc_rx: fill rx ring entries.
1804  * Return 1 if the allocations for the skbs failed and the
1805  * rx engine is without Available descriptors
1806  */
1807 static int nv_alloc_rx(struct net_device *dev)
1808 {
1809         struct fe_priv *np = netdev_priv(dev);
1810         struct ring_desc *less_rx;
1811
1812         less_rx = np->get_rx.orig;
1813         if (less_rx-- == np->first_rx.orig)
1814                 less_rx = np->last_rx.orig;
1815
1816         while (np->put_rx.orig != less_rx) {
1817                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1818                 if (skb) {
1819                         np->put_rx_ctx->skb = skb;
1820                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1821                                                              skb->data,
1822                                                              skb_tailroom(skb),
1823                                                              PCI_DMA_FROMDEVICE);
1824                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1825                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1826                         wmb();
1827                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1828                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1829                                 np->put_rx.orig = np->first_rx.orig;
1830                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1831                                 np->put_rx_ctx = np->first_rx_ctx;
1832                 } else {
1833                         u64_stats_update_begin(&np->swstats_rx_syncp);
1834                         np->stat_rx_dropped++;
1835                         u64_stats_update_end(&np->swstats_rx_syncp);
1836                         return 1;
1837                 }
1838         }
1839         return 0;
1840 }
1841
1842 static int nv_alloc_rx_optimized(struct net_device *dev)
1843 {
1844         struct fe_priv *np = netdev_priv(dev);
1845         struct ring_desc_ex *less_rx;
1846
1847         less_rx = np->get_rx.ex;
1848         if (less_rx-- == np->first_rx.ex)
1849                 less_rx = np->last_rx.ex;
1850
1851         while (np->put_rx.ex != less_rx) {
1852                 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1853                 if (skb) {
1854                         np->put_rx_ctx->skb = skb;
1855                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1856                                                              skb->data,
1857                                                              skb_tailroom(skb),
1858                                                              PCI_DMA_FROMDEVICE);
1859                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1860                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1861                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1862                         wmb();
1863                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1864                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1865                                 np->put_rx.ex = np->first_rx.ex;
1866                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1867                                 np->put_rx_ctx = np->first_rx_ctx;
1868                 } else {
1869                         u64_stats_update_begin(&np->swstats_rx_syncp);
1870                         np->stat_rx_dropped++;
1871                         u64_stats_update_end(&np->swstats_rx_syncp);
1872                         return 1;
1873                 }
1874         }
1875         return 0;
1876 }
1877
1878 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1879 static void nv_do_rx_refill(unsigned long data)
1880 {
1881         struct net_device *dev = (struct net_device *) data;
1882         struct fe_priv *np = netdev_priv(dev);
1883
1884         /* Just reschedule NAPI rx processing */
1885         napi_schedule(&np->napi);
1886 }
1887
1888 static void nv_init_rx(struct net_device *dev)
1889 {
1890         struct fe_priv *np = netdev_priv(dev);
1891         int i;
1892
1893         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1894
1895         if (!nv_optimized(np))
1896                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1897         else
1898                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1899         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1900         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1901
1902         for (i = 0; i < np->rx_ring_size; i++) {
1903                 if (!nv_optimized(np)) {
1904                         np->rx_ring.orig[i].flaglen = 0;
1905                         np->rx_ring.orig[i].buf = 0;
1906                 } else {
1907                         np->rx_ring.ex[i].flaglen = 0;
1908                         np->rx_ring.ex[i].txvlan = 0;
1909                         np->rx_ring.ex[i].bufhigh = 0;
1910                         np->rx_ring.ex[i].buflow = 0;
1911                 }
1912                 np->rx_skb[i].skb = NULL;
1913                 np->rx_skb[i].dma = 0;
1914         }
1915 }
1916
1917 static void nv_init_tx(struct net_device *dev)
1918 {
1919         struct fe_priv *np = netdev_priv(dev);
1920         int i;
1921
1922         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1923
1924         if (!nv_optimized(np))
1925                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1926         else
1927                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1928         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1929         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1930         netdev_reset_queue(np->dev);
1931         np->tx_pkts_in_progress = 0;
1932         np->tx_change_owner = NULL;
1933         np->tx_end_flip = NULL;
1934         np->tx_stop = 0;
1935
1936         for (i = 0; i < np->tx_ring_size; i++) {
1937                 if (!nv_optimized(np)) {
1938                         np->tx_ring.orig[i].flaglen = 0;
1939                         np->tx_ring.orig[i].buf = 0;
1940                 } else {
1941                         np->tx_ring.ex[i].flaglen = 0;
1942                         np->tx_ring.ex[i].txvlan = 0;
1943                         np->tx_ring.ex[i].bufhigh = 0;
1944                         np->tx_ring.ex[i].buflow = 0;
1945                 }
1946                 np->tx_skb[i].skb = NULL;
1947                 np->tx_skb[i].dma = 0;
1948                 np->tx_skb[i].dma_len = 0;
1949                 np->tx_skb[i].dma_single = 0;
1950                 np->tx_skb[i].first_tx_desc = NULL;
1951                 np->tx_skb[i].next_tx_ctx = NULL;
1952         }
1953 }
1954
1955 static int nv_init_ring(struct net_device *dev)
1956 {
1957         struct fe_priv *np = netdev_priv(dev);
1958
1959         nv_init_tx(dev);
1960         nv_init_rx(dev);
1961
1962         if (!nv_optimized(np))
1963                 return nv_alloc_rx(dev);
1964         else
1965                 return nv_alloc_rx_optimized(dev);
1966 }
1967
1968 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1969 {
1970         if (tx_skb->dma) {
1971                 if (tx_skb->dma_single)
1972                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1973                                          tx_skb->dma_len,
1974                                          PCI_DMA_TODEVICE);
1975                 else
1976                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1977                                        tx_skb->dma_len,
1978                                        PCI_DMA_TODEVICE);
1979                 tx_skb->dma = 0;
1980         }
1981 }
1982
1983 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1984 {
1985         nv_unmap_txskb(np, tx_skb);
1986         if (tx_skb->skb) {
1987                 dev_kfree_skb_any(tx_skb->skb);
1988                 tx_skb->skb = NULL;
1989                 return 1;
1990         }
1991         return 0;
1992 }
1993
1994 static void nv_drain_tx(struct net_device *dev)
1995 {
1996         struct fe_priv *np = netdev_priv(dev);
1997         unsigned int i;
1998
1999         for (i = 0; i < np->tx_ring_size; i++) {
2000                 if (!nv_optimized(np)) {
2001                         np->tx_ring.orig[i].flaglen = 0;
2002                         np->tx_ring.orig[i].buf = 0;
2003                 } else {
2004                         np->tx_ring.ex[i].flaglen = 0;
2005                         np->tx_ring.ex[i].txvlan = 0;
2006                         np->tx_ring.ex[i].bufhigh = 0;
2007                         np->tx_ring.ex[i].buflow = 0;
2008                 }
2009                 if (nv_release_txskb(np, &np->tx_skb[i])) {
2010                         u64_stats_update_begin(&np->swstats_tx_syncp);
2011                         np->stat_tx_dropped++;
2012                         u64_stats_update_end(&np->swstats_tx_syncp);
2013                 }
2014                 np->tx_skb[i].dma = 0;
2015                 np->tx_skb[i].dma_len = 0;
2016                 np->tx_skb[i].dma_single = 0;
2017                 np->tx_skb[i].first_tx_desc = NULL;
2018                 np->tx_skb[i].next_tx_ctx = NULL;
2019         }
2020         np->tx_pkts_in_progress = 0;
2021         np->tx_change_owner = NULL;
2022         np->tx_end_flip = NULL;
2023 }
2024
2025 static void nv_drain_rx(struct net_device *dev)
2026 {
2027         struct fe_priv *np = netdev_priv(dev);
2028         int i;
2029
2030         for (i = 0; i < np->rx_ring_size; i++) {
2031                 if (!nv_optimized(np)) {
2032                         np->rx_ring.orig[i].flaglen = 0;
2033                         np->rx_ring.orig[i].buf = 0;
2034                 } else {
2035                         np->rx_ring.ex[i].flaglen = 0;
2036                         np->rx_ring.ex[i].txvlan = 0;
2037                         np->rx_ring.ex[i].bufhigh = 0;
2038                         np->rx_ring.ex[i].buflow = 0;
2039                 }
2040                 wmb();
2041                 if (np->rx_skb[i].skb) {
2042                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2043                                          (skb_end_pointer(np->rx_skb[i].skb) -
2044                                           np->rx_skb[i].skb->data),
2045                                          PCI_DMA_FROMDEVICE);
2046                         dev_kfree_skb(np->rx_skb[i].skb);
2047                         np->rx_skb[i].skb = NULL;
2048                 }
2049         }
2050 }
2051
2052 static void nv_drain_rxtx(struct net_device *dev)
2053 {
2054         nv_drain_tx(dev);
2055         nv_drain_rx(dev);
2056 }
2057
2058 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2059 {
2060         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2061 }
2062
2063 static void nv_legacybackoff_reseed(struct net_device *dev)
2064 {
2065         u8 __iomem *base = get_hwbase(dev);
2066         u32 reg;
2067         u32 low;
2068         int tx_status = 0;
2069
2070         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2071         get_random_bytes(&low, sizeof(low));
2072         reg |= low & NVREG_SLOTTIME_MASK;
2073
2074         /* Need to stop tx before change takes effect.
2075          * Caller has already gained np->lock.
2076          */
2077         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2078         if (tx_status)
2079                 nv_stop_tx(dev);
2080         nv_stop_rx(dev);
2081         writel(reg, base + NvRegSlotTime);
2082         if (tx_status)
2083                 nv_start_tx(dev);
2084         nv_start_rx(dev);
2085 }
2086
2087 /* Gear Backoff Seeds */
2088 #define BACKOFF_SEEDSET_ROWS    8
2089 #define BACKOFF_SEEDSET_LFSRS   15
2090
2091 /* Known Good seed sets */
2092 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2093         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2094         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2095         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2096         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2097         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2098         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2099         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2100         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2101
2102 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2103         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2104         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2105         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2106         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2107         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2108         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2109         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2110         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2111
2112 static void nv_gear_backoff_reseed(struct net_device *dev)
2113 {
2114         u8 __iomem *base = get_hwbase(dev);
2115         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2116         u32 temp, seedset, combinedSeed;
2117         int i;
2118
2119         /* Setup seed for free running LFSR */
2120         /* We are going to read the time stamp counter 3 times
2121            and swizzle bits around to increase randomness */
2122         get_random_bytes(&miniseed1, sizeof(miniseed1));
2123         miniseed1 &= 0x0fff;
2124         if (miniseed1 == 0)
2125                 miniseed1 = 0xabc;
2126
2127         get_random_bytes(&miniseed2, sizeof(miniseed2));
2128         miniseed2 &= 0x0fff;
2129         if (miniseed2 == 0)
2130                 miniseed2 = 0xabc;
2131         miniseed2_reversed =
2132                 ((miniseed2 & 0xF00) >> 8) |
2133                  (miniseed2 & 0x0F0) |
2134                  ((miniseed2 & 0x00F) << 8);
2135
2136         get_random_bytes(&miniseed3, sizeof(miniseed3));
2137         miniseed3 &= 0x0fff;
2138         if (miniseed3 == 0)
2139                 miniseed3 = 0xabc;
2140         miniseed3_reversed =
2141                 ((miniseed3 & 0xF00) >> 8) |
2142                  (miniseed3 & 0x0F0) |
2143                  ((miniseed3 & 0x00F) << 8);
2144
2145         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2146                        (miniseed2 ^ miniseed3_reversed);
2147
2148         /* Seeds can not be zero */
2149         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2150                 combinedSeed |= 0x08;
2151         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2152                 combinedSeed |= 0x8000;
2153
2154         /* No need to disable tx here */
2155         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2156         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2157         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2158         writel(temp, base + NvRegBackOffControl);
2159
2160         /* Setup seeds for all gear LFSRs. */
2161         get_random_bytes(&seedset, sizeof(seedset));
2162         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2163         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2164                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2165                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2166                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2167                 writel(temp, base + NvRegBackOffControl);
2168         }
2169 }
2170
2171 /*
2172  * nv_start_xmit: dev->hard_start_xmit function
2173  * Called with netif_tx_lock held.
2174  */
2175 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2176 {
2177         struct fe_priv *np = netdev_priv(dev);
2178         u32 tx_flags = 0;
2179         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2180         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2181         unsigned int i;
2182         u32 offset = 0;
2183         u32 bcnt;
2184         u32 size = skb_headlen(skb);
2185         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2186         u32 empty_slots;
2187         struct ring_desc *put_tx;
2188         struct ring_desc *start_tx;
2189         struct ring_desc *prev_tx;
2190         struct nv_skb_map *prev_tx_ctx;
2191         unsigned long flags;
2192
2193         /* add fragments to entries count */
2194         for (i = 0; i < fragments; i++) {
2195                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2196
2197                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2198                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2199         }
2200
2201         spin_lock_irqsave(&np->lock, flags);
2202         empty_slots = nv_get_empty_tx_slots(np);
2203         if (unlikely(empty_slots <= entries)) {
2204                 netif_stop_queue(dev);
2205                 np->tx_stop = 1;
2206                 spin_unlock_irqrestore(&np->lock, flags);
2207                 return NETDEV_TX_BUSY;
2208         }
2209         spin_unlock_irqrestore(&np->lock, flags);
2210
2211         start_tx = put_tx = np->put_tx.orig;
2212
2213         /* setup the header buffer */
2214         do {
2215                 prev_tx = put_tx;
2216                 prev_tx_ctx = np->put_tx_ctx;
2217                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2218                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2219                                                 PCI_DMA_TODEVICE);
2220                 np->put_tx_ctx->dma_len = bcnt;
2221                 np->put_tx_ctx->dma_single = 1;
2222                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2223                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2224
2225                 tx_flags = np->tx_flags;
2226                 offset += bcnt;
2227                 size -= bcnt;
2228                 if (unlikely(put_tx++ == np->last_tx.orig))
2229                         put_tx = np->first_tx.orig;
2230                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2231                         np->put_tx_ctx = np->first_tx_ctx;
2232         } while (size);
2233
2234         /* setup the fragments */
2235         for (i = 0; i < fragments; i++) {
2236                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2237                 u32 frag_size = skb_frag_size(frag);
2238                 offset = 0;
2239
2240                 do {
2241                         prev_tx = put_tx;
2242                         prev_tx_ctx = np->put_tx_ctx;
2243                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2244                         np->put_tx_ctx->dma = skb_frag_dma_map(
2245                                                         &np->pci_dev->dev,
2246                                                         frag, offset,
2247                                                         bcnt,
2248                                                         DMA_TO_DEVICE);
2249                         np->put_tx_ctx->dma_len = bcnt;
2250                         np->put_tx_ctx->dma_single = 0;
2251                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2252                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2253
2254                         offset += bcnt;
2255                         frag_size -= bcnt;
2256                         if (unlikely(put_tx++ == np->last_tx.orig))
2257                                 put_tx = np->first_tx.orig;
2258                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2259                                 np->put_tx_ctx = np->first_tx_ctx;
2260                 } while (frag_size);
2261         }
2262
2263         /* set last fragment flag  */
2264         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2265
2266         /* save skb in this slot's context area */
2267         prev_tx_ctx->skb = skb;
2268
2269         if (skb_is_gso(skb))
2270                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2271         else
2272                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2273                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2274
2275         spin_lock_irqsave(&np->lock, flags);
2276
2277         /* set tx flags */
2278         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2279
2280         netdev_sent_queue(np->dev, skb->len);
2281
2282         skb_tx_timestamp(skb);
2283
2284         np->put_tx.orig = put_tx;
2285
2286         spin_unlock_irqrestore(&np->lock, flags);
2287
2288         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2289         return NETDEV_TX_OK;
2290 }
2291
2292 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2293                                            struct net_device *dev)
2294 {
2295         struct fe_priv *np = netdev_priv(dev);
2296         u32 tx_flags = 0;
2297         u32 tx_flags_extra;
2298         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2299         unsigned int i;
2300         u32 offset = 0;
2301         u32 bcnt;
2302         u32 size = skb_headlen(skb);
2303         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2304         u32 empty_slots;
2305         struct ring_desc_ex *put_tx;
2306         struct ring_desc_ex *start_tx;
2307         struct ring_desc_ex *prev_tx;
2308         struct nv_skb_map *prev_tx_ctx;
2309         struct nv_skb_map *start_tx_ctx;
2310         unsigned long flags;
2311
2312         /* add fragments to entries count */
2313         for (i = 0; i < fragments; i++) {
2314                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2315
2316                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2317                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2318         }
2319
2320         spin_lock_irqsave(&np->lock, flags);
2321         empty_slots = nv_get_empty_tx_slots(np);
2322         if (unlikely(empty_slots <= entries)) {
2323                 netif_stop_queue(dev);
2324                 np->tx_stop = 1;
2325                 spin_unlock_irqrestore(&np->lock, flags);
2326                 return NETDEV_TX_BUSY;
2327         }
2328         spin_unlock_irqrestore(&np->lock, flags);
2329
2330         start_tx = put_tx = np->put_tx.ex;
2331         start_tx_ctx = np->put_tx_ctx;
2332
2333         /* setup the header buffer */
2334         do {
2335                 prev_tx = put_tx;
2336                 prev_tx_ctx = np->put_tx_ctx;
2337                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2338                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2339                                                 PCI_DMA_TODEVICE);
2340                 np->put_tx_ctx->dma_len = bcnt;
2341                 np->put_tx_ctx->dma_single = 1;
2342                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2343                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2344                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2345
2346                 tx_flags = NV_TX2_VALID;
2347                 offset += bcnt;
2348                 size -= bcnt;
2349                 if (unlikely(put_tx++ == np->last_tx.ex))
2350                         put_tx = np->first_tx.ex;
2351                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2352                         np->put_tx_ctx = np->first_tx_ctx;
2353         } while (size);
2354
2355         /* setup the fragments */
2356         for (i = 0; i < fragments; i++) {
2357                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2358                 u32 frag_size = skb_frag_size(frag);
2359                 offset = 0;
2360
2361                 do {
2362                         prev_tx = put_tx;
2363                         prev_tx_ctx = np->put_tx_ctx;
2364                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2365                         np->put_tx_ctx->dma = skb_frag_dma_map(
2366                                                         &np->pci_dev->dev,
2367                                                         frag, offset,
2368                                                         bcnt,
2369                                                         DMA_TO_DEVICE);
2370                         np->put_tx_ctx->dma_len = bcnt;
2371                         np->put_tx_ctx->dma_single = 0;
2372                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2373                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2374                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2375
2376                         offset += bcnt;
2377                         frag_size -= bcnt;
2378                         if (unlikely(put_tx++ == np->last_tx.ex))
2379                                 put_tx = np->first_tx.ex;
2380                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2381                                 np->put_tx_ctx = np->first_tx_ctx;
2382                 } while (frag_size);
2383         }
2384
2385         /* set last fragment flag  */
2386         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2387
2388         /* save skb in this slot's context area */
2389         prev_tx_ctx->skb = skb;
2390
2391         if (skb_is_gso(skb))
2392                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2393         else
2394                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2395                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2396
2397         /* vlan tag */
2398         if (vlan_tx_tag_present(skb))
2399                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2400                                         vlan_tx_tag_get(skb));
2401         else
2402                 start_tx->txvlan = 0;
2403
2404         spin_lock_irqsave(&np->lock, flags);
2405
2406         if (np->tx_limit) {
2407                 /* Limit the number of outstanding tx. Setup all fragments, but
2408                  * do not set the VALID bit on the first descriptor. Save a pointer
2409                  * to that descriptor and also for next skb_map element.
2410                  */
2411
2412                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2413                         if (!np->tx_change_owner)
2414                                 np->tx_change_owner = start_tx_ctx;
2415
2416                         /* remove VALID bit */
2417                         tx_flags &= ~NV_TX2_VALID;
2418                         start_tx_ctx->first_tx_desc = start_tx;
2419                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2420                         np->tx_end_flip = np->put_tx_ctx;
2421                 } else {
2422                         np->tx_pkts_in_progress++;
2423                 }
2424         }
2425
2426         /* set tx flags */
2427         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2428
2429         netdev_sent_queue(np->dev, skb->len);
2430
2431         skb_tx_timestamp(skb);
2432
2433         np->put_tx.ex = put_tx;
2434
2435         spin_unlock_irqrestore(&np->lock, flags);
2436
2437         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2438         return NETDEV_TX_OK;
2439 }
2440
2441 static inline void nv_tx_flip_ownership(struct net_device *dev)
2442 {
2443         struct fe_priv *np = netdev_priv(dev);
2444
2445         np->tx_pkts_in_progress--;
2446         if (np->tx_change_owner) {
2447                 np->tx_change_owner->first_tx_desc->flaglen |=
2448                         cpu_to_le32(NV_TX2_VALID);
2449                 np->tx_pkts_in_progress++;
2450
2451                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2452                 if (np->tx_change_owner == np->tx_end_flip)
2453                         np->tx_change_owner = NULL;
2454
2455                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2456         }
2457 }
2458
2459 /*
2460  * nv_tx_done: check for completed packets, release the skbs.
2461  *
2462  * Caller must own np->lock.
2463  */
2464 static int nv_tx_done(struct net_device *dev, int limit)
2465 {
2466         struct fe_priv *np = netdev_priv(dev);
2467         u32 flags;
2468         int tx_work = 0;
2469         struct ring_desc *orig_get_tx = np->get_tx.orig;
2470         unsigned int bytes_compl = 0;
2471
2472         while ((np->get_tx.orig != np->put_tx.orig) &&
2473                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2474                (tx_work < limit)) {
2475
2476                 nv_unmap_txskb(np, np->get_tx_ctx);
2477
2478                 if (np->desc_ver == DESC_VER_1) {
2479                         if (flags & NV_TX_LASTPACKET) {
2480                                 if (flags & NV_TX_ERROR) {
2481                                         if ((flags & NV_TX_RETRYERROR)
2482                                             && !(flags & NV_TX_RETRYCOUNT_MASK))
2483                                                 nv_legacybackoff_reseed(dev);
2484                                 } else {
2485                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2486                                         np->stat_tx_packets++;
2487                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2488                                         u64_stats_update_end(&np->swstats_tx_syncp);
2489                                 }
2490                                 bytes_compl += np->get_tx_ctx->skb->len;
2491                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2492                                 np->get_tx_ctx->skb = NULL;
2493                                 tx_work++;
2494                         }
2495                 } else {
2496                         if (flags & NV_TX2_LASTPACKET) {
2497                                 if (flags & NV_TX2_ERROR) {
2498                                         if ((flags & NV_TX2_RETRYERROR)
2499                                             && !(flags & NV_TX2_RETRYCOUNT_MASK))
2500                                                 nv_legacybackoff_reseed(dev);
2501                                 } else {
2502                                         u64_stats_update_begin(&np->swstats_tx_syncp);
2503                                         np->stat_tx_packets++;
2504                                         np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2505                                         u64_stats_update_end(&np->swstats_tx_syncp);
2506                                 }
2507                                 bytes_compl += np->get_tx_ctx->skb->len;
2508                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2509                                 np->get_tx_ctx->skb = NULL;
2510                                 tx_work++;
2511                         }
2512                 }
2513                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2514                         np->get_tx.orig = np->first_tx.orig;
2515                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2516                         np->get_tx_ctx = np->first_tx_ctx;
2517         }
2518
2519         netdev_completed_queue(np->dev, tx_work, bytes_compl);
2520
2521         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2522                 np->tx_stop = 0;
2523                 netif_wake_queue(dev);
2524         }
2525         return tx_work;
2526 }
2527
2528 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2529 {
2530         struct fe_priv *np = netdev_priv(dev);
2531         u32 flags;
2532         int tx_work = 0;
2533         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2534         unsigned long bytes_cleaned = 0;
2535
2536         while ((np->get_tx.ex != np->put_tx.ex) &&
2537                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2538                (tx_work < limit)) {
2539
2540                 nv_unmap_txskb(np, np->get_tx_ctx);
2541
2542                 if (flags & NV_TX2_LASTPACKET) {
2543                         if (flags & NV_TX2_ERROR) {
2544                                 if ((flags & NV_TX2_RETRYERROR)
2545                                     && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2546                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2547                                                 nv_gear_backoff_reseed(dev);
2548                                         else
2549                                                 nv_legacybackoff_reseed(dev);
2550                                 }
2551                         } else {
2552                                 u64_stats_update_begin(&np->swstats_tx_syncp);
2553                                 np->stat_tx_packets++;
2554                                 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2555                                 u64_stats_update_end(&np->swstats_tx_syncp);
2556                         }
2557
2558                         bytes_cleaned += np->get_tx_ctx->skb->len;
2559                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2560                         np->get_tx_ctx->skb = NULL;
2561                         tx_work++;
2562
2563                         if (np->tx_limit)
2564                                 nv_tx_flip_ownership(dev);
2565                 }
2566
2567                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2568                         np->get_tx.ex = np->first_tx.ex;
2569                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2570                         np->get_tx_ctx = np->first_tx_ctx;
2571         }
2572
2573         netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2574
2575         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2576                 np->tx_stop = 0;
2577                 netif_wake_queue(dev);
2578         }
2579         return tx_work;
2580 }
2581
2582 /*
2583  * nv_tx_timeout: dev->tx_timeout function
2584  * Called with netif_tx_lock held.
2585  */
2586 static void nv_tx_timeout(struct net_device *dev)
2587 {
2588         struct fe_priv *np = netdev_priv(dev);
2589         u8 __iomem *base = get_hwbase(dev);
2590         u32 status;
2591         union ring_type put_tx;
2592         int saved_tx_limit;
2593
2594         if (np->msi_flags & NV_MSI_X_ENABLED)
2595                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2596         else
2597                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2598
2599         netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2600
2601         if (unlikely(debug_tx_timeout)) {
2602                 int i;
2603
2604                 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2605                 netdev_info(dev, "Dumping tx registers\n");
2606                 for (i = 0; i <= np->register_size; i += 32) {
2607                         netdev_info(dev,
2608                                     "%3x: %08x %08x %08x %08x "
2609                                     "%08x %08x %08x %08x\n",
2610                                     i,
2611                                     readl(base + i + 0), readl(base + i + 4),
2612                                     readl(base + i + 8), readl(base + i + 12),
2613                                     readl(base + i + 16), readl(base + i + 20),
2614                                     readl(base + i + 24), readl(base + i + 28));
2615                 }
2616                 netdev_info(dev, "Dumping tx ring\n");
2617                 for (i = 0; i < np->tx_ring_size; i += 4) {
2618                         if (!nv_optimized(np)) {
2619                                 netdev_info(dev,
2620                                             "%03x: %08x %08x // %08x %08x "
2621                                             "// %08x %08x // %08x %08x\n",
2622                                             i,
2623                                             le32_to_cpu(np->tx_ring.orig[i].buf),
2624                                             le32_to_cpu(np->tx_ring.orig[i].flaglen),
2625                                             le32_to_cpu(np->tx_ring.orig[i+1].buf),
2626                                             le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2627                                             le32_to_cpu(np->tx_ring.orig[i+2].buf),
2628                                             le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2629                                             le32_to_cpu(np->tx_ring.orig[i+3].buf),
2630                                             le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2631                         } else {
2632                                 netdev_info(dev,
2633                                             "%03x: %08x %08x %08x "
2634                                             "// %08x %08x %08x "
2635                                             "// %08x %08x %08x "
2636                                             "// %08x %08x %08x\n",
2637                                             i,
2638                                             le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2639                                             le32_to_cpu(np->tx_ring.ex[i].buflow),
2640                                             le32_to_cpu(np->tx_ring.ex[i].flaglen),
2641                                             le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2642                                             le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2643                                             le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2644                                             le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2645                                             le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2646                                             le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2647                                             le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2648                                             le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2649                                             le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2650                         }
2651                 }
2652         }
2653
2654         spin_lock_irq(&np->lock);
2655
2656         /* 1) stop tx engine */
2657         nv_stop_tx(dev);
2658
2659         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2660         saved_tx_limit = np->tx_limit;
2661         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2662         np->tx_stop = 0;  /* prevent waking tx queue */
2663         if (!nv_optimized(np))
2664                 nv_tx_done(dev, np->tx_ring_size);
2665         else
2666                 nv_tx_done_optimized(dev, np->tx_ring_size);
2667
2668         /* save current HW position */
2669         if (np->tx_change_owner)
2670                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2671         else
2672                 put_tx = np->put_tx;
2673
2674         /* 3) clear all tx state */
2675         nv_drain_tx(dev);
2676         nv_init_tx(dev);
2677
2678         /* 4) restore state to current HW position */
2679         np->get_tx = np->put_tx = put_tx;
2680         np->tx_limit = saved_tx_limit;
2681
2682         /* 5) restart tx engine */
2683         nv_start_tx(dev);
2684         netif_wake_queue(dev);
2685         spin_unlock_irq(&np->lock);
2686 }
2687
2688 /*
2689  * Called when the nic notices a mismatch between the actual data len on the
2690  * wire and the len indicated in the 802 header
2691  */
2692 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2693 {
2694         int hdrlen;     /* length of the 802 header */
2695         int protolen;   /* length as stored in the proto field */
2696
2697         /* 1) calculate len according to header */
2698         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2699                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2700                 hdrlen = VLAN_HLEN;
2701         } else {
2702                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2703                 hdrlen = ETH_HLEN;
2704         }
2705         if (protolen > ETH_DATA_LEN)
2706                 return datalen; /* Value in proto field not a len, no checks possible */
2707
2708         protolen += hdrlen;
2709         /* consistency checks: */
2710         if (datalen > ETH_ZLEN) {
2711                 if (datalen >= protolen) {
2712                         /* more data on wire than in 802 header, trim of
2713                          * additional data.
2714                          */
2715                         return protolen;
2716                 } else {
2717                         /* less data on wire than mentioned in header.
2718                          * Discard the packet.
2719                          */
2720                         return -1;
2721                 }
2722         } else {
2723                 /* short packet. Accept only if 802 values are also short */
2724                 if (protolen > ETH_ZLEN) {
2725                         return -1;
2726                 }
2727                 return datalen;
2728         }
2729 }
2730
2731 static int nv_rx_process(struct net_device *dev, int limit)
2732 {
2733         struct fe_priv *np = netdev_priv(dev);
2734         u32 flags;
2735         int rx_work = 0;
2736         struct sk_buff *skb;
2737         int len;
2738
2739         while ((np->get_rx.orig != np->put_rx.orig) &&
2740               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2741                 (rx_work < limit)) {
2742
2743                 /*
2744                  * the packet is for us - immediately tear down the pci mapping.
2745                  * TODO: check if a prefetch of the first cacheline improves
2746                  * the performance.
2747                  */
2748                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2749                                 np->get_rx_ctx->dma_len,
2750                                 PCI_DMA_FROMDEVICE);
2751                 skb = np->get_rx_ctx->skb;
2752                 np->get_rx_ctx->skb = NULL;
2753
2754                 /* look at what we actually got: */
2755                 if (np->desc_ver == DESC_VER_1) {
2756                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2757                                 len = flags & LEN_MASK_V1;
2758                                 if (unlikely(flags & NV_RX_ERROR)) {
2759                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2760                                                 len = nv_getlen(dev, skb->data, len);
2761                                                 if (len < 0) {
2762                                                         dev_kfree_skb(skb);
2763                                                         goto next_pkt;
2764                                                 }
2765                                         }
2766                                         /* framing errors are soft errors */
2767                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2768                                                 if (flags & NV_RX_SUBSTRACT1)
2769                                                         len--;
2770                                         }
2771                                         /* the rest are hard errors */
2772                                         else {
2773                                                 if (flags & NV_RX_MISSEDFRAME) {
2774                                                         u64_stats_update_begin(&np->swstats_rx_syncp);
2775                                                         np->stat_rx_missed_errors++;
2776                                                         u64_stats_update_end(&np->swstats_rx_syncp);
2777                                                 }
2778                                                 dev_kfree_skb(skb);
2779                                                 goto next_pkt;
2780                                         }
2781                                 }
2782                         } else {
2783                                 dev_kfree_skb(skb);
2784                                 goto next_pkt;
2785                         }
2786                 } else {
2787                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2788                                 len = flags & LEN_MASK_V2;
2789                                 if (unlikely(flags & NV_RX2_ERROR)) {
2790                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2791                                                 len = nv_getlen(dev, skb->data, len);
2792                                                 if (len < 0) {
2793                                                         dev_kfree_skb(skb);
2794                                                         goto next_pkt;
2795                                                 }
2796                                         }
2797                                         /* framing errors are soft errors */
2798                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2799                                                 if (flags & NV_RX2_SUBSTRACT1)
2800                                                         len--;
2801                                         }
2802                                         /* the rest are hard errors */
2803                                         else {
2804                                                 dev_kfree_skb(skb);
2805                                                 goto next_pkt;
2806                                         }
2807                                 }
2808                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2809                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2810                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2811                         } else {
2812                                 dev_kfree_skb(skb);
2813                                 goto next_pkt;
2814                         }
2815                 }
2816                 /* got a valid packet - forward it to the network core */
2817                 skb_put(skb, len);
2818                 skb->protocol = eth_type_trans(skb, dev);
2819                 napi_gro_receive(&np->napi, skb);
2820                 u64_stats_update_begin(&np->swstats_rx_syncp);
2821                 np->stat_rx_packets++;
2822                 np->stat_rx_bytes += len;
2823                 u64_stats_update_end(&np->swstats_rx_syncp);
2824 next_pkt:
2825                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2826                         np->get_rx.orig = np->first_rx.orig;
2827                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2828                         np->get_rx_ctx = np->first_rx_ctx;
2829
2830                 rx_work++;
2831         }
2832
2833         return rx_work;
2834 }
2835
2836 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2837 {
2838         struct fe_priv *np = netdev_priv(dev);
2839         u32 flags;
2840         u32 vlanflags = 0;
2841         int rx_work = 0;
2842         struct sk_buff *skb;
2843         int len;
2844
2845         while ((np->get_rx.ex != np->put_rx.ex) &&
2846               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2847               (rx_work < limit)) {
2848
2849                 /*
2850                  * the packet is for us - immediately tear down the pci mapping.
2851                  * TODO: check if a prefetch of the first cacheline improves
2852                  * the performance.
2853                  */
2854                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2855                                 np->get_rx_ctx->dma_len,
2856                                 PCI_DMA_FROMDEVICE);
2857                 skb = np->get_rx_ctx->skb;
2858                 np->get_rx_ctx->skb = NULL;
2859
2860                 /* look at what we actually got: */
2861                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2862                         len = flags & LEN_MASK_V2;
2863                         if (unlikely(flags & NV_RX2_ERROR)) {
2864                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2865                                         len = nv_getlen(dev, skb->data, len);
2866                                         if (len < 0) {
2867                                                 dev_kfree_skb(skb);
2868                                                 goto next_pkt;
2869                                         }
2870                                 }
2871                                 /* framing errors are soft errors */
2872                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2873                                         if (flags & NV_RX2_SUBSTRACT1)
2874                                                 len--;
2875                                 }
2876                                 /* the rest are hard errors */
2877                                 else {
2878                                         dev_kfree_skb(skb);
2879                                         goto next_pkt;
2880                                 }
2881                         }
2882
2883                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2884                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2885                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2886
2887                         /* got a valid packet - forward it to the network core */
2888                         skb_put(skb, len);
2889                         skb->protocol = eth_type_trans(skb, dev);
2890                         prefetch(skb->data);
2891
2892                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2893
2894                         /*
2895                          * There's need to check for NETIF_F_HW_VLAN_RX here.
2896                          * Even if vlan rx accel is disabled,
2897                          * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2898                          */
2899                         if (dev->features & NETIF_F_HW_VLAN_RX &&
2900                             vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2901                                 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2902
2903                                 __vlan_hwaccel_put_tag(skb, vid);
2904                         }
2905                         napi_gro_receive(&np->napi, skb);
2906                         u64_stats_update_begin(&np->swstats_rx_syncp);
2907                         np->stat_rx_packets++;
2908                         np->stat_rx_bytes += len;
2909                         u64_stats_update_end(&np->swstats_rx_syncp);
2910                 } else {
2911                         dev_kfree_skb(skb);
2912                 }
2913 next_pkt:
2914                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2915                         np->get_rx.ex = np->first_rx.ex;
2916                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2917                         np->get_rx_ctx = np->first_rx_ctx;
2918
2919                 rx_work++;
2920         }
2921
2922         return rx_work;
2923 }
2924
2925 static void set_bufsize(struct net_device *dev)
2926 {
2927         struct fe_priv *np = netdev_priv(dev);
2928
2929         if (dev->mtu <= ETH_DATA_LEN)
2930                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2931         else
2932                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2933 }
2934
2935 /*
2936  * nv_change_mtu: dev->change_mtu function
2937  * Called with dev_base_lock held for read.
2938  */
2939 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2940 {
2941         struct fe_priv *np = netdev_priv(dev);
2942         int old_mtu;
2943
2944         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2945                 return -EINVAL;
2946
2947         old_mtu = dev->mtu;
2948         dev->mtu = new_mtu;
2949
2950         /* return early if the buffer sizes will not change */
2951         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2952                 return 0;
2953         if (old_mtu == new_mtu)
2954                 return 0;
2955
2956         /* synchronized against open : rtnl_lock() held by caller */
2957         if (netif_running(dev)) {
2958                 u8 __iomem *base = get_hwbase(dev);
2959                 /*
2960                  * It seems that the nic preloads valid ring entries into an
2961                  * internal buffer. The procedure for flushing everything is
2962                  * guessed, there is probably a simpler approach.
2963                  * Changing the MTU is a rare event, it shouldn't matter.
2964                  */
2965                 nv_disable_irq(dev);
2966                 nv_napi_disable(dev);
2967                 netif_tx_lock_bh(dev);
2968                 netif_addr_lock(dev);
2969                 spin_lock(&np->lock);
2970                 /* stop engines */
2971                 nv_stop_rxtx(dev);
2972                 nv_txrx_reset(dev);
2973                 /* drain rx queue */
2974                 nv_drain_rxtx(dev);
2975                 /* reinit driver view of the rx queue */
2976                 set_bufsize(dev);
2977                 if (nv_init_ring(dev)) {
2978                         if (!np->in_shutdown)
2979                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2980                 }
2981                 /* reinit nic view of the rx queue */
2982                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2983                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2984                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2985                         base + NvRegRingSizes);
2986                 pci_push(base);
2987                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2988                 pci_push(base);
2989
2990                 /* restart rx engine */
2991                 nv_start_rxtx(dev);
2992                 spin_unlock(&np->lock);
2993                 netif_addr_unlock(dev);
2994                 netif_tx_unlock_bh(dev);
2995                 nv_napi_enable(dev);
2996                 nv_enable_irq(dev);
2997         }
2998         return 0;
2999 }
3000
3001 static void nv_copy_mac_to_hw(struct net_device *dev)
3002 {
3003         u8 __iomem *base = get_hwbase(dev);
3004         u32 mac[2];
3005
3006         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3007                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3008         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3009
3010         writel(mac[0], base + NvRegMacAddrA);
3011         writel(mac[1], base + NvRegMacAddrB);
3012 }
3013
3014 /*
3015  * nv_set_mac_address: dev->set_mac_address function
3016  * Called with rtnl_lock() held.
3017  */
3018 static int nv_set_mac_address(struct net_device *dev, void *addr)
3019 {
3020         struct fe_priv *np = netdev_priv(dev);
3021         struct sockaddr *macaddr = (struct sockaddr *)addr;
3022
3023         if (!is_valid_ether_addr(macaddr->sa_data))
3024                 return -EADDRNOTAVAIL;
3025
3026         /* synchronized against open : rtnl_lock() held by caller */
3027         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3028         dev->addr_assign_type &= ~NET_ADDR_RANDOM;
3029
3030         if (netif_running(dev)) {
3031                 netif_tx_lock_bh(dev);
3032                 netif_addr_lock(dev);
3033                 spin_lock_irq(&np->lock);
3034
3035                 /* stop rx engine */
3036                 nv_stop_rx(dev);
3037
3038                 /* set mac address */
3039                 nv_copy_mac_to_hw(dev);
3040
3041                 /* restart rx engine */
3042                 nv_start_rx(dev);
3043                 spin_unlock_irq(&np->lock);
3044                 netif_addr_unlock(dev);
3045                 netif_tx_unlock_bh(dev);
3046         } else {
3047                 nv_copy_mac_to_hw(dev);
3048         }
3049         return 0;
3050 }
3051
3052 /*
3053  * nv_set_multicast: dev->set_multicast function
3054  * Called with netif_tx_lock held.
3055  */
3056 static void nv_set_multicast(struct net_device *dev)
3057 {
3058         struct fe_priv *np = netdev_priv(dev);
3059         u8 __iomem *base = get_hwbase(dev);
3060         u32 addr[2];
3061         u32 mask[2];
3062         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3063
3064         memset(addr, 0, sizeof(addr));
3065         memset(mask, 0, sizeof(mask));
3066
3067         if (dev->flags & IFF_PROMISC) {
3068                 pff |= NVREG_PFF_PROMISC;
3069         } else {
3070                 pff |= NVREG_PFF_MYADDR;
3071
3072                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3073                         u32 alwaysOff[2];
3074                         u32 alwaysOn[2];
3075
3076                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3077                         if (dev->flags & IFF_ALLMULTI) {
3078                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3079                         } else {
3080                                 struct netdev_hw_addr *ha;
3081
3082                                 netdev_for_each_mc_addr(ha, dev) {
3083                                         unsigned char *hw_addr = ha->addr;
3084                                         u32 a, b;
3085
3086                                         a = le32_to_cpu(*(__le32 *) hw_addr);
3087                                         b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3088                                         alwaysOn[0] &= a;
3089                                         alwaysOff[0] &= ~a;
3090                                         alwaysOn[1] &= b;
3091                                         alwaysOff[1] &= ~b;
3092                                 }
3093                         }
3094                         addr[0] = alwaysOn[0];
3095                         addr[1] = alwaysOn[1];
3096                         mask[0] = alwaysOn[0] | alwaysOff[0];
3097                         mask[1] = alwaysOn[1] | alwaysOff[1];
3098                 } else {
3099                         mask[0] = NVREG_MCASTMASKA_NONE;
3100                         mask[1] = NVREG_MCASTMASKB_NONE;
3101                 }
3102         }
3103         addr[0] |= NVREG_MCASTADDRA_FORCE;
3104         pff |= NVREG_PFF_ALWAYS;
3105         spin_lock_irq(&np->lock);
3106         nv_stop_rx(dev);
3107         writel(addr[0], base + NvRegMulticastAddrA);
3108         writel(addr[1], base + NvRegMulticastAddrB);
3109         writel(mask[0], base + NvRegMulticastMaskA);
3110         writel(mask[1], base + NvRegMulticastMaskB);
3111         writel(pff, base + NvRegPacketFilterFlags);
3112         nv_start_rx(dev);
3113         spin_unlock_irq(&np->lock);
3114 }
3115
3116 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3117 {
3118         struct fe_priv *np = netdev_priv(dev);
3119         u8 __iomem *base = get_hwbase(dev);
3120
3121         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3122
3123         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3124                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3125                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3126                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3127                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3128                 } else {
3129                         writel(pff, base + NvRegPacketFilterFlags);
3130                 }
3131         }
3132         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3133                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3134                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3135                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3136                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3137                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3138                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3139                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3140                                 /* limit the number of tx pause frames to a default of 8 */
3141                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3142                         }
3143                         writel(pause_enable,  base + NvRegTxPauseFrame);
3144                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3145                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3146                 } else {
3147                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3148                         writel(regmisc, base + NvRegMisc1);
3149                 }
3150         }
3151 }
3152
3153 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3154 {
3155         struct fe_priv *np = netdev_priv(dev);
3156         u8 __iomem *base = get_hwbase(dev);
3157         u32 phyreg, txreg;
3158         int mii_status;
3159
3160         np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3161         np->duplex = duplex;
3162
3163         /* see if gigabit phy */
3164         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3165         if (mii_status & PHY_GIGABIT) {
3166                 np->gigabit = PHY_GIGABIT;
3167                 phyreg = readl(base + NvRegSlotTime);
3168                 phyreg &= ~(0x3FF00);
3169                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3170                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3171                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3172                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3173                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3174                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3175                 writel(phyreg, base + NvRegSlotTime);
3176         }
3177
3178         phyreg = readl(base + NvRegPhyInterface);
3179         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3180         if (np->duplex == 0)
3181                 phyreg |= PHY_HALF;
3182         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3183                 phyreg |= PHY_100;
3184         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3185                                                         NVREG_LINKSPEED_1000)
3186                 phyreg |= PHY_1000;
3187         writel(phyreg, base + NvRegPhyInterface);
3188
3189         if (phyreg & PHY_RGMII) {
3190                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3191                                                         NVREG_LINKSPEED_1000)
3192                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3193                 else
3194                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3195         } else {
3196                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3197         }
3198         writel(txreg, base + NvRegTxDeferral);
3199
3200         if (np->desc_ver == DESC_VER_1) {
3201                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3202         } else {
3203                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3204                                          NVREG_LINKSPEED_1000)
3205                         txreg = NVREG_TX_WM_DESC2_3_1000;
3206                 else
3207                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3208         }
3209         writel(txreg, base + NvRegTxWatermark);
3210
3211         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3212                         base + NvRegMisc1);
3213         pci_push(base);
3214         writel(np->linkspeed, base + NvRegLinkSpeed);
3215         pci_push(base);
3216
3217         return;
3218 }
3219
3220 /**
3221  * nv_update_linkspeed - Setup the MAC according to the link partner
3222  * @dev: Network device to be configured
3223  *
3224  * The function queries the PHY and checks if there is a link partner.
3225  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3226  * set to 10 MBit HD.
3227  *
3228  * The function returns 0 if there is no link partner and 1 if there is
3229  * a good link partner.
3230  */
3231 static int nv_update_linkspeed(struct net_device *dev)
3232 {
3233         struct fe_priv *np = netdev_priv(dev);
3234         u8 __iomem *base = get_hwbase(dev);
3235         int adv = 0;
3236         int lpa = 0;
3237         int adv_lpa, adv_pause, lpa_pause;
3238         int newls = np->linkspeed;
3239         int newdup = np->duplex;
3240         int mii_status;
3241         u32 bmcr;
3242         int retval = 0;
3243         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3244         u32 txrxFlags = 0;
3245         u32 phy_exp;
3246
3247         /* If device loopback is enabled, set carrier on and enable max link
3248          * speed.
3249          */
3250         bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3251         if (bmcr & BMCR_LOOPBACK) {
3252                 if (netif_running(dev)) {
3253                         nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3254                         if (!netif_carrier_ok(dev))
3255                                 netif_carrier_on(dev);
3256                 }
3257                 return 1;
3258         }
3259
3260         /* BMSR_LSTATUS is latched, read it twice:
3261          * we want the current value.
3262          */
3263         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3264         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3265
3266         if (!(mii_status & BMSR_LSTATUS)) {
3267                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3268                 newdup = 0;
3269                 retval = 0;
3270                 goto set_speed;
3271         }
3272
3273         if (np->autoneg == 0) {
3274                 if (np->fixed_mode & LPA_100FULL) {
3275                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3276                         newdup = 1;
3277                 } else if (np->fixed_mode & LPA_100HALF) {
3278                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3279                         newdup = 0;
3280                 } else if (np->fixed_mode & LPA_10FULL) {
3281                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3282                         newdup = 1;
3283                 } else {
3284                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3285                         newdup = 0;
3286                 }
3287                 retval = 1;
3288                 goto set_speed;
3289         }
3290         /* check auto negotiation is complete */
3291         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3292                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3293                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3294                 newdup = 0;
3295                 retval = 0;
3296                 goto set_speed;
3297         }
3298
3299         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3300         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3301
3302         retval = 1;
3303         if (np->gigabit == PHY_GIGABIT) {
3304                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3305                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3306
3307                 if ((control_1000 & ADVERTISE_1000FULL) &&
3308                         (status_1000 & LPA_1000FULL)) {
3309                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3310                         newdup = 1;
3311                         goto set_speed;
3312                 }
3313         }
3314
3315         /* FIXME: handle parallel detection properly */
3316         adv_lpa = lpa & adv;
3317         if (adv_lpa & LPA_100FULL) {
3318                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3319                 newdup = 1;
3320         } else if (adv_lpa & LPA_100HALF) {
3321                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3322                 newdup = 0;
3323         } else if (adv_lpa & LPA_10FULL) {
3324                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3325                 newdup = 1;
3326         } else if (adv_lpa & LPA_10HALF) {
3327                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3328                 newdup = 0;
3329         } else {
3330                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3331                 newdup = 0;
3332         }
3333
3334 set_speed:
3335         if (np->duplex == newdup && np->linkspeed == newls)
3336                 return retval;
3337
3338         np->duplex = newdup;
3339         np->linkspeed = newls;
3340
3341         /* The transmitter and receiver must be restarted for safe update */
3342         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3343                 txrxFlags |= NV_RESTART_TX;
3344                 nv_stop_tx(dev);
3345         }
3346         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3347                 txrxFlags |= NV_RESTART_RX;
3348                 nv_stop_rx(dev);
3349         }
3350
3351         if (np->gigabit == PHY_GIGABIT) {
3352                 phyreg = readl(base + NvRegSlotTime);
3353                 phyreg &= ~(0x3FF00);
3354                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3355                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3356                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3357                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3358                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3359                 writel(phyreg, base + NvRegSlotTime);
3360         }
3361
3362         phyreg = readl(base + NvRegPhyInterface);
3363         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3364         if (np->duplex == 0)
3365                 phyreg |= PHY_HALF;
3366         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3367                 phyreg |= PHY_100;
3368         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3369                 phyreg |= PHY_1000;
3370         writel(phyreg, base + NvRegPhyInterface);
3371
3372         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3373         if (phyreg & PHY_RGMII) {
3374                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3375                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3376                 } else {
3377                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3378                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3379                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3380                                 else
3381                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3382                         } else {
3383                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3384                         }
3385                 }
3386         } else {
3387                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3388                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3389                 else
3390                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3391         }
3392         writel(txreg, base + NvRegTxDeferral);
3393
3394         if (np->desc_ver == DESC_VER_1) {
3395                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3396         } else {
3397                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3398                         txreg = NVREG_TX_WM_DESC2_3_1000;
3399                 else
3400                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3401         }
3402         writel(txreg, base + NvRegTxWatermark);
3403
3404         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3405                 base + NvRegMisc1);
3406         pci_push(base);
3407         writel(np->linkspeed, base + NvRegLinkSpeed);
3408         pci_push(base);
3409
3410         pause_flags = 0;
3411         /* setup pause frame */
3412         if (netif_running(dev) && (np->duplex != 0)) {
3413                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3414                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3415                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3416
3417                         switch (adv_pause) {
3418                         case ADVERTISE_PAUSE_CAP:
3419                                 if (lpa_pause & LPA_PAUSE_CAP) {
3420                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3421                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3422                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3423                                 }
3424                                 break;
3425                         case ADVERTISE_PAUSE_ASYM:
3426                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3427                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3428                                 break;
3429                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3430                                 if (lpa_pause & LPA_PAUSE_CAP) {
3431                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3432                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3433                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3434                                 }
3435                                 if (lpa_pause == LPA_PAUSE_ASYM)
3436                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3437                                 break;
3438                         }
3439                 } else {
3440                         pause_flags = np->pause_flags;
3441                 }
3442         }
3443         nv_update_pause(dev, pause_flags);
3444
3445         if (txrxFlags & NV_RESTART_TX)
3446                 nv_start_tx(dev);
3447         if (txrxFlags & NV_RESTART_RX)
3448                 nv_start_rx(dev);
3449
3450         return retval;
3451 }
3452
3453 static void nv_linkchange(struct net_device *dev)
3454 {
3455         if (nv_update_linkspeed(dev)) {
3456                 if (!netif_carrier_ok(dev)) {
3457                         netif_carrier_on(dev);
3458                         netdev_info(dev, "link up\n");
3459                         nv_txrx_gate(dev, false);
3460                         nv_start_rx(dev);
3461                 }
3462         } else {
3463                 if (netif_carrier_ok(dev)) {
3464                         netif_carrier_off(dev);
3465                         netdev_info(dev, "link down\n");
3466                         nv_txrx_gate(dev, true);
3467                         nv_stop_rx(dev);
3468                 }
3469         }
3470 }
3471
3472 static void nv_link_irq(struct net_device *dev)
3473 {
3474         u8 __iomem *base = get_hwbase(dev);
3475         u32 miistat;
3476
3477         miistat = readl(base + NvRegMIIStatus);
3478         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3479
3480         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3481                 nv_linkchange(dev);
3482 }
3483
3484 static void nv_msi_workaround(struct fe_priv *np)
3485 {
3486
3487         /* Need to toggle the msi irq mask within the ethernet device,
3488          * otherwise, future interrupts will not be detected.
3489          */
3490         if (np->msi_flags & NV_MSI_ENABLED) {
3491                 u8 __iomem *base = np->base;
3492
3493                 writel(0, base + NvRegMSIIrqMask);
3494                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3495         }
3496 }
3497
3498 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3499 {
3500         struct fe_priv *np = netdev_priv(dev);
3501
3502         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3503                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3504                         /* transition to poll based interrupts */
3505                         np->quiet_count = 0;
3506                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3507                                 np->irqmask = NVREG_IRQMASK_CPU;
3508                                 return 1;
3509                         }
3510                 } else {
3511                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3512                                 np->quiet_count++;
3513                         } else {
3514                                 /* reached a period of low activity, switch
3515                                    to per tx/rx packet interrupts */
3516                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3517                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3518                                         return 1;
3519                                 }
3520                         }
3521                 }
3522         }
3523         return 0;
3524 }
3525
3526 static irqreturn_t nv_nic_irq(int foo, void *data)
3527 {
3528         struct net_device *dev = (struct net_device *) data;
3529         struct fe_priv *np = netdev_priv(dev);
3530         u8 __iomem *base = get_hwbase(dev);
3531
3532         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3533                 np->events = readl(base + NvRegIrqStatus);
3534                 writel(np->events, base + NvRegIrqStatus);
3535         } else {
3536                 np->events = readl(base + NvRegMSIXIrqStatus);
3537                 writel(np->events, base + NvRegMSIXIrqStatus);
3538         }
3539         if (!(np->events & np->irqmask))
3540                 return IRQ_NONE;
3541
3542         nv_msi_workaround(np);
3543
3544         if (napi_schedule_prep(&np->napi)) {
3545                 /*
3546                  * Disable further irq's (msix not enabled with napi)
3547                  */
3548                 writel(0, base + NvRegIrqMask);
3549                 __napi_schedule(&np->napi);
3550         }
3551
3552         return IRQ_HANDLED;
3553 }
3554
3555 /* All _optimized functions are used to help increase performance
3556  * (reduce CPU and increase throughput). They use descripter version 3,
3557  * compiler directives, and reduce memory accesses.
3558  */
3559 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3560 {
3561         struct net_device *dev = (struct net_device *) data;
3562         struct fe_priv *np = netdev_priv(dev);
3563         u8 __iomem *base = get_hwbase(dev);
3564
3565         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3566                 np->events = readl(base + NvRegIrqStatus);
3567                 writel(np->events, base + NvRegIrqStatus);
3568         } else {
3569                 np->events = readl(base + NvRegMSIXIrqStatus);
3570                 writel(np->events, base + NvRegMSIXIrqStatus);
3571         }
3572         if (!(np->events & np->irqmask))
3573                 return IRQ_NONE;
3574
3575         nv_msi_workaround(np);
3576
3577         if (napi_schedule_prep(&np->napi)) {
3578                 /*
3579                  * Disable further irq's (msix not enabled with napi)
3580                  */
3581                 writel(0, base + NvRegIrqMask);
3582                 __napi_schedule(&np->napi);
3583         }
3584
3585         return IRQ_HANDLED;
3586 }
3587
3588 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3589 {
3590         struct net_device *dev = (struct net_device *) data;
3591         struct fe_priv *np = netdev_priv(dev);
3592         u8 __iomem *base = get_hwbase(dev);
3593         u32 events;
3594         int i;
3595         unsigned long flags;
3596
3597         for (i = 0;; i++) {
3598                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3599                 writel(events, base + NvRegMSIXIrqStatus);
3600                 netdev_dbg(dev, "tx irq events: %08x\n", events);
3601                 if (!(events & np->irqmask))
3602                         break;
3603
3604                 spin_lock_irqsave(&np->lock, flags);
3605                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3606                 spin_unlock_irqrestore(&np->lock, flags);
3607
3608                 if (unlikely(i > max_interrupt_work)) {
3609                         spin_lock_irqsave(&np->lock, flags);
3610                         /* disable interrupts on the nic */
3611                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3612                         pci_push(base);
3613
3614                         if (!np->in_shutdown) {
3615                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3616                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3617                         }
3618                         spin_unlock_irqrestore(&np->lock, flags);
3619                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3620                                    __func__, i);
3621                         break;
3622                 }
3623
3624         }
3625
3626         return IRQ_RETVAL(i);
3627 }
3628
3629 static int nv_napi_poll(struct napi_struct *napi, int budget)
3630 {
3631         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3632         struct net_device *dev = np->dev;
3633         u8 __iomem *base = get_hwbase(dev);
3634         unsigned long flags;
3635         int retcode;
3636         int rx_count, tx_work = 0, rx_work = 0;
3637
3638         do {
3639                 if (!nv_optimized(np)) {
3640                         spin_lock_irqsave(&np->lock, flags);
3641                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3642                         spin_unlock_irqrestore(&np->lock, flags);
3643
3644                         rx_count = nv_rx_process(dev, budget - rx_work);
3645                         retcode = nv_alloc_rx(dev);
3646                 } else {
3647                         spin_lock_irqsave(&np->lock, flags);
3648                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3649                         spin_unlock_irqrestore(&np->lock, flags);
3650
3651                         rx_count = nv_rx_process_optimized(dev,
3652                             budget - rx_work);
3653                         retcode = nv_alloc_rx_optimized(dev);
3654                 }
3655         } while (retcode == 0 &&
3656                  rx_count > 0 && (rx_work += rx_count) < budget);
3657
3658         if (retcode) {
3659                 spin_lock_irqsave(&np->lock, flags);
3660                 if (!np->in_shutdown)
3661                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3662                 spin_unlock_irqrestore(&np->lock, flags);
3663         }
3664
3665         nv_change_interrupt_mode(dev, tx_work + rx_work);
3666
3667         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3668                 spin_lock_irqsave(&np->lock, flags);
3669                 nv_link_irq(dev);
3670                 spin_unlock_irqrestore(&np->lock, flags);
3671         }
3672         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3673                 spin_lock_irqsave(&np->lock, flags);
3674                 nv_linkchange(dev);
3675                 spin_unlock_irqrestore(&np->lock, flags);
3676                 np->link_timeout = jiffies + LINK_TIMEOUT;
3677         }
3678         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3679                 spin_lock_irqsave(&np->lock, flags);
3680                 if (!np->in_shutdown) {
3681                         np->nic_poll_irq = np->irqmask;
3682                         np->recover_error = 1;
3683                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3684                 }
3685                 spin_unlock_irqrestore(&np->lock, flags);
3686                 napi_complete(napi);
3687                 return rx_work;
3688         }
3689
3690         if (rx_work < budget) {
3691                 /* re-enable interrupts
3692                    (msix not enabled in napi) */
3693                 napi_complete(napi);
3694
3695                 writel(np->irqmask, base + NvRegIrqMask);
3696         }
3697         return rx_work;
3698 }
3699
3700 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3701 {
3702         struct net_device *dev = (struct net_device *) data;
3703         struct fe_priv *np = netdev_priv(dev);
3704         u8 __iomem *base = get_hwbase(dev);
3705         u32 events;
3706         int i;
3707         unsigned long flags;
3708
3709         for (i = 0;; i++) {
3710                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3711                 writel(events, base + NvRegMSIXIrqStatus);
3712                 netdev_dbg(dev, "rx irq events: %08x\n", events);
3713                 if (!(events & np->irqmask))
3714                         break;
3715
3716                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3717                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3718                                 spin_lock_irqsave(&np->lock, flags);
3719                                 if (!np->in_shutdown)
3720                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3721                                 spin_unlock_irqrestore(&np->lock, flags);
3722                         }
3723                 }
3724
3725                 if (unlikely(i > max_interrupt_work)) {
3726                         spin_lock_irqsave(&np->lock, flags);
3727                         /* disable interrupts on the nic */
3728                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3729                         pci_push(base);
3730
3731                         if (!np->in_shutdown) {
3732                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3733                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3734                         }
3735                         spin_unlock_irqrestore(&np->lock, flags);
3736                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3737                                    __func__, i);
3738                         break;
3739                 }
3740         }
3741
3742         return IRQ_RETVAL(i);
3743 }
3744
3745 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3746 {
3747         struct net_device *dev = (struct net_device *) data;
3748         struct fe_priv *np = netdev_priv(dev);
3749         u8 __iomem *base = get_hwbase(dev);
3750         u32 events;
3751         int i;
3752         unsigned long flags;
3753
3754         for (i = 0;; i++) {
3755                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3756                 writel(events, base + NvRegMSIXIrqStatus);
3757                 netdev_dbg(dev, "irq events: %08x\n", events);
3758                 if (!(events & np->irqmask))
3759                         break;
3760
3761                 /* check tx in case we reached max loop limit in tx isr */
3762                 spin_lock_irqsave(&np->lock, flags);
3763                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3764                 spin_unlock_irqrestore(&np->lock, flags);
3765
3766                 if (events & NVREG_IRQ_LINK) {
3767                         spin_lock_irqsave(&np->lock, flags);
3768                         nv_link_irq(dev);
3769                         spin_unlock_irqrestore(&np->lock, flags);
3770                 }
3771                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3772                         spin_lock_irqsave(&np->lock, flags);
3773                         nv_linkchange(dev);
3774                         spin_unlock_irqrestore(&np->lock, flags);
3775                         np->link_timeout = jiffies + LINK_TIMEOUT;
3776                 }
3777                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3778                         spin_lock_irqsave(&np->lock, flags);
3779                         /* disable interrupts on the nic */
3780                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3781                         pci_push(base);
3782
3783                         if (!np->in_shutdown) {
3784                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3785                                 np->recover_error = 1;
3786                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3787                         }
3788                         spin_unlock_irqrestore(&np->lock, flags);
3789                         break;
3790                 }
3791                 if (unlikely(i > max_interrupt_work)) {
3792                         spin_lock_irqsave(&np->lock, flags);
3793                         /* disable interrupts on the nic */
3794                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3795                         pci_push(base);
3796
3797                         if (!np->in_shutdown) {
3798                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3799                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3800                         }
3801                         spin_unlock_irqrestore(&np->lock, flags);
3802                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3803                                    __func__, i);
3804                         break;
3805                 }
3806
3807         }
3808
3809         return IRQ_RETVAL(i);
3810 }
3811
3812 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3813 {
3814         struct net_device *dev = (struct net_device *) data;
3815         struct fe_priv *np = netdev_priv(dev);
3816         u8 __iomem *base = get_hwbase(dev);
3817         u32 events;
3818
3819         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3820                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3821                 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3822         } else {
3823                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3824                 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3825         }
3826         pci_push(base);
3827         if (!(events & NVREG_IRQ_TIMER))
3828                 return IRQ_RETVAL(0);
3829
3830         nv_msi_workaround(np);
3831
3832         spin_lock(&np->lock);
3833         np->intr_test = 1;
3834         spin_unlock(&np->lock);
3835
3836         return IRQ_RETVAL(1);
3837 }
3838
3839 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3840 {
3841         u8 __iomem *base = get_hwbase(dev);
3842         int i;
3843         u32 msixmap = 0;
3844
3845         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3846          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3847          * the remaining 8 interrupts.
3848          */
3849         for (i = 0; i < 8; i++) {
3850                 if ((irqmask >> i) & 0x1)
3851                         msixmap |= vector << (i << 2);
3852         }
3853         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3854
3855         msixmap = 0;
3856         for (i = 0; i < 8; i++) {
3857                 if ((irqmask >> (i + 8)) & 0x1)
3858                         msixmap |= vector << (i << 2);
3859         }
3860         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3861 }
3862
3863 static int nv_request_irq(struct net_device *dev, int intr_test)
3864 {
3865         struct fe_priv *np = get_nvpriv(dev);
3866         u8 __iomem *base = get_hwbase(dev);
3867         int ret = 1;
3868         int i;
3869         irqreturn_t (*handler)(int foo, void *data);
3870
3871         if (intr_test) {
3872                 handler = nv_nic_irq_test;
3873         } else {
3874                 if (nv_optimized(np))
3875                         handler = nv_nic_irq_optimized;
3876                 else
3877                         handler = nv_nic_irq;
3878         }
3879
3880         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3881                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3882                         np->msi_x_entry[i].entry = i;
3883                 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3884                 if (ret == 0) {
3885                         np->msi_flags |= NV_MSI_X_ENABLED;
3886                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3887                                 /* Request irq for rx handling */
3888                                 sprintf(np->name_rx, "%s-rx", dev->name);
3889                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3890                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3891                                         netdev_info(dev,
3892                                                     "request_irq failed for rx %d\n",
3893                                                     ret);
3894                                         pci_disable_msix(np->pci_dev);
3895                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3896                                         goto out_err;
3897                                 }
3898                                 /* Request irq for tx handling */
3899                                 sprintf(np->name_tx, "%s-tx", dev->name);
3900                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3901                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3902                                         netdev_info(dev,
3903                                                     "request_irq failed for tx %d\n",
3904                                                     ret);
3905                                         pci_disable_msix(np->pci_dev);
3906                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3907                                         goto out_free_rx;
3908                                 }
3909                                 /* Request irq for link and timer handling */
3910                                 sprintf(np->name_other, "%s-other", dev->name);
3911                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3912                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3913                                         netdev_info(dev,
3914                                                     "request_irq failed for link %d\n",
3915                                                     ret);
3916                                         pci_disable_msix(np->pci_dev);
3917                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3918                                         goto out_free_tx;
3919                                 }
3920                                 /* map interrupts to their respective vector */
3921                                 writel(0, base + NvRegMSIXMap0);
3922                                 writel(0, base + NvRegMSIXMap1);
3923                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3924                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3925                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3926                         } else {
3927                                 /* Request irq for all interrupts */
3928                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3929                                         netdev_info(dev,
3930                                                     "request_irq failed %d\n",
3931                                                     ret);
3932                                         pci_disable_msix(np->pci_dev);
3933                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3934                                         goto out_err;
3935                                 }
3936
3937                                 /* map interrupts to vector 0 */
3938                                 writel(0, base + NvRegMSIXMap0);
3939                                 writel(0, base + NvRegMSIXMap1);
3940                         }
3941                         netdev_info(dev, "MSI-X enabled\n");
3942                 }
3943         }
3944         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3945                 ret = pci_enable_msi(np->pci_dev);
3946                 if (ret == 0) {
3947                         np->msi_flags |= NV_MSI_ENABLED;
3948                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3949                                 netdev_info(dev, "request_irq failed %d\n",
3950                                             ret);
3951                                 pci_disable_msi(np->pci_dev);
3952                                 np->msi_flags &= ~NV_MSI_ENABLED;
3953                                 goto out_err;
3954                         }
3955
3956                         /* map interrupts to vector 0 */
3957                         writel(0, base + NvRegMSIMap0);
3958                         writel(0, base + NvRegMSIMap1);
3959                         /* enable msi vector 0 */
3960                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3961                         netdev_info(dev, "MSI enabled\n");
3962                 }
3963         }
3964         if (ret != 0) {
3965                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3966                         goto out_err;
3967
3968         }
3969
3970         return 0;
3971 out_free_tx:
3972         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3973 out_free_rx:
3974         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3975 out_err:
3976         return 1;
3977 }
3978
3979 static void nv_free_irq(struct net_device *dev)
3980 {
3981         struct fe_priv *np = get_nvpriv(dev);
3982         int i;
3983
3984         if (np->msi_flags & NV_MSI_X_ENABLED) {
3985                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3986                         free_irq(np->msi_x_entry[i].vector, dev);
3987                 pci_disable_msix(np->pci_dev);
3988                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3989         } else {
3990                 free_irq(np->pci_dev->irq, dev);
3991                 if (np->msi_flags & NV_MSI_ENABLED) {
3992                         pci_disable_msi(np->pci_dev);
3993                         np->msi_flags &= ~NV_MSI_ENABLED;
3994                 }
3995         }
3996 }
3997
3998 static void nv_do_nic_poll(unsigned long data)
3999 {
4000         struct net_device *dev = (struct net_device *) data;
4001         struct fe_priv *np = netdev_priv(dev);
4002         u8 __iomem *base = get_hwbase(dev);
4003         u32 mask = 0;
4004
4005         /*
4006          * First disable irq(s) and then
4007          * reenable interrupts on the nic, we have to do this before calling
4008          * nv_nic_irq because that may decide to do otherwise
4009          */
4010
4011         if (!using_multi_irqs(dev)) {
4012                 if (np->msi_flags & NV_MSI_X_ENABLED)
4013                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4014                 else
4015                         disable_irq_lockdep(np->pci_dev->irq);
4016                 mask = np->irqmask;
4017         } else {
4018                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4019                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4020                         mask |= NVREG_IRQ_RX_ALL;
4021                 }
4022                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4023                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4024                         mask |= NVREG_IRQ_TX_ALL;
4025                 }
4026                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4027                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4028                         mask |= NVREG_IRQ_OTHER;
4029                 }
4030         }
4031         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4032
4033         if (np->recover_error) {
4034                 np->recover_error = 0;
4035                 netdev_info(dev, "MAC in recoverable error state\n");
4036                 if (netif_running(dev)) {
4037                         netif_tx_lock_bh(dev);
4038                         netif_addr_lock(dev);
4039                         spin_lock(&np->lock);
4040                         /* stop engines */
4041                         nv_stop_rxtx(dev);
4042                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4043                                 nv_mac_reset(dev);
4044                         nv_txrx_reset(dev);
4045                         /* drain rx queue */
4046                         nv_drain_rxtx(dev);
4047                         /* reinit driver view of the rx queue */
4048                         set_bufsize(dev);
4049                         if (nv_init_ring(dev)) {
4050                                 if (!np->in_shutdown)
4051                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4052                         }
4053                         /* reinit nic view of the rx queue */
4054                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4055                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4056                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4057                                 base + NvRegRingSizes);
4058                         pci_push(base);
4059                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4060                         pci_push(base);
4061                         /* clear interrupts */
4062                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4063                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4064                         else
4065                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4066
4067                         /* restart rx engine */
4068                         nv_start_rxtx(dev);
4069                         spin_unlock(&np->lock);
4070                         netif_addr_unlock(dev);
4071                         netif_tx_unlock_bh(dev);
4072                 }
4073         }
4074
4075         writel(mask, base + NvRegIrqMask);
4076         pci_push(base);
4077
4078         if (!using_multi_irqs(dev)) {
4079                 np->nic_poll_irq = 0;
4080                 if (nv_optimized(np))
4081                         nv_nic_irq_optimized(0, dev);
4082                 else
4083                         nv_nic_irq(0, dev);
4084                 if (np->msi_flags & NV_MSI_X_ENABLED)
4085                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4086                 else
4087                         enable_irq_lockdep(np->pci_dev->irq);
4088         } else {
4089                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4090                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4091                         nv_nic_irq_rx(0, dev);
4092                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4093                 }
4094                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4095                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4096                         nv_nic_irq_tx(0, dev);
4097                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4098                 }
4099                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4100                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4101                         nv_nic_irq_other(0, dev);
4102                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4103                 }
4104         }
4105
4106 }
4107
4108 #ifdef CONFIG_NET_POLL_CONTROLLER
4109 static void nv_poll_controller(struct net_device *dev)
4110 {
4111         nv_do_nic_poll((unsigned long) dev);
4112 }
4113 #endif
4114
4115 static void nv_do_stats_poll(unsigned long data)
4116         __acquires(&netdev_priv(dev)->hwstats_lock)
4117         __releases(&netdev_priv(dev)->hwstats_lock)
4118 {
4119         struct net_device *dev = (struct net_device *) data;
4120         struct fe_priv *np = netdev_priv(dev);
4121
4122         /* If lock is currently taken, the stats are being refreshed
4123          * and hence fresh enough */
4124         if (spin_trylock(&np->hwstats_lock)) {
4125                 nv_update_stats(dev);
4126                 spin_unlock(&np->hwstats_lock);
4127         }
4128
4129         if (!np->in_shutdown)
4130                 mod_timer(&np->stats_poll,
4131                         round_jiffies(jiffies + STATS_INTERVAL));
4132 }
4133
4134 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4135 {
4136         struct fe_priv *np = netdev_priv(dev);
4137         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4138         strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4139         strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4140 }
4141
4142 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4143 {
4144         struct fe_priv *np = netdev_priv(dev);
4145         wolinfo->supported = WAKE_MAGIC;
4146
4147         spin_lock_irq(&np->lock);
4148         if (np->wolenabled)
4149                 wolinfo->wolopts = WAKE_MAGIC;
4150         spin_unlock_irq(&np->lock);
4151 }
4152
4153 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4154 {
4155         struct fe_priv *np = netdev_priv(dev);
4156         u8 __iomem *base = get_hwbase(dev);
4157         u32 flags = 0;
4158
4159         if (wolinfo->wolopts == 0) {
4160                 np->wolenabled = 0;
4161         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4162                 np->wolenabled = 1;
4163                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4164         }
4165         if (netif_running(dev)) {
4166                 spin_lock_irq(&np->lock);
4167                 writel(flags, base + NvRegWakeUpFlags);
4168                 spin_unlock_irq(&np->lock);
4169         }
4170         device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4171         return 0;
4172 }
4173
4174 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4175 {
4176         struct fe_priv *np = netdev_priv(dev);
4177         u32 speed;
4178         int adv;
4179
4180         spin_lock_irq(&np->lock);
4181         ecmd->port = PORT_MII;
4182         if (!netif_running(dev)) {
4183                 /* We do not track link speed / duplex setting if the
4184                  * interface is disabled. Force a link check */
4185                 if (nv_update_linkspeed(dev)) {
4186                         if (!netif_carrier_ok(dev))
4187                                 netif_carrier_on(dev);
4188                 } else {
4189                         if (netif_carrier_ok(dev))
4190                                 netif_carrier_off(dev);
4191                 }
4192         }
4193
4194         if (netif_carrier_ok(dev)) {
4195                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4196                 case NVREG_LINKSPEED_10:
4197                         speed = SPEED_10;
4198                         break;
4199                 case NVREG_LINKSPEED_100:
4200                         speed = SPEED_100;
4201                         break;
4202                 case NVREG_LINKSPEED_1000:
4203                         speed = SPEED_1000;
4204                         break;
4205                 default:
4206                         speed = -1;
4207                         break;
4208                 }
4209                 ecmd->duplex = DUPLEX_HALF;
4210                 if (np->duplex)
4211                         ecmd->duplex = DUPLEX_FULL;
4212         } else {
4213                 speed = -1;
4214                 ecmd->duplex = -1;
4215         }
4216         ethtool_cmd_speed_set(ecmd, speed);
4217         ecmd->autoneg = np->autoneg;
4218
4219         ecmd->advertising = ADVERTISED_MII;
4220         if (np->autoneg) {
4221                 ecmd->advertising |= ADVERTISED_Autoneg;
4222                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4223                 if (adv & ADVERTISE_10HALF)
4224                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4225                 if (adv & ADVERTISE_10FULL)
4226                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4227                 if (adv & ADVERTISE_100HALF)
4228                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4229                 if (adv & ADVERTISE_100FULL)
4230                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4231                 if (np->gigabit == PHY_GIGABIT) {
4232                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4233                         if (adv & ADVERTISE_1000FULL)
4234                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4235                 }
4236         }
4237         ecmd->supported = (SUPPORTED_Autoneg |
4238                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4239                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4240                 SUPPORTED_MII);
4241         if (np->gigabit == PHY_GIGABIT)
4242                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4243
4244         ecmd->phy_address = np->phyaddr;
4245         ecmd->transceiver = XCVR_EXTERNAL;
4246
4247         /* ignore maxtxpkt, maxrxpkt for now */
4248         spin_unlock_irq(&np->lock);
4249         return 0;
4250 }
4251
4252 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4253 {
4254         struct fe_priv *np = netdev_priv(dev);
4255         u32 speed = ethtool_cmd_speed(ecmd);
4256
4257         if (ecmd->port != PORT_MII)
4258                 return -EINVAL;
4259         if (ecmd->transceiver != XCVR_EXTERNAL)
4260                 return -EINVAL;
4261         if (ecmd->phy_address != np->phyaddr) {
4262                 /* TODO: support switching between multiple phys. Should be
4263                  * trivial, but not enabled due to lack of test hardware. */
4264                 return -EINVAL;
4265         }
4266         if (ecmd->autoneg == AUTONEG_ENABLE) {
4267                 u32 mask;
4268
4269                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4270                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4271                 if (np->gigabit == PHY_GIGABIT)
4272                         mask |= ADVERTISED_1000baseT_Full;
4273
4274                 if ((ecmd->advertising & mask) == 0)
4275                         return -EINVAL;
4276
4277         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4278                 /* Note: autonegotiation disable, speed 1000 intentionally
4279                  * forbidden - no one should need that. */
4280
4281                 if (speed != SPEED_10 && speed != SPEED_100)
4282                         return -EINVAL;
4283                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4284                         return -EINVAL;
4285         } else {
4286                 return -EINVAL;
4287         }
4288
4289         netif_carrier_off(dev);
4290         if (netif_running(dev)) {
4291                 unsigned long flags;
4292
4293                 nv_disable_irq(dev);
4294                 netif_tx_lock_bh(dev);
4295                 netif_addr_lock(dev);
4296                 /* with plain spinlock lockdep complains */
4297                 spin_lock_irqsave(&np->lock, flags);
4298                 /* stop engines */
4299                 /* FIXME:
4300                  * this can take some time, and interrupts are disabled
4301                  * due to spin_lock_irqsave, but let's hope no daemon
4302                  * is going to change the settings very often...
4303                  * Worst case:
4304                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4305                  * + some minor delays, which is up to a second approximately
4306                  */
4307                 nv_stop_rxtx(dev);
4308                 spin_unlock_irqrestore(&np->lock, flags);
4309                 netif_addr_unlock(dev);
4310                 netif_tx_unlock_bh(dev);
4311         }
4312
4313         if (ecmd->autoneg == AUTONEG_ENABLE) {
4314                 int adv, bmcr;
4315
4316                 np->autoneg = 1;
4317
4318                 /* advertise only what has been requested */
4319                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4320                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4321                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4322                         adv |= ADVERTISE_10HALF;
4323                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4324                         adv |= ADVERTISE_10FULL;
4325                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4326                         adv |= ADVERTISE_100HALF;
4327                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4328                         adv |= ADVERTISE_100FULL;
4329                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisements but disable tx pause */
4330                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4331                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4332                         adv |=  ADVERTISE_PAUSE_ASYM;
4333                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4334
4335                 if (np->gigabit == PHY_GIGABIT) {
4336                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4337                         adv &= ~ADVERTISE_1000FULL;
4338                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4339                                 adv |= ADVERTISE_1000FULL;
4340                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4341                 }
4342
4343                 if (netif_running(dev))
4344                         netdev_info(dev, "link down\n");
4345                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4346                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4347                         bmcr |= BMCR_ANENABLE;
4348                         /* reset the phy in order for settings to stick,
4349                          * and cause autoneg to start */
4350                         if (phy_reset(dev, bmcr)) {
4351                                 netdev_info(dev, "phy reset failed\n");
4352                                 return -EINVAL;
4353                         }
4354                 } else {
4355                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4356                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4357                 }
4358         } else {
4359                 int adv, bmcr;
4360
4361                 np->autoneg = 0;
4362
4363                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4364                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4365                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4366                         adv |= ADVERTISE_10HALF;
4367                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4368                         adv |= ADVERTISE_10FULL;
4369                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4370                         adv |= ADVERTISE_100HALF;
4371                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4372                         adv |= ADVERTISE_100FULL;
4373                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4374                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4375                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4376                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4377                 }
4378                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4379                         adv |=  ADVERTISE_PAUSE_ASYM;
4380                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4381                 }
4382                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4383                 np->fixed_mode = adv;
4384
4385                 if (np->gigabit == PHY_GIGABIT) {
4386                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4387                         adv &= ~ADVERTISE_1000FULL;
4388                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4389                 }
4390
4391                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4392                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4393                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4394                         bmcr |= BMCR_FULLDPLX;
4395                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4396                         bmcr |= BMCR_SPEED100;
4397                 if (np->phy_oui == PHY_OUI_MARVELL) {
4398                         /* reset the phy in order for forced mode settings to stick */
4399                         if (phy_reset(dev, bmcr)) {
4400                                 netdev_info(dev, "phy reset failed\n");
4401                                 return -EINVAL;
4402                         }
4403                 } else {
4404                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4405                         if (netif_running(dev)) {
4406                                 /* Wait a bit and then reconfigure the nic. */
4407                                 udelay(10);
4408                                 nv_linkchange(dev);
4409                         }
4410                 }
4411         }
4412
4413         if (netif_running(dev)) {
4414                 nv_start_rxtx(dev);
4415                 nv_enable_irq(dev);
4416         }
4417
4418         return 0;
4419 }
4420
4421 #define FORCEDETH_REGS_VER      1
4422
4423 static int nv_get_regs_len(struct net_device *dev)
4424 {
4425         struct fe_priv *np = netdev_priv(dev);
4426         return np->register_size;
4427 }
4428
4429 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4430 {
4431         struct fe_priv *np = netdev_priv(dev);
4432         u8 __iomem *base = get_hwbase(dev);
4433         u32 *rbuf = buf;
4434         int i;
4435
4436         regs->version = FORCEDETH_REGS_VER;
4437         spin_lock_irq(&np->lock);
4438         for (i = 0; i < np->register_size/sizeof(u32); i++)
4439                 rbuf[i] = readl(base + i*sizeof(u32));
4440         spin_unlock_irq(&np->lock);
4441 }
4442
4443 static int nv_nway_reset(struct net_device *dev)
4444 {
4445         struct fe_priv *np = netdev_priv(dev);
4446         int ret;
4447
4448         if (np->autoneg) {
4449                 int bmcr;
4450
4451                 netif_carrier_off(dev);
4452                 if (netif_running(dev)) {
4453                         nv_disable_irq(dev);
4454                         netif_tx_lock_bh(dev);
4455                         netif_addr_lock(dev);
4456                         spin_lock(&np->lock);
4457                         /* stop engines */
4458                         nv_stop_rxtx(dev);
4459                         spin_unlock(&np->lock);
4460                         netif_addr_unlock(dev);
4461                         netif_tx_unlock_bh(dev);
4462                         netdev_info(dev, "link down\n");
4463                 }
4464
4465                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4466                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4467                         bmcr |= BMCR_ANENABLE;
4468                         /* reset the phy in order for settings to stick*/
4469                         if (phy_reset(dev, bmcr)) {
4470                                 netdev_info(dev, "phy reset failed\n");
4471                                 return -EINVAL;
4472                         }
4473                 } else {
4474                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4475                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4476                 }
4477
4478                 if (netif_running(dev)) {
4479                         nv_start_rxtx(dev);
4480                         nv_enable_irq(dev);
4481                 }
4482                 ret = 0;
4483         } else {
4484                 ret = -EINVAL;
4485         }
4486
4487         return ret;
4488 }
4489
4490 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4491 {
4492         struct fe_priv *np = netdev_priv(dev);
4493
4494         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4495         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4496
4497         ring->rx_pending = np->rx_ring_size;
4498         ring->tx_pending = np->tx_ring_size;
4499 }
4500
4501 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4502 {
4503         struct fe_priv *np = netdev_priv(dev);
4504         u8 __iomem *base = get_hwbase(dev);
4505         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4506         dma_addr_t ring_addr;
4507
4508         if (ring->rx_pending < RX_RING_MIN ||
4509             ring->tx_pending < TX_RING_MIN ||
4510             ring->rx_mini_pending != 0 ||
4511             ring->rx_jumbo_pending != 0 ||
4512             (np->desc_ver == DESC_VER_1 &&
4513              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4514               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4515             (np->desc_ver != DESC_VER_1 &&
4516              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4517               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4518                 return -EINVAL;
4519         }
4520
4521         /* allocate new rings */
4522         if (!nv_optimized(np)) {
4523                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4524                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4525                                             &ring_addr);
4526         } else {
4527                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4528                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4529                                             &ring_addr);
4530         }
4531         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4532         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4533         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4534                 /* fall back to old rings */
4535                 if (!nv_optimized(np)) {
4536                         if (rxtx_ring)
4537                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4538                                                     rxtx_ring, ring_addr);
4539                 } else {
4540                         if (rxtx_ring)
4541                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4542                                                     rxtx_ring, ring_addr);
4543                 }
4544
4545                 kfree(rx_skbuff);
4546                 kfree(tx_skbuff);
4547                 goto exit;
4548         }
4549
4550         if (netif_running(dev)) {
4551                 nv_disable_irq(dev);
4552                 nv_napi_disable(dev);
4553                 netif_tx_lock_bh(dev);
4554                 netif_addr_lock(dev);
4555                 spin_lock(&np->lock);
4556                 /* stop engines */
4557                 nv_stop_rxtx(dev);
4558                 nv_txrx_reset(dev);
4559                 /* drain queues */
4560                 nv_drain_rxtx(dev);
4561                 /* delete queues */
4562                 free_rings(dev);
4563         }
4564
4565         /* set new values */
4566         np->rx_ring_size = ring->rx_pending;
4567         np->tx_ring_size = ring->tx_pending;
4568
4569         if (!nv_optimized(np)) {
4570                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4571                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4572         } else {
4573                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4574                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4575         }
4576         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4577         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4578         np->ring_addr = ring_addr;
4579
4580         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4581         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4582
4583         if (netif_running(dev)) {
4584                 /* reinit driver view of the queues */
4585                 set_bufsize(dev);
4586                 if (nv_init_ring(dev)) {
4587                         if (!np->in_shutdown)
4588                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4589                 }
4590
4591                 /* reinit nic view of the queues */
4592                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4593                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4594                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4595                         base + NvRegRingSizes);
4596                 pci_push(base);
4597                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4598                 pci_push(base);
4599
4600                 /* restart engines */
4601                 nv_start_rxtx(dev);
4602                 spin_unlock(&np->lock);
4603                 netif_addr_unlock(dev);
4604                 netif_tx_unlock_bh(dev);
4605                 nv_napi_enable(dev);
4606                 nv_enable_irq(dev);
4607         }
4608         return 0;
4609 exit:
4610         return -ENOMEM;
4611 }
4612
4613 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4614 {
4615         struct fe_priv *np = netdev_priv(dev);
4616
4617         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4618         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4619         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4620 }
4621
4622 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4623 {
4624         struct fe_priv *np = netdev_priv(dev);
4625         int adv, bmcr;
4626
4627         if ((!np->autoneg && np->duplex == 0) ||
4628             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4629                 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4630                 return -EINVAL;
4631         }
4632         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4633                 netdev_info(dev, "hardware does not support tx pause frames\n");
4634                 return -EINVAL;
4635         }
4636
4637         netif_carrier_off(dev);
4638         if (netif_running(dev)) {
4639                 nv_disable_irq(dev);
4640                 netif_tx_lock_bh(dev);
4641                 netif_addr_lock(dev);
4642                 spin_lock(&np->lock);
4643                 /* stop engines */
4644                 nv_stop_rxtx(dev);
4645                 spin_unlock(&np->lock);
4646                 netif_addr_unlock(dev);
4647                 netif_tx_unlock_bh(dev);
4648         }
4649
4650         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4651         if (pause->rx_pause)
4652                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4653         if (pause->tx_pause)
4654                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4655
4656         if (np->autoneg && pause->autoneg) {
4657                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4658
4659                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4660                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4661                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4662                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4663                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4664                         adv |=  ADVERTISE_PAUSE_ASYM;
4665                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4666
4667                 if (netif_running(dev))
4668                         netdev_info(dev, "link down\n");
4669                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4670                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4671                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4672         } else {
4673                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4674                 if (pause->rx_pause)
4675                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4676                 if (pause->tx_pause)
4677                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4678
4679                 if (!netif_running(dev))
4680                         nv_update_linkspeed(dev);
4681                 else
4682                         nv_update_pause(dev, np->pause_flags);
4683         }
4684
4685         if (netif_running(dev)) {
4686                 nv_start_rxtx(dev);
4687                 nv_enable_irq(dev);
4688         }
4689         return 0;
4690 }
4691
4692 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4693 {
4694         struct fe_priv *np = netdev_priv(dev);
4695         unsigned long flags;
4696         u32 miicontrol;
4697         int err, retval = 0;
4698
4699         spin_lock_irqsave(&np->lock, flags);
4700         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4701         if (features & NETIF_F_LOOPBACK) {
4702                 if (miicontrol & BMCR_LOOPBACK) {
4703                         spin_unlock_irqrestore(&np->lock, flags);
4704                         netdev_info(dev, "Loopback already enabled\n");
4705                         return 0;
4706                 }
4707                 nv_disable_irq(dev);
4708                 /* Turn on loopback mode */
4709                 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4710                 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4711                 if (err) {
4712                         retval = PHY_ERROR;
4713                         spin_unlock_irqrestore(&np->lock, flags);
4714                         phy_init(dev);
4715                 } else {
4716                         if (netif_running(dev)) {
4717                                 /* Force 1000 Mbps full-duplex */
4718                                 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4719                                                                          1);
4720                                 /* Force link up */
4721                                 netif_carrier_on(dev);
4722                         }
4723                         spin_unlock_irqrestore(&np->lock, flags);
4724                         netdev_info(dev,
4725                                 "Internal PHY loopback mode enabled.\n");
4726                 }
4727         } else {
4728                 if (!(miicontrol & BMCR_LOOPBACK)) {
4729                         spin_unlock_irqrestore(&np->lock, flags);
4730                         netdev_info(dev, "Loopback already disabled\n");
4731                         return 0;
4732                 }
4733                 nv_disable_irq(dev);
4734                 /* Turn off loopback */
4735                 spin_unlock_irqrestore(&np->lock, flags);
4736                 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4737                 phy_init(dev);
4738         }
4739         msleep(500);
4740         spin_lock_irqsave(&np->lock, flags);
4741         nv_enable_irq(dev);
4742         spin_unlock_irqrestore(&np->lock, flags);
4743
4744         return retval;
4745 }
4746
4747 static netdev_features_t nv_fix_features(struct net_device *dev,
4748         netdev_features_t features)
4749 {
4750         /* vlan is dependent on rx checksum offload */
4751         if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4752                 features |= NETIF_F_RXCSUM;
4753
4754         return features;
4755 }
4756
4757 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4758 {
4759         struct fe_priv *np = get_nvpriv(dev);
4760
4761         spin_lock_irq(&np->lock);
4762
4763         if (features & NETIF_F_HW_VLAN_RX)
4764                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4765         else
4766                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4767
4768         if (features & NETIF_F_HW_VLAN_TX)
4769                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4770         else
4771                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4772
4773         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4774
4775         spin_unlock_irq(&np->lock);
4776 }
4777
4778 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4779 {
4780         struct fe_priv *np = netdev_priv(dev);
4781         u8 __iomem *base = get_hwbase(dev);
4782         netdev_features_t changed = dev->features ^ features;
4783         int retval;
4784
4785         if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4786                 retval = nv_set_loopback(dev, features);
4787                 if (retval != 0)
4788                         return retval;
4789         }
4790
4791         if (changed & NETIF_F_RXCSUM) {
4792                 spin_lock_irq(&np->lock);
4793
4794                 if (features & NETIF_F_RXCSUM)
4795                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4796                 else
4797                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4798
4799                 if (netif_running(dev))
4800                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4801
4802                 spin_unlock_irq(&np->lock);
4803         }
4804
4805         if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4806                 nv_vlan_mode(dev, features);
4807
4808         return 0;
4809 }
4810
4811 static int nv_get_sset_count(struct net_device *dev, int sset)
4812 {
4813         struct fe_priv *np = netdev_priv(dev);
4814
4815         switch (sset) {
4816         case ETH_SS_TEST:
4817                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4818                         return NV_TEST_COUNT_EXTENDED;
4819                 else
4820                         return NV_TEST_COUNT_BASE;
4821         case ETH_SS_STATS:
4822                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4823                         return NV_DEV_STATISTICS_V3_COUNT;
4824                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4825                         return NV_DEV_STATISTICS_V2_COUNT;
4826                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4827                         return NV_DEV_STATISTICS_V1_COUNT;
4828                 else
4829                         return 0;
4830         default:
4831                 return -EOPNOTSUPP;
4832         }
4833 }
4834
4835 static void nv_get_ethtool_stats(struct net_device *dev,
4836                                  struct ethtool_stats *estats, u64 *buffer)
4837         __acquires(&netdev_priv(dev)->hwstats_lock)
4838         __releases(&netdev_priv(dev)->hwstats_lock)
4839 {
4840         struct fe_priv *np = netdev_priv(dev);
4841
4842         spin_lock_bh(&np->hwstats_lock);
4843         nv_update_stats(dev);
4844         memcpy(buffer, &np->estats,
4845                nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4846         spin_unlock_bh(&np->hwstats_lock);
4847 }
4848
4849 static int nv_link_test(struct net_device *dev)
4850 {
4851         struct fe_priv *np = netdev_priv(dev);
4852         int mii_status;
4853
4854         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4855         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4856
4857         /* check phy link status */
4858         if (!(mii_status & BMSR_LSTATUS))
4859                 return 0;
4860         else
4861                 return 1;
4862 }
4863
4864 static int nv_register_test(struct net_device *dev)
4865 {
4866         u8 __iomem *base = get_hwbase(dev);
4867         int i = 0;
4868         u32 orig_read, new_read;
4869
4870         do {
4871                 orig_read = readl(base + nv_registers_test[i].reg);
4872
4873                 /* xor with mask to toggle bits */
4874                 orig_read ^= nv_registers_test[i].mask;
4875
4876                 writel(orig_read, base + nv_registers_test[i].reg);
4877
4878                 new_read = readl(base + nv_registers_test[i].reg);
4879
4880                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4881                         return 0;
4882
4883                 /* restore original value */
4884                 orig_read ^= nv_registers_test[i].mask;
4885                 writel(orig_read, base + nv_registers_test[i].reg);
4886
4887         } while (nv_registers_test[++i].reg != 0);
4888
4889         return 1;
4890 }
4891
4892 static int nv_interrupt_test(struct net_device *dev)
4893 {
4894         struct fe_priv *np = netdev_priv(dev);
4895         u8 __iomem *base = get_hwbase(dev);
4896         int ret = 1;
4897         int testcnt;
4898         u32 save_msi_flags, save_poll_interval = 0;
4899
4900         if (netif_running(dev)) {
4901                 /* free current irq */
4902                 nv_free_irq(dev);
4903                 save_poll_interval = readl(base+NvRegPollingInterval);
4904         }
4905
4906         /* flag to test interrupt handler */
4907         np->intr_test = 0;
4908
4909         /* setup test irq */
4910         save_msi_flags = np->msi_flags;
4911         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4912         np->msi_flags |= 0x001; /* setup 1 vector */
4913         if (nv_request_irq(dev, 1))
4914                 return 0;
4915
4916         /* setup timer interrupt */
4917         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4918         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4919
4920         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4921
4922         /* wait for at least one interrupt */
4923         msleep(100);
4924
4925         spin_lock_irq(&np->lock);
4926
4927         /* flag should be set within ISR */
4928         testcnt = np->intr_test;
4929         if (!testcnt)
4930                 ret = 2;
4931
4932         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4933         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4934                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4935         else
4936                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4937
4938         spin_unlock_irq(&np->lock);
4939
4940         nv_free_irq(dev);
4941
4942         np->msi_flags = save_msi_flags;
4943
4944         if (netif_running(dev)) {
4945                 writel(save_poll_interval, base + NvRegPollingInterval);
4946                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4947                 /* restore original irq */
4948                 if (nv_request_irq(dev, 0))
4949                         return 0;
4950         }
4951
4952         return ret;
4953 }
4954
4955 static int nv_loopback_test(struct net_device *dev)
4956 {
4957         struct fe_priv *np = netdev_priv(dev);
4958         u8 __iomem *base = get_hwbase(dev);
4959         struct sk_buff *tx_skb, *rx_skb;
4960         dma_addr_t test_dma_addr;
4961         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4962         u32 flags;
4963         int len, i, pkt_len;
4964         u8 *pkt_data;
4965         u32 filter_flags = 0;
4966         u32 misc1_flags = 0;
4967         int ret = 1;
4968
4969         if (netif_running(dev)) {
4970                 nv_disable_irq(dev);
4971                 filter_flags = readl(base + NvRegPacketFilterFlags);
4972                 misc1_flags = readl(base + NvRegMisc1);
4973         } else {
4974                 nv_txrx_reset(dev);
4975         }
4976
4977         /* reinit driver view of the rx queue */
4978         set_bufsize(dev);
4979         nv_init_ring(dev);
4980
4981         /* setup hardware for loopback */
4982         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4983         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4984
4985         /* reinit nic view of the rx queue */
4986         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4987         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4988         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4989                 base + NvRegRingSizes);
4990         pci_push(base);
4991
4992         /* restart rx engine */
4993         nv_start_rxtx(dev);
4994
4995         /* setup packet for tx */
4996         pkt_len = ETH_DATA_LEN;
4997         tx_skb = netdev_alloc_skb(dev, pkt_len);
4998         if (!tx_skb) {
4999                 netdev_err(dev, "netdev_alloc_skb() failed during loopback test\n");
5000                 ret = 0;
5001                 goto out;
5002         }
5003         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5004                                        skb_tailroom(tx_skb),
5005                                        PCI_DMA_FROMDEVICE);
5006         pkt_data = skb_put(tx_skb, pkt_len);
5007         for (i = 0; i < pkt_len; i++)
5008                 pkt_data[i] = (u8)(i & 0xff);
5009
5010         if (!nv_optimized(np)) {
5011                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5012                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5013         } else {
5014                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5015                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5016                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5017         }
5018         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5019         pci_push(get_hwbase(dev));
5020
5021         msleep(500);
5022
5023         /* check for rx of the packet */
5024         if (!nv_optimized(np)) {
5025                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5026                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5027
5028         } else {
5029                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5030                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5031         }
5032
5033         if (flags & NV_RX_AVAIL) {
5034                 ret = 0;
5035         } else if (np->desc_ver == DESC_VER_1) {
5036                 if (flags & NV_RX_ERROR)
5037                         ret = 0;
5038         } else {
5039                 if (flags & NV_RX2_ERROR)
5040                         ret = 0;
5041         }
5042
5043         if (ret) {
5044                 if (len != pkt_len) {
5045                         ret = 0;
5046                 } else {
5047                         rx_skb = np->rx_skb[0].skb;
5048                         for (i = 0; i < pkt_len; i++) {
5049                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5050                                         ret = 0;
5051                                         break;
5052                                 }
5053                         }
5054                 }
5055         }
5056
5057         pci_unmap_single(np->pci_dev, test_dma_addr,
5058                        (skb_end_pointer(tx_skb) - tx_skb->data),
5059                        PCI_DMA_TODEVICE);
5060         dev_kfree_skb_any(tx_skb);
5061  out:
5062         /* stop engines */
5063         nv_stop_rxtx(dev);
5064         nv_txrx_reset(dev);
5065         /* drain rx queue */
5066         nv_drain_rxtx(dev);
5067
5068         if (netif_running(dev)) {
5069                 writel(misc1_flags, base + NvRegMisc1);
5070                 writel(filter_flags, base + NvRegPacketFilterFlags);
5071                 nv_enable_irq(dev);
5072         }
5073
5074         return ret;
5075 }
5076
5077 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5078 {
5079         struct fe_priv *np = netdev_priv(dev);
5080         u8 __iomem *base = get_hwbase(dev);
5081         int result;
5082         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
5083
5084         if (!nv_link_test(dev)) {
5085                 test->flags |= ETH_TEST_FL_FAILED;
5086                 buffer[0] = 1;
5087         }
5088
5089         if (test->flags & ETH_TEST_FL_OFFLINE) {
5090                 if (netif_running(dev)) {
5091                         netif_stop_queue(dev);
5092                         nv_napi_disable(dev);
5093                         netif_tx_lock_bh(dev);
5094                         netif_addr_lock(dev);
5095                         spin_lock_irq(&np->lock);
5096                         nv_disable_hw_interrupts(dev, np->irqmask);
5097                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
5098                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5099                         else
5100                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5101                         /* stop engines */
5102                         nv_stop_rxtx(dev);
5103                         nv_txrx_reset(dev);
5104                         /* drain rx queue */
5105                         nv_drain_rxtx(dev);
5106                         spin_unlock_irq(&np->lock);
5107                         netif_addr_unlock(dev);
5108                         netif_tx_unlock_bh(dev);
5109                 }
5110
5111                 if (!nv_register_test(dev)) {
5112                         test->flags |= ETH_TEST_FL_FAILED;
5113                         buffer[1] = 1;
5114                 }
5115
5116                 result = nv_interrupt_test(dev);
5117                 if (result != 1) {
5118                         test->flags |= ETH_TEST_FL_FAILED;
5119                         buffer[2] = 1;
5120                 }
5121                 if (result == 0) {
5122                         /* bail out */
5123                         return;
5124                 }
5125
5126                 if (!nv_loopback_test(dev)) {
5127                         test->flags |= ETH_TEST_FL_FAILED;
5128                         buffer[3] = 1;
5129                 }
5130
5131                 if (netif_running(dev)) {
5132                         /* reinit driver view of the rx queue */
5133                         set_bufsize(dev);
5134                         if (nv_init_ring(dev)) {
5135                                 if (!np->in_shutdown)
5136                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5137                         }
5138                         /* reinit nic view of the rx queue */
5139                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5140                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5141                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5142                                 base + NvRegRingSizes);
5143                         pci_push(base);
5144                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5145                         pci_push(base);
5146                         /* restart rx engine */
5147                         nv_start_rxtx(dev);
5148                         netif_start_queue(dev);
5149                         nv_napi_enable(dev);
5150                         nv_enable_hw_interrupts(dev, np->irqmask);
5151                 }
5152         }
5153 }
5154
5155 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5156 {
5157         switch (stringset) {
5158         case ETH_SS_STATS:
5159                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5160                 break;
5161         case ETH_SS_TEST:
5162                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5163                 break;
5164         }
5165 }
5166
5167 static const struct ethtool_ops ops = {
5168         .get_drvinfo = nv_get_drvinfo,
5169         .get_link = ethtool_op_get_link,
5170         .get_wol = nv_get_wol,
5171         .set_wol = nv_set_wol,
5172         .get_settings = nv_get_settings,
5173         .set_settings = nv_set_settings,
5174         .get_regs_len = nv_get_regs_len,
5175         .get_regs = nv_get_regs,
5176         .nway_reset = nv_nway_reset,
5177         .get_ringparam = nv_get_ringparam,
5178         .set_ringparam = nv_set_ringparam,
5179         .get_pauseparam = nv_get_pauseparam,
5180         .set_pauseparam = nv_set_pauseparam,
5181         .get_strings = nv_get_strings,
5182         .get_ethtool_stats = nv_get_ethtool_stats,
5183         .get_sset_count = nv_get_sset_count,
5184         .self_test = nv_self_test,
5185         .get_ts_info = ethtool_op_get_ts_info,
5186 };
5187
5188 /* The mgmt unit and driver use a semaphore to access the phy during init */
5189 static int nv_mgmt_acquire_sema(struct net_device *dev)
5190 {
5191         struct fe_priv *np = netdev_priv(dev);
5192         u8 __iomem *base = get_hwbase(dev);
5193         int i;
5194         u32 tx_ctrl, mgmt_sema;
5195
5196         for (i = 0; i < 10; i++) {
5197                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5198                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5199                         break;
5200                 msleep(500);
5201         }
5202
5203         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5204                 return 0;
5205
5206         for (i = 0; i < 2; i++) {
5207                 tx_ctrl = readl(base + NvRegTransmitterControl);
5208                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5209                 writel(tx_ctrl, base + NvRegTransmitterControl);
5210
5211                 /* verify that semaphore was acquired */
5212                 tx_ctrl = readl(base + NvRegTransmitterControl);
5213                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5214                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5215                         np->mgmt_sema = 1;
5216                         return 1;
5217                 } else
5218                         udelay(50);
5219         }
5220
5221         return 0;
5222 }
5223
5224 static void nv_mgmt_release_sema(struct net_device *dev)
5225 {
5226         struct fe_priv *np = netdev_priv(dev);
5227         u8 __iomem *base = get_hwbase(dev);
5228         u32 tx_ctrl;
5229
5230         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5231                 if (np->mgmt_sema) {
5232                         tx_ctrl = readl(base + NvRegTransmitterControl);
5233                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5234                         writel(tx_ctrl, base + NvRegTransmitterControl);
5235                 }
5236         }
5237 }
5238
5239
5240 static int nv_mgmt_get_version(struct net_device *dev)
5241 {
5242         struct fe_priv *np = netdev_priv(dev);
5243         u8 __iomem *base = get_hwbase(dev);
5244         u32 data_ready = readl(base + NvRegTransmitterControl);
5245         u32 data_ready2 = 0;
5246         unsigned long start;
5247         int ready = 0;
5248
5249         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5250         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5251         start = jiffies;
5252         while (time_before(jiffies, start + 5*HZ)) {
5253                 data_ready2 = readl(base + NvRegTransmitterControl);
5254                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5255                         ready = 1;
5256                         break;
5257                 }
5258                 schedule_timeout_uninterruptible(1);
5259         }
5260
5261         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5262                 return 0;
5263
5264         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5265
5266         return 1;
5267 }
5268
5269 static int nv_open(struct net_device *dev)
5270 {
5271         struct fe_priv *np = netdev_priv(dev);
5272         u8 __iomem *base = get_hwbase(dev);
5273         int ret = 1;
5274         int oom, i;
5275         u32 low;
5276
5277         /* power up phy */
5278         mii_rw(dev, np->phyaddr, MII_BMCR,
5279                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5280
5281         nv_txrx_gate(dev, false);
5282         /* erase previous misconfiguration */
5283         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5284                 nv_mac_reset(dev);
5285         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5286         writel(0, base + NvRegMulticastAddrB);
5287         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5288         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5289         writel(0, base + NvRegPacketFilterFlags);
5290
5291         writel(0, base + NvRegTransmitterControl);
5292         writel(0, base + NvRegReceiverControl);
5293
5294         writel(0, base + NvRegAdapterControl);
5295
5296         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5297                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5298
5299         /* initialize descriptor rings */
5300         set_bufsize(dev);
5301         oom = nv_init_ring(dev);
5302
5303         writel(0, base + NvRegLinkSpeed);
5304         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5305         nv_txrx_reset(dev);
5306         writel(0, base + NvRegUnknownSetupReg6);
5307
5308         np->in_shutdown = 0;
5309
5310         /* give hw rings */
5311         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5312         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5313                 base + NvRegRingSizes);
5314
5315         writel(np->linkspeed, base + NvRegLinkSpeed);
5316         if (np->desc_ver == DESC_VER_1)
5317                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5318         else
5319                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5320         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5321         writel(np->vlanctl_bits, base + NvRegVlanControl);
5322         pci_push(base);
5323         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5324         if (reg_delay(dev, NvRegUnknownSetupReg5,
5325                       NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5326                       NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5327                 netdev_info(dev,
5328                             "%s: SetupReg5, Bit 31 remained off\n", __func__);
5329
5330         writel(0, base + NvRegMIIMask);
5331         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5332         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5333
5334         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5335         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5336         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5337         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5338
5339         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5340
5341         get_random_bytes(&low, sizeof(low));
5342         low &= NVREG_SLOTTIME_MASK;
5343         if (np->desc_ver == DESC_VER_1) {
5344                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5345         } else {
5346                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5347                         /* setup legacy backoff */
5348                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5349                 } else {
5350                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5351                         nv_gear_backoff_reseed(dev);
5352                 }
5353         }
5354         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5355         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5356         if (poll_interval == -1) {
5357                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5358                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5359                 else
5360                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5361         } else
5362                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5363         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5364         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5365                         base + NvRegAdapterControl);
5366         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5367         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5368         if (np->wolenabled)
5369                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5370
5371         i = readl(base + NvRegPowerState);
5372         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5373                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5374
5375         pci_push(base);
5376         udelay(10);
5377         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5378
5379         nv_disable_hw_interrupts(dev, np->irqmask);
5380         pci_push(base);
5381         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5382         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5383         pci_push(base);
5384
5385         if (nv_request_irq(dev, 0))
5386                 goto out_drain;
5387
5388         /* ask for interrupts */
5389         nv_enable_hw_interrupts(dev, np->irqmask);
5390
5391         spin_lock_irq(&np->lock);
5392         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5393         writel(0, base + NvRegMulticastAddrB);
5394         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5395         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5396         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5397         /* One manual link speed update: Interrupts are enabled, future link
5398          * speed changes cause interrupts and are handled by nv_link_irq().
5399          */
5400         {
5401                 u32 miistat;
5402                 miistat = readl(base + NvRegMIIStatus);
5403                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5404         }
5405         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5406          * to init hw */
5407         np->linkspeed = 0;
5408         ret = nv_update_linkspeed(dev);
5409         nv_start_rxtx(dev);
5410         netif_start_queue(dev);
5411         nv_napi_enable(dev);
5412
5413         if (ret) {
5414                 netif_carrier_on(dev);
5415         } else {
5416                 netdev_info(dev, "no link during initialization\n");
5417                 netif_carrier_off(dev);
5418         }
5419         if (oom)
5420                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5421
5422         /* start statistics timer */
5423         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5424                 mod_timer(&np->stats_poll,
5425                         round_jiffies(jiffies + STATS_INTERVAL));
5426
5427         spin_unlock_irq(&np->lock);
5428
5429         /* If the loopback feature was set while the device was down, make sure
5430          * that it's set correctly now.
5431          */
5432         if (dev->features & NETIF_F_LOOPBACK)
5433                 nv_set_loopback(dev, dev->features);
5434
5435         return 0;
5436 out_drain:
5437         nv_drain_rxtx(dev);
5438         return ret;
5439 }
5440
5441 static int nv_close(struct net_device *dev)
5442 {
5443         struct fe_priv *np = netdev_priv(dev);
5444         u8 __iomem *base;
5445
5446         spin_lock_irq(&np->lock);
5447         np->in_shutdown = 1;
5448         spin_unlock_irq(&np->lock);
5449         nv_napi_disable(dev);
5450         synchronize_irq(np->pci_dev->irq);
5451
5452         del_timer_sync(&np->oom_kick);
5453         del_timer_sync(&np->nic_poll);
5454         del_timer_sync(&np->stats_poll);
5455
5456         netif_stop_queue(dev);
5457         spin_lock_irq(&np->lock);
5458         nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
5459         nv_stop_rxtx(dev);
5460         nv_txrx_reset(dev);
5461
5462         /* disable interrupts on the nic or we will lock up */
5463         base = get_hwbase(dev);
5464         nv_disable_hw_interrupts(dev, np->irqmask);
5465         pci_push(base);
5466
5467         spin_unlock_irq(&np->lock);
5468
5469         nv_free_irq(dev);
5470
5471         nv_drain_rxtx(dev);
5472
5473         if (np->wolenabled || !phy_power_down) {
5474                 nv_txrx_gate(dev, false);
5475                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5476                 nv_start_rx(dev);
5477         } else {
5478                 /* power down phy */
5479                 mii_rw(dev, np->phyaddr, MII_BMCR,
5480                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5481                 nv_txrx_gate(dev, true);
5482         }
5483
5484         /* FIXME: power down nic */
5485
5486         return 0;
5487 }
5488
5489 static const struct net_device_ops nv_netdev_ops = {
5490         .ndo_open               = nv_open,
5491         .ndo_stop               = nv_close,
5492         .ndo_get_stats64        = nv_get_stats64,
5493         .ndo_start_xmit         = nv_start_xmit,
5494         .ndo_tx_timeout         = nv_tx_timeout,
5495         .ndo_change_mtu         = nv_change_mtu,
5496         .ndo_fix_features       = nv_fix_features,
5497         .ndo_set_features       = nv_set_features,
5498         .ndo_validate_addr      = eth_validate_addr,
5499         .ndo_set_mac_address    = nv_set_mac_address,
5500         .ndo_set_rx_mode        = nv_set_multicast,
5501 #ifdef CONFIG_NET_POLL_CONTROLLER
5502         .ndo_poll_controller    = nv_poll_controller,
5503 #endif
5504 };
5505
5506 static const struct net_device_ops nv_netdev_ops_optimized = {
5507         .ndo_open               = nv_open,
5508         .ndo_stop               = nv_close,
5509         .ndo_get_stats64        = nv_get_stats64,
5510         .ndo_start_xmit         = nv_start_xmit_optimized,
5511         .ndo_tx_timeout         = nv_tx_timeout,
5512         .ndo_change_mtu         = nv_change_mtu,
5513         .ndo_fix_features       = nv_fix_features,
5514         .ndo_set_features       = nv_set_features,
5515         .ndo_validate_addr      = eth_validate_addr,
5516         .ndo_set_mac_address    = nv_set_mac_address,
5517         .ndo_set_rx_mode        = nv_set_multicast,
5518 #ifdef CONFIG_NET_POLL_CONTROLLER
5519         .ndo_poll_controller    = nv_poll_controller,
5520 #endif
5521 };
5522
5523 static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5524 {
5525         struct net_device *dev;
5526         struct fe_priv *np;
5527         unsigned long addr;
5528         u8 __iomem *base;
5529         int err, i;
5530         u32 powerstate, txreg;
5531         u32 phystate_orig = 0, phystate;
5532         int phyinitialized = 0;
5533         static int printed_version;
5534
5535         if (!printed_version++)
5536                 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5537                         FORCEDETH_VERSION);
5538
5539         dev = alloc_etherdev(sizeof(struct fe_priv));
5540         err = -ENOMEM;
5541         if (!dev)
5542                 goto out;
5543
5544         np = netdev_priv(dev);
5545         np->dev = dev;
5546         np->pci_dev = pci_dev;
5547         spin_lock_init(&np->lock);
5548         spin_lock_init(&np->hwstats_lock);
5549         SET_NETDEV_DEV(dev, &pci_dev->dev);
5550
5551         init_timer(&np->oom_kick);
5552         np->oom_kick.data = (unsigned long) dev;
5553         np->oom_kick.function = nv_do_rx_refill;        /* timer handler */
5554         init_timer(&np->nic_poll);
5555         np->nic_poll.data = (unsigned long) dev;
5556         np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5557         init_timer_deferrable(&np->stats_poll);
5558         np->stats_poll.data = (unsigned long) dev;
5559         np->stats_poll.function = nv_do_stats_poll;     /* timer handler */
5560
5561         err = pci_enable_device(pci_dev);
5562         if (err)
5563                 goto out_free;
5564
5565         pci_set_master(pci_dev);
5566
5567         err = pci_request_regions(pci_dev, DRV_NAME);
5568         if (err < 0)
5569                 goto out_disable;
5570
5571         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5572                 np->register_size = NV_PCI_REGSZ_VER3;
5573         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5574                 np->register_size = NV_PCI_REGSZ_VER2;
5575         else
5576                 np->register_size = NV_PCI_REGSZ_VER1;
5577
5578         err = -EINVAL;
5579         addr = 0;
5580         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5581                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5582                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5583                         addr = pci_resource_start(pci_dev, i);
5584                         break;
5585                 }
5586         }
5587         if (i == DEVICE_COUNT_RESOURCE) {
5588                 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5589                 goto out_relreg;
5590         }
5591
5592         /* copy of driver data */
5593         np->driver_data = id->driver_data;
5594         /* copy of device id */
5595         np->device_id = id->device;
5596
5597         /* handle different descriptor versions */
5598         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5599                 /* packet format 3: supports 40-bit addressing */
5600                 np->desc_ver = DESC_VER_3;
5601                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5602                 if (dma_64bit) {
5603                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5604                                 dev_info(&pci_dev->dev,
5605                                          "64-bit DMA failed, using 32-bit addressing\n");
5606                         else
5607                                 dev->features |= NETIF_F_HIGHDMA;
5608                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5609                                 dev_info(&pci_dev->dev,
5610                                          "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5611                         }
5612                 }
5613         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5614                 /* packet format 2: supports jumbo frames */
5615                 np->desc_ver = DESC_VER_2;
5616                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5617         } else {
5618                 /* original packet format */
5619                 np->desc_ver = DESC_VER_1;
5620                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5621         }
5622
5623         np->pkt_limit = NV_PKTLIMIT_1;
5624         if (id->driver_data & DEV_HAS_LARGEDESC)
5625                 np->pkt_limit = NV_PKTLIMIT_2;
5626
5627         if (id->driver_data & DEV_HAS_CHECKSUM) {
5628                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5629                 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5630                         NETIF_F_TSO | NETIF_F_RXCSUM;
5631         }
5632
5633         np->vlanctl_bits = 0;
5634         if (id->driver_data & DEV_HAS_VLAN) {
5635                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5636                 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5637         }
5638
5639         dev->features |= dev->hw_features;
5640
5641         /* Add loopback capability to the device. */
5642         dev->hw_features |= NETIF_F_LOOPBACK;
5643
5644         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5645         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5646             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5647             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5648                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5649         }
5650
5651         err = -ENOMEM;
5652         np->base = ioremap(addr, np->register_size);
5653         if (!np->base)
5654                 goto out_relreg;
5655
5656         np->rx_ring_size = RX_RING_DEFAULT;
5657         np->tx_ring_size = TX_RING_DEFAULT;
5658
5659         if (!nv_optimized(np)) {
5660                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5661                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5662                                         &np->ring_addr);
5663                 if (!np->rx_ring.orig)
5664                         goto out_unmap;
5665                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5666         } else {
5667                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5668                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5669                                         &np->ring_addr);
5670                 if (!np->rx_ring.ex)
5671                         goto out_unmap;
5672                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5673         }
5674         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5675         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5676         if (!np->rx_skb || !np->tx_skb)
5677                 goto out_freering;
5678
5679         if (!nv_optimized(np))
5680                 dev->netdev_ops = &nv_netdev_ops;
5681         else
5682                 dev->netdev_ops = &nv_netdev_ops_optimized;
5683
5684         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5685         SET_ETHTOOL_OPS(dev, &ops);
5686         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5687
5688         pci_set_drvdata(pci_dev, dev);
5689
5690         /* read the mac address */
5691         base = get_hwbase(dev);
5692         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5693         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5694
5695         /* check the workaround bit for correct mac address order */
5696         txreg = readl(base + NvRegTransmitPoll);
5697         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5698                 /* mac address is already in correct order */
5699                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5700                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5701                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5702                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5703                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5704                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5705         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5706                 /* mac address is already in correct order */
5707                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5708                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5709                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5710                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5711                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5712                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5713                 /*
5714                  * Set orig mac address back to the reversed version.
5715                  * This flag will be cleared during low power transition.
5716                  * Therefore, we should always put back the reversed address.
5717                  */
5718                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5719                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5720                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5721         } else {
5722                 /* need to reverse mac address to correct order */
5723                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5724                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5725                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5726                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5727                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5728                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5729                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5730                 dev_dbg(&pci_dev->dev,
5731                         "%s: set workaround bit for reversed mac addr\n",
5732                         __func__);
5733         }
5734         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5735
5736         if (!is_valid_ether_addr(dev->perm_addr)) {
5737                 /*
5738                  * Bad mac address. At least one bios sets the mac address
5739                  * to 01:23:45:67:89:ab
5740                  */
5741                 dev_err(&pci_dev->dev,
5742                         "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5743                         dev->dev_addr);
5744                 eth_hw_addr_random(dev);
5745                 dev_err(&pci_dev->dev,
5746                         "Using random MAC address: %pM\n", dev->dev_addr);
5747         }
5748
5749         /* set mac address */
5750         nv_copy_mac_to_hw(dev);
5751
5752         /* disable WOL */
5753         writel(0, base + NvRegWakeUpFlags);
5754         np->wolenabled = 0;
5755         device_set_wakeup_enable(&pci_dev->dev, false);
5756
5757         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5758
5759                 /* take phy and nic out of low power mode */
5760                 powerstate = readl(base + NvRegPowerState2);
5761                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5762                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5763                     pci_dev->revision >= 0xA3)
5764                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5765                 writel(powerstate, base + NvRegPowerState2);
5766         }
5767
5768         if (np->desc_ver == DESC_VER_1)
5769                 np->tx_flags = NV_TX_VALID;
5770         else
5771                 np->tx_flags = NV_TX2_VALID;
5772
5773         np->msi_flags = 0;
5774         if ((id->driver_data & DEV_HAS_MSI) && msi)
5775                 np->msi_flags |= NV_MSI_CAPABLE;
5776
5777         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5778                 /* msix has had reported issues when modifying irqmask
5779                    as in the case of napi, therefore, disable for now
5780                 */
5781 #if 0
5782                 np->msi_flags |= NV_MSI_X_CAPABLE;
5783 #endif
5784         }
5785
5786         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5787                 np->irqmask = NVREG_IRQMASK_CPU;
5788                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5789                         np->msi_flags |= 0x0001;
5790         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5791                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5792                 /* start off in throughput mode */
5793                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5794                 /* remove support for msix mode */
5795                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5796         } else {
5797                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5798                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5799                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5800                         np->msi_flags |= 0x0003;
5801         }
5802
5803         if (id->driver_data & DEV_NEED_TIMERIRQ)
5804                 np->irqmask |= NVREG_IRQ_TIMER;
5805         if (id->driver_data & DEV_NEED_LINKTIMER) {
5806                 np->need_linktimer = 1;
5807                 np->link_timeout = jiffies + LINK_TIMEOUT;
5808         } else {
5809                 np->need_linktimer = 0;
5810         }
5811
5812         /* Limit the number of tx's outstanding for hw bug */
5813         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5814                 np->tx_limit = 1;
5815                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5816                     pci_dev->revision >= 0xA2)
5817                         np->tx_limit = 0;
5818         }
5819
5820         /* clear phy state and temporarily halt phy interrupts */
5821         writel(0, base + NvRegMIIMask);
5822         phystate = readl(base + NvRegAdapterControl);
5823         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5824                 phystate_orig = 1;
5825                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5826                 writel(phystate, base + NvRegAdapterControl);
5827         }
5828         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5829
5830         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5831                 /* management unit running on the mac? */
5832                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5833                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5834                     nv_mgmt_acquire_sema(dev) &&
5835                     nv_mgmt_get_version(dev)) {
5836                         np->mac_in_use = 1;
5837                         if (np->mgmt_version > 0)
5838                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5839                         /* management unit setup the phy already? */
5840                         if (np->mac_in_use &&
5841                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5842                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5843                                 /* phy is inited by mgmt unit */
5844                                 phyinitialized = 1;
5845                         } else {
5846                                 /* we need to init the phy */
5847                         }
5848                 }
5849         }
5850
5851         /* find a suitable phy */
5852         for (i = 1; i <= 32; i++) {
5853                 int id1, id2;
5854                 int phyaddr = i & 0x1F;
5855
5856                 spin_lock_irq(&np->lock);
5857                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5858                 spin_unlock_irq(&np->lock);
5859                 if (id1 < 0 || id1 == 0xffff)
5860                         continue;
5861                 spin_lock_irq(&np->lock);
5862                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5863                 spin_unlock_irq(&np->lock);
5864                 if (id2 < 0 || id2 == 0xffff)
5865                         continue;
5866
5867                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5868                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5869                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5870                 np->phyaddr = phyaddr;
5871                 np->phy_oui = id1 | id2;
5872
5873                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5874                 if (np->phy_oui == PHY_OUI_REALTEK2)
5875                         np->phy_oui = PHY_OUI_REALTEK;
5876                 /* Setup phy revision for Realtek */
5877                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5878                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5879
5880                 break;
5881         }
5882         if (i == 33) {
5883                 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5884                 goto out_error;
5885         }
5886
5887         if (!phyinitialized) {
5888                 /* reset it */
5889                 phy_init(dev);
5890         } else {
5891                 /* see if it is a gigabit phy */
5892                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5893                 if (mii_status & PHY_GIGABIT)
5894                         np->gigabit = PHY_GIGABIT;
5895         }
5896
5897         /* set default link speed settings */
5898         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5899         np->duplex = 0;
5900         np->autoneg = 1;
5901
5902         err = register_netdev(dev);
5903         if (err) {
5904                 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5905                 goto out_error;
5906         }
5907
5908         netif_carrier_off(dev);
5909
5910         /* Some NICs freeze when TX pause is enabled while NIC is
5911          * down, and this stays across warm reboots. The sequence
5912          * below should be enough to recover from that state.
5913          */
5914         nv_update_pause(dev, 0);
5915         nv_start_tx(dev);
5916         nv_stop_tx(dev);
5917
5918         if (id->driver_data & DEV_HAS_VLAN)
5919                 nv_vlan_mode(dev, dev->features);
5920
5921         dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5922                  dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5923
5924         dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5925                  dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5926                  dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5927                         "csum " : "",
5928                  dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5929                         "vlan " : "",
5930                  dev->features & (NETIF_F_LOOPBACK) ?
5931                         "loopback " : "",
5932                  id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5933                  id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5934                  id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5935                  np->gigabit == PHY_GIGABIT ? "gbit " : "",
5936                  np->need_linktimer ? "lnktim " : "",
5937                  np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5938                  np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5939                  np->desc_ver);
5940
5941         return 0;
5942
5943 out_error:
5944         if (phystate_orig)
5945                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5946         pci_set_drvdata(pci_dev, NULL);
5947 out_freering:
5948         free_rings(dev);
5949 out_unmap:
5950         iounmap(get_hwbase(dev));
5951 out_relreg:
5952         pci_release_regions(pci_dev);
5953 out_disable:
5954         pci_disable_device(pci_dev);
5955 out_free:
5956         free_netdev(dev);
5957 out:
5958         return err;
5959 }
5960
5961 static void nv_restore_phy(struct net_device *dev)
5962 {
5963         struct fe_priv *np = netdev_priv(dev);
5964         u16 phy_reserved, mii_control;
5965
5966         if (np->phy_oui == PHY_OUI_REALTEK &&
5967             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5968             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5969                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5970                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5971                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5972                 phy_reserved |= PHY_REALTEK_INIT8;
5973                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5974                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5975
5976                 /* restart auto negotiation */
5977                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5978                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5979                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5980         }
5981 }
5982
5983 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5984 {
5985         struct net_device *dev = pci_get_drvdata(pci_dev);
5986         struct fe_priv *np = netdev_priv(dev);
5987         u8 __iomem *base = get_hwbase(dev);
5988
5989         /* special op: write back the misordered MAC address - otherwise
5990          * the next nv_probe would see a wrong address.
5991          */
5992         writel(np->orig_mac[0], base + NvRegMacAddrA);
5993         writel(np->orig_mac[1], base + NvRegMacAddrB);
5994         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5995                base + NvRegTransmitPoll);
5996 }
5997
5998 static void nv_remove(struct pci_dev *pci_dev)
5999 {
6000         struct net_device *dev = pci_get_drvdata(pci_dev);
6001
6002         unregister_netdev(dev);
6003
6004         nv_restore_mac_addr(pci_dev);
6005
6006         /* restore any phy related changes */
6007         nv_restore_phy(dev);
6008
6009         nv_mgmt_release_sema(dev);
6010
6011         /* free all structures */
6012         free_rings(dev);
6013         iounmap(get_hwbase(dev));
6014         pci_release_regions(pci_dev);
6015         pci_disable_device(pci_dev);
6016         free_netdev(dev);
6017         pci_set_drvdata(pci_dev, NULL);
6018 }
6019
6020 #ifdef CONFIG_PM_SLEEP
6021 static int nv_suspend(struct device *device)
6022 {
6023         struct pci_dev *pdev = to_pci_dev(device);
6024         struct net_device *dev = pci_get_drvdata(pdev);
6025         struct fe_priv *np = netdev_priv(dev);
6026         u8 __iomem *base = get_hwbase(dev);
6027         int i;
6028
6029         if (netif_running(dev)) {
6030                 /* Gross. */
6031                 nv_close(dev);
6032         }
6033         netif_device_detach(dev);
6034
6035         /* save non-pci configuration space */
6036         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6037                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6038
6039         return 0;
6040 }
6041
6042 static int nv_resume(struct device *device)
6043 {
6044         struct pci_dev *pdev = to_pci_dev(device);
6045         struct net_device *dev = pci_get_drvdata(pdev);
6046         struct fe_priv *np = netdev_priv(dev);
6047         u8 __iomem *base = get_hwbase(dev);
6048         int i, rc = 0;
6049
6050         /* restore non-pci configuration space */
6051         for (i = 0; i <= np->register_size/sizeof(u32); i++)
6052                 writel(np->saved_config_space[i], base+i*sizeof(u32));
6053
6054         if (np->driver_data & DEV_NEED_MSI_FIX)
6055                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6056
6057         /* restore phy state, including autoneg */
6058         phy_init(dev);
6059
6060         netif_device_attach(dev);
6061         if (netif_running(dev)) {
6062                 rc = nv_open(dev);
6063                 nv_set_multicast(dev);
6064         }
6065         return rc;
6066 }
6067
6068 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6069 #define NV_PM_OPS (&nv_pm_ops)
6070
6071 #else
6072 #define NV_PM_OPS NULL
6073 #endif /* CONFIG_PM_SLEEP */
6074
6075 #ifdef CONFIG_PM
6076 static void nv_shutdown(struct pci_dev *pdev)
6077 {
6078         struct net_device *dev = pci_get_drvdata(pdev);
6079         struct fe_priv *np = netdev_priv(dev);
6080
6081         if (netif_running(dev))
6082                 nv_close(dev);
6083
6084         /*
6085          * Restore the MAC so a kernel started by kexec won't get confused.
6086          * If we really go for poweroff, we must not restore the MAC,
6087          * otherwise the MAC for WOL will be reversed at least on some boards.
6088          */
6089         if (system_state != SYSTEM_POWER_OFF)
6090                 nv_restore_mac_addr(pdev);
6091
6092         pci_disable_device(pdev);
6093         /*
6094          * Apparently it is not possible to reinitialise from D3 hot,
6095          * only put the device into D3 if we really go for poweroff.
6096          */
6097         if (system_state == SYSTEM_POWER_OFF) {
6098                 pci_wake_from_d3(pdev, np->wolenabled);
6099                 pci_set_power_state(pdev, PCI_D3hot);
6100         }
6101 }
6102 #else
6103 #define nv_shutdown NULL
6104 #endif /* CONFIG_PM */
6105
6106 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6107         {       /* nForce Ethernet Controller */
6108                 PCI_DEVICE(0x10DE, 0x01C3),
6109                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6110         },
6111         {       /* nForce2 Ethernet Controller */
6112                 PCI_DEVICE(0x10DE, 0x0066),
6113                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6114         },
6115         {       /* nForce3 Ethernet Controller */
6116                 PCI_DEVICE(0x10DE, 0x00D6),
6117                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6118         },
6119         {       /* nForce3 Ethernet Controller */
6120                 PCI_DEVICE(0x10DE, 0x0086),
6121                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6122         },
6123         {       /* nForce3 Ethernet Controller */
6124                 PCI_DEVICE(0x10DE, 0x008C),
6125                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6126         },
6127         {       /* nForce3 Ethernet Controller */
6128                 PCI_DEVICE(0x10DE, 0x00E6),
6129                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6130         },
6131         {       /* nForce3 Ethernet Controller */
6132                 PCI_DEVICE(0x10DE, 0x00DF),
6133                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6134         },
6135         {       /* CK804 Ethernet Controller */
6136                 PCI_DEVICE(0x10DE, 0x0056),
6137                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6138         },
6139         {       /* CK804 Ethernet Controller */
6140                 PCI_DEVICE(0x10DE, 0x0057),
6141                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6142         },
6143         {       /* MCP04 Ethernet Controller */
6144                 PCI_DEVICE(0x10DE, 0x0037),
6145                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6146         },
6147         {       /* MCP04 Ethernet Controller */
6148                 PCI_DEVICE(0x10DE, 0x0038),
6149                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6150         },
6151         {       /* MCP51 Ethernet Controller */
6152                 PCI_DEVICE(0x10DE, 0x0268),
6153                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6154         },
6155         {       /* MCP51 Ethernet Controller */
6156                 PCI_DEVICE(0x10DE, 0x0269),
6157                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6158         },
6159         {       /* MCP55 Ethernet Controller */
6160                 PCI_DEVICE(0x10DE, 0x0372),
6161                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6162         },
6163         {       /* MCP55 Ethernet Controller */
6164                 PCI_DEVICE(0x10DE, 0x0373),
6165                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6166         },
6167         {       /* MCP61 Ethernet Controller */
6168                 PCI_DEVICE(0x10DE, 0x03E5),
6169                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6170         },
6171         {       /* MCP61 Ethernet Controller */
6172                 PCI_DEVICE(0x10DE, 0x03E6),
6173                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6174         },
6175         {       /* MCP61 Ethernet Controller */
6176                 PCI_DEVICE(0x10DE, 0x03EE),
6177                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6178         },
6179         {       /* MCP61 Ethernet Controller */
6180                 PCI_DEVICE(0x10DE, 0x03EF),
6181                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6182         },
6183         {       /* MCP65 Ethernet Controller */
6184                 PCI_DEVICE(0x10DE, 0x0450),
6185                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6186         },
6187         {       /* MCP65 Ethernet Controller */
6188                 PCI_DEVICE(0x10DE, 0x0451),
6189                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6190         },
6191         {       /* MCP65 Ethernet Controller */
6192                 PCI_DEVICE(0x10DE, 0x0452),
6193                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6194         },
6195         {       /* MCP65 Ethernet Controller */
6196                 PCI_DEVICE(0x10DE, 0x0453),
6197                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6198         },
6199         {       /* MCP67 Ethernet Controller */
6200                 PCI_DEVICE(0x10DE, 0x054C),
6201                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6202         },
6203         {       /* MCP67 Ethernet Controller */
6204                 PCI_DEVICE(0x10DE, 0x054D),
6205                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6206         },
6207         {       /* MCP67 Ethernet Controller */
6208                 PCI_DEVICE(0x10DE, 0x054E),
6209                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6210         },
6211         {       /* MCP67 Ethernet Controller */
6212                 PCI_DEVICE(0x10DE, 0x054F),
6213                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6214         },
6215         {       /* MCP73 Ethernet Controller */
6216                 PCI_DEVICE(0x10DE, 0x07DC),
6217                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6218         },
6219         {       /* MCP73 Ethernet Controller */
6220                 PCI_DEVICE(0x10DE, 0x07DD),
6221                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6222         },
6223         {       /* MCP73 Ethernet Controller */
6224                 PCI_DEVICE(0x10DE, 0x07DE),
6225                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6226         },
6227         {       /* MCP73 Ethernet Controller */
6228                 PCI_DEVICE(0x10DE, 0x07DF),
6229                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6230         },
6231         {       /* MCP77 Ethernet Controller */
6232                 PCI_DEVICE(0x10DE, 0x0760),
6233                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6234         },
6235         {       /* MCP77 Ethernet Controller */
6236                 PCI_DEVICE(0x10DE, 0x0761),
6237                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6238         },
6239         {       /* MCP77 Ethernet Controller */
6240                 PCI_DEVICE(0x10DE, 0x0762),
6241                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6242         },
6243         {       /* MCP77 Ethernet Controller */
6244                 PCI_DEVICE(0x10DE, 0x0763),
6245                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6246         },
6247         {       /* MCP79 Ethernet Controller */
6248                 PCI_DEVICE(0x10DE, 0x0AB0),
6249                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6250         },
6251         {       /* MCP79 Ethernet Controller */
6252                 PCI_DEVICE(0x10DE, 0x0AB1),
6253                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6254         },
6255         {       /* MCP79 Ethernet Controller */
6256                 PCI_DEVICE(0x10DE, 0x0AB2),
6257                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6258         },
6259         {       /* MCP79 Ethernet Controller */
6260                 PCI_DEVICE(0x10DE, 0x0AB3),
6261                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6262         },
6263         {       /* MCP89 Ethernet Controller */
6264                 PCI_DEVICE(0x10DE, 0x0D7D),
6265                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6266         },
6267         {0,},
6268 };
6269
6270 static struct pci_driver driver = {
6271         .name           = DRV_NAME,
6272         .id_table       = pci_tbl,
6273         .probe          = nv_probe,
6274         .remove         = nv_remove,
6275         .shutdown       = nv_shutdown,
6276         .driver.pm      = NV_PM_OPS,
6277 };
6278
6279 static int __init init_nic(void)
6280 {
6281         return pci_register_driver(&driver);
6282 }
6283
6284 static void __exit exit_nic(void)
6285 {
6286         pci_unregister_driver(&driver);
6287 }
6288
6289 module_param(max_interrupt_work, int, 0);
6290 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6291 module_param(optimization_mode, int, 0);
6292 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6293 module_param(poll_interval, int, 0);
6294 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6295 module_param(msi, int, 0);
6296 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6297 module_param(msix, int, 0);
6298 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6299 module_param(dma_64bit, int, 0);
6300 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6301 module_param(phy_cross, int, 0);
6302 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6303 module_param(phy_power_down, int, 0);
6304 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6305 module_param(debug_tx_timeout, bool, 0);
6306 MODULE_PARM_DESC(debug_tx_timeout,
6307                  "Dump tx related registers and ring when tx_timeout happens");
6308
6309 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6310 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6311 MODULE_LICENSE("GPL");
6312
6313 MODULE_DEVICE_TABLE(pci, pci_tbl);
6314
6315 module_init(init_nic);
6316 module_exit(exit_nic);