2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #ifdef CONFIG_MLX4_EN_DCB
44 #include <linux/dcbnl.h>
46 #include <linux/cpu_rmap.h>
48 #include <linux/mlx4/device.h>
49 #include <linux/mlx4/qp.h>
50 #include <linux/mlx4/cq.h>
51 #include <linux/mlx4/srq.h>
52 #include <linux/mlx4/doorbell.h>
53 #include <linux/mlx4/cmd.h>
57 #define DRV_NAME "mlx4_en"
58 #define DRV_VERSION "2.0"
59 #define DRV_RELDATE "Dec 2011"
61 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
68 #define MLX4_EN_PAGE_SHIFT 12
69 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
70 #define DEF_RX_RINGS 16
71 #define MAX_RX_RINGS 128
72 #define MIN_RX_RINGS 4
74 #define HEADROOM (2048 / TXBB_SIZE + 1)
75 #define STAMP_STRIDE 64
76 #define STAMP_DWORDS (STAMP_STRIDE / 4)
77 #define STAMP_SHIFT 31
78 #define STAMP_VAL 0x7fffffff
79 #define STATS_DELAY (HZ / 4)
80 #define MAX_NUM_OF_FS_RULES 256
82 #define MLX4_EN_FILTER_HASH_SHIFT 4
83 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
85 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
86 #define MAX_DESC_SIZE 512
87 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
90 * OS related constants and tunables
93 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
95 /* Use the maximum between 16384 and a single page */
96 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
97 #define MLX4_EN_ALLOC_ORDER get_order(MLX4_EN_ALLOC_SIZE)
99 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
100 * and 4K allocations) */
102 FRAG_SZ0 = 512 - NET_IP_ALIGN,
105 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
107 #define MLX4_EN_MAX_RX_FRAGS 4
109 /* Maximum ring sizes */
110 #define MLX4_EN_MAX_TX_SIZE 8192
111 #define MLX4_EN_MAX_RX_SIZE 8192
113 /* Minimum ring size for our page-allocation scheme to work */
114 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
115 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
117 #define MLX4_EN_SMALL_PKT_SIZE 64
118 #define MLX4_EN_MAX_TX_RING_P_UP 32
119 #define MLX4_EN_NUM_UP 8
120 #define MLX4_EN_DEF_TX_RING_SIZE 512
121 #define MLX4_EN_DEF_RX_RING_SIZE 1024
122 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
125 /* Target number of packets to coalesce with interrupt moderation */
126 #define MLX4_EN_RX_COAL_TARGET 44
127 #define MLX4_EN_RX_COAL_TIME 0x10
129 #define MLX4_EN_TX_COAL_PKTS 16
130 #define MLX4_EN_TX_COAL_TIME 0x10
132 #define MLX4_EN_RX_RATE_LOW 400000
133 #define MLX4_EN_RX_COAL_TIME_LOW 0
134 #define MLX4_EN_RX_RATE_HIGH 450000
135 #define MLX4_EN_RX_COAL_TIME_HIGH 128
136 #define MLX4_EN_RX_SIZE_THRESH 1024
137 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
138 #define MLX4_EN_SAMPLE_INTERVAL 0
139 #define MLX4_EN_AVG_PKT_SMALL 256
141 #define MLX4_EN_AUTO_CONF 0xffff
143 #define MLX4_EN_DEF_RX_PAUSE 1
144 #define MLX4_EN_DEF_TX_PAUSE 1
146 /* Interval between successive polls in the Tx routine when polling is used
147 instead of interrupts (in per-core Tx rings) - should be power of 2 */
148 #define MLX4_EN_TX_POLL_MODER 16
149 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
151 #define ETH_LLC_SNAP_SIZE 8
153 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
154 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
155 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
157 #define MLX4_EN_MIN_MTU 46
158 #define ETH_BCAST 0xffffffffffffULL
160 #define MLX4_EN_LOOPBACK_RETRIES 5
161 #define MLX4_EN_LOOPBACK_TIMEOUT 100
163 #ifdef MLX4_EN_PERF_STAT
164 /* Number of samples to 'average' */
166 #define AVG_FACTOR 1024
167 #define NUM_PERF_STATS NUM_PERF_COUNTERS
169 #define INC_PERF_COUNTER(cnt) (++(cnt))
170 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
171 #define AVG_PERF_COUNTER(cnt, sample) \
172 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
173 #define GET_PERF_COUNTER(cnt) (cnt)
174 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
178 #define NUM_PERF_STATS 0
179 #define INC_PERF_COUNTER(cnt) do {} while (0)
180 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
181 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
182 #define GET_PERF_COUNTER(cnt) (0)
183 #define GET_AVG_PERF_COUNTER(cnt) (0)
184 #endif /* MLX4_EN_PERF_STAT */
199 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
200 #define XNOR(x, y) (!(x) == !(y))
201 #define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0)
204 struct mlx4_en_tx_info {
214 #define MLX4_EN_BIT_DESC_OWN 0x80000000
215 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
216 #define MLX4_EN_MEMTYPE_PAD 0x100
217 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
220 struct mlx4_en_tx_desc {
221 struct mlx4_wqe_ctrl_seg ctrl;
223 struct mlx4_wqe_data_seg data; /* at least one data segment */
224 struct mlx4_wqe_lso_seg lso;
225 struct mlx4_wqe_inline_seg inl;
229 #define MLX4_EN_USE_SRQ 0x01000000
231 #define MLX4_EN_CX3_LOW_ID 0x1000
232 #define MLX4_EN_CX3_HIGH_ID 0x1005
234 struct mlx4_en_rx_alloc {
240 struct mlx4_en_tx_ring {
241 struct mlx4_hwq_resources wqres;
242 u32 size ; /* number of TXBBs */
245 u16 cqn; /* index of port CQ associated with this ring */
252 struct mlx4_en_tx_info *tx_info;
256 struct mlx4_qp_context context;
258 enum mlx4_qp_state qp_state;
259 struct mlx4_srq dummy;
261 unsigned long packets;
262 unsigned long tx_csum;
265 struct netdev_queue *tx_queue;
268 struct mlx4_en_rx_desc {
269 /* actual number of entries depends on rx ring stride */
270 struct mlx4_wqe_data_seg data[0];
273 struct mlx4_en_rx_ring {
274 struct mlx4_hwq_resources wqres;
275 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
276 u32 size ; /* number of Rx descs*/
281 u16 cqn; /* index of port CQ associated with this ring */
289 unsigned long packets;
290 unsigned long csum_ok;
291 unsigned long csum_none;
296 struct mlx4_hwq_resources wqres;
299 struct net_device *dev;
300 struct napi_struct napi;
307 struct mlx4_cqe *buf;
308 #define MLX4_EN_OPCODE_ERROR 0x1e
311 struct mlx4_en_port_profile {
324 struct mlx4_en_profile {
331 u8 num_tx_rings_p_up;
332 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
336 struct mlx4_dev *dev;
337 struct pci_dev *pdev;
338 struct mutex state_lock;
339 struct net_device *pndev[MLX4_MAX_PORTS + 1];
342 struct mlx4_en_profile profile;
344 struct workqueue_struct *workqueue;
345 struct device *dma_device;
346 void __iomem *uar_map;
347 struct mlx4_uar priv_uar;
351 u8 mac_removed[MLX4_MAX_PORTS + 1];
355 struct mlx4_en_rss_map {
357 struct mlx4_qp qps[MAX_RX_RINGS];
358 enum mlx4_qp_state state[MAX_RX_RINGS];
359 struct mlx4_qp indir_qp;
360 enum mlx4_qp_state indir_state;
363 struct mlx4_en_port_state {
369 struct mlx4_en_pkt_stats {
370 unsigned long broadcast;
371 unsigned long rx_prio[8];
372 unsigned long tx_prio[8];
373 #define NUM_PKT_STATS 17
376 struct mlx4_en_port_stats {
377 unsigned long tso_packets;
378 unsigned long queue_stopped;
379 unsigned long wake_queue;
380 unsigned long tx_timeout;
381 unsigned long rx_alloc_failed;
382 unsigned long rx_chksum_good;
383 unsigned long rx_chksum_none;
384 unsigned long tx_chksum_offload;
385 #define NUM_PORT_STATS 8
388 struct mlx4_en_perf_stats {
395 #define NUM_PERF_COUNTERS 6
398 enum mlx4_en_mclist_act {
404 struct mlx4_en_mc_list {
405 struct list_head list;
406 enum mlx4_en_mclist_act action;
411 struct mlx4_en_frag_info {
413 u16 frag_prefix_size;
420 #ifdef CONFIG_MLX4_EN_DCB
421 /* Minimal TC BW - setting to 0 will block traffic */
422 #define MLX4_EN_BW_MIN 1
423 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
425 #define MLX4_EN_TC_ETS 7
429 struct ethtool_flow_id {
430 struct ethtool_rx_flow_spec flow_spec;
434 struct mlx4_en_priv {
435 struct mlx4_en_dev *mdev;
436 struct mlx4_en_port_profile *prof;
437 struct net_device *dev;
438 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
439 struct net_device_stats stats;
440 struct net_device_stats ret_stats;
441 struct mlx4_en_port_state port_state;
442 spinlock_t stats_lock;
443 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
445 unsigned long last_moder_packets[MAX_RX_RINGS];
446 unsigned long last_moder_tx_packets;
447 unsigned long last_moder_bytes[MAX_RX_RINGS];
448 unsigned long last_moder_jiffies;
449 int last_moder_time[MAX_RX_RINGS];
459 u16 adaptive_rx_coal;
462 u32 validate_loopback;
464 struct mlx4_hwq_resources res;
477 struct mlx4_en_rss_map rss_map;
480 #define MLX4_EN_FLAG_PROMISC 0x1
481 #define MLX4_EN_FLAG_MC_PROMISC 0x2
482 u8 num_tx_rings_p_up;
486 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
490 struct mlx4_en_tx_ring *tx_ring;
491 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
492 struct mlx4_en_cq *tx_cq;
493 struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
494 struct mlx4_qp drop_qp;
495 struct work_struct mcast_task;
496 struct work_struct mac_task;
497 struct work_struct watchdog_task;
498 struct work_struct linkstate_task;
499 struct delayed_work stats_task;
500 struct mlx4_en_perf_stats pstats;
501 struct mlx4_en_pkt_stats pkstats;
502 struct mlx4_en_port_stats port_stats;
504 struct list_head mc_list;
505 struct list_head curr_list;
507 struct mlx4_en_stat_out_mbox hw_stats;
513 #ifdef CONFIG_MLX4_EN_DCB
515 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
517 #ifdef CONFIG_RFS_ACCEL
518 spinlock_t filters_lock;
520 struct list_head filters;
521 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
527 MLX4_EN_WOL_MAGIC = (1ULL << 61),
528 MLX4_EN_WOL_ENABLED = (1ULL << 62),
531 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
533 void mlx4_en_destroy_netdev(struct net_device *dev);
534 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
535 struct mlx4_en_port_profile *prof);
537 int mlx4_en_start_port(struct net_device *dev);
538 void mlx4_en_stop_port(struct net_device *dev);
540 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
541 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
543 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
544 int entries, int ring, enum cq_type mode);
545 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
546 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
548 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
549 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
550 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
552 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
553 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
554 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
556 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
557 int qpn, u32 size, u16 stride);
558 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
559 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
560 struct mlx4_en_tx_ring *ring,
561 int cq, int user_prio);
562 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
563 struct mlx4_en_tx_ring *ring);
565 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
566 struct mlx4_en_rx_ring *ring,
567 u32 size, u16 stride);
568 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
569 struct mlx4_en_rx_ring *ring,
570 u32 size, u16 stride);
571 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
572 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
573 struct mlx4_en_rx_ring *ring);
574 int mlx4_en_process_rx_cq(struct net_device *dev,
575 struct mlx4_en_cq *cq,
577 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
578 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
579 int is_tx, int rss, int qpn, int cqn, int user_prio,
580 struct mlx4_qp_context *context);
581 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
582 int mlx4_en_map_buffer(struct mlx4_buf *buf);
583 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
585 void mlx4_en_calc_rx_buf(struct net_device *dev);
586 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
587 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
588 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
589 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
590 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
591 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
593 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
594 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
596 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
597 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
599 #ifdef CONFIG_MLX4_EN_DCB
600 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
603 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
605 #ifdef CONFIG_RFS_ACCEL
606 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
607 struct mlx4_en_rx_ring *rx_ring);
610 #define MLX4_EN_NUM_SELF_TEST 5
611 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
612 u64 mlx4_en_mac_to_u64(u8 *addr);
617 extern const struct ethtool_ops mlx4_en_ethtool_ops;
622 * printk / logging functions
626 int en_print(const char *level, const struct mlx4_en_priv *priv,
627 const char *format, ...);
629 #define en_dbg(mlevel, priv, format, arg...) \
631 if (NETIF_MSG_##mlevel & priv->msg_enable) \
632 en_print(KERN_DEBUG, priv, format, ##arg); \
634 #define en_warn(priv, format, arg...) \
635 en_print(KERN_WARNING, priv, format, ##arg)
636 #define en_err(priv, format, arg...) \
637 en_print(KERN_ERR, priv, format, ##arg)
638 #define en_info(priv, format, arg...) \
639 en_print(KERN_INFO, priv, format, ## arg)
641 #define mlx4_err(mdev, format, arg...) \
642 pr_err("%s %s: " format, DRV_NAME, \
643 dev_name(&mdev->pdev->dev), ##arg)
644 #define mlx4_info(mdev, format, arg...) \
645 pr_info("%s %s: " format, DRV_NAME, \
646 dev_name(&mdev->pdev->dev), ##arg)
647 #define mlx4_warn(mdev, format, arg...) \
648 pr_warning("%s %s: " format, DRV_NAME, \
649 dev_name(&mdev->pdev->dev), ##arg)