arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/export.h>
  23 #include <linux/irqdomain.h>
  24 #include <linux/of_address.h>
  25
  26 #include <asm/proc-fns.h>
  27 #include <asm/exception.h>
  28 #include <asm/hardware/cache-l2x0.h>
  29 #include <asm/hardware/gic.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32 #include <asm/cacheflush.h>
  33
  34 #include <mach/regs-irq.h>
  35 #include <mach/regs-pmu.h>
  36 #include <mach/regs-gpio.h>
  37 #include <mach/pmu.h>
  38
  39 #include <plat/cpu.h>
  40 #include <plat/clock.h>
  41 #include <plat/devs.h>
  42 #include <plat/pm.h>
  43 #include <plat/sdhci.h>
  44 #include <plat/gpio-cfg.h>
  45 #include <plat/adc-core.h>
  46 #include <plat/fb-core.h>
  47 #include <plat/fimc-core.h>
  48 #include <plat/iic-core.h>
  49 #include <plat/tv-core.h>
  50 #include <plat/spi-core.h>
  51 #include <plat/regs-serial.h>
  52
  53 #include "common.h"
  54 #define L2_AUX_VAL 0x7C470001
  55 #define L2_AUX_MASK 0xC200ffff
  56
  57 static const char name_exynos4210[] = "EXYNOS4210";
  58 static const char name_exynos4212[] = "EXYNOS4212";
  59 static const char name_exynos4412[] = "EXYNOS4412";
  60 static const char name_exynos5250[] = "EXYNOS5250";
  61 static const char name_exynos5440[] = "EXYNOS5440";
  62
  63 static void exynos4_map_io(void);
  64 static void exynos5_map_io(void);
  65 static void exynos5440_map_io(void);
  66 static void exynos4_init_clocks(int xtal);
  67 static void exynos5_init_clocks(int xtal);
  68 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  69 static int exynos_init(void);
  70
  71 static struct cpu_table cpu_ids[] __initdata = {
  72         {
  73                 .idcode         = EXYNOS4210_CPU_ID,
  74                 .idmask         = EXYNOS4_CPU_MASK,
  75                 .map_io         = exynos4_map_io,
  76                 .init_clocks    = exynos4_init_clocks,
  77                 .init_uarts     = exynos_init_uarts,
  78                 .init           = exynos_init,
  79                 .name           = name_exynos4210,
  80         }, {
  81                 .idcode         = EXYNOS4212_CPU_ID,
  82                 .idmask         = EXYNOS4_CPU_MASK,
  83                 .map_io         = exynos4_map_io,
  84                 .init_clocks    = exynos4_init_clocks,
  85                 .init_uarts     = exynos_init_uarts,
  86                 .init           = exynos_init,
  87                 .name           = name_exynos4212,
  88         }, {
  89                 .idcode         = EXYNOS4412_CPU_ID,
  90                 .idmask         = EXYNOS4_CPU_MASK,
  91                 .map_io         = exynos4_map_io,
  92                 .init_clocks    = exynos4_init_clocks,
  93                 .init_uarts     = exynos_init_uarts,
  94                 .init           = exynos_init,
  95                 .name           = name_exynos4412,
  96         }, {
  97                 .idcode         = EXYNOS5250_SOC_ID,
  98                 .idmask         = EXYNOS5_SOC_MASK,
  99                 .map_io         = exynos5_map_io,
 100                 .init_clocks    = exynos5_init_clocks,
 101                 .init_uarts     = exynos_init_uarts,
 102                 .init           = exynos_init,
 103                 .name           = name_exynos5250,
 104         }, {
 105                 .idcode         = EXYNOS5440_SOC_ID,
 106                 .idmask         = EXYNOS5_SOC_MASK,
 107                 .map_io         = exynos5440_map_io,
 108                 .init           = exynos_init,
 109                 .name           = name_exynos5440,
 110         },
 111 };
 112
 113 /* Initial IO mappings */
 114
 115 static struct map_desc exynos_iodesc[] __initdata = {
 116         {
 117                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 118                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 119                 .length         = SZ_4K,
 120                 .type           = MT_DEVICE,
 121         },
 122 };
 123
 124 static struct map_desc exynos5440_iodesc[] __initdata = {
 125         {
 126                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 127                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_CHIPID),
 128                 .length         = SZ_4K,
 129                 .type           = MT_DEVICE,
 130         },
 131 };
 132
 133 static struct map_desc exynos4_iodesc[] __initdata = {
 134         {
 135                 .virtual        = (unsigned long)S3C_VA_SYS,
 136                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 137                 .length         = SZ_64K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S3C_VA_TIMER,
 141                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 142                 .length         = SZ_16K,
 143                 .type           = MT_DEVICE,
 144         }, {
 145                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 146                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 147                 .length         = SZ_4K,
 148                 .type           = MT_DEVICE,
 149         }, {
 150                 .virtual        = (unsigned long)S5P_VA_SROMC,
 151                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 152                 .length         = SZ_4K,
 153                 .type           = MT_DEVICE,
 154         }, {
 155                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 156                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 157                 .length         = SZ_4K,
 158                 .type           = MT_DEVICE,
 159         }, {
 160                 .virtual        = (unsigned long)S5P_VA_PMU,
 161                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 162                 .length         = SZ_64K,
 163                 .type           = MT_DEVICE,
 164         }, {
 165                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 166                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 167                 .length         = SZ_4K,
 168                 .type           = MT_DEVICE,
 169         }, {
 170                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 171                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 172                 .length         = SZ_64K,
 173                 .type           = MT_DEVICE,
 174         }, {
 175                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 176                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 177                 .length         = SZ_64K,
 178                 .type           = MT_DEVICE,
 179         }, {
 180                 .virtual        = (unsigned long)S3C_VA_UART,
 181                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 182                 .length         = SZ_512K,
 183                 .type           = MT_DEVICE,
 184         }, {
 185                 .virtual        = (unsigned long)S5P_VA_CMU,
 186                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 187                 .length         = SZ_128K,
 188                 .type           = MT_DEVICE,
 189         }, {
 190                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 191                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 192                 .length         = SZ_8K,
 193                 .type           = MT_DEVICE,
 194         }, {
 195                 .virtual        = (unsigned long)S5P_VA_L2CC,
 196                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 197                 .length         = SZ_4K,
 198                 .type           = MT_DEVICE,
 199         }, {
 200                 .virtual        = (unsigned long)S5P_VA_DMC0,
 201                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 202                 .length         = SZ_64K,
 203                 .type           = MT_DEVICE,
 204         }, {
 205                 .virtual        = (unsigned long)S5P_VA_DMC1,
 206                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 207                 .length         = SZ_64K,
 208                 .type           = MT_DEVICE,
 209         }, {
 210                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 211                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 212                 .length         = SZ_4K,
 213                 .type           = MT_DEVICE,
 214         },
 215 };
 216
 217 static struct map_desc exynos4_iodesc0[] __initdata = {
 218         {
 219                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 220                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 221                 .length         = SZ_4K,
 222                 .type           = MT_DEVICE,
 223         },
 224 };
 225
 226 static struct map_desc exynos4_iodesc1[] __initdata = {
 227         {
 228                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 229                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 230                 .length         = SZ_4K,
 231                 .type           = MT_DEVICE,
 232         },
 233 };
 234
 235 static struct map_desc exynos5_iodesc[] __initdata = {
 236         {
 237                 .virtual        = (unsigned long)S3C_VA_SYS,
 238                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 239                 .length         = SZ_64K,
 240                 .type           = MT_DEVICE,
 241         }, {
 242                 .virtual        = (unsigned long)S3C_VA_TIMER,
 243                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 244                 .length         = SZ_16K,
 245                 .type           = MT_DEVICE,
 246         }, {
 247                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 248                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 249                 .length         = SZ_4K,
 250                 .type           = MT_DEVICE,
 251         }, {
 252                 .virtual        = (unsigned long)S5P_VA_SROMC,
 253                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 254                 .length         = SZ_4K,
 255                 .type           = MT_DEVICE,
 256         }, {
 257                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 258                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 259                 .length         = SZ_4K,
 260                 .type           = MT_DEVICE,
 261         }, {
 262                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 263                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 264                 .length         = SZ_4K,
 265                 .type           = MT_DEVICE,
 266         }, {
 267                 .virtual        = (unsigned long)S5P_VA_CMU,
 268                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 269                 .length         = 144 * SZ_1K,
 270                 .type           = MT_DEVICE,
 271         }, {
 272                 .virtual        = (unsigned long)S5P_VA_PMU,
 273                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 274                 .length         = SZ_64K,
 275                 .type           = MT_DEVICE,
 276         }, {
 277                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 278                 .pfn            = __phys_to_pfn(EXYNOS5_PA_COMBINER),
 279                 .length         = SZ_4K,
 280                 .type           = MT_DEVICE,
 281         }, {
 282                 .virtual        = (unsigned long)S3C_VA_UART,
 283                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 284                 .length         = SZ_512K,
 285                 .type           = MT_DEVICE,
 286         }, {
 287                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 288                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
 289                 .length         = SZ_8K,
 290                 .type           = MT_DEVICE,
 291         }, {
 292                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 293                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
 294                 .length         = SZ_4K,
 295                 .type           = MT_DEVICE,
 296         },
 297 };
 298
 299 static struct map_desc exynos5440_iodesc0[] __initdata = {
 300         {
 301                 .virtual        = (unsigned long)S3C_VA_UART,
 302                 .pfn            = __phys_to_pfn(EXYNOS5440_PA_UART0),
 303                 .length         = SZ_512K,
 304                 .type           = MT_DEVICE,
 305         },
 306 };
 307
 308 void exynos4_restart(char mode, const char *cmd)
 309 {
 310         __raw_writel(0x1, S5P_SWRESET);
 311 }
 312
 313 void exynos5_restart(char mode, const char *cmd)
 314 {
 315         u32 val;
 316         void __iomem *addr;
 317
 318         if (of_machine_is_compatible("samsung,exynos5250")) {
 319                 val = 0x1;
 320                 addr = EXYNOS_SWRESET;
 321         } else if (of_machine_is_compatible("samsung,exynos5440")) {
 322                 val = (0x10 << 20) | (0x1 << 16);
 323                 addr = EXYNOS5440_SWRESET;
 324         } else {
 325                 pr_err("%s: cannot support non-DT\n", __func__);
 326                 return;
 327         }
 328
 329         __raw_writel(val, addr);
 330 }
 331
 332 void __init exynos_init_late(void)
 333 {
 334         if (of_machine_is_compatible("samsung,exynos5440"))
 335                 /* to be supported later */
 336                 return;
 337
 338         exynos_pm_late_initcall();
 339 }
 340
 341 /*
 342  * exynos_map_io
 343  *
 344  * register the standard cpu IO areas
 345  */
 346
 347 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 348 {
 349         /* initialize the io descriptors we need for initialization */
 350         if (of_machine_is_compatible("samsung,exynos5440"))
 351                 iotable_init(exynos5440_iodesc, ARRAY_SIZE(exynos5440_iodesc));
 352         else
 353                 iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 354
 355         if (mach_desc)
 356                 iotable_init(mach_desc, size);
 357
 358         /* detect cpu id and rev. */
 359         s5p_init_cpu(S5P_VA_CHIPID);
 360
 361         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 362 }
 363
 364 static void __init exynos4_map_io(void)
 365 {
 366         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 367
 368         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 369                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 370         else
 371                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 372
 373         /* initialize device information early */
 374         exynos4_default_sdhci0();
 375         exynos4_default_sdhci1();
 376         exynos4_default_sdhci2();
 377         exynos4_default_sdhci3();
 378
 379         s3c_adc_setname("samsung-adc-v3");
 380
 381         s3c_fimc_setname(0, "exynos4-fimc");
 382         s3c_fimc_setname(1, "exynos4-fimc");
 383         s3c_fimc_setname(2, "exynos4-fimc");
 384         s3c_fimc_setname(3, "exynos4-fimc");
 385
 386         s3c_sdhci_setname(0, "exynos4-sdhci");
 387         s3c_sdhci_setname(1, "exynos4-sdhci");
 388         s3c_sdhci_setname(2, "exynos4-sdhci");
 389         s3c_sdhci_setname(3, "exynos4-sdhci");
 390
 391         /* The I2C bus controllers are directly compatible with s3c2440 */
 392         s3c_i2c0_setname("s3c2440-i2c");
 393         s3c_i2c1_setname("s3c2440-i2c");
 394         s3c_i2c2_setname("s3c2440-i2c");
 395
 396         s5p_fb_setname(0, "exynos4-fb");
 397         s5p_hdmi_setname("exynos4-hdmi");
 398
 399         s3c64xx_spi_setname("exynos4210-spi");
 400 }
 401
 402 static void __init exynos5_map_io(void)
 403 {
 404         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 405
 406         s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
 407         s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
 408         s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
 409         s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
 410
 411         s3c_sdhci_setname(0, "exynos4-sdhci");
 412         s3c_sdhci_setname(1, "exynos4-sdhci");
 413         s3c_sdhci_setname(2, "exynos4-sdhci");
 414         s3c_sdhci_setname(3, "exynos4-sdhci");
 415
 416         /* The I2C bus controllers are directly compatible with s3c2440 */
 417         s3c_i2c0_setname("s3c2440-i2c");
 418         s3c_i2c1_setname("s3c2440-i2c");
 419         s3c_i2c2_setname("s3c2440-i2c");
 420
 421         s3c64xx_spi_setname("exynos4210-spi");
 422 }
 423
 424 static void __init exynos4_init_clocks(int xtal)
 425 {
 426         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 427
 428         s3c24xx_register_baseclocks(xtal);
 429         s5p_register_clocks(xtal);
 430
 431         if (soc_is_exynos4210())
 432                 exynos4210_register_clocks();
 433         else if (soc_is_exynos4212() || soc_is_exynos4412())
 434                 exynos4212_register_clocks();
 435
 436         exynos4_register_clocks();
 437         exynos4_setup_clocks();
 438 }
 439
 440 static void __init exynos5440_map_io(void)
 441 {
 442         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 443 }
 444
 445 static void __init exynos5_init_clocks(int xtal)
 446 {
 447         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 448
 449         s3c24xx_register_baseclocks(xtal);
 450         s5p_register_clocks(xtal);
 451
 452         exynos5_register_clocks();
 453         exynos5_setup_clocks();
 454 }
 455
 456 #define COMBINER_ENABLE_SET     0x0
 457 #define COMBINER_ENABLE_CLEAR   0x4
 458 #define COMBINER_INT_STATUS     0xC
 459
 460 static DEFINE_SPINLOCK(irq_controller_lock);
 461
 462 struct combiner_chip_data {
 463         unsigned int irq_offset;
 464         unsigned int irq_mask;
 465         void __iomem *base;
 466 };
 467
 468 static struct irq_domain *combiner_irq_domain;
 469 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 470
 471 static inline void __iomem *combiner_base(struct irq_data *data)
 472 {
 473         struct combiner_chip_data *combiner_data =
 474                 irq_data_get_irq_chip_data(data);
 475
 476         return combiner_data->base;
 477 }
 478
 479 static void combiner_mask_irq(struct irq_data *data)
 480 {
 481         u32 mask = 1 << (data->hwirq % 32);
 482
 483         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 484 }
 485
 486 static void combiner_unmask_irq(struct irq_data *data)
 487 {
 488         u32 mask = 1 << (data->hwirq % 32);
 489
 490         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 491 }
 492
 493 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 494 {
 495         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 496         struct irq_chip *chip = irq_get_chip(irq);
 497         unsigned int cascade_irq, combiner_irq;
 498         unsigned long status;
 499
 500         chained_irq_enter(chip, desc);
 501
 502         spin_lock(&irq_controller_lock);
 503         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 504         spin_unlock(&irq_controller_lock);
 505         status &= chip_data->irq_mask;
 506
 507         if (status == 0)
 508                 goto out;
 509
 510         combiner_irq = __ffs(status);
 511
 512         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 513         if (unlikely(cascade_irq >= NR_IRQS))
 514                 do_bad_IRQ(cascade_irq, desc);
 515         else
 516                 generic_handle_irq(cascade_irq);
 517
 518  out:
 519         chained_irq_exit(chip, desc);
 520 }
 521
 522 static struct irq_chip combiner_chip = {
 523         .name           = "COMBINER",
 524         .irq_mask       = combiner_mask_irq,
 525         .irq_unmask     = combiner_unmask_irq,
 526 };
 527
 528 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 529 {
 530         unsigned int max_nr;
 531
 532         if (soc_is_exynos5250())
 533                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 534         else
 535                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 536
 537         if (combiner_nr >= max_nr)
 538                 BUG();
 539         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 540                 BUG();
 541         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 542 }
 543
 544 static void __init combiner_init_one(unsigned int combiner_nr,
 545                                      void __iomem *base)
 546 {
 547         combiner_data[combiner_nr].base = base;
 548         combiner_data[combiner_nr].irq_offset = irq_find_mapping(
 549                 combiner_irq_domain, combiner_nr * MAX_IRQ_IN_COMBINER);
 550         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 551
 552         /* Disable all interrupts */
 553         __raw_writel(combiner_data[combiner_nr].irq_mask,
 554                      base + COMBINER_ENABLE_CLEAR);
 555 }
 556
 557 #ifdef CONFIG_OF
 558 static int combiner_irq_domain_xlate(struct irq_domain *d,
 559                                      struct device_node *controller,
 560                                      const u32 *intspec, unsigned int intsize,
 561                                      unsigned long *out_hwirq,
 562                                      unsigned int *out_type)
 563 {
 564         if (d->of_node != controller)
 565                 return -EINVAL;
 566
 567         if (intsize < 2)
 568                 return -EINVAL;
 569
 570         *out_hwirq = intspec[0] * MAX_IRQ_IN_COMBINER + intspec[1];
 571         *out_type = 0;
 572
 573         return 0;
 574 }
 575 #else
 576 static int combiner_irq_domain_xlate(struct irq_domain *d,
 577                                      struct device_node *controller,
 578                                      const u32 *intspec, unsigned int intsize,
 579                                      unsigned long *out_hwirq,
 580                                      unsigned int *out_type)
 581 {
 582         return -EINVAL;
 583 }
 584 #endif
 585
 586 static int combiner_irq_domain_map(struct irq_domain *d, unsigned int irq,
 587                                    irq_hw_number_t hw)
 588 {
 589         irq_set_chip_and_handler(irq, &combiner_chip, handle_level_irq);
 590         irq_set_chip_data(irq, &combiner_data[hw >> 3]);
 591         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
 592
 593         return 0;
 594 }
 595
 596 static struct irq_domain_ops combiner_irq_domain_ops = {
 597         .xlate  = combiner_irq_domain_xlate,
 598         .map    = combiner_irq_domain_map,
 599 };
 600
 601 static void __init combiner_init(void __iomem *combiner_base,
 602                                  struct device_node *np)
 603 {
 604         int i, irq, irq_base;
 605         unsigned int max_nr, nr_irq;
 606
 607         if (np) {
 608                 if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) {
 609                         pr_warning("%s: number of combiners not specified, "
 610                                 "setting default as %d.\n",
 611                                 __func__, EXYNOS4_MAX_COMBINER_NR);
 612                         max_nr = EXYNOS4_MAX_COMBINER_NR;
 613                 }
 614         } else {
 615                 max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR :
 616                                                 EXYNOS4_MAX_COMBINER_NR;
 617         }
 618         nr_irq = max_nr * MAX_IRQ_IN_COMBINER;
 619
 620         irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0);
 621         if (IS_ERR_VALUE(irq_base)) {
 622                 irq_base = COMBINER_IRQ(0, 0);
 623                 pr_warning("%s: irq desc alloc failed. Continuing with %d as linux irq base\n", __func__, irq_base);
 624         }
 625
 626         combiner_irq_domain = irq_domain_add_legacy(np, nr_irq, irq_base, 0,
 627                                 &combiner_irq_domain_ops, &combiner_data);
 628         if (WARN_ON(!combiner_irq_domain)) {
 629                 pr_warning("%s: irq domain init failed\n", __func__);
 630                 return;
 631         }
 632
 633         for (i = 0; i < max_nr; i++) {
 634                 combiner_init_one(i, combiner_base + (i >> 2) * 0x10);
 635                 irq = IRQ_SPI(i);
 636 #ifdef CONFIG_OF
 637                 if (np)
 638                         irq = irq_of_parse_and_map(np, i);
 639 #endif
 640                 combiner_cascade_irq(i, irq);
 641         }
 642 }
 643
 644 #ifdef CONFIG_OF
 645 int __init combiner_of_init(struct device_node *np, struct device_node *parent)
 646 {
 647         void __iomem *combiner_base;
 648
 649         combiner_base = of_iomap(np, 0);
 650         if (!combiner_base) {
 651                 pr_err("%s: failed to map combiner registers\n", __func__);
 652                 return -ENXIO;
 653         }
 654
 655         combiner_init(combiner_base, np);
 656
 657         return 0;
 658 }
 659
 660 static const struct of_device_id exynos_dt_irq_match[] = {
 661         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 662         { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
 663         { .compatible = "samsung,exynos4210-combiner",
 664                         .data = combiner_of_init, },
 665         {},
 666 };
 667 #endif
 668
 669 void __init exynos4_init_irq(void)
 670 {
 671         unsigned int gic_bank_offset;
 672
 673         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 674
 675         if (!of_have_populated_dt())
 676                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 677 #ifdef CONFIG_OF
 678         else
 679                 of_irq_init(exynos_dt_irq_match);
 680 #endif
 681
 682         if (!of_have_populated_dt())
 683                 combiner_init(S5P_VA_COMBINER_BASE, NULL);
 684
 685         /*
 686          * The parameters of s5p_init_irq() are for VIC init.
 687          * Theses parameters should be NULL and 0 because EXYNOS4
 688          * uses GIC instead of VIC.
 689          */
 690         s5p_init_irq(NULL, 0);
 691 }
 692
 693 void __init exynos5_init_irq(void)
 694 {
 695 #ifdef CONFIG_OF
 696         of_irq_init(exynos_dt_irq_match);
 697 #endif
 698         /*
 699          * The parameters of s5p_init_irq() are for VIC init.
 700          * Theses parameters should be NULL and 0 because EXYNOS4
 701          * uses GIC instead of VIC.
 702          */
 703         s5p_init_irq(NULL, 0);
 704 }
 705
 706 struct bus_type exynos_subsys = {
 707         .name           = "exynos-core",
 708         .dev_name       = "exynos-core",
 709 };
 710
 711 static struct device exynos4_dev = {
 712         .bus    = &exynos_subsys,
 713 };
 714
 715 static int __init exynos_core_init(void)
 716 {
 717         return subsys_system_register(&exynos_subsys, NULL);
 718 }
 719 core_initcall(exynos_core_init);
 720
 721 #ifdef CONFIG_CACHE_L2X0
 722 static int __init exynos4_l2x0_cache_init(void)
 723 {
 724         int ret;
 725
 726         if (soc_is_exynos5250() || soc_is_exynos5440())
 727                 return 0;
 728
 729         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 730         if (!ret) {
 731                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 732                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 733                 return 0;
 734         }
 735
 736         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 737                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 738                 /* TAG, Data Latency Control: 2 cycles */
 739                 l2x0_saved_regs.tag_latency = 0x110;
 740
 741                 if (soc_is_exynos4212() || soc_is_exynos4412())
 742                         l2x0_saved_regs.data_latency = 0x120;
 743                 else
 744                         l2x0_saved_regs.data_latency = 0x110;
 745
 746                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 747                 l2x0_saved_regs.pwr_ctrl =
 748                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 749
 750                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 751
 752                 __raw_writel(l2x0_saved_regs.tag_latency,
 753                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 754                 __raw_writel(l2x0_saved_regs.data_latency,
 755                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 756
 757                 /* L2X0 Prefetch Control */
 758                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 759                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 760
 761                 /* L2X0 Power Control */
 762                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 763                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 764
 765                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 766                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 767         }
 768
 769         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 770         return 0;
 771 }
 772 early_initcall(exynos4_l2x0_cache_init);
 773 #endif
 774
 775 static int __init exynos_init(void)
 776 {
 777         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 778
 779         return device_register(&exynos4_dev);
 780 }
 781
 782 /* uart registration process */
 783
 784 static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 785 {
 786         struct s3c2410_uartcfg *tcfg = cfg;
 787         u32 ucnt;
 788
 789         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 790                 tcfg->has_fracval = 1;
 791
 792         if (soc_is_exynos5250())
 793                 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
 794         else
 795                 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 796 }
 797
 798 static void __iomem *exynos_eint_base;
 799
 800 static DEFINE_SPINLOCK(eint_lock);
 801
 802 static unsigned int eint0_15_data[16];
 803
 804 static inline int exynos4_irq_to_gpio(unsigned int irq)
 805 {
 806         if (irq < IRQ_EINT(0))
 807                 return -EINVAL;
 808
 809         irq -= IRQ_EINT(0);
 810         if (irq < 8)
 811                 return EXYNOS4_GPX0(irq);
 812
 813         irq -= 8;
 814         if (irq < 8)
 815                 return EXYNOS4_GPX1(irq);
 816
 817         irq -= 8;
 818         if (irq < 8)
 819                 return EXYNOS4_GPX2(irq);
 820
 821         irq -= 8;
 822         if (irq < 8)
 823                 return EXYNOS4_GPX3(irq);
 824
 825         return -EINVAL;
 826 }
 827
 828 static inline int exynos5_irq_to_gpio(unsigned int irq)
 829 {
 830         if (irq < IRQ_EINT(0))
 831                 return -EINVAL;
 832
 833         irq -= IRQ_EINT(0);
 834         if (irq < 8)
 835                 return EXYNOS5_GPX0(irq);
 836
 837         irq -= 8;
 838         if (irq < 8)
 839                 return EXYNOS5_GPX1(irq);
 840
 841         irq -= 8;
 842         if (irq < 8)
 843                 return EXYNOS5_GPX2(irq);
 844
 845         irq -= 8;
 846         if (irq < 8)
 847                 return EXYNOS5_GPX3(irq);
 848
 849         return -EINVAL;
 850 }
 851
 852 static unsigned int exynos4_eint0_15_src_int[16] = {
 853         EXYNOS4_IRQ_EINT0,
 854         EXYNOS4_IRQ_EINT1,
 855         EXYNOS4_IRQ_EINT2,
 856         EXYNOS4_IRQ_EINT3,
 857         EXYNOS4_IRQ_EINT4,
 858         EXYNOS4_IRQ_EINT5,
 859         EXYNOS4_IRQ_EINT6,
 860         EXYNOS4_IRQ_EINT7,
 861         EXYNOS4_IRQ_EINT8,
 862         EXYNOS4_IRQ_EINT9,
 863         EXYNOS4_IRQ_EINT10,
 864         EXYNOS4_IRQ_EINT11,
 865         EXYNOS4_IRQ_EINT12,
 866         EXYNOS4_IRQ_EINT13,
 867         EXYNOS4_IRQ_EINT14,
 868         EXYNOS4_IRQ_EINT15,
 869 };
 870
 871 static unsigned int exynos5_eint0_15_src_int[16] = {
 872         EXYNOS5_IRQ_EINT0,
 873         EXYNOS5_IRQ_EINT1,
 874         EXYNOS5_IRQ_EINT2,
 875         EXYNOS5_IRQ_EINT3,
 876         EXYNOS5_IRQ_EINT4,
 877         EXYNOS5_IRQ_EINT5,
 878         EXYNOS5_IRQ_EINT6,
 879         EXYNOS5_IRQ_EINT7,
 880         EXYNOS5_IRQ_EINT8,
 881         EXYNOS5_IRQ_EINT9,
 882         EXYNOS5_IRQ_EINT10,
 883         EXYNOS5_IRQ_EINT11,
 884         EXYNOS5_IRQ_EINT12,
 885         EXYNOS5_IRQ_EINT13,
 886         EXYNOS5_IRQ_EINT14,
 887         EXYNOS5_IRQ_EINT15,
 888 };
 889 static inline void exynos_irq_eint_mask(struct irq_data *data)
 890 {
 891         u32 mask;
 892
 893         spin_lock(&eint_lock);
 894         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 895         mask |= EINT_OFFSET_BIT(data->irq);
 896         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 897         spin_unlock(&eint_lock);
 898 }
 899
 900 static void exynos_irq_eint_unmask(struct irq_data *data)
 901 {
 902         u32 mask;
 903
 904         spin_lock(&eint_lock);
 905         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 906         mask &= ~(EINT_OFFSET_BIT(data->irq));
 907         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 908         spin_unlock(&eint_lock);
 909 }
 910
 911 static inline void exynos_irq_eint_ack(struct irq_data *data)
 912 {
 913         __raw_writel(EINT_OFFSET_BIT(data->irq),
 914                      EINT_PEND(exynos_eint_base, data->irq));
 915 }
 916
 917 static void exynos_irq_eint_maskack(struct irq_data *data)
 918 {
 919         exynos_irq_eint_mask(data);
 920         exynos_irq_eint_ack(data);
 921 }
 922
 923 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 924 {
 925         int offs = EINT_OFFSET(data->irq);
 926         int shift;
 927         u32 ctrl, mask;
 928         u32 newvalue = 0;
 929
 930         switch (type) {
 931         case IRQ_TYPE_EDGE_RISING:
 932                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 933                 break;
 934
 935         case IRQ_TYPE_EDGE_FALLING:
 936                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 937                 break;
 938
 939         case IRQ_TYPE_EDGE_BOTH:
 940                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 941                 break;
 942
 943         case IRQ_TYPE_LEVEL_LOW:
 944                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 945                 break;
 946
 947         case IRQ_TYPE_LEVEL_HIGH:
 948                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 949                 break;
 950
 951         default:
 952                 printk(KERN_ERR "No such irq type %d", type);
 953                 return -EINVAL;
 954         }
 955
 956         shift = (offs & 0x7) * 4;
 957         mask = 0x7 << shift;
 958
 959         spin_lock(&eint_lock);
 960         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 961         ctrl &= ~mask;
 962         ctrl |= newvalue << shift;
 963         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 964         spin_unlock(&eint_lock);
 965
 966         if (soc_is_exynos5250())
 967                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 968         else
 969                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 970
 971         return 0;
 972 }
 973
 974 static struct irq_chip exynos_irq_eint = {
 975         .name           = "exynos-eint",
 976         .irq_mask       = exynos_irq_eint_mask,
 977         .irq_unmask     = exynos_irq_eint_unmask,
 978         .irq_mask_ack   = exynos_irq_eint_maskack,
 979         .irq_ack        = exynos_irq_eint_ack,
 980         .irq_set_type   = exynos_irq_eint_set_type,
 981 #ifdef CONFIG_PM
 982         .irq_set_wake   = s3c_irqext_wake,
 983 #endif
 984 };
 985
 986 /*
 987  * exynos4_irq_demux_eint
 988  *
 989  * This function demuxes the IRQ from from EINTs 16 to 31.
 990  * It is designed to be inlined into the specific handler
 991  * s5p_irq_demux_eintX_Y.
 992  *
 993  * Each EINT pend/mask registers handle eight of them.
 994  */
 995 static inline void exynos_irq_demux_eint(unsigned int start)
 996 {
 997         unsigned int irq;
 998
 999         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
1000         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
1001
1002         status &= ~mask;
1003         status &= 0xff;
1004
1005         while (status) {
1006                 irq = fls(status) - 1;
1007                 generic_handle_irq(irq + start);
1008                 status &= ~(1 << irq);
1009         }
1010 }
1011
1012 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
1013 {
1014         struct irq_chip *chip = irq_get_chip(irq);
1015         chained_irq_enter(chip, desc);
1016         exynos_irq_demux_eint(IRQ_EINT(16));
1017         exynos_irq_demux_eint(IRQ_EINT(24));
1018         chained_irq_exit(chip, desc);
1019 }
1020
1021 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
1022 {
1023         u32 *irq_data = irq_get_handler_data(irq);
1024         struct irq_chip *chip = irq_get_chip(irq);
1025
1026         chained_irq_enter(chip, desc);
1027         chip->irq_mask(&desc->irq_data);
1028
1029         if (chip->irq_ack)
1030                 chip->irq_ack(&desc->irq_data);
1031
1032         generic_handle_irq(*irq_data);
1033
1034         chip->irq_unmask(&desc->irq_data);
1035         chained_irq_exit(chip, desc);
1036 }
1037
1038 static int __init exynos_init_irq_eint(void)
1039 {
1040         int irq;
1041
1042 #ifdef CONFIG_PINCTRL_SAMSUNG
1043         /*
1044          * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
1045          * functionality along with support for external gpio and wakeup
1046          * interrupts. If the samsung pinctrl driver is enabled and includes
1047          * the wakeup interrupt support, then the setting up external wakeup
1048          * interrupts here can be skipped. This check here is temporary to
1049          * allow exynos4 platforms that do not use Samsung pinctrl driver to
1050          * co-exist with platforms that do. When all of the Samsung Exynos4
1051          * platforms switch over to using the pinctrl driver, the wakeup
1052          * interrupt support code here can be completely removed.
1053          */
1054         struct device_node *pctrl_np, *wkup_np;
1055         const char *pctrl_compat = "samsung,pinctrl-exynos4210";
1056         const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
1057
1058         for_each_compatible_node(pctrl_np, NULL, pctrl_compat) {
1059                 if (of_device_is_available(pctrl_np)) {
1060                         wkup_np = of_find_compatible_node(pctrl_np, NULL,
1061                                                         wkup_compat);
1062                         if (wkup_np)
1063                                 return -ENODEV;
1064                 }
1065         }
1066 #endif
1067         if (soc_is_exynos5440())
1068                 return 0;
1069
1070         if (soc_is_exynos5250())
1071                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
1072         else
1073                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
1074
1075         if (exynos_eint_base == NULL) {
1076                 pr_err("unable to ioremap for EINT base address\n");
1077                 return -ENOMEM;
1078         }
1079
1080         for (irq = 0 ; irq <= 31 ; irq++) {
1081                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
1082                                          handle_level_irq);
1083                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
1084         }
1085
1086         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
1087
1088         for (irq = 0 ; irq <= 15 ; irq++) {
1089                 eint0_15_data[irq] = IRQ_EINT(irq);
1090
1091                 if (soc_is_exynos5250()) {
1092                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
1093                                              &eint0_15_data[irq]);
1094                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
1095                                                 exynos_irq_eint0_15);
1096                 } else {
1097                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
1098                                              &eint0_15_data[irq]);
1099                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
1100                                                 exynos_irq_eint0_15);
1101                 }
1102         }
1103
1104         return 0;
1105 }
1106 arch_initcall(exynos_init_irq_eint);