arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17 #include <linux/power/smartreflex.h>
  18 #include <linux/platform_data/gpio-omap.h>
  19
  20 #include <plat/omap_hwmod.h>
  21 #include <plat/dma.h>
  22 #include <plat/serial.h>
  23 #include "l3_3xxx.h"
  24 #include "l4_3xxx.h"
  25 #include <plat/i2c.h>
  26 #include <plat/mmc.h>
  27 #include <linux/platform_data/asoc-ti-mcbsp.h>
  28 #include <linux/platform_data/spi-omap2-mcspi.h>
  29 #include <plat/dmtimer.h>
  30 #include <plat/iommu.h>
  31
  32 #include "am35xx.h"
  33
  34 #include "soc.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "cm-regbits-34xx.h"
  38 #include "wd_timer.h"
  39
  40 /*
  41  * OMAP3xxx hardware module integration data
  42  *
  43  * All of the data in this section should be autogeneratable from the
  44  * TI hardware database or other technical documentation.  Data that
  45  * is driver-specific or driver-kernel integration-specific belongs
  46  * elsewhere.
  47  */
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /* L3 */
  54 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  55         { .irq = 9 + OMAP_INTC_START, },
  56         { .irq = 10 + OMAP_INTC_START, },
  57         { .irq = -1 },
  58 };
  59
  60 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  61         .name           = "l3_main",
  62         .class          = &l3_hwmod_class,
  63         .mpu_irqs       = omap3xxx_l3_main_irqs,
  64         .flags          = HWMOD_NO_IDLEST,
  65 };
  66
  67 /* L4 CORE */
  68 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  69         .name           = "l4_core",
  70         .class          = &l4_hwmod_class,
  71         .flags          = HWMOD_NO_IDLEST,
  72 };
  73
  74 /* L4 PER */
  75 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  76         .name           = "l4_per",
  77         .class          = &l4_hwmod_class,
  78         .flags          = HWMOD_NO_IDLEST,
  79 };
  80
  81 /* L4 WKUP */
  82 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  83         .name           = "l4_wkup",
  84         .class          = &l4_hwmod_class,
  85         .flags          = HWMOD_NO_IDLEST,
  86 };
  87
  88 /* L4 SEC */
  89 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  90         .name           = "l4_sec",
  91         .class          = &l4_hwmod_class,
  92         .flags          = HWMOD_NO_IDLEST,
  93 };
  94
  95 /* MPU */
  96 static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
  97         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
  98         { .irq = -1 }
  99 };
 100
 101 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 102         .name           = "mpu",
 103         .mpu_irqs       = omap3xxx_mpu_irqs,
 104         .class          = &mpu_hwmod_class,
 105         .main_clk       = "arm_fck",
 106 };
 107
 108 /* IVA2 (IVA2) */
 109 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 110         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 111         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 112         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 113 };
 114
 115 static struct omap_hwmod omap3xxx_iva_hwmod = {
 116         .name           = "iva",
 117         .class          = &iva_hwmod_class,
 118         .clkdm_name     = "iva2_clkdm",
 119         .rst_lines      = omap3xxx_iva_resets,
 120         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 121         .main_clk       = "iva2_ck",
 122         .prcm = {
 123                 .omap2 = {
 124                         .module_offs = OMAP3430_IVA2_MOD,
 125                         .prcm_reg_id = 1,
 126                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 127                         .idlest_reg_id = 1,
 128                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 129                 }
 130         },
 131 };
 132
 133 /*
 134  * 'debugss' class
 135  * debug and emulation sub system
 136  */
 137
 138 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 139         .name   = "debugss",
 140 };
 141
 142 /* debugss */
 143 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 144         .name           = "debugss",
 145         .class          = &omap3xxx_debugss_hwmod_class,
 146         .clkdm_name     = "emu_clkdm",
 147         .main_clk       = "emu_src_ck",
 148         .flags          = HWMOD_NO_IDLEST,
 149 };
 150
 151 /* timer class */
 152 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 153         .rev_offs       = 0x0000,
 154         .sysc_offs      = 0x0010,
 155         .syss_offs      = 0x0014,
 156         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 157                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 158                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 160         .sysc_fields    = &omap_hwmod_sysc_type1,
 161 };
 162
 163 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 164         .name = "timer",
 165         .sysc = &omap3xxx_timer_1ms_sysc,
 166 };
 167
 168 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 169         .rev_offs       = 0x0000,
 170         .sysc_offs      = 0x0010,
 171         .syss_offs      = 0x0014,
 172         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 173                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 174         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 175         .sysc_fields    = &omap_hwmod_sysc_type1,
 176 };
 177
 178 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 179         .name = "timer",
 180         .sysc = &omap3xxx_timer_sysc,
 181 };
 182
 183 /* secure timers dev attribute */
 184 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 185         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 186 };
 187
 188 /* always-on timers dev attribute */
 189 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 190         .timer_capability       = OMAP_TIMER_ALWON,
 191 };
 192
 193 /* pwm timers dev attribute */
 194 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 195         .timer_capability       = OMAP_TIMER_HAS_PWM,
 196 };
 197
 198 /* timers with DSP interrupt dev attribute */
 199 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 200         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 201 };
 202
 203 /* pwm timers with DSP interrupt dev attribute */
 204 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 205         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
 206 };
 207
 208 /* timer1 */
 209 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 210         .name           = "timer1",
 211         .mpu_irqs       = omap2_timer1_mpu_irqs,
 212         .main_clk       = "gpt1_fck",
 213         .prcm           = {
 214                 .omap2 = {
 215                         .prcm_reg_id = 1,
 216                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 217                         .module_offs = WKUP_MOD,
 218                         .idlest_reg_id = 1,
 219                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 220                 },
 221         },
 222         .dev_attr       = &capability_alwon_dev_attr,
 223         .class          = &omap3xxx_timer_1ms_hwmod_class,
 224 };
 225
 226 /* timer2 */
 227 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 228         .name           = "timer2",
 229         .mpu_irqs       = omap2_timer2_mpu_irqs,
 230         .main_clk       = "gpt2_fck",
 231         .prcm           = {
 232                 .omap2 = {
 233                         .prcm_reg_id = 1,
 234                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 235                         .module_offs = OMAP3430_PER_MOD,
 236                         .idlest_reg_id = 1,
 237                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 238                 },
 239         },
 240         .class          = &omap3xxx_timer_1ms_hwmod_class,
 241 };
 242
 243 /* timer3 */
 244 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 245         .name           = "timer3",
 246         .mpu_irqs       = omap2_timer3_mpu_irqs,
 247         .main_clk       = "gpt3_fck",
 248         .prcm           = {
 249                 .omap2 = {
 250                         .prcm_reg_id = 1,
 251                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 252                         .module_offs = OMAP3430_PER_MOD,
 253                         .idlest_reg_id = 1,
 254                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 255                 },
 256         },
 257         .class          = &omap3xxx_timer_hwmod_class,
 258 };
 259
 260 /* timer4 */
 261 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 262         .name           = "timer4",
 263         .mpu_irqs       = omap2_timer4_mpu_irqs,
 264         .main_clk       = "gpt4_fck",
 265         .prcm           = {
 266                 .omap2 = {
 267                         .prcm_reg_id = 1,
 268                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 269                         .module_offs = OMAP3430_PER_MOD,
 270                         .idlest_reg_id = 1,
 271                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 272                 },
 273         },
 274         .class          = &omap3xxx_timer_hwmod_class,
 275 };
 276
 277 /* timer5 */
 278 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 279         .name           = "timer5",
 280         .mpu_irqs       = omap2_timer5_mpu_irqs,
 281         .main_clk       = "gpt5_fck",
 282         .prcm           = {
 283                 .omap2 = {
 284                         .prcm_reg_id = 1,
 285                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 286                         .module_offs = OMAP3430_PER_MOD,
 287                         .idlest_reg_id = 1,
 288                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 289                 },
 290         },
 291         .dev_attr       = &capability_dsp_dev_attr,
 292         .class          = &omap3xxx_timer_hwmod_class,
 293 };
 294
 295 /* timer6 */
 296 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 297         .name           = "timer6",
 298         .mpu_irqs       = omap2_timer6_mpu_irqs,
 299         .main_clk       = "gpt6_fck",
 300         .prcm           = {
 301                 .omap2 = {
 302                         .prcm_reg_id = 1,
 303                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 304                         .module_offs = OMAP3430_PER_MOD,
 305                         .idlest_reg_id = 1,
 306                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 307                 },
 308         },
 309         .dev_attr       = &capability_dsp_dev_attr,
 310         .class          = &omap3xxx_timer_hwmod_class,
 311 };
 312
 313 /* timer7 */
 314 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 315         .name           = "timer7",
 316         .mpu_irqs       = omap2_timer7_mpu_irqs,
 317         .main_clk       = "gpt7_fck",
 318         .prcm           = {
 319                 .omap2 = {
 320                         .prcm_reg_id = 1,
 321                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 322                         .module_offs = OMAP3430_PER_MOD,
 323                         .idlest_reg_id = 1,
 324                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 325                 },
 326         },
 327         .dev_attr       = &capability_dsp_dev_attr,
 328         .class          = &omap3xxx_timer_hwmod_class,
 329 };
 330
 331 /* timer8 */
 332 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 333         .name           = "timer8",
 334         .mpu_irqs       = omap2_timer8_mpu_irqs,
 335         .main_clk       = "gpt8_fck",
 336         .prcm           = {
 337                 .omap2 = {
 338                         .prcm_reg_id = 1,
 339                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 340                         .module_offs = OMAP3430_PER_MOD,
 341                         .idlest_reg_id = 1,
 342                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 343                 },
 344         },
 345         .dev_attr       = &capability_dsp_pwm_dev_attr,
 346         .class          = &omap3xxx_timer_hwmod_class,
 347 };
 348
 349 /* timer9 */
 350 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 351         .name           = "timer9",
 352         .mpu_irqs       = omap2_timer9_mpu_irqs,
 353         .main_clk       = "gpt9_fck",
 354         .prcm           = {
 355                 .omap2 = {
 356                         .prcm_reg_id = 1,
 357                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 358                         .module_offs = OMAP3430_PER_MOD,
 359                         .idlest_reg_id = 1,
 360                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 361                 },
 362         },
 363         .dev_attr       = &capability_pwm_dev_attr,
 364         .class          = &omap3xxx_timer_hwmod_class,
 365 };
 366
 367 /* timer10 */
 368 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 369         .name           = "timer10",
 370         .mpu_irqs       = omap2_timer10_mpu_irqs,
 371         .main_clk       = "gpt10_fck",
 372         .prcm           = {
 373                 .omap2 = {
 374                         .prcm_reg_id = 1,
 375                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 376                         .module_offs = CORE_MOD,
 377                         .idlest_reg_id = 1,
 378                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 379                 },
 380         },
 381         .dev_attr       = &capability_pwm_dev_attr,
 382         .class          = &omap3xxx_timer_1ms_hwmod_class,
 383 };
 384
 385 /* timer11 */
 386 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 387         .name           = "timer11",
 388         .mpu_irqs       = omap2_timer11_mpu_irqs,
 389         .main_clk       = "gpt11_fck",
 390         .prcm           = {
 391                 .omap2 = {
 392                         .prcm_reg_id = 1,
 393                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 394                         .module_offs = CORE_MOD,
 395                         .idlest_reg_id = 1,
 396                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 397                 },
 398         },
 399         .dev_attr       = &capability_pwm_dev_attr,
 400         .class          = &omap3xxx_timer_hwmod_class,
 401 };
 402
 403 /* timer12 */
 404 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 405         { .irq = 95 + OMAP_INTC_START, },
 406         { .irq = -1 },
 407 };
 408
 409 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 410         .name           = "timer12",
 411         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 412         .main_clk       = "gpt12_fck",
 413         .prcm           = {
 414                 .omap2 = {
 415                         .prcm_reg_id = 1,
 416                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 417                         .module_offs = WKUP_MOD,
 418                         .idlest_reg_id = 1,
 419                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 420                 },
 421         },
 422         .dev_attr       = &capability_secure_dev_attr,
 423         .class          = &omap3xxx_timer_hwmod_class,
 424 };
 425
 426 /*
 427  * 'wd_timer' class
 428  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 429  * overflow condition
 430  */
 431
 432 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 433         .rev_offs       = 0x0000,
 434         .sysc_offs      = 0x0010,
 435         .syss_offs      = 0x0014,
 436         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 437                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 438                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 439                            SYSS_HAS_RESET_STATUS),
 440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 441         .sysc_fields    = &omap_hwmod_sysc_type1,
 442 };
 443
 444 /* I2C common */
 445 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 446         .rev_offs       = 0x00,
 447         .sysc_offs      = 0x20,
 448         .syss_offs      = 0x10,
 449         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 450                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 451                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 452         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 453         .clockact       = CLOCKACT_TEST_ICLK,
 454         .sysc_fields    = &omap_hwmod_sysc_type1,
 455 };
 456
 457 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 458         .name           = "wd_timer",
 459         .sysc           = &omap3xxx_wd_timer_sysc,
 460         .pre_shutdown   = &omap2_wd_timer_disable,
 461         .reset          = &omap2_wd_timer_reset,
 462 };
 463
 464 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 465         .name           = "wd_timer2",
 466         .class          = &omap3xxx_wd_timer_hwmod_class,
 467         .main_clk       = "wdt2_fck",
 468         .prcm           = {
 469                 .omap2 = {
 470                         .prcm_reg_id = 1,
 471                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 472                         .module_offs = WKUP_MOD,
 473                         .idlest_reg_id = 1,
 474                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 475                 },
 476         },
 477         /*
 478          * XXX: Use software supervised mode, HW supervised smartidle seems to
 479          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 480          */
 481         .flags          = HWMOD_SWSUP_SIDLE,
 482 };
 483
 484 /* UART1 */
 485 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 486         .name           = "uart1",
 487         .mpu_irqs       = omap2_uart1_mpu_irqs,
 488         .sdma_reqs      = omap2_uart1_sdma_reqs,
 489         .main_clk       = "uart1_fck",
 490         .prcm           = {
 491                 .omap2 = {
 492                         .module_offs = CORE_MOD,
 493                         .prcm_reg_id = 1,
 494                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 495                         .idlest_reg_id = 1,
 496                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 497                 },
 498         },
 499         .class          = &omap2_uart_class,
 500 };
 501
 502 /* UART2 */
 503 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 504         .name           = "uart2",
 505         .mpu_irqs       = omap2_uart2_mpu_irqs,
 506         .sdma_reqs      = omap2_uart2_sdma_reqs,
 507         .main_clk       = "uart2_fck",
 508         .prcm           = {
 509                 .omap2 = {
 510                         .module_offs = CORE_MOD,
 511                         .prcm_reg_id = 1,
 512                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 513                         .idlest_reg_id = 1,
 514                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 515                 },
 516         },
 517         .class          = &omap2_uart_class,
 518 };
 519
 520 /* UART3 */
 521 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 522         .name           = "uart3",
 523         .mpu_irqs       = omap2_uart3_mpu_irqs,
 524         .sdma_reqs      = omap2_uart3_sdma_reqs,
 525         .main_clk       = "uart3_fck",
 526         .prcm           = {
 527                 .omap2 = {
 528                         .module_offs = OMAP3430_PER_MOD,
 529                         .prcm_reg_id = 1,
 530                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 531                         .idlest_reg_id = 1,
 532                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 533                 },
 534         },
 535         .class          = &omap2_uart_class,
 536 };
 537
 538 /* UART4 */
 539 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 540         { .irq = 80 + OMAP_INTC_START, },
 541         { .irq = -1 },
 542 };
 543
 544 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 545         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 546         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 547         { .dma_req = -1 }
 548 };
 549
 550 static struct omap_hwmod omap36xx_uart4_hwmod = {
 551         .name           = "uart4",
 552         .mpu_irqs       = uart4_mpu_irqs,
 553         .sdma_reqs      = uart4_sdma_reqs,
 554         .main_clk       = "uart4_fck",
 555         .prcm           = {
 556                 .omap2 = {
 557                         .module_offs = OMAP3430_PER_MOD,
 558                         .prcm_reg_id = 1,
 559                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 560                         .idlest_reg_id = 1,
 561                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 562                 },
 563         },
 564         .class          = &omap2_uart_class,
 565 };
 566
 567 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 568         { .irq = 84 + OMAP_INTC_START, },
 569         { .irq = -1 },
 570 };
 571
 572 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 573         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 574         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 575         { .dma_req = -1 }
 576 };
 577
 578 /*
 579  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 580  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 581  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 582  * should not be needed.  The functional clock structure of the AM35xx
 583  * UART4 is extremely unclear and opaque; it is unclear what the role
 584  * of uart1/2_fck is for the UART4.  Any clarification from either
 585  * empirical testing or the AM3505/3517 hardware designers would be
 586  * most welcome.
 587  */
 588 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 589         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 590 };
 591
 592 static struct omap_hwmod am35xx_uart4_hwmod = {
 593         .name           = "uart4",
 594         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 595         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 596         .main_clk       = "uart4_fck",
 597         .prcm           = {
 598                 .omap2 = {
 599                         .module_offs = CORE_MOD,
 600                         .prcm_reg_id = 1,
 601                         .module_bit = AM35XX_EN_UART4_SHIFT,
 602                         .idlest_reg_id = 1,
 603                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 604                 },
 605         },
 606         .opt_clks       = am35xx_uart4_opt_clks,
 607         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 608         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 609         .class          = &omap2_uart_class,
 610 };
 611
 612 static struct omap_hwmod_class i2c_class = {
 613         .name   = "i2c",
 614         .sysc   = &i2c_sysc,
 615         .rev    = OMAP_I2C_IP_VERSION_1,
 616         .reset  = &omap_i2c_reset,
 617 };
 618
 619 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 620         { .name = "dispc", .dma_req = 5 },
 621         { .name = "dsi1", .dma_req = 74 },
 622         { .dma_req = -1 }
 623 };
 624
 625 /* dss */
 626 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 627         /*
 628          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 629          * driver does not use these clocks.
 630          */
 631         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 632         { .role = "tv_clk", .clk = "dss_tv_fck" },
 633         /* required only on OMAP3430 */
 634         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 635 };
 636
 637 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 638         .name           = "dss_core",
 639         .class          = &omap2_dss_hwmod_class,
 640         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 641         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 642         .prcm           = {
 643                 .omap2 = {
 644                         .prcm_reg_id = 1,
 645                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 646                         .module_offs = OMAP3430_DSS_MOD,
 647                         .idlest_reg_id = 1,
 648                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 649                 },
 650         },
 651         .opt_clks       = dss_opt_clks,
 652         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 653         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 654 };
 655
 656 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 657         .name           = "dss_core",
 658         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 659         .class          = &omap2_dss_hwmod_class,
 660         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 661         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 662         .prcm           = {
 663                 .omap2 = {
 664                         .prcm_reg_id = 1,
 665                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 666                         .module_offs = OMAP3430_DSS_MOD,
 667                         .idlest_reg_id = 1,
 668                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 669                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 670                 },
 671         },
 672         .opt_clks       = dss_opt_clks,
 673         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 674 };
 675
 676 /*
 677  * 'dispc' class
 678  * display controller
 679  */
 680
 681 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 682         .rev_offs       = 0x0000,
 683         .sysc_offs      = 0x0010,
 684         .syss_offs      = 0x0014,
 685         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 686                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 687                            SYSC_HAS_ENAWAKEUP),
 688         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 689                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 690         .sysc_fields    = &omap_hwmod_sysc_type1,
 691 };
 692
 693 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 694         .name   = "dispc",
 695         .sysc   = &omap3_dispc_sysc,
 696 };
 697
 698 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 699         .name           = "dss_dispc",
 700         .class          = &omap3_dispc_hwmod_class,
 701         .mpu_irqs       = omap2_dispc_irqs,
 702         .main_clk       = "dss1_alwon_fck",
 703         .prcm           = {
 704                 .omap2 = {
 705                         .prcm_reg_id = 1,
 706                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 707                         .module_offs = OMAP3430_DSS_MOD,
 708                 },
 709         },
 710         .flags          = HWMOD_NO_IDLEST,
 711         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 712 };
 713
 714 /*
 715  * 'dsi' class
 716  * display serial interface controller
 717  */
 718
 719 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 720         .name = "dsi",
 721 };
 722
 723 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 724         { .irq = 25 + OMAP_INTC_START, },
 725         { .irq = -1 },
 726 };
 727
 728 /* dss_dsi1 */
 729 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 730         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 731 };
 732
 733 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 734         .name           = "dss_dsi1",
 735         .class          = &omap3xxx_dsi_hwmod_class,
 736         .mpu_irqs       = omap3xxx_dsi1_irqs,
 737         .main_clk       = "dss1_alwon_fck",
 738         .prcm           = {
 739                 .omap2 = {
 740                         .prcm_reg_id = 1,
 741                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 742                         .module_offs = OMAP3430_DSS_MOD,
 743                 },
 744         },
 745         .opt_clks       = dss_dsi1_opt_clks,
 746         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 747         .flags          = HWMOD_NO_IDLEST,
 748 };
 749
 750 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 751         { .role = "ick", .clk = "dss_ick" },
 752 };
 753
 754 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 755         .name           = "dss_rfbi",
 756         .class          = &omap2_rfbi_hwmod_class,
 757         .main_clk       = "dss1_alwon_fck",
 758         .prcm           = {
 759                 .omap2 = {
 760                         .prcm_reg_id = 1,
 761                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 762                         .module_offs = OMAP3430_DSS_MOD,
 763                 },
 764         },
 765         .opt_clks       = dss_rfbi_opt_clks,
 766         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 767         .flags          = HWMOD_NO_IDLEST,
 768 };
 769
 770 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 771         /* required only on OMAP3430 */
 772         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 773 };
 774
 775 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 776         .name           = "dss_venc",
 777         .class          = &omap2_venc_hwmod_class,
 778         .main_clk       = "dss_tv_fck",
 779         .prcm           = {
 780                 .omap2 = {
 781                         .prcm_reg_id = 1,
 782                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 783                         .module_offs = OMAP3430_DSS_MOD,
 784                 },
 785         },
 786         .opt_clks       = dss_venc_opt_clks,
 787         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 788         .flags          = HWMOD_NO_IDLEST,
 789 };
 790
 791 /* I2C1 */
 792 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 793         .fifo_depth     = 8, /* bytes */
 794         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 795                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 796                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 797 };
 798
 799 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 800         .name           = "i2c1",
 801         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 802         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 803         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 804         .main_clk       = "i2c1_fck",
 805         .prcm           = {
 806                 .omap2 = {
 807                         .module_offs = CORE_MOD,
 808                         .prcm_reg_id = 1,
 809                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 810                         .idlest_reg_id = 1,
 811                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 812                 },
 813         },
 814         .class          = &i2c_class,
 815         .dev_attr       = &i2c1_dev_attr,
 816 };
 817
 818 /* I2C2 */
 819 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 820         .fifo_depth     = 8, /* bytes */
 821         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 822                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 823                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 824 };
 825
 826 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 827         .name           = "i2c2",
 828         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 829         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 830         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 831         .main_clk       = "i2c2_fck",
 832         .prcm           = {
 833                 .omap2 = {
 834                         .module_offs = CORE_MOD,
 835                         .prcm_reg_id = 1,
 836                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 837                         .idlest_reg_id = 1,
 838                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 839                 },
 840         },
 841         .class          = &i2c_class,
 842         .dev_attr       = &i2c2_dev_attr,
 843 };
 844
 845 /* I2C3 */
 846 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 847         .fifo_depth     = 64, /* bytes */
 848         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 849                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 850                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 851 };
 852
 853 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 854         { .irq = 61 + OMAP_INTC_START, },
 855         { .irq = -1 },
 856 };
 857
 858 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 859         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 860         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 861         { .dma_req = -1 }
 862 };
 863
 864 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 865         .name           = "i2c3",
 866         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 867         .mpu_irqs       = i2c3_mpu_irqs,
 868         .sdma_reqs      = i2c3_sdma_reqs,
 869         .main_clk       = "i2c3_fck",
 870         .prcm           = {
 871                 .omap2 = {
 872                         .module_offs = CORE_MOD,
 873                         .prcm_reg_id = 1,
 874                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 875                         .idlest_reg_id = 1,
 876                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 877                 },
 878         },
 879         .class          = &i2c_class,
 880         .dev_attr       = &i2c3_dev_attr,
 881 };
 882
 883 /*
 884  * 'gpio' class
 885  * general purpose io module
 886  */
 887
 888 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 889         .rev_offs       = 0x0000,
 890         .sysc_offs      = 0x0010,
 891         .syss_offs      = 0x0014,
 892         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 893                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 894                            SYSS_HAS_RESET_STATUS),
 895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 896         .sysc_fields    = &omap_hwmod_sysc_type1,
 897 };
 898
 899 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 900         .name = "gpio",
 901         .sysc = &omap3xxx_gpio_sysc,
 902         .rev = 1,
 903 };
 904
 905 /* gpio_dev_attr */
 906 static struct omap_gpio_dev_attr gpio_dev_attr = {
 907         .bank_width = 32,
 908         .dbck_flag = true,
 909 };
 910
 911 /* gpio1 */
 912 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 913         { .role = "dbclk", .clk = "gpio1_dbck", },
 914 };
 915
 916 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 917         .name           = "gpio1",
 918         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 919         .mpu_irqs       = omap2_gpio1_irqs,
 920         .main_clk       = "gpio1_ick",
 921         .opt_clks       = gpio1_opt_clks,
 922         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 923         .prcm           = {
 924                 .omap2 = {
 925                         .prcm_reg_id = 1,
 926                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 927                         .module_offs = WKUP_MOD,
 928                         .idlest_reg_id = 1,
 929                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 930                 },
 931         },
 932         .class          = &omap3xxx_gpio_hwmod_class,
 933         .dev_attr       = &gpio_dev_attr,
 934 };
 935
 936 /* gpio2 */
 937 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 938         { .role = "dbclk", .clk = "gpio2_dbck", },
 939 };
 940
 941 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 942         .name           = "gpio2",
 943         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 944         .mpu_irqs       = omap2_gpio2_irqs,
 945         .main_clk       = "gpio2_ick",
 946         .opt_clks       = gpio2_opt_clks,
 947         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 948         .prcm           = {
 949                 .omap2 = {
 950                         .prcm_reg_id = 1,
 951                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 952                         .module_offs = OMAP3430_PER_MOD,
 953                         .idlest_reg_id = 1,
 954                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 955                 },
 956         },
 957         .class          = &omap3xxx_gpio_hwmod_class,
 958         .dev_attr       = &gpio_dev_attr,
 959 };
 960
 961 /* gpio3 */
 962 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 963         { .role = "dbclk", .clk = "gpio3_dbck", },
 964 };
 965
 966 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 967         .name           = "gpio3",
 968         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 969         .mpu_irqs       = omap2_gpio3_irqs,
 970         .main_clk       = "gpio3_ick",
 971         .opt_clks       = gpio3_opt_clks,
 972         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 973         .prcm           = {
 974                 .omap2 = {
 975                         .prcm_reg_id = 1,
 976                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 977                         .module_offs = OMAP3430_PER_MOD,
 978                         .idlest_reg_id = 1,
 979                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 980                 },
 981         },
 982         .class          = &omap3xxx_gpio_hwmod_class,
 983         .dev_attr       = &gpio_dev_attr,
 984 };
 985
 986 /* gpio4 */
 987 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 988         { .role = "dbclk", .clk = "gpio4_dbck", },
 989 };
 990
 991 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 992         .name           = "gpio4",
 993         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 994         .mpu_irqs       = omap2_gpio4_irqs,
 995         .main_clk       = "gpio4_ick",
 996         .opt_clks       = gpio4_opt_clks,
 997         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 998         .prcm           = {
 999                 .omap2 = {
1000                         .prcm_reg_id = 1,
1001                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1002                         .module_offs = OMAP3430_PER_MOD,
1003                         .idlest_reg_id = 1,
1004                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1005                 },
1006         },
1007         .class          = &omap3xxx_gpio_hwmod_class,
1008         .dev_attr       = &gpio_dev_attr,
1009 };
1010
1011 /* gpio5 */
1012 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1013         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
1014         { .irq = -1 },
1015 };
1016
1017 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1018         { .role = "dbclk", .clk = "gpio5_dbck", },
1019 };
1020
1021 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1022         .name           = "gpio5",
1023         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1024         .mpu_irqs       = omap3xxx_gpio5_irqs,
1025         .main_clk       = "gpio5_ick",
1026         .opt_clks       = gpio5_opt_clks,
1027         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1028         .prcm           = {
1029                 .omap2 = {
1030                         .prcm_reg_id = 1,
1031                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1032                         .module_offs = OMAP3430_PER_MOD,
1033                         .idlest_reg_id = 1,
1034                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1035                 },
1036         },
1037         .class          = &omap3xxx_gpio_hwmod_class,
1038         .dev_attr       = &gpio_dev_attr,
1039 };
1040
1041 /* gpio6 */
1042 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1043         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1044         { .irq = -1 },
1045 };
1046
1047 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1048         { .role = "dbclk", .clk = "gpio6_dbck", },
1049 };
1050
1051 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1052         .name           = "gpio6",
1053         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054         .mpu_irqs       = omap3xxx_gpio6_irqs,
1055         .main_clk       = "gpio6_ick",
1056         .opt_clks       = gpio6_opt_clks,
1057         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1058         .prcm           = {
1059                 .omap2 = {
1060                         .prcm_reg_id = 1,
1061                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1062                         .module_offs = OMAP3430_PER_MOD,
1063                         .idlest_reg_id = 1,
1064                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1065                 },
1066         },
1067         .class          = &omap3xxx_gpio_hwmod_class,
1068         .dev_attr       = &gpio_dev_attr,
1069 };
1070
1071 /* dma attributes */
1072 static struct omap_dma_dev_attr dma_dev_attr = {
1073         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1074                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1075         .lch_count = 32,
1076 };
1077
1078 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1079         .rev_offs       = 0x0000,
1080         .sysc_offs      = 0x002c,
1081         .syss_offs      = 0x0028,
1082         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1083                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1084                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1085                            SYSS_HAS_RESET_STATUS),
1086         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1087                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1088         .sysc_fields    = &omap_hwmod_sysc_type1,
1089 };
1090
1091 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1092         .name = "dma",
1093         .sysc = &omap3xxx_dma_sysc,
1094 };
1095
1096 /* dma_system */
1097 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1098         .name           = "dma",
1099         .class          = &omap3xxx_dma_hwmod_class,
1100         .mpu_irqs       = omap2_dma_system_irqs,
1101         .main_clk       = "core_l3_ick",
1102         .prcm = {
1103                 .omap2 = {
1104                         .module_offs            = CORE_MOD,
1105                         .prcm_reg_id            = 1,
1106                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1107                         .idlest_reg_id          = 1,
1108                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1109                 },
1110         },
1111         .dev_attr       = &dma_dev_attr,
1112         .flags          = HWMOD_NO_IDLEST,
1113 };
1114
1115 /*
1116  * 'mcbsp' class
1117  * multi channel buffered serial port controller
1118  */
1119
1120 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1121         .sysc_offs      = 0x008c,
1122         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1123                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1124         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1125         .sysc_fields    = &omap_hwmod_sysc_type1,
1126         .clockact       = 0x2,
1127 };
1128
1129 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1130         .name = "mcbsp",
1131         .sysc = &omap3xxx_mcbsp_sysc,
1132         .rev  = MCBSP_CONFIG_TYPE3,
1133 };
1134
1135 /* McBSP functional clock mapping */
1136 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1137         { .role = "pad_fck", .clk = "mcbsp_clks" },
1138         { .role = "prcm_fck", .clk = "core_96m_fck" },
1139 };
1140
1141 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1142         { .role = "pad_fck", .clk = "mcbsp_clks" },
1143         { .role = "prcm_fck", .clk = "per_96m_fck" },
1144 };
1145
1146 /* mcbsp1 */
1147 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1148         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1149         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1150         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1151         { .irq = -1 },
1152 };
1153
1154 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1155         .name           = "mcbsp1",
1156         .class          = &omap3xxx_mcbsp_hwmod_class,
1157         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1158         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1159         .main_clk       = "mcbsp1_fck",
1160         .prcm           = {
1161                 .omap2 = {
1162                         .prcm_reg_id = 1,
1163                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1164                         .module_offs = CORE_MOD,
1165                         .idlest_reg_id = 1,
1166                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1167                 },
1168         },
1169         .opt_clks       = mcbsp15_opt_clks,
1170         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1171 };
1172
1173 /* mcbsp2 */
1174 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1175         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1176         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1177         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1178         { .irq = -1 },
1179 };
1180
1181 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1182         .sidetone       = "mcbsp2_sidetone",
1183 };
1184
1185 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1186         .name           = "mcbsp2",
1187         .class          = &omap3xxx_mcbsp_hwmod_class,
1188         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1189         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1190         .main_clk       = "mcbsp2_fck",
1191         .prcm           = {
1192                 .omap2 = {
1193                         .prcm_reg_id = 1,
1194                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1195                         .module_offs = OMAP3430_PER_MOD,
1196                         .idlest_reg_id = 1,
1197                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1198                 },
1199         },
1200         .opt_clks       = mcbsp234_opt_clks,
1201         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1202         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1203 };
1204
1205 /* mcbsp3 */
1206 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1207         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1208         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1209         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1210         { .irq = -1 },
1211 };
1212
1213 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1214         .sidetone       = "mcbsp3_sidetone",
1215 };
1216
1217 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1218         .name           = "mcbsp3",
1219         .class          = &omap3xxx_mcbsp_hwmod_class,
1220         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1221         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1222         .main_clk       = "mcbsp3_fck",
1223         .prcm           = {
1224                 .omap2 = {
1225                         .prcm_reg_id = 1,
1226                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1227                         .module_offs = OMAP3430_PER_MOD,
1228                         .idlest_reg_id = 1,
1229                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1230                 },
1231         },
1232         .opt_clks       = mcbsp234_opt_clks,
1233         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1234         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1235 };
1236
1237 /* mcbsp4 */
1238 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1239         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1240         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1241         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1242         { .irq = -1 },
1243 };
1244
1245 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1246         { .name = "rx", .dma_req = 20 },
1247         { .name = "tx", .dma_req = 19 },
1248         { .dma_req = -1 }
1249 };
1250
1251 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1252         .name           = "mcbsp4",
1253         .class          = &omap3xxx_mcbsp_hwmod_class,
1254         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1255         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1256         .main_clk       = "mcbsp4_fck",
1257         .prcm           = {
1258                 .omap2 = {
1259                         .prcm_reg_id = 1,
1260                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1261                         .module_offs = OMAP3430_PER_MOD,
1262                         .idlest_reg_id = 1,
1263                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1264                 },
1265         },
1266         .opt_clks       = mcbsp234_opt_clks,
1267         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1268 };
1269
1270 /* mcbsp5 */
1271 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1272         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1273         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1274         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1275         { .irq = -1 },
1276 };
1277
1278 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1279         { .name = "rx", .dma_req = 22 },
1280         { .name = "tx", .dma_req = 21 },
1281         { .dma_req = -1 }
1282 };
1283
1284 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1285         .name           = "mcbsp5",
1286         .class          = &omap3xxx_mcbsp_hwmod_class,
1287         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1288         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1289         .main_clk       = "mcbsp5_fck",
1290         .prcm           = {
1291                 .omap2 = {
1292                         .prcm_reg_id = 1,
1293                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1294                         .module_offs = CORE_MOD,
1295                         .idlest_reg_id = 1,
1296                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1297                 },
1298         },
1299         .opt_clks       = mcbsp15_opt_clks,
1300         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1301 };
1302
1303 /* 'mcbsp sidetone' class */
1304 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1305         .sysc_offs      = 0x0010,
1306         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1307         .sysc_fields    = &omap_hwmod_sysc_type1,
1308 };
1309
1310 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1311         .name = "mcbsp_sidetone",
1312         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1313 };
1314
1315 /* mcbsp2_sidetone */
1316 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1317         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1318         { .irq = -1 },
1319 };
1320
1321 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1322         .name           = "mcbsp2_sidetone",
1323         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1324         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1325         .main_clk       = "mcbsp2_fck",
1326         .prcm           = {
1327                 .omap2 = {
1328                         .prcm_reg_id = 1,
1329                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1330                         .module_offs = OMAP3430_PER_MOD,
1331                         .idlest_reg_id = 1,
1332                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1333                 },
1334         },
1335 };
1336
1337 /* mcbsp3_sidetone */
1338 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1339         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1340         { .irq = -1 },
1341 };
1342
1343 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1344         .name           = "mcbsp3_sidetone",
1345         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1346         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1347         .main_clk       = "mcbsp3_fck",
1348         .prcm           = {
1349                 .omap2 = {
1350                         .prcm_reg_id = 1,
1351                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1352                         .module_offs = OMAP3430_PER_MOD,
1353                         .idlest_reg_id = 1,
1354                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1355                 },
1356         },
1357 };
1358
1359 /* SR common */
1360 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1361         .clkact_shift   = 20,
1362 };
1363
1364 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1365         .sysc_offs      = 0x24,
1366         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1367         .clockact       = CLOCKACT_TEST_ICLK,
1368         .sysc_fields    = &omap34xx_sr_sysc_fields,
1369 };
1370
1371 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1372         .name = "smartreflex",
1373         .sysc = &omap34xx_sr_sysc,
1374         .rev  = 1,
1375 };
1376
1377 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1378         .sidle_shift    = 24,
1379         .enwkup_shift   = 26,
1380 };
1381
1382 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1383         .sysc_offs      = 0x38,
1384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1385         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1386                         SYSC_NO_CACHE),
1387         .sysc_fields    = &omap36xx_sr_sysc_fields,
1388 };
1389
1390 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1391         .name = "smartreflex",
1392         .sysc = &omap36xx_sr_sysc,
1393         .rev  = 2,
1394 };
1395
1396 /* SR1 */
1397 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1398         .sensor_voltdm_name   = "mpu_iva",
1399 };
1400
1401 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1402         { .irq = 18 + OMAP_INTC_START, },
1403         { .irq = -1 },
1404 };
1405
1406 static struct omap_hwmod omap34xx_sr1_hwmod = {
1407         .name           = "smartreflex_mpu_iva",
1408         .class          = &omap34xx_smartreflex_hwmod_class,
1409         .main_clk       = "sr1_fck",
1410         .prcm           = {
1411                 .omap2 = {
1412                         .prcm_reg_id = 1,
1413                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1414                         .module_offs = WKUP_MOD,
1415                         .idlest_reg_id = 1,
1416                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1417                 },
1418         },
1419         .dev_attr       = &sr1_dev_attr,
1420         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1421         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1422 };
1423
1424 static struct omap_hwmod omap36xx_sr1_hwmod = {
1425         .name           = "smartreflex_mpu_iva",
1426         .class          = &omap36xx_smartreflex_hwmod_class,
1427         .main_clk       = "sr1_fck",
1428         .prcm           = {
1429                 .omap2 = {
1430                         .prcm_reg_id = 1,
1431                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1432                         .module_offs = WKUP_MOD,
1433                         .idlest_reg_id = 1,
1434                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1435                 },
1436         },
1437         .dev_attr       = &sr1_dev_attr,
1438         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1439 };
1440
1441 /* SR2 */
1442 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1443         .sensor_voltdm_name     = "core",
1444 };
1445
1446 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1447         { .irq = 19 + OMAP_INTC_START, },
1448         { .irq = -1 },
1449 };
1450
1451 static struct omap_hwmod omap34xx_sr2_hwmod = {
1452         .name           = "smartreflex_core",
1453         .class          = &omap34xx_smartreflex_hwmod_class,
1454         .main_clk       = "sr2_fck",
1455         .prcm           = {
1456                 .omap2 = {
1457                         .prcm_reg_id = 1,
1458                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1459                         .module_offs = WKUP_MOD,
1460                         .idlest_reg_id = 1,
1461                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1462                 },
1463         },
1464         .dev_attr       = &sr2_dev_attr,
1465         .mpu_irqs       = omap3_smartreflex_core_irqs,
1466         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1467 };
1468
1469 static struct omap_hwmod omap36xx_sr2_hwmod = {
1470         .name           = "smartreflex_core",
1471         .class          = &omap36xx_smartreflex_hwmod_class,
1472         .main_clk       = "sr2_fck",
1473         .prcm           = {
1474                 .omap2 = {
1475                         .prcm_reg_id = 1,
1476                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1477                         .module_offs = WKUP_MOD,
1478                         .idlest_reg_id = 1,
1479                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1480                 },
1481         },
1482         .dev_attr       = &sr2_dev_attr,
1483         .mpu_irqs       = omap3_smartreflex_core_irqs,
1484 };
1485
1486 /*
1487  * 'mailbox' class
1488  * mailbox module allowing communication between the on-chip processors
1489  * using a queued mailbox-interrupt mechanism.
1490  */
1491
1492 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1493         .rev_offs       = 0x000,
1494         .sysc_offs      = 0x010,
1495         .syss_offs      = 0x014,
1496         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1497                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1498         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1499         .sysc_fields    = &omap_hwmod_sysc_type1,
1500 };
1501
1502 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1503         .name = "mailbox",
1504         .sysc = &omap3xxx_mailbox_sysc,
1505 };
1506
1507 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1508         { .irq = 26 + OMAP_INTC_START, },
1509         { .irq = -1 },
1510 };
1511
1512 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1513         .name           = "mailbox",
1514         .class          = &omap3xxx_mailbox_hwmod_class,
1515         .mpu_irqs       = omap3xxx_mailbox_irqs,
1516         .main_clk       = "mailboxes_ick",
1517         .prcm           = {
1518                 .omap2 = {
1519                         .prcm_reg_id = 1,
1520                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1521                         .module_offs = CORE_MOD,
1522                         .idlest_reg_id = 1,
1523                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1524                 },
1525         },
1526 };
1527
1528 /*
1529  * 'mcspi' class
1530  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1531  * bus
1532  */
1533
1534 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1535         .rev_offs       = 0x0000,
1536         .sysc_offs      = 0x0010,
1537         .syss_offs      = 0x0014,
1538         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1539                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1540                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1542         .sysc_fields    = &omap_hwmod_sysc_type1,
1543 };
1544
1545 static struct omap_hwmod_class omap34xx_mcspi_class = {
1546         .name = "mcspi",
1547         .sysc = &omap34xx_mcspi_sysc,
1548         .rev = OMAP3_MCSPI_REV,
1549 };
1550
1551 /* mcspi1 */
1552 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1553         .num_chipselect = 4,
1554 };
1555
1556 static struct omap_hwmod omap34xx_mcspi1 = {
1557         .name           = "mcspi1",
1558         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1559         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1560         .main_clk       = "mcspi1_fck",
1561         .prcm           = {
1562                 .omap2 = {
1563                         .module_offs = CORE_MOD,
1564                         .prcm_reg_id = 1,
1565                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1566                         .idlest_reg_id = 1,
1567                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1568                 },
1569         },
1570         .class          = &omap34xx_mcspi_class,
1571         .dev_attr       = &omap_mcspi1_dev_attr,
1572 };
1573
1574 /* mcspi2 */
1575 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1576         .num_chipselect = 2,
1577 };
1578
1579 static struct omap_hwmod omap34xx_mcspi2 = {
1580         .name           = "mcspi2",
1581         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1582         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1583         .main_clk       = "mcspi2_fck",
1584         .prcm           = {
1585                 .omap2 = {
1586                         .module_offs = CORE_MOD,
1587                         .prcm_reg_id = 1,
1588                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1589                         .idlest_reg_id = 1,
1590                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1591                 },
1592         },
1593         .class          = &omap34xx_mcspi_class,
1594         .dev_attr       = &omap_mcspi2_dev_attr,
1595 };
1596
1597 /* mcspi3 */
1598 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1599         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1600         { .irq = -1 },
1601 };
1602
1603 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1604         { .name = "tx0", .dma_req = 15 },
1605         { .name = "rx0", .dma_req = 16 },
1606         { .name = "tx1", .dma_req = 23 },
1607         { .name = "rx1", .dma_req = 24 },
1608         { .dma_req = -1 }
1609 };
1610
1611 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1612         .num_chipselect = 2,
1613 };
1614
1615 static struct omap_hwmod omap34xx_mcspi3 = {
1616         .name           = "mcspi3",
1617         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1618         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1619         .main_clk       = "mcspi3_fck",
1620         .prcm           = {
1621                 .omap2 = {
1622                         .module_offs = CORE_MOD,
1623                         .prcm_reg_id = 1,
1624                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1625                         .idlest_reg_id = 1,
1626                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1627                 },
1628         },
1629         .class          = &omap34xx_mcspi_class,
1630         .dev_attr       = &omap_mcspi3_dev_attr,
1631 };
1632
1633 /* mcspi4 */
1634 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1635         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1636         { .irq = -1 },
1637 };
1638
1639 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1640         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1641         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1642         { .dma_req = -1 }
1643 };
1644
1645 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1646         .num_chipselect = 1,
1647 };
1648
1649 static struct omap_hwmod omap34xx_mcspi4 = {
1650         .name           = "mcspi4",
1651         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1652         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1653         .main_clk       = "mcspi4_fck",
1654         .prcm           = {
1655                 .omap2 = {
1656                         .module_offs = CORE_MOD,
1657                         .prcm_reg_id = 1,
1658                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1659                         .idlest_reg_id = 1,
1660                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1661                 },
1662         },
1663         .class          = &omap34xx_mcspi_class,
1664         .dev_attr       = &omap_mcspi4_dev_attr,
1665 };
1666
1667 /* usbhsotg */
1668 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1669         .rev_offs       = 0x0400,
1670         .sysc_offs      = 0x0404,
1671         .syss_offs      = 0x0408,
1672         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1673                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1674                           SYSC_HAS_AUTOIDLE),
1675         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1676                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1677         .sysc_fields    = &omap_hwmod_sysc_type1,
1678 };
1679
1680 static struct omap_hwmod_class usbotg_class = {
1681         .name = "usbotg",
1682         .sysc = &omap3xxx_usbhsotg_sysc,
1683 };
1684
1685 /* usb_otg_hs */
1686 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1687
1688         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1689         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1690         { .irq = -1 },
1691 };
1692
1693 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1694         .name           = "usb_otg_hs",
1695         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1696         .main_clk       = "hsotgusb_ick",
1697         .prcm           = {
1698                 .omap2 = {
1699                         .prcm_reg_id = 1,
1700                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1701                         .module_offs = CORE_MOD,
1702                         .idlest_reg_id = 1,
1703                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1704                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1705                 },
1706         },
1707         .class          = &usbotg_class,
1708
1709         /*
1710          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1711          * broken when autoidle is enabled
1712          * workaround is to disable the autoidle bit at module level.
1713          */
1714         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1715                                 | HWMOD_SWSUP_MSTANDBY,
1716 };
1717
1718 /* usb_otg_hs */
1719 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1720         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1721         { .irq = -1 },
1722 };
1723
1724 static struct omap_hwmod_class am35xx_usbotg_class = {
1725         .name = "am35xx_usbotg",
1726 };
1727
1728 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1729         .name           = "am35x_otg_hs",
1730         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1731         .main_clk       = "hsotgusb_fck",
1732         .class          = &am35xx_usbotg_class,
1733         .flags          = HWMOD_NO_IDLEST,
1734 };
1735
1736 /* MMC/SD/SDIO common */
1737 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1738         .rev_offs       = 0x1fc,
1739         .sysc_offs      = 0x10,
1740         .syss_offs      = 0x14,
1741         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1742                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1743                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1744         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1745         .sysc_fields    = &omap_hwmod_sysc_type1,
1746 };
1747
1748 static struct omap_hwmod_class omap34xx_mmc_class = {
1749         .name = "mmc",
1750         .sysc = &omap34xx_mmc_sysc,
1751 };
1752
1753 /* MMC/SD/SDIO1 */
1754
1755 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1756         { .irq = 83 + OMAP_INTC_START, },
1757         { .irq = -1 },
1758 };
1759
1760 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1761         { .name = "tx", .dma_req = 61, },
1762         { .name = "rx", .dma_req = 62, },
1763         { .dma_req = -1 }
1764 };
1765
1766 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1767         { .role = "dbck", .clk = "omap_32k_fck", },
1768 };
1769
1770 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1771         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1772 };
1773
1774 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1775 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1776         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1777                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1778 };
1779
1780 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1781         .name           = "mmc1",
1782         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1783         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1784         .opt_clks       = omap34xx_mmc1_opt_clks,
1785         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1786         .main_clk       = "mmchs1_fck",
1787         .prcm           = {
1788                 .omap2 = {
1789                         .module_offs = CORE_MOD,
1790                         .prcm_reg_id = 1,
1791                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1792                         .idlest_reg_id = 1,
1793                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1794                 },
1795         },
1796         .dev_attr       = &mmc1_pre_es3_dev_attr,
1797         .class          = &omap34xx_mmc_class,
1798 };
1799
1800 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1801         .name           = "mmc1",
1802         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1803         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1804         .opt_clks       = omap34xx_mmc1_opt_clks,
1805         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1806         .main_clk       = "mmchs1_fck",
1807         .prcm           = {
1808                 .omap2 = {
1809                         .module_offs = CORE_MOD,
1810                         .prcm_reg_id = 1,
1811                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1812                         .idlest_reg_id = 1,
1813                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1814                 },
1815         },
1816         .dev_attr       = &mmc1_dev_attr,
1817         .class          = &omap34xx_mmc_class,
1818 };
1819
1820 /* MMC/SD/SDIO2 */
1821
1822 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1823         { .irq = 86 + OMAP_INTC_START, },
1824         { .irq = -1 },
1825 };
1826
1827 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1828         { .name = "tx", .dma_req = 47, },
1829         { .name = "rx", .dma_req = 48, },
1830         { .dma_req = -1 }
1831 };
1832
1833 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1834         { .role = "dbck", .clk = "omap_32k_fck", },
1835 };
1836
1837 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1838 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1839         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1840 };
1841
1842 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1843         .name           = "mmc2",
1844         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1845         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1846         .opt_clks       = omap34xx_mmc2_opt_clks,
1847         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1848         .main_clk       = "mmchs2_fck",
1849         .prcm           = {
1850                 .omap2 = {
1851                         .module_offs = CORE_MOD,
1852                         .prcm_reg_id = 1,
1853                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1854                         .idlest_reg_id = 1,
1855                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1856                 },
1857         },
1858         .dev_attr       = &mmc2_pre_es3_dev_attr,
1859         .class          = &omap34xx_mmc_class,
1860 };
1861
1862 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1863         .name           = "mmc2",
1864         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1865         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1866         .opt_clks       = omap34xx_mmc2_opt_clks,
1867         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1868         .main_clk       = "mmchs2_fck",
1869         .prcm           = {
1870                 .omap2 = {
1871                         .module_offs = CORE_MOD,
1872                         .prcm_reg_id = 1,
1873                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1874                         .idlest_reg_id = 1,
1875                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1876                 },
1877         },
1878         .class          = &omap34xx_mmc_class,
1879 };
1880
1881 /* MMC/SD/SDIO3 */
1882
1883 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1884         { .irq = 94 + OMAP_INTC_START, },
1885         { .irq = -1 },
1886 };
1887
1888 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1889         { .name = "tx", .dma_req = 77, },
1890         { .name = "rx", .dma_req = 78, },
1891         { .dma_req = -1 }
1892 };
1893
1894 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1895         { .role = "dbck", .clk = "omap_32k_fck", },
1896 };
1897
1898 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1899         .name           = "mmc3",
1900         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1901         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1902         .opt_clks       = omap34xx_mmc3_opt_clks,
1903         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1904         .main_clk       = "mmchs3_fck",
1905         .prcm           = {
1906                 .omap2 = {
1907                         .prcm_reg_id = 1,
1908                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1909                         .idlest_reg_id = 1,
1910                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1911                 },
1912         },
1913         .class          = &omap34xx_mmc_class,
1914 };
1915
1916 /*
1917  * 'usb_host_hs' class
1918  * high-speed multi-port usb host controller
1919  */
1920
1921 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1922         .rev_offs       = 0x0000,
1923         .sysc_offs      = 0x0010,
1924         .syss_offs      = 0x0014,
1925         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1926                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1927                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1928         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1929                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1930         .sysc_fields    = &omap_hwmod_sysc_type1,
1931 };
1932
1933 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1934         .name = "usb_host_hs",
1935         .sysc = &omap3xxx_usb_host_hs_sysc,
1936 };
1937
1938 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1939           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1940 };
1941
1942 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1943         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1944         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1945         { .irq = -1 },
1946 };
1947
1948 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1949         .name           = "usb_host_hs",
1950         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1951         .clkdm_name     = "l3_init_clkdm",
1952         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1953         .main_clk       = "usbhost_48m_fck",
1954         .prcm = {
1955                 .omap2 = {
1956                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1957                         .prcm_reg_id = 1,
1958                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1959                         .idlest_reg_id = 1,
1960                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1961                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1962                 },
1963         },
1964         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1965         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1966
1967         /*
1968          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1969          * id: i660
1970          *
1971          * Description:
1972          * In the following configuration :
1973          * - USBHOST module is set to smart-idle mode
1974          * - PRCM asserts idle_req to the USBHOST module ( This typically
1975          *   happens when the system is going to a low power mode : all ports
1976          *   have been suspended, the master part of the USBHOST module has
1977          *   entered the standby state, and SW has cut the functional clocks)
1978          * - an USBHOST interrupt occurs before the module is able to answer
1979          *   idle_ack, typically a remote wakeup IRQ.
1980          * Then the USB HOST module will enter a deadlock situation where it
1981          * is no more accessible nor functional.
1982          *
1983          * Workaround:
1984          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1985          */
1986
1987         /*
1988          * Errata: USB host EHCI may stall when entering smart-standby mode
1989          * Id: i571
1990          *
1991          * Description:
1992          * When the USBHOST module is set to smart-standby mode, and when it is
1993          * ready to enter the standby state (i.e. all ports are suspended and
1994          * all attached devices are in suspend mode), then it can wrongly assert
1995          * the Mstandby signal too early while there are still some residual OCP
1996          * transactions ongoing. If this condition occurs, the internal state
1997          * machine may go to an undefined state and the USB link may be stuck
1998          * upon the next resume.
1999          *
2000          * Workaround:
2001          * Don't use smart standby; use only force standby,
2002          * hence HWMOD_SWSUP_MSTANDBY
2003          */
2004
2005         /*
2006          * During system boot; If the hwmod framework resets the module
2007          * the module will have smart idle settings; which can lead to deadlock
2008          * (above Errata Id:i660); so, dont reset the module during boot;
2009          * Use HWMOD_INIT_NO_RESET.
2010          */
2011
2012         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
2013                           HWMOD_INIT_NO_RESET,
2014 };
2015
2016 /*
2017  * 'usb_tll_hs' class
2018  * usb_tll_hs module is the adapter on the usb_host_hs ports
2019  */
2020 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
2021         .rev_offs       = 0x0000,
2022         .sysc_offs      = 0x0010,
2023         .syss_offs      = 0x0014,
2024         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2025                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2026                            SYSC_HAS_AUTOIDLE),
2027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2028         .sysc_fields    = &omap_hwmod_sysc_type1,
2029 };
2030
2031 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
2032         .name = "usb_tll_hs",
2033         .sysc = &omap3xxx_usb_tll_hs_sysc,
2034 };
2035
2036 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2037         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2038         { .irq = -1 },
2039 };
2040
2041 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2042         .name           = "usb_tll_hs",
2043         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2044         .clkdm_name     = "l3_init_clkdm",
2045         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2046         .main_clk       = "usbtll_fck",
2047         .prcm = {
2048                 .omap2 = {
2049                         .module_offs = CORE_MOD,
2050                         .prcm_reg_id = 3,
2051                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2052                         .idlest_reg_id = 3,
2053                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2054                 },
2055         },
2056 };
2057
2058 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2059         .name           = "hdq1w",
2060         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2061         .main_clk       = "hdq_fck",
2062         .prcm           = {
2063                 .omap2 = {
2064                         .module_offs = CORE_MOD,
2065                         .prcm_reg_id = 1,
2066                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2067                         .idlest_reg_id = 1,
2068                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2069                 },
2070         },
2071         .class          = &omap2_hdq1w_class,
2072 };
2073
2074 /* SAD2D */
2075 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2076         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2077         { .name = "rst_modem_sw", .rst_shift = 1 },
2078 };
2079
2080 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2081         .name                   = "sad2d",
2082 };
2083
2084 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2085         .name           = "sad2d",
2086         .rst_lines      = omap3xxx_sad2d_resets,
2087         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2088         .main_clk       = "sad2d_ick",
2089         .prcm           = {
2090                 .omap2 = {
2091                         .module_offs = CORE_MOD,
2092                         .prcm_reg_id = 1,
2093                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2094                         .idlest_reg_id = 1,
2095                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2096                 },
2097         },
2098         .class          = &omap3xxx_sad2d_class,
2099 };
2100
2101 /*
2102  * '32K sync counter' class
2103  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2104  */
2105 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2106         .rev_offs       = 0x0000,
2107         .sysc_offs      = 0x0004,
2108         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2109         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2110         .sysc_fields    = &omap_hwmod_sysc_type1,
2111 };
2112
2113 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2114         .name   = "counter",
2115         .sysc   = &omap3xxx_counter_sysc,
2116 };
2117
2118 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2119         .name           = "counter_32k",
2120         .class          = &omap3xxx_counter_hwmod_class,
2121         .clkdm_name     = "wkup_clkdm",
2122         .flags          = HWMOD_SWSUP_SIDLE,
2123         .main_clk       = "wkup_32k_fck",
2124         .prcm           = {
2125                 .omap2  = {
2126                         .module_offs = WKUP_MOD,
2127                         .prcm_reg_id = 1,
2128                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2129                         .idlest_reg_id = 1,
2130                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2131                 },
2132         },
2133 };
2134
2135 /*
2136  * 'gpmc' class
2137  * general purpose memory controller
2138  */
2139
2140 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2141         .rev_offs       = 0x0000,
2142         .sysc_offs      = 0x0010,
2143         .syss_offs      = 0x0014,
2144         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2145                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2146         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2147         .sysc_fields    = &omap_hwmod_sysc_type1,
2148 };
2149
2150 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2151         .name   = "gpmc",
2152         .sysc   = &omap3xxx_gpmc_sysc,
2153 };
2154
2155 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2156         { .irq = 20 },
2157         { .irq = -1 }
2158 };
2159
2160 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2161         .name           = "gpmc",
2162         .class          = &omap3xxx_gpmc_hwmod_class,
2163         .clkdm_name     = "core_l3_clkdm",
2164         .mpu_irqs       = omap3xxx_gpmc_irqs,
2165         .main_clk       = "gpmc_fck",
2166         /*
2167          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2168          * block.  It is not being added due to any known bugs with
2169          * resetting the GPMC IP block, but rather because any timings
2170          * set by the bootloader are not being correctly programmed by
2171          * the kernel from the board file or DT data.
2172          * HWMOD_INIT_NO_RESET should be removed ASAP.
2173          */
2174         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2175                            HWMOD_NO_IDLEST),
2176 };
2177
2178 /*
2179  * interfaces
2180  */
2181
2182 /* L3 -> L4_CORE interface */
2183 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2184         .master = &omap3xxx_l3_main_hwmod,
2185         .slave  = &omap3xxx_l4_core_hwmod,
2186         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2187 };
2188
2189 /* L3 -> L4_PER interface */
2190 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2191         .master = &omap3xxx_l3_main_hwmod,
2192         .slave  = &omap3xxx_l4_per_hwmod,
2193         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2194 };
2195
2196 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2197         {
2198                 .pa_start       = 0x68000000,
2199                 .pa_end         = 0x6800ffff,
2200                 .flags          = ADDR_TYPE_RT,
2201         },
2202         { }
2203 };
2204
2205 /* MPU -> L3 interface */
2206 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2207         .master   = &omap3xxx_mpu_hwmod,
2208         .slave    = &omap3xxx_l3_main_hwmod,
2209         .addr     = omap3xxx_l3_main_addrs,
2210         .user   = OCP_USER_MPU,
2211 };
2212
2213 static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
2214         {
2215                 .pa_start       = 0x54000000,
2216                 .pa_end         = 0x547fffff,
2217                 .flags          = ADDR_TYPE_RT,
2218         },
2219         { }
2220 };
2221
2222 /* l3 -> debugss */
2223 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
2224         .master         = &omap3xxx_l3_main_hwmod,
2225         .slave          = &omap3xxx_debugss_hwmod,
2226         .addr           = omap3xxx_l4_emu_addrs,
2227         .user           = OCP_USER_MPU,
2228 };
2229
2230 /* DSS -> l3 */
2231 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2232         .master         = &omap3430es1_dss_core_hwmod,
2233         .slave          = &omap3xxx_l3_main_hwmod,
2234         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2235 };
2236
2237 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2238         .master         = &omap3xxx_dss_core_hwmod,
2239         .slave          = &omap3xxx_l3_main_hwmod,
2240         .fw = {
2241                 .omap2 = {
2242                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2243                         .flags  = OMAP_FIREWALL_L3,
2244                 }
2245         },
2246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2247 };
2248
2249 /* l3_core -> usbhsotg interface */
2250 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2251         .master         = &omap3xxx_usbhsotg_hwmod,
2252         .slave          = &omap3xxx_l3_main_hwmod,
2253         .clk            = "core_l3_ick",
2254         .user           = OCP_USER_MPU,
2255 };
2256
2257 /* l3_core -> am35xx_usbhsotg interface */
2258 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2259         .master         = &am35xx_usbhsotg_hwmod,
2260         .slave          = &omap3xxx_l3_main_hwmod,
2261         .clk            = "hsotgusb_ick",
2262         .user           = OCP_USER_MPU,
2263 };
2264
2265 /* l3_core -> sad2d interface */
2266 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2267         .master         = &omap3xxx_sad2d_hwmod,
2268         .slave          = &omap3xxx_l3_main_hwmod,
2269         .clk            = "core_l3_ick",
2270         .user           = OCP_USER_MPU,
2271 };
2272
2273 /* L4_CORE -> L4_WKUP interface */
2274 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2275         .master = &omap3xxx_l4_core_hwmod,
2276         .slave  = &omap3xxx_l4_wkup_hwmod,
2277         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2278 };
2279
2280 /* L4 CORE -> MMC1 interface */
2281 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2282         .master         = &omap3xxx_l4_core_hwmod,
2283         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2284         .clk            = "mmchs1_ick",
2285         .addr           = omap2430_mmc1_addr_space,
2286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2287         .flags          = OMAP_FIREWALL_L4
2288 };
2289
2290 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2291         .master         = &omap3xxx_l4_core_hwmod,
2292         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2293         .clk            = "mmchs1_ick",
2294         .addr           = omap2430_mmc1_addr_space,
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296         .flags          = OMAP_FIREWALL_L4
2297 };
2298
2299 /* L4 CORE -> MMC2 interface */
2300 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2301         .master         = &omap3xxx_l4_core_hwmod,
2302         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2303         .clk            = "mmchs2_ick",
2304         .addr           = omap2430_mmc2_addr_space,
2305         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2306         .flags          = OMAP_FIREWALL_L4
2307 };
2308
2309 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2310         .master         = &omap3xxx_l4_core_hwmod,
2311         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2312         .clk            = "mmchs2_ick",
2313         .addr           = omap2430_mmc2_addr_space,
2314         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2315         .flags          = OMAP_FIREWALL_L4
2316 };
2317
2318 /* L4 CORE -> MMC3 interface */
2319 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2320         {
2321                 .pa_start       = 0x480ad000,
2322                 .pa_end         = 0x480ad1ff,
2323                 .flags          = ADDR_TYPE_RT,
2324         },
2325         { }
2326 };
2327
2328 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2329         .master         = &omap3xxx_l4_core_hwmod,
2330         .slave          = &omap3xxx_mmc3_hwmod,
2331         .clk            = "mmchs3_ick",
2332         .addr           = omap3xxx_mmc3_addr_space,
2333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2334         .flags          = OMAP_FIREWALL_L4
2335 };
2336
2337 /* L4 CORE -> UART1 interface */
2338 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2339         {
2340                 .pa_start       = OMAP3_UART1_BASE,
2341                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2342                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2343         },
2344         { }
2345 };
2346
2347 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2348         .master         = &omap3xxx_l4_core_hwmod,
2349         .slave          = &omap3xxx_uart1_hwmod,
2350         .clk            = "uart1_ick",
2351         .addr           = omap3xxx_uart1_addr_space,
2352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 /* L4 CORE -> UART2 interface */
2356 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2357         {
2358                 .pa_start       = OMAP3_UART2_BASE,
2359                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2360                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2361         },
2362         { }
2363 };
2364
2365 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2366         .master         = &omap3xxx_l4_core_hwmod,
2367         .slave          = &omap3xxx_uart2_hwmod,
2368         .clk            = "uart2_ick",
2369         .addr           = omap3xxx_uart2_addr_space,
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372
2373 /* L4 PER -> UART3 interface */
2374 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2375         {
2376                 .pa_start       = OMAP3_UART3_BASE,
2377                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2378                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2379         },
2380         { }
2381 };
2382
2383 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2384         .master         = &omap3xxx_l4_per_hwmod,
2385         .slave          = &omap3xxx_uart3_hwmod,
2386         .clk            = "uart3_ick",
2387         .addr           = omap3xxx_uart3_addr_space,
2388         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2389 };
2390
2391 /* L4 PER -> UART4 interface */
2392 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2393         {
2394                 .pa_start       = OMAP3_UART4_BASE,
2395                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2396                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2397         },
2398         { }
2399 };
2400
2401 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2402         .master         = &omap3xxx_l4_per_hwmod,
2403         .slave          = &omap36xx_uart4_hwmod,
2404         .clk            = "uart4_ick",
2405         .addr           = omap36xx_uart4_addr_space,
2406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2407 };
2408
2409 /* AM35xx: L4 CORE -> UART4 interface */
2410 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2411         {
2412                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2413                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2414                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2415         },
2416         { }
2417 };
2418
2419 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2420         .master         = &omap3xxx_l4_core_hwmod,
2421         .slave          = &am35xx_uart4_hwmod,
2422         .clk            = "uart4_ick",
2423         .addr           = am35xx_uart4_addr_space,
2424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2425 };
2426
2427 /* L4 CORE -> I2C1 interface */
2428 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2429         .master         = &omap3xxx_l4_core_hwmod,
2430         .slave          = &omap3xxx_i2c1_hwmod,
2431         .clk            = "i2c1_ick",
2432         .addr           = omap2_i2c1_addr_space,
2433         .fw = {
2434                 .omap2 = {
2435                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2436                         .l4_prot_group = 7,
2437                         .flags  = OMAP_FIREWALL_L4,
2438                 }
2439         },
2440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2441 };
2442
2443 /* L4 CORE -> I2C2 interface */
2444 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2445         .master         = &omap3xxx_l4_core_hwmod,
2446         .slave          = &omap3xxx_i2c2_hwmod,
2447         .clk            = "i2c2_ick",
2448         .addr           = omap2_i2c2_addr_space,
2449         .fw = {
2450                 .omap2 = {
2451                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2452                         .l4_prot_group = 7,
2453                         .flags = OMAP_FIREWALL_L4,
2454                 }
2455         },
2456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2457 };
2458
2459 /* L4 CORE -> I2C3 interface */
2460 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2461         {
2462                 .pa_start       = 0x48060000,
2463                 .pa_end         = 0x48060000 + SZ_128 - 1,
2464                 .flags          = ADDR_TYPE_RT,
2465         },
2466         { }
2467 };
2468
2469 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2470         .master         = &omap3xxx_l4_core_hwmod,
2471         .slave          = &omap3xxx_i2c3_hwmod,
2472         .clk            = "i2c3_ick",
2473         .addr           = omap3xxx_i2c3_addr_space,
2474         .fw = {
2475                 .omap2 = {
2476                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2477                         .l4_prot_group = 7,
2478                         .flags = OMAP_FIREWALL_L4,
2479                 }
2480         },
2481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2482 };
2483
2484 /* L4 CORE -> SR1 interface */
2485 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2486         {
2487                 .pa_start       = OMAP34XX_SR1_BASE,
2488                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2489                 .flags          = ADDR_TYPE_RT,
2490         },
2491         { }
2492 };
2493
2494 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2495         .master         = &omap3xxx_l4_core_hwmod,
2496         .slave          = &omap34xx_sr1_hwmod,
2497         .clk            = "sr_l4_ick",
2498         .addr           = omap3_sr1_addr_space,
2499         .user           = OCP_USER_MPU,
2500 };
2501
2502 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2503         .master         = &omap3xxx_l4_core_hwmod,
2504         .slave          = &omap36xx_sr1_hwmod,
2505         .clk            = "sr_l4_ick",
2506         .addr           = omap3_sr1_addr_space,
2507         .user           = OCP_USER_MPU,
2508 };
2509
2510 /* L4 CORE -> SR1 interface */
2511 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2512         {
2513                 .pa_start       = OMAP34XX_SR2_BASE,
2514                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2515                 .flags          = ADDR_TYPE_RT,
2516         },
2517         { }
2518 };
2519
2520 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2521         .master         = &omap3xxx_l4_core_hwmod,
2522         .slave          = &omap34xx_sr2_hwmod,
2523         .clk            = "sr_l4_ick",
2524         .addr           = omap3_sr2_addr_space,
2525         .user           = OCP_USER_MPU,
2526 };
2527
2528 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2529         .master         = &omap3xxx_l4_core_hwmod,
2530         .slave          = &omap36xx_sr2_hwmod,
2531         .clk            = "sr_l4_ick",
2532         .addr           = omap3_sr2_addr_space,
2533         .user           = OCP_USER_MPU,
2534 };
2535
2536 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2537         {
2538                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2539                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2540                 .flags          = ADDR_TYPE_RT
2541         },
2542         { }
2543 };
2544
2545 /* l4_core -> usbhsotg  */
2546 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2547         .master         = &omap3xxx_l4_core_hwmod,
2548         .slave          = &omap3xxx_usbhsotg_hwmod,
2549         .clk            = "l4_ick",
2550         .addr           = omap3xxx_usbhsotg_addrs,
2551         .user           = OCP_USER_MPU,
2552 };
2553
2554 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2555         {
2556                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2557                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2558                 .flags          = ADDR_TYPE_RT
2559         },
2560         { }
2561 };
2562
2563 /* l4_core -> usbhsotg  */
2564 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2565         .master         = &omap3xxx_l4_core_hwmod,
2566         .slave          = &am35xx_usbhsotg_hwmod,
2567         .clk            = "hsotgusb_ick",
2568         .addr           = am35xx_usbhsotg_addrs,
2569         .user           = OCP_USER_MPU,
2570 };
2571
2572 /* L4_WKUP -> L4_SEC interface */
2573 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2574         .master = &omap3xxx_l4_wkup_hwmod,
2575         .slave  = &omap3xxx_l4_sec_hwmod,
2576         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2577 };
2578
2579 /* IVA2 <- L3 interface */
2580 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2581         .master         = &omap3xxx_l3_main_hwmod,
2582         .slave          = &omap3xxx_iva_hwmod,
2583         .clk            = "core_l3_ick",
2584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2585 };
2586
2587 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2588         {
2589                 .pa_start       = 0x48318000,
2590                 .pa_end         = 0x48318000 + SZ_1K - 1,
2591                 .flags          = ADDR_TYPE_RT
2592         },
2593         { }
2594 };
2595
2596 /* l4_wkup -> timer1 */
2597 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2598         .master         = &omap3xxx_l4_wkup_hwmod,
2599         .slave          = &omap3xxx_timer1_hwmod,
2600         .clk            = "gpt1_ick",
2601         .addr           = omap3xxx_timer1_addrs,
2602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2603 };
2604
2605 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2606         {
2607                 .pa_start       = 0x49032000,
2608                 .pa_end         = 0x49032000 + SZ_1K - 1,
2609                 .flags          = ADDR_TYPE_RT
2610         },
2611         { }
2612 };
2613
2614 /* l4_per -> timer2 */
2615 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2616         .master         = &omap3xxx_l4_per_hwmod,
2617         .slave          = &omap3xxx_timer2_hwmod,
2618         .clk            = "gpt2_ick",
2619         .addr           = omap3xxx_timer2_addrs,
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2624         {
2625                 .pa_start       = 0x49034000,
2626                 .pa_end         = 0x49034000 + SZ_1K - 1,
2627                 .flags          = ADDR_TYPE_RT
2628         },
2629         { }
2630 };
2631
2632 /* l4_per -> timer3 */
2633 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2634         .master         = &omap3xxx_l4_per_hwmod,
2635         .slave          = &omap3xxx_timer3_hwmod,
2636         .clk            = "gpt3_ick",
2637         .addr           = omap3xxx_timer3_addrs,
2638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2639 };
2640
2641 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2642         {
2643                 .pa_start       = 0x49036000,
2644                 .pa_end         = 0x49036000 + SZ_1K - 1,
2645                 .flags          = ADDR_TYPE_RT
2646         },
2647         { }
2648 };
2649
2650 /* l4_per -> timer4 */
2651 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2652         .master         = &omap3xxx_l4_per_hwmod,
2653         .slave          = &omap3xxx_timer4_hwmod,
2654         .clk            = "gpt4_ick",
2655         .addr           = omap3xxx_timer4_addrs,
2656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2657 };
2658
2659 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2660         {
2661                 .pa_start       = 0x49038000,
2662                 .pa_end         = 0x49038000 + SZ_1K - 1,
2663                 .flags          = ADDR_TYPE_RT
2664         },
2665         { }
2666 };
2667
2668 /* l4_per -> timer5 */
2669 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2670         .master         = &omap3xxx_l4_per_hwmod,
2671         .slave          = &omap3xxx_timer5_hwmod,
2672         .clk            = "gpt5_ick",
2673         .addr           = omap3xxx_timer5_addrs,
2674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676
2677 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2678         {
2679                 .pa_start       = 0x4903A000,
2680                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2681                 .flags          = ADDR_TYPE_RT
2682         },
2683         { }
2684 };
2685
2686 /* l4_per -> timer6 */
2687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2688         .master         = &omap3xxx_l4_per_hwmod,
2689         .slave          = &omap3xxx_timer6_hwmod,
2690         .clk            = "gpt6_ick",
2691         .addr           = omap3xxx_timer6_addrs,
2692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2696         {
2697                 .pa_start       = 0x4903C000,
2698                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2699                 .flags          = ADDR_TYPE_RT
2700         },
2701         { }
2702 };
2703
2704 /* l4_per -> timer7 */
2705 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2706         .master         = &omap3xxx_l4_per_hwmod,
2707         .slave          = &omap3xxx_timer7_hwmod,
2708         .clk            = "gpt7_ick",
2709         .addr           = omap3xxx_timer7_addrs,
2710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2711 };
2712
2713 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2714         {
2715                 .pa_start       = 0x4903E000,
2716                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2717                 .flags          = ADDR_TYPE_RT
2718         },
2719         { }
2720 };
2721
2722 /* l4_per -> timer8 */
2723 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2724         .master         = &omap3xxx_l4_per_hwmod,
2725         .slave          = &omap3xxx_timer8_hwmod,
2726         .clk            = "gpt8_ick",
2727         .addr           = omap3xxx_timer8_addrs,
2728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2729 };
2730
2731 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2732         {
2733                 .pa_start       = 0x49040000,
2734                 .pa_end         = 0x49040000 + SZ_1K - 1,
2735                 .flags          = ADDR_TYPE_RT
2736         },
2737         { }
2738 };
2739
2740 /* l4_per -> timer9 */
2741 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2742         .master         = &omap3xxx_l4_per_hwmod,
2743         .slave          = &omap3xxx_timer9_hwmod,
2744         .clk            = "gpt9_ick",
2745         .addr           = omap3xxx_timer9_addrs,
2746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2747 };
2748
2749 /* l4_core -> timer10 */
2750 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2751         .master         = &omap3xxx_l4_core_hwmod,
2752         .slave          = &omap3xxx_timer10_hwmod,
2753         .clk            = "gpt10_ick",
2754         .addr           = omap2_timer10_addrs,
2755         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2756 };
2757
2758 /* l4_core -> timer11 */
2759 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2760         .master         = &omap3xxx_l4_core_hwmod,
2761         .slave          = &omap3xxx_timer11_hwmod,
2762         .clk            = "gpt11_ick",
2763         .addr           = omap2_timer11_addrs,
2764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2765 };
2766
2767 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2768         {
2769                 .pa_start       = 0x48304000,
2770                 .pa_end         = 0x48304000 + SZ_1K - 1,
2771                 .flags          = ADDR_TYPE_RT
2772         },
2773         { }
2774 };
2775
2776 /* l4_core -> timer12 */
2777 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2778         .master         = &omap3xxx_l4_sec_hwmod,
2779         .slave          = &omap3xxx_timer12_hwmod,
2780         .clk            = "gpt12_ick",
2781         .addr           = omap3xxx_timer12_addrs,
2782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2783 };
2784
2785 /* l4_wkup -> wd_timer2 */
2786 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2787         {
2788                 .pa_start       = 0x48314000,
2789                 .pa_end         = 0x4831407f,
2790                 .flags          = ADDR_TYPE_RT
2791         },
2792         { }
2793 };
2794
2795 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2796         .master         = &omap3xxx_l4_wkup_hwmod,
2797         .slave          = &omap3xxx_wd_timer2_hwmod,
2798         .clk            = "wdt2_ick",
2799         .addr           = omap3xxx_wd_timer2_addrs,
2800         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2801 };
2802
2803 /* l4_core -> dss */
2804 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2805         .master         = &omap3xxx_l4_core_hwmod,
2806         .slave          = &omap3430es1_dss_core_hwmod,
2807         .clk            = "dss_ick",
2808         .addr           = omap2_dss_addrs,
2809         .fw = {
2810                 .omap2 = {
2811                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2812                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2813                         .flags  = OMAP_FIREWALL_L4,
2814                 }
2815         },
2816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2817 };
2818
2819 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2820         .master         = &omap3xxx_l4_core_hwmod,
2821         .slave          = &omap3xxx_dss_core_hwmod,
2822         .clk            = "dss_ick",
2823         .addr           = omap2_dss_addrs,
2824         .fw = {
2825                 .omap2 = {
2826                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2827                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2828                         .flags  = OMAP_FIREWALL_L4,
2829                 }
2830         },
2831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2832 };
2833
2834 /* l4_core -> dss_dispc */
2835 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2836         .master         = &omap3xxx_l4_core_hwmod,
2837         .slave          = &omap3xxx_dss_dispc_hwmod,
2838         .clk            = "dss_ick",
2839         .addr           = omap2_dss_dispc_addrs,
2840         .fw = {
2841                 .omap2 = {
2842                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2843                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2844                         .flags  = OMAP_FIREWALL_L4,
2845                 }
2846         },
2847         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2848 };
2849
2850 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2851         {
2852                 .pa_start       = 0x4804FC00,
2853                 .pa_end         = 0x4804FFFF,
2854                 .flags          = ADDR_TYPE_RT
2855         },
2856         { }
2857 };
2858
2859 /* l4_core -> dss_dsi1 */
2860 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2861         .master         = &omap3xxx_l4_core_hwmod,
2862         .slave          = &omap3xxx_dss_dsi1_hwmod,
2863         .clk            = "dss_ick",
2864         .addr           = omap3xxx_dss_dsi1_addrs,
2865         .fw = {
2866                 .omap2 = {
2867                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2868                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2869                         .flags  = OMAP_FIREWALL_L4,
2870                 }
2871         },
2872         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2873 };
2874
2875 /* l4_core -> dss_rfbi */
2876 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2877         .master         = &omap3xxx_l4_core_hwmod,
2878         .slave          = &omap3xxx_dss_rfbi_hwmod,
2879         .clk            = "dss_ick",
2880         .addr           = omap2_dss_rfbi_addrs,
2881         .fw = {
2882                 .omap2 = {
2883                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2884                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2885                         .flags  = OMAP_FIREWALL_L4,
2886                 }
2887         },
2888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2889 };
2890
2891 /* l4_core -> dss_venc */
2892 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2893         .master         = &omap3xxx_l4_core_hwmod,
2894         .slave          = &omap3xxx_dss_venc_hwmod,
2895         .clk            = "dss_ick",
2896         .addr           = omap2_dss_venc_addrs,
2897         .fw = {
2898                 .omap2 = {
2899                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2900                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2901                         .flags  = OMAP_FIREWALL_L4,
2902                 }
2903         },
2904         .flags          = OCPIF_SWSUP_IDLE,
2905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2906 };
2907
2908 /* l4_wkup -> gpio1 */
2909 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2910         {
2911                 .pa_start       = 0x48310000,
2912                 .pa_end         = 0x483101ff,
2913                 .flags          = ADDR_TYPE_RT
2914         },
2915         { }
2916 };
2917
2918 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2919         .master         = &omap3xxx_l4_wkup_hwmod,
2920         .slave          = &omap3xxx_gpio1_hwmod,
2921         .addr           = omap3xxx_gpio1_addrs,
2922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2923 };
2924
2925 /* l4_per -> gpio2 */
2926 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2927         {
2928                 .pa_start       = 0x49050000,
2929                 .pa_end         = 0x490501ff,
2930                 .flags          = ADDR_TYPE_RT
2931         },
2932         { }
2933 };
2934
2935 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2936         .master         = &omap3xxx_l4_per_hwmod,
2937         .slave          = &omap3xxx_gpio2_hwmod,
2938         .addr           = omap3xxx_gpio2_addrs,
2939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2940 };
2941
2942 /* l4_per -> gpio3 */
2943 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2944         {
2945                 .pa_start       = 0x49052000,
2946                 .pa_end         = 0x490521ff,
2947                 .flags          = ADDR_TYPE_RT
2948         },
2949         { }
2950 };
2951
2952 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2953         .master         = &omap3xxx_l4_per_hwmod,
2954         .slave          = &omap3xxx_gpio3_hwmod,
2955         .addr           = omap3xxx_gpio3_addrs,
2956         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2957 };
2958
2959 /*
2960  * 'mmu' class
2961  * The memory management unit performs virtual to physical address translation
2962  * for its requestors.
2963  */
2964
2965 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2966         .rev_offs       = 0x000,
2967         .sysc_offs      = 0x010,
2968         .syss_offs      = 0x014,
2969         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2970                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2971         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2972         .sysc_fields    = &omap_hwmod_sysc_type1,
2973 };
2974
2975 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2976         .name = "mmu",
2977         .sysc = &mmu_sysc,
2978 };
2979
2980 /* mmu isp */
2981
2982 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2983         .da_start       = 0x0,
2984         .da_end         = 0xfffff000,
2985         .nr_tlb_entries = 8,
2986 };
2987
2988 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2989 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2990         { .irq = 24 },
2991         { .irq = -1 }
2992 };
2993
2994 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2995         {
2996                 .pa_start       = 0x480bd400,
2997                 .pa_end         = 0x480bd47f,
2998                 .flags          = ADDR_TYPE_RT,
2999         },
3000         { }
3001 };
3002
3003 /* l4_core -> mmu isp */
3004 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
3005         .master         = &omap3xxx_l4_core_hwmod,
3006         .slave          = &omap3xxx_mmu_isp_hwmod,
3007         .addr           = omap3xxx_mmu_isp_addrs,
3008         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3009 };
3010
3011 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
3012         .name           = "mmu_isp",
3013         .class          = &omap3xxx_mmu_hwmod_class,
3014         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
3015         .main_clk       = "cam_ick",
3016         .dev_attr       = &mmu_isp_dev_attr,
3017         .flags          = HWMOD_NO_IDLEST,
3018 };
3019
3020 #ifdef CONFIG_OMAP_IOMMU_IVA2
3021
3022 /* mmu iva */
3023
3024 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
3025         .da_start       = 0x11000000,
3026         .da_end         = 0xfffff000,
3027         .nr_tlb_entries = 32,
3028 };
3029
3030 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
3031 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
3032         { .irq = 28 },
3033         { .irq = -1 }
3034 };
3035
3036 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
3037         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
3038 };
3039
3040 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
3041         {
3042                 .pa_start       = 0x5d000000,
3043                 .pa_end         = 0x5d00007f,
3044                 .flags          = ADDR_TYPE_RT,
3045         },
3046         { }
3047 };
3048
3049 /* l3_main -> iva mmu */
3050 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
3051         .master         = &omap3xxx_l3_main_hwmod,
3052         .slave          = &omap3xxx_mmu_iva_hwmod,
3053         .addr           = omap3xxx_mmu_iva_addrs,
3054         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3055 };
3056
3057 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3058         .name           = "mmu_iva",
3059         .class          = &omap3xxx_mmu_hwmod_class,
3060         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3061         .rst_lines      = omap3xxx_mmu_iva_resets,
3062         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3063         .main_clk       = "iva2_ck",
3064         .prcm = {
3065                 .omap2 = {
3066                         .module_offs = OMAP3430_IVA2_MOD,
3067                 },
3068         },
3069         .dev_attr       = &mmu_iva_dev_attr,
3070         .flags          = HWMOD_NO_IDLEST,
3071 };
3072
3073 #endif
3074
3075 /* l4_per -> gpio4 */
3076 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3077         {
3078                 .pa_start       = 0x49054000,
3079                 .pa_end         = 0x490541ff,
3080                 .flags          = ADDR_TYPE_RT
3081         },
3082         { }
3083 };
3084
3085 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3086         .master         = &omap3xxx_l4_per_hwmod,
3087         .slave          = &omap3xxx_gpio4_hwmod,
3088         .addr           = omap3xxx_gpio4_addrs,
3089         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3090 };
3091
3092 /* l4_per -> gpio5 */
3093 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3094         {
3095                 .pa_start       = 0x49056000,
3096                 .pa_end         = 0x490561ff,
3097                 .flags          = ADDR_TYPE_RT
3098         },
3099         { }
3100 };
3101
3102 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3103         .master         = &omap3xxx_l4_per_hwmod,
3104         .slave          = &omap3xxx_gpio5_hwmod,
3105         .addr           = omap3xxx_gpio5_addrs,
3106         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3107 };
3108
3109 /* l4_per -> gpio6 */
3110 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3111         {
3112                 .pa_start       = 0x49058000,
3113                 .pa_end         = 0x490581ff,
3114                 .flags          = ADDR_TYPE_RT
3115         },
3116         { }
3117 };
3118
3119 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3120         .master         = &omap3xxx_l4_per_hwmod,
3121         .slave          = &omap3xxx_gpio6_hwmod,
3122         .addr           = omap3xxx_gpio6_addrs,
3123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3124 };
3125
3126 /* dma_system -> L3 */
3127 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3128         .master         = &omap3xxx_dma_system_hwmod,
3129         .slave          = &omap3xxx_l3_main_hwmod,
3130         .clk            = "core_l3_ick",
3131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3132 };
3133
3134 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3135         {
3136                 .pa_start       = 0x48056000,
3137                 .pa_end         = 0x48056fff,
3138                 .flags          = ADDR_TYPE_RT
3139         },
3140         { }
3141 };
3142
3143 /* l4_cfg -> dma_system */
3144 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3145         .master         = &omap3xxx_l4_core_hwmod,
3146         .slave          = &omap3xxx_dma_system_hwmod,
3147         .clk            = "core_l4_ick",
3148         .addr           = omap3xxx_dma_system_addrs,
3149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3150 };
3151
3152 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3153         {
3154                 .name           = "mpu",
3155                 .pa_start       = 0x48074000,
3156                 .pa_end         = 0x480740ff,
3157                 .flags          = ADDR_TYPE_RT
3158         },
3159         { }
3160 };
3161
3162 /* l4_core -> mcbsp1 */
3163 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3164         .master         = &omap3xxx_l4_core_hwmod,
3165         .slave          = &omap3xxx_mcbsp1_hwmod,
3166         .clk            = "mcbsp1_ick",
3167         .addr           = omap3xxx_mcbsp1_addrs,
3168         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3169 };
3170
3171 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3172         {
3173                 .name           = "mpu",
3174                 .pa_start       = 0x49022000,
3175                 .pa_end         = 0x490220ff,
3176                 .flags          = ADDR_TYPE_RT
3177         },
3178         { }
3179 };
3180
3181 /* l4_per -> mcbsp2 */
3182 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3183         .master         = &omap3xxx_l4_per_hwmod,
3184         .slave          = &omap3xxx_mcbsp2_hwmod,
3185         .clk            = "mcbsp2_ick",
3186         .addr           = omap3xxx_mcbsp2_addrs,
3187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3188 };
3189
3190 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3191         {
3192                 .name           = "mpu",
3193                 .pa_start       = 0x49024000,
3194                 .pa_end         = 0x490240ff,
3195                 .flags          = ADDR_TYPE_RT
3196         },
3197         { }
3198 };
3199
3200 /* l4_per -> mcbsp3 */
3201 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3202         .master         = &omap3xxx_l4_per_hwmod,
3203         .slave          = &omap3xxx_mcbsp3_hwmod,
3204         .clk            = "mcbsp3_ick",
3205         .addr           = omap3xxx_mcbsp3_addrs,
3206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3207 };
3208
3209 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3210         {
3211                 .name           = "mpu",
3212                 .pa_start       = 0x49026000,
3213                 .pa_end         = 0x490260ff,
3214                 .flags          = ADDR_TYPE_RT
3215         },
3216         { }
3217 };
3218
3219 /* l4_per -> mcbsp4 */
3220 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3221         .master         = &omap3xxx_l4_per_hwmod,
3222         .slave          = &omap3xxx_mcbsp4_hwmod,
3223         .clk            = "mcbsp4_ick",
3224         .addr           = omap3xxx_mcbsp4_addrs,
3225         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3226 };
3227
3228 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3229         {
3230                 .name           = "mpu",
3231                 .pa_start       = 0x48096000,
3232                 .pa_end         = 0x480960ff,
3233                 .flags          = ADDR_TYPE_RT
3234         },
3235         { }
3236 };
3237
3238 /* l4_core -> mcbsp5 */
3239 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3240         .master         = &omap3xxx_l4_core_hwmod,
3241         .slave          = &omap3xxx_mcbsp5_hwmod,
3242         .clk            = "mcbsp5_ick",
3243         .addr           = omap3xxx_mcbsp5_addrs,
3244         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3245 };
3246
3247 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3248         {
3249                 .name           = "sidetone",
3250                 .pa_start       = 0x49028000,
3251                 .pa_end         = 0x490280ff,
3252                 .flags          = ADDR_TYPE_RT
3253         },
3254         { }
3255 };
3256
3257 /* l4_per -> mcbsp2_sidetone */
3258 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3259         .master         = &omap3xxx_l4_per_hwmod,
3260         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3261         .clk            = "mcbsp2_ick",
3262         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3263         .user           = OCP_USER_MPU,
3264 };
3265
3266 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3267         {
3268                 .name           = "sidetone",
3269                 .pa_start       = 0x4902A000,
3270                 .pa_end         = 0x4902A0ff,
3271                 .flags          = ADDR_TYPE_RT
3272         },
3273         { }
3274 };
3275
3276 /* l4_per -> mcbsp3_sidetone */
3277 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3278         .master         = &omap3xxx_l4_per_hwmod,
3279         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3280         .clk            = "mcbsp3_ick",
3281         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3282         .user           = OCP_USER_MPU,
3283 };
3284
3285 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3286         {
3287                 .pa_start       = 0x48094000,
3288                 .pa_end         = 0x480941ff,
3289                 .flags          = ADDR_TYPE_RT,
3290         },
3291         { }
3292 };
3293
3294 /* l4_core -> mailbox */
3295 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3296         .master         = &omap3xxx_l4_core_hwmod,
3297         .slave          = &omap3xxx_mailbox_hwmod,
3298         .addr           = omap3xxx_mailbox_addrs,
3299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3300 };
3301
3302 /* l4 core -> mcspi1 interface */
3303 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3304         .master         = &omap3xxx_l4_core_hwmod,
3305         .slave          = &omap34xx_mcspi1,
3306         .clk            = "mcspi1_ick",
3307         .addr           = omap2_mcspi1_addr_space,
3308         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3309 };
3310
3311 /* l4 core -> mcspi2 interface */
3312 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3313         .master         = &omap3xxx_l4_core_hwmod,
3314         .slave          = &omap34xx_mcspi2,
3315         .clk            = "mcspi2_ick",
3316         .addr           = omap2_mcspi2_addr_space,
3317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3318 };
3319
3320 /* l4 core -> mcspi3 interface */
3321 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3322         .master         = &omap3xxx_l4_core_hwmod,
3323         .slave          = &omap34xx_mcspi3,
3324         .clk            = "mcspi3_ick",
3325         .addr           = omap2430_mcspi3_addr_space,
3326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3327 };
3328
3329 /* l4 core -> mcspi4 interface */
3330 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3331         {
3332                 .pa_start       = 0x480ba000,
3333                 .pa_end         = 0x480ba0ff,
3334                 .flags          = ADDR_TYPE_RT,
3335         },
3336         { }
3337 };
3338
3339 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3340         .master         = &omap3xxx_l4_core_hwmod,
3341         .slave          = &omap34xx_mcspi4,
3342         .clk            = "mcspi4_ick",
3343         .addr           = omap34xx_mcspi4_addr_space,
3344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3345 };
3346
3347 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3348         .master         = &omap3xxx_usb_host_hs_hwmod,
3349         .slave          = &omap3xxx_l3_main_hwmod,
3350         .clk            = "core_l3_ick",
3351         .user           = OCP_USER_MPU,
3352 };
3353
3354 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3355         {
3356                 .name           = "uhh",
3357                 .pa_start       = 0x48064000,
3358                 .pa_end         = 0x480643ff,
3359                 .flags          = ADDR_TYPE_RT
3360         },
3361         {
3362                 .name           = "ohci",
3363                 .pa_start       = 0x48064400,
3364                 .pa_end         = 0x480647ff,
3365         },
3366         {
3367                 .name           = "ehci",
3368                 .pa_start       = 0x48064800,
3369                 .pa_end         = 0x48064cff,
3370         },
3371         {}
3372 };
3373
3374 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3375         .master         = &omap3xxx_l4_core_hwmod,
3376         .slave          = &omap3xxx_usb_host_hs_hwmod,
3377         .clk            = "usbhost_ick",
3378         .addr           = omap3xxx_usb_host_hs_addrs,
3379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3380 };
3381
3382 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3383         {
3384                 .name           = "tll",
3385                 .pa_start       = 0x48062000,
3386                 .pa_end         = 0x48062fff,
3387                 .flags          = ADDR_TYPE_RT
3388         },
3389         {}
3390 };
3391
3392 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3393         .master         = &omap3xxx_l4_core_hwmod,
3394         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3395         .clk            = "usbtll_ick",
3396         .addr           = omap3xxx_usb_tll_hs_addrs,
3397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3398 };
3399
3400 /* l4_core -> hdq1w interface */
3401 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3402         .master         = &omap3xxx_l4_core_hwmod,
3403         .slave          = &omap3xxx_hdq1w_hwmod,
3404         .clk            = "hdq_ick",
3405         .addr           = omap2_hdq1w_addr_space,
3406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3407         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3408 };
3409
3410 /* l4_wkup -> 32ksync_counter */
3411 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3412         {
3413                 .pa_start       = 0x48320000,
3414                 .pa_end         = 0x4832001f,
3415                 .flags          = ADDR_TYPE_RT
3416         },
3417         { }
3418 };
3419
3420 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3421         {
3422                 .pa_start       = 0x6e000000,
3423                 .pa_end         = 0x6e000fff,
3424                 .flags          = ADDR_TYPE_RT
3425         },
3426         { }
3427 };
3428
3429 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3430         .master         = &omap3xxx_l4_wkup_hwmod,
3431         .slave          = &omap3xxx_counter_32k_hwmod,
3432         .clk            = "omap_32ksync_ick",
3433         .addr           = omap3xxx_counter_32k_addrs,
3434         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3435 };
3436
3437 /* am35xx has Davinci MDIO & EMAC */
3438 static struct omap_hwmod_class am35xx_mdio_class = {
3439         .name = "davinci_mdio",
3440 };
3441
3442 static struct omap_hwmod am35xx_mdio_hwmod = {
3443         .name           = "davinci_mdio",
3444         .class          = &am35xx_mdio_class,
3445         .flags          = HWMOD_NO_IDLEST,
3446 };
3447
3448 /*
3449  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3450  * but this will probably require some additional hwmod core support,
3451  * so is left as a future to-do item.
3452  */
3453 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3454         .master         = &am35xx_mdio_hwmod,
3455         .slave          = &omap3xxx_l3_main_hwmod,
3456         .clk            = "emac_fck",
3457         .user           = OCP_USER_MPU,
3458 };
3459
3460 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3461         {
3462                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3463                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3464                 .flags          = ADDR_TYPE_RT,
3465         },
3466         { }
3467 };
3468
3469 /* l4_core -> davinci mdio  */
3470 /*
3471  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3472  * but this will probably require some additional hwmod core support,
3473  * so is left as a future to-do item.
3474  */
3475 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3476         .master         = &omap3xxx_l4_core_hwmod,
3477         .slave          = &am35xx_mdio_hwmod,
3478         .clk            = "emac_fck",
3479         .addr           = am35xx_mdio_addrs,
3480         .user           = OCP_USER_MPU,
3481 };
3482
3483 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3484         { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
3485         { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
3486         { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
3487         { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3488         { .irq = -1 },
3489 };
3490
3491 static struct omap_hwmod_class am35xx_emac_class = {
3492         .name = "davinci_emac",
3493 };
3494
3495 static struct omap_hwmod am35xx_emac_hwmod = {
3496         .name           = "davinci_emac",
3497         .mpu_irqs       = am35xx_emac_mpu_irqs,
3498         .class          = &am35xx_emac_class,
3499         .flags          = HWMOD_NO_IDLEST,
3500 };
3501
3502 /* l3_core -> davinci emac interface */
3503 /*
3504  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3505  * but this will probably require some additional hwmod core support,
3506  * so is left as a future to-do item.
3507  */
3508 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3509         .master         = &am35xx_emac_hwmod,
3510         .slave          = &omap3xxx_l3_main_hwmod,
3511         .clk            = "emac_ick",
3512         .user           = OCP_USER_MPU,
3513 };
3514
3515 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3516         {
3517                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3518                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3519                 .flags          = ADDR_TYPE_RT,
3520         },
3521         { }
3522 };
3523
3524 /* l4_core -> davinci emac  */
3525 /*
3526  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3527  * but this will probably require some additional hwmod core support,
3528  * so is left as a future to-do item.
3529  */
3530 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3531         .master         = &omap3xxx_l4_core_hwmod,
3532         .slave          = &am35xx_emac_hwmod,
3533         .clk            = "emac_ick",
3534         .addr           = am35xx_emac_addrs,
3535         .user           = OCP_USER_MPU,
3536 };
3537
3538 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3539         .master         = &omap3xxx_l3_main_hwmod,
3540         .slave          = &omap3xxx_gpmc_hwmod,
3541         .clk            = "core_l3_ick",
3542         .addr           = omap3xxx_gpmc_addrs,
3543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3544 };
3545
3546 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3547         &omap3xxx_l3_main__l4_core,
3548         &omap3xxx_l3_main__l4_per,
3549         &omap3xxx_mpu__l3_main,
3550         &omap3xxx_l3_main__l4_debugss,
3551         &omap3xxx_l4_core__l4_wkup,
3552         &omap3xxx_l4_core__mmc3,
3553         &omap3_l4_core__uart1,
3554         &omap3_l4_core__uart2,
3555         &omap3_l4_per__uart3,
3556         &omap3_l4_core__i2c1,
3557         &omap3_l4_core__i2c2,
3558         &omap3_l4_core__i2c3,
3559         &omap3xxx_l4_wkup__l4_sec,
3560         &omap3xxx_l4_wkup__timer1,
3561         &omap3xxx_l4_per__timer2,
3562         &omap3xxx_l4_per__timer3,
3563         &omap3xxx_l4_per__timer4,
3564         &omap3xxx_l4_per__timer5,
3565         &omap3xxx_l4_per__timer6,
3566         &omap3xxx_l4_per__timer7,
3567         &omap3xxx_l4_per__timer8,
3568         &omap3xxx_l4_per__timer9,
3569         &omap3xxx_l4_core__timer10,
3570         &omap3xxx_l4_core__timer11,
3571         &omap3xxx_l4_wkup__wd_timer2,
3572         &omap3xxx_l4_wkup__gpio1,
3573         &omap3xxx_l4_per__gpio2,
3574         &omap3xxx_l4_per__gpio3,
3575         &omap3xxx_l4_per__gpio4,
3576         &omap3xxx_l4_per__gpio5,
3577         &omap3xxx_l4_per__gpio6,
3578         &omap3xxx_dma_system__l3,
3579         &omap3xxx_l4_core__dma_system,
3580         &omap3xxx_l4_core__mcbsp1,
3581         &omap3xxx_l4_per__mcbsp2,
3582         &omap3xxx_l4_per__mcbsp3,
3583         &omap3xxx_l4_per__mcbsp4,
3584         &omap3xxx_l4_core__mcbsp5,
3585         &omap3xxx_l4_per__mcbsp2_sidetone,
3586         &omap3xxx_l4_per__mcbsp3_sidetone,
3587         &omap34xx_l4_core__mcspi1,
3588         &omap34xx_l4_core__mcspi2,
3589         &omap34xx_l4_core__mcspi3,
3590         &omap34xx_l4_core__mcspi4,
3591         &omap3xxx_l4_wkup__counter_32k,
3592         &omap3xxx_l3_main__gpmc,
3593         NULL,
3594 };
3595
3596 /* GP-only hwmod links */
3597 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3598         &omap3xxx_l4_sec__timer12,
3599         NULL
3600 };
3601
3602 /* 3430ES1-only hwmod links */
3603 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3604         &omap3430es1_dss__l3,
3605         &omap3430es1_l4_core__dss,
3606         NULL
3607 };
3608
3609 /* 3430ES2+-only hwmod links */
3610 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3611         &omap3xxx_dss__l3,
3612         &omap3xxx_l4_core__dss,
3613         &omap3xxx_usbhsotg__l3,
3614         &omap3xxx_l4_core__usbhsotg,
3615         &omap3xxx_usb_host_hs__l3_main_2,
3616         &omap3xxx_l4_core__usb_host_hs,
3617         &omap3xxx_l4_core__usb_tll_hs,
3618         NULL
3619 };
3620
3621 /* <= 3430ES3-only hwmod links */
3622 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3623         &omap3xxx_l4_core__pre_es3_mmc1,
3624         &omap3xxx_l4_core__pre_es3_mmc2,
3625         NULL
3626 };
3627
3628 /* 3430ES3+-only hwmod links */
3629 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3630         &omap3xxx_l4_core__es3plus_mmc1,
3631         &omap3xxx_l4_core__es3plus_mmc2,
3632         NULL
3633 };
3634
3635 /* 34xx-only hwmod links (all ES revisions) */
3636 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3637         &omap3xxx_l3__iva,
3638         &omap34xx_l4_core__sr1,
3639         &omap34xx_l4_core__sr2,
3640         &omap3xxx_l4_core__mailbox,
3641         &omap3xxx_l4_core__hdq1w,
3642         &omap3xxx_sad2d__l3,
3643         &omap3xxx_l4_core__mmu_isp,
3644 #ifdef CONFIG_OMAP_IOMMU_IVA2
3645         &omap3xxx_l3_main__mmu_iva,
3646 #endif
3647         NULL
3648 };
3649
3650 /* 36xx-only hwmod links (all ES revisions) */
3651 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3652         &omap3xxx_l3__iva,
3653         &omap36xx_l4_per__uart4,
3654         &omap3xxx_dss__l3,
3655         &omap3xxx_l4_core__dss,
3656         &omap36xx_l4_core__sr1,
3657         &omap36xx_l4_core__sr2,
3658         &omap3xxx_usbhsotg__l3,
3659         &omap3xxx_l4_core__usbhsotg,
3660         &omap3xxx_l4_core__mailbox,
3661         &omap3xxx_usb_host_hs__l3_main_2,
3662         &omap3xxx_l4_core__usb_host_hs,
3663         &omap3xxx_l4_core__usb_tll_hs,
3664         &omap3xxx_l4_core__es3plus_mmc1,
3665         &omap3xxx_l4_core__es3plus_mmc2,
3666         &omap3xxx_l4_core__hdq1w,
3667         &omap3xxx_sad2d__l3,
3668         &omap3xxx_l4_core__mmu_isp,
3669 #ifdef CONFIG_OMAP_IOMMU_IVA2
3670         &omap3xxx_l3_main__mmu_iva,
3671 #endif
3672         NULL
3673 };
3674
3675 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3676         &omap3xxx_dss__l3,
3677         &omap3xxx_l4_core__dss,
3678         &am35xx_usbhsotg__l3,
3679         &am35xx_l4_core__usbhsotg,
3680         &am35xx_l4_core__uart4,
3681         &omap3xxx_usb_host_hs__l3_main_2,
3682         &omap3xxx_l4_core__usb_host_hs,
3683         &omap3xxx_l4_core__usb_tll_hs,
3684         &omap3xxx_l4_core__es3plus_mmc1,
3685         &omap3xxx_l4_core__es3plus_mmc2,
3686         &omap3xxx_l4_core__hdq1w,
3687         &am35xx_mdio__l3,
3688         &am35xx_l4_core__mdio,
3689         &am35xx_emac__l3,
3690         &am35xx_l4_core__emac,
3691         NULL
3692 };
3693
3694 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3695         &omap3xxx_l4_core__dss_dispc,
3696         &omap3xxx_l4_core__dss_dsi1,
3697         &omap3xxx_l4_core__dss_rfbi,
3698         &omap3xxx_l4_core__dss_venc,
3699         NULL
3700 };
3701
3702 int __init omap3xxx_hwmod_init(void)
3703 {
3704         int r;
3705         struct omap_hwmod_ocp_if **h = NULL;
3706         unsigned int rev;
3707
3708         omap_hwmod_init();
3709
3710         /* Register hwmod links common to all OMAP3 */
3711         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3712         if (r < 0)
3713                 return r;
3714
3715         /* Register GP-only hwmod links. */
3716         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3717                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3718                 if (r < 0)
3719                         return r;
3720         }
3721
3722         rev = omap_rev();
3723
3724         /*
3725          * Register hwmod links common to individual OMAP3 families, all
3726          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3727          * All possible revisions should be included in this conditional.
3728          */
3729         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3730             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3731             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3732                 h = omap34xx_hwmod_ocp_ifs;
3733         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3734                 h = am35xx_hwmod_ocp_ifs;
3735         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3736                    rev == OMAP3630_REV_ES1_2) {
3737                 h = omap36xx_hwmod_ocp_ifs;
3738         } else {
3739                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3740                 return -EINVAL;
3741         }
3742
3743         r = omap_hwmod_register_links(h);
3744         if (r < 0)
3745                 return r;
3746
3747         /*
3748          * Register hwmod links specific to certain ES levels of a
3749          * particular family of silicon (e.g., 34xx ES1.0)
3750          */
3751         h = NULL;
3752         if (rev == OMAP3430_REV_ES1_0) {
3753                 h = omap3430es1_hwmod_ocp_ifs;
3754         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3755                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3756                    rev == OMAP3430_REV_ES3_1_2) {
3757                 h = omap3430es2plus_hwmod_ocp_ifs;
3758         }
3759
3760         if (h) {
3761                 r = omap_hwmod_register_links(h);
3762                 if (r < 0)
3763                         return r;
3764         }
3765
3766         h = NULL;
3767         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3768             rev == OMAP3430_REV_ES2_1) {
3769                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3770         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3771                    rev == OMAP3430_REV_ES3_1_2) {
3772                 h = omap3430_es3plus_hwmod_ocp_ifs;
3773         }
3774
3775         if (h)
3776                 r = omap_hwmod_register_links(h);
3777         if (r < 0)
3778                 return r;
3779
3780         /*
3781          * DSS code presumes that dss_core hwmod is handled first,
3782          * _before_ any other DSS related hwmods so register common
3783          * DSS hwmod links last to ensure that dss_core is already
3784          * registered.  Otherwise some change things may happen, for
3785          * ex. if dispc is handled before dss_core and DSS is enabled
3786          * in bootloader DISPC will be reset with outputs enabled
3787          * which sometimes leads to unrecoverable L3 error.  XXX The
3788          * long-term fix to this is to ensure hwmods are set up in
3789          * dependency order in the hwmod core code.
3790          */
3791         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3792
3793         return r;
3794 }