Irq_Restore() and Irq_Save now implemented. Also moved from Cpu.h to cpu specific code.
Mcu corrected and with support from BSW Builder.
Added support for SVC instruction.
Removed unnecessary interrupt enables and disables from Irq_Handler.
Added CAN register definitions.
Fixed bug in variable declaration in PDUR.
Added ifdef for TRUE and FALSE.
Fixed bug in Os_CfgGetAlarmBase().
#define __CM3_CORE_H__\r
#include "stm32f10x.h"\r
\r
+static inline unsigned long _Irq_Save(void)\r
+{\r
+ unsigned long val = __get_PRIMASK();\r
+ Irq_Disable();\r
+ return val;\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+static inline void _Irq_Restore(unsigned mask) {\r
+ __set_PRIMASK(mask);\r
+}\r
+\r
+\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif \r
(MCU_RESET_ON_SLIP << MCU_RESET_ON_SLIP_OFFSET)\r
| (MCU_BYPASS_ON_SLIP << MCU_BYPASS_ON_SLIP_OFFSET)\r
| (MCU_RESET_ON_OSC_FAIL << MCU_RESET_ON_OSC_FAIL_OFFSET)\r
- | (clockSettingsPtr->Pll1 << MCU_REFCLKDIV_OFFSET)\r
- | (clockSettingsPtr->Pll2 << MCU_PLLMUL_OFFSET)\r
- | (clockSettingsPtr->Pll4 << MCU_PLLDIV_OFFSET);\r
+ | ((clockSettingsPtr->Pll1 - 1) << MCU_REFCLKDIV_OFFSET)\r
+ | (((clockSettingsPtr->Pll2 - 1) * 256) << MCU_PLLMUL_OFFSET)\r
+ | ((clockSettingsPtr->Pll4 - 1) << MCU_PLLDIV_OFFSET);\r
\r
\r
/** Setup PLLCTL2\r
| (MCU_SPREADING_RATE << MCU_SPREADING_RATE_OFFSET)\r
| (MCU_BWADJ << MCU_BWADJ_OFFSET)\r
| (MCU_SPREADING_AMOUNT << MCU_SPREADING_AMOUT_OFFSET)\r
- | (clockSettingsPtr->Pll3 << MCU_ODPLL_OFFSET);\r
+ | ((clockSettingsPtr->Pll3 - 1) << MCU_ODPLL_OFFSET);\r
\r
/** - Wait for until clocks are locked */\r
while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF));\r
pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;\r
\r
/** - Setup synchronous peripheral clock dividers for VCLK1 and VCLK2\r
- * 0 = divide by 1\r
+ * 1 = divide by 2\r
*/\r
- systemREG1->VCLKR = 0U;\r
- systemREG1->VCLK2R = 0U;\r
+ systemREG1->VCLKR = 1U;\r
+ systemREG1->VCLK2R = 1U;\r
\r
/** - Setup RTICLK1 and RTICLK2 clocks */\r
systemREG1->RCLKSRC = (0U << 24U) // RTICLK2 divider is 1\r
\r
// PLLCLK = (CLKIN * PLLMUL) / (REFCLKDIV * ODPLL * PLLDIV);\r
\r
- uint32 odpll = (systemREG1->PLLCTL2 & MCU_ODPLL_MASK) >> MCU_ODPLL_OFFSET;\r
- uint32 plldiv = (systemREG1->PLLCTL1 & MCU_PLLDIV_MASK) >> MCU_PLLDIV_OFFSET;\r
- uint32 refclkdiv = (systemREG1->PLLCTL1 & MCU_REFCLKDIV_MASK) >> MCU_REFCLKDIV_OFFSET;\r
- uint32 pllmult = (systemREG1->PLLCTL1 & MCU_PLLMUL_MASK) >> MCU_PLLMUL_OFFSET;\r
+ uint32 odpll = ((systemREG1->PLLCTL2 & MCU_ODPLL_MASK) >> MCU_ODPLL_OFFSET) + 1;\r
+ uint32 plldiv = ((systemREG1->PLLCTL1 & MCU_PLLDIV_MASK) >> MCU_PLLDIV_OFFSET) + 1;\r
+ uint32 refclkdiv = ((systemREG1->PLLCTL1 & MCU_REFCLKDIV_MASK) >> MCU_REFCLKDIV_OFFSET) + 1;\r
+ uint32 pllmult = (((systemREG1->PLLCTL1 & MCU_PLLMUL_MASK) >> MCU_PLLMUL_OFFSET) / 256) + 1;\r
\r
f_sys = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;\r
f_sys = f_sys * pllmult / (refclkdiv * odpll * plldiv);\r
\r
.global Irq_Handler\r
.type Irq_Handler, %function\r
+ \r
+ .global Svc_Handler\r
+ .type Svc_Handler, %function \r
\r
\r
// Registers part of context.\r
Irq_Handler:\r
// Setup return address. This requires subtraction from LR.\r
sub lr, lr, #4\r
- \r
+\r
+Svc_Handler:\r
// Store return stuff on system mode's stack\r
srsdb sp!, #31 // 31 = System mode\r
\r
mov.w r4,#LC_PATTERN\r
str r4,[sp,#C_CONTEXT_OFFS]\r
\r
+ // Preserve r0 in r1 for svc calls\r
+ mov r1, r0\r
+ \r
// Put stack as first arg to Irq_Entry \r
mov r0,sp \r
\r
pop {REG_SAVE,lr}\r
\r
/* Enable interrupts */\r
- cpsie i \r
+ //cpsie i \r
\r
// Return using stuff from stack.\r
rfeia sp!\r
#ifndef CORE_CR4_H_\r
#define CORE_CR4_H_\r
\r
+#include "Std_Types.h"\r
+\r
#define __I volatile const /*!< defines 'read only' permissions */\r
#define __O volatile /*!< defines 'write only' permissions */\r
#define __IO volatile /*!< defines 'read / write' permissions */\r
#define pcrREG ((pcrBASE_t *)0xFFFFE000U)\r
\r
\r
+/*----------------------------------------------------------------------------*/\r
+/* CAN register definition */\r
+\r
+typedef volatile struct\r
+{\r
+ uint32 CTL;\r
+ uint32 SR;\r
+ unsigned : 16;\r
+ unsigned REC : 8;\r
+ unsigned TEC : 8;\r
+ uint32 BTR;\r
+ uint32 IR;\r
+ uint32 TR;\r
+ unsigned : 32;\r
+ uint32 PEC;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 ABOT;\r
+ uint32 TRX;\r
+ uint32 TRx[4];\r
+ uint32 NDX;\r
+ uint32 NDx[4];\r
+ uint32 IPX;\r
+ uint32 IPx[4];\r
+ uint32 MVX;\r
+ uint32 MVx[4];\r
+ unsigned : 32;\r
+ uint32 IPMx[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ struct\r
+ {\r
+ uint32 COM;\r
+ uint32 MASK;\r
+ uint32 ARB;\r
+ uint32 MC;\r
+ uint8 DATx[8];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ } IFx[3];\r
+ uint32 IF3UEy[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 IOTX;\r
+ uint32 IORX;\r
+} Can_RegisterType;\r
+\r
+\r
+#define Can0_Base ((Can_RegisterType *)0xFFF7DC00)\r
+#define Can1_Base ((Can_RegisterType *)0xFFF7DE00)\r
+\r
+\r
+\r
+typedef volatile struct gioBase\r
+{\r
+ unsigned GCR0; /**< 0x0000: Global Control Register */\r
+ unsigned PWDN; /**< 0x0004: Power Down Register */\r
+ unsigned INTDET; /**< 0x0008: Interrupt Detect Regsiter*/\r
+ unsigned POL; /**< 0x000C: Interrupt Polarity Register */\r
+ unsigned INTENASET; /**< 0x0010: Interrupt Enable Set Register */\r
+ unsigned INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */\r
+ unsigned LVLSET; /**< 0x0018: Interrupt Priority Set Register */\r
+ unsigned LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */\r
+ unsigned FLG; /**< 0x0020: Interrupt Flag Register */\r
+ unsigned OFFSET0; /**< 0x0024: Interrupt Offset A Register */\r
+ unsigned OFFSET1; /**< 0x0028: Interrupt Offset B Register */\r
+} gioBASE_t;\r
+\r
+\r
+/** @struct gioPort\r
+* @brief GIO Port Register Definition\r
+*/\r
+/** @typedef gioPORT_t\r
+* @brief GIO Port Register Type Definition\r
+*\r
+* This type is used to access the GIO Port Registers.\r
+*/\r
+typedef volatile struct gioPort\r
+{\r
+ unsigned DIR; /**< 0x0000: Data Direction Register */\r
+ unsigned DIN; /**< 0x0004: Data Input Register */\r
+ unsigned DOUT; /**< 0x0008: Data Output Register */\r
+ unsigned DSET; /**< 0x000C: Data Output Set Register */\r
+ unsigned DCLR; /**< 0x0010: Data Output Clear Register */\r
+ unsigned PDR; /**< 0x0014: Open Drain Regsiter */\r
+ unsigned PULDIS; /**< 0x0018: Pullup Disable Register */\r
+ unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */\r
+} gioPORT_t;\r
+\r
+\r
+/** @def gioREG\r
+* @brief GIO Register Frame Pointer\r
+*\r
+* This pointer is used by the GIO driver to access the gio module registers.\r
+*/\r
+#define gioREG ((gioBASE_t *)0xFFF7BC00U)\r
+\r
+/** @def gioPORTA\r
+* @brief GIO Port (A) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTA\r
+*/\r
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)\r
+\r
+/** @def gioPORTB\r
+* @brief GIO Port (B) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTB\r
+*/\r
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)\r
+\r
+\r
typedef struct\r
{\r
__IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
__I uint32_t CALIB; /*!< SysTick Calibration Register */\r
} SysTick_Type;\r
\r
+\r
static inline void __disable_irq() {\r
__asm volatile("CPSID if");\r
}\r
__asm volatile("CPSIE if");\r
}\r
\r
+static inline unsigned long _Irq_Save(void)\r
+{\r
+ register unsigned long val asm("r0");\r
+ asm("mrs r0, cpsr");\r
+ asm("and r0, r0, #0xC0"); // Mask the I and F bit of CPSR\r
+ __disable_irq();\r
+ return val;\r
+}\r
\r
-\r
+static inline void _Irq_Restore(unsigned mask) {\r
+ if (mask & 0x80) {\r
+ __asm volatile("CPSID i");\r
+ } else {\r
+ __asm volatile("CPSIE i");\r
+ }\r
+ if (mask & 0x40) {\r
+ __asm volatile("CPSID f");\r
+ } else {\r
+ __asm volatile("CPSIE f");\r
+ }\r
+}\r
\r
#endif /* CORE_CR4_H_ */\r
// Get the active interrupt channel
uint8 channel = IrqGetCurrentInterruptSource();
- Irq_Disable();
+ if (channel == 255) {
+ // This irq is a result of a svc call
+ register uint32 irq_vector asm("r1");
+ channel = irq_vector;
+
+ }
+
+ //Irq_Disable();
stack = (uint32_t *)stack_p;
stack = Os_Isr(stack, (void *)Irq_VectorTable[channel]);
- Irq_Enable();
+ //Irq_Enable();
return stack;
}
*/
void Irq_GenerateSoftInt( IrqType vector ) {
- // Todo replace NVIC->STIR = (vector);
+ __asm volatile("svc #0");
}
/**
******************************************************************************/ \r
.section .int_vecs,"ax",%progbits\r
.extern Irq_Handler\r
+ .extern Svc_Handler\r
\r
b Reset_Handler /* Reset? */\r
b Dummy_Irq /* Undefined instruction exception */\r
- b Irq_Handler /* SVC, to be able to use software interrupt instruction. */\r
+ b Svc_Handler /* SVC, to be able to use software interrupt instruction. */\r
b Dummy_Irq /* Prefetch exception */\r
b Dummy_Irq /* Data exception */\r
b Dummy_Irq /* Reserved */\r
static inline uint32_t SysTick_Config(uint32_t ticks)\r
{\r
\r
- /** - Setup NTU source, debug options and disable both counter blocks */\r
- rtiREG1->GCTRL = 0x0;\r
+ /** - Setup NTU source, debug options and disable both counter blocks */\r
+ rtiREG1->GCTRL = 0x0;\r
\r
- /** - Setup timebase for free running counter 0 */\r
- rtiREG1->TBCTRL = 0x0;\r
+ /** - Setup timebase for free running counter 0 */\r
+ rtiREG1->TBCTRL = 0x0;\r
\r
- /** - Enable/Disable capture event sources for both counter blocks */\r
- rtiREG1->CAPCTRL = 0x0;\r
+ /** - Enable/Disable capture event sources for both counter blocks */\r
+ rtiREG1->CAPCTRL = 0x0;\r
\r
- /** - Setup input source compare 0-3 */\r
- rtiREG1->COMPCTRL = 0x0;\r
+ /** - Setup input source compare 0-3 */\r
+ rtiREG1->COMPCTRL = 0x0;\r
\r
- /** - Reset up counter 0 */\r
- rtiREG1->CNT[0U].UCx = 0x00000000U;\r
+ /** - Reset up counter 0 */\r
+ rtiREG1->CNT[0U].UCx = 0x00000000U;\r
\r
- /** - Reset free running counter 0 */\r
- rtiREG1->CNT[0U].FRCx = 0x00000000U;\r
+ /** - Reset free running counter 0 */\r
+ rtiREG1->CNT[0U].FRCx = 0x00000000U;\r
\r
- /** - Setup up counter 0 compare value\r
- * - 0x00000000: Divide by 2^32\r
- * - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1)\r
- */\r
- rtiREG1->CNT[0U].CPUCx = 4U;\r
+ /** - Setup up counter 0 compare value\r
+ * - 0x00000000: Divide by 2^32\r
+ * - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1)\r
+ */\r
+ rtiREG1->CNT[0U].CPUCx = 4U;\r
\r
- /** - Setup compare 0 value. This value is compared with selected free running counter. */\r
- rtiREG1->CMP[0U].COMPx = 9360U;\r
+ /** - Setup compare 0 value. This value is compared with selected free running counter. */\r
+ rtiREG1->CMP[0U].COMPx = ticks / 8;\r
\r
- /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */\r
- rtiREG1->CMP[0U].UDCPx = 9360U;\r
+ /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */\r
+ rtiREG1->CMP[0U].UDCPx = ticks / 8;\r
\r
- /** - Clear all pending interrupts */\r
- rtiREG1->INTFLAG = 0x0;\r
+ /** - Clear all pending interrupts */\r
+ rtiREG1->INTFLAG = 0x0;\r
\r
- /** - Disable all interrupts */\r
- rtiREG1->CLEARINT = 0x0;\r
+ /** - Disable all interrupts */\r
+ rtiREG1->CLEARINT = 0x0;\r
\r
- return (0); /* Function successful */\r
+ return (0);\r
}\r
\r
/**\r
rtiREG1->GCTRL = 0x1;\r
rtiREG1->SETINT = 0x1;\r
\r
-\r
- /* Set SysTick Priority to 3 */\r
- // TODO removeNVIC_SetPriority(SysTick_IRQn, 0x0C);\r
-\r
-#if 0\r
- // SysTick interrupt each 250ms with counter clock equal to 9MHz\r
- if (SysTick_Config((SystemFrequency / 8) / 4)) {\r
- // Capture error\r
- while (1)\r
- ;\r
- }\r
-\r
- // Select HCLK/8 as SysTick clock source\r
- SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);\r
-#endif\r
-\r
}\r
\r
/**\r
\r
MOD_AVAIL+=MCU\r
# System + Communication + Diagnostic\r
-MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE CAN\r
# Additional\r
MOD_AVAIL+=RAMLOG \r
\r
-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Oct 25 12:52:40 CEST 2010\r
+ */\r
+\r
+\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
\r
Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
{\r
- // This parameter shall represent the Data pre-setting to be initialized\r
- .McuRamDefaultValue = 0,\r
-\r
- // This parameter shall represent the MCU RAM section base address\r
- .McuRamSectionBaseAddress = 0,\r
-\r
- // This parameter shall represent the MCU RAM Section size\r
- .McuRamSectionSize = 0xFF,\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
}\r
};\r
-
-
-const Mcu_PerClockConfigType McuPerClockConfigData =
-{
- .AHBClocksEnable = 0,
- .APB1ClocksEnable = 0,
- .APB2ClocksEnable = 0,
-};
\r
Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
{\r
{\r
- .McuClockReferencePointFrequency = 25000000UL,\r
- .Pll1 = 9,\r
- .Pll2 = 8,\r
- .Pll3 = 0,\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 4, // REFCLKDIV\r
+ .Pll2 = 100, // PLLMULT\r
+ .Pll3 = 2, // ODPLL\r
+ .Pll4 = 2, // PLLDIV\r
},\r
};\r
\r
\r
- const Mcu_ConfigType McuConfigData[] = {\r
+const Mcu_ConfigType McuConfigData[] = {\r
{\r
- // Enables/Disables clock failure notification. In case this feature is not supported\r
- // by HW the setting should be disabled.\r
- .McuClockSrcFailureNotification = 0,\r
-\r
- // This parameter shall represent the number of Modes available for the\r
- // MCU. calculationFormula = Number of configured McuModeSettingConf\r
-// .McuNumberOfMcuModes = 1, /* NOT USED */\r
-\r
- // This parameter shall represent the number of RAM sectors available for\r
- // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
- // tingConf\r
- .McuRamSectors = 1,\r
-\r
- // This parameter shall represent the number of clock setting available for\r
- // the MCU.\r
- .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
-\r
- // Default clock frequency used\r
- .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_25MHZ,\r
-\r
- // This parameter relates to the MCU specific reset configuration. This ap-\r
- // plies to the function Mcu_PerformReset, which performs a microcontroller\r
- // reset using the hardware feature of the microcontroller.\r
-// .McuResetSetting = 0, /* NOT USED */\r
-\r
- // This container contains the configuration (parameters) for the\r
- // Clock settings of the MCU. Please see MCU031 for more in-\r
- // formation on the MCU clock settings.\r
- .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
-\r
- // This container contains the configuration (parameters) for the\r
- // Mode setting of the MCU. Please see MCU035 for more infor-\r
- // mation on the MCU mode settings.\r
-// .McuModeSettingConfig = 0,\r
-\r
- // This container contains the configuration (parameters) for the\r
- // RAM Sector setting. Please see MCU030 for more information\r
- // on RAM sec-tor settings.\r
- .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
- },\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
};\r
\r
#endif /*MCU_CFG_C_*/\r
putc(c, stdout);\r
fflush(stdout);\r
#else\r
- arc_putchar(file->_cookie, c);\r
+ arc_putchar((int)file, c);\r
#endif\r
} else {\r
**buf = c;\r
\r
\r
#ifndef CFG_RAMLOG_SIZE\r
-#define CFG_RAMLOG_SIZE 2000\r
+#define CFG_RAMLOG_SIZE 20000\r
#endif\r
\r
#define RAMLOG_MAGIC 1\r
/* Contain the current state of the PDU router. The router is uninitialized\r
* until PduR_Init has been run.\r
*/\r
-PduR_StateType PduRState;\r
+//PduR_StateType PduRState;\r
\r
extern const PduR_PBConfigType *PduRConfig;\r
\r
#define CPU_BIT_ORDER MSB_FIRST \r
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST\r
\r
+#if !defined(FALSE)\r
#define FALSE 0\r
#define TRUE 1\r
+#endif\r
\r
typedef unsigned long boolean; \r
typedef signed char sint8; \r
#define Irq_SuspendOs() Irq_Disable()
#define Irq_ResumeOs() Irq_Enable()
-static inline unsigned long _Irq_Save(void)
-{
- unsigned long val = 0;
- return val;
-}
-
-/*-----------------------------------------------------------------*/
-
-static inline void _Irq_Restore(unsigned mask) {
-
-}
#define CallService(index,param)
\r
if( alarm_id >= Os_CfgGetAlarmCnt() ) {\r
rv = E_OS_ID;\r
- }\r
+ } else {\r
#if (OS_ALARM_CNT!=0)\r
- *info = alarm_list[alarm_id].counter->alarm_base;\r
+ *info = alarm_list[alarm_id].counter->alarm_base;\r
#endif\r
+ }\r
return rv;\r
}\r
\r
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