--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Std_Types.h"\r
+#include "Gpt.h"\r
+#include "Cpu.h"\r
+#include <assert.h>\r
+#include <string.h>\r
+#include "mpc55xx.h"\r
+#include "Mcu.h"\r
+#include "Trace.h"\r
+#include "Det.h"\r
+\r
+// Implementation specific\r
+\r
+#if ( GPT_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+\r
+#define VALID_CHANNEL(_ch) ( Gpt_Global.configured & (1<<(_ch)) )\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+typedef enum\r
+{\r
+ GPT_STATE_STOPPED = 0,\r
+ GPT_STATE_STARTED,\r
+} Gpt_StateType;\r
+\r
+/**\r
+ * Type that holds all global data for Gpt\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Gpt_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Gpt_ConfigType *config;\r
+\r
+ uint8 wakeupEnabled;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[GPT_CHANNEL_CNT];\r
+\r
+} Gpt_GlobalType;\r
+\r
+/**\r
+ * Type that holds data that are specific for a channel\r
+ */\r
+typedef struct\r
+{\r
+ Gpt_StateType state;\r
+} Gpt_UnitType;\r
+\r
+Gpt_UnitType Gpt_Unit[GPT_CHANNEL_CNT];\r
+\r
+// Global config\r
+Gpt_GlobalType Gpt_Global;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * ISR helper-function that handles the HW channels( 0 to 8 )\r
+ *\r
+ * @param channel - Channel that the raised the interrupt\r
+ */\r
+\r
+static void Gpt_IsrCh(Gpt_ChannelType channel)\r
+{\r
+ const Gpt_ConfigType *config;\r
+ int confCh;\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+ assert(confCh != GPT_CHANNEL_ILL);\r
+\r
+ config = &Gpt_Global.config[confCh];\r
+\r
+ if (config->GptChannelMode == GPT_MODE_ONESHOT)\r
+ {\r
+ // Disable the channel\r
+ PIT.EN.R &= ~(1<<channel);\r
+\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+ }\r
+ config->GptNotification();\r
+\r
+ // Clear interrupt\r
+ PIT.FLG.R = (1<<channel); // Added by Mattias 2009-01\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+// Macro that counts leading zeroes.\r
+#define CNTLZW_INV(x) (31-cntlzw(x))\r
+\r
+/**\r
+ * ISR that handles all interrupts to the PIT channels\r
+ * ( NOT the decrementer )\r
+ */\r
+\r
+static void Gpt_Isr(void)\r
+{\r
+ uint32 flgMask= PIT.FLG.R;\r
+ uint8 chNr = 0;\r
+\r
+ // Loop over all interrupts\r
+ for (; flgMask; flgMask&=~(1<<chNr))\r
+ {\r
+ // Find first channel that is requesting service.\r
+ chNr = CNTLZW_INV(flgMask);\r
+ Gpt_IsrCh(chNr);\r
+ // Clear interrupt\r
+ PIT.FLG.R = (1<<chNr);\r
+ }\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Gpt_Init(const Gpt_ConfigType *config)\r
+{\r
+ uint32_t i=0;\r
+ const Gpt_ConfigType *cfg;\r
+ VALIDATE( (Gpt_Global.initRun == STD_OFF), GPT_INIT_SERVICE_ID, GPT_E_ALREADY_INITIALIZED );\r
+#if defined(GPT_VARIANT_PB)\r
+ VALIDATE( (config != NULL ), GPT_INIT_SERVICE_ID, GPT_E_PARAM_CONFIG );\r
+#elif defined(GPT_VARIANT_PC)\r
+ // We don't support GPT_VARIANT_PC\r
+ assert(0);\r
+#endif\r
+ Gpt_ChannelType ch;\r
+\r
+ for (i=0; i<GPT_CHANNEL_CNT; i++)\r
+ {\r
+ Gpt_Global.channelMap[i] = GPT_CHANNEL_ILL;\r
+ }\r
+\r
+ i = 0;\r
+ cfg = config;\r
+ while (cfg->GptChannelId != GPT_CHANNEL_ILL)\r
+ {\r
+ ch = cfg->GptChannelId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Gpt_Global.channelMap[cfg->GptChannelId] = i;\r
+ Gpt_Global.configured |= (1<<ch);\r
+\r
+ if (ch <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ if (cfg->GptNotification != NULL)\r
+ {\r
+ Irq_InstallVector(Gpt_Isr, PIT_PITFLG_RTIF + ch, 1, CPU_Z1);\r
+ }\r
+ }\r
+#if defined(USE_KERNEL)\r
+ // Don't install if we use kernel.. it handles that.\r
+#else\r
+ else if (ch == GPT_CHANNEL_DEC)\r
+ {\r
+ // Decrementer event is default an exception. Use software interrupt 7 as wrapper.\r
+ Irq_InstallVector(config[i].GptNotification, INTC_SSCIR0_CLR7, 1, CPU_Z1);\r
+ }\r
+#endif\r
+\r
+ cfg++;\r
+ i++;\r
+ }\r
+\r
+ Gpt_Global.config = config;\r
+\r
+ Gpt_Global.initRun = STD_ON;\r
+ PIT.CTRL.B.MDIS = 0;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if GPT_DEINIT_API == STD_ON\r
+void Gpt_DeInit(void)\r
+{\r
+ Gpt_ChannelType channel;\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DEINIT_SERVICE_ID, GPT_E_UNINIT );\r
+ for (channel=0; channel<GPT_CHANNEL_CNT; channel++) // Validate that all channels have been stopped\r
+ {\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_DEINIT_SERVICE_ID, GPT_E_BUSY );\r
+ Gpt_StopTimer(channel); // Should this be done here?\r
+ }\r
+ Gpt_Global.initRun = STD_OFF;\r
+ Gpt_Global.configured = 0;\r
+ //_config.config = NULL;\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+// period is in "ticks" !!\r
+void Gpt_StartTimer(Gpt_ChannelType channel, Gpt_ValueType period_ticks)\r
+{\r
+ uint32_t tmp;\r
+ int confCh;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STARTTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STARTTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_STARTTIMER_SERVICE_ID, GPT_E_BUSY );\r
+ // GPT_E_PARAM_VALUE, all have 32-bit so no need to check\r
+\r
+ DEBUG(DEBUG_HIGH, "Gpt_StartTimer ch=%d, period=%d [ticks]\n", channel, period_ticks);\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ uint32 *tlval = (uint32 *)&PIT.TLVAL0;\r
+ uint32 *tval = (uint32 *)&PIT.TVAL0;\r
+\r
+ tlval[channel] = period_ticks;\r
+ tval[channel] = period_ticks;\r
+\r
+ // always select interrupt\r
+ if (channel != GPT_CHANNEL_RTI)\r
+ {\r
+ PIT.INTSEL.R |= ( 1 << channel );\r
+ }\r
+\r
+ // Make sure that no interrupt is pending.\r
+ PIT.FLG.R = ( 1 << channel );\r
+\r
+ // Enable timer\r
+ PIT.EN.R |= ( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ // Enable the TB\r
+ tmp = get_spr(SPR_HID0);\r
+ tmp |= HID0_TBEN;\r
+ set_spr(SPR_HID0,tmp);\r
+\r
+ /* Initialize the Decrementer */\r
+ set_spr(SPR_DEC, period_ticks);\r
+ set_spr(SPR_DECAR, period_ticks);\r
+\r
+ if( Gpt_Global.config[confCh].GptChannelMode == GPT_MODE_CONTINUOUS )\r
+ {\r
+ /* Set autoreload */\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp |= TCR_ARE;\r
+ set_spr(SPR_TCR,tmp);\r
+ }\r
+ }\r
+\r
+ if( Gpt_Global.config[confCh].GptNotification != NULL )\r
+ {\r
+ // GPT275\r
+ Gpt_EnableNotification(channel);\r
+ }\r
+\r
+ Gpt_Unit[channel].state = GPT_STATE_STARTED;\r
+}\r
+\r
+void Gpt_StopTimer(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STOPTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STOPTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ // Disable timer\r
+ PIT.EN.R &= ~( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ uint32 tb;\r
+ tb = get_spr(SPR_HID0);\r
+ tb &= ~HID0_TBEN;\r
+ set_spr(SPR_HID0,tb);\r
+ }\r
+\r
+ Gpt_DisableNotification(channel);\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+}\r
+\r
+#if ( GPT_TIME_REMAINING_API == STD_ON )\r
+\r
+Gpt_ValueType Gpt_GetTimeRemaining(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_UNINIT, 0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+ Gpt_ValueType remaining;\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ uint32 *tval = (uint32 *)&PIT.TVAL0;\r
+ // Time remaining is the time until it hits 0, so just return the current timer value\r
+ remaining = tval[channel];\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ remaining = get_spr(SPR_DEC);\r
+ }\r
+\r
+return remaining;\r
+}\r
+#endif\r
+\r
+#if ( GPT_TIME_ELAPSED_API == STD_ON )\r
+Gpt_ValueType Gpt_GetTimeElapsed(Gpt_ChannelType channel)\r
+{\r
+ Gpt_ValueType timer;\r
+\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_UNINIT ,0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+\r
+ // NOTE!\r
+ // These little creatures count down\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ uint32 *tval = (uint32 *)&PIT.TVAL0;\r
+ uint32 *tlval = (uint32 *)&PIT.TLVAL0;\r
+ timer = tlval[channel] - tval[channel];\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
+ }\r
+\r
+ return (timer);\r
+}\r
+#endif\r
+\r
+#if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
+void Gpt_EnableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x7, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x7, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ // enable interrupts\r
+ PIT.INTEN.R |= ( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ uint32 tmp;\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp |= TCR_DIE;\r
+ set_spr(SPR_TCR, tmp );\r
+ }\r
+}\r
+\r
+void Gpt_DisableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x8, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x8, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_PIT_8)\r
+ {\r
+ PIT.INTEN.R &= ~( 1 << channel );\r
+ }\r
+ else if (channel == GPT_CHANNEL_DEC)\r
+ {\r
+ uint32 tmp;\r
+ tmp = get_spr(SPR_TCR);\r
+ tmp &= ~TCR_DIE;\r
+ set_spr(SPR_TCR, tmp );\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+#endif\r
+\r
+#if ( GPT_WAKEUP_FUNCTIONALITY_API == STD_ON )\r
+\r
+void Gpt_SetMode(Gpt_ModeType mode)\r
+{\r
+ int i;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_SETMODE_SERVIVCE_ID, GPT_E_UNINIT );\r
+ VALIDATE( ( mode <= GPT_MODE_SLEEP ), GPT_SETMODE_SERVIVCE_ID, GPT_E_PARAM_MODE );\r
+\r
+ if (mode == GPT_MODE_NORMAL)\r
+ {\r
+ PIT.CTRL.B.MDIS = 0;\r
+ // Do NOT restart channels\r
+ }\r
+ else if (mode == GPT_MODE_SLEEP)\r
+ {\r
+\r
+ PIT.CTRL.B.MDIS = 1;\r
+ // Disable all but RTI\r
+ for (i= 0; i <= GPT_CHANNEL_PIT_8; i++)\r
+ {\r
+ Gpt_StopTimer(i);\r
+ }\r
+ }\r
+}\r
+\r
+void Gpt_DisableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ // Only RTI have system wakeup\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_OFF;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_EnableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_ON;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_Cbk_CheckWakeup(EcuM_WakeupSourceType wakeupSource)\r
+{\r
+\r
+}\r
+\r
+#endif\r
+\r
\r
void Os_ArchSetupContext( OsPcbType *pcb ) {\r
// TODO: Add lots of things here, see ppc55xx\r
- uint32_t *context = (uint32_t *)pcb->stack.curr;\r
- context[C_CONTEXT_OFF/4] = SC_PATTERN;\r
+// uint16_t *context = (uint16_t *)pcb->stack.curr;\r
+// context[C_CONTEXT_OFF/4] = SC_PATTERN;\r
\r
/* Set LR to start function */\r
- if( pcb->proc_type == PROC_EXTENDED ) {\r
- context[VGPR_LR_OFF/4] = (uint32_t)Os_TaskStartExtended;\r
- } else if( pcb->proc_type == PROC_BASIC ) {\r
- context[VGPR_LR_OFF/4] = (uint32_t)Os_TaskStartBasic;\r
- }\r
- Os_StackSetEndmark(pcb);\r
+// if( pcb->proc_type == PROC_EXTENDED ) {\r
+// context[VGPR_LR_OFF/4] = (uint16_t)Os_TaskStartExtended;\r
+// } else if( pcb->proc_type == PROC_BASIC ) {\r
+// context[VGPR_LR_OFF/4] = (uint16_t)Os_TaskStartBasic;\r
+// }\r
+// Os_StackSetEndmark(pcb);\r
// Os_ArchSetupContext_asm(pcb->stack.curr,NULL);\r
}\r
\r
*/\r
\r
void OsArch_SetTaskEntry(OsPcbType *pcbPtr ) {\r
- uint32_t *context = (uint32_t *)pcbPtr->stack.curr;\r
+ uint16_t *context = (uint16_t *)pcbPtr->stack.curr;\r
\r
- context[C_CONTEXT_OFF/4] = SC_PATTERN;\r
+// context[C_CONTEXT_OFF/4] = SC_PATTERN;\r
\r
- /* Set LR to start function */\r
+ /* Set Return to start function */\r
if( pcbPtr->proc_type == PROC_EXTENDED ) {\r
- context[C_LR_OFF/4] = (uint32_t)Os_TaskStartExtended;\r
+ context[C_RETURN_PPAGE_OFF] = OS_KERNEL_CODE_PPAGE;\r
+ context[C_RETURN_ADDR_OFF] = (uint16_t)Os_TaskStartExtended;\r
} else if( pcbPtr->proc_type == PROC_BASIC ) {\r
- context[C_LR_OFF/4] = (uint32_t)Os_TaskStartBasic;\r
+ context[C_RETURN_PPAGE_OFF] = OS_KERNEL_CODE_PPAGE;\r
+ context[C_RETURN_ADDR_OFF] = (uint16_t)Os_TaskStartBasic;\r
}\r
}\r
\r
--- /dev/null
+\r
+\r
+#define _ASSEMBLER_\r
+#include "kernel_offset.h"\r
+#include "irq_defines.h"\r
+#include "arch_irq.sx"\r
+//#include "arch_offset.h"\r
+//#include "stack.h"\r
+\r
+.extern os_sys\r
+\r
+.section .text\r
+\r
+\r
+DECLARE_IRQ_MAP(IRQ_NR_RES0)\r
+DECLARE_IRQ_MAP(IRQ_NR_RES1)\r
+DECLARE_IRQ_MAP(IRQ_NR_RES2)\r
+DECLARE_IRQ_MAP(IRQ_NR_RES3)\r
+DECLARE_IRQ_MAP(IRQ_NR_RES4)\r
+DECLARE_IRQ_MAP(IRQ_NR_RES5)\r
+DECLARE_IRQ_MAP(IRQ_NR_PWM_SHUTDOWN)\r
+DECLARE_IRQ_MAP(IRQ_NR_PTPIF)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN4_TX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN4_RX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN4_ERR)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN4_WAKE)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN3_TX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN3_RX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN3_ERR)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN3_WAKE)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN2_TX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN2_RX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN2_ERR)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN2_WAKE)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN1_TX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN1_RX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN1_ERR)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN1_WAKE)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN0_TX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN0_RX)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN0_ERR)\r
+DECLARE_IRQ_MAP(IRQ_NR_CAN0_WAKE)\r
+DECLARE_IRQ_MAP(IRQ_NR_FLASH)\r
+DECLARE_IRQ_MAP(IRQ_NR_EEPROM)\r
+DECLARE_IRQ_MAP(IRQ_NR_SPI2)\r
+DECLARE_IRQ_MAP(IRQ_NR_SPI1)\r
+DECLARE_IRQ_MAP(IRQ_NR_IIC)\r
+DECLARE_IRQ_MAP(IRQ_NR_BDLC)\r
+DECLARE_IRQ_MAP(IRQ_NR_SELFCLK_MODE)\r
+DECLARE_IRQ_MAP(IRQ_NR_PLL_LOCK)\r
+DECLARE_IRQ_MAP(IRQ_NR_ACCB_OVERFLOW)\r
+DECLARE_IRQ_MAP(IRQ_NR_MCCNT_UNDERFLOW)\r
+DECLARE_IRQ_MAP(IRQ_NR_PTHIF)\r
+DECLARE_IRQ_MAP(IRQ_NR_PTJIF)\r
+DECLARE_IRQ_MAP(IRQ_NR_ATD1)\r
+DECLARE_IRQ_MAP(IRQ_NR_ATD0)\r
+DECLARE_IRQ_MAP(IRQ_NR_SCI1)\r
+DECLARE_IRQ_MAP(IRQ_NR_SCI0)\r
+DECLARE_IRQ_MAP(IRQ_NR_SPI0)\r
+DECLARE_IRQ_MAP(IRQ_NR_ACCA_INPUT)\r
+DECLARE_IRQ_MAP(IRQ_NR_ACCA_OVERFLOW)\r
+DECLARE_IRQ_MAP(IRQ_NR_TIMER_OVERFLOW)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC7)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC6)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC5)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC4)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC3)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC2)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC1)\r
+DECLARE_IRQ_MAP(IRQ_NR_TC0)\r
+DECLARE_IRQ_MAP(IRQ_NR_RTII)\r
+DECLARE_IRQ_MAP(IRQ_NR_IRQ)\r
+DECLARE_IRQ_MAP(IRQ_NR_XIRQ)\r
+DECLARE_IRQ_MAP(IRQ_NR_SWI)\r
+DECLARE_IRQ_MAP(IRQ_NR_ILLEGAL)\r
+DECLARE_IRQ_MAP(IRQ_NR_COP_FAIL)\r
+DECLARE_IRQ_MAP(IRQ_NR_COP_CLOCK)\r
\r
\r
+/*\r
+ * IVOR4\r
+ * 1. Save stack frames: EXC, VGPR, NVGPR and C\r
+ * 2. Call Irq_Entry(void *curr_stack)\r
+ * 2.1 Check for exception\r
+ * 2.2 If softint, clear it.\r
+ * 2.3 If PROC_ISR1, then just call the function\r
+ * 2.4 If PROC_ISR2 -> it's a PCB, let the OS handle it.\r
+ */\r
+\r
#define _ASSEMBLER_\r
#include "kernel_offset.h"\r
-//#include "arch_offset.h"\r
-//#include "stack.h"\r
-\r
+#include "asm_hc1x.h"\r
+.extern os_intc_pcb_tbl\r
+.extern os_intc_types_tbl\r
.extern os_sys\r
\r
- .section .text\r
-\r
- .global Irq_Handler\r
- .type Irq_Handler, %function\r
+/*\r
+#define LOCK() wrteei 0\r
+#define UNLOCK() wrteei 1\r
+*/\r
\r
#define IRQ_ENABLE() cpsie i\r
#define IRQ_DISABLE() cpsid i\r
\r
-Irq_Handler:\r
-/*\r
- push {r4-r8,r10,r11,lr}\r
- sub.w sp,sp,#C_SIZE\r
- mov.w r4,#LC_PATTERN\r
- str r4,[sp,#C_CONTEXT_OFFS]\r
- mov r0,sp // stack as first arg\r
- bl Irq_Entry\r
- mov sp, r0 // pop from returned stack\r
- b os_lc_restore\r
-*/\r
+.extern os_proc_start_extended\r
\r
-/* r0 - pcb for old task\r
- * r1 pcb for new task\r
+/*--------------------------------------------------------------------\r
+ * void os_swap_context(pcb_t *old, pcb_t *new )\r
*\r
- * -------------- higher addr\r
- * r4-r8,etc\r
- * -------\r
- * 4 - Large or Small context indicator\r
- * 0 - ?\r
- * ---------- <- JABBA\r
+ * Saves a small context on current stack, pops a new one from new context\r
*\r
- */\r
- .global Os_ArchSwapContext\r
- .type Os_ArchSwapContext, %function\r
-Os_ArchSwapContext:\r
-/*\r
-// mov r2, sp\r
- push {r4-r8,r10,r11,lr}\r
+ * r3 - pcb for old process\r
+ * r4 - pcb for new process\r
+ *\r
+ *--------------------------------------------------------------------*/\r
\r
- // Store c-frame\r
- sub.w sp,sp,#C_SIZE\r
+// TODO: this assumes that both are in user mode?.. can this happen under trusted functions?\r
+// When I get here we're ALWAYS in kernel mode\r
\r
- mov.w r4,#SC_PATTERN\r
- str r4,[sp,#C_CONTEXT_OFFS]\r
-// str r2,[sp,#C_SP_OFF]\r
- // ---> We have saved NVGPR+C\r
+.global Os_ArchSwapContextToW\r
+.global Os_ArchSwapContextTo\r
+.global Os_ArchSwapContext\r
+.global Os_ArchSetSpAndCall\r
+.section .text\r
\r
- // store old stack for old task\r
- mov.w r4,sp\r
- str r4,[r0,#PCB_STACK_CURR_P]\r
-*/\r
-// R1 - new PCB\r
- .global Os_ArchSwapContextTo\r
- .type Os_ArchSwapContextTo, %function\r
-Os_ArchSwapContextTo:\r
+Os_ArchSetSpAndCall:\r
/*\r
- // Get stack for new task\r
- ldr r2,[r1,#PCB_STACK_CURR_P]\r
-// msr msp,r2\r
- mov.w sp,r2\r
+ mr r1,r3\r
+ mtlr r4\r
+ blr\r
+*/\r
\r
+Os_ArchSwapContextToW:\r
+/*\r
+ mr r1,r5\r
+ b Os_ArchSwapContextTo\r
+*/\r
\r
-// TODO: Fix this for all arch's..call pre,post hooks. Done here or after?\r
-// Set new current pcb\r
- ldr r5,= os_sys\r
- str r1,[r5,#SYS_CURR_PCB_P]\r
+/* void Os_ArchSwapContext(void *old, void *new); */\r
+Os_ArchSwapContext:\r
+Os_ArchSwapContext_get_args:\r
+ GET_ARG_0_TO_X // old --> X\r
+ GET_ARG_1_TO(y) // new --> Y\r
+ \r
+ movb #0x00, 1,-sp // skip byte\r
+ movw _.frame, 2,-sp // restore _.frame\r
+ movw _.z, 2,-sp // restore _.z\r
+ movw _.xy, 2,-sp // restore _.xy\r
+ movw _.tmp ,2,-sp // restore _.tmp\r
+ pshy // restore Y\r
+ pshx // restore X\r
+ pshd // restore D\r
+ pshc // restore CCR\r
+ movb #0x00, 1,-sp // skip byte\r
+ \r
+ sts PCB_STACK_CURR_P, x // SP --> old->stack.curr\r
+ bra Os_ArchSwapContextTo_do\r
+\r
+\r
+/* void Os_ArchSwapContextTo(void *old, void *new); */\r
+Os_ArchSwapContextTo:\r
+Os_ArchSwapContextTo_get_args:\r
+// Get stack for new task\r
+ GET_ARG_1_TO(y) // new --> Y\r
+ \r
+Os_ArchSwapContextTo_do:\r
+// Set current process\r
+ sty os_sys // new (Y) --> os_sys.curr_pcb\r
+// Restore context\r
+ lds PCB_STACK_CURR_P, y // new->stack.curr --> SP\r
+ ins // skip byte \r
+ pulc // restore CCR\r
+ puld // restore D\r
+ pulx // restore X\r
+ puly // restore Y\r
+ movw 2,sp+,_.tmp // restore _.tmp\r
+ movw 2,sp+,_.xy // restore _.xy\r
+ movw 2,sp+,_.z // restore _.z\r
+ movw 2,sp+,_.frame // restore _.frame\r
+\r
+ ins // skip byte\r
+ \r
+ rtc\r
+/*\r
+// Set new current process\r
+ LOAD_ADDR_32(3,os_sys)\r
+ stw r4,SYS_CURR_PCB_P(r3)\r
\r
// Restore C context\r
- ldr r6,[sp,#C_CONTEXT_OFFS]\r
- cmp r6,#SC_PATTERN\r
- beq os_sc_restore\r
- cmp r6,#LC_PATTERN\r
- beq os_lc_restore\r
+ lwz r0,C_CR_OFF(sp)\r
+ mtcr r0\r
+ lwz r0,C_LR_OFF (sp)\r
+ mtlr r0\r
+\r
+// Get the context type\r
+ lwz r0,C_CONTEXT_OFF(sp)\r
+ cmpli 0,r0,SC_PATTERN\r
+ beq+ os_sc_restore\r
+ cmpli 0,r0,LC_PATTERN\r
+ beq+ os_lc_restore\r
+ b os_bad_bad\r
*/\r
\r
-// Os_ArchSwapContextToW(currPcbPtr ,pcbPtr, pcbPtr->stack.curr );\r
- .global Os_ArchSwapContextToW\r
- .type Os_ArchSwapContextToW, %function\r
-Os_ArchSwapContextToW:\r
+// SC_xxx\r
+// C_xxxx <- We point here\r
+\r
/*\r
+os_sc_restore:\r
+ RESTORE_NVGPR(sp,(C_SIZE-14*GPR_SIZE))\r
+ addi sp,sp,(C_SIZE+NVGPR_SIZE)\r
+ // TODO: The blr will not do the trick if swapping to a user land task.\r
+ blr\r
+\r
+os_lc_restore:\r
+ addi r1,r1,C_SIZE\r
+ RESTORE_NVGPR(1,0)\r
+ addi r1,r1,-C_SIZE\r
+ RESTORE_VGPR(1,C_SIZE)\r
+\r
+ RESTORE_WORK_AND_MORE\r
+ rfi\r
\r
+// When something really bad happens we end up here for the moment\r
+os_bad_bad:\r
+ b os_bad_bad\r
*/\r
\r
- .global Os_ArchSetSpAndCall\r
- .type Os_ArchSetSpAndCall, %function\r
-Os_ArchSetSpAndCall:\r
\r
-os_stack_problem:\r
-// TODO: Jump to error handler\r
-// b os_stack_problem\r
\r
-os_sc_restore:\r
-/*\r
- add.w sp,sp,#C_SIZE\r
+// ------------------------------------------------------------------\r
\r
- pop {r4-r8,r10,r11,lr}\r
- // ehh, we are in handler mode so a bx instruction works here\r
- IRQ_ENABLE()\r
- bx lr\r
-*/\r
-os_lc_restore:\r
/*\r
- add.w sp,sp,#C_SIZE\r
- pop {r4-r8,r10,r11,lr}\r
- // ehh, we are in handler mode so a bx instruction works here\r
- IRQ_ENABLE()\r
- bx lr\r
-*/\r
+ * Trap interface !!!! See article http://www.linuxjournal.com/article/6516\r
+ * http://www.osweekly.com/index.php?option=com_content&task=view&id=2229\r
+ */\r
+\r
+/* The T32 instruction sim can't handle trap's so we have to make something\r
+ * - write SRR0, SRR1, MSR\r
+ * - jump to there routines\r
+ */\r
+\r
+// ------------------------------------------------------------------\r
+\r
+\r
+// System call, use this for trusted function ???\r
+// TODO: The example in autosar is not neccesary.. sc here here instead??\r
+//\r
+// NOTE!!!!!\r
+// Since the sc is a sync call, it should be enough to save NV regs(14->)\r
+// If I don't use the NV regs here I shouldn't need to save them\r
+// TODO: Inform compiler in SC_CALL() that I clobber volatile regs( r0, r3->\r
+// (since the compiler does not know it's a function call)\r
+// TODO: Could probably do this shorter....only NV regs that I use need saving\r
+// ( only cr2->cr4 according to e500 ABI )\r
+\r
+\r
+\r
+\r
\r
\r
/*\r
- * context.h\r
- *\r
- * DESCRIPTION\r
- * ARM Cortex-M3 (architecture ARMv7-M).\r
- *\r
- * REFERENCES\r
- * - Any ABI?\r
- *\r
- * REGISTER USE\r
- * Args\r
- * ?
+ * context.h
*
- * RETURN
- * ?? r0?\r
- *\r
- * Non-volatile regs (saved by function call)\r
- * ?\r
- *\r
- * Misc
- * ?\r
- *\r
- * EXCEPTION FRAME\r
- * ?\r
- *\r
- * EXCEPTION/IRQ TABLE
- * ?\r
*
- * EXCEPTIONS
- * ?\r
- *\r
- * IRQ
- * ?\r
+ * PPAGE
+ * PC
+ * PC
*\r
- * EXCEPTION/IRQ FLOW\r
*/\r
\r
#ifndef CONTEXT_H_\r
#define CONTEXT_H_\r
\r
+#define OS_KERNEL_CODE_PPAGE 0x38
\r
-#define SC_PATTERN 0xde\r
-#define LC_PATTERN 0xad\r
-\r
-/* Minimum alignment req */\r
-#define ARCH_ALIGN 4\r
-\r
-/* Small context (task swap==function call) */\r
-#define SAVE_NVGPR(_x,_y)\r
-#define RESTORE_NVGPR(_x,_y)\r
-\r
-/* Save volatile regs, NOT preserved by function calls */\r
-#define SAVE_VGPR(_x,_y)\r
-#define RESTORE_VGPR(_x,_y)\r
-\r
-/* Large context (interrupt) */\r
-#define SAVE_ALL_GPR(_x,_y)\r
-#define RESTORE_ALL_GPR(_x,_y)\r
-
+#define SC_PATTERN 0xde\r
+#define LC_PATTERN 0xad\r
+/*
// NVREGS: r4+r5+r6+r7+r8++r10+r11+lr = 9*4 = 36
#define NVGPR_SIZE 32
// VGPR: 9*4 = 36
#define VGPR_LR_OFF (C_SIZE+NVGPR_SIZE-4)
#define C_CONTEXT_OFF 4
#define C_SP_OFF 0
-#define C_LR_OFF 16 // TODO: value is from ppc
-\r
-#define SC_SIZE (NVGPR_SIZE+C_SIZE)
-\r
+*/
+
+/* Context layout, sizes in 16 bit words */
+// -- STACK TOP, CONTEXT START
+#define C_REG_CCR_OFF 0
+// -- CCR
+#define C_REG_D_OFF 1
+// -- D
+#define C_REG_X_OFF 2
+// -- X
+#define C_REG_Y_OFF 3
+// -- Y
+#define C_REG_TMP_OFF 4
+// -- _.tmp
+#define C_REG_XY_OFF 5
+// -- _.xy
+#define C_REG_Z_OFF 6
+// -- _.z
+#define C_REG_FRAME_OFF 7
+// -- _.frame
+#define C_RETURN_PPAGE_OFF 8
+// -- PPAGE
+#define C_RETURN_ADDR_OFF 9
+// -- ADDR
+#define SC_SIZE 10
+// -- CONTEXT END\r
\r
#endif /* CONTEXT_H_ */\r
#include "internal.h"
#include "irq.h"
-extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+extern void * Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+extern uint8 Irq_IsrTypeTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+
extern void _start (void);
+
void Irq_Init( void ) {
}
}
-
-static uint32_t NVIC_GetActiveVector( void) {
- return 0;
-}
-
-void *Irq_Entry( void *stack_p )
+void *Irq_Entry( uint8 irq_nr )
{
- return NULL;
+ if( Irq_GetIsrType(vector) == ISR_TYPE_1 ) {
+ // It's a function, just call it.
+ ((func_t)Irq_VectorTable[vector])();
+ return stack;
+ } else {
+ // It's a PCB
+ // Let the kernel handle the rest,
+ return Os_Isr(stack, (void *)Irq_VectorTable[vector]);
+ }
}
/**
* @param prio
*/
void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
+ Irq_VectorTable[vector] = (void *)entry;
+ Irq_SetIsrType(vector, ISR_TYPE_1);
}
pcb = os_find_task(tid);
Irq_VectorTable[vector] = (void *)pcb;
+ Irq_IsrTypeTable[vector] = PROC_ISR2;
}
}
+// ##################### INTERRUPT TRANSLATE TABLE #######################
+#define IRQ_MAP(x) irq_##x
+
const struct interrupt_vectors __attribute__((section(".vectors"))) vectors =
{
- pwm_shutdown_handler:
- bad_int,
- ptpif_handler:
- bad_int,
- can4_tx_handler:
- bad_int,
- can4_rx_handler:
- bad_int,
- can4_err_handler:
- bad_int,
- can4_wake_handler:
- bad_int,
- can3_tx_handler:
- bad_int,
- can3_rx_handler:
- bad_int,
- can3_err_handler:
- bad_int,
- can3_wake_handler:
- bad_int,
- can2_tx_handler:
- bad_int,
- can2_rx_handler:
- bad_int,
- can2_err_handler:
- bad_int,
- can2_wake_handler:
- bad_int,
- can1_tx_handler:
- bad_int,
- can1_rx_handler:
- bad_int,
- can1_err_handler:
- bad_int,
- can1_wake_handler:
- bad_int,
- can0_tx_handler:
- bad_int,
- can0_rx_handler:
- bad_int,
- can0_err_handler:
- bad_int,
- can0_wake_handler:
- bad_int,
- flash_handler:
- bad_int,
- eeprom_handler:
- bad_int,
- spi2_handler:
- bad_int,
- spi1_handler:
- bad_int,
- iic_handler:
- bad_int,
- bdlc_handler:
- bad_int,
- selfclk_mode_handler:
- bad_int,
- pll_lock_handler:
- bad_int,
- accb_overflow_handler:
- bad_int,
- mccnt_underflow_handler:
- bad_int,
- pthif_handler:
- bad_int,
- ptjif_handler:
- bad_int,
- atd1_handler:
- bad_int,
- atd0_handler:
- bad_int,
- sci1_handler:
- bad_int,
- sci0_handler:
- bad_int,
- spi0_handler:
- bad_int,
-
- // Timer and Accumulator
- acca_input_handler:
- bad_int,
- acca_overflow_handler:
- bad_int,
- timer_overflow_handler:
- bad_int,
-
- // InputCapture/OutputCompare Timers
- tc7_handler:
- bad_int,
- tc6_handler:
- bad_int,
- tc5_handler:
- bad_int,
- tc4_handler:
- bad_int,
- tc3_handler:
- bad_int,
- tc2_handler:
- bad_int,
- tc1_handler:
- bad_int,
- tc0_handler:
- bad_int,
-
- // External Interrupts
- rtii_handler:
- bad_int,
- irq_handler:
- bad_int,
- xirq_handler:
- bad_int,
-
- illegal_handler:
- bad_int,
- cop_fail_handler:
- bad_int,
- cop_clock_handler:
- bad_int,
-
- // Vectors in use
- swi_handler:
- bad_int,
-
- rtii_handler:
- bad_int,
- sci0_handler:
- bad_int,
- sci1_handler:
- bad_int,
+ pwm_shutdown_handler:
+ IRQ_MAP(IRQ_NR_PWM_SHUTDOWN),
+ ptpif_handler:
+ IRQ_MAP(IRQ_NR_PTPIF),
+ can4_tx_handler:
+ IRQ_MAP(IRQ_NR_CAN4_TX),
+ can4_rx_handler:
+ IRQ_MAP(IRQ_NR_CAN4_RX),
+ can4_err_handler:
+ IRQ_MAP(IRQ_NR_CAN4_ERR),
+ can4_wake_handler:
+ IRQ_MAP(IRQ_NR_CAN4_WAKE),
+ can3_tx_handler:
+ IRQ_MAP(IRQ_NR_CAN3_TX),
+ can3_rx_handler:
+ IRQ_MAP(IRQ_NR_CAN3_RX),
+ can3_err_handler:
+ IRQ_MAP(IRQ_NR_CAN3_ERR),
+ can3_wake_handler:
+ IRQ_MAP(IRQ_NR_CAN3_WAKE),
+ can2_tx_handler:
+ IRQ_MAP(IRQ_NR_CAN2_TX),
+ can2_rx_handler:
+ IRQ_MAP(IRQ_NR_CAN2_RX),
+ can2_err_handler:
+ IRQ_MAP(IRQ_NR_CAN2_ERR),
+ can2_wake_handler:
+ IRQ_MAP(IRQ_NR_CAN2_WAKE),
+ can1_tx_handler:
+ IRQ_MAP(IRQ_NR_CAN1_TX),
+ can1_rx_handler:
+ IRQ_MAP(IRQ_NR_CAN1_RX),
+ can1_err_handler:
+ IRQ_MAP(IRQ_NR_CAN1_ERR),
+ can1_wake_handler:
+ IRQ_MAP(IRQ_NR_CAN1_WAKE),
+ can0_tx_handler:
+ IRQ_MAP(IRQ_NR_CAN0_TX),
+ can0_rx_handler:
+ IRQ_MAP(IRQ_NR_CAN0_RX),
+ can0_err_handler:
+ IRQ_MAP(IRQ_NR_CAN0_ERR),
+ can0_wake_handler:
+ IRQ_MAP(IRQ_NR_CAN0_WAKE),
+ flash_handler:
+ IRQ_MAP(IRQ_NR_FLASH),
+ eeprom_handler:
+ IRQ_MAP(IRQ_NR_EEPROM),
+ spi2_handler:
+ IRQ_MAP(IRQ_NR_SPI2),
+ spi1_handler:
+ IRQ_MAP(IRQ_NR_SPI1),
+ iic_handler:
+ IRQ_MAP(IRQ_NR_IIC),
+ bdlc_handler:
+ IRQ_MAP(IRQ_NR_BDLC),
+ selfclk_mode_handler:
+ IRQ_MAP(IRQ_NR_SELFCLK_MODE),
+ pll_lock_handler:
+ IRQ_MAP(IRQ_NR_PLL_LOCK),
+ accb_overflow_handler:
+ IRQ_MAP(IRQ_NR_ACCB_OVERFLOW),
+ mccnt_underflow_handler:
+ IRQ_MAP(IRQ_NR_MCCNT_UNDERFLOW),
+ pthif_handler:
+ IRQ_MAP(IRQ_NR_PTHIF),
+ ptjif_handler:
+ IRQ_MAP(IRQ_NR_PTJIF),
+ atd1_handler:
+ IRQ_MAP(IRQ_NR_ATD1),
+ atd0_handler:
+ IRQ_MAP(IRQ_NR_ATD0),
+ sci1_handler:
+ IRQ_MAP(IRQ_NR_SCI1),
+ sci0_handler:
+ IRQ_MAP(IRQ_NR_SCI0),
+ spi0_handler:
+ IRQ_MAP(IRQ_NR_SPI0),
+
+ // Timer and Accumulator
+ acca_input_handler:
+ IRQ_MAP(IRQ_NR_ACCA_INPUT),
+ acca_overflow_handler:
+ IRQ_MAP(IRQ_NR_ACCA_OVERFLOW),
+ timer_overflow_handler:
+ IRQ_MAP(IRQ_NR_TIMER_OVERFLOW),
+
+ // InputCapture/OutputCompare Timers
+ tc7_handler:
+ IRQ_MAP(IRQ_NR_TC7),
+ tc6_handler:
+ IRQ_MAP(IRQ_NR_TC6),
+ tc5_handler:
+ IRQ_MAP(IRQ_NR_TC5),
+ tc4_handler:
+ IRQ_MAP(IRQ_NR_TC4),
+ tc3_handler:
+ IRQ_MAP(IRQ_NR_TC3),
+ tc2_handler:
+ IRQ_MAP(IRQ_NR_TC2),
+ tc1_handler:
+ IRQ_MAP(IRQ_NR_TC1),
+ tc0_handler:
+ IRQ_MAP(IRQ_NR_TC0),
+
+ // External Interrupts
+ rtii_handler:
+ IRQ_MAP(IRQ_NR_RTII),
+ irq_handler:
+ IRQ_MAP(IRQ_NR_IRQ),
+ xirq_handler:
+ IRQ_MAP(IRQ_NR_XIRQ),
+
+ // Vectors in use
+ swi_handler:
+ IRQ_MAP(IRQ_NR_SWI),
+
+ illegal_handler:
+ IRQ_MAP(IRQ_NR_ILLEGAL),
+ cop_fail_handler:
+ IRQ_MAP(IRQ_NR_COP_FAIL),
+ cop_clock_handler:
+ IRQ_MAP(IRQ_NR_COP_CLOCK),
reset_handler:
_start,
#ifndef IRQ_H
#define IRQ_H
+#include "irq_defines.h"
typedef enum
{
- RESET,
- CLOCK_MONITOR_FAIL_RESET,
- /* TODO: */
+ IRQ_TYPE_RES0,
+ IRQ_TYPE_RES1,
+ IRQ_TYPE_RES2,
+ IRQ_TYPE_RES3,
+ IRQ_TYPE_RES4,
+ IRQ_TYPE_RES5,
+ IRQ_TYPE_PWM_SHUTDOWN,
+ IRQ_TYPE_PTPIF,
+
+ /* CAN */
+ IRQ_TYPE_CAN4_TX,
+ IRQ_TYPE_CAN4_RX,
+ IRQ_TYPE_CAN4_ERR,
+ IRQ_TYPE_CAN4_WAKE,
+ IRQ_TYPE_CAN3_TX,
+ IRQ_TYPE_CAN3_RX,
+ IRQ_TYPE_CAN3_ERR,
+ IRQ_TYPE_CAN3_WAKE,
+ IRQ_TYPE_CAN2_TX,
+ IRQ_TYPE_CAN2_RX,
+ IRQ_TYPE_CAN2_ERR,
+ IRQ_TYPE_CAN2_WAKE,
+ IRQ_TYPE_CAN1_TX,
+ IRQ_TYPE_CAN1_RX,
+ IRQ_TYPE_CAN1_ERR,
+ IRQ_TYPE_CAN1_WAKE,
+ IRQ_TYPE_CAN0_TX,
+ IRQ_TYPE_CAN0_RX,
+ IRQ_TYPE_CAN0_ERR,
+ IRQ_TYPE_CAN0_WAKE,
+
+ IRQ_TYPE_FLASH,
+ IRQ_TYPE_EEPROM,
+ IRQ_TYPE_SPI2,
+ IRQ_TYPE_SPI1,
+ IRQ_TYPE_IIC,
+ IRQ_TYPE_BDLC,
+ IRQ_TYPE_SELFCLK_MODE,
+ IRQ_TYPE_PLL_LOCK,
+ IRQ_TYPE_ACCB_OVERFLOW,
+ IRQ_TYPE_MCCNT_UNDERFLOW,
+ IRQ_TYPE_PTHIF,
+ IRQ_TYPE_PTJIF,
+ IRQ_TYPE_ATD1,
+ IRQ_TYPE_ATD0,
+ IRQ_TYPE_SCI1,
+ IRQ_TYPE_SCI0,
+ IRQ_TYPE_SPI0,
+
+ /* TIMER AND ACCUMULATOR */
+ IRQ_TYPE_ACCA_INPUT,
+ IRQ_TYPE_ACCA_OVERFLOW,
+ IRQ_TYPE_TIMER_OVERFLOW,
+
+ /* INPUTCAPTURE/OUTPUTCOMPARE TIMERS */
+ IRQ_TYPE_TC7,
+ IRQ_TYPE_TC6,
+ IRQ_TYPE_TC5,
+ IRQ_TYPE_TC4,
+ IRQ_TYPE_TC3,
+ IRQ_TYPE_TC2,
+ IRQ_TYPE_TC1,
+ IRQ_TYPE_TC0,
+
+ /* EXTERNAL INTERRUPTS */
+ IRQ_TYPE_RTII,
+ IRQ_TYPE_IRQ,
+ IRQ_TYPE_XIRQ,
+
+ /* SOFTWARE INTERRUPT */
+ IRQ_TYPE_SWI,
+
+ /* ILLEGAL INSTRUCTION RESET */
+ IRQ_TYPE_ILLEGAL,
+
+ /* COP TIMEOUT RESET */
+ IRQ_TYPE_COP_FAIL,
+
+ /* CLOCK MONITOR FAIL RESET */
+ IRQ_TYPE_COP_CLOCK,
+
+ /* START OR RESET VECTOR */
+ IRQ_TYPE_RESET,
NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS,
}IrqType;
bank15 (rx) : ORIGIN = 0x10c000, LENGTH = 16k-0x100\r
\r
/* Flash memory banks LMA:s */\r
+ /* iSystem winIDEA */\r
+ bank8_lma (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+ bank9_lma (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+ bank10_lma (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+ bank11_lma (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+ bank12_lma (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+ bank13_lma (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+\r
+ bank14_lma (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+ bank15_lma (rx) : ORIGIN = 0x10c000, LENGTH = 16k-0x100\r
+ vectors_lma (rx) : ORIGIN = 0x10ff80, LENGTH = 0x80\r
+ \r
+ /* Freescale Codewarrior Hiwave (s19, TBDML)\r
bank8_lma (rx) : ORIGIN = 0x388000, LENGTH = 16k\r
bank9_lma (rx) : ORIGIN = 0x398000, LENGTH = 16k\r
bank10_lma (rx) : ORIGIN = 0x3a8000, LENGTH = 16k\r
bank14_lma (rx) : ORIGIN = 0x3e8000, LENGTH = 16k\r
bank15_lma (rx) : ORIGIN = 0x3f8000, LENGTH = 16k-0x100\r
vectors_lma (rx) : ORIGIN = 0x3fff80, LENGTH = 0x80\r
+ */\r
}\r
\r
/* Setup the stack on the top of the data memory bank. */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+#ifndef ASM_HC1X_H_\r
+#define ASM_HC1X_H_\r
+\r
+\r
+/*
+ * Function argument macros
+ */
+
+#define ARG_1_STACK_OFFS 3
+#define ARG_2_STACK_OFFS 5
+
+// Arg 0 is already in D
+#define GET_ARG_0_TO_D
+
+// Arg 0 (D) -> X
+#define GET_ARG_0_TO_X \
+ tfr d,x;
+
+// Arg 0 (D) -> Y
+#define GET_ARG_0_TO_Y \
+ tfr d,y;
+
+// Arg 1 (from stack) -> reg
+#define GET_ARG_1_TO(reg) \
+ ld##reg ARG_1_STACK_OFFS,sp;
+
+// Arg 2 (from stack) -> reg
+#define GET_ARG_2(reg) \
+ ld##reg ARG_2_STACK_OFFS,x;
+
+// Macro used to create the IRQ mapping table
+#define DECLARE_IRQ_MAP(x) \
+irq_##x: \
+ movb ##x, CSize;SP \
+ bra Irq_PreEntry \\r
+\r
+#endif /*ASM_HC1X_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef IRQ_DEFINES_H_\r
+#define IRQ_DEFINES_H_\r
+\r
+#define IRQ_NR_RES0 0\r
+#define IRQ_NR_RES1 1\r
+#define IRQ_NR_RES2 2\r
+#define IRQ_NR_RES3 3\r
+#define IRQ_NR_RES4 4\r
+#define IRQ_NR_RES5 5\r
+#define IRQ_NR_PWM_SHUTDOWN 6\r
+#define IRQ_NR_PTPIF 7\r
+#define IRQ_NR_CAN4_TX 8\r
+#define IRQ_NR_CAN4_RX 9\r
+#define IRQ_NR_CAN4_ERR 10\r
+#define IRQ_NR_CAN4_WAKE 11\r
+#define IRQ_NR_CAN3_TX 12\r
+#define IRQ_NR_CAN3_RX 13\r
+#define IRQ_NR_CAN3_ERR 14\r
+#define IRQ_NR_CAN3_WAKE 15\r
+#define IRQ_NR_CAN2_TX 16\r
+#define IRQ_NR_CAN2_RX 17\r
+#define IRQ_NR_CAN2_ERR 18\r
+#define IRQ_NR_CAN2_WAKE 19\r
+#define IRQ_NR_CAN1_TX 20\r
+#define IRQ_NR_CAN1_RX 21\r
+#define IRQ_NR_CAN1_ERR 22\r
+#define IRQ_NR_CAN1_WAKE 23\r
+#define IRQ_NR_CAN0_TX 24\r
+#define IRQ_NR_CAN0_RX 25\r
+#define IRQ_NR_CAN0_ERR 26\r
+#define IRQ_NR_CAN0_WAKE 27\r
+#define IRQ_NR_FLASH 28\r
+#define IRQ_NR_EEPROM 29\r
+#define IRQ_NR_SPI2 30\r
+#define IRQ_NR_SPI1 31\r
+#define IRQ_NR_IIC 32\r
+#define IRQ_NR_BDLC 33\r
+#define IRQ_NR_SELFCLK34_MODE\r
+#define IRQ_NR_PLL_LOCK 35\r
+#define IRQ_NR_ACCB_OVERFLOW 36\r
+#define IRQ_NR_MCCNT_UNDERFLOW 37\r
+#define IRQ_NR_PTHIF 38\r
+#define IRQ_NR_PTJIF 39\r
+#define IRQ_NR_ATD1 40\r
+#define IRQ_NR_ATD0 41\r
+#define IRQ_NR_SCI1 42\r
+#define IRQ_NR_SCI0 43\r
+#define IRQ_NR_SPI0 44\r
+#define IRQ_NR_ACCA_INPUT 45\r
+#define IRQ_NR_ACCA_OVERFLOW 46\r
+#define IRQ_NR_TIMER_OVERFLOW 47\r
+#define IRQ_NR_TC7 48\r
+#define IRQ_NR_TC6 49\r
+#define IRQ_NR_TC5 50\r
+#define IRQ_NR_TC4 51\r
+#define IRQ_NR_TC3 52\r
+#define IRQ_NR_TC2 53\r
+#define IRQ_NR_TC1 54\r
+#define IRQ_NR_TC0 55\r
+#define IRQ_NR_RTII 56\r
+#define IRQ_NR_IRQ 57\r
+#define IRQ_NR_XIRQ 58\r
+#define IRQ_NR_SWI 59\r
+#define IRQ_NR_ILLEGAL 60\r
+#define IRQ_NR_COP_FAIL 61\r
+#define IRQ_NR_COP_CLOCK 62\r
+#define IRQ_NR_RESET 63\r
+\r
+#endif\r
projects / arc.git / commitdiff