-/* -------------------------------- Arctic Core ------------------------------
- * Arctic Core - the open source AUTOSAR platform http://arccore.com
- *
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
- *
- * This source code is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- * -------------------------------- Arctic Core ------------------------------*/
-
-
-
-
-
-
-
-
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
#include "Std_Types.h"\r
#include "Gpt.h"\r
#include "Cpu.h"\r
#include <assert.h>\r
#include <string.h>\r
-#include "mpc55xx.h"\r
+#include "regs.h"\r
#include "Mcu.h"\r
#include "Trace.h"\r
#include "Det.h"\r
+#include "irq_types.h"\r
+#include "Os.h"\r
+#include "arc.h"\r
+\r
+#define FIRST_OC_REG 0x50\r
\r
// Implementation specific\r
\r
Gpt_StateType state;\r
} Gpt_UnitType;\r
\r
+\r
+// Holds the enable/disable status of notifications.\r
+uint8 GptNotificationStatuses[8] = {\r
+ STD_ON,\r
+ STD_ON,\r
+ STD_ON,\r
+ STD_ON,\r
+ STD_ON,\r
+ STD_ON,\r
+ STD_ON,\r
+ STD_ON\r
+};\r
+\r
+uint16 GptPeriods[GPT_CHANNEL_CNT];\r
+\r
+#if (GPT_TIME_ELAPSED_API == STD_ON)\r
+uint16 GptPrevOc[GPT_CHANNEL_CNT];\r
+#endif\r
+\r
+\r
Gpt_UnitType Gpt_Unit[GPT_CHANNEL_CNT];\r
\r
// Global config\r
*\r
* @param channel - Channel that the raised the interrupt\r
*/\r
-\r
static void Gpt_IsrCh(Gpt_ChannelType channel)\r
{\r
const Gpt_ConfigType *config;\r
if (config->GptChannelMode == GPT_MODE_ONESHOT)\r
{\r
// Disable the channel\r
- PIT.EN.R &= ~(1<<channel);\r
-\r
+ Gpt_StopTimer(channel);\r
Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
- }\r
- config->GptNotification();\r
\r
- // Clear interrupt\r
- PIT.FLG.R = (1<<channel); // Added by Mattias 2009-01\r
+ } else {\r
+ // Start the next period.\r
+ uint16 curr_oc = PORTIO_16((FIRST_OC_REG + (2 * channel)));\r
+ PORTIO_16((FIRST_OC_REG + (2*channel))) = curr_oc + GptPeriods[channel];\r
+\r
+ #if (GPT_TIME_ELAPSED_API == STD_ON)\r
+ GptPrevOc[channel] = curr_oc;\r
+ #endif\r
+ }\r
+ if (GptNotificationStatuses[channel] == STD_ON) {\r
+ config->GptNotification();\r
+ }\r
}\r
\r
//-------------------------------------------------------------------\r
// Macro that counts leading zeroes.\r
#define CNTLZW_INV(x) (31-cntlzw(x))\r
\r
+\r
/**\r
* ISR that handles all interrupts to the PIT channels\r
* ( NOT the decrementer )\r
*/\r
+#define DECLARE_GPT_ISR_PROTOTYPE(x) \\r
+void Gpt_Isr_##x (void) { \\r
+ Gpt_IsrCh(x); \\r
+}\r
\r
-static void Gpt_Isr(void)\r
-{\r
- uint32 flgMask= PIT.FLG.R;\r
- uint8 chNr = 0;\r
+#define GPT_IRQ_TYPE(x) IRQ_TYPE_TC(x)\r
+\r
+DECLARE_GPT_ISR_PROTOTYPE(0)\r
+DECLARE_GPT_ISR_PROTOTYPE(1)\r
+DECLARE_GPT_ISR_PROTOTYPE(2)\r
+DECLARE_GPT_ISR_PROTOTYPE(3)\r
+DECLARE_GPT_ISR_PROTOTYPE(4)\r
+DECLARE_GPT_ISR_PROTOTYPE(5)\r
+DECLARE_GPT_ISR_PROTOTYPE(6)\r
+DECLARE_GPT_ISR_PROTOTYPE(7)\r
\r
- // Loop over all interrupts\r
- for (; flgMask; flgMask&=~(1<<chNr))\r
- {\r
- // Find first channel that is requesting service.\r
- chNr = CNTLZW_INV(flgMask);\r
- Gpt_IsrCh(chNr);\r
- // Clear interrupt\r
- PIT.FLG.R = (1<<chNr);\r
- }\r
-}\r
\r
//-------------------------------------------------------------------\r
\r
uint32_t i=0;\r
const Gpt_ConfigType *cfg;\r
VALIDATE( (Gpt_Global.initRun == STD_OFF), GPT_INIT_SERVICE_ID, GPT_E_ALREADY_INITIALIZED );\r
-#if defined(GPT_VARIANT_PB)\r
VALIDATE( (config != NULL ), GPT_INIT_SERVICE_ID, GPT_E_PARAM_CONFIG );\r
-#elif defined(GPT_VARIANT_PC)\r
- // We don't support GPT_VARIANT_PC\r
- assert(0);\r
-#endif\r
+\r
Gpt_ChannelType ch;\r
\r
for (i=0; i<GPT_CHANNEL_CNT; i++)\r
Gpt_Global.channelMap[cfg->GptChannelId] = i;\r
Gpt_Global.configured |= (1<<ch);\r
\r
- if (ch <= GPT_CHANNEL_PIT_8)\r
+ if (ch <= GPT_CHANNEL_7)\r
{\r
if (cfg->GptNotification != NULL)\r
{\r
- Irq_InstallVector(Gpt_Isr, PIT_PITFLG_RTIF + ch, 1, CPU_Z1);\r
+ TaskType tid;\r
+ switch (ch) {\r
+ case 0:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_0, 1, "Gpt_Isr_0");\r
+ break;\r
+ case 1:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_1, 1, "Gpt_Isr_1");\r
+ break;\r
+ case 2:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_2, 1, "Gpt_Isr_2");\r
+ break;\r
+ case 3:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_3, 1, "Gpt_Isr_3");\r
+ break;\r
+ case 4:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_4, 1, "Gpt_Isr_4");\r
+ break;\r
+ case 5:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_5, 1, "Gpt_Isr_5");\r
+ break;\r
+ case 6:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_6, 1, "Gpt_Isr_6");\r
+ break;\r
+ case 7:\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_7, 1, "Gpt_Isr_7");\r
+ break;\r
+ }\r
+\r
+ Irq_AttachIsr2(tid, NULL, (IRQ_NR_TC0 - ch));\r
}\r
}\r
-#if defined(USE_KERNEL)\r
- // Don't install if we use kernel.. it handles that.\r
-#else\r
- else if (ch == GPT_CHANNEL_DEC)\r
- {\r
- // Decrementer event is default an exception. Use software interrupt 7 as wrapper.\r
- Irq_InstallVector(config[i].GptNotification, INTC_SSCIR0_CLR7, 1, CPU_Z1);\r
- }\r
-#endif\r
\r
cfg++;\r
i++;\r
Gpt_Global.config = config;\r
\r
Gpt_Global.initRun = STD_ON;\r
- PIT.CTRL.B.MDIS = 0;\r
+\r
+ TSCR1 |= TEN; // Turn timer on.\r
}\r
\r
//-------------------------------------------------------------------\r
}\r
Gpt_Global.initRun = STD_OFF;\r
Gpt_Global.configured = 0;\r
+ TSCR1 &= ~TEN; // Turn timer off.\r
//_config.config = NULL;\r
}\r
#endif\r
\r
confCh = Gpt_Global.channelMap[channel];\r
\r
- if (channel <= GPT_CHANNEL_PIT_8)\r
- {\r
- uint32 *tlval = (uint32 *)&PIT.TLVAL0;\r
- uint32 *tval = (uint32 *)&PIT.TVAL0;\r
+ if (channel <= GPT_CHANNEL_7) {\r
\r
- tlval[channel] = period_ticks;\r
- tval[channel] = period_ticks;\r
\r
- // always select interrupt\r
- if (channel != GPT_CHANNEL_RTI)\r
- {\r
- PIT.INTSEL.R |= ( 1 << channel );\r
- }\r
\r
- // Make sure that no interrupt is pending.\r
- PIT.FLG.R = ( 1 << channel );\r
+ // Setup channel for output compare (OC).\r
+ TIOS |= (1 << channel);\r
\r
- // Enable timer\r
- PIT.EN.R |= ( 1 << channel );\r
- }\r
- else if (channel == GPT_CHANNEL_DEC)\r
- {\r
- // Enable the TB\r
- tmp = get_spr(SPR_HID0);\r
- tmp |= HID0_TBEN;\r
- set_spr(SPR_HID0,tmp);\r
+ // Enable interrupt for timer\r
+ TIE |= (1 << channel);\r
\r
- /* Initialize the Decrementer */\r
- set_spr(SPR_DEC, period_ticks);\r
- set_spr(SPR_DECAR, period_ticks);\r
+ // Set OC value.\r
+ uint16 curr_cnt = TCNT;\r
+ PORTIO_16((FIRST_OC_REG + (2*channel))) = curr_cnt + period_ticks;\r
\r
- if( Gpt_Global.config[confCh].GptChannelMode == GPT_MODE_CONTINUOUS )\r
- {\r
- /* Set autoreload */\r
- tmp = get_spr(SPR_TCR);\r
- tmp |= TCR_ARE;\r
- set_spr(SPR_TCR,tmp);\r
- }\r
+ #if (GPT_TIME_ELAPSED_API == STD_ON)\r
+ GptPrevOc[channel] = curr_cnt;\r
+ #endif\r
}\r
\r
+ #if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
if( Gpt_Global.config[confCh].GptNotification != NULL )\r
{\r
// GPT275\r
Gpt_EnableNotification(channel);\r
}\r
+ #endif\r
\r
+ GptPeriods[channel] = period_ticks;\r
Gpt_Unit[channel].state = GPT_STATE_STARTED;\r
}\r
\r
VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STOPTIMER_SERVICE_ID, GPT_E_UNINIT );\r
VALIDATE( VALID_CHANNEL(channel), GPT_STOPTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
\r
- if (channel <= GPT_CHANNEL_PIT_8)\r
- {\r
- // Disable timer\r
- PIT.EN.R &= ~( 1 << channel );\r
- }\r
- else if (channel == GPT_CHANNEL_DEC)\r
+ if (channel <= GPT_CHANNEL_7)\r
{\r
- uint32 tb;\r
- tb = get_spr(SPR_HID0);\r
- tb &= ~HID0_TBEN;\r
- set_spr(SPR_HID0,tb);\r
+ TIE &= ~(1 << channel);\r
}\r
\r
+#if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
Gpt_DisableNotification(channel);\r
+#endif\r
+\r
Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
}\r
\r
-#if ( GPT_TIME_REMAINING_API == STD_ON )\r
\r
+#if ( GPT_TIME_REMAINING_API == STD_ON )\r
Gpt_ValueType Gpt_GetTimeRemaining(Gpt_ChannelType channel)\r
{\r
VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_UNINIT, 0 );\r
VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
Gpt_ValueType remaining;\r
\r
- if (channel <= GPT_CHANNEL_PIT_8)\r
+ if (channel <= GPT_CHANNEL_7)\r
{\r
- uint32 *tval = (uint32 *)&PIT.TVAL0;\r
- // Time remaining is the time until it hits 0, so just return the current timer value\r
- remaining = tval[channel];\r
- }\r
- else if (channel == GPT_CHANNEL_DEC)\r
- {\r
- remaining = get_spr(SPR_DEC);\r
+ uint16 now = TCNT;\r
+ uint16 next = PORTIO_16((FIRST_OC_REG + (2*channel)));\r
+ if (next > now) {\r
+ remaining = next - now;\r
+\r
+ } else {\r
+ remaining = next + (0xFF - now) ;\r
+ }\r
}\r
\r
-return remaining;\r
+ return remaining;\r
}\r
#endif\r
\r
#if ( GPT_TIME_ELAPSED_API == STD_ON )\r
Gpt_ValueType Gpt_GetTimeElapsed(Gpt_ChannelType channel)\r
{\r
- Gpt_ValueType timer;\r
+ Gpt_ValueType elapsed;\r
\r
VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_UNINIT ,0 );\r
VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
\r
- // NOTE!\r
- // These little creatures count down\r
+ if (channel <= GPT_CHANNEL_7) {\r
+ uint16 now = TCNT;\r
+ if (now > GptPrevOc[channel]) {\r
+ elapsed = now - GptPrevOc[channel];\r
\r
- if (channel <= GPT_CHANNEL_PIT_8)\r
- {\r
- uint32 *tval = (uint32 *)&PIT.TVAL0;\r
- uint32 *tlval = (uint32 *)&PIT.TLVAL0;\r
- timer = tlval[channel] - tval[channel];\r
- }\r
- else if (channel == GPT_CHANNEL_DEC)\r
- {\r
- timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
+ } else {\r
+ elapsed = (0xFF - GptPrevOc[channel]) + now;\r
+ }\r
}\r
\r
- return (timer);\r
+ return (elapsed);\r
}\r
#endif\r
\r
VALIDATE( (Gpt_Global.initRun == STD_ON), 0x7, GPT_E_UNINIT );\r
VALIDATE( VALID_CHANNEL(channel),0x7, GPT_E_PARAM_CHANNEL );\r
\r
- if (channel <= GPT_CHANNEL_PIT_8)\r
- {\r
- // enable interrupts\r
- PIT.INTEN.R |= ( 1 << channel );\r
- }\r
- else if (channel == GPT_CHANNEL_DEC)\r
+ if (channel <= GPT_CHANNEL_7)\r
{\r
- uint32 tmp;\r
- tmp = get_spr(SPR_TCR);\r
- tmp |= TCR_DIE;\r
- set_spr(SPR_TCR, tmp );\r
+ GptNotificationStatuses[channel] = STD_ON;\r
}\r
}\r
\r
void Gpt_DisableNotification(Gpt_ChannelType channel)\r
{\r
-\r
VALIDATE( (Gpt_Global.initRun == STD_ON), 0x8, GPT_E_UNINIT );\r
VALIDATE( VALID_CHANNEL(channel),0x8, GPT_E_PARAM_CHANNEL );\r
\r
- if (channel <= GPT_CHANNEL_PIT_8)\r
+ if (channel <= GPT_CHANNEL_7)\r
{\r
- PIT.INTEN.R &= ~( 1 << channel );\r
+ GptNotificationStatuses[channel] = STD_OFF;\r
}\r
- else if (channel == GPT_CHANNEL_DEC)\r
- {\r
- uint32 tmp;\r
- tmp = get_spr(SPR_TCR);\r
- tmp &= ~TCR_DIE;\r
- set_spr(SPR_TCR, tmp );\r
- }\r
-\r
- return;\r
}\r
-\r
#endif\r
\r
#if ( GPT_WAKEUP_FUNCTIONALITY_API == STD_ON )\r
\r
if (mode == GPT_MODE_NORMAL)\r
{\r
- PIT.CTRL.B.MDIS = 0;\r
- // Do NOT restart channels\r
+\r
}\r
else if (mode == GPT_MODE_SLEEP)\r
{\r
\r
- PIT.CTRL.B.MDIS = 1;\r
- // Disable all but RTI\r
- for (i= 0; i <= GPT_CHANNEL_PIT_8; i++)\r
- {\r
- Gpt_StopTimer(i);\r
- }\r
}\r
}\r
\r
{\r
VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
VALIDATE( VALID_CHANNEL(channel), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
- // Only RTI have system wakeup\r
- if (channel == GPT_CHANNEL_RTI)\r
- {\r
- Gpt_Global.wakeupEnabled = STD_OFF;\r
- }\r
- else\r
- {\r
- // TODO:\r
- //assert(0);\r
- }\r
+\r
+\r
}\r
\r
void Gpt_EnableWakeup(Gpt_ChannelType channel)\r
{\r
VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
VALIDATE( VALID_CHANNEL(channel),GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
- if (channel == GPT_CHANNEL_RTI)\r
- {\r
- Gpt_Global.wakeupEnabled = STD_ON;\r
- }\r
- else\r
- {\r
- // TODO:\r
- //assert(0);\r
- }\r
+\r
}\r
\r
void Gpt_Cbk_CheckWakeup(EcuM_WakeupSourceType wakeupSource)\r
}\r
\r
unsigned int Os_ArchGetScSize( void ) {\r
- return SC_SIZE;\r
+ return CONTEXT_SIZE_W;\r
}\r
\r
\r
*/\r
\r
void OsArch_SetTaskEntry(OsPcbType *pcbPtr ) {\r
- uint16_t *context = (uint16_t *)pcbPtr->stack.curr;\r
-\r
-// context[C_CONTEXT_OFF/4] = SC_PATTERN;\r
+ uint16_t *context_words = (uint16_t *)pcbPtr->stack.curr;\r
+ uint8_t *context_bytes = (uint8_t *)pcbPtr->stack.curr;\r
\r
/* Set Return to start function */\r
+\r
+ context_bytes[8] = OS_KERNEL_CODE_PPAGE;\r
+\r
if( pcbPtr->proc_type == PROC_EXTENDED ) {\r
- context[C_RETURN_PPAGE_OFF] = OS_KERNEL_CODE_PPAGE;\r
- context[C_RETURN_ADDR_OFF] = (uint16_t)Os_TaskStartExtended;\r
+ context_words[8] = (uint16_t)Os_TaskStartExtended;\r
} else if( pcbPtr->proc_type == PROC_BASIC ) {\r
- context[C_RETURN_PPAGE_OFF] = OS_KERNEL_CODE_PPAGE;\r
- context[C_RETURN_ADDR_OFF] = (uint16_t)Os_TaskStartBasic;\r
+ context_words[8] = (uint16_t)Os_TaskStartBasic;\r
}\r
}\r
\r
\r
\r
#define _ASSEMBLER_\r
+\r
+#define PPAGE 0x30 /* bank nr. reg */\r
+#define MCFLG 0x67 /* modulus counter flag reg */\r
+\r
#include "kernel_offset.h"\r
+#include "asm_hc1x.h"\r
+#include "context.sx"\r
+#include "context.h"\r
#include "irq_defines.h"\r
-#include "arch_irq.sx"\r
-//#include "arch_offset.h"\r
-//#include "stack.h"\r
\r
.extern os_sys\r
\r
+.macro DECLARE_IRQ_MAP_GLOBAL name\r
+.global irq_\name\r
+.endm\r
+\r
+//Macro used to create the IRQ mapping table\r
+.macro DECLARE_IRQ_MAP name nr\r
+irq_\name:\r
+ movb #\nr, -10, sp // save irq nr. above context space\r
+ bra Irq_PreEntry\r
+.endm\r
+\r
+\r
+DECLARE_IRQ_MAP_GLOBAL res0\r
+DECLARE_IRQ_MAP_GLOBAL res1\r
+DECLARE_IRQ_MAP_GLOBAL res2\r
+DECLARE_IRQ_MAP_GLOBAL res3\r
+DECLARE_IRQ_MAP_GLOBAL res4\r
+DECLARE_IRQ_MAP_GLOBAL res5\r
+DECLARE_IRQ_MAP_GLOBAL pwm_shutdown\r
+DECLARE_IRQ_MAP_GLOBAL ptpif\r
+DECLARE_IRQ_MAP_GLOBAL can4_tx\r
+DECLARE_IRQ_MAP_GLOBAL can4_rx\r
+DECLARE_IRQ_MAP_GLOBAL can4_err\r
+DECLARE_IRQ_MAP_GLOBAL can4_wake\r
+DECLARE_IRQ_MAP_GLOBAL can3_tx\r
+DECLARE_IRQ_MAP_GLOBAL can3_rx\r
+DECLARE_IRQ_MAP_GLOBAL can3_err\r
+DECLARE_IRQ_MAP_GLOBAL can3_wake\r
+DECLARE_IRQ_MAP_GLOBAL can2_tx\r
+DECLARE_IRQ_MAP_GLOBAL can2_rx\r
+DECLARE_IRQ_MAP_GLOBAL can2_err\r
+DECLARE_IRQ_MAP_GLOBAL can2_wake\r
+DECLARE_IRQ_MAP_GLOBAL can1_tx\r
+DECLARE_IRQ_MAP_GLOBAL can1_rx\r
+DECLARE_IRQ_MAP_GLOBAL can1_err\r
+DECLARE_IRQ_MAP_GLOBAL can1_wake\r
+DECLARE_IRQ_MAP_GLOBAL can0_tx\r
+DECLARE_IRQ_MAP_GLOBAL can0_rx\r
+DECLARE_IRQ_MAP_GLOBAL can0_err\r
+DECLARE_IRQ_MAP_GLOBAL can0_wake\r
+DECLARE_IRQ_MAP_GLOBAL flash\r
+DECLARE_IRQ_MAP_GLOBAL eeprom\r
+DECLARE_IRQ_MAP_GLOBAL spi2\r
+DECLARE_IRQ_MAP_GLOBAL spi1\r
+DECLARE_IRQ_MAP_GLOBAL iic\r
+DECLARE_IRQ_MAP_GLOBAL bdlc\r
+DECLARE_IRQ_MAP_GLOBAL selfclk_mode\r
+DECLARE_IRQ_MAP_GLOBAL pll_lock\r
+DECLARE_IRQ_MAP_GLOBAL accb_overflow\r
+DECLARE_IRQ_MAP_GLOBAL mccnt_underflow\r
+DECLARE_IRQ_MAP_GLOBAL pthif\r
+DECLARE_IRQ_MAP_GLOBAL ptjif\r
+DECLARE_IRQ_MAP_GLOBAL atd1\r
+DECLARE_IRQ_MAP_GLOBAL atd0\r
+DECLARE_IRQ_MAP_GLOBAL sci1\r
+DECLARE_IRQ_MAP_GLOBAL sci0\r
+DECLARE_IRQ_MAP_GLOBAL spi0\r
+DECLARE_IRQ_MAP_GLOBAL acca_input\r
+DECLARE_IRQ_MAP_GLOBAL acca_overflow\r
+DECLARE_IRQ_MAP_GLOBAL timer_overflow\r
+DECLARE_IRQ_MAP_GLOBAL tc7\r
+DECLARE_IRQ_MAP_GLOBAL tc6\r
+DECLARE_IRQ_MAP_GLOBAL tc5\r
+DECLARE_IRQ_MAP_GLOBAL tc4\r
+DECLARE_IRQ_MAP_GLOBAL tc3\r
+DECLARE_IRQ_MAP_GLOBAL tc2\r
+DECLARE_IRQ_MAP_GLOBAL tc1\r
+DECLARE_IRQ_MAP_GLOBAL tc0\r
+DECLARE_IRQ_MAP_GLOBAL rtii\r
+DECLARE_IRQ_MAP_GLOBAL irq\r
+DECLARE_IRQ_MAP_GLOBAL xirq\r
+DECLARE_IRQ_MAP_GLOBAL swi\r
+DECLARE_IRQ_MAP_GLOBAL illegal\r
+DECLARE_IRQ_MAP_GLOBAL cop_fail\r
+DECLARE_IRQ_MAP_GLOBAL cop_clock\r
+\r
.section .text\r
\r
+Irq_PreEntry:\r
+ SAVE_CONTEXT_FROM_INTERRUPT\r
+ ldaa #0 // load irq nr. as arg 0..\r
+ ldab -1,sp // ..from above context space\r
+ sts 2,-sp // put SP as arg 1\r
+ call Irq_Entry //\r
+ tfr d,sp // load stack_p returned from Irq_Entry\r
+ RESTORE_CONTEXT_FOR_INTERRUPT\r
+ rti\r
+ \r
+\r
+DECLARE_IRQ_MAP res0, IRQ_NR_RES0\r
+DECLARE_IRQ_MAP res1, IRQ_NR_RES1\r
+DECLARE_IRQ_MAP res2, IRQ_NR_RES2\r
+DECLARE_IRQ_MAP res3, IRQ_NR_RES3\r
+DECLARE_IRQ_MAP res4, IRQ_NR_RES4\r
+DECLARE_IRQ_MAP res5, IRQ_NR_RES5\r
+DECLARE_IRQ_MAP pwm_shutdown, IRQ_NR_PWM_SHUTDOWN\r
+DECLARE_IRQ_MAP ptpif, IRQ_NR_PTPIF\r
+DECLARE_IRQ_MAP can4_tx, IRQ_NR_CAN4_TX\r
+DECLARE_IRQ_MAP can4_rx, IRQ_NR_CAN4_RX\r
+DECLARE_IRQ_MAP can4_err, IRQ_NR_CAN4_ERR\r
+DECLARE_IRQ_MAP can4_wake, IRQ_NR_CAN4_WAKE\r
+DECLARE_IRQ_MAP can3_tx, IRQ_NR_CAN3_TX\r
+DECLARE_IRQ_MAP can3_rx, IRQ_NR_CAN3_RX\r
+DECLARE_IRQ_MAP can3_err, IRQ_NR_CAN3_ERR\r
+DECLARE_IRQ_MAP can3_wake, IRQ_NR_CAN3_WAKE\r
+DECLARE_IRQ_MAP can2_tx, IRQ_NR_CAN2_TX\r
+DECLARE_IRQ_MAP can2_rx, IRQ_NR_CAN2_RX\r
+DECLARE_IRQ_MAP can2_err, IRQ_NR_CAN2_ERR\r
+DECLARE_IRQ_MAP can2_wake, IRQ_NR_CAN2_WAKE\r
+DECLARE_IRQ_MAP can1_tx, IRQ_NR_CAN1_TX\r
+DECLARE_IRQ_MAP can1_rx, IRQ_NR_CAN1_RX\r
+DECLARE_IRQ_MAP can1_err, IRQ_NR_CAN1_ERR\r
+DECLARE_IRQ_MAP can1_wake, IRQ_NR_CAN1_WAKE\r
+DECLARE_IRQ_MAP can0_tx, IRQ_NR_CAN0_TX\r
+DECLARE_IRQ_MAP can0_rx, IRQ_NR_CAN0_RX\r
+DECLARE_IRQ_MAP can0_err, IRQ_NR_CAN0_ERR\r
+DECLARE_IRQ_MAP can0_wake, IRQ_NR_CAN0_WAKE\r
+DECLARE_IRQ_MAP flash, IRQ_NR_FLASH\r
+DECLARE_IRQ_MAP eeprom, IRQ_NR_EEPROM\r
+DECLARE_IRQ_MAP spi2, IRQ_NR_SPI2\r
+DECLARE_IRQ_MAP spi1, IRQ_NR_SPI1\r
+DECLARE_IRQ_MAP iic, IRQ_NR_IIC\r
+DECLARE_IRQ_MAP bdlc, IRQ_NR_BDLC\r
+DECLARE_IRQ_MAP selfclk_mode, IRQ_NR_SELFCLK_MODE\r
+DECLARE_IRQ_MAP pll_lock, IRQ_NR_PLL_LOCK\r
+DECLARE_IRQ_MAP accb_overflow, IRQ_NR_ACCB_OVERFLOW\r
+\r
+// DECLARE_IRQ_MAP mccnt_underflow, IRQ_NR_MCCNT_UNDERFLOW\r
+// We need to clear the modulus counter interrupt flag\r
+irq_mccnt_underflow:\r
+ movb #IRQ_NR_MCCNT_UNDERFLOW, -10, sp // save irq nr. above context space\r
+ movb #0x80, MCFLG // clear interrupt flag\r
+ bra Irq_PreEntry\r
\r
-DECLARE_IRQ_MAP(IRQ_NR_RES0)\r
-DECLARE_IRQ_MAP(IRQ_NR_RES1)\r
-DECLARE_IRQ_MAP(IRQ_NR_RES2)\r
-DECLARE_IRQ_MAP(IRQ_NR_RES3)\r
-DECLARE_IRQ_MAP(IRQ_NR_RES4)\r
-DECLARE_IRQ_MAP(IRQ_NR_RES5)\r
-DECLARE_IRQ_MAP(IRQ_NR_PWM_SHUTDOWN)\r
-DECLARE_IRQ_MAP(IRQ_NR_PTPIF)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN4_TX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN4_RX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN4_ERR)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN4_WAKE)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN3_TX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN3_RX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN3_ERR)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN3_WAKE)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN2_TX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN2_RX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN2_ERR)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN2_WAKE)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN1_TX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN1_RX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN1_ERR)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN1_WAKE)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN0_TX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN0_RX)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN0_ERR)\r
-DECLARE_IRQ_MAP(IRQ_NR_CAN0_WAKE)\r
-DECLARE_IRQ_MAP(IRQ_NR_FLASH)\r
-DECLARE_IRQ_MAP(IRQ_NR_EEPROM)\r
-DECLARE_IRQ_MAP(IRQ_NR_SPI2)\r
-DECLARE_IRQ_MAP(IRQ_NR_SPI1)\r
-DECLARE_IRQ_MAP(IRQ_NR_IIC)\r
-DECLARE_IRQ_MAP(IRQ_NR_BDLC)\r
-DECLARE_IRQ_MAP(IRQ_NR_SELFCLK_MODE)\r
-DECLARE_IRQ_MAP(IRQ_NR_PLL_LOCK)\r
-DECLARE_IRQ_MAP(IRQ_NR_ACCB_OVERFLOW)\r
-DECLARE_IRQ_MAP(IRQ_NR_MCCNT_UNDERFLOW)\r
-DECLARE_IRQ_MAP(IRQ_NR_PTHIF)\r
-DECLARE_IRQ_MAP(IRQ_NR_PTJIF)\r
-DECLARE_IRQ_MAP(IRQ_NR_ATD1)\r
-DECLARE_IRQ_MAP(IRQ_NR_ATD0)\r
-DECLARE_IRQ_MAP(IRQ_NR_SCI1)\r
-DECLARE_IRQ_MAP(IRQ_NR_SCI0)\r
-DECLARE_IRQ_MAP(IRQ_NR_SPI0)\r
-DECLARE_IRQ_MAP(IRQ_NR_ACCA_INPUT)\r
-DECLARE_IRQ_MAP(IRQ_NR_ACCA_OVERFLOW)\r
-DECLARE_IRQ_MAP(IRQ_NR_TIMER_OVERFLOW)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC7)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC6)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC5)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC4)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC3)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC2)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC1)\r
-DECLARE_IRQ_MAP(IRQ_NR_TC0)\r
-DECLARE_IRQ_MAP(IRQ_NR_RTII)\r
-DECLARE_IRQ_MAP(IRQ_NR_IRQ)\r
-DECLARE_IRQ_MAP(IRQ_NR_XIRQ)\r
-DECLARE_IRQ_MAP(IRQ_NR_SWI)\r
-DECLARE_IRQ_MAP(IRQ_NR_ILLEGAL)\r
-DECLARE_IRQ_MAP(IRQ_NR_COP_FAIL)\r
-DECLARE_IRQ_MAP(IRQ_NR_COP_CLOCK)\r
+DECLARE_IRQ_MAP pthif, IRQ_NR_PTHIF\r
+DECLARE_IRQ_MAP ptjif, IRQ_NR_PTJIF\r
+DECLARE_IRQ_MAP atd1, IRQ_NR_ATD1\r
+DECLARE_IRQ_MAP atd0, IRQ_NR_ATD0\r
+DECLARE_IRQ_MAP sci1, IRQ_NR_SCI1\r
+DECLARE_IRQ_MAP sci0, IRQ_NR_SCI0\r
+DECLARE_IRQ_MAP spi0, IRQ_NR_SPI0\r
+DECLARE_IRQ_MAP acca_input, IRQ_NR_ACCA_INPUT\r
+DECLARE_IRQ_MAP acca_overflow, IRQ_NR_ACCA_OVERFLOW\r
+DECLARE_IRQ_MAP timer_overflow, IRQ_NR_TIMER_OVERFLOW\r
+DECLARE_IRQ_MAP tc7, IRQ_NR_TC7\r
+DECLARE_IRQ_MAP tc6, IRQ_NR_TC6\r
+DECLARE_IRQ_MAP tc5, IRQ_NR_TC5\r
+DECLARE_IRQ_MAP tc4, IRQ_NR_TC4\r
+DECLARE_IRQ_MAP tc3, IRQ_NR_TC3\r
+DECLARE_IRQ_MAP tc2, IRQ_NR_TC2\r
+DECLARE_IRQ_MAP tc1, IRQ_NR_TC1\r
+DECLARE_IRQ_MAP tc0, IRQ_NR_TC0\r
+DECLARE_IRQ_MAP rtii, IRQ_NR_RTII\r
+DECLARE_IRQ_MAP irq, IRQ_NR_IRQ\r
+DECLARE_IRQ_MAP xirq, IRQ_NR_XIRQ\r
+DECLARE_IRQ_MAP swi, IRQ_NR_SWI\r
+DECLARE_IRQ_MAP illegal, IRQ_NR_ILLEGAL\r
+DECLARE_IRQ_MAP cop_fail, IRQ_NR_COP_FAIL\r
+DECLARE_IRQ_MAP cop_clock, IRQ_NR_COP_CLOCK\r
\r
\r
-/*\r
- * IVOR4\r
- * 1. Save stack frames: EXC, VGPR, NVGPR and C\r
- * 2. Call Irq_Entry(void *curr_stack)\r
- * 2.1 Check for exception\r
- * 2.2 If softint, clear it.\r
- * 2.3 If PROC_ISR1, then just call the function\r
- * 2.4 If PROC_ISR2 -> it's a PCB, let the OS handle it.\r
- */\r
-\r
#define _ASSEMBLER_\r
#include "kernel_offset.h"\r
#include "asm_hc1x.h"\r
-.extern os_intc_pcb_tbl\r
-.extern os_intc_types_tbl\r
-.extern os_sys\r
+#include "context.sx"\r
\r
-/*\r
-#define LOCK() wrteei 0\r
-#define UNLOCK() wrteei 1\r
-*/\r
+.extern os_sys\r
+.extern os_proc_start_extended\r
\r
#define IRQ_ENABLE() cpsie i\r
#define IRQ_DISABLE() cpsid i\r
\r
-.extern os_proc_start_extended\r
-\r
-/*--------------------------------------------------------------------\r
- * void os_swap_context(pcb_t *old, pcb_t *new )\r
- *\r
- * Saves a small context on current stack, pops a new one from new context\r
- *\r
- * r3 - pcb for old process\r
- * r4 - pcb for new process\r
- *\r
- *--------------------------------------------------------------------*/\r
-\r
-// TODO: this assumes that both are in user mode?.. can this happen under trusted functions?\r
-// When I get here we're ALWAYS in kernel mode\r
\r
.global Os_ArchSwapContextToW\r
.global Os_ArchSwapContextTo\r
.global Os_ArchSwapContext\r
.global Os_ArchSetSpAndCall\r
+\r
.section .text\r
\r
Os_ArchSetSpAndCall:\r
GET_ARG_0_TO_X // old --> X\r
GET_ARG_1_TO(y) // new --> Y\r
\r
- movb #0x00, 1,-sp // skip byte\r
- movw _.frame, 2,-sp // restore _.frame\r
- movw _.z, 2,-sp // restore _.z\r
- movw _.xy, 2,-sp // restore _.xy\r
- movw _.tmp ,2,-sp // restore _.tmp\r
- pshy // restore Y\r
- pshx // restore X\r
- pshd // restore D\r
- pshc // restore CCR\r
- movb #0x00, 1,-sp // skip byte\r
+ SAVE_CONTEXT_FROM_FUNCTION\r
\r
sts PCB_STACK_CURR_P, x // SP --> old->stack.curr\r
bra Os_ArchSwapContextTo_do\r
sty os_sys // new (Y) --> os_sys.curr_pcb\r
// Restore context\r
lds PCB_STACK_CURR_P, y // new->stack.curr --> SP\r
- ins // skip byte \r
- pulc // restore CCR\r
- puld // restore D\r
- pulx // restore X\r
- puly // restore Y\r
- movw 2,sp+,_.tmp // restore _.tmp\r
- movw 2,sp+,_.xy // restore _.xy\r
- movw 2,sp+,_.z // restore _.z\r
- movw 2,sp+,_.frame // restore _.frame\r
-\r
- ins // skip byte\r
+ \r
+ RESTORE_CONTEXT_FOR_FUNCTION\r
\r
rtc\r
/*\r
#define SC_PATTERN 0xde\r
#define LC_PATTERN 0xad\r
-/*
-// NVREGS: r4+r5+r6+r7+r8++r10+r11+lr = 9*4 = 36
-#define NVGPR_SIZE 32
-// VGPR: 9*4 = 36
-#define VGPR_SIZE 36
-// SP + context
-#define C_SIZE 8
+#define CONTEXT_SIZE_W 9
-//...
-#define VGPR_LR_OFF (C_SIZE+NVGPR_SIZE-4)
-#define C_CONTEXT_OFF 4
-#define C_SP_OFF 0
-*/
-
-/* Context layout, sizes in 16 bit words */
-// -- STACK TOP, CONTEXT START
-#define C_REG_CCR_OFF 0
-// -- CCR
-#define C_REG_D_OFF 1
-// -- D
-#define C_REG_X_OFF 2
-// -- X
-#define C_REG_Y_OFF 3
-// -- Y
-#define C_REG_TMP_OFF 4
-// -- _.tmp
-#define C_REG_XY_OFF 5
-// -- _.xy
-#define C_REG_Z_OFF 6
-// -- _.z
-#define C_REG_FRAME_OFF 7
-// -- _.frame
-#define C_RETURN_PPAGE_OFF 8
-// -- PPAGE
-#define C_RETURN_ADDR_OFF 9
-// -- ADDR
-#define SC_SIZE 10
-// -- CONTEXT END\r
\r
#endif /* CONTEXT_H_ */\r
--- /dev/null
+\r
+\r
+/*\r
+\r
+ Layout of standard saved context on stack \r
+ (this is the format that we write and read contexts):\r
+ \r
+ (low addr.) (high addr.)\r
+ | | | | | | | | | | | | | | | | | | |\r
+ | frame | z | xy | tmp | P | CCR | B | A | X | Y | Addr |\r
+\r
+ \------------------ softregs -------------------/\r
+ \r
+ P = PPAGE, the bank nr. of the return address\r
+\r
+\r
+ Layout of function call context on stack, \r
+ before we convert it to standard:\r
+ \r
+ (low addr.) (high addr.)\r
+ | | | |\r
+ | P | Addr |\r
+\r
+\r
+ Layout of interrupt context on stack, \r
+ before we convert it to standard:\r
+ \r
+ (low addr.) (high addr.)\r
+ | | | | | | | | | |\r
+ | CCR | B | A | X | Y | Addr |\r
+\r
+\r
+*/\r
+\r
+.macro SAVE_CONTEXT_FROM_FUNCTION\r
+ staa -4, sp // save A -> ctx(A)\r
+ ldaa 0, sp // load callctx(P) -> A *\r
+ sty 1, -sp // save Y -> ctx(Y)\r
+ stx 2, -sp // save X -> ctx(X)\r
+ stab 2, -sp // save B -> ctx(B) (skipping ctx(A))\r
+ pshc // save CCR -> ctx(CCR)\r
+ psha // save P -> ctx(P) *\r
+ movw _.tmp ,2,-sp // save tmp -> ctx(tmp)\r
+ movw _.xy, 2,-sp // save xy -> ctx(xy)\r
+ movw _.z, 2,-sp // save z -> ctx(z)\r
+ movw _.frame, 2,-sp // save frame -> ctx(frame)\r
+.endm\r
+\r
+.macro RESTORE_CONTEXT_FOR_FUNCTION\r
+ movw 2,sp+, _.frame // load frame <- ctx(frame)\r
+ movw 2,sp+, _.z // load z <- ctx(z)\r
+ movw 2,sp+, _.xy // load xy <- ctx(xy)\r
+ movw 2,sp+, _.tmp // load tmp <- ctx(tmp)\r
+ ldy 6,sp // load Y <- ctx(Y)\r
+ movb 1,sp+, 6,sp // move ctx(P) -> callctx(P)\r
+ pulc // load CCR <- ctx(CCR)\r
+ puld // load D <- ctx(D)\r
+ pulx // load X <- ctx(X)\r
+ ins // skipping ctx(Yh)\r
+\r
+.endm\r
+\r
+\r
+.macro SAVE_CONTEXT_FROM_INTERRUPT\r
+ movb PPAGE, 1,-sp // save P -> ctx(P) \r
+ movw _.tmp ,2,-sp // save tmp -> ctx(tmp)\r
+ movw _.xy, 2,-sp // save xy -> ctx(xy)\r
+ movw _.z, 2,-sp // save z -> ctx(z)\r
+ movw _.frame, 2,-sp // save frame -> ctx(frame)\r
+.endm\r
+\r
+.macro RESTORE_CONTEXT_FOR_INTERRUPT\r
+ movw 2,sp+, _.frame // load frame <- ctx(frame)\r
+ movw 2,sp+, _.z // load z <- ctx(z)\r
+ movw 2,sp+, _.xy // load xy <- ctx(xy)\r
+ movw 2,sp+, _.tmp // load tmp <- ctx(tmp)\r
+ movb 1,sp+, PPAGE // load P <- ctx(P)\r
+\r
+.endm
\ No newline at end of file
#include "internal.h"
#include "irq.h"
+#include "irq_types.h"
+#include "regs.h"
extern void * Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
extern uint8 Irq_IsrTypeTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
}
-void *Irq_Entry( uint8 irq_nr )
+void bad_irq(uint8_t irq_nr) {
+ for (;;);
+}
+
+void *Irq_Entry( uint8_t irq_nr, void *stack )
{
- if( Irq_GetIsrType(vector) == ISR_TYPE_1 ) {
+ void* vector = (void *)Irq_VectorTable[irq_nr];
+
+ // trap uninitialized interrupts
+ if (vector == NULL) {
+ bad_irq(irq_nr);
+ }
+
+ if( Irq_GetIsrType(irq_nr) == ISR_TYPE_1 ) {
// It's a function, just call it.
- ((func_t)Irq_VectorTable[vector])();
+ ((func_t)vector)();
return stack;
+
} else {
// It's a PCB
// Let the kernel handle the rest,
- return Os_Isr(stack, (void *)Irq_VectorTable[vector]);
+ return Os_Isr(stack, vector);
}
}
return prio;
}
-void bad_int()
-{
- for (;;);
-}
-
// ##################### INTERRUPT TRANSLATE TABLE #######################
#define IRQ_MAP(x) irq_##x
const struct interrupt_vectors __attribute__((section(".vectors"))) vectors =
{
pwm_shutdown_handler:
- IRQ_MAP(IRQ_NR_PWM_SHUTDOWN),
+ IRQ_MAP(pwm_shutdown),
ptpif_handler:
- IRQ_MAP(IRQ_NR_PTPIF),
+ IRQ_MAP(ptpif),
can4_tx_handler:
- IRQ_MAP(IRQ_NR_CAN4_TX),
+ IRQ_MAP(can4_tx),
can4_rx_handler:
- IRQ_MAP(IRQ_NR_CAN4_RX),
+ IRQ_MAP(can4_rx),
can4_err_handler:
- IRQ_MAP(IRQ_NR_CAN4_ERR),
+ IRQ_MAP(can4_err),
can4_wake_handler:
- IRQ_MAP(IRQ_NR_CAN4_WAKE),
+ IRQ_MAP(can4_wake),
can3_tx_handler:
- IRQ_MAP(IRQ_NR_CAN3_TX),
+ IRQ_MAP(can3_tx),
can3_rx_handler:
- IRQ_MAP(IRQ_NR_CAN3_RX),
+ IRQ_MAP(can3_rx),
can3_err_handler:
- IRQ_MAP(IRQ_NR_CAN3_ERR),
+ IRQ_MAP(can3_err),
can3_wake_handler:
- IRQ_MAP(IRQ_NR_CAN3_WAKE),
+ IRQ_MAP(can3_wake),
can2_tx_handler:
- IRQ_MAP(IRQ_NR_CAN2_TX),
+ IRQ_MAP(can2_tx),
can2_rx_handler:
- IRQ_MAP(IRQ_NR_CAN2_RX),
+ IRQ_MAP(can2_rx),
can2_err_handler:
- IRQ_MAP(IRQ_NR_CAN2_ERR),
+ IRQ_MAP(can2_err),
can2_wake_handler:
- IRQ_MAP(IRQ_NR_CAN2_WAKE),
+ IRQ_MAP(can2_wake),
can1_tx_handler:
- IRQ_MAP(IRQ_NR_CAN1_TX),
+ IRQ_MAP(can1_tx),
can1_rx_handler:
- IRQ_MAP(IRQ_NR_CAN1_RX),
+ IRQ_MAP(can1_rx),
can1_err_handler:
- IRQ_MAP(IRQ_NR_CAN1_ERR),
+ IRQ_MAP(can1_err),
can1_wake_handler:
- IRQ_MAP(IRQ_NR_CAN1_WAKE),
+ IRQ_MAP(can1_wake),
can0_tx_handler:
- IRQ_MAP(IRQ_NR_CAN0_TX),
+ IRQ_MAP(can0_tx),
can0_rx_handler:
- IRQ_MAP(IRQ_NR_CAN0_RX),
+ IRQ_MAP(can0_rx),
can0_err_handler:
- IRQ_MAP(IRQ_NR_CAN0_ERR),
+ IRQ_MAP(can0_err),
can0_wake_handler:
- IRQ_MAP(IRQ_NR_CAN0_WAKE),
+ IRQ_MAP(can0_wake),
flash_handler:
- IRQ_MAP(IRQ_NR_FLASH),
+ IRQ_MAP(flash),
eeprom_handler:
- IRQ_MAP(IRQ_NR_EEPROM),
+ IRQ_MAP(eeprom),
spi2_handler:
- IRQ_MAP(IRQ_NR_SPI2),
+ IRQ_MAP(spi2),
spi1_handler:
- IRQ_MAP(IRQ_NR_SPI1),
+ IRQ_MAP(spi1),
iic_handler:
- IRQ_MAP(IRQ_NR_IIC),
+ IRQ_MAP(iic),
bdlc_handler:
- IRQ_MAP(IRQ_NR_BDLC),
+ IRQ_MAP(bdlc),
selfclk_mode_handler:
- IRQ_MAP(IRQ_NR_SELFCLK_MODE),
+ IRQ_MAP(selfclk_mode),
pll_lock_handler:
- IRQ_MAP(IRQ_NR_PLL_LOCK),
+ IRQ_MAP(pll_lock),
accb_overflow_handler:
- IRQ_MAP(IRQ_NR_ACCB_OVERFLOW),
+ IRQ_MAP(accb_overflow),
mccnt_underflow_handler:
- IRQ_MAP(IRQ_NR_MCCNT_UNDERFLOW),
+ IRQ_MAP(mccnt_underflow),
pthif_handler:
- IRQ_MAP(IRQ_NR_PTHIF),
+ IRQ_MAP(pthif),
ptjif_handler:
- IRQ_MAP(IRQ_NR_PTJIF),
+ IRQ_MAP(ptjif),
atd1_handler:
- IRQ_MAP(IRQ_NR_ATD1),
+ IRQ_MAP(atd1),
atd0_handler:
- IRQ_MAP(IRQ_NR_ATD0),
+ IRQ_MAP(atd0),
sci1_handler:
- IRQ_MAP(IRQ_NR_SCI1),
+ IRQ_MAP(sci1),
sci0_handler:
- IRQ_MAP(IRQ_NR_SCI0),
+ IRQ_MAP(sci0),
spi0_handler:
- IRQ_MAP(IRQ_NR_SPI0),
+ IRQ_MAP(spi0),
// Timer and Accumulator
acca_input_handler:
- IRQ_MAP(IRQ_NR_ACCA_INPUT),
+ IRQ_MAP(acca_input),
acca_overflow_handler:
- IRQ_MAP(IRQ_NR_ACCA_OVERFLOW),
+ IRQ_MAP(acca_overflow),
timer_overflow_handler:
- IRQ_MAP(IRQ_NR_TIMER_OVERFLOW),
+ IRQ_MAP(timer_overflow),
// InputCapture/OutputCompare Timers
tc7_handler:
- IRQ_MAP(IRQ_NR_TC7),
+ IRQ_MAP(tc7),
tc6_handler:
- IRQ_MAP(IRQ_NR_TC6),
+ IRQ_MAP(tc6),
tc5_handler:
- IRQ_MAP(IRQ_NR_TC5),
+ IRQ_MAP(tc5),
tc4_handler:
- IRQ_MAP(IRQ_NR_TC4),
+ IRQ_MAP(tc4),
tc3_handler:
- IRQ_MAP(IRQ_NR_TC3),
+ IRQ_MAP(tc3),
tc2_handler:
- IRQ_MAP(IRQ_NR_TC2),
+ IRQ_MAP(tc2),
tc1_handler:
- IRQ_MAP(IRQ_NR_TC1),
+ IRQ_MAP(tc1),
tc0_handler:
- IRQ_MAP(IRQ_NR_TC0),
+ IRQ_MAP(tc0),
// External Interrupts
rtii_handler:
- IRQ_MAP(IRQ_NR_RTII),
+ IRQ_MAP(rtii),
irq_handler:
- IRQ_MAP(IRQ_NR_IRQ),
+ IRQ_MAP(irq),
xirq_handler:
- IRQ_MAP(IRQ_NR_XIRQ),
+ IRQ_MAP(xirq),
// Vectors in use
swi_handler:
- IRQ_MAP(IRQ_NR_SWI),
+ IRQ_MAP(swi),
illegal_handler:
- IRQ_MAP(IRQ_NR_ILLEGAL),
+ IRQ_MAP(illegal),
cop_fail_handler:
- IRQ_MAP(IRQ_NR_COP_FAIL),
+ IRQ_MAP(cop_fail),
cop_clock_handler:
- IRQ_MAP(IRQ_NR_COP_CLOCK),
+ IRQ_MAP(cop_clock),
reset_handler:
_start,
#include "irq_defines.h"
+#define DECLARE_IRQ_PROTOTYPE(x) \
+void irq_##x (void);
+
+
+DECLARE_IRQ_PROTOTYPE(res0)
+DECLARE_IRQ_PROTOTYPE(res1)
+DECLARE_IRQ_PROTOTYPE(res2)
+DECLARE_IRQ_PROTOTYPE(res3)
+DECLARE_IRQ_PROTOTYPE(res4)
+DECLARE_IRQ_PROTOTYPE(res5)
+DECLARE_IRQ_PROTOTYPE(pwm_shutdown)
+DECLARE_IRQ_PROTOTYPE(ptpif)
+DECLARE_IRQ_PROTOTYPE(can4_tx)
+DECLARE_IRQ_PROTOTYPE(can4_rx)
+DECLARE_IRQ_PROTOTYPE(can4_err)
+DECLARE_IRQ_PROTOTYPE(can4_wake)
+DECLARE_IRQ_PROTOTYPE(can3_tx)
+DECLARE_IRQ_PROTOTYPE(can3_rx)
+DECLARE_IRQ_PROTOTYPE(can3_err)
+DECLARE_IRQ_PROTOTYPE(can3_wake)
+DECLARE_IRQ_PROTOTYPE(can2_tx)
+DECLARE_IRQ_PROTOTYPE(can2_rx)
+DECLARE_IRQ_PROTOTYPE(can2_err)
+DECLARE_IRQ_PROTOTYPE(can2_wake)
+DECLARE_IRQ_PROTOTYPE(can1_tx)
+DECLARE_IRQ_PROTOTYPE(can1_rx)
+DECLARE_IRQ_PROTOTYPE(can1_err)
+DECLARE_IRQ_PROTOTYPE(can1_wake)
+DECLARE_IRQ_PROTOTYPE(can0_tx)
+DECLARE_IRQ_PROTOTYPE(can0_rx)
+DECLARE_IRQ_PROTOTYPE(can0_err)
+DECLARE_IRQ_PROTOTYPE(can0_wake)
+DECLARE_IRQ_PROTOTYPE(flash)
+DECLARE_IRQ_PROTOTYPE(eeprom)
+DECLARE_IRQ_PROTOTYPE(spi2)
+DECLARE_IRQ_PROTOTYPE(spi1)
+DECLARE_IRQ_PROTOTYPE(iic)
+DECLARE_IRQ_PROTOTYPE(bdlc)
+DECLARE_IRQ_PROTOTYPE(selfclk_mode)
+DECLARE_IRQ_PROTOTYPE(pll_lock)
+DECLARE_IRQ_PROTOTYPE(accb_overflow)
+DECLARE_IRQ_PROTOTYPE(mccnt_underflow)
+DECLARE_IRQ_PROTOTYPE(pthif)
+DECLARE_IRQ_PROTOTYPE(ptjif)
+DECLARE_IRQ_PROTOTYPE(atd1)
+DECLARE_IRQ_PROTOTYPE(atd0)
+DECLARE_IRQ_PROTOTYPE(sci1)
+DECLARE_IRQ_PROTOTYPE(sci0)
+DECLARE_IRQ_PROTOTYPE(spi0)
+DECLARE_IRQ_PROTOTYPE(acca_input)
+DECLARE_IRQ_PROTOTYPE(acca_overflow)
+DECLARE_IRQ_PROTOTYPE(timer_overflow)
+DECLARE_IRQ_PROTOTYPE(tc7)
+DECLARE_IRQ_PROTOTYPE(tc6)
+DECLARE_IRQ_PROTOTYPE(tc5)
+DECLARE_IRQ_PROTOTYPE(tc4)
+DECLARE_IRQ_PROTOTYPE(tc3)
+DECLARE_IRQ_PROTOTYPE(tc2)
+DECLARE_IRQ_PROTOTYPE(tc1)
+DECLARE_IRQ_PROTOTYPE(tc0)
+DECLARE_IRQ_PROTOTYPE(rtii)
+DECLARE_IRQ_PROTOTYPE(irq)
+DECLARE_IRQ_PROTOTYPE(xirq)
+DECLARE_IRQ_PROTOTYPE(swi)
+DECLARE_IRQ_PROTOTYPE(illegal)
+DECLARE_IRQ_PROTOTYPE(cop_fail)
+DECLARE_IRQ_PROTOTYPE(cop_clock)
+
typedef enum
{
IRQ_TYPE_RES0,
#include "internal.h"
#include "irq.h"
#include "arc.h"
+#include "regs.h"
\r
/**\r
* Init of free running timer.\r
*/\r
void Os_SysTickInit( void ) {
-#if 0\r
+ // Set timer 0 as output compare. Timer 0 is reserved for the OS.
+
+ // TEN, timer enable
+ // TSFRZ, stop in freeze mode (easier debugging)
+ TSCR1 = TEN | TSFRZ;
+
+ // Modulus counter
+ // MCZI, enable interrupt, MCEN enable modulus counter
+ // Prescaler 4
+ MCCTL = MCZI | MCEN | MCPRE_VAL_4;
+
+ // Set auto-reload
+ MCCTL |= MODMC;
+
+ // time = (count * prescaler)/(bus frequency)
+ // = (0xFA0 * 4)/(16*10^6)
+ // = 1ms
+ MCCNT = 0xFA0;
+
+ ICSYS = 0;
+\r
TaskType tid;\r
- tid = Os_Arc_CreateIsr(OsTick,6/*prio*/,"OsTick");\r
- Irq_AttachIsr2(tid,NULL,7);
-#endif\r
+ tid = Os_Arc_CreateIsr(OsTick, 6/*prio*/, "OsTick");\r
+ Irq_AttachIsr2(tid, NULL, IRQ_TYPE_MCCNT_UNDERFLOW);\r
}\r
\r
/**\r
* on PowerPC often driver by the CPU clock or some platform clock.\r
*
*/\r
-void Os_SysTickStart(uint32_t period_ticks) {\r
-#if 0
- uint32_t tmp;\r
-\r
- // Enable the TB\r
- tmp = get_spr(SPR_HID0);\r
- tmp |= HID0_TBEN;\r
- set_spr(SPR_HID0, tmp);\r
+void Os_SysTickStart(uint32_t period_ticks) {
\r
- /* Initialize the Decrementer */\r
- set_spr(SPR_DEC, period_ticks);\r
- set_spr(SPR_DECAR, period_ticks);\r
-\r
- /* Set autoreload */\r
- tmp = get_spr(SPR_TCR);\r
- tmp |= TCR_ARE;\r
- set_spr(SPR_TCR, tmp);\r
-\r
- /* Enable notification */\r
- tmp = get_spr(SPR_TCR);\r
- tmp |= TCR_DIE;\r
- set_spr(SPR_TCR, tmp );
-#endif\r
}\r
\r
/**\r
# What buildable modules does this board have,
# default or private
-MOD_AVAIL=KERNEL MCU T32_TERM WINIDEA_TERM SIMPLE_PRINTF
+MOD_AVAIL=KERNEL MCU T32_TERM WINIDEA_TERM SIMPLE_PRINTF GPT
# Needed by us
-MOD_USE=KERNEL MCU
+MOD_USE=KERNEL MCU GPT
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_0,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = TRUE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_1,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_2,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_3,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_4,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_5,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_6,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_7,\r
+ .GptChannelMode = GPT_MODE_CONTINUOUS,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_8,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptEnableWakeup = FALSE,\r
+ },
+ {\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Gpt GPT Driver
+ * @{ */
+
+/** @file Gpt_Cfg.h
+ * Definitions of configuration parameters for GPT Driver.
+ */
+
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Configuration is pre-compile only. Not supported. */
+#define GPT_VARIANT_PC STD_OFF\r
+/** Configuration is a mix of pre-compile and post-build */
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/** HW channels */\r
+#define GPT_CHANNEL_0 0\r
+#define GPT_CHANNEL_1 1\r
+#define GPT_CHANNEL_2 2\r
+#define GPT_CHANNEL_3 3\r
+#define GPT_CHANNEL_4 4\r
+#define GPT_CHANNEL_5 5\r
+#define GPT_CHANNEL_6 6\r
+#define GPT_CHANNEL_7 7\r
+#define GPT_CHANNEL_8 8\r
+\r
+#define GPT_CHANNEL_CNT 9\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+/** Enable Development Error Trace */
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+/** Enables/Disables wakeup source reporting. Not supported. */
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+/** Build DeInit API */
+#define GPT_DEINIT_API STD_ON
+/** Build notification API */
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON
+/** Build time remaining API */
+#define GPT_TIME_REMAINING_API STD_ON
+/** Build time elapsed API */
+#define GPT_TIME_ELAPSED_API STD_ON
+/** Build version info API */
+#define GPT_VERSION_INFO_API STD_ON\r
+/** Build wakeup API. Not supported */
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+/** This container contains the channel-wide configuration (parameters) of the
+ * GPT Driver */
+typedef struct {\r
+ /** GPT187: The GPT module specific clock input for the timer unit can
+ * statically be configured and allows to select different clock sources
+ * (external clock, internal GPT specific clock) per channel */
+ uint32 GptChannelClkSrc;\r
+\r
+ /** Channel Id of the GPT channel. */
+ Gpt_ChannelType GptChannelId;\r
+\r
+ /** Specifies the behaviour of the timer channel after the timeout has expired. */
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ /** Function pointer to callback function */
+ void (*GptNotification)();\r
+\r
+ /** GPT module specific prescaler factor per channel
+ * Not available on HCS12
+ */
+ //uint32 GptChannelPrescale;\r
+\r
+ /** GPT188: Enables wakeup capability of CPU for a channel when timeout
+ * period expires. This might be different to enabling the notification
+ * depending on hardware capabilities. Not supported. */
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+
+/** The list of channel configurations */
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/
+/** @} */
#define GET_ARG_2(reg) \
ld##reg ARG_2_STACK_OFFS,x;
-// Macro used to create the IRQ mapping table
-#define DECLARE_IRQ_MAP(x) \
-irq_##x: \
- movb ##x, CSize;SP \
- bra Irq_PreEntry \\r
\r
#endif /*ASM_HC1X_H_*/\r
#define IRQ_NR_SPI1 31\r
#define IRQ_NR_IIC 32\r
#define IRQ_NR_BDLC 33\r
-#define IRQ_NR_SELFCLK34_MODE\r
+#define IRQ_NR_SELFCLK_MODE 34\r
#define IRQ_NR_PLL_LOCK 35\r
#define IRQ_NR_ACCB_OVERFLOW 36\r
#define IRQ_NR_MCCNT_UNDERFLOW 37\r
--- /dev/null
+#ifndef _REGS_H_\r
+#define _REGS_H_\r
+\r
+#define IO_BASE 0\r
+\r
+#define ienable() __asm("cli");\r
+#define idisable() __asm("orcc #0x10")\r
+#define xenable() __asm("andcc #0xbf")\r
+#define xdisable()__asm("orcc #0x40")\r
+\r
+/**\r
+ * constant offsets to use where a C expression doesn't work\r
+ * You may use it with GEL\r
+ */\r
+#define M6811_PORTA 0x00\r
+#define M6811_PORTB 0x01\r
+#define M6811_PTT 0x240\r
+#define M6811_PTM 0x250\r
+#define M6811_PTP 0x258\r
+#define M6811_PTH 0x260\r
+\r
+#define PORTIO_8 *(volatile unsigned char *)\r
+#define PORTIO_16 *(volatile unsigned short int *)\r
+\r
+\r
+/* \r
+ * Core HC12 Registers\r
+ */\r
+#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
+#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
+#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
+#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
+#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
+#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
+#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
+#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
+#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
+#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
+#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
+#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
+#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
+#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
+#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
+#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
+#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
+#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
+#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
+#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
+#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
+#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
+#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
+#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
+\r
+// Bitflags - PEAR\r
+#define NOACCE 0x80\r
+#define PIPOE 0x20\r
+#define NECLK 0x10\r
+#define LSTRE 0x08\r
+#define RDWE 0x04\r
+\r
+// INTCR bitflags\r
+#define IRQE 0x80\r
+#define IRQEN 0x40\r
+#define DLY 0x20\r
+\r
+// BKP Module\r
+#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
+#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
+#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
+#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
+#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
+#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
+\r
+// MEBI Module \r
+#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
+#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
+#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
+\r
+// CRG Module \r
+#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
+#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
+#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
+#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
+#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
+#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
+#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
+#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
+#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
+#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
+#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
+#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
+\r
+// CRG bitflags\r
+#define RTIF 0x80\r
+#define RTIE 0x80\r
+#define LOCK 0x08\r
+#define AUTO 0x20\r
+#define PLLSEL 0x80\r
+\r
+// COPCTL bitflags\r
+#define WCOP 0x80\r
+#define RSBCK 0x40\r
+\r
+// ECT Module\r
+#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
+#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
+#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
+#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
+#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
+#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
+#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
+#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
+#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
+#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
+#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
+#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
+#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
+#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
+#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
+#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
+#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
+#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
+#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
+#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
+#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
+#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
+#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
+#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
+#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
+#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
+#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
+#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
+#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
+#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
+#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
+#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
+#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
+#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
+#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
+#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
+#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
+#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
+#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
+#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
+#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
+#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
+#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
+#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
+#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
+#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
+#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
+\r
+#define TEN 0x80\r
+#define TSFRZ 0x20\r
+#define TOI 0x80\r
+#define MCZI 0x80\r
+#define MODMC 0x40\r
+#define MCEN 0x4\r
+#define MCPR1 0x2\r
+#define MCPR0 0x1\r
+\r
+#define MCPRE_VAL_1 0\r
+#define MCPRE_VAL_4 MCPR0\r
+#define MCPRE_VAL_8 MCPR1\r
+#define MCPRE_VAL_16 MCPR0 | MCPR1\r
+\r
+// ATD0 Module \r
+#define ATD0_BASE (IO_BASE + 0x80)\r
+#define ATD0CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D0 control register 0 */\r
+#define ATD0CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D0 control register 1 */\r
+#define ATD0CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D0 control register 2 */\r
+#define ATD0CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D0 control register 3 */\r
+#define ATD0CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D0 control register 4 */\r
+#define ATD0CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D0 control register 5 */\r
+#define ATD0STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D0 status register 0 */\r
+#define ATD0STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D0 status register 1 */\r
+#define ATD0TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D0 test register 0 */\r
+#define ATD0TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D0 test register 1 */\r
+#define ATD0DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D0 interrupt enable */\r
+#define PORTAD0 PORTIO_8(IO_BASE + 0x8f) /* port AD0 data input register */\r
+#define ATD0DR0 PORTIO_16(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR0H PORTIO_8(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR1 PORTIO_16(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR1H PORTIO_8(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR2 PORTIO_16(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR2H PORTIO_8(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR3 PORTIO_16(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR3H PORTIO_8(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR4 PORTIO_16(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR4H PORTIO_8(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+#define ATD0DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+\r
+// ATDnCTL5 bitflags\r
+#define DJM 0x80\r
+#define DSGN 0x40\r
+#define SCAN 0x20\r
+#define MULT 0x10\r
+\r
+// ATDnSTAT0 bitflags\r
+#define SCF 0x80\r
+#define ETORF 0x20\r
+#define FIFOR 0x10\r
+\r
+// PWM Module \r
+#define PWME PORTIO_8(IO_BASE + 0xa0) /* PWM Enable */\r
+#define PWMPOL PORTIO_8(IO_BASE + 0xa1) /* PWM Clock Polarity */\r
+#define PWMCLK PORTIO_8(IO_BASE + 0xa2) /* PWM Clocks */\r
+#define PWMPRCLK PORTIO_8(IO_BASE + 0xa3) /* PWM prescale clock select */\r
+#define PWMCAE PORTIO_8(IO_BASE + 0xa4) /* PWM center align enable */\r
+#define PWMCTL PORTIO_8(IO_BASE + 0xa5) /* PWM Control Register */\r
+#define PWMTST PORTIO_8(IO_BASE + 0xa6) /* PWM Test Register */\r
+#define PWMPRSC PORTIO_8(IO_BASE + 0xa7) /* PWM Test Register */\r
+#define PWMSCLA PORTIO_8(IO_BASE + 0xa8) /* PWM scale A */\r
+#define PWMSCLB PORTIO_8(IO_BASE + 0xa9) /* PWM scale B */\r
+#define PWMSCNTA PORTIO_8(IO_BASE + 0xaa) /* PWM Test Register A */\r
+#define PWMSCNTB PORTIO_8(IO_BASE + 0xab) /* PWM Test Register B */\r
+#define PWMCNT0 PORTIO_8(IO_BASE + 0xac) /* PWM Channel Counter 0 */\r
+#define PWMCNT1 PORTIO_8(IO_BASE + 0xad) /* PWM Channel Counter 1 */\r
+#define PWMCNT2 PORTIO_8(IO_BASE + 0xae) /* PWM Channel Counter 2 */\r
+#define PWMCNT3 PORTIO_8(IO_BASE + 0xaf) /* PWM Channel Counter 3 */\r
+#define PWMCNT4 PORTIO_8(IO_BASE + 0xb0) /* PWM Channel Counter 4 */\r
+#define PWMCNT5 PORTIO_8(IO_BASE + 0xb1) /* PWM Channel Counter 5 */\r
+#define PWMCNT6 PORTIO_8(IO_BASE + 0xb2) /* PWM Channel Counter 6 */\r
+#define PWMCNT7 PORTIO_8(IO_BASE + 0xb3) /* PWM Channel Counter 7 */\r
+#define PWMPER0 PORTIO_8(IO_BASE + 0xb4) /* PWM Channel Period 0 */\r
+#define PWMPER1 PORTIO_8(IO_BASE + 0xb5) /* PWM Channel Period 1 */\r
+#define PWMPER2 PORTIO_8(IO_BASE + 0xb6) /* PWM Channel Period 2 */\r
+#define PWMPER3 PORTIO_8(IO_BASE + 0xb7) /* PWM Channel Period 3 */\r
+#define PWMPER4 PORTIO_8(IO_BASE + 0xb8) /* PWM Channel Period 4 */\r
+#define PWMPER5 PORTIO_8(IO_BASE + 0xb9) /* PWM Channel Period 5 */\r
+#define PWMPER6 PORTIO_8(IO_BASE + 0xba) /* PWM Channel Period 6 */\r
+#define PWMPER7 PORTIO_8(IO_BASE + 0xbb) /* PWM Channel Period 7 */\r
+#define PWMDTY0 PORTIO_8(IO_BASE + 0xbc) /* PWM Channel Duty 0 */\r
+#define PWMDTY1 PORTIO_8(IO_BASE + 0xbd) /* PWM Channel Duty 1 */\r
+#define PWMDTY2 PORTIO_8(IO_BASE + 0xbe) /* PWM Channel Duty 2 */\r
+#define PWMDTY3 PORTIO_8(IO_BASE + 0xbf) /* PWM Channel Duty 3 */\r
+#define PWMDTY4 PORTIO_8(IO_BASE + 0xc0) /* PWM Channel Duty 4 */\r
+#define PWMDTY5 PORTIO_8(IO_BASE + 0xc1) /* PWM Channel Duty 5 */\r
+#define PWMDTY6 PORTIO_8(IO_BASE + 0xc2) /* PWM Channel Duty 6 */\r
+#define PWMDTY7 PORTIO_8(IO_BASE + 0xc3) /* PWM Channel Duty 7 */\r
+#define PWMSDN PORTIO_8(IO_BASE + 0xc4) /* PWM shutdown register */\r
+\r
+#define PWMCNT01_16BIT PORTIO_16(IO_BASE + 0xac) /* pwm channel 0,1 counter, 16bit */\r
+#define PWMCNT23_16BIT PORTIO_16(IO_BASE + 0xae) /* pwm channel 2,3 counter, 16bit */\r
+#define PWMCNT45_16BIT PORTIO_16(IO_BASE + 0xb0) /* pwm channel 4,5 counter, 16bit */\r
+#define PWMCNT67_16BIT PORTIO_16(IO_BASE + 0xb2) /* pwm channel 6,7 counter, 16bit */\r
+#define PWMPER01_16BIT PORTIO_16(IO_BASE + 0xb4) /* pwm channel 0,1 period, 16bit */\r
+#define PWMPER23_16BIT PORTIO_16(IO_BASE + 0xb6) /* pwm channel 2,3 period, 16bit */\r
+#define PWMPER45_16BIT PORTIO_16(IO_BASE + 0xb8) /* pwm channel 4,5 period, 16bit */\r
+#define PWMPER67_16BIT PORTIO_16(IO_BASE + 0xba) /* pwm channel 6,7 period, 16bit */\r
+#define PWMDTY01_16BIT PORTIO_16(IO_BASE + 0xbc) /* pwm channel 0,1 duty cycle, 16bit */\r
+#define PWMDTY23_16BIT PORTIO_16(IO_BASE + 0xbe) /* pwm channel 2,3 duty cycle, 16bit */\r
+#define PWMDTY45_16BIT PORTIO_16(IO_BASE + 0xc0) /* pwm channel 4,5 duty cycle, 16bit */\r
+#define PWMDTY67_16BIT PORTIO_16(IO_BASE + 0xc2) /* pwm channel 6,7 duty cycle, 16bit */\r
+\r
+\r
+\r
+// SCI register offsets\r
+#define _SCIBD 0x0 /* SCI baud rate high */\r
+#define _SCIBDH 0x0 /* SCI baud rate high */\r
+#define _SCIBDL 0x1 /* SCI baud rate low */\r
+#define _SCICR1 0x2 /* SCI control register 1 */\r
+#define _SCICR2 0x3 /* SCI control register 2 */\r
+#define _SCISR1 0x4 /* SCI status register 1 */\r
+#define _SCISR2 0x5 /* SCI status register 2 */\r
+#define _SCIDRH 0x6 /* SCI data register high */\r
+#define _SCIDRL 0x7 /* SCI data register low */\r
+\r
+// SCI0 Module\r
+#define SCI0_BASE (IO_BASE + 0xc8)\r
+#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
+#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
+#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
+#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
+#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
+#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
+#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
+\r
+// SCI1 Module \r
+#define SCI1_BASE (IO_BASE + 0xd0)\r
+#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
+#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
+#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
+#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
+#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
+#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
+#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
+#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
+#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
+\r
+// SCInSR1\r
+#define TDRE 0x80\r
+#define RDRF 0x20\r
+#define IDLE 0x10\r
+\r
+// SPI register offsets\r
+#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
+#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
+#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
+#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
+#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
+\r
+// SPI0 Module \r
+#define SPI0_BASE (IO_BASE + 0xd8)\r
+#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
+#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
+#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
+#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
+#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
+\r
+// SPInCR1\r
+#define SPIE 0x80\r
+#define SPE 0x40\r
+#define SPTIE 0x20\r
+#define MSTR 0x10\r
+#define CPOL 0x08\r
+#define CPHA 0x04\r
+#define SSOE 0x02\r
+#define LSBFE 0x01\r
+\r
+// SPInSR\r
+#define SPIF 0x80\r
+#define SPTEF 0x20\r
+#define MODF 0x10\r
+\r
+// I2C Module \r
+#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
+#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
+#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
+#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
+#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
+\r
+// IBSR\r
+#define TCF 0x80\r
+#define IAAS 0x40\r
+#define IBB 0x20\r
+#define IBAL 0x10\r
+#define SRW 0x04\r
+#define IBIF 0x02\r
+#define RXAK 0x01\r
+\r
+// BDLC Module\r
+#define DLCBCR1 PORTIO_8(IO_BASE + 0xe8) /* BDLC control register 1 */\r
+#define DLCBSVR PORTIO_8(IO_BASE + 0xe9) /* BDLC state vector register */\r
+#define DLCBCR2 PORTIO_8(IO_BASE + 0xea) /* BDLC control register 2 */\r
+#define DLCBDR PORTIO_8(IO_BASE + 0xeb) /* BDLC data register */\r
+#define DLCBARD PORTIO_8(IO_BASE + 0xec) /* BDLC analog round trip delay */\r
+#define DLCBRSR PORTIO_8(IO_BASE + 0xed) /* BDLC rate select register */\r
+#define DLCSCR PORTIO_8(IO_BASE + 0xee) /* BDLC control register */\r
+#define DLCBSTAT PORTIO_8(IO_BASE + 0xef) /* BDLC status register */\r
+\r
+// SPI1 Module\r
+#define SPI1_BASE (IO_BASE + 0xf0)\r
+#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
+#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
+#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
+#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
+#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
+\r
+// SPI2 Module\r
+#define SPI2_BASE (IO_BASE + 0xf8)\r
+#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
+#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
+#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
+#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
+#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
+\r
+// FLC Module\r
+#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
+#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
+#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
+#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
+#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
+#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
+\r
+// EEPROM Module\r
+#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
+#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
+#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
+#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
+#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
+\r
+// ATD1 Module \r
+#define ATD1_BASE (IO_BASE + 0x120)\r
+#define ATD1CTL0 PORTIO_8(IO_BASE + 0x120) /* A/D1 control register 0 */\r
+#define ATD1CTL1 PORTIO_8(IO_BASE + 0x121) /* A/D1 control register 1 */\r
+#define ATD1CTL2 PORTIO_8(IO_BASE + 0x122) /* A/D1 control register 2 */\r
+#define ATD1CTL3 PORTIO_8(IO_BASE + 0x123) /* A/D1 control register 3 */\r
+#define ATD1CTL4 PORTIO_8(IO_BASE + 0x124) /* A/D1 control register 4 */\r
+#define ATD1CTL5 PORTIO_8(IO_BASE + 0x125) /* A/D1 control register 5 */\r
+#define ATD1STAT0 PORTIO_8(IO_BASE + 0x126) /* A/D1 status register 0 */\r
+#define ATD1STAT1 PORTIO_8(IO_BASE + 0x127) /* A/D1 status register 1 */\r
+#define ATD1TEST0 PORTIO_8(IO_BASE + 0x128) /* A/D1 test register 0 */\r
+#define ATD1TEST1 PORTIO_8(IO_BASE + 0x129) /* A/D1 test register 1 */\r
+#define ATD1DIEN PORTIO_8(IO_BASE + 0x12d) /* A/D1 interrupt enable */\r
+#define PORTAD1 PORTIO_8(IO_BASE + 0x12f) /* port AD1 data input register */\r
+#define ATD1DR0 PORTIO_16(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR0H PORTIO_8(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR1 PORTIO_16(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR1H PORTIO_8(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR2 PORTIO_16(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR2H PORTIO_8(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR3 PORTIO_16(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR3H PORTIO_8(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR4 PORTIO_16(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR4H PORTIO_8(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR5 PORTIO_16(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR5H PORTIO_8(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR6 PORTIO_16(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR6H PORTIO_8(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR7 PORTIO_16(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+#define ATD1DR7H PORTIO_8(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+\r
+// CAN0 Module \r
+#define CAN0_BASE (IO_BASE + 0x140)\r
+#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
+#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
+#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
+#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
+#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
+#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
+#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
+#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
+#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
+#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
+#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
+#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
+#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
+#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
+#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
+#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
+#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
+#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
+#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
+#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
+#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
+#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
+#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
+#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
+#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
+#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
+#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
+#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
+#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
+#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
+#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
+#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
+\r
+// CAN1 Module \r
+#define CAN1_BASE (IO_BASE + 0x180)\r
+#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
+#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
+#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
+#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
+#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
+#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
+#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
+#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
+#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
+#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
+#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
+#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
+#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
+#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
+#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
+#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
+#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
+#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
+#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
+#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
+#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
+#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
+#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
+#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
+#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
+#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
+#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
+#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
+#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
+#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
+#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
+#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
+\r
+// CAN2 Module \r
+#define CAN2_BASE (IO_BASE + 0x1c0)\r
+#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
+#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
+#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
+#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
+#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
+#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
+#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
+#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
+#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
+#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
+#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
+#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
+#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
+#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
+#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
+#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
+#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
+#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
+#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
+#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
+#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
+#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
+#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
+#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
+#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
+#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
+#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
+#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
+#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
+#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
+#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
+#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
+\r
+// CAN3 Module \r
+#define CAN3_BASE (IO_BASE + 0x200)\r
+#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
+#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
+#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
+#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
+#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
+#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
+#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
+#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
+#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
+#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
+#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
+#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
+#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
+#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
+#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
+#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
+#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
+#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
+#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
+#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
+#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
+#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
+#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
+#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
+#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
+#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
+#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
+#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
+#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
+#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
+#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
+#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
+\r
+\r
+// Port T register offsets\r
+#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
+#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
+#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
+#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
+#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
+#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
+\r
+// Port S\r
+#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
+#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
+#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
+#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
+#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
+#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
+#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
+\r
+// Port M\r
+#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
+#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
+#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
+#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
+#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
+#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
+#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
+\r
+// Port P\r
+#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
+#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
+#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
+#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
+#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
+#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
+#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
+#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
+\r
+// Port H\r
+#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
+#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
+#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
+#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
+#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
+#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
+#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
+#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
+\r
+// Port J\r
+#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
+#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
+#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
+#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
+#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
+#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
+#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
+#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
+\r
+\r
+\r
+// CAN4 Module \r
+#define CAN4_BASE (IO_BASE + 0x280)\r
+#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
+#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
+#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
+#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
+#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
+#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
+#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
+#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
+#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
+#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
+#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
+#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
+#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
+#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
+#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
+#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
+#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
+#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
+#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
+#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
+#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
+#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
+#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
+#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
+#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
+#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
+#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
+#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
+#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
+#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
+#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
+#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
+\r
+\r
+\r
+# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
+# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
+# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
+# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
+# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
+# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+\r
+#endif /* ifndef _REGS_H_ */\r
*/
void Irq_EOI( void );
+#if defined(CFG_HC1X)
+/**
+ *
+ * @param stack Ptr to the current stack.
+ * @param irq_nr The nr. of the interrupt being handled.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+void *Irq_Entry( uint8_t irq_nr, void *stack );
+#else
/**
*
* @param stack_p Ptr to the current stack.
*
*/
void *Irq_Entry( void *stack_p );
-
+#endif
/**
* Attach an ISR type 1 to the interrupt controller.
*
\r
%.s: %.sx\r
@echo " >> CPP $(notdir $<)"\r
- $(Q)$(CPP) -x assembler-with-cpp -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+ $(Q)$(CPP) -x assembler-with-cpp -E -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+ cp $@ $(ROOTDIR)/\r
\r
\r
# @cat $@ \r
#if defined(USE_PWM)\r
.PwmConfig = &PwmConfig,\r
#endif\r
+#if defined(USE_GPT)
+ .GptConfig = GptConfigData,
+#endif
};\r
\r
void EcuM_OnGoOffTwo( void ) {\r
#if defined(USE_ADC)\r
#include "Adc.h"\r
#endif\r
+#if defined(USE_GPT)
+#include "Gpt.h"
+#endif
\r
typedef struct\r
{\r
#endif\r
#if defined(USE_ADC)\r
const Adc_ConfigType* AdcConfig;\r
+#endif
+#if defined(USE_GPT)
+ const Gpt_ConfigType* GptConfig;
#endif\r
} EcuM_ConfigType;\r
\r
#obj-y += asm_sample.o\r
#CFLAGS_asm_sample.o += -O3\r
obj-y += arch_krn.o\r
+obj-$(CFG_HCS12D) += arch_irq.o\r
#obj-y += stm32f10x_it.o\r
\r
# object files \r
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