#include <stdint.h>
#include "Std_Types.h"\r
#include "Mcu.h"\r
-//#include "Det.h" // TODO Mattias restore\r
-//#include <assert.h> // TODO Mattias restore\r
+#include "Det.h"\r
+#include <assert.h>\r
#include "Cpu.h"\r
-#include <string.h>
-//#include "hcs12.h"\r
-//#include "Ramlog.h" // TODO Mattias restore\r
+#include <string.h>\r
+#include "Ramlog.h"\r
\r
-//#define USE_TRACE 1\r
-//#define USE_DEBUG 1\r
-//#include "Trace.h" // TODO Mattias restore
+#define USE_TRACE 1\r
+#define USE_DEBUG 1\r
+#include "Trace.h"
-#define PORTIO_8 *(volatile unsigned char *)
-#define IO_BASE 0
-#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */
-#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */
-#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */
-#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */
-#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */
-
+#define PORTIO_8 *(volatile unsigned char *)
+#define IO_BASE 0
+#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */
+#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */
+#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */
+#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */
+#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */
+#define S12_REFCLK 8000000 // PLL internal reference clock
+/*
#define BM_RTIF 0x80
#define BM_PORF 0x40
//#define reserved 0x20
#define BM_SCME 0x01
-#define S12_REFCLK 8000000 // PLL internal reference clock
+
+*/
\r
\r
typedef struct {\r
void Mcu_Init(const Mcu_ConfigType *configPtr)\r
{\r
VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
-
-/*\r
- if( !SIMULATOR() ) {\r
- Mcu_CheckCpu();\r
- }\r
-*/
\r
memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
Mcu_Global.clockSetting = ClockSetting;\r
clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
-/*
-#define S12_OSCCLK 16000000 // input frequency from Xtal/Osc
-#define S12_PLLCLK 48000000 // desired output frequency of PLL
-*/
-// PLL clock generation formula, according to CRG Block User Guide:
-// PLLCLK = OSCCLK * 2(SYNR+1) / (REFDV+1)
-
-//#define S12_ECLK (S12_PLLCLK/2) // final bus clock frequency (ECLK)
-//#define S12_ECLK (S12_OSCCLK/2) // bus clock if PLL not in use / off
-
- uint8 s12_refdv = (uint8)(clockSettingsPtr->McuClockReferencePointFrequency / S12_REFCLK) - 1;
- uint8 s12_synr = (uint8)(clockSettingsPtr->PllClock / (2 * S12_REFCLK) ) -1;\r
-
- //PLLCLK = 2 * OSCCLK * (SYNR + 1) / (REFDV + 1)
-
CLKSEL &= ~BM_PLLSEL; // Turn off PLL
PLLCTL |= BM_PLLON+BM_AUTO; // Enable PLL module, Auto Mode
- REFDV = s12_refdv; // Set reference divider
- SYNR = s12_synr; // Set synthesizer multiplier
-
- // the following dummy write has no effect except consuming some cycles,
- // this is a workaround for erratum MUCTS00174 (mask set 0K36N only)
- // CRGFLG = 0;
+ REFDV = clockSettingsPtr->Pll1; // Set reference divider
+ SYNR = clockSettingsPtr->Pll2; // Set synthesizer multiplier
while (Mcu_GetPllStatus() != MCU_PLL_LOCKED) ;
CLKSEL |= BM_PLLSEL; // Switch to PLL clock
*/
#ifndef MCU_H_\r
-#define MCU_H_\r
+#define MCU_H_
+
+#define MCU_SW_MAJOR_VERSION 2
+#define MCU_SW_MINOR_VERSION 0
+#define MCU_SW_PATCH_VERSION 0
+
+#define MCU_AR_MAJOR_VERSION 2
+#define MCU_AR_MINOR_VERSION 2
+#define MCU_AR_PATCH_VERSION 2\r
\r
#include "Cpu.h"\r
#include "irq_types.h"
void Mcu_SetMode( const Mcu_ModeType McuMode );\r
\r
#if ( MCU_VERSION_INFO_API == STD_ON )\r
-#define MCU_SW_MAJOR_VERSION 2\r
-#define MCU_SW_MINOR_VERSION 0\r
-#define MCU_SW_PATCH_VERSION 0\r
-#define MCU_AR_MAJOR_VERSION 2\r
-#define MCU_AR_MINOR_VERSION 2\r
-#define MCU_AR_PATCH_VERSION 2\r
-\r
#define Mcu_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,MCU)\r
#endif\r
\r