CAN_InitStructure.CAN_NART=DISABLE;
CAN_InitStructure.CAN_RFLM=DISABLE;
CAN_InitStructure.CAN_TXFP=DISABLE;
- CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;//CAN_Mode_LoopBack;
+ if(config->Can_Arc_Loopback){
+ CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
+ }else{
+ CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;
+ }
CAN_InitStructure.CAN_SJW=config->CanControllerPropSeg;
CAN_InitStructure.CAN_BS1=config->CanControllerSeg1;
cleanup: return;\r
}\r
\r
-#if (DIO_VERSION_INFO_API == STD_ON)\r
-void Dio_GetVersionInfo(Std_VersionInfoType *versionInfo)\r
-{\r
- memcpy(versionInfo, &_Dio_VersionInfo, sizeof(Std_VersionInfoType));\r
-}\r
-#endif\r
-\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#include "Std_Types.h"\r
+//#include "Det.h"\r
+#include "Gpt.h"\r
+#include <string.h>\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#include "irq.h"\r
+#include "arc.h"\r
+#endif\r
+#include "stm32f10x.h"\r
+\r
+\r
+\r
+//TIM2->DIER =\r
+\r
+\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Gpt.h"\r
+#include "Cpu.h"\r
+#include <assert.h>\r
+#include <string.h>\r
+#include "Mcu.h"\r
+#include "Det.h"\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#include "irq.h"\r
+#endif\r
+\r
+// Implementation specific\r
+/* STM32 helper arrays\r
+ *
+ */\r
+TIM_TypeDef * const TimAddr[] =\r
+{\r
+ ((TIM_TypeDef *)TIM1_BASE),\r
+ ((TIM_TypeDef *)TIM2_BASE),\r
+ ((TIM_TypeDef *)TIM3_BASE),\r
+ ((TIM_TypeDef *)TIM4_BASE),\r
+ ((TIM_TypeDef *)TIM5_BASE),\r
+ ((TIM_TypeDef *)TIM6_BASE),\r
+ ((TIM_TypeDef *)TIM7_BASE),\r
+};\r
+\r
+#if ( GPT_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+\r
+#define VALID_CHANNEL(_ch) ( Gpt_Global.configured & (1<<(_ch)) )\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+const uint32 IrqVector[] =\r
+{\r
+ TIM1_UP_IRQn,\r
+ TIM2_IRQn,\r
+ TIM3_IRQn,\r
+ TIM4_IRQn,\r
+};\r
+\r
+typedef enum\r
+{\r
+ GPT_STATE_STOPPED = 0,\r
+ GPT_STATE_STARTED,\r
+} Gpt_StateType;\r
+\r
+/**\r
+ * Type that holds all global data for Gpt\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Gpt_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Gpt_ConfigType *config;\r
+\r
+ uint8 wakeupEnabled;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[GPT_CHANNEL_CNT];\r
+\r
+} Gpt_GlobalType;\r
+\r
+/**\r
+ * Type that holds data that are specific for a channel\r
+ */\r
+typedef struct\r
+{\r
+ Gpt_StateType state;\r
+} Gpt_UnitType;\r
+\r
+Gpt_UnitType Gpt_Unit[GPT_CHANNEL_CNT];\r
+\r
+// Global config\r
+Gpt_GlobalType Gpt_Global;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * ISR helper-function that handles the HW channels( 0 to 8 )\r
+ *\r
+ * @param channel - Channel that the raised the interrupt\r
+ */\r
+static void Gpt_IsrCh(Gpt_ChannelType channel)\r
+{\r
+ const Gpt_ConfigType *config;\r
+ int confCh;\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+ assert(confCh != GPT_CHANNEL_ILL);\r
+\r
+ config = &Gpt_Global.config[confCh];\r
+\r
+ if (config->GptChannelMode == GPT_MODE_ONESHOT)\r
+ {\r
+ // Disable the channel\r
+ TimAddr[channel]->CR1 &= ~TIM_CR1_CEN;\r
+\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+ }\r
+ config->GptNotification();\r
+\r
+ // Clear interrupt\r
+ TimAddr[channel]->SR &= ~TIM_SR_UIF;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+// Macro that counts leading zeroes.\r
+#define CNTLZW_INV(x) (31-cntlzw(x))\r
+\r
+/**\r
+ * ISR that handles all interrupts\r
+ */\r
+static void Gpt_Isr(void)\r
+{\r
+ static int i;\r
+ int found = 0;\r
+ /* Find channel for this interrupt. */\r
+ for (i = 0; ((i < GPT_CHANNEL_CNT) && !found);i++)\r
+ {\r
+ found = (((TimAddr[i]->SR & TIM_SR_UIF) == TIM_SR_UIF) &&\r
+ ((TimAddr[i]->CR1 & TIM_CR1_CEN) == TIM_CR1_CEN));\r
+ }\r
+ if (found)\r
+ {\r
+ Gpt_IsrCh(i - 1);\r
+ }\r
+}\r
+//-------------------------------------------------------------------\r
+\r
+void Gpt_Init(const Gpt_ConfigType *config)\r
+{\r
+ uint32_t i=0;\r
+ const Gpt_ConfigType *cfg;\r
+ VALIDATE( (Gpt_Global.initRun == STD_OFF), GPT_INIT_SERVICE_ID, GPT_E_ALREADY_INITIALIZED );\r
+#if defined(GPT_VARIANT_PB)\r
+ VALIDATE( (config != NULL ), GPT_INIT_SERVICE_ID, GPT_E_PARAM_CONFIG );\r
+#elif defined(GPT_VARIANT_PC)\r
+ // We don't support GPT_VARIANT_PC\r
+ assert(0);\r
+#endif\r
+ Gpt_ChannelType ch;\r
+\r
+ for (i=0; i<GPT_CHANNEL_CNT; i++)\r
+ {\r
+ Gpt_Global.channelMap[i] = GPT_CHANNEL_ILL;\r
+ }\r
+\r
+ i = 0;\r
+ cfg = config;\r
+ while (cfg->GptChannelId != GPT_CHANNEL_ILL)\r
+ {\r
+ ch = cfg->GptChannelId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Gpt_Global.channelMap[cfg->GptChannelId] = i;\r
+ Gpt_Global.configured |= (1<<ch);\r
+\r
+ if (ch <= GPT_CHANNEL_CNT)\r
+ {\r
+ if (cfg->GptNotification != NULL)\r
+ {\r
+\r
+#if defined(USE_KERNEL)\r
+ TaskType tid;\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr, 6, "Gpt_Isr");\r
+ Irq_AttachIsr2(tid, NULL, IrqVector[ch]);\r
+#else\r
+ //IntCtrl_InstallVector(Gpt_Isr, PIT_PITFLG_RTIF + ch, 1, CPU_Z1); TODO\r
+#endif\r
+ }\r
+ }\r
+#if defined(USE_KERNEL)\r
+ // Don't install if we use kernel.. it handles that.\r
+#else\r
+\r
+#endif\r
+\r
+ cfg++;\r
+ i++;\r
+ }\r
+\r
+ Gpt_Global.config = config;\r
+\r
+ Gpt_Global.initRun = STD_ON;\r
+ //PIT.CTRL.B.MDIS = 0;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if GPT_DEINIT_API == STD_ON\r
+void Gpt_DeInit(void)\r
+{\r
+ Gpt_ChannelType channel;\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DEINIT_SERVICE_ID, GPT_E_UNINIT );\r
+ for (channel=0; channel<GPT_CHANNEL_CNT; channel++) // Validate that all channels have been stopped\r
+ {\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_DEINIT_SERVICE_ID, GPT_E_BUSY );\r
+ Gpt_StopTimer(channel); // Should this be done here?\r
+ }\r
+ Gpt_Global.initRun = STD_OFF;\r
+ Gpt_Global.configured = 0;\r
+ //_config.config = NULL;\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+// period is in "ticks" !!\r
+void Gpt_StartTimer(Gpt_ChannelType channel, Gpt_ValueType period_ticks)\r
+{\r
+ int confCh;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STARTTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STARTTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_STARTTIMER_SERVICE_ID, GPT_E_BUSY );\r
+ // GPT_E_PARAM_VALUE, all have 32-bit so no need to check\r
+\r
+ //DEBUG(DEBUG_HIGH, "Gpt_StartTimer ch=%d, period=%d [ticks]\n", channel, period_ticks);\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ uint32 *tlval = (uint32 *)&(TimAddr[channel]->ARR);\r
+ uint32 *tval = (uint32 *)&(TimAddr[channel]->CNT);\r
+\r
+ *tlval = period_ticks;\r
+ *tval = period_ticks;\r
+\r
+ // always select interrupt\r
+ //TimAddr[channel]->DIER |= TIM_DIER_UIE;\r
+\r
+ // Make sure that no interrupt is pending.\r
+ TimAddr[channel]->SR &= ~TIM_SR_UIF;\r
+\r
+ // Set prescaler.\r
+ TimAddr[channel]->PSC = Gpt_Global.config[confCh].GptChannelPrescale;\r
+\r
+ // Enable timer\r
+ TimAddr[channel]->CR1 |= (TIM_CR1_CEN | TIM_CR1_URS | TIM_CR1_DIR);\r
+ TimAddr[channel]->CR1 &= ~TIM_CR1_UDIS;\r
+ }\r
+\r
+ if( Gpt_Global.config[confCh].GptNotification != NULL )\r
+ {\r
+ // GPT275\r
+ Gpt_EnableNotification(channel);\r
+ }\r
+\r
+ Gpt_Unit[channel].state = GPT_STATE_STARTED;\r
+}\r
+\r
+void Gpt_StopTimer(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STOPTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STOPTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ // Disable timer\r
+ TimAddr[channel]->CR1 &= ~TIM_CR1_CEN;\r
+ }\r
+\r
+ Gpt_DisableNotification(channel);\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+}\r
+\r
+#if ( GPT_TIME_REMAINING_API == STD_ON )\r
+\r
+Gpt_ValueType Gpt_GetTimeRemaining(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_UNINIT, 0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+ Gpt_ValueType remaining;\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ uint32 *tval = (uint32 *)&(TimAddr[channel]->CNT);\r
+ // Time remaining is the time until it hits 0, so just return the current timer value\r
+ remaining = *tval;\r
+ }\r
+\r
+ return remaining;\r
+}\r
+#endif\r
+\r
+#if ( GPT_TIME_ELAPSED_API == STD_ON )\r
+Gpt_ValueType Gpt_GetTimeElapsed(Gpt_ChannelType channel)\r
+{\r
+ Gpt_ValueType timer;\r
+\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_UNINIT ,0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+\r
+ // NOTE!\r
+ // These little creatures count down\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ uint32 *tlval = (uint32 *)&(TimAddr[channel]->ARR);\r
+ uint32 *tval = (uint32 *)&(TimAddr[channel]->CNT);\r
+ timer = *tlval - *tval;\r
+ }\r
+\r
+ return (timer);\r
+}\r
+#endif\r
+\r
+#if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
+void Gpt_EnableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x7, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x7, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ // enable interrupts\r
+ TimAddr[channel]->DIER |= TIM_DIER_UIE;\r
+ }\r
+}\r
+\r
+void Gpt_DisableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x8, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x8, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ TimAddr[channel]->DIER &= ~TIM_DIER_UIE;\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+#endif\r
+\r
+#if ( GPT_WAKEUP_FUNCTIONALITY_API == STD_ON )\r
+\r
+void Gpt_SetMode(Gpt_ModeType mode)\r
+{\r
+ int i;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_SETMODE_SERVIVCE_ID, GPT_E_UNINIT );\r
+ VALIDATE( ( mode <= GPT_MODE_SLEEP ), GPT_SETMODE_SERVIVCE_ID, GPT_E_PARAM_MODE );\r
+\r
+ if (mode == GPT_MODE_NORMAL)\r
+ {\r
+ //PIT.CTRL.B.MDIS = 0; TODO\r
+ // Do NOT restart channels\r
+ }\r
+ else if (mode == GPT_MODE_SLEEP)\r
+ {\r
+\r
+ //PIT.CTRL.B.MDIS = 1; TODO\r
+ // Disable all\r
+ for (i= 0; i <= GPT_CHANNEL_CNT; i++)\r
+ {\r
+ Gpt_StopTimer(i);\r
+ }\r
+ }\r
+}\r
+\r
+void Gpt_DisableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ // Only RTI have system wakeup\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_OFF;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_EnableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_ON;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_Cbk_CheckWakeup(EcuM_WakeupSourceType wakeupSource)\r
+{\r
+\r
+}\r
+\r
+#endif\r
+\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
-#include "Std_Types.h"\r
+\r
#include "Port.h" /** @req PORT131 */\r
+#include "stm32f10x.h"\r
#include "Det.h"\r
#include "string.h"\r
-#include "stm32f10x_rcc.h"\r
+#include "stm32f10x_gpio.h"\r
+\r
+const uint32 *GpioBaseAddr[] =\r
+{\r
+ (uint32 *)GPIOA_BASE,\r
+ (uint32 *)GPIOB_BASE,\r
+ (uint32 *)GPIOC_BASE,\r
+ (uint32 *)GPIOD_BASE,\r
+ (uint32 *)GPIOE_BASE,\r
+ (uint32 *)GPIOF_BASE,\r
+ (uint32 *)GPIOG_BASE\r
+};\r
+\r
+const uint32 *GpioODRAddr[] =\r
+{\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOA_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOB_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOC_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOD_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOE_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOF_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOG_BASE)->ODR\r
+};\r
\r
typedef enum\r
{\r
/** @req PORT121 */\r
void Port_Init(const Port_ConfigType *configType)\r
{\r
- VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID); /** @req PORT105 */\r
-\r
- uint16_t portIndex,pinIndex;\r
-\r
- // Set up all the ports\r
- for (portIndex = 0; portIndex < configType->portCount; portIndex++) {\r
- const Port_PortConfigType* portConfig = configType->ports[portIndex];\r
-\r
- // set up all pins\r
- for (pinIndex = 0; pinIndex < portConfig->pinCount; pinIndex++) {\r
-\r
- GPIO_Init(portConfig->port, &portConfig->pins[pinIndex]);\r
-\r
- }\r
- }\r
+ VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID); /** @req PORT105 */\r
+ volatile const uint32 *gpioAddr;\r
+\r
+ for (uint8_t i = 0; i < configType->padCnt; i++)\r
+ {\r
+ /* Configure pin. */\r
+ gpioAddr = GpioBaseAddr[i];\r
+ //*((GpioPinCnfMode_Type *)gpioAddr) = configType->padConfig[i];\r
+ *(uint32 *)gpioAddr = *(uint32 *)&configType->padConfig[i];\r
+ *(1+(uint32 *)gpioAddr) = *(1+(uint32 *)&configType->padConfig[i]);\r
+\r
+ /* Set default output level. */\r
+ gpioAddr = GpioODRAddr[i];\r
+ *((GpioPinOutLevel_Type *)gpioAddr) = configType->outConfig[i];\r
+ }\r
\r
// Enable remaps\r
- for (portIndex = 0; portIndex < configType->remapCount; portIndex++) {\r
+ for (int portIndex = 0; portIndex < configType->remapCount; portIndex++) {\r
GPIO_PinRemapConfig(configType->remaps[portIndex], ENABLE);\r
}\r
\r
_portState = PORT_INITIALIZED;\r
- _configPtr = configType;\r
+ _configPtr = (Port_ConfigType *)configType;\r
cleanup: return;\r
}\r
\r
#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )\r
void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
{\r
- VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
-\r
- {\r
- Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_DIRECTION_ID, PORT_E_PARAM_PIN );\r
- }\r
-\r
- cleanup:return;\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
+\r
+ uint32 * gpioAddr;\r
+ static uint8 index, bit, reg;\r
+\r
+ index = pin / 16;\r
+ bit = pin % 16;\r
+ reg = bit / 8;\r
+ bit = (bit % 8) * 4;\r
+ // Ex. DIO_CHANNEL_B8 = 24\r
+ // index = 1 => GPIOB\r
+ // bit = 8\r
+ // reg = 1 => CRH\r
+ // bit = 0 => MODE8, CNF8 => OK\r
+ // 0 1 2\r
+ // 0 4 8\r
+ gpioAddr = (uint32 *)GpioBaseAddr[index];\r
+\r
+ /* Adjust for CRL/CRH */\r
+ gpioAddr += reg;\r
+\r
+ *gpioAddr &= ~(0x000000F << bit);\r
+\r
+ if (direction==PORT_PIN_IN)\r
+ {\r
+ /* Configure pin. */\r
+ //*gpioAddr |= (GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF) << bit; // TODO shall this be added to conf?\r
+ *gpioAddr |= (GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF) << bit; // TODO shall this be added to conf?\r
+ }\r
+ else\r
+ {\r
+ *gpioAddr |= (GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF) << bit; // TODO shall this be added to conf?\r
+ }\r
+\r
+ cleanup:return;\r
}\r
#endif\r
\r
/** @req PORT061 */\r
void Port_RefreshPortDirection(void)\r
{\r
- uint8_t curValue;\r
VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);\r
\r
+ /* TODO Not implemented yet */\r
cleanup: return;\r
}\r
\r
cleanup: return;\r
}\r
#endif\r
-\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r
+<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>\r
+\r
+\r
+\r
+\r
+<meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1">\r
+<link rel="File-List" href="Library_files/filelist.xml">\r
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+<tbody>\r
+ <tr>\r
+ <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>\r
+ </tr>\r
+<tr style="">\r
+<td style="padding: 1.5pt;">\r
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
+Notes for STM32F10x Standard Peripherals Library Drivers\r
+(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2010 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+<tbody>\r
+<tr>\r
+<td style="padding: 0cm;" valign="top">\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+<ol style="margin-top: 0cm;" start="1" type="1">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library\r
+Drivers update History</a><o:p></o:p></span></li>\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
+</ol>\r
+<span style="font-family: "Times New Roman";">\r
+</span>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard\r
+Peripherals Library Drivers update History</span></h2>\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0\r
+- 10/15/2010</span></h3>\r
+\r
+ <ol style="margin-top: 0in;" start="1" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>\r
+ </ol>\r
+\r
+ <ul style="margin-top: 0in;" type="disc">\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density value line </span>devices.</span></li>\r
+ </ul>\r
+\r
+ <ol style="margin-top: 0in;" start="2" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>\r
+ </ol>\r
+\r
+ \r
+ <ul style="margin-top: 0in;" type="disc">\r
+\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file. </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.<br>\r
+</span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Update the wording of some defines and Asserts macro. <br>\r
+ </span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetFlagStatus()\r
+and CAN_ClearFlag() functions: updated to support new flags (were not\r
+supported in previous version). These flags are: CAN_FLAG_RQCP0,\r
+CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,\r
+CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0, CAN_FLAG_FOV0,\r
+CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC. <br>\r
+ </span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetITStatus()\r
+function: add a check of the interrupt enable bit before getting the\r
+status of corresponding interrupt pending bit. <br>\r
+ </span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit. <br>\r
+ </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_crc.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dac.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file. </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file. </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.</span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"<br>\r
+ </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.</span><span style="font-style: italic;"></span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.</span><span style="font-style: italic;"></span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_pwr.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c</span></li>\r
+<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".</span></span></li></ul>\r
+ \r
+ </ul>\r
+\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0\r
+- 04/16/2010</span></h3>\r
+\r
+<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>\r
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>\r
+<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>\r
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:\r
+updated to support Bank2 of XL-density devices (up to 1MByte of Flash\r
+memory). For more details, refer to the description provided within\r
+stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>\r
+function: updated to check whether the last event contains the\r
+I2C_EVENT (instead of check whether the last event is equal to\r
+I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add\r
+detailed description of I2C events and how to manage them using the\r
+functions provided by this driver. For more information, refer to\r
+stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h: </span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br> \r
+#define\r
+SDIO_ReadWaitMode_CLK \r
+ ((uint32_t)0x00000000)<br> #define\r
+SDIO_ReadWaitMode_DATA2 \r
+((uint32_t)0x00000001)<br>by<br> #define\r
+SDIO_ReadWaitMode_CLK \r
+ ((uint32_t)0x00000001)<br> #define\r
+SDIO_ReadWaitMode_DATA2 \r
+((uint32_t)0x00000000)</span></li></ul></ul>\r
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0\r
+- 03/01/2010</span></h3>\r
+<ol style="margin-top: 0in;" start="1" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>\r
+</ol>\r
+<ul style="margin-top: 0in;" type="disc">\r
+\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support\r
+for <b>STM32 Low-density Value line (STM32F100x4/6) and\r
+Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost\r
+peripherals drivers were updated to support Value\r
+line devices features</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>\r
+\r
+</ul>\r
+<ol style="margin-top: 0in;" start="2" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>\r
+</ol>\r
+<ul style="margin-top: 0in;" type="disc">\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new\r
+firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART\r
+driver: add support for Oversampling by 8 mode and onebit method. 2\r
+functions has been added: USART_OverSampling8Cmd() and\r
+USART_OneBitMethodCmd().<br>\r
+ </span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC\r
+driver: add new functions handling the DAC under run feature:\r
+DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()\r
+and DAC_ClearITPendingBit().</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>\r
+ </span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH\r
+driver: the FLASH_EraseOptionBytes() function updated. This is now just\r
+erasing the option bytes without modifying the RDP status either\r
+enabled or disabled.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR\r
+driver: the PWR_EnterSTOPMode() function updated. When woken up from\r
+STOP mode, this function resets again the SLEEPDEEP bit in the\r
+Cortex-M3 System Control register to allow Sleep mode entering.</span></li>\r
+ \r
+\r
+</ul>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The\r
+enclosed firmware and all the related documentation are not covered by\r
+a License Agreement, if you need such License you can contact your\r
+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE\r
+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO\r
+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR\r
+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY\r
+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY\r
+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH\r
+THEIR PRODUCTS. <o:p></o:p></span></b></p>\r
+<p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>\r
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+<hr align="center" size="2" width="100%"></span></div>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers\r
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+</div>\r
+<p class="MsoNormal"><o:p> </o:p></p>\r
+</div>\r
+</body></html>
\ No newline at end of file
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the miscellaneous\r
+ * firmware library functions (add-on to CMSIS functions).\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __MISC_H\r
+#define __MISC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup MISC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief NVIC Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
+ This parameter can be a value of @ref IRQn_Type \r
+ (For the complete STM32 Devices IRQ Channels list, please\r
+ refer to stm32f10x.h file) */\r
+\r
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
+ specified in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
+ in NVIC_IRQChannel. This parameter can be a value\r
+ between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
+\r
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
+ will be enabled or disabled. \r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+} NVIC_InitTypeDef;\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup NVIC_Priority_Table \r
+ * @{\r
+ */\r
+\r
+/**\r
+@code \r
+ The table below gives the allowed values of the pre-emption priority and subpriority according\r
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
+ ============================================================================================================================\r
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
+ | | | 4 bits for subpriority\r
+ ----------------------------------------------------------------------------------------------------------------------------\r
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
+ | | | 3 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
+ | | | 2 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
+ | | | 1 bits for subpriority\r
+ ---------------------------------------------------------------------------------------------------------------------------- \r
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
+ | | | 0 bits for subpriority \r
+ ============================================================================================================================\r
+@endcode\r
+*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Vector_Table_Base \r
+ * @{\r
+ */\r
+\r
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
+ ((VECTTAB) == NVIC_VectTab_FLASH))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup System_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
+ ((LP) == NVIC_LP_SLEEPDEEP) || \\r
+ ((LP) == NVIC_LP_SLEEPONEXIT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Preemption_Priority_Group \r
+ * @{\r
+ */\r
+\r
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
+ 4 bits for subpriority */\r
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
+ 3 bits for subpriority */\r
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
+ 2 bits for subpriority */\r
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
+ 1 bits for subpriority */\r
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
+ 0 bits for subpriority */\r
+\r
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
+ ((GROUP) == NVIC_PriorityGroup_1) || \\r
+ ((GROUP) == NVIC_PriorityGroup_2) || \\r
+ ((GROUP) == NVIC_PriorityGroup_3) || \\r
+ ((GROUP) == NVIC_PriorityGroup_4))\r
+\r
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
+\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SysTick_clock_source \r
+ * @{\r
+ */\r
+\r
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __MISC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_adc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_ADC_H\r
+#define __STM32F10x_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or\r
+ dual mode. \r
+ This parameter can be a value of @ref ADC_mode */\r
+\r
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
+ Scan (multichannels) or Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+\r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
+ Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
+ to digital conversion of regular channels. This parameter\r
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
+\r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
+ This parameter can be a value of @ref ADC_data_align */\r
+\r
+ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted\r
+ using the sequencer for regular channel group.\r
+ This parameter must range from 1 to 16. */\r
+}ADC_InitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
+ ((PERIPH) == ADC2) || \\r
+ ((PERIPH) == ADC3))\r
+\r
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
+ ((PERIPH) == ADC3))\r
+\r
+/** @defgroup ADC_mode \r
+ * @{\r
+ */\r
+\r
+#define ADC_Mode_Independent ((uint32_t)0x00000000)\r
+#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)\r
+#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)\r
+#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)\r
+#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)\r
+#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)\r
+#define ADC_Mode_RegSimult ((uint32_t)0x00060000)\r
+#define ADC_Mode_FastInterl ((uint32_t)0x00070000)\r
+#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)\r
+#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)\r
+\r
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \\r
+ ((MODE) == ADC_Mode_RegInjecSimult) || \\r
+ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \\r
+ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \\r
+ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \\r
+ ((MODE) == ADC_Mode_InjecSimult) || \\r
+ ((MODE) == ADC_Mode_RegSimult) || \\r
+ ((MODE) == ADC_Mode_FastInterl) || \\r
+ ((MODE) == ADC_Mode_SlowInterl) || \\r
+ ((MODE) == ADC_Mode_AlterTrig))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion \r
+ * @{\r
+ */\r
+\r
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */\r
+\r
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */\r
+\r
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */\r
+\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_None) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */\r
+\r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */\r
+\r
+#define ADC_Channel_0 ((uint8_t)0x00)\r
+#define ADC_Channel_1 ((uint8_t)0x01)\r
+#define ADC_Channel_2 ((uint8_t)0x02)\r
+#define ADC_Channel_3 ((uint8_t)0x03)\r
+#define ADC_Channel_4 ((uint8_t)0x04)\r
+#define ADC_Channel_5 ((uint8_t)0x05)\r
+#define ADC_Channel_6 ((uint8_t)0x06)\r
+#define ADC_Channel_7 ((uint8_t)0x07)\r
+#define ADC_Channel_8 ((uint8_t)0x08)\r
+#define ADC_Channel_9 ((uint8_t)0x09)\r
+#define ADC_Channel_10 ((uint8_t)0x0A)\r
+#define ADC_Channel_11 ((uint8_t)0x0B)\r
+#define ADC_Channel_12 ((uint8_t)0x0C)\r
+#define ADC_Channel_13 ((uint8_t)0x0D)\r
+#define ADC_Channel_14 ((uint8_t)0x0E)\r
+#define ADC_Channel_15 ((uint8_t)0x0F)\r
+#define ADC_Channel_16 ((uint8_t)0x10)\r
+#define ADC_Channel_17 ((uint8_t)0x11)\r
+\r
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_sampling_time \r
+ * @{\r
+ */\r
+\r
+#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)\r
+#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)\r
+#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)\r
+#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)\r
+#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)\r
+#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)\r
+#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)\r
+#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_7Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_13Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_28Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_41Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_55Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_71Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_239Cycles5))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
+ * @{\r
+ */\r
+\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */\r
+\r
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */\r
+\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_channel_selection \r
+ * @{\r
+ */\r
+\r
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)\r
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)\r
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)\r
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */\r
+\r
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)\r
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define ADC_IT_EOC ((uint16_t)0x0220)\r
+#define ADC_IT_AWD ((uint16_t)0x0140)\r
+#define ADC_IT_JEOC ((uint16_t)0x0480)\r
+\r
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \\r
+ ((IT) == ADC_IT_JEOC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define ADC_FLAG_AWD ((uint8_t)0x01)\r
+#define ADC_FLAG_EOC ((uint8_t)0x02)\r
+#define ADC_FLAG_JEOC ((uint8_t)0x04)\r
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)\r
+#define ADC_FLAG_STRT ((uint8_t)0x10)\r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_offset \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_length \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_rank \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_regular_length \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_regular_rank \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_regular_discontinuous_mode_number \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void ADC_DeInit(ADC_TypeDef* ADCx);\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_StartCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+uint32_t ADC_GetDualModeConversionValue(void);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_bkp.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the BKP firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_BKP_H\r
+#define __STM32F10x_BKP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup BKP\r
+ * @{\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Tamper_Pin_active_level \r
+ * @{\r
+ */\r
+\r
+#define BKP_TamperPinLevel_High ((uint16_t)0x0000)\r
+#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)\r
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \\r
+ ((LEVEL) == BKP_TamperPinLevel_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin \r
+ * @{\r
+ */\r
+\r
+#define BKP_RTCOutputSource_None ((uint16_t)0x0000)\r
+#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)\r
+#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)\r
+#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)\r
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_Second))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Data_Backup_Register \r
+ * @{\r
+ */\r
+\r
+#define BKP_DR1 ((uint16_t)0x0004)\r
+#define BKP_DR2 ((uint16_t)0x0008)\r
+#define BKP_DR3 ((uint16_t)0x000C)\r
+#define BKP_DR4 ((uint16_t)0x0010)\r
+#define BKP_DR5 ((uint16_t)0x0014)\r
+#define BKP_DR6 ((uint16_t)0x0018)\r
+#define BKP_DR7 ((uint16_t)0x001C)\r
+#define BKP_DR8 ((uint16_t)0x0020)\r
+#define BKP_DR9 ((uint16_t)0x0024)\r
+#define BKP_DR10 ((uint16_t)0x0028)\r
+#define BKP_DR11 ((uint16_t)0x0040)\r
+#define BKP_DR12 ((uint16_t)0x0044)\r
+#define BKP_DR13 ((uint16_t)0x0048)\r
+#define BKP_DR14 ((uint16_t)0x004C)\r
+#define BKP_DR15 ((uint16_t)0x0050)\r
+#define BKP_DR16 ((uint16_t)0x0054)\r
+#define BKP_DR17 ((uint16_t)0x0058)\r
+#define BKP_DR18 ((uint16_t)0x005C)\r
+#define BKP_DR19 ((uint16_t)0x0060)\r
+#define BKP_DR20 ((uint16_t)0x0064)\r
+#define BKP_DR21 ((uint16_t)0x0068)\r
+#define BKP_DR22 ((uint16_t)0x006C)\r
+#define BKP_DR23 ((uint16_t)0x0070)\r
+#define BKP_DR24 ((uint16_t)0x0074)\r
+#define BKP_DR25 ((uint16_t)0x0078)\r
+#define BKP_DR26 ((uint16_t)0x007C)\r
+#define BKP_DR27 ((uint16_t)0x0080)\r
+#define BKP_DR28 ((uint16_t)0x0084)\r
+#define BKP_DR29 ((uint16_t)0x0088)\r
+#define BKP_DR30 ((uint16_t)0x008C)\r
+#define BKP_DR31 ((uint16_t)0x0090)\r
+#define BKP_DR32 ((uint16_t)0x0094)\r
+#define BKP_DR33 ((uint16_t)0x0098)\r
+#define BKP_DR34 ((uint16_t)0x009C)\r
+#define BKP_DR35 ((uint16_t)0x00A0)\r
+#define BKP_DR36 ((uint16_t)0x00A4)\r
+#define BKP_DR37 ((uint16_t)0x00A8)\r
+#define BKP_DR38 ((uint16_t)0x00AC)\r
+#define BKP_DR39 ((uint16_t)0x00B0)\r
+#define BKP_DR40 ((uint16_t)0x00B4)\r
+#define BKP_DR41 ((uint16_t)0x00B8)\r
+#define BKP_DR42 ((uint16_t)0x00BC)\r
+\r
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \\r
+ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \\r
+ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \\r
+ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \\r
+ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \\r
+ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \\r
+ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \\r
+ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \\r
+ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \\r
+ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \\r
+ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \\r
+ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \\r
+ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \\r
+ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))\r
+\r
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void BKP_DeInit(void);\r
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);\r
+void BKP_TamperPinCmd(FunctionalState NewState);\r
+void BKP_ITConfig(FunctionalState NewState);\r
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);\r
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);\r
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);\r
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);\r
+FlagStatus BKP_GetFlagStatus(void);\r
+void BKP_ClearFlag(void);\r
+ITStatus BKP_GetITStatus(void);\r
+void BKP_ClearITPendingBit(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_BKP_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_can.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the CAN firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CAN_H\r
+#define __STM32F10x_CAN_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CAN\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Types\r
+ * @{\r
+ */\r
+\r
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \\r
+ ((PERIPH) == CAN2))\r
+\r
+/** \r
+ * @brief CAN init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */\r
+ \r
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.\r
+ This parameter can be a value of @ref CAN_operating_mode */\r
+\r
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware\r
+ is allowed to lengthen or shorten a bit to perform resynchronization.\r
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */\r
+\r
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.\r
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\r
+\r
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.\r
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r
+ \r
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+ \r
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. \r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+} CAN_InitTypeDef;\r
+\r
+/** \r
+ * @brief CAN filter init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit\r
+ configuration, first one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit\r
+ configuration, second one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (MSBs for a 32-bit configuration,\r
+ first one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (LSBs for a 32-bit configuration,\r
+ second one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r
+ This parameter can be a value of @ref CAN_filter_FIFO */\r
+ \r
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */\r
+\r
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.\r
+ This parameter can be a value of @ref CAN_filter_mode */\r
+\r
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.\r
+ This parameter can be a value of @ref CAN_filter_scale */\r
+\r
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+} CAN_FilterInitTypeDef;\r
+\r
+/** \r
+ * @brief CAN Tx message structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter can be a value between 0 to 0x7FF. */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter can be a value between 0 to 0x1FFFFFFF. */\r
+\r
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.\r
+ This parameter can be a value of @ref CAN_identifier_type */\r
+\r
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.\r
+ This parameter can be a value of @ref CAN_remote_transmission_request */\r
+\r
+ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.\r
+ This parameter can be a value between 0 to 8 */\r
+\r
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */\r
+} CanTxMsg;\r
+\r
+/** \r
+ * @brief CAN Rx message structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter can be a value between 0 to 0x7FF. */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter can be a value between 0 to 0x1FFFFFFF. */\r
+\r
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.\r
+ This parameter can be a value of @ref CAN_identifier_type */\r
+\r
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.\r
+ This parameter can be a value of @ref CAN_remote_transmission_request */\r
+\r
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.\r
+ This parameter can be a value between 0 to 8 */\r
+\r
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */\r
+\r
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.\r
+ This parameter can be a value between 0 to 0xFF */\r
+} CanRxMsg;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_sleep_constants \r
+ * @{\r
+ */\r
+\r
+#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */\r
+#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_operating_mode \r
+ * @{\r
+ */\r
+\r
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */\r
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */\r
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */\r
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */\r
+\r
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \\r
+ ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_synchronisation_jump_width \r
+ * @{\r
+ */\r
+\r
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+\r
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \\r
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_1 \r
+ * @{\r
+ */\r
+\r
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */\r
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */\r
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */\r
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */\r
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */\r
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */\r
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */\r
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */\r
+\r
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_2 \r
+ * @{\r
+ */\r
+\r
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
+\r
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_clock_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_number \r
+ * @{\r
+ */\r
+#ifndef STM32F10X_CL\r
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)\r
+#else\r
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r
+#endif /* STM32F10X_CL */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_mode \r
+ * @{\r
+ */\r
+\r
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */\r
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */\r
+\r
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\r
+ ((MODE) == CAN_FilterMode_IdList))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_scale \r
+ * @{\r
+ */\r
+\r
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */\r
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */\r
+\r
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \\r
+ ((SCALE) == CAN_FilterScale_32bit))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_FIFO\r
+ * @{\r
+ */\r
+\r
+#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r
+#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \\r
+ ((FIFO) == CAN_FilterFIFO1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Start_bank_filter_for_slave_CAN \r
+ * @{\r
+ */\r
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Tx \r
+ * @{\r
+ */\r
+\r
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))\r
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_identifier_type \r
+ * @{\r
+ */\r
+\r
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */\r
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */\r
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_remote_transmission_request \r
+ * @{\r
+ */\r
+\r
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */\r
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */\r
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_transmit_constants \r
+ * @{\r
+ */\r
+\r
+#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */\r
+#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */\r
+#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */\r
+#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_receive_FIFO_number_constants \r
+ * @{\r
+ */\r
+\r
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */\r
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */\r
+\r
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_sleep_constants \r
+ * @{\r
+ */\r
+\r
+#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */\r
+#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_wake_up_constants \r
+ * @{\r
+ */\r
+\r
+#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */\r
+#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_flags \r
+ * @{\r
+ */\r
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()\r
+ and CAN_ClearFlag() functions. */\r
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */\r
+\r
+/* Transmit Flags */\r
+#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */\r
+#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */\r
+#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */\r
+\r
+/* Receive Flags */\r
+#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */\r
+#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */\r
+#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */\r
+#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */\r
+#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */\r
+#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */\r
+\r
+/* Operating Mode Flags */\r
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */\r
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */\r
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. \r
+ In this case the SLAK bit can be polled.*/\r
+\r
+/* Error Flags */\r
+#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */\r
+#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */\r
+#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */\r
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */\r
+\r
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \\r
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \\r
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \\r
+ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \\r
+ ((FLAG) == CAN_FLAG_SLAK ))\r
+\r
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\\r
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup CAN_interrupts \r
+ * @{\r
+ */\r
+\r
+\r
+ \r
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/\r
+\r
+/* Receive Interrupts */\r
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/\r
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/\r
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/\r
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/\r
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/\r
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/\r
+\r
+/* Operating Mode Interrupts */\r
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/\r
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/\r
+\r
+/* Error Interrupts */\r
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/\r
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/\r
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/\r
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/\r
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/\r
+\r
+/* Flags named as Interrupts : kept only for FW compatibility */\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+\r
+\r
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\\r
+ ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void CAN_DeInit(CAN_TypeDef* CANx);\r
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); \r
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);\r
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);\r
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);\r
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);\r
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);\r
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);\r
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);\r
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);\r
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_CAN_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_cec.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the CEC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CEC_H\r
+#define __STM32F10x_CEC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CEC\r
+ * @{\r
+ */\r
+ \r
+\r
+/** @defgroup CEC_Exported_Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief CEC Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. \r
+ This parameter can be a value of @ref CEC_BitTiming_Mode */\r
+ uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. \r
+ This parameter can be a value of @ref CEC_BitPeriod_Mode */\r
+}CEC_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup CEC_BitTiming_Mode \r
+ * @{\r
+ */ \r
+#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */\r
+#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */\r
+\r
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \\r
+ ((MODE) == CEC_BitTimingErrFreeMode))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_BitPeriod_Mode \r
+ * @{\r
+ */ \r
+#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */\r
+#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */\r
+\r
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \\r
+ ((MODE) == CEC_BitPeriodFlexibleMode))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_interrupts_definition \r
+ * @{\r
+ */ \r
+#define CEC_IT_TERR CEC_CSR_TERR\r
+#define CEC_IT_TBTRF CEC_CSR_TBTRF\r
+#define CEC_IT_RERR CEC_CSR_RERR\r
+#define CEC_IT_RBTF CEC_CSR_RBTF\r
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \\r
+ ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Own_Addres \r
+ * @{\r
+ */ \r
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CEC_Prescaler \r
+ * @{\r
+ */ \r
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_flags_definition \r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief ESR register flags \r
+ */ \r
+#define CEC_FLAG_BTE ((uint32_t)0x10010000)\r
+#define CEC_FLAG_BPE ((uint32_t)0x10020000)\r
+#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)\r
+#define CEC_FLAG_SBE ((uint32_t)0x10080000)\r
+#define CEC_FLAG_ACKE ((uint32_t)0x10100000)\r
+#define CEC_FLAG_LINE ((uint32_t)0x10200000)\r
+#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)\r
+\r
+/** \r
+ * @brief CSR register flags \r
+ */ \r
+#define CEC_FLAG_TEOM ((uint32_t)0x00000002) \r
+#define CEC_FLAG_TERR ((uint32_t)0x00000004)\r
+#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)\r
+#define CEC_FLAG_RSOM ((uint32_t)0x00000010)\r
+#define CEC_FLAG_REOM ((uint32_t)0x00000020)\r
+#define CEC_FLAG_RERR ((uint32_t)0x00000040)\r
+#define CEC_FLAG_RBTF ((uint32_t)0x00000080)\r
+\r
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))\r
+ \r
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \\r
+ ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \\r
+ ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \\r
+ ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \\r
+ ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \\r
+ ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \\r
+ ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CEC_Exported_Macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions\r
+ * @{\r
+ */ \r
+void CEC_DeInit(void);\r
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);\r
+void CEC_Cmd(FunctionalState NewState);\r
+void CEC_ITConfig(FunctionalState NewState);\r
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);\r
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);\r
+void CEC_SendDataByte(uint8_t Data);\r
+uint8_t CEC_ReceiveDataByte(void);\r
+void CEC_StartOfMessage(void);\r
+void CEC_EndOfMessageCmd(FunctionalState NewState);\r
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);\r
+void CEC_ClearFlag(uint32_t CEC_FLAG);\r
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);\r
+void CEC_ClearITPendingBit(uint16_t CEC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_CEC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_crc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CRC_H\r
+#define __STM32F10x_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void CRC_ResetDR(void);\r
+uint32_t CRC_CalcCRC(uint32_t Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+void CRC_SetIDRegister(uint8_t IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_CRC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dac.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DAC_H\r
+#define __STM32F10x_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_trigger_selection */\r
+\r
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
+ are generated, or whether no wave is generated.\r
+ This parameter can be a value of @ref DAC_wave_generation */\r
+\r
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
+ the maximum amplitude triangle generation for the DAC channel. \r
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_output_buffer */\r
+}DAC_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
+ only in High-density devices*/\r
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
+ only in Connectivity line, Medium-density and Low-density Value Line devices */\r
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \r
+ only in Medium-density and Low-density Value Line devices*/\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_lfsrunmask_triangleamplitude\r
+ * @{\r
+ */\r
+\r
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define DAC_Channel_2 ((uint32_t)0x00000010)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignement \r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+/**\r
+ * @}\r
+ */\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/** @defgroup DAC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DAC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void DAC_DeInit(void);\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
+#endif\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) \r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_DAC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the DBGMCU \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DBGMCU_H\r
+#define __STM32F10x_DBGMCU_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)\r
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)\r
+#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)\r
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)\r
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)\r
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)\r
+#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)\r
+#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)\r
+#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)\r
+#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)\r
+#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)\r
+#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)\r
+#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)\r
+#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)\r
+#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)\r
+#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)\r
+ \r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DBGMCU_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_DBGMCU_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dma.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the DMA firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DMA_H\r
+#define __STM32F10x_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief DMA Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
+ This parameter can be a value of @ref DMA_data_transfer_direction */\r
+\r
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
+ or DMA_MemoryDataSize members depending in the transfer direction. */\r
+\r
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
+\r
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_memory_incremented_mode */\r
+\r
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_peripheral_data_size */\r
+\r
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_memory_data_size */\r
+\r
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_circular_normal_mode.\r
+ @note: The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_priority_level */\r
+\r
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
+ This parameter can be a value of @ref DMA_memory_to_memory */\r
+}DMA_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
+ ((PERIPH) == DMA1_Channel2) || \\r
+ ((PERIPH) == DMA1_Channel3) || \\r
+ ((PERIPH) == DMA1_Channel4) || \\r
+ ((PERIPH) == DMA1_Channel5) || \\r
+ ((PERIPH) == DMA1_Channel6) || \\r
+ ((PERIPH) == DMA1_Channel7) || \\r
+ ((PERIPH) == DMA2_Channel1) || \\r
+ ((PERIPH) == DMA2_Channel2) || \\r
+ ((PERIPH) == DMA2_Channel3) || \\r
+ ((PERIPH) == DMA2_Channel4) || \\r
+ ((PERIPH) == DMA2_Channel5))\r
+\r
+/** @defgroup DMA_data_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
+ ((DIR) == DMA_DIR_PeripheralSRC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
+ ((STATE) == DMA_PeripheralInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
+ ((STATE) == DMA_MemoryInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_circular_normal_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
+#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_priority_level \r
+ * @{\r
+ */\r
+\r
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
+#define DMA_Priority_High ((uint32_t)0x00002000)\r
+#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
+#define DMA_Priority_Low ((uint32_t)0x00000000)\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_to_memory \r
+ * @{\r
+ */\r
+\r
+#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
+#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define DMA_IT_TC ((uint32_t)0x00000002)\r
+#define DMA_IT_HT ((uint32_t)0x00000004)\r
+#define DMA_IT_TE ((uint32_t)0x00000008)\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
+\r
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
+\r
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)\r
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)\r
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)\r
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)\r
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)\r
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)\r
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)\r
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)\r
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)\r
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)\r
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)\r
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)\r
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)\r
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)\r
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)\r
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)\r
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)\r
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)\r
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)\r
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))\r
+\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \\r
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \\r
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \\r
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \\r
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \\r
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \\r
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \\r
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \\r
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \\r
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \\r
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flags_definition \r
+ * @{\r
+ */\r
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
+\r
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)\r
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)\r
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)\r
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)\r
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)\r
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)\r
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)\r
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)\r
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)\r
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)\r
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)\r
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)\r
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)\r
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)\r
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)\r
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)\r
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)\r
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)\r
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)\r
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))\r
+\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \\r
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \\r
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \\r
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \\r
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \\r
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \\r
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \\r
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \\r
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \\r
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \\r
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Buffer_Size \r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); \r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_DMA_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_exti.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the EXTI firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_EXTI_H\r
+#define __STM32F10x_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief EXTI mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+ * @brief EXTI Trigger enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+ * @brief EXTI Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
+ This parameter can be any combination of @ref EXTI_Lines */\r
+ \r
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Lines \r
+ * @{\r
+ */\r
+\r
+#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */\r
+#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */\r
+#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */\r
+#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */\r
+#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */\r
+#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */\r
+#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */\r
+#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */\r
+#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */\r
+#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */\r
+#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */\r
+#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */\r
+#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */\r
+#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */\r
+#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */\r
+#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */\r
+#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */\r
+#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
+#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS\r
+ Wakeup from suspend event */ \r
+#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */\r
+ \r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))\r
+\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void EXTI_DeInit(void);\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_EXTI_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_flash.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FLASH_H\r
+#define __STM32F10x_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief FLASH Status \r
+ */\r
+\r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_PG,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Flash_Latency \r
+ * @{\r
+ */\r
+\r
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */\r
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1) || \\r
+ ((LATENCY) == FLASH_Latency_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Half_Cycle_Enable_Disable \r
+ * @{\r
+ */\r
+\r
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */\r
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */\r
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \\r
+ ((STATE) == FLASH_HalfCycleAccess_Disable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Prefetch_Buffer_Enable_Disable \r
+ * @{\r
+ */\r
+\r
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */\r
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */\r
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \\r
+ ((STATE) == FLASH_PrefetchBuffer_Disable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_Write_Protection \r
+ * @{\r
+ */\r
+\r
+/* Values to be used with STM32 Low and Medium density devices */\r
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */\r
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */\r
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */\r
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */\r
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */\r
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */\r
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */\r
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */\r
+\r
+/* Values to be used with STM32 Medium-density devices */\r
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */\r
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */\r
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */\r
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */\r
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */\r
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */\r
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */\r
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */\r
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */\r
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */\r
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */\r
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */\r
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */\r
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */\r
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */\r
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */\r
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */\r
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */\r
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */\r
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */\r
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */\r
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */\r
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */\r
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */\r
+\r
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */\r
+#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 0 to 1 */\r
+#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 2 to 3 */\r
+#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 4 to 5 */\r
+#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 6 to 7 */\r
+#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 8 to 9 */\r
+#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 10 to 11 */\r
+#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 12 to 13 */\r
+#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 14 to 15 */\r
+#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 16 to 17 */\r
+#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 18 to 19 */\r
+#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 20 to 21 */\r
+#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 22 to 23 */\r
+#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 24 to 25 */\r
+#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 26 to 27 */\r
+#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 28 to 29 */\r
+#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 30 to 31 */\r
+#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 32 to 33 */\r
+#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 34 to 35 */\r
+#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 36 to 37 */\r
+#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 38 to 39 */\r
+#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 40 to 41 */\r
+#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 42 to 43 */\r
+#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 44 to 45 */\r
+#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 46 to 47 */\r
+#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 48 to 49 */\r
+#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 50 to 51 */\r
+#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 52 to 53 */\r
+#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 54 to 55 */\r
+#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 56 to 57 */\r
+#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 58 to 59 */\r
+#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 60 to 61 */\r
+#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */\r
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */\r
+#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */\r
+\r
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */\r
+\r
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))\r
+\r
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_IWatchdog \r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */\r
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STOP \r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup FLASH_Boot\r
+ * @{\r
+ */\r
+#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank1(Default) */\r
+#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank 2 or Bank 1,\r
+ depending on the activation of the bank */\r
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */\r
+#ifdef STM32F10X_XL\r
+#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */\r
+#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */\r
+\r
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
+\r
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */\r
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+#else\r
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */\r
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */\r
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
+\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */\r
+#ifdef STM32F10X_XL\r
+#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */\r
+#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */\r
+#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */\r
+#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */\r
+\r
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
+\r
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_OPTERR)|| \\r
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))\r
+#else\r
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
+\r
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_OPTERR))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/*------------ Functions used for all STM32F10x devices -----*/\r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);\r
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);\r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+FLASH_Status FLASH_EraseAllPages(void);\r
+FLASH_Status FLASH_EraseOptionBytes(void);\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);\r
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);\r
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);\r
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);\r
+uint32_t FLASH_GetUserOptionByte(void);\r
+uint32_t FLASH_GetWriteProtectionOptionByte(void);\r
+FlagStatus FLASH_GetReadOutProtectionStatus(void);\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void);\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+/*------------ New function used for all STM32F10x devices -----*/\r
+void FLASH_UnlockBank1(void);\r
+void FLASH_LockBank1(void);\r
+FLASH_Status FLASH_EraseAllBank1Pages(void);\r
+FLASH_Status FLASH_GetBank1Status(void);\r
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);\r
+\r
+#ifdef STM32F10X_XL\r
+/*---- New Functions used only with STM32F10x_XL density devices -----*/\r
+void FLASH_UnlockBank2(void);\r
+void FLASH_LockBank2(void);\r
+FLASH_Status FLASH_EraseAllBank2Pages(void);\r
+FLASH_Status FLASH_GetBank2Status(void);\r
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);\r
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_FLASH_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_fsmc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the FSMC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FSMC_H\r
+#define __STM32F10x_FSMC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FSMC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief Timing parameters For NOR/SRAM Banks \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address setup time. \r
+ This parameter can be a value between 0 and 0xF.\r
+ @note: It is not used with synchronous NOR Flash memories. */\r
+\r
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address hold time.\r
+ This parameter can be a value between 0 and 0xF. \r
+ @note: It is not used with synchronous NOR Flash memories.*/\r
+\r
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the data setup time.\r
+ This parameter can be a value between 0 and 0xFF.\r
+ @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the bus turnaround.\r
+ This parameter can be a value between 0 and 0xF.\r
+ @note: It is only used for multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r
+ This parameter can be a value between 1 and 0xF.\r
+ @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r
+\r
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r
+ to the memory before getting the first data.\r
+ The value of this parameter depends on the memory type as shown below:\r
+ - It must be set to 0 in case of a CRAM\r
+ - It is don\92t care in asynchronous NOR, SRAM or ROM accesses\r
+ - It may assume a value between 0 and 0xF in NOR Flash memories\r
+ with synchronous burst mode enable */\r
+\r
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r
+ This parameter can be a value of @ref FSMC_Access_Mode */\r
+}FSMC_NORSRAMTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NOR/SRAM Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r
+\r
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r
+ multiplexed on the databus or not. \r
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r
+\r
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r
+ the corresponding memory bank.\r
+ This parameter can be a value of @ref FSMC_Memory_Type */\r
+\r
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be a value of @ref FSMC_Data_Width */\r
+\r
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
+ valid only with synchronous burst Flash memories.\r
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r
+ \r
+ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r
+ valid only with asynchronous Flash memories.\r
+ This parameter can be a value of @ref FSMC_AsynchronousWait */\r
+\r
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
+ the Flash memory in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r
+\r
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r
+ memory, valid only when accessing Flash memories in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wrap_Mode */\r
+\r
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
+ clock cycle before the wait state or during the wait state,\r
+ valid only when accessing memories in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Timing */\r
+\r
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r
+ This parameter can be a value of @ref FSMC_Write_Operation */\r
+\r
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r
+ signal, valid for Flash memory access in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Signal */\r
+\r
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r
+ This parameter can be a value of @ref FSMC_Extended_Mode */\r
+\r
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r
+ This parameter can be a value of @ref FSMC_Write_Burst */ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r
+}FSMC_NORSRAMInitTypeDef;\r
+\r
+/** \r
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before\r
+ the command assertion for NAND-Flash read or write access\r
+ to common/Attribute or I/O memory space (depending on\r
+ the memory space timing to be configured).\r
+ This parameter can be a value between 0 and 0xFF.*/\r
+\r
+ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the\r
+ command for NAND-Flash read or write access to\r
+ common/Attribute or I/O memory space (depending on the\r
+ memory space timing to be configured). \r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address\r
+ (and data for write access) after the command deassertion\r
+ for NAND-Flash read or write access to common/Attribute\r
+ or I/O memory space (depending on the memory space timing\r
+ to be configured).\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the\r
+ databus is kept in HiZ after the start of a NAND-Flash\r
+ write access to common/Attribute or I/O memory space (depending\r
+ on the memory space timing to be configured).\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+}FSMC_NAND_PCCARDTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NAND Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.\r
+ This parameter can be a value of @ref FSMC_NAND_Bank */\r
+\r
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.\r
+ This parameter can be any value of @ref FSMC_Wait_feature */\r
+\r
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be any value of @ref FSMC_Data_Width */\r
+\r
+ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.\r
+ This parameter can be any value of @ref FSMC_ECC */\r
+\r
+ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.\r
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */\r
+\r
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between CLE low and RE low.\r
+ This parameter can be a value between 0 and 0xFF. */\r
+\r
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between ALE low and RE low.\r
+ This parameter can be a number between 0x0 and 0xFF */ \r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ \r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */\r
+}FSMC_NANDInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC PCCARD Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.\r
+ This parameter can be any value of @ref FSMC_Wait_feature */\r
+\r
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between CLE low and RE low.\r
+ This parameter can be a value between 0 and 0xFF. */\r
+\r
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between ALE low and RE low.\r
+ This parameter can be a number between 0x0 and 0xFF */ \r
+\r
+ \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */\r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ \r
+ \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ \r
+}FSMC_PCCARDInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_NORSRAM_Bank \r
+ * @{\r
+ */\r
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_NAND_Bank \r
+ * @{\r
+ */ \r
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)\r
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_PCCARD_Bank \r
+ * @{\r
+ */ \r
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM4))\r
+\r
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND))\r
+\r
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+\r
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+\r
+/** @defgroup NOR_SRAM_Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
+ ((MUX) == FSMC_DataAddressMux_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Memory_Type \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
+ ((MEMORY) == FSMC_MemoryType_NOR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Width \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Burst_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
+ ((STATE) == FSMC_BurstAccessMode_Enable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_AsynchronousWait \r
+ * @{\r
+ */\r
+#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)\r
+#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)\r
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \\r
+ ((STATE) == FSMC_AsynchronousWait_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_Wait_Signal_Polarity \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
+ ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wrap_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
+ ((MODE) == FSMC_WrapMode_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Timing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Operation \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
+ ((OPERATION) == FSMC_WriteOperation_Enable))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Signal \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
+ ((SIGNAL) == FSMC_WaitSignal_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Extended_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
+\r
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
+ ((MODE) == FSMC_ExtendedMode_Enable)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Burst \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
+ ((BURST) == FSMC_WriteBurst_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Hold_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Bus_Turn_around_Duration \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_CLK_Division \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Latency \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
+#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
+ ((MODE) == FSMC_AccessMode_B) || \\r
+ ((MODE) == FSMC_AccessMode_C) || \\r
+ ((MODE) == FSMC_AccessMode_D)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup NAND_PCCARD_Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_feature \r
+ * @{\r
+ */\r
+\r
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)\r
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
+ ((FEATURE) == FSMC_Waitfeature_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup FSMC_ECC \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)\r
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
+ ((STATE) == FSMC_ECC_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_ECC_Page_Size \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)\r
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)\r
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)\r
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)\r
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)\r
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)\r
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TCLR_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TAR_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Hold_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_HiZ_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)\r
+#define FSMC_IT_Level ((uint32_t)0x00000010)\r
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)\r
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
+ ((IT) == FSMC_IT_Level) || \\r
+ ((IT) == FSMC_IT_FallingEdge)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Flags \r
+ * @{\r
+ */\r
+\r
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)\r
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)\r
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)\r
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)\r
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_Level) || \\r
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_FEMPT))\r
+\r
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);\r
+void FSMC_PCCARDDeInit(void);\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+void FSMC_PCCARDCmd(FunctionalState NewState);\r
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_FSMC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the GPIO \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_GPIO_H\r
+#define __STM32F10x_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Types\r
+ * @{\r
+ */\r
+\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB) || \\r
+ ((PERIPH) == GPIOC) || \\r
+ ((PERIPH) == GPIOD) || \\r
+ ((PERIPH) == GPIOE) || \\r
+ ((PERIPH) == GPIOF) || \\r
+ ((PERIPH) == GPIOG))\r
+ \r
+/** \r
+ * @brief Output Maximum frequency selection \r
+ */\r
+\r
+typedef enum\r
+{ \r
+ GPIO_Speed_10MHz = 1,\r
+ GPIO_Speed_2MHz, \r
+ GPIO_Speed_50MHz\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+ ((SPEED) == GPIO_Speed_50MHz))\r
+\r
+/** \r
+ * @brief Configuration Mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{ GPIO_Mode_AIN = 0x0,\r
+ GPIO_Mode_IN_FLOATING = 0x04,\r
+ GPIO_Mode_IPD = 0x28,\r
+ GPIO_Mode_IPU = 0x48,\r
+ GPIO_Mode_Out_OD = 0x14,\r
+ GPIO_Mode_Out_PP = 0x10,\r
+ GPIO_Mode_AF_OD = 0x1C,\r
+ GPIO_Mode_AF_PP = 0x18\r
+}GPIOMode_TypeDef;\r
+\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \\r
+ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \\r
+ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \\r
+ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))\r
+\r
+/** \r
+ * @brief GPIO Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIOMode_TypeDef */\r
+}GPIO_InitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief Bit_SET and Bit_RESET enumeration \r
+ */\r
+\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_pins_define \r
+ * @{\r
+ */\r
+\r
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))\r
+\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Remap_define \r
+ * @{\r
+ */\r
+\r
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */\r
+#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */\r
+#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */\r
+#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */\r
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */\r
+#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */\r
+#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */\r
+#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */\r
+#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */\r
+#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */\r
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */\r
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */\r
+#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */\r
+#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */\r
+#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */\r
+#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */\r
+#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */\r
+#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */\r
+#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */\r
+#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */\r
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected\r
+ to TIM2 Internal Trigger 1 for calibration\r
+ (only for Connectivity line devices) */\r
+#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */\r
+\r
+#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */\r
+\r
+#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */\r
+#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */\r
+#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */\r
+#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */\r
+#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */\r
+#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */\r
+\r
+#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */\r
+#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */\r
+#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \r
+ only for High density Value line devices) */ \r
+\r
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \\r
+ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \\r
+ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \\r
+ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \\r
+ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \\r
+ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \\r
+ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \\r
+ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \\r
+ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \\r
+ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \\r
+ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \\r
+ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \\r
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \\r
+ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \\r
+ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \\r
+ ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \\r
+ ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \\r
+ ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \\r
+ ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \\r
+ ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \\r
+ ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \\r
+ ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup GPIO_Port_Sources \r
+ * @{\r
+ */\r
+\r
+#define GPIO_PortSourceGPIOA ((uint8_t)0x00)\r
+#define GPIO_PortSourceGPIOB ((uint8_t)0x01)\r
+#define GPIO_PortSourceGPIOC ((uint8_t)0x02)\r
+#define GPIO_PortSourceGPIOD ((uint8_t)0x03)\r
+#define GPIO_PortSourceGPIOE ((uint8_t)0x04)\r
+#define GPIO_PortSourceGPIOF ((uint8_t)0x05)\r
+#define GPIO_PortSourceGPIOG ((uint8_t)0x06)\r
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE))\r
+\r
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOG))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+ * @{\r
+ */\r
+\r
+#define GPIO_PinSource0 ((uint8_t)0x00)\r
+#define GPIO_PinSource1 ((uint8_t)0x01)\r
+#define GPIO_PinSource2 ((uint8_t)0x02)\r
+#define GPIO_PinSource3 ((uint8_t)0x03)\r
+#define GPIO_PinSource4 ((uint8_t)0x04)\r
+#define GPIO_PinSource5 ((uint8_t)0x05)\r
+#define GPIO_PinSource6 ((uint8_t)0x06)\r
+#define GPIO_PinSource7 ((uint8_t)0x07)\r
+#define GPIO_PinSource8 ((uint8_t)0x08)\r
+#define GPIO_PinSource9 ((uint8_t)0x09)\r
+#define GPIO_PinSource10 ((uint8_t)0x0A)\r
+#define GPIO_PinSource11 ((uint8_t)0x0B)\r
+#define GPIO_PinSource12 ((uint8_t)0x0C)\r
+#define GPIO_PinSource13 ((uint8_t)0x0D)\r
+#define GPIO_PinSource14 ((uint8_t)0x0E)\r
+#define GPIO_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Ethernet_Media_Interface \r
+ * @{\r
+ */ \r
+#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) \r
+#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) \r
+\r
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \\r
+ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_AFIODeInit(void);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);\r
+void GPIO_EventOutputCmd(FunctionalState NewState);\r
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);\r
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);\r
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_GPIO_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the I2C firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_I2C_H\r
+#define __STM32F10x_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief I2C Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
+ This parameter must be set to a value lower than 400kHz */\r
+\r
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
+ This parameter can be a value of @ref I2C_mode */\r
+\r
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
+\r
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
+ This parameter can be a value of @ref I2C_acknowledgement */\r
+\r
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+ This parameter can be a value of @ref I2C_acknowledged_address */\r
+}I2C_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+ ((PERIPH) == I2C2))\r
+/** @defgroup I2C_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_Mode_I2C ((uint16_t)0x0000)\r
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_duty_cycle_in_fast_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+ ((CYCLE) == I2C_DutyCycle_2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_acknowledgement\r
+ * @{\r
+ */\r
+\r
+#define I2C_Ack_Enable ((uint16_t)0x0400)\r
+#define I2C_Ack_Disable ((uint16_t)0x0000)\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+ ((STATE) == I2C_Ack_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
+#define I2C_Direction_Receiver ((uint8_t)0x01)\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledged_address \r
+ * @{\r
+ */\r
+\r
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_registers \r
+ * @{\r
+ */\r
+\r
+#define I2C_Register_CR1 ((uint8_t)0x00)\r
+#define I2C_Register_CR2 ((uint8_t)0x04)\r
+#define I2C_Register_OAR1 ((uint8_t)0x08)\r
+#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
+#define I2C_Register_DR ((uint8_t)0x10)\r
+#define I2C_Register_SR1 ((uint8_t)0x14)\r
+#define I2C_Register_SR2 ((uint8_t)0x18)\r
+#define I2C_Register_CCR ((uint8_t)0x1C)\r
+#define I2C_Register_TRISE ((uint8_t)0x20)\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_DR) || \\r
+ ((REGISTER) == I2C_Register_SR1) || \\r
+ ((REGISTER) == I2C_Register_SR2) || \\r
+ ((REGISTER) == I2C_Register_CCR) || \\r
+ ((REGISTER) == I2C_Register_TRISE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_SMBus_alert_pin_level \r
+ * @{\r
+ */\r
+\r
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+ ((ALERT) == I2C_SMBusAlert_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_PEC_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+ ((POSITION) == I2C_PECPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_BUF ((uint16_t)0x0400)\r
+#define I2C_IT_EVT ((uint16_t)0x0200)\r
+#define I2C_IT_ERR ((uint16_t)0x0100)\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
+#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
+#define I2C_IT_OVR ((uint32_t)0x01000800)\r
+#define I2C_IT_AF ((uint32_t)0x01000400)\r
+#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
+#define I2C_IT_BERR ((uint32_t)0x01000100)\r
+#define I2C_IT_TXE ((uint32_t)0x06000080)\r
+#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
+#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
+#define I2C_IT_BTF ((uint32_t)0x02000004)\r
+#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
+#define I2C_IT_SB ((uint32_t)0x02000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_flags_definition \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SR2 register flags \r
+ */\r
+\r
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
+\r
+/** \r
+ * @brief SR1 register flags \r
+ */\r
+\r
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
+#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
+#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Events \r
+ * @{\r
+ */\r
+\r
+/*========================================\r
+ \r
+ I2C Master Events (Events grouped in order of communication)\r
+ ==========================================*/\r
+/** \r
+ * @brief Communication start\r
+ * \r
+ * After sending the START condition (I2C_GenerateSTART() function) the master \r
+ * has to wait for this event. It means that the Start condition has been correctly \r
+ * released on the I2C bus (the bus is free, no other devices is communicating).\r
+ * \r
+ */\r
+/* --EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/** \r
+ * @brief Address Acknowledge\r
+ * \r
+ * After checking on EV5 (start condition correctly released on the bus), the \r
+ * master sends the address of the slave(s) with which it will communicate \r
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
+ * his address. If an acknowledge is sent on the bus, one of the following events will \r
+ * be set:\r
+ * \r
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
+ * event is set.\r
+ * \r
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
+ * is set\r
+ * \r
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
+ * function). Then master should wait on EV9. It means that the 10-bit addressing \r
+ * header has been correctly sent on the bus. Then master should send the second part of \r
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
+ * should wait for event EV6. \r
+ * \r
+ */\r
+\r
+/* --EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
+/* --EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * If a communication is established (START condition generated and slave address \r
+ * acknowledged) then the master has to check on one of the following events for \r
+ * communication procedures:\r
+ * \r
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
+ * the data received from the slave (I2C_ReceiveData() function).\r
+ * \r
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
+ * function) then to wait on event EV8 or EV8_2.\r
+ * These two events are similar: \r
+ * - EV8 means that the data has been written in the data register and is \r
+ * being shifted out.\r
+ * - EV8_2 means that the data has been physically shifted out and output \r
+ * on the bus.\r
+ * In most cases, using EV8 is sufficient for the application.\r
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
+ * (before Stop condition generation).\r
+ * \r
+ * @note In case the user software does not guarantee that this event EV7 is \r
+ * managed before the current byte end of transfer, then user may check on EV7 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ * \r
+ */\r
+\r
+/* Master RECEIVER mode -----------------------------*/ \r
+/* --EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* Master TRANSMITTER mode --------------------------*/\r
+/* --EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
+/* --EV8_2 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+/*========================================\r
+ \r
+ I2C Slave Events (Events grouped in order of communication)\r
+ ==========================================*/\r
+\r
+/** \r
+ * @brief Communication start events\r
+ * \r
+ * Wait on one of these events at the start of the communication. It means that \r
+ * the I2C peripheral detected a Start condition on the bus (generated by master \r
+ * device) followed by the peripheral address. The peripheral generates an ACK \r
+ * condition on the bus (if the acknowledge feature is enabled through function \r
+ * I2C_AcknowledgeConfig()) and the events listed above are set :\r
+ * \r
+ * 1) In normal case (only one address managed by the slave), when the address \r
+ * sent by the master matches the own address of the peripheral (configured by \r
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
+ * (where XXX could be TRANSMITTER or RECEIVER).\r
+ * \r
+ * 2) In case the address sent by the master matches the second address of the \r
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
+ * \r
+ * 3) In case the address sent by the master is General Call (address 0x00) and \r
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
+ * \r
+ */\r
+\r
+/* --EV1 (all the events below are variants of EV1) */ \r
+/* 1) Case of One Single Address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+\r
+/* 2) Case of Dual address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+\r
+/* 3) Case of General Call enabled for the slave */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * Wait on one of these events when EV1 has already been checked and: \r
+ * \r
+ * - Slave RECEIVER mode:\r
+ * - EV2: When the application is expecting a data byte to be received. \r
+ * - EV4: When the application is expecting the end of the communication: master \r
+ * sends a stop condition and data transmission is stopped.\r
+ * \r
+ * - Slave Transmitter mode:\r
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
+ * used when the user software doesn't guarantee the EV3 is managed before the\r
+ * current byte end of tranfer.\r
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
+ * shall end (before sending the STOP condition). In this case slave has to stop sending \r
+ * data bytes and expect a Stop condition on the bus.\r
+ * \r
+ * @note In case the user software does not guarantee that the event EV2 is \r
+ * managed before the current byte end of transfer, then user may check on EV2 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+\r
+/* Slave RECEIVER mode --------------------------*/ \r
+/* --EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
+/* --EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
+\r
+/* Slave TRANSMITTER mode -----------------------*/\r
+/* --EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
+/* --EV3_2 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
+\r
+/*=========================== End of Events Description ==========================================*/\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address1 \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_clock_speed \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
+\r
+/**\r
+ * @brief\r
+ ****************************************************************************************\r
+ *\r
+ * I2C State Monitoring Functions\r
+ * \r
+ **************************************************************************************** \r
+ * This I2C driver provides three different ways for I2C state monitoring\r
+ * depending on the application requirements and constraints:\r
+ * \r
+ * \r
+ * 1) Basic state monitoring:\r
+ * Using I2C_CheckEvent() function:\r
+ * It compares the status registers (SR1 and SR2) content to a given event\r
+ * (can be the combination of one or more flags).\r
+ * It returns SUCCESS if the current status includes the given flags \r
+ * and returns ERROR if one or more flags are missing in the current status.\r
+ * - When to use:\r
+ * - This function is suitable for most applications as well as for startup \r
+ * activity since the events are fully described in the product reference manual \r
+ * (RM0008).\r
+ * - It is also suitable for users who need to define their own events.\r
+ * - Limitations:\r
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
+ * hold or corrupted real state. \r
+ * In this case, it is advised to use error interrupts to monitor the error\r
+ * events and handle them in the interrupt IRQ handler.\r
+ * \r
+ * @note \r
+ * For error management, it is advised to use the following functions:\r
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
+ * Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()\r
+ * in order to determine which error occured.\r
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
+ * and return to correct communication status.\r
+ * \r
+ *\r
+ * 2) Advanced state monitoring:\r
+ * Using the function I2C_GetLastEvent() which returns the image of both status \r
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ * by 16 bits and concatenated to Status Register 1).\r
+ * - When to use:\r
+ * - This function is suitable for the same applications above but it allows to\r
+ * overcome the limitations of I2C_GetFlagStatus() function (see below).\r
+ * The returned value could be compared to events already defined in the \r
+ * library (stm32f10x_i2c.h) or to custom values defined by user.\r
+ * - This function is suitable when multiple flags are monitored at the same time.\r
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
+ * choose when an event is accepted (when all events flags are set and no \r
+ * other flags are set or just when the needed flags are set like \r
+ * I2C_CheckEvent() function).\r
+ * - Limitations:\r
+ * - User may need to define his own events.\r
+ * - Same remark concerning the error management is applicable for this \r
+ * function if user decides to check only regular communication flags (and \r
+ * ignores error flags).\r
+ * \r
+ *\r
+ * 3) Flag-based state monitoring:\r
+ * Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ * one single flag (ie. I2C_FLAG_RXNE ...). \r
+ * - When to use:\r
+ * - This function could be used for specific applications or in debug phase.\r
+ * - It is suitable when only one flag checking is needed (most I2C events \r
+ * are monitored through multiple flags).\r
+ * - Limitations: \r
+ * - When calling this function, the Status register is accessed. Some flags are\r
+ * cleared when the status register is accessed. So checking the status\r
+ * of one Flag, may clear other ones.\r
+ * - Function may need to be called twice or more in order to monitor one \r
+ * single event.\r
+ * \r
+ */\r
+\r
+/**\r
+ * \r
+ * 1) Basic state monitoring\r
+ *******************************************************************************\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
+/**\r
+ * \r
+ * 2) Advanced state monitoring\r
+ *******************************************************************************\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+/**\r
+ * \r
+ * 3) Flag-based state monitoring\r
+ *******************************************************************************\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+/**\r
+ *\r
+ *******************************************************************************\r
+ */\r
+\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_I2C_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the IWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_IWDG_H\r
+#define __STM32F10x_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_WriteAccess\r
+ * @{\r
+ */\r
+\r
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
+#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
+#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
+#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
+#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
+#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
+#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Flag \r
+ * @{\r
+ */\r
+\r
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
+void IWDG_SetReload(uint16_t Reload);\r
+void IWDG_ReloadCounter(void);\r
+void IWDG_Enable(void);\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_IWDG_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_PWR_H\r
+#define __STM32F10x_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)\r
+#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)\r
+#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)\r
+#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)\r
+#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)\r
+#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)\r
+#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)\r
+#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Regulator_state_is_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower ((uint32_t)0x00000001)\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU ((uint32_t)0x00000001)\r
+#define PWR_FLAG_SB ((uint32_t)0x00000002)\r
+#define PWR_FLAG_PVDO ((uint32_t)0x00000004)\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void PWR_DeInit(void);\r
+void PWR_BackupAccessCmd(FunctionalState NewState);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_WakeUpPinCmd(FunctionalState NewState);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_PWR_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the RCC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RCC_H\r
+#define __STM32F10x_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */\r
+ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */\r
+ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */\r
+ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */\r
+ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */\r
+}RCC_ClocksTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_HSE_OFF ((uint32_t)0x00000000)\r
+#define RCC_HSE_ON ((uint32_t)0x00010000)\r
+#define RCC_HSE_Bypass ((uint32_t)0x00040000)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PLL_entry_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)\r
+ #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)\r
+ #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)\r
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE_Div2))\r
+#else\r
+ #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)\r
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
+ ((SOURCE) == RCC_PLLSource_PREDIV1))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PLL_multiplication_factor \r
+ * @{\r
+ */\r
+#ifndef STM32F10X_CL\r
+ #define RCC_PLLMul_2 ((uint32_t)0x00000000)\r
+ #define RCC_PLLMul_3 ((uint32_t)0x00040000)\r
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)\r
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)\r
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)\r
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)\r
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)\r
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)\r
+ #define RCC_PLLMul_10 ((uint32_t)0x00200000)\r
+ #define RCC_PLLMul_11 ((uint32_t)0x00240000)\r
+ #define RCC_PLLMul_12 ((uint32_t)0x00280000)\r
+ #define RCC_PLLMul_13 ((uint32_t)0x002C0000)\r
+ #define RCC_PLLMul_14 ((uint32_t)0x00300000)\r
+ #define RCC_PLLMul_15 ((uint32_t)0x00340000)\r
+ #define RCC_PLLMul_16 ((uint32_t)0x00380000)\r
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \\r
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \\r
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \\r
+ ((MUL) == RCC_PLLMul_16))\r
+\r
+#else\r
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)\r
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)\r
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)\r
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)\r
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)\r
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)\r
+ #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)\r
+\r
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
+ ((MUL) == RCC_PLLMul_6_5))\r
+#endif /* STM32F10X_CL */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PREDIV1_division_factor\r
+ * @{\r
+ */\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)\r
+ #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)\r
+ #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)\r
+ #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)\r
+ #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)\r
+ #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)\r
+ #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)\r
+ #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)\r
+ #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)\r
+ #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)\r
+ #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)\r
+ #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)\r
+ #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)\r
+ #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)\r
+ #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)\r
+ #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)\r
+ #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)\r
+\r
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PREDIV1_clock_source\r
+ * @{\r
+ */\r
+#ifdef STM32F10X_CL\r
+/* PREDIV1 clock source (for STM32 connectivity line devices) */\r
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) \r
+ #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) \r
+\r
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \\r
+ ((SOURCE) == RCC_PREDIV1_Source_PLL2)) \r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/* PREDIV1 clock source (for STM32 Value line devices) */\r
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) \r
+\r
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) \r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef STM32F10X_CL\r
+/** @defgroup PREDIV2_division_factor\r
+ * @{\r
+ */\r
+ \r
+ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)\r
+ #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)\r
+ #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)\r
+ #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)\r
+ #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)\r
+ #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)\r
+ #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)\r
+ #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)\r
+ #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)\r
+ #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)\r
+ #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)\r
+ #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)\r
+ #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)\r
+ #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)\r
+ #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)\r
+ #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)\r
+\r
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PLL2_multiplication_factor\r
+ * @{\r
+ */\r
+ \r
+ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)\r
+ #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)\r
+ #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)\r
+ #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)\r
+ #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)\r
+ #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)\r
+ #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)\r
+ #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)\r
+ #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)\r
+\r
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \\r
+ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \\r
+ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \\r
+ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \\r
+ ((MUL) == RCC_PLL2Mul_20))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PLL3_multiplication_factor\r
+ * @{\r
+ */\r
+\r
+ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)\r
+ #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)\r
+ #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)\r
+ #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)\r
+ #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)\r
+ #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)\r
+ #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)\r
+ #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)\r
+ #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)\r
+\r
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \\r
+ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \\r
+ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \\r
+ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \\r
+ ((MUL) == RCC_PLL3Mul_20))\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F10X_CL */\r
+\r
+\r
+/** @defgroup System_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)\r
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)\r
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)\r
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)\r
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)\r
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)\r
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)\r
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)\r
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)\r
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)\r
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_APB2_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)\r
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)\r
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)\r
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)\r
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Interrupt_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))\r
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))\r
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))\r
+#else\r
+ #define RCC_IT_PLL2RDY ((uint8_t)0x20)\r
+ #define RCC_IT_PLL3RDY ((uint8_t)0x40)\r
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))\r
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \\r
+ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))\r
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)\r
+#endif /* STM32F10X_CL */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifndef STM32F10X_CL\r
+/** @defgroup USB_Device_clock_source \r
+ * @{\r
+ */\r
+\r
+ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)\r
+ #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \\r
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))\r
+/**\r
+ * @}\r
+ */\r
+#else\r
+/** @defgroup USB_OTG_FS_clock_source \r
+ * @{\r
+ */\r
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)\r
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \\r
+ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F10X_CL */ \r
+\r
+\r
+#ifdef STM32F10X_CL\r
+/** @defgroup I2S2_clock_source \r
+ * @{\r
+ */\r
+ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)\r
+ #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S3_clock_source \r
+ * @{\r
+ */\r
+ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)\r
+ #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) \r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F10X_CL */ \r
+ \r
+\r
+/** @defgroup ADC_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)\r
+#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)\r
+#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)\r
+#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)\r
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \\r
+ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSE_OFF ((uint8_t)0x00)\r
+#define RCC_LSE_ON ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass ((uint8_t)0x04)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)\r
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)\r
+#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_peripheral \r
+ * @{\r
+ */\r
+\r
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)\r
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)\r
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)\r
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)\r
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)\r
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)\r
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))\r
+#else\r
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)\r
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)\r
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)\r
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)\r
+\r
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))\r
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))\r
+#endif /* STM32F10X_CL */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup APB2_peripheral \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)\r
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)\r
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)\r
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)\r
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)\r
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)\r
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)\r
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)\r
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)\r
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)\r
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)\r
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)\r
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)\r
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)\r
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)\r
+#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)\r
+#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)\r
+#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)\r
+#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)\r
+#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)\r
+#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_peripheral \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)\r
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)\r
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)\r
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)\r
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)\r
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)\r
+#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)\r
+#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)\r
+#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)\r
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)\r
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)\r
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)\r
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)\r
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)\r
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)\r
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)\r
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)\r
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)\r
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)\r
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)\r
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)\r
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)\r
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)\r
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)\r
+#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)\r
+ \r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Clock_source_to_output_on_MCO_pin \r
+ * @{\r
+ */\r
+\r
+#define RCC_MCO_NoClock ((uint8_t)0x00)\r
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)\r
+#define RCC_MCO_HSI ((uint8_t)0x05)\r
+#define RCC_MCO_HSE ((uint8_t)0x06)\r
+#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \\r
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \\r
+ ((MCO) == RCC_MCO_PLLCLK_Div2))\r
+#else\r
+ #define RCC_MCO_PLL2CLK ((uint8_t)0x08)\r
+ #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)\r
+ #define RCC_MCO_XT1 ((uint8_t)0x0A)\r
+ #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)\r
+\r
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \\r
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \\r
+ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \\r
+ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \\r
+ ((MCO) == RCC_MCO_PLL3CLK))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \\r
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \\r
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_LPWRRST))\r
+#else\r
+ #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) \r
+ #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) \r
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \\r
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \\r
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_LPWRRST))\r
+#endif /* STM32F10X_CL */ \r
+\r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void RCC_DeInit(void);\r
+void RCC_HSEConfig(uint32_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)\r
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);\r
+#endif\r
+\r
+#ifdef STM32F10X_CL\r
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);\r
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);\r
+ void RCC_PLL2Cmd(FunctionalState NewState);\r
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);\r
+ void RCC_PLL3Cmd(FunctionalState NewState);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+\r
+#ifndef STM32F10X_CL\r
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);\r
+#else\r
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);\r
+\r
+#ifdef STM32F10X_CL\r
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); \r
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+#ifdef STM32F10X_CL\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_BackupResetCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCO);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_RCC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the RTC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RTC_H\r
+#define __STM32F10x_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RTC_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC_interrupts_define \r
+ * @{\r
+ */\r
+\r
+#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */\r
+#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */\r
+#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */\r
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \\r
+ ((IT) == RTC_IT_SEC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_interrupts_flags \r
+ * @{\r
+ */\r
+\r
+#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */\r
+#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */\r
+#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */\r
+#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */\r
+#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */\r
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \\r
+ ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \\r
+ ((FLAG) == RTC_FLAG_SEC))\r
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);\r
+void RTC_EnterConfigMode(void);\r
+void RTC_ExitConfigMode(void);\r
+uint32_t RTC_GetCounter(void);\r
+void RTC_SetCounter(uint32_t CounterValue);\r
+void RTC_SetPrescaler(uint32_t PrescalerValue);\r
+void RTC_SetAlarm(uint32_t AlarmValue);\r
+uint32_t RTC_GetDivider(void);\r
+void RTC_WaitForLastTask(void);\r
+void RTC_WaitForSynchro(void);\r
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);\r
+void RTC_ClearFlag(uint16_t RTC_FLAG);\r
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);\r
+void RTC_ClearITPendingBit(uint16_t RTC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_RTC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_sdio.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the SDIO firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SDIO_H\r
+#define __STM32F10x_SDIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDIO\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Types\r
+ * @{\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref SDIO_Clock_Edge */\r
+\r
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r
+ enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Clock_Bypass */\r
+\r
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r
+ disabled when the bus is idle.\r
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */\r
+\r
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r
+ This parameter can be a value of @ref SDIO_Bus_Wide */\r
+\r
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r
+\r
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r
+ This parameter can be a value between 0x00 and 0xFF. */\r
+ \r
+} SDIO_InitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r
+ to a card as part of a command message. If a command\r
+ contains an argument, it must be loaded into this register\r
+ before writing the command to the command register */\r
+\r
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r
+\r
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r
+ This parameter can be a value of @ref SDIO_Response_Type */\r
+\r
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r
+\r
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_CPSM_State */\r
+} SDIO_CmdInitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
+\r
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
+ \r
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r
+ This parameter can be a value of @ref SDIO_Data_Block_Size */\r
+ \r
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
+ is a read or write.\r
+ This parameter can be a value of @ref SDIO_Transfer_Direction */\r
+ \r
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
+ This parameter can be a value of @ref SDIO_Transfer_Type */\r
+ \r
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_DPSM_State */\r
+} SDIO_DataInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Edge \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
+ ((EDGE) == SDIO_ClockEdge_Falling))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Bypass \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
+ ((BYPASS) == SDIO_ClockBypass_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Clock_Power_Save \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
+ ((SAVE) == SDIO_ClockPowerSave_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Bus_Wide \r
+ * @{\r
+ */\r
+\r
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
+ ((WIDE) == SDIO_BusWide_8b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Hardware_Flow_Control \r
+ * @{\r
+ */\r
+\r
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Power_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SDIO_Interrupt_soucres \r
+ * @{\r
+ */\r
+\r
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Command_Index\r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Response_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Response_No ((uint32_t)0x00000000)\r
+#define SDIO_Response_Short ((uint32_t)0x00000040)\r
+#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
+ ((RESPONSE) == SDIO_Response_Short) || \\r
+ ((RESPONSE) == SDIO_Response_Long))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Wait_Interrupt_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
+ ((WAIT) == SDIO_Wait_Pend))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_CPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Response_Registers \r
+ * @{\r
+ */\r
+\r
+#define SDIO_RESP1 ((uint32_t)0x00000000)\r
+#define SDIO_RESP2 ((uint32_t)0x00000004)\r
+#define SDIO_RESP3 ((uint32_t)0x00000008)\r
+#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Length \r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Block_Size \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_32b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_64b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_128b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_256b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_512b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16384b)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Direction \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
+ ((DIR) == SDIO_TransferDir_ToSDIO))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
+ ((MODE) == SDIO_TransferMode_Block))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_DPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Flags \r
+ * @{\r
+ */\r
+\r
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
+ ((FLAG) == SDIO_FLAG_CMDREND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
+ ((FLAG) == SDIO_FLAG_DATAEND) || \\r
+ ((FLAG) == SDIO_FLAG_STBITERR) || \\r
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXACT) || \\r
+ ((FLAG) == SDIO_FLAG_RXACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
+ ((FLAG) == SDIO_FLAG_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
+\r
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
+ ((IT) == SDIO_IT_DCRCFAIL) || \\r
+ ((IT) == SDIO_IT_CTIMEOUT) || \\r
+ ((IT) == SDIO_IT_DTIMEOUT) || \\r
+ ((IT) == SDIO_IT_TXUNDERR) || \\r
+ ((IT) == SDIO_IT_RXOVERR) || \\r
+ ((IT) == SDIO_IT_CMDREND) || \\r
+ ((IT) == SDIO_IT_CMDSENT) || \\r
+ ((IT) == SDIO_IT_DATAEND) || \\r
+ ((IT) == SDIO_IT_STBITERR) || \\r
+ ((IT) == SDIO_IT_DBCKEND) || \\r
+ ((IT) == SDIO_IT_CMDACT) || \\r
+ ((IT) == SDIO_IT_TXACT) || \\r
+ ((IT) == SDIO_IT_RXACT) || \\r
+ ((IT) == SDIO_IT_TXFIFOHE) || \\r
+ ((IT) == SDIO_IT_RXFIFOHF) || \\r
+ ((IT) == SDIO_IT_TXFIFOF) || \\r
+ ((IT) == SDIO_IT_RXFIFOF) || \\r
+ ((IT) == SDIO_IT_TXFIFOE) || \\r
+ ((IT) == SDIO_IT_RXFIFOE) || \\r
+ ((IT) == SDIO_IT_TXDAVL) || \\r
+ ((IT) == SDIO_IT_RXDAVL) || \\r
+ ((IT) == SDIO_IT_SDIOIT) || \\r
+ ((IT) == SDIO_IT_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Read_Wait_Mode \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)\r
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)\r
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
+ ((MODE) == SDIO_ReadWaitMode_DATA2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void SDIO_DeInit(void);\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_ClockCmd(FunctionalState NewState);\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
+uint32_t SDIO_GetPowerState(void);\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
+void SDIO_DMACmd(FunctionalState NewState);\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
+uint8_t SDIO_GetCommandResponse(void);\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+uint32_t SDIO_GetDataCounter(void);\r
+uint32_t SDIO_ReadData(void);\r
+void SDIO_WriteData(uint32_t Data);\r
+uint32_t SDIO_GetFIFOCount(void);\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
+void SDIO_SetSDIOOperation(FunctionalState NewState);\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
+void SDIO_CEATAITCmd(FunctionalState NewState);\r
+void SDIO_SendCEATACmd(FunctionalState NewState);\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_SDIO_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_spi.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the SPI firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SPI_H\r
+#define __STM32F10x_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SPI_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+ This parameter can be a value of @ref SPI_data_direction */\r
+\r
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be a value of @ref SPI_mode */\r
+\r
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be a value of @ref SPI_data_size */\r
+\r
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
+ This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be a value of @ref SPI_Slave_Select_management */\r
+ \r
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+/** \r
+ * @brief I2S Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
+ This parameter can be a value of @ref I2S_Mode */\r
+\r
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Standard */\r
+\r
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Data_Format */\r
+\r
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
+ This parameter can be a value of @ref I2S_MCLK_Output */\r
+\r
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Audio_Frequency */\r
+\r
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
+ This parameter can be a value of @ref I2S_Clock_Polarity */\r
+}I2S_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+\r
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+\r
+/** @defgroup SPI_data_direction \r
+ * @{\r
+ */\r
+ \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_mode \r
+ * @{\r
+ */\r
+\r
+#define SPI_Mode_Master ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_data_size \r
+ * @{\r
+ */\r
+\r
+#define SPI_DataSize_16b ((uint16_t)0x0800)\r
+#define SPI_DataSize_8b ((uint16_t)0x0000)\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+ ((DATASIZE) == SPI_DataSize_8b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPOL_Low ((uint16_t)0x0000)\r
+#define SPI_CPOL_High ((uint16_t)0x0002)\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSS_Soft ((uint16_t)0x0200)\r
+#define SPI_NSS_Hard ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+ * @{\r
+ */\r
+\r
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Mode \r
+ * @{\r
+ */\r
+\r
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
+ ((MODE) == I2S_Mode_SlaveRx) || \\r
+ ((MODE) == I2S_Mode_MasterTx) || \\r
+ ((MODE) == I2S_Mode_MasterRx) )\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Standard \r
+ * @{\r
+ */\r
+\r
+#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
+#define I2S_Standard_MSB ((uint16_t)0x0010)\r
+#define I2S_Standard_LSB ((uint16_t)0x0020)\r
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
+ ((STANDARD) == I2S_Standard_MSB) || \\r
+ ((STANDARD) == I2S_Standard_LSB) || \\r
+ ((STANDARD) == I2S_Standard_PCMShort) || \\r
+ ((STANDARD) == I2S_Standard_PCMLong))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Data_Format \r
+ * @{\r
+ */\r
+\r
+#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
+#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
+#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
+ ((FORMAT) == I2S_DataFormat_16bextended) || \\r
+ ((FORMAT) == I2S_DataFormat_24b) || \\r
+ ((FORMAT) == I2S_DataFormat_32b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2S_MCLK_Output \r
+ * @{\r
+ */\r
+\r
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
+ ((OUTPUT) == I2S_MCLKOutput_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Audio_Frequency \r
+ * @{\r
+ */\r
+\r
+#define I2S_AudioFreq_192k ((uint32_t)192000)\r
+#define I2S_AudioFreq_96k ((uint32_t)96000)\r
+#define I2S_AudioFreq_48k ((uint32_t)48000)\r
+#define I2S_AudioFreq_44k ((uint32_t)44100)\r
+#define I2S_AudioFreq_32k ((uint32_t)32000)\r
+#define I2S_AudioFreq_22k ((uint32_t)22050)\r
+#define I2S_AudioFreq_16k ((uint32_t)16000)\r
+#define I2S_AudioFreq_11k ((uint32_t)11025)\r
+#define I2S_AudioFreq_8k ((uint32_t)8000)\r
+#define I2S_AudioFreq_Default ((uint32_t)2)\r
+\r
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\r
+ ((FREQ) <= I2S_AudioFreq_192k)) || \\r
+ ((FREQ) == I2S_AudioFreq_Default))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2S_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define I2S_CPOL_Low ((uint16_t)0x0000)\r
+#define I2S_CPOL_High ((uint16_t)0x0008)\r
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
+ ((CPOL) == I2S_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSS_internal_software_mangement \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_CRC_Tx ((uint8_t)0x00)\r
+#define SPI_CRC_Rx ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
+#define SPI_IT_MODF ((uint8_t)0x55)\r
+#define SPI_IT_CRCERR ((uint8_t)0x54)\r
+#define I2S_IT_UDR ((uint8_t)0x53)\r
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \\r
+ ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r
+#define I2S_FLAG_UDR ((uint16_t)0x0008)\r
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
+#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_SPI_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_tim.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the TIM firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TIM_H\r
+#define __STM32F10x_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup TIM_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition\r
+ * @note This sturcture is used with all TIMx except for TIM6 and TIM7. \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ This parameter must be a number between 0x00 and 0xFF. \r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_state\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/** \r
+ * @brief BDTR structure definition \r
+ * @note This sturcture is used only with TIM1 and TIM8. \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */\r
+\r
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */\r
+\r
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r
+ This parameter can be a value of @ref Lock_level */ \r
+\r
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r
+ switching-on of the outputs.\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r
+ This parameter can be a value of @ref Break_Input_enable_disable */\r
+\r
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r
+ This parameter can be a value of @ref Break_Polarity */\r
+\r
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BDTRInitTypeDef;\r
+\r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10)|| \\r
+ ((PERIPH) == TIM11)|| \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM13)|| \\r
+ ((PERIPH) == TIM14)|| \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST1: TIM 1 and 8 */\r
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM8))\r
+\r
+/* LIST2: TIM 1, 8, 15 16 and 17 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17)) \r
+\r
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8)) \r
+ \r
+/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ \r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)) \r
+\r
+/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */\r
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM15))\r
+\r
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */\r
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM15)) \r
+\r
+/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ \r
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10)|| \\r
+ ((PERIPH) == TIM11)|| \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM13)|| \\r
+ ((PERIPH) == TIM14)|| \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */\r
+#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17)) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
+ ((POLARITY) == TIM_OCNPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
+ ((STATE) == TIM_OutputNState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCxN_Enable ((uint16_t)0x0004)\r
+#define TIM_CCxN_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
+ ((CCXN) == TIM_CCxN_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Break_Input_enable_disable \r
+ * @{\r
+ */\r
+\r
+#define TIM_Break_Enable ((uint16_t)0x1000)\r
+#define TIM_Break_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
+ ((STATE) == TIM_Break_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Break_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
+ ((POLARITY) == TIM_BreakPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset \r
+ * @{\r
+ */\r
+\r
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
+ ((STATE) == TIM_AutomaticOutput_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Lock_level \r
+ * @{\r
+ */\r
+\r
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
+ ((LEVEL) == TIM_LOCKLevel_1) || \\r
+ ((LEVEL) == TIM_LOCKLevel_2) || \\r
+ ((LEVEL) == TIM_LOCKLevel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
+ ((STATE) == TIM_OSSIState_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
+ ((STATE) == TIM_OSSRState_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
+ ((STATE) == TIM_OCIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
+ ((STATE) == TIM_OCNIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling))\r
+#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+ ((POLARITY) == TIM_ICPolarity_BothEdge)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_COM ((uint16_t)0x0020)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define TIM_IT_Break ((uint16_t)0x0080)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_COM) || \\r
+ ((IT) == TIM_IT_Trigger) || \\r
+ ((IT) == TIM_IT_Break))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_RCR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_BDTR) || \\r
+ ((BASE) == TIM_DMABase_DCR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_COM ((uint16_t)0x2000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_COM ((uint16_t)0x0020)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define TIM_EventSource_Break ((uint16_t)0x0080)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_COM ((uint16_t)0x0020)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_Break ((uint16_t)0x0080)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_COM) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_Break) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+ \r
+ \r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_TIM_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_usart.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the USART \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_USART_H\r
+#define __STM32F10x_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief USART Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
+\r
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USART_Word_Length */\r
+\r
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint16_t USART_Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+ * @brief USART Clock Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+\r
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Clock */\r
+\r
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3) || \\r
+ ((PERIPH) == UART4) || \\r
+ ((PERIPH) == UART5))\r
+\r
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3))\r
+\r
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3) || \\r
+ ((PERIPH) == UART4))\r
+/** @defgroup USART_Word_Length \r
+ * @{\r
+ */ \r
+ \r
+#define USART_WordLength_8b ((uint16_t)0x0000)\r
+#define USART_WordLength_9b ((uint16_t)0x1000)\r
+ \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+ * @{\r
+ */ \r
+ \r
+#define USART_StopBits_1 ((uint16_t)0x0000)\r
+#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
+#define USART_StopBits_2 ((uint16_t)0x2000)\r
+#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_0_5) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Parity \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Parity_No ((uint16_t)0x0000)\r
+#define USART_Parity_Even ((uint16_t)0x0400)\r
+#define USART_Parity_Odd ((uint16_t)0x0600) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Mode \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Mode_Rx ((uint16_t)0x0004)\r
+#define USART_Mode_Tx ((uint16_t)0x0008)\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+ * @{\r
+ */ \r
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock \r
+ * @{\r
+ */ \r
+#define USART_Clock_Disable ((uint16_t)0x0000)\r
+#define USART_Clock_Enable ((uint16_t)0x0800)\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define USART_CPOL_Low ((uint16_t)0x0000)\r
+#define USART_CPOL_High ((uint16_t)0x0400)\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+ * @{\r
+ */\r
+\r
+#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
+#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit\r
+ * @{\r
+ */\r
+\r
+#define USART_LastBit_Disable ((uint16_t)0x0000)\r
+#define USART_LastBit_Enable ((uint16_t)0x0100)\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+ * @{\r
+ */\r
+ \r
+#define USART_IT_PE ((uint16_t)0x0028)\r
+#define USART_IT_TXE ((uint16_t)0x0727)\r
+#define USART_IT_TC ((uint16_t)0x0626)\r
+#define USART_IT_RXNE ((uint16_t)0x0525)\r
+#define USART_IT_IDLE ((uint16_t)0x0424)\r
+#define USART_IT_LBD ((uint16_t)0x0846)\r
+#define USART_IT_CTS ((uint16_t)0x096A)\r
+#define USART_IT_ERR ((uint16_t)0x0060)\r
+#define USART_IT_ORE ((uint16_t)0x0360)\r
+#define USART_IT_NE ((uint16_t)0x0260)\r
+#define USART_IT_FE ((uint16_t)0x0160)\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_DMA_Requests \r
+ * @{\r
+ */\r
+\r
+#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
+#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_WakeUp_methods\r
+ * @{\r
+ */\r
+\r
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+ * @{\r
+ */\r
+ \r
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Flags \r
+ * @{\r
+ */\r
+\r
+#define USART_FLAG_CTS ((uint16_t)0x0200)\r
+#define USART_FLAG_LBD ((uint16_t)0x0100)\r
+#define USART_FLAG_TXE ((uint16_t)0x0080)\r
+#define USART_FLAG_TC ((uint16_t)0x0040)\r
+#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
+#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
+#define USART_FLAG_ORE ((uint16_t)0x0008)\r
+#define USART_FLAG_NE ((uint16_t)0x0004)\r
+#define USART_FLAG_FE ((uint16_t)0x0002)\r
+#define USART_FLAG_PE ((uint16_t)0x0001)\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\\r
+ ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \\r
+ || ((USART_FLAG) != USART_FLAG_CTS)) \r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_USART_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the WWDG firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_WWDG_H\r
+#define __STM32F10x_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Types\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup WWDG_Prescaler \r
+ * @{\r
+ */ \r
+ \r
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Functions\r
+ * @{\r
+ */ \r
+ \r
+void WWDG_DeInit(void);\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+void WWDG_Enable(uint8_t Counter);\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file misc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the miscellaneous firmware functions (add-on\r
+ * to CMSIS functions).\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "misc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC \r
+ * @brief MISC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup MISC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup MISC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup MISC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
+ * 4 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
+ * 3 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
+ * 2 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
+ * 1 bits for subpriority\r
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
+ * 0 bits for subpriority\r
+ * @retval None\r
+ */\r
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
+ \r
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the NVIC peripheral according to the specified\r
+ * parameters in the NVIC_InitStruct.\r
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
+ * the configuration information for the specified NVIC peripheral.\r
+ * @retval None\r
+ */\r
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
+{\r
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
+ \r
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
+ {\r
+ /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
+ tmppre = (0x4 - tmppriority);\r
+ tmpsub = tmpsub >> tmppriority;\r
+\r
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
+ tmppriority = tmppriority << 0x04;\r
+ \r
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
+ \r
+ /* Enable the Selected IRQ Channels --------------------------------------*/\r
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Selected IRQ Channels -------------------------------------*/\r
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the vector table location and Offset.\r
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_VectTab_RAM\r
+ * @arg NVIC_VectTab_FLASH\r
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.\r
+ * @retval None\r
+ */\r
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
+ assert_param(IS_NVIC_OFFSET(Offset)); \r
+ \r
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
+}\r
+\r
+/**\r
+ * @brief Selects the condition for the system to enter low power mode.\r
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg NVIC_LP_SEVONPEND\r
+ * @arg NVIC_LP_SLEEPDEEP\r
+ * @arg NVIC_LP_SLEEPONEXIT\r
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_NVIC_LP(LowPowerMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ SCB->SCR |= LowPowerMode;\r
+ }\r
+ else\r
+ {\r
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the SysTick clock source.\r
+ * @param SysTick_CLKSource: specifies the SysTick clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
+ * @retval None\r
+ */\r
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
+ {\r
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
+ }\r
+ else\r
+ {\r
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_adc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the ADC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_adc.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC \r
+ * @brief ADC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)\r
+\r
+/* ADC DISCEN mask */\r
+#define CR1_DISCEN_Set ((uint32_t)0x00000800)\r
+#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)\r
+\r
+/* ADC JAUTO mask */\r
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)\r
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)\r
+\r
+/* ADC JDISCEN mask */\r
+#define CR1_JDISCEN_Set ((uint32_t)0x00001000)\r
+#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)\r
+\r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)\r
+\r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)\r
+\r
+/* CR1 register Mask */\r
+#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)\r
+\r
+/* ADC ADON mask */\r
+#define CR2_ADON_Set ((uint32_t)0x00000001)\r
+#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)\r
+\r
+/* ADC DMA mask */\r
+#define CR2_DMA_Set ((uint32_t)0x00000100)\r
+#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)\r
+\r
+/* ADC RSTCAL mask */\r
+#define CR2_RSTCAL_Set ((uint32_t)0x00000008)\r
+\r
+/* ADC CAL mask */\r
+#define CR2_CAL_Set ((uint32_t)0x00000004)\r
+\r
+/* ADC SWSTART mask */\r
+#define CR2_SWSTART_Set ((uint32_t)0x00400000)\r
+\r
+/* ADC EXTTRIG mask */\r
+#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)\r
+#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)\r
+\r
+/* ADC Software start mask */\r
+#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)\r
+#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)\r
+\r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)\r
+\r
+/* ADC JEXTTRIG mask */\r
+#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)\r
+#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)\r
+\r
+/* ADC JSWSTART mask */\r
+#define CR2_JSWSTART_Set ((uint32_t)0x00200000)\r
+\r
+/* ADC injected software start mask */\r
+#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)\r
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)\r
+\r
+/* ADC TSPD mask */\r
+#define CR2_TSVREFE_Set ((uint32_t)0x00800000)\r
+#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)\r
+\r
+/* CR2 register Mask */\r
+#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)\r
+\r
+/* ADC SQx mask */\r
+#define SQR3_SQ_Set ((uint32_t)0x0000001F)\r
+#define SQR2_SQ_Set ((uint32_t)0x0000001F)\r
+#define SQR1_SQ_Set ((uint32_t)0x0000001F)\r
+\r
+/* SQR1 register Mask */\r
+#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)\r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_Set ((uint32_t)0x0000001F)\r
+\r
+/* ADC JL mask */\r
+#define JSQR_JL_Set ((uint32_t)0x00300000)\r
+#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)\r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_Set ((uint32_t)0x00000007)\r
+#define SMPR2_SMP_Set ((uint32_t)0x00000007)\r
+\r
+/* ADC JDRx registers offset */\r
+#define JDR_Offset ((uint8_t)0x28)\r
+\r
+/* ADC1 DR register base address */\r
+#define DR_ADDRESS ((uint32_t)0x4001244C)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ if (ADCx == ADC1)\r
+ {\r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+ }\r
+ else if (ADCx == ADC2)\r
+ {\r
+ /* Enable ADC2 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);\r
+ /* Release ADC2 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (ADCx == ADC3)\r
+ {\r
+ /* Enable ADC3 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);\r
+ /* Release ADC3 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters\r
+ * in the ADC_InitStruct.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains\r
+ * the configuration information for the specified ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint8_t tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));\r
+\r
+ /*---------------------------- ADCx CR1 Configuration -----------------*/\r
+ /* Get the ADCx CR1 value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear DUALMOD and SCAN bits */\r
+ tmpreg1 &= CR1_CLEAR_Mask;\r
+ /* Configure ADCx: Dual mode and scan conversion mode */\r
+ /* Set DUALMOD bits according to ADC_Mode value */\r
+ /* Set SCAN bit according to ADC_ScanConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));\r
+ /* Write to ADCx CR1 */\r
+ ADCx->CR1 = tmpreg1;\r
+\r
+ /*---------------------------- ADCx CR2 Configuration -----------------*/\r
+ /* Get the ADCx CR2 value */\r
+ tmpreg1 = ADCx->CR2;\r
+ /* Clear CONT, ALIGN and EXTSEL bits */\r
+ tmpreg1 &= CR2_CLEAR_Mask;\r
+ /* Configure ADCx: external trigger event and continuous conversion mode */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |\r
+ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
+ /* Write to ADCx CR2 */\r
+ ADCx->CR2 = tmpreg1;\r
+\r
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
+ /* Get the ADCx SQR1 value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Clear L bits */\r
+ tmpreg1 &= SQR1_CLEAR_Mask;\r
+ /* Configure ADCx: regular channel sequence length */\r
+ /* Set L bits according to ADC_NbrOfChannel value */\r
+ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);\r
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;\r
+ /* Write to ADCx SQR1 */\r
+ ADCx->SQR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_InitStruct member with its default value.\r
+ * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Mode member */\r
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;\r
+ /* initialize the ADC_ScanConvMode member */\r
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+ /* Initialize the ADC_NbrOfChannel member */\r
+ ADC_InitStruct->ADC_NbrOfChannel = 1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC peripheral.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the ADCx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADON bit to wake up the ADC from power down mode */\r
+ ADCx->CR2 |= CR2_ADON_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC peripheral */\r
+ ADCx->CR2 &= CR2_ADON_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC DMA request.\r
+ * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.\r
+ * Note: ADC2 hasn't a DMA capability.\r
+ * @param NewState: new state of the selected ADC DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CR2 |= CR2_DMA_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CR2 &= CR2_DMA_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC interrupts.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt mask\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
+ * @param NewState: new state of the specified ADC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)\r
+{\r
+ uint8_t itmask = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)ADC_IT;\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->CR1 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->CR1 &= (~(uint32_t)itmask);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Resets the selected ADC calibration registers.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Resets the selected ADC calibartion registers */ \r
+ ADCx->CR2 |= CR2_RSTCAL_Set;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC reset calibration registers status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC reset calibration registers (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of RSTCAL bit */\r
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)\r
+ {\r
+ /* RSTCAL bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* RSTCAL bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RSTCAL bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Starts the selected ADC calibration process.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_StartCalibration(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Enable the selected ADC calibration process */ \r
+ ADCx->CR2 |= CR2_CAL_Set;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC calibration status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC calibration (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of CAL bit */\r
+ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)\r
+ {\r
+ /* CAL bit is set: calibration on going */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAL bit is reset: end of calibration */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CAL bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC software start conversion .\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC software start conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion on external event and start the selected\r
+ ADC conversion */\r
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC conversion on external event and stop the selected\r
+ ADC conversion */\r
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start conversion Status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC software start conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of SWSTART bit */\r
+ if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)\r
+ {\r
+ /* SWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Configures the discontinuous mode for the selected ADC regular\r
+ * group channel.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param Number: specifies the discontinuous mode regular channel\r
+ * count value. This number must be between 1 and 8.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= CR1_DISCNUM_Reset;\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg2 = Number - 1;\r
+ tmpreg1 |= tmpreg2 << 13;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode on regular group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on regular group channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 |= CR1_DISCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 &= CR1_DISCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
+ * @retval None\r
+ */\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
+ if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ /* For Rank 1 to 6 */\r
+ if (Rank < 7)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR3 = tmpreg1;\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (Rank < 13)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR2 = tmpreg1;\r
+ }\r
+ /* For Rank 13 to 16 */\r
+ else\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR1 = tmpreg1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADCx conversion through external trigger.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC external trigger start of conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion on external event */\r
+ ADCx->CR2 |= CR2_EXTTRIG_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC conversion on external event */\r
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADCx conversion result data for regular channel.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Return the selected ADC conversion value */\r
+ return (uint16_t) ADCx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint32_t ADC_GetDualModeConversionValue(void)\r
+{\r
+ /* Return the dual mode conversion value */\r
+ return (*(__IO uint32_t *) DR_ADDRESS);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC automatic injected group\r
+ * conversion after regular one.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC auto injected conversion\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 |= CR1_JAUTO_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 &= CR1_JAUTO_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode for injected group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on injected group channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 |= CR1_JDISCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 &= CR1_JDISCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger for injected channels conversion.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)\r
+ * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)\r
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8\r
+ * capture compare4 event selected (for ADC1 and ADC2) \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)\r
+ * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) \r
+ * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)\r
+ * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) \r
+ * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) \r
+ * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not\r
+ * by external trigger (for ADC1, ADC2 and ADC3)\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external event selection for injected group */\r
+ tmpreg &= CR2_JEXTSEL_Reset;\r
+ /* Set the external event selection for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConv;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADCx injected channels conversion through\r
+ * external trigger\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC external trigger start of\r
+ * injected conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC external event selection for injected group */\r
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC external event selection for injected group */\r
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC start of the injected \r
+ * channels conversion.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC software start injected conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion for injected group on external event and start the selected\r
+ ADC injected conversion */\r
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected\r
+ ADC injected conversion */\r
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start injected conversion Status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC software start injected conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of JSWSTART bit */\r
+ if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)\r
+ {\r
+ /* JSWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* JSWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the JSWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
+ * @retval None\r
+ */\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_INJECTED_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
+ if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ /* Rank configuration */\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Get JL value: Number = JL+1 */\r
+ tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;\r
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */\r
+ tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Clear the old JSQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Set the JSQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the sequencer length for injected channels\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param Length: The sequencer length. \r
+ * This parameter must be a number between 1 to 4.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Clear the old injected sequnence lenght JL bits */\r
+ tmpreg1 &= JSQR_JL_Reset;\r
+ /* Set the injected sequnence lenght JL bits */\r
+ tmpreg2 = Length - 1; \r
+ tmpreg1 |= tmpreg2 << 20;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Set the injected channels conversion value offset\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @param Offset: the offset value for the selected ADC injected channel\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+ assert_param(IS_ADC_OFFSET(Offset)); \r
+ \r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel;\r
+ \r
+ /* Set the selected injected channel data offset */\r
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
+}\r
+\r
+/**\r
+ * @brief Returns the ADC injected channel conversion result\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_InjectedChannel: the converted ADC injected channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+\r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel + JDR_Offset;\r
+ \r
+ /* Returns the selected injected channel conversion data value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp); \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the analog watchdog on single/all regular\r
+ * or injected channels\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel\r
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel\r
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel\r
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel\r
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel\r
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels\r
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
+ * @retval None \r
+ */\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */\r
+ tmpreg &= CR1_AWDMode_Reset;\r
+ /* Set the analog watchdog enable mode */\r
+ tmpreg |= ADC_AnalogWatchdog;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the high and low thresholds of the analog watchdog.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param HighThreshold: the ADC analog watchdog High threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
+ uint16_t LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
+ /* Set the ADCx high threshold */\r
+ ADCx->HTR = HighThreshold;\r
+ /* Set the ADCx low threshold */\r
+ ADCx->LTR = LowThreshold;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog guarded single channel\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= CR1_AWDCH_Reset;\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_Channel;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the temperature sensor and Vrefint channel.\r
+ * @param NewState: new state of the temperature sensor.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor and Vrefint channel*/\r
+ ADC1->CR2 |= CR2_TSVREFE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor and Vrefint channel*/\r
+ ADC1->CR2 &= CR2_TSVREFE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC flag is set or not.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @retval The new state of ADC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
+ /* Check the status of the specified ADC flag */\r
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's pending flags.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @retval None\r
+ */\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+ /* Clear the selected ADC flags */\r
+ ADCx->SR = ~(uint32_t)ADC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC interrupt has occurred or not.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt mask\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
+ * @retval The new state of ADC_IT (SET or RESET).\r
+ */\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t itmask = 0, enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_IT(ADC_IT));\r
+ /* Get the ADC IT index */\r
+ itmask = ADC_IT >> 8;\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx\92s interrupt pending bits.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt mask\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
+ * @retval None\r
+ */\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ uint8_t itmask = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)(ADC_IT >> 8);\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->SR = ~(uint32_t)itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_bkp.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the BKP firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_bkp.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup BKP \r
+ * @brief BKP driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup BKP_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ BKP registers bit address in the alias region --------------- */\r
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ----*/\r
+\r
+/* Alias word address of TPAL bit */\r
+#define CR_OFFSET (BKP_OFFSET + 0x30)\r
+#define TPAL_BitNumber 0x01\r
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))\r
+\r
+/* Alias word address of TPE bit */\r
+#define TPE_BitNumber 0x00\r
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of TPIE bit */\r
+#define CSR_OFFSET (BKP_OFFSET + 0x34)\r
+#define TPIE_BitNumber 0x02\r
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))\r
+\r
+/* Alias word address of TIF bit */\r
+#define TIF_BitNumber 0x09\r
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))\r
+\r
+/* Alias word address of TEF bit */\r
+#define TEF_BitNumber 0x08\r
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))\r
+\r
+/* ---------------------- BKP registers bit mask ------------------------ */\r
+\r
+/* RTCCR register bit mask */\r
+#define RTCCR_CAL_MASK ((uint16_t)0xFF80)\r
+#define RTCCR_MASK ((uint16_t)0xFC7F)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup BKP_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the BKP peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BKP_DeInit(void)\r
+{\r
+ RCC_BackupResetCmd(ENABLE);\r
+ RCC_BackupResetCmd(DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Configures the Tamper Pin active level.\r
+ * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.\r
+ * This parameter can be one of the following values:\r
+ * @arg BKP_TamperPinLevel_High: Tamper pin active on high level\r
+ * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level\r
+ * @retval None\r
+ */\r
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));\r
+ *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Tamper Pin activation.\r
+ * @param NewState: new state of the Tamper Pin activation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void BKP_TamperPinCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Tamper Pin Interrupt.\r
+ * @param NewState: new state of the Tamper Pin Interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void BKP_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Select the RTC output source to output on the Tamper pin.\r
+ * @param BKP_RTCOutputSource: specifies the RTC output source.\r
+ * This parameter can be one of the following values:\r
+ * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.\r
+ * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency\r
+ * divided by 64 on the Tamper pin.\r
+ * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on\r
+ * the Tamper pin.\r
+ * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on\r
+ * the Tamper pin. \r
+ * @retval None\r
+ */\r
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));\r
+ tmpreg = BKP->RTCCR;\r
+ /* Clear CCO, ASOE and ASOS bits */\r
+ tmpreg &= RTCCR_MASK;\r
+ \r
+ /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */\r
+ tmpreg |= BKP_RTCOutputSource;\r
+ /* Store the new value */\r
+ BKP->RTCCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets RTC Clock Calibration value.\r
+ * @param CalibrationValue: specifies the RTC Clock Calibration value.\r
+ * This parameter must be a number between 0 and 0x7F.\r
+ * @retval None\r
+ */\r
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));\r
+ tmpreg = BKP->RTCCR;\r
+ /* Clear CAL[6:0] bits */\r
+ tmpreg &= RTCCR_CAL_MASK;\r
+ /* Set CAL[6:0] bits according to CalibrationValue value */\r
+ tmpreg |= CalibrationValue;\r
+ /* Store the new value */\r
+ BKP->RTCCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Writes user data to the specified Data Backup Register.\r
+ * @param BKP_DR: specifies the Data Backup Register.\r
+ * This parameter can be BKP_DRx where x:[1, 42]\r
+ * @param Data: data to write\r
+ * @retval None\r
+ */\r
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_DR(BKP_DR));\r
+\r
+ tmp = (uint32_t)BKP_BASE; \r
+ tmp += BKP_DR;\r
+\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified Data Backup Register.\r
+ * @param BKP_DR: specifies the Data Backup Register.\r
+ * This parameter can be BKP_DRx where x:[1, 42]\r
+ * @retval The content of the specified Data Backup Register\r
+ */\r
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_DR(BKP_DR));\r
+\r
+ tmp = (uint32_t)BKP_BASE; \r
+ tmp += BKP_DR;\r
+\r
+ return (*(__IO uint16_t *) tmp);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the Tamper Pin Event flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Tamper Pin Event flag (SET or RESET).\r
+ */\r
+FlagStatus BKP_GetFlagStatus(void)\r
+{\r
+ return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);\r
+}\r
+\r
+/**\r
+ * @brief Clears Tamper Pin Event pending flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BKP_ClearFlag(void)\r
+{\r
+ /* Set CTE bit to clear Tamper Pin Event flag */\r
+ BKP->CSR |= BKP_CSR_CTE;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the Tamper Pin Interrupt has occurred or not.\r
+ * @param None\r
+ * @retval The new state of the Tamper Pin Interrupt (SET or RESET).\r
+ */\r
+ITStatus BKP_GetITStatus(void)\r
+{\r
+ return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);\r
+}\r
+\r
+/**\r
+ * @brief Clears Tamper Pin Interrupt pending bit.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BKP_ClearITPendingBit(void)\r
+{\r
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */\r
+ BKP->CSR |= BKP_CSR_CTI;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_can.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the CAN firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_can.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN \r
+ * @brief CAN driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup CAN_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* CAN Master Control Register bits */\r
+\r
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */\r
+\r
+/* CAN Mailbox Transmit Request */\r
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */\r
+\r
+/* CAN Filter Master Register bits */\r
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */\r
+\r
+/* Time out for INAK bit */\r
+#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)\r
+/* Time out for SLAK bit */\r
+#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)\r
+\r
+\r
+\r
+/* Flags in TSR register */\r
+#define CAN_FLAGS_TSR ((uint32_t)0x08000000) \r
+/* Flags in RF1R register */\r
+#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) \r
+/* Flags in RF0R register */\r
+#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) \r
+/* Flags in MSR register */\r
+#define CAN_FLAGS_MSR ((uint32_t)0x01000000) \r
+/* Flags in ESR register */\r
+#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.\r
+ * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r
+ * @retval None.\r
+ */\r
+void CAN_DeInit(CAN_TypeDef* CANx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ if (CANx == CAN1)\r
+ {\r
+ /* Enable CAN1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);\r
+ /* Release CAN1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);\r
+ }\r
+ else\r
+ { \r
+ /* Enable CAN2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);\r
+ /* Release CAN2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_InitStruct.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
+ * contains the configuration information for the CAN peripheral.\r
+ * @retval Constant indicates initialization succeed which will be \r
+ * CANINITFAILED or CANINITOK.\r
+ */\r
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ uint8_t InitStatus = CANINITFAILED;\r
+ uint32_t wait_ack = 0x00000000;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r
+\r
+ /* exit from sleep mode */\r
+ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r
+\r
+ /* Request initialisation */\r
+ CANx->MCR |= CAN_MCR_INRQ ;\r
+\r
+ /* Wait the acknowledge */\r
+ while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r
+ {\r
+ wait_ack++;\r
+ }\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else \r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (CAN_InitStruct->CAN_NART == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |\r
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |\r
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);\r
+\r
+ /* Request leave initialisation */\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r
+\r
+ /* Wait the acknowledge */\r
+ wait_ack = 0x00;\r
+\r
+ while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r
+ {\r
+ wait_ack++;\r
+ }\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else\r
+ {\r
+ InitStatus = CANINITOK ;\r
+ }\r
+ }\r
+\r
+ /* At this step, return the status of initialization */\r
+ return InitStatus;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_FilterInitStruct.\r
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef\r
+ * structure that contains the configuration information.\r
+ * @retval None.\r
+ */\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r
+{\r
+ uint32_t filter_number_bit_pos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r
+\r
+ filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;\r
+\r
+ /* Initialisation mode for the filter */\r
+ CAN1->FMR |= FMR_FINIT;\r
+\r
+ /* Filter Deactivation */\r
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;\r
+\r
+ /* Filter Scale */\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);\r
+ }\r
+\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ CAN1->FS1R |= filter_number_bit_pos;\r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;\r
+ }\r
+\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r
+ {\r
+ CAN1->FA1R |= filter_number_bit_pos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ CAN1->FMR &= ~FMR_FINIT;\r
+}\r
+\r
+/**\r
+ * @brief Fills each CAN_InitStruct member with its default value.\r
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None.\r
+ */\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ /* Reset CAN init structure parameters values */\r
+ /* Initialize the time triggered communication mode */\r
+ CAN_InitStruct->CAN_TTCM = DISABLE;\r
+ /* Initialize the automatic bus-off management */\r
+ CAN_InitStruct->CAN_ABOM = DISABLE;\r
+ /* Initialize the automatic wake-up mode */\r
+ CAN_InitStruct->CAN_AWUM = DISABLE;\r
+ /* Initialize the no automatic retransmission */\r
+ CAN_InitStruct->CAN_NART = DISABLE;\r
+ /* Initialize the receive FIFO locked mode */\r
+ CAN_InitStruct->CAN_RFLM = DISABLE;\r
+ /* Initialize the transmit FIFO priority */\r
+ CAN_InitStruct->CAN_TXFP = DISABLE;\r
+ /* Initialize the CAN_Mode member */\r
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r
+ /* Initialize the CAN_SJW member */\r
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;\r
+ /* Initialize the CAN_BS1 member */\r
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r
+ /* Initialize the CAN_BS2 member */\r
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r
+ /* Initialize the CAN_Prescaler member */\r
+ CAN_InitStruct->CAN_Prescaler = 1;\r
+}\r
+\r
+/**\r
+ * @brief Select the start bank filter for slave CAN.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.\r
+ * @retval None.\r
+ */\r
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));\r
+ /* enter Initialisation mode for the filter */\r
+ CAN1->FMR |= FMR_FINIT;\r
+ /* Select the start slave bank */\r
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;\r
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;\r
+ /* Leave Initialisation mode for the filter */\r
+ CAN1->FMR &= ~FMR_FINIT;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CANx interrupts.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.\r
+ * This parameter can be: \r
+ * -CAN_IT_TME, \r
+ * -CAN_IT_FMP0, \r
+ * -CAN_IT_FF0,\r
+ * -CAN_IT_FOV0, \r
+ * -CAN_IT_FMP1, \r
+ * -CAN_IT_FF1,\r
+ * -CAN_IT_FOV1, \r
+ * -CAN_IT_EWG, \r
+ * -CAN_IT_EPV,\r
+ * -CAN_IT_LEC, \r
+ * -CAN_IT_ERR, \r
+ * -CAN_IT_WKU or \r
+ * -CAN_IT_SLK.\r
+ * @param NewState: new state of the CAN interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_IT(CAN_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected CANx interrupt */\r
+ CANx->IER |= CAN_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected CANx interrupt */\r
+ CANx->IER &= ~CAN_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initiates the transmission of a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN\r
+ * DLC and CAN datas.\r
+ * @retval The number of the mailbox that is used for transmission\r
+ * or CAN_NO_MB if there is no empty mailbox.\r
+ */\r
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)\r
+{\r
+ uint8_t transmit_mailbox = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));\r
+ assert_param(IS_CAN_RTR(TxMessage->RTR));\r
+ assert_param(IS_CAN_DLC(TxMessage->DLC));\r
+\r
+ /* Select one empty transmit mailbox */\r
+ if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmit_mailbox = 0;\r
+ }\r
+ else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmit_mailbox = 1;\r
+ }\r
+ else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ transmit_mailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ transmit_mailbox = CAN_NO_MB;\r
+ }\r
+\r
+ if (transmit_mailbox != CAN_NO_MB)\r
+ {\r
+ /* Set up the Id */\r
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;\r
+ if (TxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(TxMessage->StdId)); \r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));\r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | \r
+ TxMessage->RTR);\r
+ }\r
+ \r
+\r
+ /* Set up the DLC */\r
+ TxMessage->DLC &= (uint8_t)0x0000000F;\r
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;\r
+\r
+ /* Set up the data field */\r
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | \r
+ ((uint32_t)TxMessage->Data[2] << 16) |\r
+ ((uint32_t)TxMessage->Data[1] << 8) | \r
+ ((uint32_t)TxMessage->Data[0]));\r
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | \r
+ ((uint32_t)TxMessage->Data[6] << 16) |\r
+ ((uint32_t)TxMessage->Data[5] << 8) |\r
+ ((uint32_t)TxMessage->Data[4]));\r
+ /* Request transmission */\r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;\r
+ }\r
+ return transmit_mailbox;\r
+}\r
+\r
+/**\r
+ * @brief Checks the transmission of a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param TransmitMailbox: the number of the mailbox that is used for transmission.\r
+ * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.\r
+ */\r
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)\r
+{\r
+ /* RQCP, TXOK and TME bits */\r
+ uint8_t state = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r
+ switch (TransmitMailbox)\r
+ {\r
+ case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26);\r
+ break;\r
+ case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27);\r
+ break;\r
+ case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28);\r
+ break;\r
+ default:\r
+ state = CANTXFAILED;\r
+ break;\r
+ }\r
+ switch (state)\r
+ {\r
+ /* transmit pending */\r
+ case (0x0): state = CANTXPENDING;\r
+ break;\r
+ /* transmit failed */\r
+ case (0x5): state = CANTXFAILED;\r
+ break;\r
+ /* transmit succedeed */\r
+ case (0x7): state = CANTXOK;\r
+ break;\r
+ default:\r
+ state = CANTXFAILED;\r
+ break;\r
+ }\r
+ return state;\r
+}\r
+\r
+/**\r
+ * @brief Cancels a transmit request.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
+ * @param Mailbox: Mailbox number.\r
+ * @retval None.\r
+ */\r
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));\r
+ /* abort transmission */\r
+ switch (Mailbox)\r
+ {\r
+ case (0): CANx->TSR |= CAN_TSR_ABRQ0;\r
+ break;\r
+ case (1): CANx->TSR |= CAN_TSR_ABRQ1;\r
+ break;\r
+ case (2): CANx->TSR |= CAN_TSR_ABRQ2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Releases a FIFO.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval None.\r
+ */\r
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ CANx->RF0R |= CAN_RF0R_RFOM0;\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ CANx->RF1R |= CAN_RF1R_RFOM1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of pending messages.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval NbMessage which is the number of pending message.\r
+ */\r
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
+{\r
+ uint8_t message_pending=0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);\r
+ }\r
+ else if (FIFONumber == CAN_FIFO1)\r
+ {\r
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);\r
+ }\r
+ else\r
+ {\r
+ message_pending = 0;\r
+ }\r
+ return message_pending;\r
+}\r
+\r
+/**\r
+ * @brief Receives a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @param RxMessage: pointer to a structure receive message which \r
+ * contains CAN Id, CAN DLC, CAN datas and FMI number.\r
+ * @retval None.\r
+ */\r
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ /* Get the Id */\r
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
+ if (RxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;\r
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;\r
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ /* Release the FIFO */\r
+ CAN_FIFORelease(CANx, FIFONumber);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DBG Freeze for CAN.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param NewState: new state of the CAN peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Debug Freeze */\r
+ CANx->MCR |= MCR_DBF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable Debug Freeze */\r
+ CANx->MCR &= ~MCR_DBF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the low power mode.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.\r
+ */\r
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)\r
+{\r
+ uint8_t sleepstatus = CANSLEEPFAILED;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ /* Request Sleep mode */\r
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
+ \r
+ /* Sleep mode status */\r
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode not entered */\r
+ sleepstatus = CANSLEEPOK;\r
+ }\r
+ /* At this step, sleep mode status */\r
+ return (uint8_t)sleepstatus;\r
+}\r
+\r
+/**\r
+ * @brief Wakes the CAN up.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.\r
+ */\r
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)\r
+{\r
+ uint32_t wait_slak = SLAK_TIMEOUT;\r
+ uint8_t wakeupstatus = CANWAKEUPFAILED;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ /* Wake up request */\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r
+ \r
+ /* Sleep mode status */\r
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))\r
+ {\r
+ wait_slak--;\r
+ }\r
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode exited */\r
+ wakeupstatus = CANWAKEUPOK;\r
+ }\r
+ /* At this step, sleep mode status */\r
+ return (uint8_t)wakeupstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CAN flag is set or not.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following flags: \r
+ * - CAN_FLAG_EWG\r
+ * - CAN_FLAG_EPV \r
+ * - CAN_FLAG_BOF\r
+ * - CAN_FLAG_RQCP0\r
+ * - CAN_FLAG_RQCP1\r
+ * - CAN_FLAG_RQCP2\r
+ * - CAN_FLAG_FMP1 \r
+ * - CAN_FLAG_FF1 \r
+ * - CAN_FLAG_FOV1 \r
+ * - CAN_FLAG_FMP0 \r
+ * - CAN_FLAG_FF0 \r
+ * - CAN_FLAG_FOV0 \r
+ * - CAN_FLAG_WKU \r
+ * - CAN_FLAG_SLAK \r
+ * - CAN_FLAG_LEC \r
+ * @retval The new state of CAN_FLAG (SET or RESET).\r
+ */\r
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));\r
+ \r
+\r
+ if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ /* Return the CAN_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CAN's pending flags.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following flags: \r
+ * - CAN_FLAG_RQCP0\r
+ * - CAN_FLAG_RQCP1\r
+ * - CAN_FLAG_RQCP2\r
+ * - CAN_FLAG_FF1 \r
+ * - CAN_FLAG_FOV1 \r
+ * - CAN_FLAG_FF0 \r
+ * - CAN_FLAG_FOV0 \r
+ * - CAN_FLAG_WKU \r
+ * - CAN_FLAG_SLAK \r
+ * - CAN_FLAG_LEC \r
+ * @retval None.\r
+ */\r
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
+{\r
+ uint32_t flagtmp=0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));\r
+ \r
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */\r
+ {\r
+ /* Clear the selected CAN flags */\r
+ CANx->ESR = (uint32_t)RESET;\r
+ }\r
+ else /* MSR or TSR or RF0R or RF1R */\r
+ {\r
+ flagtmp = CAN_FLAG & 0x000FFFFF;\r
+\r
+ if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)\r
+ {\r
+ /* Receive Flags */\r
+ CANx->RF0R = (uint32_t)(flagtmp);\r
+ }\r
+ else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)\r
+ {\r
+ /* Receive Flags */\r
+ CANx->RF1R = (uint32_t)(flagtmp);\r
+ }\r
+ else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)\r
+ {\r
+ /* Transmit Flags */\r
+ CANx->TSR = (uint32_t)(flagtmp);\r
+ }\r
+ else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */\r
+ {\r
+ /* Operating mode Flags */\r
+ CANx->MSR = (uint32_t)(flagtmp);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CANx interrupt has occurred or not.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the CAN interrupt source to check.\r
+ * This parameter can be one of the following flags: \r
+ * - CAN_IT_TME \r
+ * - CAN_IT_FMP0 \r
+ * - CAN_IT_FF0 \r
+ * - CAN_IT_FOV0 \r
+ * - CAN_IT_FMP1 \r
+ * - CAN_IT_FF1 \r
+ * - CAN_IT_FOV1 \r
+ * - CAN_IT_WKU \r
+ * - CAN_IT_SLK \r
+ * - CAN_IT_EWG \r
+ * - CAN_IT_EPV \r
+ * - CAN_IT_BOF \r
+ * - CAN_IT_LEC \r
+ * - CAN_IT_ERR \r
+ * @retval The current state of CAN_IT (SET or RESET).\r
+ */\r
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
+{\r
+ ITStatus itstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_IT(CAN_IT));\r
+ \r
+ /* check the enable interrupt bit */\r
+ if((CANx->IER & CAN_IT) != RESET)\r
+ {\r
+ /* in case the Interrupt is enabled, .... */\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_TME:\r
+ /* Check CAN_TSR_RQCPx bits */\r
+ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); \r
+ break;\r
+ case CAN_IT_FMP0:\r
+ /* Check CAN_RF0R_FMP0 bit */\r
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); \r
+ break;\r
+ case CAN_IT_FF0:\r
+ /* Check CAN_RF0R_FULL0 bit */\r
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); \r
+ break;\r
+ case CAN_IT_FOV0:\r
+ /* Check CAN_RF0R_FOVR0 bit */\r
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); \r
+ break;\r
+ case CAN_IT_FMP1:\r
+ /* Check CAN_RF1R_FMP1 bit */\r
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); \r
+ break;\r
+ case CAN_IT_FF1:\r
+ /* Check CAN_RF1R_FULL1 bit */\r
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); \r
+ break;\r
+ case CAN_IT_FOV1:\r
+ /* Check CAN_RF1R_FOVR1 bit */\r
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); \r
+ break;\r
+ case CAN_IT_WKU:\r
+ /* Check CAN_MSR_WKUI bit */\r
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); \r
+ break;\r
+ case CAN_IT_SLK:\r
+ /* Check CAN_MSR_SLAKI bit */\r
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); \r
+ break;\r
+ case CAN_IT_EWG:\r
+ /* Check CAN_ESR_EWGF bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); \r
+ break;\r
+ case CAN_IT_EPV:\r
+ /* Check CAN_ESR_EPVF bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); \r
+ break;\r
+ case CAN_IT_BOF:\r
+ /* Check CAN_ESR_BOFF bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); \r
+ break;\r
+ case CAN_IT_LEC:\r
+ /* Check CAN_ESR_LEC bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); \r
+ break;\r
+ case CAN_IT_ERR:\r
+ /* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC); \r
+ itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI); \r
+ break;\r
+ default :\r
+ /* in case of error, return RESET */\r
+ itstatus = RESET;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* in case the Interrupt is not enabled, return RESET */\r
+ itstatus = RESET;\r
+ }\r
+ \r
+ /* Return the CAN_IT status */\r
+ return itstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CANx\92s interrupt pending bits.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the interrupt pending bit to clear.\r
+ * - CAN_IT_TME \r
+ * - CAN_IT_FF0 \r
+ * - CAN_IT_FOV0 \r
+ * - CAN_IT_FF1 \r
+ * - CAN_IT_FOV1 \r
+ * - CAN_IT_WKU \r
+ * - CAN_IT_SLK \r
+ * - CAN_IT_EWG \r
+ * - CAN_IT_EPV \r
+ * - CAN_IT_BOF \r
+ * - CAN_IT_LEC \r
+ * - CAN_IT_ERR \r
+ * @retval None.\r
+ */\r
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_CLEAR_IT(CAN_IT));\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_TME:\r
+ /* Clear CAN_TSR_RQCPx (rc_w1)*/\r
+ CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; \r
+ break;\r
+ case CAN_IT_FF0:\r
+ /* Clear CAN_RF0R_FULL0 (rc_w1)*/\r
+ CANx->RF0R = CAN_RF0R_FULL0; \r
+ break;\r
+ case CAN_IT_FOV0:\r
+ /* Clear CAN_RF0R_FOVR0 (rc_w1)*/\r
+ CANx->RF0R = CAN_RF0R_FOVR0; \r
+ break;\r
+ case CAN_IT_FF1:\r
+ /* Clear CAN_RF1R_FULL1 (rc_w1)*/\r
+ CANx->RF1R = CAN_RF1R_FULL1; \r
+ break;\r
+ case CAN_IT_FOV1:\r
+ /* Clear CAN_RF1R_FOVR1 (rc_w1)*/\r
+ CANx->RF1R = CAN_RF1R_FOVR1; \r
+ break;\r
+ case CAN_IT_WKU:\r
+ /* Clear CAN_MSR_WKUI (rc_w1)*/\r
+ CANx->MSR = CAN_MSR_WKUI; \r
+ break;\r
+ case CAN_IT_SLK:\r
+ /* Clear CAN_MSR_SLAKI (rc_w1)*/ \r
+ CANx->MSR = CAN_MSR_SLAKI; \r
+ break;\r
+ case CAN_IT_EWG:\r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI;\r
+ /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ \r
+ break;\r
+ case CAN_IT_EPV:\r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/\r
+ break;\r
+ case CAN_IT_BOF:\r
+ /* Clear CAN_MSR_ERRI (rc_w1) */ \r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/\r
+ break;\r
+ case CAN_IT_LEC:\r
+ /* Clear LEC bits */\r
+ CANx->ESR = RESET; \r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ break;\r
+ case CAN_IT_ERR:\r
+ /*Clear LEC bits */\r
+ CANx->ESR = RESET; \r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/\r
+ break;\r
+ default :\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the CAN interrupt has occurred or not.\r
+ * @param CAN_Reg: specifies the CAN interrupt register to check.\r
+ * @param It_Bit: specifies the interrupt source bit to check.\r
+ * @retval The new state of the CAN Interrupt (SET or RESET).\r
+ */\r
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ \r
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)\r
+ {\r
+ /* CAN_IT is set */\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_IT is reset */\r
+ pendingbitstatus = RESET;\r
+ }\r
+ return pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_cec.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the CEC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_cec.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC \r
+ * @brief CEC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup CEC_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* ------------ CEC registers bit address in the alias region ----------- */\r
+#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)\r
+\r
+/* --- CFGR Register ---*/\r
+\r
+/* Alias word address of PE bit */\r
+#define CFGR_OFFSET (CEC_OFFSET + 0x00)\r
+#define PE_BitNumber 0x00\r
+#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))\r
+\r
+/* Alias word address of IE bit */\r
+#define IE_BitNumber 0x01\r
+#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of TSOM bit */\r
+#define CSR_OFFSET (CEC_OFFSET + 0x10)\r
+#define TSOM_BitNumber 0x00\r
+#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))\r
+\r
+/* Alias word address of TEOM bit */\r
+#define TEOM_BitNumber 0x01\r
+#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))\r
+ \r
+#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */\r
+#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Variables\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Deinitializes the CEC peripheral registers to their default reset \r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_DeInit(void)\r
+{\r
+ /* Enable CEC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); \r
+ /* Release CEC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the CEC peripheral according to the specified \r
+ * parameters in the CEC_InitStruct.\r
+ * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that\r
+ * contains the configuration information for the specified\r
+ * CEC peripheral.\r
+ * @retval None\r
+ */\r
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); \r
+ assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));\r
+ \r
+ /*---------------------------- CEC CFGR Configuration -----------------*/\r
+ /* Get the CEC CFGR value */\r
+ tmpreg = CEC->CFGR;\r
+ \r
+ /* Clear BTEM and BPEM bits */\r
+ tmpreg &= CFGR_CLEAR_Mask;\r
+ \r
+ /* Configure CEC: Bit Timing Error and Bit Period Error */\r
+ tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);\r
+\r
+ /* Write to CEC CFGR register*/\r
+ CEC->CFGR = tmpreg;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CEC peripheral.\r
+ * @param NewState: new state of the CEC peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;\r
+\r
+ if(NewState == DISABLE)\r
+ {\r
+ /* Wait until the PE bit is cleared by hardware (Idle Line detected) */\r
+ while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)\r
+ {\r
+ } \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CEC interrupt.\r
+ * @param NewState: new state of the CEC interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Defines the Own Address of the CEC device.\r
+ * @param CEC_OwnAddress: The CEC own address\r
+ * @retval None\r
+ */\r
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));\r
+\r
+ /* Set the CEC own address */\r
+ CEC->OAR = CEC_OwnAddress;\r
+}\r
+\r
+/**\r
+ * @brief Sets the CEC prescaler value.\r
+ * @param CEC_Prescaler: CEC prescaler new value\r
+ * @retval None\r
+ */\r
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_PRESCALER(CEC_Prescaler));\r
+\r
+ /* Set the Prescaler value*/\r
+ CEC->PRES = CEC_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Transmits single data through the CEC peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void CEC_SendDataByte(uint8_t Data)\r
+{ \r
+ /* Transmit Data */\r
+ CEC->TXD = Data ;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the CEC peripheral.\r
+ * @param None\r
+ * @retval The received data.\r
+ */\r
+uint8_t CEC_ReceiveDataByte(void)\r
+{\r
+ /* Receive Data */\r
+ return (uint8_t)(CEC->RXD);\r
+}\r
+\r
+/**\r
+ * @brief Starts a new message.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_StartOfMessage(void)\r
+{ \r
+ /* Starts of new message */\r
+ *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;\r
+}\r
+\r
+/**\r
+ * @brief Transmits message with or without an EOM bit.\r
+ * @param NewState: new state of the CEC Tx End Of Message. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_EndOfMessageCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* The data byte will be transmitted with or without an EOM bit*/\r
+ *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Gets the CEC flag status\r
+ * @param CEC_FLAG: specifies the CEC flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_FLAG_BTE: Bit Timing Error\r
+ * @arg CEC_FLAG_BPE: Bit Period Error\r
+ * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error\r
+ * @arg CEC_FLAG_SBE: Start Bit Error\r
+ * @arg CEC_FLAG_ACKE: Block Acknowledge Error\r
+ * @arg CEC_FLAG_LINE: Line Error\r
+ * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error\r
+ * @arg CEC_FLAG_TEOM: Tx End Of Message \r
+ * @arg CEC_FLAG_TERR: Tx Error\r
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
+ * @arg CEC_FLAG_REOM: Rx End Of Message\r
+ * @arg CEC_FLAG_RERR: Rx Error\r
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
+ * @retval The new state of CEC_FLAG (SET or RESET)\r
+ */\r
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) \r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t cecreg = 0, cecbase = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_FLAG(CEC_FLAG));\r
+ \r
+ /* Get the CEC peripheral base address */\r
+ cecbase = (uint32_t)(CEC_BASE);\r
+ \r
+ /* Read flag register index */\r
+ cecreg = CEC_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ CEC_FLAG &= FLAG_Mask;\r
+ \r
+ if(cecreg != 0)\r
+ {\r
+ /* Flag in CEC ESR Register */\r
+ CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);\r
+ \r
+ /* Get the CEC ESR register address */\r
+ cecbase += 0xC;\r
+ }\r
+ else\r
+ {\r
+ /* Get the CEC CSR register address */\r
+ cecbase += 0x10;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* CEC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the CEC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's pending flags.\r
+ * @param CEC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_FLAG_TERR: Tx Error\r
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
+ * @arg CEC_FLAG_REOM: Rx End Of Message\r
+ * @arg CEC_FLAG_RERR: Rx Error\r
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
+ * @retval None\r
+ */\r
+void CEC_ClearFlag(uint32_t CEC_FLAG)\r
+{ \r
+ uint32_t tmp = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));\r
+\r
+ tmp = CEC->CSR & 0x2;\r
+ \r
+ /* Clear the selected CEC flags */\r
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CEC interrupt has occurred or not.\r
+ * @param CEC_IT: specifies the CEC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_IT_TERR: Tx Error\r
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
+ * @arg CEC_IT_RERR: Rx Error\r
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
+ * @retval The new state of CEC_IT (SET or RESET).\r
+ */\r
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_IT(CEC_IT));\r
+ \r
+ /* Get the CEC IT enable bit status */\r
+ enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;\r
+ \r
+ /* Check the status of the specified CEC interrupt */\r
+ if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* CEC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CEC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's interrupt pending bits.\r
+ * @param CEC_IT: specifies the CEC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_IT_TERR: Tx Error\r
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
+ * @arg CEC_IT_RERR: Rx Error\r
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
+ * @retval None\r
+ */\r
+void CEC_ClearITPendingBit(uint16_t CEC_IT)\r
+{\r
+ uint32_t tmp = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_IT(CEC_IT));\r
+ \r
+ tmp = CEC->CSR & 0x2;\r
+ \r
+ /* Clear the selected CEC interrupt pending bits */\r
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_crc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the CRC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_crc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC \r
+ * @brief CRC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the CRC Data register (DR).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CRC_ResetDR(void)\r
+{\r
+ /* Reset CRC generator */\r
+ CRC->CR = CRC_CR_RESET;\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
+ * @param Data: data word(32-bit) to compute its CRC\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcCRC(uint32_t Data)\r
+{\r
+ CRC->DR = Data;\r
+ \r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
+ * @param pBuffer: pointer to the buffer containing the data to be computed\r
+ * @param BufferLength: length of the buffer to be computed \r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0;\r
+ \r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ CRC->DR = pBuffer[index];\r
+ }\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current CRC value.\r
+ * @param None\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_GetCRC(void)\r
+{\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
+ * @param IDValue: 8-bit value to be stored in the ID register \r
+ * @retval None\r
+ */\r
+void CRC_SetIDRegister(uint8_t IDValue)\r
+{\r
+ CRC->IDR = IDValue;\r
+}\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
+ * @param None\r
+ * @retval 8-bit value of the ID register \r
+ */\r
+uint8_t CRC_GetIDRegister(void)\r
+{\r
+ return (CRC->IDR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dac.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the DAC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dac.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* CR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
+\r
+/* DAC Dual Channels SWTRIG masks */\r
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
+\r
+/* DOR register offset */\r
+#define DOR_OFFSET ((uint32_t)0x0000002C)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified DAC channel.\r
+ * @retval None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+/*---------------------------- DAC CR Configuration --------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger, wave genration,\r
+ mask/amplitude for wave genration */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set WAVEx bits according to DAC_WaveGeneration value */\r
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_WaveGeneration member */\r
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+}\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/**\r
+ * @brief Enables or disables the specified DAC interrupts.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @param NewState: new state of the specified DAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */ \r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC interrupts */\r
+ DAC->CR |= (DAC_IT << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC interrupts */\r
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables simultaneously the two DAC channels software\r
+ * triggers.\r
+ * @param NewState: new state of the DAC channels software triggers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for both DAC channels */\r
+ DAC->SWTRIGR |= DUAL_SWTRIG_SET ;\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for both DAC channels */\r
+ DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_Wave: Specifies the wave type to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Wave_Noise: noise wave generation\r
+ * @arg DAC_Wave_Triangle: triangle wave generation\r
+ * @param NewState: new state of the selected DAC channel wave generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_WAVE(DAC_Wave)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ DAC->CR |= DAC_Wave << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected wave generation for the selected DAC channel */\r
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE; \r
+ tmp += DHR12R1_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel2.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel2.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12R2_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel2 selected data holding register */\r
+ *(__IO uint32_t *)tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual channel\r
+ * DAC.\r
+ * @param DAC_Align: Specifies the data alignement for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
+ * holding register.\r
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
+ * holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
+{\r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (DAC_Align == DAC_Align_8b_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12RD_OFFSET + DAC_Align;\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC cahnnel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ \r
+ tmp = (uint32_t) DAC_BASE ;\r
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp);\r
+}\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/**\r
+ * @brief Checks whether the specified DAC flag is set or not.\r
+ * @param DAC_Channel: thee selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to check. \r
+ * This parameter can be only of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval The new state of DAC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Check the status of the specified DAC flag */\r
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
+ {\r
+ /* DAC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channelx's pending flags.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to clear. \r
+ * This parameter can be of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval None\r
+ */\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Clear the selected DAC flags */\r
+ DAC->SR = (DAC_FLAG << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC interrupt has occurred or not.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt source to check. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval The new state of DAC_IT (SET or RESET).\r
+ */\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT));\r
+\r
+ /* Get the DAC_IT enable bit status */\r
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
+ \r
+ /* Check the status of the specified DAC interrupt */\r
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* DAC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channelx\92s interrupt pending bits.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval None\r
+ */\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ /* Clear the selected DAC interrupt pending bits */\r
+ DAC->SR = (DAC_IT << DAC_Channel);\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dbgmcu.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the DBGMCU firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dbgmcu.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU \r
+ * @brief DBGMCU driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DBGMCU_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @param None\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t DBGMCU_GetREVID(void)\r
+{\r
+ return(DBGMCU->IDCODE >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @param None\r
+ * @retval Device identifier\r
+ */\r
+uint32_t DBGMCU_GetDEVID(void)\r
+{\r
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified peripheral and low power mode behavior\r
+ * when the MCU under Debug mode.\r
+ * @param DBGMCU_Periph: specifies the peripheral and low power mode.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted \r
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted \r
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted \r
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted \r
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted\r
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted\r
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted\r
+ * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted \r
+ * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted\r
+ * @param NewState: new state of the specified peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->CR |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->CR &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dma.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the DMA firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dma.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA \r
+ * @brief DMA driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DMA_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Defines\r
+ * @{\r
+ */\r
+\r
+\r
+/* DMA1 Channelx interrupt pending bit masks */\r
+#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
+#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
+\r
+/* DMA2 Channelx interrupt pending bit masks */\r
+#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+\r
+/* DMA2 FLAG mask */\r
+#define FLAG_Mask ((uint32_t)0x10000000)\r
+\r
+/* DMA registers Masks */\r
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DMAy Channelx registers to their default reset\r
+ * values.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ \r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+ \r
+ /* Reset DMAy Channelx control register */\r
+ DMAy_Channelx->CCR = 0;\r
+ \r
+ /* Reset DMAy Channelx remaining bytes register */\r
+ DMAy_Channelx->CNDTR = 0;\r
+ \r
+ /* Reset DMAy Channelx peripheral address register */\r
+ DMAy_Channelx->CPAR = 0;\r
+ \r
+ /* Reset DMAy Channelx memory address register */\r
+ DMAy_Channelx->CMAR = 0;\r
+ \r
+ if (DMAy_Channelx == DMA1_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel1 */\r
+ DMA1->IFCR |= DMA1_Channel1_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel2 */\r
+ DMA1->IFCR |= DMA1_Channel2_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel3 */\r
+ DMA1->IFCR |= DMA1_Channel3_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel4 */\r
+ DMA1->IFCR |= DMA1_Channel4_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel5 */\r
+ DMA1->IFCR |= DMA1_Channel5_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel6)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel6 */\r
+ DMA1->IFCR |= DMA1_Channel6_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel7)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel7 */\r
+ DMA1->IFCR |= DMA1_Channel7_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel1 */\r
+ DMA2->IFCR |= DMA2_Channel1_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel2 */\r
+ DMA2->IFCR |= DMA2_Channel2_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel3 */\r
+ DMA2->IFCR |= DMA2_Channel3_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel4 */\r
+ DMA2->IFCR |= DMA2_Channel4_IT_Mask;\r
+ }\r
+ else\r
+ { \r
+ if (DMAy_Channelx == DMA2_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel5 */\r
+ DMA2->IFCR |= DMA2_Channel5_IT_Mask;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMAy Channelx according to the specified\r
+ * parameters in the DMA_InitStruct.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+ * contains the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
+ /* Get the DMAy_Channelx CCR value */\r
+ tmpreg = DMAy_Channelx->CCR;\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
+ tmpreg &= CCR_CLEAR_Mask;\r
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRC bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+\r
+ /* Write to DMAy Channelx CCR */\r
+ DMAy_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CPAR */\r
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CMAR */\r
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DMA_InitStruct member with its default value.\r
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param NewState: new state of the DMAy Channelx. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx interrupts.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
+ * or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @param NewState: new state of the specified DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DataNumber: The number of data units in the current DMAy Channelx\r
+ * transfer. \r
+ * @note This function can only be used when the DMAy_Channelx is disabled. \r
+ * @retval None.\r
+ */\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ \r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DataNumber; \r
+}\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current\r
+ * DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval The number of remaining data units in the current DMAy Channelx\r
+ * transfer.\r
+ */\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Return the number of remaining data units for DMAy Channelx */\r
+ return ((uint16_t)(DMAy_Channelx->CNDTR));\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
+ * @param DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
+ * @retval The new state of DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR ;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA flag */\r
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the DMA_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's pending flags.\r
+ * @param DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
+ * @retval None\r
+ */\r
+void DMA_ClearFlag(uint32_t DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
+ /* Calculate the used DMA */\r
+\r
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA2->IFCR = DMA_FLAG;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA1->IFCR = DMA_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
+ * @param DMA_IT: specifies the DMA interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
+ * @retval The new state of DMA_IT (SET or RESET).\r
+ */\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR ;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA interrupt */\r
+ if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
+ * @retval None\r
+ */\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA2->IFCR = DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA1->IFCR = DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_exti.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the EXTI firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_exti.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI \r
+ * @brief EXTI driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x00000000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000; \r
+ EXTI->FTSR = 0x00000000; \r
+ EXTI->PR = 0x000FFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the EXTI peripheral according to the specified\r
+ * parameters in the EXTI_InitStruct.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+ * that contains the configuration information for the EXTI peripheral.\r
+ * @retval None\r
+ */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ \r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ /* Disable the selected external lines */\r
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each EXTI_InitStruct member with its reset value.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt.\r
+ * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
+ * @retval None\r
+ */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param EXTI_Line: specifies the EXTI line flag to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending flags.\r
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param EXTI_Line: specifies the EXTI line to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending bits.\r
+ * @param EXTI_Line: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_flash.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the FLASH firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_flash.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* Flash Access Control Register bits */\r
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)\r
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)\r
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)\r
+\r
+/* Flash Access Control Register bits */\r
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) \r
+\r
+/* Flash Control Register bits */\r
+#define CR_PG_Set ((uint32_t)0x00000001)\r
+#define CR_PG_Reset ((uint32_t)0x00001FFE) \r
+#define CR_PER_Set ((uint32_t)0x00000002)\r
+#define CR_PER_Reset ((uint32_t)0x00001FFD)\r
+#define CR_MER_Set ((uint32_t)0x00000004)\r
+#define CR_MER_Reset ((uint32_t)0x00001FFB)\r
+#define CR_OPTPG_Set ((uint32_t)0x00000010)\r
+#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)\r
+#define CR_OPTER_Set ((uint32_t)0x00000020)\r
+#define CR_OPTER_Reset ((uint32_t)0x00001FDF)\r
+#define CR_STRT_Set ((uint32_t)0x00000040)\r
+#define CR_LOCK_Set ((uint32_t)0x00000080)\r
+\r
+/* FLASH Mask */\r
+#define RDPRT_Mask ((uint32_t)0x00000002)\r
+#define WRP0_Mask ((uint32_t)0x000000FF)\r
+#define WRP1_Mask ((uint32_t)0x0000FF00)\r
+#define WRP2_Mask ((uint32_t)0x00FF0000)\r
+#define WRP3_Mask ((uint32_t)0xFF000000)\r
+#define OB_USER_BFB2 ((uint16_t)0x0008)\r
+\r
+/* FLASH Keys */\r
+#define RDP_Key ((uint16_t)0x00A5)\r
+#define FLASH_KEY1 ((uint32_t)0x45670123)\r
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r
+\r
+/* FLASH BANK address */\r
+#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)\r
+\r
+/* Delay definition */ \r
+#define EraseTimeout ((uint32_t)0x000B0000)\r
+#define ProgramTimeout ((uint32_t)0x00002000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+@code \r
+ \r
+ This driver provides functions to configure and program the Flash memory of all STM32F10x devices,\r
+ including the latest STM32F10x_XL density devices. \r
+\r
+ STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:\r
+ - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)\r
+ - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)\r
+ While other STM32F10x devices features only one bank with memory up to 512 Kbytes.\r
+\r
+ In version V3.3.0, some functions were updated and new ones were added to support\r
+ STM32F10x_XL devices. Thus some functions manages all devices, while other are \r
+ dedicated for XL devices only.\r
+ \r
+ The table below presents the list of available functions depending on the used STM32F10x devices. \r
+ \r
+ ***************************************************\r
+ * Legacy functions used for all STM32F10x devices *\r
+ ***************************************************\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
+ | | devices | devices | |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_SetLatency | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_PrefetchBufferCmd | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |\r
+ | | | | - For other devices: unlock Bank1 and it is equivalent |\r
+ | | | | to FLASH_UnlockBank1 function. |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |\r
+ | | | | - For other devices: lock Bank1 and it is equivalent |\r
+ | | | | to FLASH_LockBank1 function. |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |\r
+ | | | | - For other devices: erase a page in Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |\r
+ | | | | - For other devices: erase all pages in Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_EraseOptionBytes | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ProgramOptionByteData | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_EnableWriteProtection | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ReadOutProtection | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_UserOptionByteConfig | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetUserOptionByte | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|\r
+ | | | | - For other devices: enable Bank1's interrupts |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|\r
+ | | | | - For other devices: return Bank1's flag status |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |\r
+ | | | | - For other devices: clear Bank1's flag |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |\r
+ | | | | equivalent to FLASH_GetBank1Status function |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |\r
+ | | | | equivalent to: FLASH_WaitForLastBank1Operation function |\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+\r
+ ************************************************************************************************************************\r
+ * New functions used for all STM32F10x devices to manage Bank1: *\r
+ * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *\r
+ * - For other devices, these functions are optional (covered by functions listed above) *\r
+ ************************************************************************************************************************\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
+ | | devices | devices | |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+\r
+ *****************************************************************************\r
+ * New Functions used only with STM32F10x_XL density devices to manage Bank2 *\r
+ *****************************************************************************\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
+ | | devices | devices | |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_LockBank2 | Yes | No | - Lock Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+@endcode\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Sets the code latency value.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_Latency: specifies the FLASH Latency value.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
+ * @arg FLASH_Latency_1: FLASH One Latency cycle\r
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles\r
+ * @retval None\r
+ */\r
+void FLASH_SetLatency(uint32_t FLASH_Latency)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
+ \r
+ /* Read the ACR register */\r
+ tmpreg = FLASH->ACR; \r
+ \r
+ /* Sets the Latency value */\r
+ tmpreg &= ACR_LATENCY_Mask;\r
+ tmpreg |= FLASH_Latency;\r
+ \r
+ /* Write the ACR register */\r
+ FLASH->ACR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Half cycle flash access.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable\r
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable\r
+ * @retval None\r
+ */\r
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));\r
+ \r
+ /* Enable or disable the Half cycle access */\r
+ FLASH->ACR &= ACR_HLFCYA_Mask;\r
+ FLASH->ACR |= FLASH_HalfCycleAccess;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Prefetch Buffer.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable\r
+ * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable\r
+ * @retval None\r
+ */\r
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));\r
+ \r
+ /* Enable or disable the Prefetch Buffer */\r
+ FLASH->ACR &= ACR_PRFTBE_Mask;\r
+ FLASH->ACR |= FLASH_PrefetchBuffer;\r
+}\r
+\r
+/**\r
+ * @brief Unlocks the FLASH Program Erase Controller.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.\r
+ * - For all other devices it unlocks Bank1 and it is equivalent \r
+ * to FLASH_UnlockBank1 function.. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Unlock(void)\r
+{\r
+ /* Authorize the FPEC of Bank1 Access */\r
+ FLASH->KEYR = FLASH_KEY1;\r
+ FLASH->KEYR = FLASH_KEY2;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Authorize the FPEC of Bank2 Access */\r
+ FLASH->KEYR2 = FLASH_KEY1;\r
+ FLASH->KEYR2 = FLASH_KEY2;\r
+#endif /* STM32F10X_XL */\r
+}\r
+/**\r
+ * @brief Unlocks the FLASH Bank1 Program Erase Controller.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function unlocks Bank1.\r
+ * - For all other devices it unlocks Bank1 and it is \r
+ * equivalent to FLASH_Unlock function.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_UnlockBank1(void)\r
+{\r
+ /* Authorize the FPEC of Bank1 Access */\r
+ FLASH->KEYR = FLASH_KEY1;\r
+ FLASH->KEYR = FLASH_KEY2;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Unlocks the FLASH Bank2 Program Erase Controller.\r
+ * @note This function can be used only for STM32F10X_XL density devices.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_UnlockBank2(void)\r
+{\r
+ /* Authorize the FPEC of Bank2 Access */\r
+ FLASH->KEYR2 = FLASH_KEY1;\r
+ FLASH->KEYR2 = FLASH_KEY2;\r
+\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Locks the FLASH Program Erase Controller.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.\r
+ * - For all other devices it Locks Bank1 and it is equivalent \r
+ * to FLASH_LockBank1 function.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Lock(void)\r
+{\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
+ FLASH->CR |= CR_LOCK_Set;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
+ FLASH->CR2 |= CR_LOCK_Set;\r
+#endif /* STM32F10X_XL */\r
+}\r
+\r
+/**\r
+ * @brief Locks the FLASH Bank1 Program Erase Controller.\r
+ * @note this function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function Locks Bank1.\r
+ * - For all other devices it Locks Bank1 and it is equivalent \r
+ * to FLASH_Lock function.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_LockBank1(void)\r
+{\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
+ FLASH->CR |= CR_LOCK_Set;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Locks the FLASH Bank2 Program Erase Controller.\r
+ * @note This function can be used only for STM32F10X_XL density devices.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_LockBank2(void)\r
+{\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
+ FLASH->CR2 |= CR_LOCK_Set;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Erases a specified FLASH page.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Page_Address: The page address to be erased.\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Page_Address));\r
+\r
+#ifdef STM32F10X_XL\r
+ if(Page_Address < FLASH_BANK1_END_ADDRESS) \r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* if the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR|= CR_PER_Set;\r
+ FLASH->AR = Page_Address; \r
+ FLASH->CR|= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+\r
+ /* Disable the PER Bit */\r
+ FLASH->CR &= CR_PER_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* if the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR2|= CR_PER_Set;\r
+ FLASH->AR2 = Page_Address; \r
+ FLASH->CR2|= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ \r
+ /* Disable the PER Bit */\r
+ FLASH->CR2 &= CR_PER_Reset;\r
+ }\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* if the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR|= CR_PER_Set;\r
+ FLASH->AR = Page_Address; \r
+ FLASH->CR|= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ /* Disable the PER Bit */\r
+ FLASH->CR &= CR_PER_Reset;\r
+ }\r
+#endif /* STM32F10X_XL */\r
+\r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erases all FLASH pages.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllPages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= CR_MER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ /* Disable the MER Bit */\r
+ FLASH->CR &= CR_MER_Reset;\r
+ } \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR2 |= CR_MER_Set;\r
+ FLASH->CR2 |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ \r
+ /* Disable the MER Bit */\r
+ FLASH->CR2 &= CR_MER_Reset;\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= CR_MER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+\r
+ /* Disable the MER Bit */\r
+ FLASH->CR &= CR_MER_Reset;\r
+ }\r
+#endif /* STM32F10X_XL */\r
+\r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erases all Bank1 FLASH pages.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function erases all Bank1 pages.\r
+ * - For all other devices it erases all Bank1 pages and it is equivalent \r
+ * to FLASH_EraseAllPages function.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllBank1Pages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= CR_MER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ /* Disable the MER Bit */\r
+ FLASH->CR &= CR_MER_Reset;\r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Erases all Bank2 FLASH pages.\r
+ * @note This function can be used only for STM32F10x_XL density devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllBank2Pages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR2 |= CR_MER_Set;\r
+ FLASH->CR2 |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+\r
+ /* Disable the MER Bit */\r
+ FLASH->CR2 &= CR_MER_Reset;\r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Erases the FLASH option bytes.\r
+ * @note This functions erases all option bytes except the Read protection (RDP). \r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseOptionBytes(void)\r
+{\r
+ uint16_t rdptmp = RDP_Key;\r
+\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Get the actual read protection Option Byte value */ \r
+ if(FLASH_GetReadOutProtectionStatus() != RESET)\r
+ {\r
+ rdptmp = 0x00; \r
+ }\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* if the previous operation is completed, proceed to erase the option bytes */\r
+ FLASH->CR |= CR_OPTER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set;\r
+ /* Restore the last read protection Option Byte value */\r
+ OB->RDP = (uint16_t)rdptmp; \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (status != FLASH_TIMEOUT)\r
+ {\r
+ /* Disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ }\r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+\r
+#ifdef STM32F10X_XL\r
+ if(Address < FLASH_BANK1_END_ADDRESS - 2)\r
+ { \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout); \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ }\r
+ }\r
+ else if(Address == (FLASH_BANK1_END_ADDRESS - 1))\r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ FLASH->CR2 |= CR_PG_Set;\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR2 |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ }\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ } \r
+#endif /* STM32F10X_XL */\r
+ \r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half word at a specified address.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(Address < FLASH_BANK1_END_ADDRESS)\r
+ {\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
+\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR2 |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+\r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ } \r
+#endif /* STM32F10X_XL */\r
+ \r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half word at a specified Option Byte Data address.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Address: specifies the address to be programmed.\r
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806. \r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_DATA_ADDRESS(Address));\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ /* Enables the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ *(__IO uint16_t*)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ /* Return the Option Byte Data Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_Pages: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 \r
+ * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3\r
+ * and FLASH_WRProt_Pages124to127\r
+ * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and\r
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255\r
+ * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and\r
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 \r
+ * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and\r
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511\r
+ * @arg FLASH_WRProt_AllPages\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)\r
+{\r
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));\r
+ \r
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);\r
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);\r
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);\r
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);\r
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorizes the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ FLASH->CR |= CR_OPTPG_Set;\r
+ if(WRP0_Data != 0xFF)\r
+ {\r
+ OB->WRP0 = WRP0_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))\r
+ {\r
+ OB->WRP1 = WRP1_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))\r
+ {\r
+ OB->WRP2 = WRP2_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ \r
+ if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))\r
+ {\r
+ OB->WRP3 = WRP3_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * @note If the user has already programmed the other option bytes before calling \r
+ * this function, he must re-program them since this function erases all option bytes.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Newstate: new state of the ReadOut Protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorizes the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ FLASH->CR |= CR_OPTER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ if(NewState != DISABLE)\r
+ {\r
+ OB->RDP = 0x00;\r
+ }\r
+ else\r
+ {\r
+ OB->RDP = RDP_Key; \r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout); \r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ else \r
+ {\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* Disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ }\r
+ }\r
+ }\r
+ /* Return the protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param OB_IWDG: Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param OB_STOP: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param OB_STDBY: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ \r
+ OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); \r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Configures to boot from Bank1 or Bank2. \r
+ * @note This function can be used only for STM32F10x_XL density devices.\r
+ * @param FLASH_BOOT: select the FLASH Bank to boot from.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank1(Default).\r
+ * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank2 or Bank1,\r
+ * depending on the activation of the bank. The active banks are checked in\r
+ * the following order: Bank2, followed by Bank1.\r
+ * The active bank is recognized by the value programmed at the base address\r
+ * of the respective bank (corresponding to the initial stack pointer value\r
+ * in the interrupt vector table).\r
+ * For more information, please refer to AN2606 from www.st.com. \r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE; \r
+ assert_param(IS_FLASH_BOOT(FLASH_BOOT));\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+\r
+ if(FLASH_BOOT == FLASH_BOOT_Bank1)\r
+ {\r
+ OB->USER |= OB_USER_BFB2;\r
+ }\r
+ else\r
+ {\r
+ OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)\r
+ * and RST_STDBY(Bit2).\r
+ */\r
+uint32_t FLASH_GetUserOptionByte(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint32_t)(FLASH->OBR >> 2);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes Register value\r
+ */\r
+uint32_t FLASH_GetWriteProtectionOptionByte(void)\r
+{\r
+ /* Return the Falsh write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH ReadOut Protection Status(SET or RESET)\r
+ */\r
+FlagStatus FLASH_GetReadOutProtectionStatus(void)\r
+{\r
+ FlagStatus readoutstatus = RESET;\r
+ if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)\r
+ {\r
+ readoutstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ readoutstatus = RESET;\r
+ }\r
+ return readoutstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH Prefetch Buffer Status (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified FLASH interrupts.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts\r
+ for Bank1 and Bank2.\r
+ * - For other devices it enables or disables the specified FLASH interrupts for Bank1.\r
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_ERROR: FLASH Error Interrupt\r
+ * @arg FLASH_IT_EOP: FLASH end of operation Interrupt\r
+ * @param NewState: new state of the specified Flash interrupts.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None \r
+ */\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
+{\r
+#ifdef STM32F10X_XL\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if((FLASH_IT & 0x80000000) != 0x0)\r
+ {\r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+ }\r
+#else\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+#endif /* STM32F10X_XL */\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices, this function checks whether the specified \r
+ * Bank1 or Bank2 flag is set or not.\r
+ * - For other devices, it checks whether the specified Bank1 flag is \r
+ * set or not.\r
+ * @param FLASH_FLAG: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag \r
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
+ * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag \r
+ * @retval The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
+ {\r
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((FLASH_FLAG & 0x80000000) != 0x0)\r
+ {\r
+ if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ }\r
+#else\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
+ {\r
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+#endif /* STM32F10X_XL */\r
+\r
+ /* Return the new state of FLASH_FLAG (SET or RESET) */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the FLASH\92s pending flags.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices, this function clears Bank1 or Bank2\92s pending flags\r
+ * - For other devices, it clears Bank1\92s pending flags.\r
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values: \r
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
+ * @retval None\r
+ */\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
+{\r
+#ifdef STM32F10X_XL\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
+\r
+ if((FLASH_FLAG & 0x80000000) != 0x0)\r
+ {\r
+ /* Clear the flags */\r
+ FLASH->SR2 = FLASH_FLAG;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+ } \r
+\r
+#else\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
+ \r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+#endif /* STM32F10X_XL */\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @note This function can be used for all STM32F10x devices, it is equivalent\r
+ * to FLASH_GetBank1Status function.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+FLASH_Status FLASH_GetStatus(void)\r
+{\r
+ FLASH_Status flashstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ flashstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & FLASH_FLAG_PGERR) != 0)\r
+ { \r
+ flashstatus = FLASH_ERROR_PG;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )\r
+ {\r
+ flashstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else\r
+ {\r
+ flashstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Flash Status */\r
+ return flashstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Bank1 Status.\r
+ * @note This function can be used for all STM32F10x devices, it is equivalent\r
+ * to FLASH_GetStatus function.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+FLASH_Status FLASH_GetBank1Status(void)\r
+{\r
+ FLASH_Status flashstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ flashstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)\r
+ { \r
+ flashstatus = FLASH_ERROR_PG;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )\r
+ {\r
+ flashstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else\r
+ {\r
+ flashstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Flash Status */\r
+ return flashstatus;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Returns the FLASH Bank2 Status.\r
+ * @note This function can be used for STM32F10x_XL density devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+FLASH_Status FLASH_GetBank2Status(void)\r
+{\r
+ FLASH_Status flashstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) \r
+ {\r
+ flashstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)\r
+ { \r
+ flashstatus = FLASH_ERROR_PG;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )\r
+ {\r
+ flashstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else\r
+ {\r
+ flashstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Flash Status */\r
+ return flashstatus;\r
+}\r
+#endif /* STM32F10X_XL */\r
+/**\r
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.\r
+ * @note This function can be used for all STM32F10x devices, \r
+ * it is equivalent to FLASH_WaitForLastBank1Operation.\r
+ * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation\r
+ * to complete or a TIMEOUT to occur.\r
+ * - For all other devices it waits for a Flash operation to complete \r
+ * or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH progamming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the Flash Status */\r
+ status = FLASH_GetBank1Status();\r
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetBank1Status();\r
+ Timeout--;\r
+ }\r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.\r
+ * @note This function can be used for all STM32F10x devices, \r
+ * it is equivalent to FLASH_WaitForLastOperation.\r
+ * @param Timeout: FLASH progamming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the Flash Status */\r
+ status = FLASH_GetBank1Status();\r
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetBank1Status();\r
+ Timeout--;\r
+ }\r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.\r
+ * @note This function can be used only for STM32F10x_XL density devices.\r
+ * @param Timeout: FLASH progamming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the Flash Status */\r
+ status = FLASH_GetBank2Status();\r
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
+ while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetBank2Status();\r
+ Timeout--;\r
+ }\r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_fsmc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the FSMC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_fsmc.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC \r
+ * @brief FSMC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FSMC_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* --------------------- FSMC registers bit mask ---------------------------- */\r
+\r
+/* FSMC BCRx Mask */\r
+#define BCR_MBKEN_Set ((uint32_t)0x00000001)\r
+#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)\r
+#define BCR_FACCEN_Set ((uint32_t)0x00000040)\r
+\r
+/* FSMC PCRx Mask */\r
+#define PCR_PBKEN_Set ((uint32_t)0x00000004)\r
+#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)\r
+#define PCR_ECCEN_Set ((uint32_t)0x00000040)\r
+#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)\r
+#define PCR_MemoryType_NAND ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
+ * reset values.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ \r
+ /* FSMC_Bank1_NORSRAM1 */\r
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r
+ }\r
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
+ else\r
+ { \r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
+ }\r
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
+ * @retval None\r
+ */\r
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* Set the FSMC_Bank2 registers to their reset values */\r
+ FSMC_Bank2->PCR2 = 0x00000018;\r
+ FSMC_Bank2->SR2 = 0x00000040;\r
+ FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
+ FSMC_Bank2->PATT2 = 0xFCFCFCFC; \r
+ }\r
+ /* FSMC_Bank3_NAND */ \r
+ else\r
+ {\r
+ /* Set the FSMC_Bank3 registers to their reset values */\r
+ FSMC_Bank3->PCR3 = 0x00000018;\r
+ FSMC_Bank3->SR3 = 0x00000040;\r
+ FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
+ FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDDeInit(void)\r
+{\r
+ /* Set the FSMC_Bank4 registers to their reset values */\r
+ FSMC_Bank4->PCR4 = 0x00000018; \r
+ FSMC_Bank4->SR4 = 0x00000000; \r
+ FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
+ FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
+ FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the specified\r
+ * parameters in the FSMC_NORSRAMInitStruct.\r
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
+ * structure that contains the configuration information for \r
+ * the FSMC NOR/SRAM specified Banks. \r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
+ assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
+ \r
+ /* Bank1 NOR/SRAM control register configuration */ \r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
+\r
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
+ }\r
+ \r
+ /* Bank1 NOR/SRAM timing register configuration */\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
+ \r
+ \r
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
+ {\r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC NAND Banks according to the specified \r
+ * parameters in the FSMC_NANDInitStruct.\r
+ * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
+ * structure that contains the configuration information for the FSMC NAND specified Banks. \r
+ * @retval None\r
+ */\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
+{\r
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
+ \r
+ /* Check the parameters */\r
+ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
+ assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
+ assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
+ assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
+ assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
+ assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
+ assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
+ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
+ PCR_MemoryType_NAND |\r
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
+ FSMC_NANDInitStruct->FSMC_ECC |\r
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
+ \r
+ /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
+ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
+ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
+ \r
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* FSMC_Bank2_NAND registers configuration */\r
+ FSMC_Bank2->PCR2 = tmppcr;\r
+ FSMC_Bank2->PMEM2 = tmppmem;\r
+ FSMC_Bank2->PATT2 = tmppatt;\r
+ }\r
+ else\r
+ {\r
+ /* FSMC_Bank3_NAND registers configuration */\r
+ FSMC_Bank3->PCR3 = tmppcr;\r
+ FSMC_Bank3->PMEM3 = tmppmem;\r
+ FSMC_Bank3->PATT3 = tmppatt;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC PCCARD Bank according to the specified \r
+ * parameters in the FSMC_PCCARDInitStruct.\r
+ * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
+ * structure that contains the configuration information for the FSMC PCCARD Bank. \r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
+ assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
+ assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
+ \r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
+ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
+ FSMC_MemoryDataWidth_16b | \r
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
+ \r
+ /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Reset NOR/SRAM Init structure parameters values */\r
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_NANDInitStruct member with its default value.\r
+ * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
+{ \r
+ /* Reset NAND Init structure parameters values */\r
+ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
+ FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
+ FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
+ FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
+ FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
+ FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_PCCARDInitStruct member with its default value.\r
+ * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
+{\r
+ /* Reset PCCARD Init structure parameters values */\r
+ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
+ FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
+ FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified NAND Memory Bank.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PCCARD Memory Bank.\r
+ * @param NewState: new state of the PCCARD Memory Bank. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
+ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
+ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the FSMC NAND ECC feature.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @param NewState: new state of the FSMC NAND ECC feature. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the error correction code register value.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @retval The Error Correction Code (ECC) value.\r
+ */\r
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
+{\r
+ uint32_t eccval = 0x00000000;\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* Get the ECCR2 register value */\r
+ eccval = FSMC_Bank2->ECCR2;\r
+ }\r
+ else\r
+ {\r
+ /* Get the ECCR3 register value */\r
+ eccval = FSMC_Bank3->ECCR3;\r
+ }\r
+ /* Return the error correction code value */\r
+ return(eccval);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified FSMC interrupts.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
+ * @param NewState: new state of the specified FSMC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_IT(FSMC_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected FSMC_Bank2 interrupts */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 |= FSMC_IT;\r
+ }\r
+ /* Enable the selected FSMC_Bank3 interrupts */\r
+ else if (FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 |= FSMC_IT;\r
+ }\r
+ /* Enable the selected FSMC_Bank4 interrupts */\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 |= FSMC_IT; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected FSMC_Bank2 interrupts */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ \r
+ FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
+ }\r
+ /* Disable the selected FSMC_Bank3 interrupts */\r
+ else if (FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
+ }\r
+ /* Disable the selected FSMC_Bank4 interrupts */\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FSMC flag is set or not.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
+ * @arg FSMC_FLAG_Level: Level detection Flag.\r
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
+ * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
+ * @retval The new state of FSMC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpsr = 0x00000000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank2->SR2;\r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank3->SR3;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ tmpsr = FSMC_Bank4->SR4;\r
+ } \r
+ \r
+ /* Get the flag status */\r
+ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the FSMC\92s pending flags.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
+ * @arg FSMC_FLAG_Level: Level detection Flag.\r
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
+ * @retval None\r
+ */\r
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FSMC interrupt has occurred or not.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the FSMC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
+ * @retval The new state of FSMC_IT (SET or RESET).\r
+ */\r
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank2->SR2;\r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank3->SR3;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ tmpsr = FSMC_Bank4->SR4;\r
+ } \r
+ \r
+ itstatus = tmpsr & FSMC_IT;\r
+ \r
+ itenable = tmpsr & (FSMC_IT >> 3);\r
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the FSMC\92s interrupt pending bits.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
+ * @retval None\r
+ */\r
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_IT(FSMC_IT));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the GPIO firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_gpio.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------------*/\r
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)\r
+\r
+/* --- EVENTCR Register -----*/\r
+\r
+/* Alias word address of EVOE bit */\r
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)\r
+#define EVOE_BitNumber ((uint8_t)0x07)\r
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))\r
+\r
+\r
+/* --- MAPR Register ---*/ \r
+/* Alias word address of MII_RMII_SEL bit */ \r
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04) \r
+#define MII_RMII_SEL_BitNumber ((u8)0x17) \r
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))\r
+\r
+\r
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)\r
+#define LSB_MASK ((uint16_t)0xFFFF)\r
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)\r
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)\r
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)\r
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ if (GPIOx == GPIOA)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOB)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOC)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOD)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);\r
+ } \r
+ else if (GPIOx == GPIOE)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);\r
+ } \r
+ else if (GPIOx == GPIOF)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (GPIOx == GPIOG)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the Alternate Functions (remap, event control\r
+ * and EXTI configuration) registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void GPIO_AFIODeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified\r
+ * parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that\r
+ * contains the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;\r
+ uint32_t tmpreg = 0x00, pinmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); \r
+ \r
+/*---------------------------- GPIO Mode Configuration -----------------------*/\r
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);\r
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)\r
+ { \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+ /* Output mode */\r
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;\r
+ }\r
+/*---------------------------- GPIO CRL Configuration ------------------------*/\r
+ /* Configure the eight low port pins */\r
+ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)\r
+ {\r
+ tmpreg = GPIOx->CRL;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding low control register bits */\r
+ pinmask = ((uint32_t)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((uint32_t)0x01) << pinpos);\r
+ }\r
+ else\r
+ {\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((uint32_t)0x01) << pinpos);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRL = tmpreg;\r
+ }\r
+/*---------------------------- GPIO CRH Configuration ------------------------*/\r
+ /* Configure the eight high port pins */\r
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)\r
+ {\r
+ tmpreg = GPIOx->CRH;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ /* Get the port pins position */\r
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding high control register bits */\r
+ pinmask = ((uint32_t)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ }\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRH = tmpreg;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enum values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal)); \r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BRR = GPIO_Pin;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint32_t tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as Event output.\r
+ * @param GPIO_PortSource: selects the GPIO port to be used as source\r
+ * for Event output.\r
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).\r
+ * @param GPIO_PinSource: specifies the pin for the Event output.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmpreg = AFIO->EVCR;\r
+ /* Clear the PORT[6:4] and PIN[3:0] bits */\r
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;\r
+ tmpreg |= (uint32_t)GPIO_PortSource << 0x04;\r
+ tmpreg |= GPIO_PinSource;\r
+ AFIO->EVCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Event Output.\r
+ * @param NewState: new state of the Event output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void GPIO_EventOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param GPIO_Remap: selects the pin to remap.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping\r
+ * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping\r
+ * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping\r
+ * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping\r
+ * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping\r
+ * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping\r
+ * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping\r
+ * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping\r
+ * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping\r
+ * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping\r
+ * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping\r
+ * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping\r
+ * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping\r
+ * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping\r
+ * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping\r
+ * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping\r
+ * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping\r
+ * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration\r
+ * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping\r
+ * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping\r
+ * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping\r
+ * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping\r
+ * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST\r
+ * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled\r
+ * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)\r
+ * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected\r
+ * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)\r
+ * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to \r
+ * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. \r
+ * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)\r
+ * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)\r
+ * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)\r
+ * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)\r
+ * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)\r
+ * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)\r
+ * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)\r
+ * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)\r
+ * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \r
+ * only for High density Value line devices) \r
+ * @param NewState: new state of the port pin remapping.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)\r
+{\r
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if((GPIO_Remap & 0x80000000) == 0x80000000)\r
+ {\r
+ tmpreg = AFIO->MAPR2;\r
+ }\r
+ else\r
+ {\r
+ tmpreg = AFIO->MAPR;\r
+ }\r
+\r
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;\r
+ tmp = GPIO_Remap & LSB_MASK;\r
+\r
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))\r
+ {\r
+ tmpreg &= DBGAFR_SWJCFG_MASK;\r
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)\r
+ {\r
+ tmp1 = ((uint32_t)0x03) << tmpmask;\r
+ tmpreg &= ~tmp1;\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else\r
+ {\r
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ }\r
+\r
+ if((GPIO_Remap & 0x80000000) == 0x80000000)\r
+ {\r
+ AFIO->MAPR2 = tmpreg;\r
+ }\r
+ else\r
+ {\r
+ AFIO->MAPR = tmpreg;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.\r
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).\r
+ * @param GPIO_PinSource: specifies the EXTI line to be configured.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
+{\r
+ uint32_t tmp = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @brief Selects the Ethernet media interface.\r
+ * @note This function applies only to STM32 Connectivity line devices. \r
+ * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_ETH_MediaInterface_MII: MII mode\r
+ * @arg GPIO_ETH_MediaInterface_RMII: RMII mode \r
+ * @retval None\r
+ */\r
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) \r
+{ \r
+ assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); \r
+\r
+ /* Configure MII_RMII selection bit */ \r
+ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; \r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the I2C firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_i2c.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C \r
+ * @brief I2C driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup I2C_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* I2C SPE mask */\r
+#define CR1_PE_Set ((uint16_t)0x0001)\r
+#define CR1_PE_Reset ((uint16_t)0xFFFE)\r
+\r
+/* I2C START mask */\r
+#define CR1_START_Set ((uint16_t)0x0100)\r
+#define CR1_START_Reset ((uint16_t)0xFEFF)\r
+\r
+/* I2C STOP mask */\r
+#define CR1_STOP_Set ((uint16_t)0x0200)\r
+#define CR1_STOP_Reset ((uint16_t)0xFDFF)\r
+\r
+/* I2C ACK mask */\r
+#define CR1_ACK_Set ((uint16_t)0x0400)\r
+#define CR1_ACK_Reset ((uint16_t)0xFBFF)\r
+\r
+/* I2C ENGC mask */\r
+#define CR1_ENGC_Set ((uint16_t)0x0040)\r
+#define CR1_ENGC_Reset ((uint16_t)0xFFBF)\r
+\r
+/* I2C SWRST mask */\r
+#define CR1_SWRST_Set ((uint16_t)0x8000)\r
+#define CR1_SWRST_Reset ((uint16_t)0x7FFF)\r
+\r
+/* I2C PEC mask */\r
+#define CR1_PEC_Set ((uint16_t)0x1000)\r
+#define CR1_PEC_Reset ((uint16_t)0xEFFF)\r
+\r
+/* I2C ENPEC mask */\r
+#define CR1_ENPEC_Set ((uint16_t)0x0020)\r
+#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)\r
+\r
+/* I2C ENARP mask */\r
+#define CR1_ENARP_Set ((uint16_t)0x0010)\r
+#define CR1_ENARP_Reset ((uint16_t)0xFFEF)\r
+\r
+/* I2C NOSTRETCH mask */\r
+#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)\r
+#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)\r
+\r
+/* I2C registers Masks */\r
+#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)\r
+\r
+/* I2C DMAEN mask */\r
+#define CR2_DMAEN_Set ((uint16_t)0x0800)\r
+#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)\r
+\r
+/* I2C LAST mask */\r
+#define CR2_LAST_Set ((uint16_t)0x1000)\r
+#define CR2_LAST_Reset ((uint16_t)0xEFFF)\r
+\r
+/* I2C FREQ mask */\r
+#define CR2_FREQ_Reset ((uint16_t)0xFFC0)\r
+\r
+/* I2C ADD0 mask */\r
+#define OAR1_ADD0_Set ((uint16_t)0x0001)\r
+#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)\r
+\r
+/* I2C ENDUAL mask */\r
+#define OAR2_ENDUAL_Set ((uint16_t)0x0001)\r
+#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)\r
+\r
+/* I2C ADD2 mask */\r
+#define OAR2_ADD2_Reset ((uint16_t)0xFF01)\r
+\r
+/* I2C F/S mask */\r
+#define CCR_FS_Set ((uint16_t)0x8000)\r
+\r
+/* I2C CCR mask */\r
+#define CCR_CCR_Set ((uint16_t)0x0FFF)\r
+\r
+/* I2C FLAG mask */\r
+#define FLAG_Mask ((uint32_t)0x00FFFFFF)\r
+\r
+/* I2C Interrupt Enable mask */\r
+#define ITEN_Mask ((uint32_t)0x07000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ if (I2Cx == I2C1)\r
+ {\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the I2Cx peripheral according to the specified \r
+ * parameters in the I2C_InitStruct.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+ * contains the configuration information for the specified I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, freqrange = 0;\r
+ uint16_t result = 0x04;\r
+ uint32_t pclk1 = 8000000;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+\r
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear frequency FREQ[5:0] bits */\r
+ tmpreg &= CR2_FREQ_Reset;\r
+ /* Get pclk1 frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ pclk1 = rcc_clocks.PCLK1_Frequency;\r
+ /* Set frequency bits depending on pclk1 value */\r
+ freqrange = (uint16_t)(pclk1 / 1000000);\r
+ tmpreg |= freqrange;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+\r
+/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
+ /* Disable the selected I2C peripheral to configure TRISE */\r
+ I2Cx->CR1 &= CR1_PE_Reset;\r
+ /* Reset tmpreg value */\r
+ /* Clear F/S, DUTY and CCR[11:0] bits */\r
+ tmpreg = 0;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
+ /* Test if CCR value is under 0x4*/\r
+ if (result < 0x04)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result = 0x04; \r
+ }\r
+ /* Set speed value for standard mode */\r
+ tmpreg |= result; \r
+ /* Set Maximum Rise Time for standard mode */\r
+ I2Cx->TRISE = freqrange + 1; \r
+ }\r
+ /* Configure speed in fast mode */\r
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
+ {\r
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
+ }\r
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
+ /* Set DUTY bit */\r
+ result |= I2C_DutyCycle_16_9;\r
+ }\r
+\r
+ /* Test if CCR value is under 0x1*/\r
+ if ((result & CCR_CCR_Set) == 0)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result |= (uint16_t)0x0001; \r
+ }\r
+ /* Set speed value and set F/S bit for fast mode */\r
+ tmpreg |= (uint16_t)(result | CCR_FS_Set);\r
+ /* Set Maximum Rise Time for fast mode */\r
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
+ }\r
+\r
+ /* Write to I2Cx CCR */\r
+ I2Cx->CCR = tmpreg;\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+\r
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear ACK, SMBTYPE and SMBUS bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure I2Cx: mode and acknowledgement */\r
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
+ /* Set ACK bit according to I2C_Ack value */\r
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
+ /* Set I2Cx Own Address1 and acknowledged address */\r
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2C_InitStruct member with its default value.\r
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+/*---------------- Reset I2C init structure parameters values ----------------*/\r
+ /* initialize the I2C_ClockSpeed member */\r
+ I2C_InitStruct->I2C_ClockSpeed = 5000;\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+ /* Initialize the I2C_DutyCycle member */\r
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= CR1_PE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C DMA requests.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR2 |= CR2_DMAEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR2 &= CR2_DMAEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Specifies if the next DMA transfer will be the last one.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA last transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Next DMA transfer is the last transfer */\r
+ I2Cx->CR2 |= CR2_LAST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Next DMA transfer is not the last transfer */\r
+ I2Cx->CR2 &= CR2_LAST_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication START condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C START condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR1 |= CR1_START_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR1 &= CR1_START_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication STOP condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C STOP condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR1 |= CR1_STOP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR1 &= CR1_STOP_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C acknowledge feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C Acknowledgement.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2Cx->CR1 |= CR1_ACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2Cx->CR1 &= CR1_ACK_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified I2C own address2.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the 7bit I2C own address2.\r
+ * @retval None.\r
+ */\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
+{\r
+ uint16_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+\r
+ /* Reset I2Cx Own address2 bit [7:1] */\r
+ tmpreg &= OAR2_ADD2_Reset;\r
+\r
+ /* Set I2Cx Own address2 */\r
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
+\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C dual addressing mode.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C dual addressing mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable dual addressing mode */\r
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable dual addressing mode */\r
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C general call feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C General call.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable generall call */\r
+ I2Cx->CR1 |= CR1_ENGC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable generall call */\r
+ I2Cx->CR1 &= CR1_ENGC_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C interrupts.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_BUF: Buffer interrupt mask\r
+ * @arg I2C_IT_EVT: Event interrupt mask\r
+ * @arg I2C_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified I2C interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR2 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sends a data byte through the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Data: Byte to be transmitted..\r
+ * @retval None\r
+ */\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the data in the DR register */\r
+ return (uint8_t)I2Cx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Transmits the address byte to select the slave device.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the slave address which will be transmitted\r
+ * @param I2C_Direction: specifies whether the I2C device will be a\r
+ * Transmitter or a Receiver. This parameter can be one of the following values\r
+ * @arg I2C_Direction_Transmitter: Transmitter mode\r
+ * @arg I2C_Direction_Receiver: Receiver mode\r
+ * @retval None.\r
+ */\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction != I2C_Direction_Transmitter)\r
+ {\r
+ /* Set the address bit0 for read */\r
+ Address |= OAR1_ADD0_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= OAR1_ADD0_Reset;\r
+ }\r
+ /* Send the address */\r
+ I2Cx->DR = Address;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified I2C register and returns its value.\r
+ * @param I2C_Register: specifies the register to read.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Register_CR1: CR1 register.\r
+ * @arg I2C_Register_CR2: CR2 register.\r
+ * @arg I2C_Register_OAR1: OAR1 register.\r
+ * @arg I2C_Register_OAR2: OAR2 register.\r
+ * @arg I2C_Register_DR: DR register.\r
+ * @arg I2C_Register_SR1: SR1 register.\r
+ * @arg I2C_Register_SR2: SR2 register.\r
+ * @arg I2C_Register_CCR: CCR register.\r
+ * @arg I2C_Register_TRISE: TRISE register.\r
+ * @retval The value of the read register.\r
+ */\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ tmp = (uint32_t) I2Cx;\r
+ tmp += I2C_Register;\r
+\r
+ /* Return the selected register value */\r
+ return (*(__IO uint16_t *) tmp);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C software reset.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C software reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= CR1_SWRST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= CR1_SWRST_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
+ * @retval None\r
+ */\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
+ {\r
+ /* Drive the SMBusAlert pin Low */\r
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
+ }\r
+ else\r
+ {\r
+ /* Drive the SMBusAlert pin High */\r
+ I2Cx->CR1 &= I2C_SMBusAlert_High;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C PEC transfer.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C PEC transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC transmission */\r
+ I2Cx->CR1 |= CR1_PEC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC transmission */\r
+ I2Cx->CR1 &= CR1_PEC_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C PEC position.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_PECPosition: specifies the PEC position. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
+ * @retval None\r
+ */\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
+ if (I2C_PECPosition == I2C_PECPosition_Next)\r
+ {\r
+ /* Next byte in shift register is PEC */\r
+ I2Cx->CR1 |= I2C_PECPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* Current byte in shift register is PEC */\r
+ I2Cx->CR1 &= I2C_PECPosition_Current;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PEC value calculation of the transfered bytes.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx PEC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC calculation */\r
+ I2Cx->CR1 |= CR1_ENPEC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC calculation */\r
+ I2Cx->CR1 &= CR1_ENPEC_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the PEC value for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The PEC value.\r
+ */\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the selected I2C PEC value */\r
+ return ((I2Cx->SR2) >> 8);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C ARP.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx ARP. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C ARP */\r
+ I2Cx->CR1 |= CR1_ENARP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C ARP */\r
+ I2Cx->CR1 &= CR1_ENARP_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C Clock stretching.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Clock stretching.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable the selected I2C Clock stretching */\r
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C Clock stretching */\r
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C fast mode duty cycle.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
+ * @retval None\r
+ */\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=2 */\r
+ I2Cx->CCR &= I2C_DutyCycle_2;\r
+ }\r
+ else\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=16/9 */\r
+ I2Cx->CCR |= I2C_DutyCycle_16_9;\r
+ }\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief\r
+ ****************************************************************************************\r
+ *\r
+ * I2C State Monitoring Functions\r
+ * \r
+ **************************************************************************************** \r
+ * This I2C driver provides three different ways for I2C state monitoring\r
+ * depending on the application requirements and constraints:\r
+ * \r
+ * \r
+ * 1) Basic state monitoring:\r
+ * Using I2C_CheckEvent() function:\r
+ * It compares the status registers (SR1 and SR2) content to a given event\r
+ * (can be the combination of one or more flags).\r
+ * It returns SUCCESS if the current status includes the given flags \r
+ * and returns ERROR if one or more flags are missing in the current status.\r
+ * - When to use:\r
+ * - This function is suitable for most applciations as well as for startup \r
+ * activity since the events are fully described in the product reference manual \r
+ * (RM0008).\r
+ * - It is also suitable for users who need to define their own events.\r
+ * - Limitations:\r
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
+ * hold or corrupted real state. \r
+ * In this case, it is advised to use error interrupts to monitor the error\r
+ * events and handle them in the interrupt IRQ handler.\r
+ * \r
+ * @note \r
+ * For error management, it is advised to use the following functions:\r
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
+ * Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() \r
+ * in order to determine which error occured.\r
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
+ * and return to correct communication status.\r
+ * \r
+ *\r
+ * 2) Advanced state monitoring:\r
+ * Using the function I2C_GetLastEvent() which returns the image of both status \r
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ * by 16 bits and concatenated to Status Register 1).\r
+ * - When to use:\r
+ * - This function is suitable for the same applications above but it allows to\r
+ * overcome the mentionned limitation of I2C_GetFlagStatus() function.\r
+ * The returned value could be compared to events already defined in the \r
+ * library (stm32f10x_i2c.h) or to custom values defiend by user.\r
+ * - This function is suitable when multiple flags are monitored at the same time.\r
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
+ * choose when an event is accepted (when all events flags are set and no \r
+ * other flags are set or just when the needed flags are set like \r
+ * I2C_CheckEvent() function).\r
+ * - Limitations:\r
+ * - User may need to define his own events.\r
+ * - Same remark concerning the error management is applicable for this \r
+ * function if user decides to check only regular communication flags (and \r
+ * ignores error flags).\r
+ * \r
+ *\r
+ * 3) Flag-based state monitoring:\r
+ * Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ * one single flag (ie. I2C_FLAG_RXNE ...). \r
+ * - When to use:\r
+ * - This function could be used for specific applications or in debug phase.\r
+ * - It is suitable when only one flag checking is needed (most I2C events \r
+ * are monitored through multiple flags).\r
+ * - Limitations: \r
+ * - When calling this function, the Status register is accessed. Some flags are\r
+ * cleared when the status register is accessed. So checking the status\r
+ * of one Flag, may clear other ones.\r
+ * - Function may need to be called twice or more in order to monitor one \r
+ * single event.\r
+ *\r
+ * For detailed description of Events, please refer to section I2C_Events in \r
+ * stm32f10x_i2c.h file.\r
+ * \r
+ */\r
+\r
+/**\r
+ * \r
+ * 1) Basic state monitoring\r
+ *******************************************************************************\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the last I2Cx Event is equal to the one passed\r
+ * as parameter.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_EVENT: specifies the event to be checked. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 \r
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32f10x_i2c.h file.\r
+ * \r
+ * @retval An ErrorStatus enumuration value:\r
+ * - SUCCESS: Last event is equal to the I2C_EVENT\r
+ * - ERROR: Last event is different from the I2C_EVENT\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_EVENT(I2C_EVENT));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_Mask;\r
+\r
+ /* Check whether the last event contains the I2C_EVENT */\r
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \r
+ * 2) Advanced state monitoring\r
+ *******************************************************************************\r
+ */\r
+\r
+/**\r
+ * @brief Returns the last I2Cx Event.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32f10x_i2c.h file.\r
+ * \r
+ * @retval The last event\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_Mask;\r
+\r
+ /* Return status */\r
+ return lastevent;\r
+}\r
+\r
+/**\r
+ * \r
+ * 3) Flag-based state monitoring\r
+ *******************************************************************************\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C flag is set or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
+ * @arg I2C_FLAG_BUSY: Bus busy flag\r
+ * @arg I2C_FLAG_MSL: Master/Slave flag\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ __IO uint32_t i2creg = 0, i2cxbase = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
+\r
+ /* Get the I2Cx peripheral base address */\r
+ i2cxbase = (uint32_t)I2Cx;\r
+ \r
+ /* Read flag register index */\r
+ i2creg = I2C_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_FLAG &= FLAG_Mask;\r
+ \r
+ if(i2creg != 0)\r
+ {\r
+ /* Get the I2Cx SR1 register address */\r
+ i2cxbase += 0x14;\r
+ }\r
+ else\r
+ {\r
+ /* Flag in I2Cx SR2 Register */\r
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
+ /* Get the I2Cx SR2 register address */\r
+ i2cxbase += 0x18;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the I2C_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Clears the I2Cx's pending flags.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
+ * second byte of the address in DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
+ * register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_FLAG & FLAG_Mask;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C interrupt has occurred or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_IT_PECERR: PEC error in reception flag\r
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure flag\r
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error flag\r
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_IT_BTF: Byte transfer finished flag\r
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_IT_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_IT (SET or RESET).\r
+ */\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_IT(I2C_IT));\r
+\r
+ /* Check if the interrupt source is enabled or not */\r
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_IT &= FLAG_Mask;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx\92s interrupt pending bits.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure interrupt\r
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error interrupt\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
+ * byte of the address in I2C_DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_DR register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_IT & FLAG_Mask;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the IWDG firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_iwdg.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG \r
+ * @brief IWDG driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup IWDG_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* ---------------------- IWDG registers bit mask ----------------------------*/\r
+\r
+/* KR register bit mask */\r
+#define KR_KEY_Reload ((uint16_t)0xAAAA)\r
+#define KR_KEY_Enable ((uint16_t)0xCCCC)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup IWDG_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
+ * @retval None\r
+ */\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
+ IWDG->KR = IWDG_WriteAccess;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Prescaler value.\r
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
+ * @retval None\r
+ */\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
+ IWDG->PR = IWDG_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Reload value.\r
+ * @param Reload: specifies the IWDG Reload value.\r
+ * This parameter must be a number between 0 and 0x0FFF.\r
+ * @retval None\r
+ */\r
+void IWDG_SetReload(uint16_t Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_RELOAD(Reload));\r
+ IWDG->RLR = Reload;\r
+}\r
+\r
+/**\r
+ * @brief Reloads IWDG counter with value defined in the reload register\r
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = KR_KEY_Reload;\r
+}\r
+\r
+/**\r
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = KR_KEY_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified IWDG flag is set or not.\r
+ * @param IWDG_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
+ * @retval The new state of IWDG_FLAG (SET or RESET).\r
+ */\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the PWR firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_pwr.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR \r
+ * @brief PWR driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber 0x08\r
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber 0x04\r
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber 0x08\r
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables access to the RTC and backup registers.\r
+ * @param NewState: new state of the access to the RTC and backup registers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_BackupAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Power Voltage Detector(PVD).\r
+ * @param NewState: new state of the PVD.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param PWR_PVDLevel: specifies the PVD detection level\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V\r
+ * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V\r
+ * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V\r
+ * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V\r
+ * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V\r
+ * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V\r
+ * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V\r
+ * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V\r
+ * @retval None\r
+ */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+ tmpreg = PWR->CR;\r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_MASK;\r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the WakeUp Pin functionality.\r
+ * @param NewState: new state of the WakeUp Pin functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_WakeUpPinCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enters STOP mode.\r
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ /* Set LPDS bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ \r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
+}\r
+\r
+/**\r
+ * @brief Enters STANDBY mode.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wake-up flag */\r
+ PWR->CR |= PWR_CR_CWUF;\r
+ /* Select STANDBY mode */\r
+ PWR->CR |= PWR_CR_PDDS;\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM )\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified PWR flag is set or not.\r
+ * @param PWR_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @arg PWR_FLAG_PVDO: PVD Output\r
+ * @retval The new state of PWR_FLAG (SET or RESET).\r
+ */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+ \r
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the PWR's pending flags.\r
+ * @param PWR_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @retval None\r
+ */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+ \r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the RCC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RCC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Alias word address of PLL2ON bit */\r
+ #define PLL2ON_BitNumber 0x1A\r
+ #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))\r
+\r
+ /* Alias word address of PLL3ON bit */\r
+ #define PLL3ON_BitNumber 0x1C\r
+ #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x13\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CFGR Register ---*/\r
+\r
+/* Alias word address of USBPRE bit */\r
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define USBPRE_BitNumber 0x16\r
+ #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))\r
+#else\r
+ #define OTGFSPRE_BitNumber 0x16\r
+ #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* --- BDCR Register ---*/\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)\r
+#define RTCEN_BitNumber 0x0F\r
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of BDRST bit */\r
+#define BDRST_BitNumber 0x10\r
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x24)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+#ifdef STM32F10X_CL\r
+/* --- CFGR2 Register ---*/\r
+\r
+ /* Alias word address of I2S2SRC bit */\r
+ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)\r
+ #define I2S2SRC_BitNumber 0x11\r
+ #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))\r
+\r
+ /* Alias word address of I2S3SRC bit */\r
+ #define I2S3SRC_BitNumber 0x12\r
+ #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))\r
+#endif /* STM32F10X_CL */\r
+\r
+/* ---------------------- RCC registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)\r
+#define CR_HSEBYP_Set ((uint32_t)0x00040000)\r
+#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)\r
+#define CR_HSEON_Set ((uint32_t)0x00010000)\r
+#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)\r
+\r
+/* CFGR register bit mask */\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) \r
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)\r
+#else\r
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)\r
+#endif /* STM32F10X_CL */ \r
+\r
+#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)\r
+#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)\r
+#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)\r
+#define CFGR_SWS_Mask ((uint32_t)0x0000000C)\r
+#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)\r
+#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)\r
+#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)\r
+#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)\r
+#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)\r
+#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)\r
+#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)\r
+#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)\r
+#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)\r
+\r
+/* CSR register bit mask */\r
+#define CSR_RMVF_Set ((uint32_t)0x01000000)\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) \r
+/* CFGR2 register bit mask */\r
+ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)\r
+ #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)\r
+#endif\r
+#ifdef STM32F10X_CL\r
+ #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)\r
+ #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)\r
+ #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* RCC Flag Mask */\r
+#define FLAG_Mask ((uint8_t)0x1F)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)\r
+\r
+/* BDCR register base address */\r
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Private_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Private_Variables\r
+ * @{\r
+ */ \r
+\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */ \r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000; \r
+#else\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#endif /* STM32F10X_CL */\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.\r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: HSE oscillator OFF\r
+ * @arg RCC_HSE_ON: HSE oscillator ON\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint32_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ /* Reset HSEON bit */\r
+ RCC->CR &= CR_HSEON_Reset;\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= CR_HSEBYP_Reset;\r
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */\r
+ switch(RCC_HSE)\r
+ {\r
+ case RCC_HSE_ON:\r
+ /* Set HSEON bit */\r
+ RCC->CR |= CR_HSEON_Set;\r
+ break;\r
+ \r
+ case RCC_HSE_Bypass:\r
+ /* Set HSEBYP and HSEON bits */\r
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @param None\r
+ * @retval An ErrorStatus enumuration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus HSEStatus = RESET;\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+ \r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @param HSICalibrationValue: specifies the calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r
+ tmpreg = RCC->CR;\r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= CR_HSITRIM_Mask;\r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.\r
+ * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL clock source and multiplication factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, \r
+ * this parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry\r
+ * For @b other_STM32_devices, this parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
+ * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry \r
+ * @param RCC_PLLMul: specifies the PLL multiplication factor.\r
+ * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}\r
+ * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] \r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
+ tmpreg &= CFGR_PLL_Mask;\r
+ /* Set the PLL configuration bits */\r
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLL.\r
+ * @note The PLL can not be disabled if it is used as system clock.\r
+ * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)\r
+/**\r
+ * @brief Configures the PREDIV1 division factor.\r
+ * @note \r
+ * - This function must be used only when the PLL is disabled.\r
+ * - This function applies only to STM32 Connectivity line and Value line \r
+ * devices.\r
+ * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock\r
+ * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock\r
+ * @note \r
+ * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE \r
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.\r
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]\r
+ * @retval None\r
+ */\r
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));\r
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PREDIV1[3:0] and PREDIV1SRC bits */\r
+ tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);\r
+ /* Set the PREDIV1 clock source and division factor */\r
+ tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+#endif\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Configures the PREDIV2 division factor.\r
+ * @note \r
+ * - This function must be used only when both PLL2 and PLL3 are disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.\r
+ * This parameter can be RCC_PREDIV2_Divx where x:[1,16]\r
+ * @retval None\r
+ */\r
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PREDIV2[3:0] bits */\r
+ tmpreg &= ~CFGR2_PREDIV2;\r
+ /* Set the PREDIV2 division factor */\r
+ tmpreg |= RCC_PREDIV2_Div;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL2 multiplication factor.\r
+ * @note\r
+ * - This function must be used only when the PLL2 is disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.\r
+ * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}\r
+ * @retval None\r
+ */\r
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PLL2Mul[3:0] bits */\r
+ tmpreg &= ~CFGR2_PLL2MUL;\r
+ /* Set the PLL2 configuration bits */\r
+ tmpreg |= RCC_PLL2Mul;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the PLL2.\r
+ * @note \r
+ * - The PLL2 can not be disabled if it is used indirectly as system clock\r
+ * (i.e. it is used as PLL clock entry that is used as System clock).\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLL2Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the PLL3 multiplication factor.\r
+ * @note \r
+ * - This function must be used only when the PLL3 is disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.\r
+ * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}\r
+ * @retval None\r
+ */\r
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PLL3Mul[3:0] bits */\r
+ tmpreg &= ~CFGR2_PLL3MUL;\r
+ /* Set the PLL3 configuration bits */\r
+ tmpreg |= RCC_PLL3Mul;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the PLL3.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLL3Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;\r
+}\r
+#endif /* STM32F10X_CL */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= CFGR_SW_Mask;\r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can\r
+ * be one of the following:\r
+ * - 0x00: HSI used as system clock\r
+ * - 0x04: HSE used as system clock\r
+ * - 0x08: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= CFGR_HPRE_Reset_Mask;\r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Low Speed APB clock (PCLK1).\r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= CFGR_PPRE1_Reset_Mask;\r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed APB clock (PCLK2).\r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= CFGR_PPRE2_Reset_Mask;\r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the \r
+ * following values \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * \r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+#ifndef STM32F10X_CL\r
+/**\r
+ * @brief Configures the USB clock (USBCLK).\r
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is \r
+ * derived from the PLL output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB \r
+ * clock source\r
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source\r
+ * @retval None\r
+ */\r
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;\r
+}\r
+#else\r
+/**\r
+ * @brief Configures the USB OTG FS clock (OTGFSCLK).\r
+ * This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.\r
+ * This clock is derived from the PLL output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
+ * @retval None\r
+ */\r
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;\r
+}\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @brief Configures the ADC clock (ADCCLK).\r
+ * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from \r
+ * the APB2 clock (PCLK2).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2\r
+ * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4\r
+ * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6\r
+ * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8\r
+ * @retval None\r
+ */\r
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear ADCPRE[1:0] bits */\r
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;\r
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */\r
+ tmpreg |= RCC_PCLK2;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Configures the I2S2 clock source(I2S2CLK).\r
+ * @note\r
+ * - This function must be called before enabling I2S2 APB clock.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry\r
+ * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry\r
+ * @retval None\r
+ */\r
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Configures the I2S3 clock source(I2S2CLK).\r
+ * @note\r
+ * - This function must be called before enabling I2S3 APB clock.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry\r
+ * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry\r
+ * @retval None\r
+ */\r
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;\r
+}\r
+#endif /* STM32F10X_CL */\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: LSE oscillator OFF\r
+ * @arg RCC_LSE_ON: LSE oscillator ON\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ /* Reset LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+ /* Reset LSEBYP bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r
+ switch(RCC_LSE)\r
+ {\r
+ case RCC_LSE_ON:\r
+ /* Set LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;\r
+ break;\r
+ \r
+ case RCC_LSE_Bypass:\r
+ /* Set LSEBYP and LSEON bits */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;\r
+ break; \r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the RTC clock (RTCCLK).\r
+ * @note Once the RTC clock is selected it can\92t be changed unless the Backup domain is reset.\r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+ /* Select the RTC clock source */\r
+ RCC->BDCR |= RCC_RTCCLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of different on chip clocks.\r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold\r
+ * the clocks frequencies.\r
+ * @note The result of this function could be not correct when using \r
+ * fractional value for HSE crystal. \r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;\r
+\r
+#ifdef STM32F10X_CL\r
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;\r
+#endif /* STM32F10X_CL */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ uint32_t prediv1factor = 0;\r
+#endif\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & CFGR_SWS_Mask;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock */\r
+\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;\r
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;\r
+ \r
+#ifndef STM32F10X_CL \r
+ pllmull = ( pllmull >> 18) + 2;\r
+ \r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
+ /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; \r
+ #else\r
+ /* HSE selected as PLL clock entry */\r
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)\r
+ {/* HSE oscillator clock divided by 2 */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;\r
+ }\r
+ #endif\r
+ }\r
+#else\r
+ pllmull = pllmull >> 18;\r
+ \r
+ if (pllmull != 0x0D)\r
+ {\r
+ pllmull += 2;\r
+ }\r
+ else\r
+ { /* PLL multiplication factor = PLL input clock * 6.5 */\r
+ pllmull = 13 / 2; \r
+ }\r
+ \r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {/* PREDIV1 selected as PLL clock entry */\r
+ \r
+ /* Get PREDIV1 clock source and division factor */\r
+ prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;\r
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
+ \r
+ if (prediv1source == 0)\r
+ { /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; \r
+ }\r
+ else\r
+ {/* PLL2 clock selected as PREDIV1 clock entry */\r
+ \r
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */\r
+ prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;\r
+ pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; \r
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; \r
+ }\r
+ }\r
+#endif /* STM32F10X_CL */ \r
+ break;\r
+\r
+ default:\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ }\r
+\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+ /* Get ADCCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;\r
+ tmp = tmp >> 14;\r
+ presc = ADCPrescTable[tmp];\r
+ /* ADCCLK clock frequency */\r
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values: \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @arg RCC_AHBPeriph_DMA2\r
+ * @arg RCC_AHBPeriph_SRAM\r
+ * @arg RCC_AHBPeriph_FLITF\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_OTG_FS \r
+ * @arg RCC_AHBPeriph_ETH_MAC \r
+ * @arg RCC_AHBPeriph_ETH_MAC_Tx\r
+ * @arg RCC_AHBPeriph_ETH_MAC_Rx\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the \r
+ * following values: \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @arg RCC_AHBPeriph_DMA2\r
+ * @arg RCC_AHBPeriph_SRAM\r
+ * @arg RCC_AHBPeriph_FLITF\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FSMC\r
+ * @arg RCC_AHBPeriph_SDIO\r
+ * \r
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_OTG_FS \r
+ * @arg RCC_AHBPeriph_ETH_MAC\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBRSTR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the Backup domain reset.\r
+ * @param NewState: new state of the Backup domain reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_BackupResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @param NewState: new state of the Clock Security System..\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin.\r
+ * @param RCC_MCO: specifies the clock source to output.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values: \r
+ * @arg RCC_MCO_NoClock: No clock selected\r
+ * @arg RCC_MCO_SYSCLK: System clock selected\r
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+ * @arg RCC_MCO_PLL2CLK: PLL2 clock selected \r
+ * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected \r
+ * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected \r
+ * @arg RCC_MCO_PLL3CLK: PLL3 clock selected \r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_MCO_NoClock: No clock selected\r
+ * @arg RCC_MCO_SYSCLK: System clock selected\r
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_MCOConfig(uint8_t RCC_MCO)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCO));\r
+\r
+ /* Perform Byte access to MCO bits to select the MCO source */\r
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready \r
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready \r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * \r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else if (tmp == 2) /* The flag to check is in BDCR register */\r
+ {\r
+ statusreg = RCC->BDCR;\r
+ }\r
+ else /* The flag to check is in CSR register */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_Mask;\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= CSR_RMVF_Set;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+\r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC\92s interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the\r
+ * following values: \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+\r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the RTC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rtc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC \r
+ * @brief RTC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Defines\r
+ * @{\r
+ */\r
+#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */\r
+#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC interrupts.\r
+ * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_OW: Overflow interrupt\r
+ * @arg RTC_IT_ALR: Alarm interrupt\r
+ * @arg RTC_IT_SEC: Second interrupt\r
+ * @param NewState: new state of the specified RTC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_IT(RTC_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RTC->CRH |= RTC_IT;\r
+ }\r
+ else\r
+ {\r
+ RTC->CRH &= (uint16_t)~RTC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the RTC configuration mode.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_EnterConfigMode(void)\r
+{\r
+ /* Set the CNF flag to enter in the Configuration Mode */\r
+ RTC->CRL |= RTC_CRL_CNF;\r
+}\r
+\r
+/**\r
+ * @brief Exits from the RTC configuration mode.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_ExitConfigMode(void)\r
+{\r
+ /* Reset the CNF flag to exit from the Configuration Mode */\r
+ RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); \r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC counter value.\r
+ * @param None\r
+ * @retval RTC counter value.\r
+ */\r
+uint32_t RTC_GetCounter(void)\r
+{\r
+ uint16_t tmp = 0;\r
+ tmp = RTC->CNTL;\r
+ return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;\r
+}\r
+\r
+/**\r
+ * @brief Sets the RTC counter value.\r
+ * @param CounterValue: RTC counter new value.\r
+ * @retval None\r
+ */\r
+void RTC_SetCounter(uint32_t CounterValue)\r
+{ \r
+ RTC_EnterConfigMode();\r
+ /* Set RTC COUNTER MSB word */\r
+ RTC->CNTH = CounterValue >> 16;\r
+ /* Set RTC COUNTER LSB word */\r
+ RTC->CNTL = (CounterValue & RTC_LSB_MASK);\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/**\r
+ * @brief Sets the RTC prescaler value.\r
+ * @param PrescalerValue: RTC prescaler new value.\r
+ * @retval None\r
+ */\r
+void RTC_SetPrescaler(uint32_t PrescalerValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_PRESCALER(PrescalerValue));\r
+ \r
+ RTC_EnterConfigMode();\r
+ /* Set RTC PRESCALER MSB word */\r
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;\r
+ /* Set RTC PRESCALER LSB word */\r
+ RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/**\r
+ * @brief Sets the RTC alarm value.\r
+ * @param AlarmValue: RTC alarm new value.\r
+ * @retval None\r
+ */\r
+void RTC_SetAlarm(uint32_t AlarmValue)\r
+{ \r
+ RTC_EnterConfigMode();\r
+ /* Set the ALARM MSB word */\r
+ RTC->ALRH = AlarmValue >> 16;\r
+ /* Set the ALARM LSB word */\r
+ RTC->ALRL = (AlarmValue & RTC_LSB_MASK);\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC divider value.\r
+ * @param None\r
+ * @retval RTC Divider value.\r
+ */\r
+uint32_t RTC_GetDivider(void)\r
+{\r
+ uint32_t tmp = 0x00;\r
+ tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;\r
+ tmp |= RTC->DIVL;\r
+ return tmp;\r
+}\r
+\r
+/**\r
+ * @brief Waits until last write operation on RTC registers has finished.\r
+ * @note This function must be called before any write to RTC registers.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_WaitForLastTask(void)\r
+{\r
+ /* Loop until RTOFF flag is set */\r
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)\r
+ * are synchronized with RTC APB clock.\r
+ * @note This function must be called before any read operation after an APB reset\r
+ * or an APB clock stop.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_WaitForSynchro(void)\r
+{\r
+ /* Clear RSF flag */\r
+ RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;\r
+ /* Loop until RSF flag is set */\r
+ while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC flag is set or not.\r
+ * @param RTC_FLAG: specifies the flag to check.\r
+ * This parameter can be one the following values:\r
+ * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @arg RTC_FLAG_OW: Overflow flag\r
+ * @arg RTC_FLAG_ALR: Alarm flag\r
+ * @arg RTC_FLAG_SEC: Second flag\r
+ * @retval The new state of RTC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); \r
+ \r
+ if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC\92s pending flags.\r
+ * @param RTC_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after\r
+ * an APB reset or an APB Clock stop.\r
+ * @arg RTC_FLAG_OW: Overflow flag\r
+ * @arg RTC_FLAG_ALR: Alarm flag\r
+ * @arg RTC_FLAG_SEC: Second flag\r
+ * @retval None\r
+ */\r
+void RTC_ClearFlag(uint16_t RTC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); \r
+ \r
+ /* Clear the coressponding RTC flag */\r
+ RTC->CRL &= (uint16_t)~RTC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occured or not.\r
+ * @param RTC_IT: specifies the RTC interrupts sources to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_IT_OW: Overflow interrupt\r
+ * @arg RTC_IT_ALR: Alarm interrupt\r
+ * @arg RTC_IT_SEC: Second interrupt\r
+ * @retval The new state of the RTC_IT (SET or RESET).\r
+ */\r
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_IT(RTC_IT)); \r
+ \r
+ bitstatus = (ITStatus)(RTC->CRL & RTC_IT);\r
+ if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC\92s interrupt pending bits.\r
+ * @param RTC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_OW: Overflow interrupt\r
+ * @arg RTC_IT_ALR: Alarm interrupt\r
+ * @arg RTC_IT_SEC: Second interrupt\r
+ * @retval None\r
+ */\r
+void RTC_ClearITPendingBit(uint16_t RTC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_IT(RTC_IT)); \r
+ \r
+ /* Clear the coressponding RTC pending bit */\r
+ RTC->CRL &= (uint16_t)~RTC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_sdio.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the SDIO firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_sdio.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO \r
+ * @brief SDIO driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SDIO_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+\r
+/* ------------ SDIO registers bit address in the alias region ----------- */\r
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)\r
+\r
+/* --- CLKCR Register ---*/\r
+\r
+/* Alias word address of CLKEN bit */\r
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)\r
+#define CLKEN_BitNumber 0x08\r
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))\r
+\r
+/* --- CMD Register ---*/\r
+\r
+/* Alias word address of SDIOSUSPEND bit */\r
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)\r
+#define SDIOSUSPEND_BitNumber 0x0B\r
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))\r
+\r
+/* Alias word address of ENCMDCOMPL bit */\r
+#define ENCMDCOMPL_BitNumber 0x0C\r
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))\r
+\r
+/* Alias word address of NIEN bit */\r
+#define NIEN_BitNumber 0x0D\r
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))\r
+\r
+/* Alias word address of ATACMD bit */\r
+#define ATACMD_BitNumber 0x0E\r
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))\r
+\r
+/* --- DCTRL Register ---*/\r
+\r
+/* Alias word address of DMAEN bit */\r
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)\r
+#define DMAEN_BitNumber 0x03\r
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))\r
+\r
+/* Alias word address of RWSTART bit */\r
+#define RWSTART_BitNumber 0x08\r
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))\r
+\r
+/* Alias word address of RWSTOP bit */\r
+#define RWSTOP_BitNumber 0x09\r
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))\r
+\r
+/* Alias word address of RWMOD bit */\r
+#define RWMOD_BitNumber 0x0A\r
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))\r
+\r
+/* Alias word address of SDIOEN bit */\r
+#define SDIOEN_BitNumber 0x0B\r
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))\r
+\r
+/* ---------------------- SDIO registers bit mask ------------------------ */\r
+\r
+/* --- CLKCR Register ---*/\r
+\r
+/* CLKCR register clear mask */\r
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) \r
+\r
+/* --- PWRCTRL Register ---*/\r
+\r
+/* SDIO PWRCTRL Mask */\r
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)\r
+\r
+/* --- DCTRL Register ---*/\r
+\r
+/* SDIO DCTRL Clear Mask */\r
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)\r
+\r
+/* --- CMD Register ---*/\r
+\r
+/* CMD Register clear mask */\r
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)\r
+\r
+/* SDIO RESP Registers Address */\r
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SDIO_DeInit(void)\r
+{\r
+ SDIO->POWER = 0x00000000;\r
+ SDIO->CLKCR = 0x00000000;\r
+ SDIO->ARG = 0x00000000;\r
+ SDIO->CMD = 0x00000000;\r
+ SDIO->DTIMER = 0x00000000;\r
+ SDIO->DLEN = 0x00000000;\r
+ SDIO->DCTRL = 0x00000000;\r
+ SDIO->ICR = 0x00C007FF;\r
+ SDIO->MASK = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SDIO peripheral according to the specified \r
+ * parameters in the SDIO_InitStruct.\r
+ * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure \r
+ * that contains the configuration information for the SDIO peripheral.\r
+ * @retval None\r
+ */\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));\r
+ assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));\r
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));\r
+ assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));\r
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); \r
+ \r
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/ \r
+ /* Get the SDIO CLKCR value */\r
+ tmpreg = SDIO->CLKCR;\r
+ \r
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r
+ tmpreg &= CLKCR_CLEAR_MASK;\r
+ \r
+ /* Set CLKDIV bits according to SDIO_ClockDiv value */\r
+ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */\r
+ /* Set BYPASS bit according to SDIO_ClockBypass value */\r
+ /* Set WIDBUS bits according to SDIO_BusWide value */\r
+ /* Set NEGEDGE bits according to SDIO_ClockEdge value */\r
+ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */\r
+ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |\r
+ SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |\r
+ SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); \r
+ \r
+ /* Write to SDIO CLKCR */\r
+ SDIO->CLKCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_InitStruct member with its default value.\r
+ * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which \r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)\r
+{\r
+ /* SDIO_InitStruct members default value */\r
+ SDIO_InitStruct->SDIO_ClockDiv = 0x00;\r
+ SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;\r
+ SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;\r
+ SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;\r
+ SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;\r
+ SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO Clock.\r
+ * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_ClockCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Sets the power status of the controller.\r
+ * @param SDIO_PowerState: new state of the Power state. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_PowerState_OFF\r
+ * @arg SDIO_PowerState_ON\r
+ * @retval None\r
+ */\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));\r
+ \r
+ SDIO->POWER &= PWR_PWRCTRL_MASK;\r
+ SDIO->POWER |= SDIO_PowerState;\r
+}\r
+\r
+/**\r
+ * @brief Gets the power status of the controller.\r
+ * @param None\r
+ * @retval Power status of the controller. The returned value can\r
+ * be one of the following:\r
+ * - 0x00: Power OFF\r
+ * - 0x02: Power UP\r
+ * - 0x03: Power ON \r
+ */\r
+uint32_t SDIO_GetPowerState(void)\r
+{\r
+ return (SDIO->POWER & (~PWR_PWRCTRL_MASK));\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO interrupts.\r
+ * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
+ * @param NewState: new state of the specified SDIO interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None \r
+ */\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_IT(SDIO_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SDIO interrupts */\r
+ SDIO->MASK |= SDIO_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SDIO interrupts */\r
+ SDIO->MASK &= ~SDIO_IT;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO DMA request.\r
+ * @param NewState: new state of the selected SDIO DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_DMACmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SDIO Command according to the specified \r
+ * parameters in the SDIO_CmdInitStruct and send the command.\r
+ * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef \r
+ * structure that contains the configuration information for the SDIO command.\r
+ * @retval None\r
+ */\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));\r
+ assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));\r
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));\r
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));\r
+ \r
+/*---------------------------- SDIO ARG Configuration ------------------------*/\r
+ /* Set the SDIO Argument value */\r
+ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;\r
+ \r
+/*---------------------------- SDIO CMD Configuration ------------------------*/ \r
+ /* Get the SDIO CMD value */\r
+ tmpreg = SDIO->CMD;\r
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r
+ tmpreg &= CMD_CLEAR_MASK;\r
+ /* Set CMDINDEX bits according to SDIO_CmdIndex value */\r
+ /* Set WAITRESP bits according to SDIO_Response value */\r
+ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */\r
+ /* Set CPSMEN bits according to SDIO_CPSM value */\r
+ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response\r
+ | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;\r
+ \r
+ /* Write to SDIO CMD */\r
+ SDIO->CMD = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.\r
+ * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)\r
+{\r
+ /* SDIO_CmdInitStruct members default value */\r
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;\r
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;\r
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;\r
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;\r
+ SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Returns command index of last command for which response received.\r
+ * @param None\r
+ * @retval Returns the command index of the last command response received.\r
+ */\r
+uint8_t SDIO_GetCommandResponse(void)\r
+{\r
+ return (uint8_t)(SDIO->RESPCMD);\r
+}\r
+\r
+/**\r
+ * @brief Returns response received from the card for the last command.\r
+ * @param SDIO_RESP: Specifies the SDIO response register. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_RESP1: Response Register 1\r
+ * @arg SDIO_RESP2: Response Register 2\r
+ * @arg SDIO_RESP3: Response Register 3\r
+ * @arg SDIO_RESP4: Response Register 4\r
+ * @retval The Corresponding response register value.\r
+ */\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_RESP(SDIO_RESP));\r
+\r
+ tmp = SDIO_RESP_ADDR + SDIO_RESP;\r
+ \r
+ return (*(__IO uint32_t *) tmp); \r
+}\r
+\r
+/**\r
+ * @brief Initializes the SDIO data path according to the specified \r
+ * parameters in the SDIO_DataInitStruct.\r
+ * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that\r
+ * contains the configuration information for the SDIO command.\r
+ * @retval None\r
+ */\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));\r
+ assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));\r
+ assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));\r
+ assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));\r
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));\r
+\r
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/\r
+ /* Set the SDIO Data TimeOut value */\r
+ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;\r
+\r
+/*---------------------------- SDIO DLEN Configuration -----------------------*/\r
+ /* Set the SDIO DataLength value */\r
+ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;\r
+\r
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/ \r
+ /* Get the SDIO DCTRL value */\r
+ tmpreg = SDIO->DCTRL;\r
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r
+ tmpreg &= DCTRL_CLEAR_MASK;\r
+ /* Set DEN bit according to SDIO_DPSM value */\r
+ /* Set DTMODE bit according to SDIO_TransferMode value */\r
+ /* Set DTDIR bit according to SDIO_TransferDir value */\r
+ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */\r
+ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir\r
+ | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;\r
+\r
+ /* Write to SDIO DCTRL */\r
+ SDIO->DCTRL = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_DataInitStruct member with its default value.\r
+ * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
+{\r
+ /* SDIO_DataInitStruct members default value */\r
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;\r
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;\r
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;\r
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;\r
+ SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; \r
+ SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Returns number of remaining data bytes to be transferred.\r
+ * @param None\r
+ * @retval Number of remaining data bytes to be transferred\r
+ */\r
+uint32_t SDIO_GetDataCounter(void)\r
+{ \r
+ return SDIO->DCOUNT;\r
+}\r
+\r
+/**\r
+ * @brief Read one data word from Rx FIFO.\r
+ * @param None\r
+ * @retval Data received\r
+ */\r
+uint32_t SDIO_ReadData(void)\r
+{ \r
+ return SDIO->FIFO;\r
+}\r
+\r
+/**\r
+ * @brief Write one data word to Tx FIFO.\r
+ * @param Data: 32-bit data word to write.\r
+ * @retval None\r
+ */\r
+void SDIO_WriteData(uint32_t Data)\r
+{ \r
+ SDIO->FIFO = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of words left to be written to or read from FIFO. \r
+ * @param None\r
+ * @retval Remaining number of words.\r
+ */\r
+uint32_t SDIO_GetFIFOCount(void)\r
+{ \r
+ return SDIO->FIFOCNT;\r
+}\r
+\r
+/**\r
+ * @brief Starts the SD I/O Read Wait operation. \r
+ * @param NewState: new state of the Start SDIO Read Wait operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;\r
+}\r
+\r
+/**\r
+ * @brief Stops the SD I/O Read Wait operation. \r
+ * @param NewState: new state of the Stop SDIO Read Wait operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;\r
+}\r
+\r
+/**\r
+ * @brief Sets one of the two options of inserting read wait interval.\r
+ * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r
+ * This parametre can be:\r
+ * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK\r
+ * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2\r
+ * @retval None\r
+ */\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SD I/O Mode Operation.\r
+ * @param NewState: new state of SDIO specific operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SetSDIOOperation(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SD I/O Mode suspend command sending.\r
+ * @param NewState: new state of the SD I/O Mode suspend command.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the command completion signal.\r
+ * @param NewState: new state of command completion signal. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CE-ATA interrupt.\r
+ * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_CEATAITCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));\r
+}\r
+\r
+/**\r
+ * @brief Sends CE-ATA command (CMD61).\r
+ * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SendCEATACmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SDIO flag is set or not.\r
+ * @param SDIO_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode.\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress\r
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress\r
+ * @arg SDIO_FLAG_RXACT: Data receive in progress\r
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\r
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full\r
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full\r
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty\r
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty\r
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO\r
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval The new state of SDIO_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)\r
+{ \r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));\r
+ \r
+ if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SDIO's pending flags.\r
+ * @param SDIO_FLAG: specifies the flag to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval None\r
+ */\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));\r
+ \r
+ SDIO->ICR = SDIO_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.\r
+ * @param SDIO_IT: specifies the SDIO interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
+ * @retval The new state of SDIO_IT (SET or RESET).\r
+ */\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)\r
+{ \r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_GET_IT(SDIO_IT));\r
+ if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) \r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SDIO\92s interrupt pending bits.\r
+ * @param SDIO_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval None\r
+ */\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));\r
+ \r
+ SDIO->ICR = SDIO_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_spi.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the SPI firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_spi.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI \r
+ * @brief SPI driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SPI_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SPI_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* SPI SPE mask */\r
+#define CR1_SPE_Set ((uint16_t)0x0040)\r
+#define CR1_SPE_Reset ((uint16_t)0xFFBF)\r
+\r
+/* I2S I2SE mask */\r
+#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)\r
+#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)\r
+\r
+/* SPI CRCNext mask */\r
+#define CR1_CRCNext_Set ((uint16_t)0x1000)\r
+\r
+/* SPI CRCEN mask */\r
+#define CR1_CRCEN_Set ((uint16_t)0x2000)\r
+#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)\r
+\r
+/* SPI SSOE mask */\r
+#define CR2_SSOE_Set ((uint16_t)0x0004)\r
+#define CR2_SSOE_Reset ((uint16_t)0xFFFB)\r
+\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_Mask ((uint16_t)0x3040)\r
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
+\r
+/* SPI or I2S mode selection masks */\r
+#define SPI_Mode_Select ((uint16_t)0xF7FF)\r
+#define I2S_Mode_Select ((uint16_t)0x0800) \r
+\r
+/* I2S clock source selection masks */\r
+#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))\r
+#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))\r
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))\r
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPIx peripheral registers to their default\r
+ * reset values (Affects also the I2Ss).\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ if (SPIx == SPI1)\r
+ {\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ }\r
+ else if (SPIx == SPI2)\r
+ {\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (SPIx == SPI3)\r
+ {\r
+ /* Enable SPI3 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
+ /* Release SPI3 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the SPI_InitStruct.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx)); \r
+ \r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+ \r
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
+ SPIx->I2SCFGR &= SPI_Mode_Select; \r
+\r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the I2S_InitStruct.\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral\r
+ * (configured in I2S mode).\r
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral\r
+ * configured in I2S mode.\r
+ * @note\r
+ * The function calculates the optimal prescaler needed to obtain the most \r
+ * accurate audio frequency (depending on the I2S clock source, the PLL values \r
+ * and the product configuration). But in case the prescaler value is greater \r
+ * than 511, the default value (0x02) will be configured instead. * \r
+ * @retval None\r
+ */\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ uint32_t tmp = 0;\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ uint32_t sourceclock = 0;\r
+ \r
+ /* Check the I2S parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
+\r
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
+ SPIx->I2SPR = 0x0002;\r
+ \r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = SPIx->I2SCFGR;\r
+ \r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
+ {\r
+ i2sodd = (uint16_t)0;\r
+ i2sdiv = (uint16_t)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) */\r
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+\r
+ /* Get the I2S clock source mask depending on the peripheral number */\r
+ if(((uint32_t)SPIx) == SPI2_BASE)\r
+ {\r
+ /* The mask is relative to I2S2 */\r
+ tmp = I2S2_CLOCK_SRC;\r
+ }\r
+ else \r
+ {\r
+ /* The mask is relative to I2S3 */ \r
+ tmp = I2S3_CLOCK_SRC;\r
+ }\r
+\r
+ /* Check the I2S clock source configuration depending on the Device:\r
+ Only Connectivity line devices have the PLL3 VCO clock */\r
+#ifdef STM32F10X_CL\r
+ if((RCC->CFGR2 & tmp) != 0)\r
+ {\r
+ /* Get the configuration bits of RCC PLL3 multiplier */\r
+ tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);\r
+\r
+ /* Get the value of the PLL3 multiplier */ \r
+ if((tmp > 5) && (tmp < 15))\r
+ {\r
+ /* Multplier is between 8 and 14 (value 15 is forbidden) */\r
+ tmp += 2;\r
+ }\r
+ else\r
+ {\r
+ if (tmp == 15)\r
+ {\r
+ /* Multiplier is 20 */\r
+ tmp = 20;\r
+ }\r
+ } \r
+ /* Get the PREDIV2 value */\r
+ sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);\r
+ \r
+ /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */\r
+ sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); \r
+ }\r
+ else\r
+ {\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+ \r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;\r
+ } \r
+#else /* STM32F10X_HD */\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+ \r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
+#endif /* STM32F10X_CL */ \r
+\r
+ /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the flaoting point */\r
+ tmp = tmp / 10; \r
+ \r
+ /* Check the parity of the divider */\r
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
+ \r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
+ \r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (uint16_t) (i2sodd << 8);\r
+ }\r
+ \r
+ /* Test if the divider is 1 or 0 or greater than 0xFF */\r
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+\r
+ /* Write to SPIx I2SPR register the computed value */\r
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); \r
+ \r
+ /* Configure the I2S with the SPI_InitStruct values */\r
+ tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
+ \r
+ /* Write to SPIx I2SCFGR */ \r
+ SPIx->I2SCFGR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Fills each SPI_InitStruct member with its default value.\r
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2S_InitStruct member with its default value.\r
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+/*--------------- Reset I2S init structure parameters values -----------------*/\r
+ /* Initialize the I2S_Mode member */\r
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
+ \r
+ /* Initialize the I2S_Standard member */\r
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
+ \r
+ /* Initialize the I2S_DataFormat member */\r
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
+ \r
+ /* Initialize the I2S_MCLKOutput member */\r
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
+ \r
+ /* Initialize the I2S_AudioFreq member */\r
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
+ \r
+ /* Initialize the I2S_CPOL member */\r
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= CR1_SPE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= CR1_SPE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI/I2S interrupts.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified SPI/I2S interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ uint16_t itpos = 0, itmask = 0 ;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 &= (uint16_t)~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
+ * @param NewState: new state of the selected SPI/I2S DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param Data : Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @retval The value of the received data.\r
+ */\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SS output for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx SS output. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= CR2_SSOE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= CR2_SSOE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the data size for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_DataSize: specifies the SPI data size.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
+ * @retval None\r
+ */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+ /* Clear DFF bit */\r
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
+ /* Set new DFF bit value */\r
+ SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/**\r
+ * @brief Transmit the SPIx CRC value.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= CR1_CRCNext_Set;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transfered bytes.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= CR1_CRCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= CR1_CRCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_CRC: specifies the CRC register to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRC_Tx: Selects Tx CRC register\r
+ * @arg SPI_CRC_Rx: Selects Rx CRC register\r
+ * @retval The selected CRC register value..\r
+ */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+ uint16_t crcreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
+ * @arg SPI_Direction_Rx: Selects Rx receive direction\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI/I2S flag is set or not.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
+ * @arg SPI_FLAG_MODF: Mode Fault flag.\r
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.\r
+ * @arg I2S_FLAG_UDR: Underrun Error flag.\r
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.\r
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+ /* Check the status of the specified SPI/I2S flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
+ * This function clears only CRCERR flag.\r
+ * @note\r
+ * - OVR (OverRun error) flag is cleared by software sequence: a read \r
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - UDR (UnderRun error) flag is cleared by a read operation to \r
+ * SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
+ * @arg SPI_IT_MODF: Mode Fault interrupt.\r
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.\r
+ * @arg I2S_IT_UDR: Underrun Error interrupt.\r
+ * @retval The new state of SPI_I2S_IT (SET or RESET).\r
+ */\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Get the SPI/I2S IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = 0x01 << itmask;\r
+\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI/I2S interrupt */\r
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
+ * This function clears only CRCERR intetrrupt pending bit. \r
+ * @note\r
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
+ * the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ uint16_t itpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
+ SPIx->SR = (uint16_t)~itpos;\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_tim.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the TIM firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_tim.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM \r
+ * @brief TIM driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define SMCR_ETR_Mask ((uint16_t)0x00FF) \r
+#define CCMR_Offset ((uint16_t)0x0018)\r
+#define CCER_CCE_Set ((uint16_t)0x0001) \r
+#define CCER_CCNE_Set ((uint16_t)0x0004) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ \r
+ if (TIMx == TIM1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); \r
+ } \r
+ else if (TIMx == TIM2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+ }\r
+ else if (TIMx == TIM3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+ }\r
+ else if (TIMx == TIM4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
+ } \r
+ else if (TIMx == TIM5)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);\r
+ } \r
+ else if (TIMx == TIM6)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
+ } \r
+ else if (TIMx == TIM7)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
+ } \r
+ else if (TIMx == TIM8)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);\r
+ }\r
+ else if (TIMx == TIM9)\r
+ { \r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); \r
+ } \r
+ else if (TIMx == TIM10)\r
+ { \r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); \r
+ } \r
+ else if (TIMx == TIM11) \r
+ { \r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
+ } \r
+ else if (TIMx == TIM12)\r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); \r
+ } \r
+ else if (TIMx == TIM13) \r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); \r
+ }\r
+ else if (TIMx == TIM14) \r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); \r
+ } \r
+ else if (TIMx == TIM15)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);\r
+ } \r
+ else if (TIMx == TIM16)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (TIMx == TIM17)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);\r
+ } \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Time Base Unit peripheral according to \r
+ * the specified parameters in the TIM_TimeBaseInitStruct.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+\r
+ tmpcr1 = TIMx->CR1; \r
+\r
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||\r
+ (TIMx == TIM4) || (TIMx == TIM5)) \r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+ }\r
+ \r
+ if((TIMx != TIM6) && (TIMx != TIM7))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+ \r
+ if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) \r
+ {\r
+ /* Set the Repetition Counter value */\r
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;\r
+ }\r
+\r
+ /* Generate an update event to reload the Prescaler and the Repetition counter\r
+ values immediately */\r
+ TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel1 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||\r
+ (TIMx == TIM16)|| (TIMx == TIM17))\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;\r
+ \r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); \r
+ /* Set the Output N State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;\r
+ \r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));\r
+ \r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; \r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel2 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8))\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);\r
+ \r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); \r
+ /* Set the Output N State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);\r
+ \r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));\r
+ \r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel3 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8))\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);\r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));\r
+ \r
+ /* Set the Output N State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);\r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel4 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8))\r
+ {\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ /* Reset the Ouput Compare IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); \r
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* TI3 Configuration */\r
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* TI4 Configuration */\r
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Rising;\r
+ }\r
+ /* Select the Opposite Input */\r
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+ {\r
+ icoppositeselection = TIM_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ icoppositeselection = TIM_ICSelection_DirectTI;\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,\r
+ * the OSSR State and the AOE(automatic output enable).\r
+ * @param TIMx: where x can be 1 or 8 to select the TIM \r
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that\r
+ * contains the BDTR Register configuration information for the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));\r
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));\r
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));\r
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));\r
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));\r
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));\r
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |\r
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |\r
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |\r
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_OCInitStruct member with its default value.\r
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;\r
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;\r
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;\r
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_ICInitStruct member with its default value.\r
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.\r
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;\r
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;\r
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;\r
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;\r
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;\r
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;\r
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM peripheral.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIMx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Counter */\r
+ TIMx->CR1 |= TIM_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Counter */\r
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM peripheral Main Outputs.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIM peripheral Main Outputs.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Main Output */\r
+ TIMx->BDTR |= TIM_BDTR_MOE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Main Output */\r
+ TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM interrupts.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update interrupt.\r
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
+ * TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @param NewState: new state of the TIM interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIMx->DIER |= TIM_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx event to be generate by software.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_EventSource: specifies the event source.\r
+ * This parameter can be one or more of the following values: \r
+ * @arg TIM_EventSource_Update: Timer update Event source\r
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EventSource_COM: Timer COM event source \r
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
+ * @arg TIM_EventSource_Break: Timer Break event source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update event. \r
+ * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. \r
+ * @retval None\r
+ */\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));\r
+ \r
+ /* Set the event sources */\r
+ TIMx->EGR = TIM_EventSource;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx\92s DMA interface.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_DMABase: DMA Base address.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
+ * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,\r
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
+ * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,\r
+ * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,\r
+ * TIM_DMABase_DCR.\r
+ * @param TIM_DMABurstLength: DMA Burst length.\r
+ * This parameter can be one value between:\r
+ * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
+ * @retval None\r
+ */\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase));\r
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s DMA Requests.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 \r
+ * to select the TIM peripheral. \r
+ * @param TIM_DMASource: specifies the DMA Request sources.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_DMA_Update: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST9_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ TIMx->DIER |= TIM_DMASource; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx interrnal Clock\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15\r
+ * to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Internal Trigger as External Clock\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ITRSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @param TIM_TS_ITR0: Internal Trigger 0\r
+ * @param TIM_TS_ITR1: Internal Trigger 1\r
+ * @param TIM_TS_ITR2: Internal Trigger 2\r
+ * @param TIM_TS_ITR3: Internal Trigger 3\r
+ * @retval None\r
+ */\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Select the Internal Trigger */\r
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Trigger as External Clock\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_TIxExternalCLKSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
+ * @param TIM_ICPolarity: specifies the TIx Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param ICFilter : specifies the filter value.\r
+ * This parameter must be a value between 0x0 and 0xF.\r
+ * @retval None\r
+ */\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_FILTER(ICFilter));\r
+ /* Configure the Timer Input Clock Source */\r
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ /* Select the Trigger source */\r
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode1\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ /* Select the External clock mode1 */\r
+ tmpsmcr |= TIM_SlaveMode_External1;\r
+ /* Select the Trigger selection : ETRF */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ tmpsmcr |= TIM_TS_ETRF;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode2\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ /* Enable the External clock mode2 */\r
+ TIMx->SMCR |= TIM_SMCR_ECE;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= SMCR_ETR_Mask;\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Prescaler.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param Prescaler: specifies the Prescaler Register value\r
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.\r
+ * @retval None\r
+ */\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Prescaler;\r
+ /* Set or reset the UG Bit */\r
+ TIMx->EGR = TIM_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Specifies the TIMx Counter Mode to be used.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_CounterMode: specifies the Counter Mode to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+ * @retval None\r
+ */\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+ tmpcr1 = TIMx->CR1;\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM_CounterMode;\r
+ /* Write to TIMx CR1 register */\r
+ TIMx->CR1 = tmpcr1;\r
+}\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_InputTriggerSource: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= TIM_InputTriggerSource;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Encoder Interface.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
+ * on the level of the other input.\r
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @retval None\r
+ */\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ uint16_t tmpccmr1 = 0;\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ tmpsmcr |= TIM_EncoderMode;\r
+ \r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
+ \r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
+ \r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx peripheral Preload register\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ARR Preload Bit */\r
+ TIMx->CR1 |= TIM_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ARR Preload Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM peripheral Commutation event.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral\r
+ * @param NewState: new state of the Commutation event.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the COM Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCUS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the COM Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
+ * the TIM peripheral.\r
+ * @param NewState: new state of the Capture Compare DMA source\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCDS Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCDS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCDS Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 \r
+ * to select the TIMx peripheral\r
+ * @param NewState: new state of the Capture Compare Preload Control bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCPC Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCPC;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCPC Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 1 Fast feature.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 2 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 3 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 4 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF1 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OC1CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF2 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF3 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF4 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 1 polarity.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
+ tmpccer |= TIM_OCPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 1N polarity.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_OCNPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 2 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 2N polarity.\r
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);\r
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 3 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC3 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 3N polarity.\r
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);\r
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 4 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC4 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC4P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
+ assert_param(IS_TIM_CCX(TIM_CCx));\r
+\r
+ tmp = CCER_CCE_Set << TIM_Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t)~ tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel xN.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.\r
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));\r
+ assert_param(IS_TIM_CCXN(TIM_CCxN));\r
+\r
+ tmp = CCER_CCNE_Set << TIM_Channel;\r
+\r
+ /* Reset the CCxNE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp;\r
+\r
+ /* Set or reset the CCxNE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM Ouput Compare Mode.\r
+ * @note This function disables the selected channel before changing the Ouput\r
+ * Compare Mode.\r
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_OCMode_Timing\r
+ * @arg TIM_OCMode_Active\r
+ * @arg TIM_OCMode_Toggle\r
+ * @arg TIM_OCMode_PWM1\r
+ * @arg TIM_OCMode_PWM2\r
+ * @arg TIM_ForcedAction_Active\r
+ * @arg TIM_ForcedAction_InActive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint16_t tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
+ assert_param(IS_TIM_OCM(TIM_OCMode));\r
+\r
+ tmp = (uint32_t) TIMx;\r
+ tmp += CCMR_Offset;\r
+\r
+ tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;\r
+\r
+ /* Disable the Channel: Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp1;\r
+\r
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
+ {\r
+ tmp += (TIM_Channel>>1);\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= TIM_OCMode;\r
+ }\r
+ else\r
+ {\r
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIMx Update event.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx UDIS bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the Update Disable Bit */\r
+ TIMx->CR1 |= TIM_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the Update Disable Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Update Request Interrupt source.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_UpdateSource: specifies the Update source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller.\r
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
+ {\r
+ /* Set the URS Bit */\r
+ TIMx->CR1 |= TIM_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the URS Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx Hall sensor interface.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the TI1S Bit */\r
+ TIMx->CR2 |= TIM_CR2_TI1S;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the TI1S Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx\92s One Pulse Mode.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_OPMode: specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMode_Single\r
+ * @arg TIM_OPMode_Repetitive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
+ /* Reset the OPM Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
+ /* Configure the OPM Mode */\r
+ TIMx->CR1 |= TIM_OPMode;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Trigger Output Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_TRGOSource: specifies the Trigger Output source.\r
+ * This paramter can be one of the following values:\r
+ *\r
+ * - For all TIMx\r
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
+ *\r
+ * - For all TIMx except TIM6 and TIM7\r
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
+ * is to be set, as soon as a capture or compare match occurs (TRGO).\r
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
+ *\r
+ * @retval None\r
+ */\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST7_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+ /* Reset the MMS Bits */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
+ /* Select the TRGO source */\r
+ TIMx->CR2 |= TIM_TRGOSource;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Slave Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
+ * the counter and triggers an update of the registers.\r
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
+ * @retval None\r
+ */\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+ /* Reset the SMS Bits */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
+ /* Select the Slave Mode */\r
+ TIMx->SMCR |= TIM_SlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIMx Master/Slave Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
+ * and its slaves (through TRGO).\r
+ * @arg TIM_MasterSlaveMode_Disable: No action\r
+ * @retval None\r
+ */\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+ /* Reset the MSM Bit */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
+ \r
+ /* Set or Reset the MSM Bit */\r
+ TIMx->SMCR |= TIM_MasterSlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Counter Register value\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param Counter: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Set the Counter Register value */\r
+ TIMx->CNT = Counter;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Autoreload Register value\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param Autoreload: specifies the Autoreload register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Set the Autoreload Register value */\r
+ TIMx->ARR = Autoreload;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare1 Register value\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param Compare1: specifies the Capture Compare1 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ /* Set the Capture Compare1 Register value */\r
+ TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare2 Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param Compare2: specifies the Capture Compare2 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Set the Capture Compare2 Register value */\r
+ TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare3 Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param Compare3: specifies the Capture Compare3 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* Set the Capture Compare3 Register value */\r
+ TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare4 Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param Compare4: specifies the Capture Compare4 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* Set the Capture Compare4 Register value */\r
+ TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 1 prescaler.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC1PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
+ /* Set the IC1PSC value */\r
+ TIMx->CCMR1 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 2 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC2PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
+ /* Set the IC2PSC value */\r
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 3 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC3PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
+ /* Set the IC3PSC value */\r
+ TIMx->CCMR2 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 4 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC4PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
+ /* Set the IC4PSC value */\r
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Clock Division value.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_CKD: specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
+ * @retval None\r
+ */\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
+ /* Reset the CKD Bits */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
+ /* Set the CKD value */\r
+ TIMx->CR1 |= TIM_CKD;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 1 value.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ /* Get the Capture 1 Register value */\r
+ return TIMx->CCR1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 2 value.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Get the Capture 2 Register value */\r
+ return TIMx->CCR2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 3 value.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ /* Get the Capture 3 Register value */\r
+ return TIMx->CCR3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 4 value.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @retval Capture Compare 4 Register value.\r
+ */\r
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* Get the Capture 4 Register value */\r
+ return TIMx->CCR4;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Counter value.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @retval Counter Register value.\r
+ */\r
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Get the Counter Register value */\r
+ return TIMx->CNT;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Prescaler value.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @retval Prescaler Register value.\r
+ */\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Get the Prescaler Register value */\r
+ return TIMx->PSC;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM flag is set or not.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_COM: TIM Commutation Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_Break: TIM Break Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag. \r
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval The new state of TIM_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ ITStatus bitstatus = RESET; \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
+ \r
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's pending flags.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_COM: TIM Commutation Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_Break: TIM Break Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag. \r
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval None\r
+ */\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ TIMx->SR = (uint16_t)~TIM_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM interrupt has occurred or not.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
+ * TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval The new state of the TIM_IT(SET or RESET).\r
+ */\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ ITStatus bitstatus = RESET; \r
+ uint16_t itstatus = 0x0, itenable = 0x0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_IT(TIM_IT));\r
+ \r
+ itstatus = TIMx->SR & TIM_IT;\r
+ \r
+ itenable = TIMx->DIER & TIM_IT;\r
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's interrupt pending bits.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM1 update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
+ * TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval None\r
+ */\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ /* Clear the IT pending Bit */\r
+ TIMx->SR = (uint16_t)~TIM_IT;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0;\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ }\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 4);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);\r
+ }\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 8);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);\r
+ }\r
+ \r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 12);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);\r
+ }\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_usart.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the USART firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_usart.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART \r
+ * @brief USART driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */\r
+#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */\r
+\r
+#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */\r
+\r
+#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */\r
+#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */\r
+#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */\r
+#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */\r
+#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */\r
+\r
+#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */\r
+#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */\r
+\r
+#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */\r
+#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */\r
+#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */\r
+\r
+#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */\r
+#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */\r
+\r
+#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */\r
+#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */\r
+\r
+#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */\r
+#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */\r
+\r
+#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */\r
+#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */\r
+\r
+#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */\r
+#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */\r
+#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */\r
+#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */\r
+#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */\r
+\r
+/* USART OverSampling-8 Mask */\r
+#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */\r
+#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */\r
+\r
+/* USART One Bit Sampling Mask */\r
+#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */\r
+#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval None\r
+ */\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ if (USARTx == USART1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ }\r
+ else if (USARTx == USART2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ }\r
+ else if (USARTx == USART3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
+ } \r
+ else if (USARTx == UART4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (USARTx == UART5)\r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral according to the specified\r
+ * parameters in the USART_InitStruct .\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * that contains the configuration information for the specified USART peripheral.\r
+ * @retval None\r
+ */\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00, apbclock = 0x00;\r
+ uint32_t integerdivider = 0x00;\r
+ uint32_t fractionaldivider = 0x00;\r
+ uint32_t usartxbase = 0;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */\r
+ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ }\r
+\r
+ usartxbase = (uint32_t)USARTx;\r
+\r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12] bits */\r
+ tmpreg &= CR2_STOP_CLEAR_Mask;\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_StopBits value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
+ \r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/ \r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= CR3_CLEAR_Mask;\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ if (usartxbase == USART1_BASE)\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+ }\r
+ \r
+ /* Determine the integer part */\r
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 8 Samples */\r
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 16 Samples */\r
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ tmpreg = (integerdivider / 100) << 4;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
+\r
+ /* Implement the fractional part in the register */\r
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
+ }\r
+ \r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_InitStruct member with its default value.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 9600;\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral Clock according to the \r
+ * specified parameters in the USART_ClockInitStruct .\r
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure that contains the configuration information for the specified \r
+ * USART peripheral. \r
+ * @note The Smart Card mode is not available for UART4 and UART5.\r
+ * @retval None\r
+ */\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
+ tmpreg &= CR2_CLOCK_CLEAR_Mask;\r
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set CLKEN bit according to USART_Clock value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_ClockInitStruct member with its default value.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ /* USART_ClockInitStruct members default value */\r
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART peripheral.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USARTx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_UE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_UE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART interrupts.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @param NewState: new state of the specified USARTx interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
+{\r
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+ uint32_t usartxbase = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ /* The CTS interrupt is not available for UART4 and UART5 */\r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ usartxbase = (uint32_t)USARTx;\r
+\r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & IT_Mask;\r
+ itmask = (((uint32_t)0x01) << itpos);\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ usartxbase += 0x0C;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ usartxbase += 0x10;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ usartxbase += 0x14; \r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(__IO uint32_t*)usartxbase |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint32_t*)usartxbase &= ~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s DMA interface.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_DMAReq: specifies the DMA request.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_DMAReq_Tx: USART DMA transmit request\r
+ * @arg USART_DMAReq_Rx: USART DMA receive request\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note The DMA mode is not available for UART5 except in the STM32\r
+ * High density value line devices(STM32F10X_HD_VL). \r
+ * @retval None\r
+ */\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the address of the USART node.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_Address: Indicates the address of the USART node.\r
+ * @retval None\r
+ */\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_ADDRESS(USART_Address)); \r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= CR2_Address_Mask;\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/**\r
+ * @brief Selects the USART WakeUp method.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_WakeUp: specifies the USART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
+ * @retval None\r
+ */\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
+ \r
+ USARTx->CR1 &= CR1_WAKE_Mask;\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the USART is in mute mode or not.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART mute mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_RWU_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_RWU_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the USART LIN Break detection length.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
+ * @retval None\r
+ */\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+ \r
+ USARTx->CR2 &= CR2_LBDL_Mask;\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s LIN mode.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART LIN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ USARTx->CR2 |= CR2_LINEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+ USARTx->CR2 &= CR2_LINEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits single data through the USARTx peripheral.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->DR = (Data & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the USARTx peripheral.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval The received data.\r
+ */\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Receive Data */\r
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval None\r
+ */\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Send break characters */\r
+ USARTx->CR1 |= CR1_SBK_Set;\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified USART guard time.\r
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
+ * @param USART_GuardTime: specifies the guard time.\r
+ * @note The guard time bits are not available for UART4 and UART5. \r
+ * @retval None\r
+ */\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= GTPR_LSB_Mask;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_Prescaler: specifies the prescaler clock. \r
+ * @note The function is used for IrDA mode with UART4 and UART5.\r
+ * @retval None\r
+ */\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= GTPR_MSB_Mask;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Smart Card mode.\r
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @note The Smart Card mode is not available for UART4 and UART5. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_SCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_SCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. \r
+ * @param NewState: new state of the NACK transmission.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @note The Smart Card mode is not available for UART4 and UART5.\r
+ * @retval None\r
+ */\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_NACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_NACK_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Half Duplex communication.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART Communication.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_HDSEL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_HDSEL_Reset;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the USART's 8x oversampling mode.\r
+ * @param USARTx: Select the USART or the UART peripheral.\r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART one bit sampling methode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note\r
+ * This function has to be called before calling USART_Init()\r
+ * function in order to have correct baudrate Divider value. \r
+ * @retval None\r
+ */\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_OVER8_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_OVER8_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's one bit sampling methode.\r
+ * @param USARTx: Select the USART or the UART peripheral.\r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART one bit sampling methode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_ONEBITE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_ONEBITE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IrDAMode: specifies the IrDA mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IrDAMode_LowPower\r
+ * @arg USART_IrDAMode_Normal\r
+ * @retval None\r
+ */\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+ \r
+ USARTx->CR3 &= CR3_IRLP_Mask;\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_IREN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_IREN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART flag is set or not.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag\r
+ * @arg USART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg USART_FLAG_TC: Transmission Complete flag\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg USART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg USART_FLAG_ORE: OverRun Error flag\r
+ * @arg USART_FLAG_NE: Noise Error flag\r
+ * @arg USART_FLAG_FE: Framing Error flag\r
+ * @arg USART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of USART_FLAG (SET or RESET).\r
+ */\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_FLAG(USART_FLAG));\r
+ /* The CTS flag is not available for UART4 and UART5 */\r
+ if (USART_FLAG == USART_FLAG_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's pending flags.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) flags are cleared by software \r
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
+ * - RXNE flag can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC flag can be also cleared by software sequence: a read operation to \r
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
+ * to USART_DR register (USART_SendData()).\r
+ * - TXE flag is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+ /* The CTS flag is not available for UART4 and UART5 */\r
+ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ USARTx->SR = (uint16_t)~USART_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART interrupt has occurred or not.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_ORE: OverRun Error interrupt\r
+ * @arg USART_IT_NE: Noise Error interrupt\r
+ * @arg USART_IT_FE: Framing Error interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of USART_IT (SET or RESET).\r
+ */\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_GET_IT(USART_IT));\r
+ /* The CTS interrupt is not available for UART4 and UART5 */ \r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & IT_Mask;\r
+ itmask = (uint32_t)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ bitpos = (uint32_t)0x01 << bitpos;\r
+ bitpos &= USARTx->SR;\r
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx\92s interrupt pending bits.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt. \r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) pending bits are cleared by \r
+ * software sequence: a read operation to USART_SR register \r
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC pending bit can be also cleared by software sequence: a read \r
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
+ * operation to USART_DR register (USART_SendData()).\r
+ * - TXE pending bit is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint16_t bitpos = 0x00, itmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_IT(USART_IT));\r
+ /* The CTS interrupt is not available for UART4 and UART5 */\r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
+ USARTx->SR = (uint16_t)~itmask;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the WWDG firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_wwdg.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG \r
+ * @brief WWDG driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ----------- WWDG registers bit address in the alias region ----------- */\r
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
+\r
+/* Alias word address of EWI bit */\r
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
+#define EWI_BitNumber 0x09\r
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
+\r
+/* --------------------- WWDG registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_WDGA_Set ((uint32_t)0x00000080)\r
+\r
+/* CFR register bit mask */\r
+#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)\r
+#define CFR_W_Mask ((uint32_t)0xFFFFFF80)\r
+#define BIT_Mask ((uint8_t)0x7F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG Prescaler.\r
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
+ * @retval None\r
+ */\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
+ /* Clear WDGTB[1:0] bits */\r
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;\r
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
+ tmpreg |= WWDG_Prescaler;\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the downcounter.\r
+ * This parameter value must be lower than 0x80.\r
+ * @retval None\r
+ */\r
+void WWDG_SetWindowValue(uint8_t WindowValue)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
+ /* Clear W[6:0] bits */\r
+\r
+ tmpreg = WWDG->CFR & CFR_W_Mask;\r
+\r
+ /* Set W[6:0] bits according to WindowValue value */\r
+ tmpreg |= WindowValue & (uint32_t) BIT_Mask;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_EnableIT(void)\r
+{\r
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG counter value.\r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F.\r
+ * @retval None\r
+ */\r
+void WWDG_SetCounter(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = Counter & BIT_Mask;\r
+}\r
+\r
+/**\r
+ * @brief Enables WWDG and load the counter value. \r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F.\r
+ * @retval None\r
+ */\r
+void WWDG_Enable(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ WWDG->CR = CR_WDGA_Set | Counter;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r
+ */\r
+FlagStatus WWDG_GetFlagStatus(void)\r
+{\r
+ return (FlagStatus)(WWDG->SR);\r
+}\r
+\r
+/**\r
+ * @brief Clears Early Wakeup interrupt flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_ClearFlag(void)\r
+{\r
+ WWDG->SR = (uint32_t)RESET;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_eth.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 11/20/2009\r
+ * @brief This file contains all the functions prototypes for the Ethernet\r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32_ETH_H\r
+#define __STM32_ETH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32_ETH_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief ETH MAC Init structure definition\r
+ * @note The user should not configure all the ETH_InitTypeDef structure's fields. \r
+ * By calling the ETH_StructInit function the structure\92s fields are set to their default values.\r
+ * Only the parameters that will be set to a non-default value should be configured. \r
+ */ \r
+typedef struct {\r
+/** \r
+ * @brief / * MAC \r
+ */ \r
+ uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
+ and the mode (half/full-duplex).\r
+ This parameter can be a value of @ref ETH_AutoNegotiation */\r
+\r
+ uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be received.\r
+ When disabled, the MAC can receive up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_watchdog */ \r
+\r
+ uint32_t ETH_Jabber; /*!< Selects or not Jabber timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be sent.\r
+ When disabled, the MAC can send up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Jabber */\r
+\r
+ uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission\r
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */ \r
+\r
+ uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense\r
+ This parameter can be a value of @ref ETH_Carrier_Sense */\r
+\r
+ uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps\r
+ This parameter can be a value of @ref ETH_Speed */\r
+\r
+ uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn\r
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
+ in Half-Duplex mode\r
+ This parameter can be a value of @ref ETH_Receive_Own */ \r
+\r
+ uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode\r
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */ \r
+\r
+ uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
+ This parameter can be a value of @ref ETH_Duplex_Mode */ \r
+\r
+ uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
+ This parameter can be a value of @ref ETH_Checksum_Offload */ \r
+\r
+ uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
+ when a colision occurs (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Retry_Transmission */\r
+\r
+ uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping\r
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ \r
+\r
+ uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value\r
+ This parameter can be a value of @ref ETH_Back_Off_Limit */\r
+\r
+ uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Deferral_Check */ \r
+\r
+ uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No fitering)\r
+ This parameter can be a value of @ref ETH_Receive_All */ \r
+\r
+ uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode \r
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */ \r
+\r
+ uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) \r
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */ \r
+\r
+ uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames\r
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
+\r
+ uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames\r
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */ \r
+\r
+ uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
+\r
+ uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter\r
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ \r
+\r
+ uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter\r
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ \r
+\r
+ uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ \r
+\r
+ uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ \r
+\r
+ uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the\r
+ transmit control frame */\r
+\r
+ uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames\r
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ \r
+\r
+ uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
+ automatic retransmission of PAUSE Frame\r
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
+ \r
+ uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
+ unicast address and unique multicast address)\r
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ \r
+\r
+ uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
+ disable its transmitter for a specified time (Pause Time)\r
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
+\r
+ uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
+ or the MAC back-pressure operation (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */ \r
+\r
+ uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
+ comparison and filtering\r
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ \r
+\r
+ uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
+\r
+/** \r
+ * @brief / * DMA \r
+ */ \r
+\r
+ uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames\r
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ \r
+\r
+ uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode\r
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */ \r
+\r
+ uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames\r
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */ \r
+\r
+ uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode\r
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */ \r
+\r
+ uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control\r
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
+\r
+ uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames\r
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
+\r
+ uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
+ and length less than 64 bytes) including pad-bytes and CRC)\r
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
+\r
+ uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO\r
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
+\r
+ uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
+ frame of Transmit data even before obtaining the status for the first frame.\r
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
+\r
+ uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats\r
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
+\r
+ uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers\r
+ This parameter can be a value of @ref ETH_Fixed_Burst */\r
+ \r
+ uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction\r
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ \r
+\r
+ uint32_t ETH_TxDMABurstLength; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction\r
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ \r
+\r
+ uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ \r
+\r
+ uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration\r
+ This parameter can be a value of @ref ETH_DMA_Arbitration */ \r
+}ETH_InitTypeDef;\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief DMA descriptors types\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/** \r
+ * @brief ETH DMA Desciptors data structure definition\r
+ */ \r
+typedef struct {\r
+ uint32_t Status; /*!< Status */\r
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
+} ETH_DMADESCTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Uncomment the line below if you want to use user defined Delay function\r
+ * (for precise timing), otherwise default _eth_delay_ function defined within\r
+ * this driver is used (less precise timing). \r
+ */\r
+/* #define USE_Delay */\r
+\r
+#ifdef USE_Delay\r
+#include "main.h" \r
+ #define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */\r
+#else\r
+ #define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */\r
+#endif \r
+ \r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief ETH Frames defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/** @defgroup ENET_Buffers_setting \r
+ * @{\r
+ */ \r
+#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC 4 /*!< Ethernet CRC */\r
+#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ \r
+#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */\r
+#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */\r
+#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */\r
+#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ \r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet DMA descriptors registers bits definition\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/**\r
+@code \r
+ DMA Tx Desciptor\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+@endcode\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
+ */ \r
+#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */\r
+#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */\r
+#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */\r
+#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */\r
+#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */\r
+#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */\r
+#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */\r
+#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ \r
+#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ \r
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ \r
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ \r
+#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */\r
+#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */\r
+#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */\r
+#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */\r
+#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */\r
+#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */\r
+#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */\r
+#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */\r
+#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */\r
+#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */\r
+#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */\r
+#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */\r
+\r
+/** \r
+ * @brief Bit definition of TDES1 register\r
+ */ \r
+#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */\r
+#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of TDES2 register\r
+ */ \r
+#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of TDES3 register\r
+ */ \r
+#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_Rx_descriptor \r
+ * @{\r
+ */\r
+\r
+/**\r
+@code \r
+ DMA Rx Desciptor\r
+ --------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+@endcode\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register\r
+ */ \r
+#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */\r
+#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */\r
+#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */\r
+#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */\r
+#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */\r
+#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */\r
+#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ \r
+#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ \r
+#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */\r
+#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */\r
+#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */\r
+#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/** \r
+ * @brief Bit definition of RDES1 register\r
+ */ \r
+#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */\r
+#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */\r
+#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */\r
+#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */\r
+#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of RDES2 register \r
+ */ \r
+#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of RDES3 register \r
+ */ \r
+#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Desciption of common PHY registers\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Read_write_Timeouts \r
+ * @{\r
+ */ \r
+#define PHY_READ_TO ((uint32_t)0x0004FFFF)\r
+#define PHY_WRITE_TO ((uint32_t)0x0004FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Reset_Delay \r
+ * @{\r
+ */ \r
+#define PHY_ResetDelay ((uint32_t)0x000FFFFF) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Config_Delay \r
+ * @{\r
+ */ \r
+#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Register_address \r
+ * @{\r
+ */ \r
+#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */\r
+#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_basic_Control_register \r
+ * @{\r
+ */ \r
+#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */\r
+#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */\r
+#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */\r
+#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */\r
+#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */\r
+#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */\r
+#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */\r
+#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */\r
+#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */\r
+#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_basic_status_register \r
+ * @{\r
+ */ \r
+#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */\r
+#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */\r
+#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_status_register \r
+ * @{\r
+ */ \r
+/* The PHY status register value change from a PHY to another so the user have \r
+ to update this value depending on the used external PHY */\r
+/** \r
+ * @brief For LAN8700 \r
+ */ \r
+//#define PHY_SR 31 /*!< Tranceiver Status Register */\r
+/** \r
+ * @brief For DP83848 \r
+ */ \r
+#define PHY_SR 16 /*!< Tranceiver Status Register */\r
+\r
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update\r
+ this value depending on the used external PHY */\r
+/** \r
+ * @brief For LAN8700 \r
+ */ \r
+//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */\r
+//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */\r
+\r
+/** \r
+ * @brief For DP83848 \r
+ */ \r
+#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */\r
+#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \\r
+ ((REG) == PHY_BSR) || \\r
+ ((REG) == PHY_SR))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief MAC defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ETH_AutoNegotiation \r
+ * @{\r
+ */ \r
+#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001)\r
+#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \\r
+ ((CMD) == ETH_AutoNegotiation_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_watchdog \r
+ * @{\r
+ */ \r
+#define ETH_Watchdog_Enable ((uint32_t)0x00000000)\r
+#define ETH_Watchdog_Disable ((uint32_t)0x00800000)\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \\r
+ ((CMD) == ETH_Watchdog_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Jabber \r
+ * @{\r
+ */ \r
+#define ETH_Jabber_Enable ((uint32_t)0x00000000)\r
+#define ETH_Jabber_Disable ((uint32_t)0x00400000)\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \\r
+ ((CMD) == ETH_Jabber_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Inter_Frame_Gap \r
+ * @{\r
+ */ \r
+#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_88Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_80Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_72Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_64Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_56Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_48Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_40Bit))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Carrier_Sense \r
+ * @{\r
+ */ \r
+#define ETH_CarrierSense_Enable ((uint32_t)0x00000000)\r
+#define ETH_CarrierSense_Disable ((uint32_t)0x00010000)\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \\r
+ ((CMD) == ETH_CarrierSense_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Speed \r
+ * @{\r
+ */ \r
+#define ETH_Speed_10M ((uint32_t)0x00000000)\r
+#define ETH_Speed_100M ((uint32_t)0x00004000)\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \\r
+ ((SPEED) == ETH_Speed_100M))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Own \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000)\r
+#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000)\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \\r
+ ((CMD) == ETH_ReceiveOwn_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Loop_Back_Mode \r
+ * @{\r
+ */ \r
+#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000)\r
+#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \\r
+ ((CMD) == ETH_LoopbackMode_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Duplex_Mode \r
+ * @{\r
+ */ \r
+#define ETH_Mode_FullDuplex ((uint32_t)0x00000800)\r
+#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000)\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \\r
+ ((MODE) == ETH_Mode_HalfDuplex))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Offload \r
+ * @{\r
+ */ \r
+#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400)\r
+#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \\r
+ ((CMD) == ETH_ChecksumOffload_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Retry_Transmission \r
+ * @{\r
+ */ \r
+#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000)\r
+#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200)\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \\r
+ ((CMD) == ETH_RetryTransmission_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Automatic_Pad_CRC_Strip \r
+ * @{\r
+ */ \r
+#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080)\r
+#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \\r
+ ((CMD) == ETH_AutomaticPadCRCStrip_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Back_Off_Limit \r
+ * @{\r
+ */ \r
+#define ETH_BackOffLimit_10 ((uint32_t)0x00000000)\r
+#define ETH_BackOffLimit_8 ((uint32_t)0x00000020)\r
+#define ETH_BackOffLimit_4 ((uint32_t)0x00000040)\r
+#define ETH_BackOffLimit_1 ((uint32_t)0x00000060)\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \\r
+ ((LIMIT) == ETH_BackOffLimit_8) || \\r
+ ((LIMIT) == ETH_BackOffLimit_4) || \\r
+ ((LIMIT) == ETH_BackOffLimit_1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Deferral_Check \r
+ * @{\r
+ */\r
+#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010)\r
+#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \\r
+ ((CMD) == ETH_DeferralCheck_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_All \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000)\r
+#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \\r
+ ((CMD) == ETH_ReceiveAll_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Source_Addr_Filter \r
+ * @{\r
+ */ \r
+#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200)\r
+#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300)\r
+#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \\r
+ ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \\r
+ ((CMD) == ETH_SourceAddrFilter_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pass_Control_Frames \r
+ * @{\r
+ */ \r
+#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */\r
+#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ \r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \\r
+ ((PASS) == ETH_PassControlFrames_ForwardAll) || \\r
+ ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Broadcast_Frames_Reception \r
+ * @{\r
+ */ \r
+#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000)\r
+#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020)\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \\r
+ ((CMD) == ETH_BroadcastFramesReception_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Destination_Addr_Filter \r
+ * @{\r
+ */ \r
+#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000)\r
+#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008)\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \\r
+ ((FILTER) == ETH_DestinationAddrFilter_Inverse))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Promiscuous_Mode \r
+ * @{\r
+ */ \r
+#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001)\r
+#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \\r
+ ((CMD) == ETH_PromiscuousMode_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Multicast_Frames_Filter \r
+ * @{\r
+ */ \r
+#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404)\r
+#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004)\r
+#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000)\r
+#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010)\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_None))\r
+ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Frames_Filter \r
+ * @{\r
+ */ \r
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)\r
+#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002)\r
+#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000)\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \\r
+ ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \\r
+ ((FILTER) == ETH_UnicastFramesFilter_Perfect))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Time \r
+ * @{\r
+ */ \r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Zero_Quanta_Pause \r
+ * @{\r
+ */ \r
+#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000)\r
+#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080)\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \\r
+ ((CMD) == ETH_ZeroQuantaPause_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Low_Threshold \r
+ * @{\r
+ */ \r
+#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */\r
+#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */\r
+#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */\r
+#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Pause_Frame_Detect \r
+ * @{\r
+ */ \r
+#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008)\r
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \\r
+ ((CMD) == ETH_UnicastPauseFrameDetect_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Flow_Control \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004)\r
+#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \\r
+ ((CMD) == ETH_ReceiveFlowControl_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Flow_Control \r
+ * @{\r
+ */ \r
+#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002)\r
+#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \\r
+ ((CMD) == ETH_TransmitFlowControl_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_VLAN_Tag_Comparison \r
+ * @{\r
+ */ \r
+#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000)\r
+#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000)\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \\r
+ ((COMPARISON) == ETH_VLANTagComparison_16Bit))\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Flags \r
+ * @{\r
+ */ \r
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses \r
+ * @{\r
+ */ \r
+#define ETH_MAC_Address0 ((uint32_t)0x00000000)\r
+#define ETH_MAC_Address1 ((uint32_t)0x00000008)\r
+#define ETH_MAC_Address2 ((uint32_t)0x00000010)\r
+#define ETH_MAC_Address3 ((uint32_t)0x00000018)\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \\r
+ ((ADDRESS) == ETH_MAC_Address1) || \\r
+ ((ADDRESS) == ETH_MAC_Address2) || \\r
+ ((ADDRESS) == ETH_MAC_Address3))\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \\r
+ ((ADDRESS) == ETH_MAC_Address2) || \\r
+ ((ADDRESS) == ETH_MAC_Address3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames \r
+ * @{\r
+ */ \r
+#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000)\r
+#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008)\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \\r
+ ((FILTER) == ETH_MAC_AddressFilter_DA))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes \r
+ * @{\r
+ */ \r
+#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte5) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte4) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte3) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte2) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte1))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet DMA Desciptors defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_flags\r
+ * @{\r
+ */ \r
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \\r
+ ((FLAG) == ETH_DMATxDesc_IC) || \\r
+ ((FLAG) == ETH_DMATxDesc_LS) || \\r
+ ((FLAG) == ETH_DMATxDesc_FS) || \\r
+ ((FLAG) == ETH_DMATxDesc_DC) || \\r
+ ((FLAG) == ETH_DMATxDesc_DP) || \\r
+ ((FLAG) == ETH_DMATxDesc_TTSE) || \\r
+ ((FLAG) == ETH_DMATxDesc_TER) || \\r
+ ((FLAG) == ETH_DMATxDesc_TCH) || \\r
+ ((FLAG) == ETH_DMATxDesc_TTSS) || \\r
+ ((FLAG) == ETH_DMATxDesc_IHE) || \\r
+ ((FLAG) == ETH_DMATxDesc_ES) || \\r
+ ((FLAG) == ETH_DMATxDesc_JT) || \\r
+ ((FLAG) == ETH_DMATxDesc_FF) || \\r
+ ((FLAG) == ETH_DMATxDesc_PCE) || \\r
+ ((FLAG) == ETH_DMATxDesc_LCA) || \\r
+ ((FLAG) == ETH_DMATxDesc_NC) || \\r
+ ((FLAG) == ETH_DMATxDesc_LCO) || \\r
+ ((FLAG) == ETH_DMATxDesc_EC) || \\r
+ ((FLAG) == ETH_DMATxDesc_VF) || \\r
+ ((FLAG) == ETH_DMATxDesc_CC) || \\r
+ ((FLAG) == ETH_DMATxDesc_ED) || \\r
+ ((FLAG) == ETH_DMATxDesc_UF) || \\r
+ ((FLAG) == ETH_DMATxDesc_DB))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_segment \r
+ * @{\r
+ */ \r
+#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */\r
+#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \\r
+ ((SEGMENT) == ETH_DMATxDesc_FirstSegment))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control\r
+ * @{\r
+ */ \r
+#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */\r
+#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */\r
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))\r
+/** \r
+ * @brief ETH DMA Tx Desciptor buffer size\r
+ */ \r
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_flags\r
+ * @{\r
+ */ \r
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \\r
+ ((FLAG) == ETH_DMARxDesc_AFM) || \\r
+ ((FLAG) == ETH_DMARxDesc_ES) || \\r
+ ((FLAG) == ETH_DMARxDesc_DE) || \\r
+ ((FLAG) == ETH_DMARxDesc_SAF) || \\r
+ ((FLAG) == ETH_DMARxDesc_LE) || \\r
+ ((FLAG) == ETH_DMARxDesc_OE) || \\r
+ ((FLAG) == ETH_DMARxDesc_VLAN) || \\r
+ ((FLAG) == ETH_DMARxDesc_FS) || \\r
+ ((FLAG) == ETH_DMARxDesc_LS) || \\r
+ ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARxDesc_LC) || \\r
+ ((FLAG) == ETH_DMARxDesc_FT) || \\r
+ ((FLAG) == ETH_DMARxDesc_RWT) || \\r
+ ((FLAG) == ETH_DMARxDesc_RE) || \\r
+ ((FLAG) == ETH_DMARxDesc_DBE) || \\r
+ ((FLAG) == ETH_DMARxDesc_CE) || \\r
+ ((FLAG) == ETH_DMARxDesc_MAMPCE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_ \r
+ * @{\r
+ */ \r
+#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */\r
+#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \\r
+ ((BUFFER) == ETH_DMARxDesc_Buffer2))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet DMA defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame \r
+ * @{\r
+ */ \r
+#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000)\r
+#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000)\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \\r
+ ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Store_Forward \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000)\r
+#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \\r
+ ((CMD) == ETH_ReceiveStoreForward_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Flush_Received_Frame \r
+ * @{\r
+ */ \r
+#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000)\r
+#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000)\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \\r
+ ((CMD) == ETH_FlushReceivedFrame_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Store_Forward \r
+ * @{\r
+ */ \r
+#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000)\r
+#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \\r
+ ((CMD) == ETH_TransmitStoreForward_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Threshold_Control \r
+ * @{\r
+ */ \r
+#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Error_Frames \r
+ * @{\r
+ */ \r
+#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080)\r
+#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \\r
+ ((CMD) == ETH_ForwardErrorFrames_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Undersized_Good_Frames \r
+ * @{\r
+ */ \r
+#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040)\r
+#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \\r
+ ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Threshold_Control \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Second_Frame_Operate \r
+ * @{\r
+ */ \r
+#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004)\r
+#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \\r
+ ((CMD) == ETH_SecondFrameOperate_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Address_Aligned_Beats \r
+ * @{\r
+ */ \r
+#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000)\r
+#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \\r
+ ((CMD) == ETH_AddressAlignedBeats_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Fixed_Burst \r
+ * @{\r
+ */ \r
+#define ETH_FixedBurst_Enable ((uint32_t)0x00010000)\r
+#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \\r
+ ((CMD) == ETH_FixedBurst_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Rx_DMA_Burst_Length \r
+ * @{\r
+ */ \r
+#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Tx_DMA_Burst_Length \r
+ * @{\r
+ */ \r
+#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))\r
+/** \r
+ * @brief ETH DMA Desciptor SkipLength \r
+ */ \r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Arbitration \r
+ * @{\r
+ */ \r
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000)\r
+#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002)\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RxPriorTx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Flags \r
+ * @{\r
+ */ \r
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */\r
+#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */\r
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */\r
+\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) \r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */\r
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */\r
+\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_transmit_process_state_ \r
+ * @{\r
+ */ \r
+#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */\r
+#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */\r
+#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */\r
+#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_DMA_receive_process_state_ \r
+ * @{\r
+ */ \r
+#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */\r
+#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */\r
+#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */\r
+#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */\r
+#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_overflow_ \r
+ * @{\r
+ */ \r
+#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \\r
+ ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet PMT defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PMT_Flags \r
+ * @{\r
+ */ \r
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */\r
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet MMC defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Tx_Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Rx_Interrupts \r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Registers \r
+ * @{\r
+ */ \r
+#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */\r
+#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */\r
+#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */\r
+#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */\r
+#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ \r
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */\r
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ \r
+#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */\r
+#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */\r
+#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */\r
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */\r
+\r
+/** \r
+ * @brief ETH MMC registers \r
+ */ \r
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \\r
+ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \\r
+ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \\r
+ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \\r
+ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \\r
+ ((REG) == ETH_MMCRGUFCR)) \r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet PTP defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PTP_time_update_method \r
+ * @{\r
+ */ \r
+#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */\r
+#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */\r
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \\r
+ ((UPDATE) == ETH_PTP_CoarseUpdate))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_PTP_Flags \r
+ * @{\r
+ */ \r
+#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */\r
+#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */\r
+#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */\r
+#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */\r
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSITE) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSSTU) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSSTI))\r
+/** \r
+ * @brief ETH PTP subsecond increment \r
+ */ \r
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_PTP_time_sign \r
+ * @{\r
+ */ \r
+#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */\r
+#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */\r
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \\r
+ ((SIGN) == ETH_PTP_NegativeTime))\r
+\r
+/** \r
+ * @brief ETH PTP time stamp low update \r
+ */ \r
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)\r
+\r
+/** \r
+ * @brief ETH PTP registers \r
+ */ \r
+#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */\r
+#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */\r
+#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */\r
+#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */\r
+#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */\r
+#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */\r
+#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */\r
+#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */\r
+#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */\r
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \\r
+ ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \\r
+ ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \\r
+ ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \\r
+ ((REG) == ETH_PTPTTLR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions\r
+ * @{\r
+ */ \r
+void ETH_DeInit(void);\r
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);\r
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);\r
+void ETH_SoftwareReset(void);\r
+FlagStatus ETH_GetSoftwareResetStatus(void);\r
+void ETH_Start(void);\r
+uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength);\r
+uint32_t ETH_HandleRxPkt(u8 *ppkt);\r
+uint32_t ETH_GetRxPktSize(void);\r
+void ETH_DropRxPkt(void);\r
+\r
+/** \r
+ * @brief PHY \r
+ */ \r
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);\r
+uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);\r
+uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);\r
+\r
+/** \r
+ * @brief MAC \r
+ */ \r
+void ETH_MACTransmissionCmd(FunctionalState NewState);\r
+void ETH_MACReceptionCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetFlowControlBusyStatus(void);\r
+void ETH_InitiatePauseControlFrame(void); \r
+void ETH_BackPressureActivationCmd(FunctionalState NewState); \r
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); \r
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);\r
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);\r
+void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr);\r
+void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr);\r
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);\r
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);\r
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);\r
+\r
+/** \r
+ * @brief DMA Tx/Rx descriptors \r
+ */ \r
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount);\r
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount);\r
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);\r
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);\r
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);\r
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);\r
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);\r
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);\r
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount);\r
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount);\r
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);\r
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);\r
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);\r
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);\r
+\r
+/** \r
+ * @brief DMA\r
+ */ \r
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);\r
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);\r
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);\r
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);\r
+uint32_t ETH_GetTransmitProcessState(void);\r
+uint32_t ETH_GetReceiveProcessState(void);\r
+void ETH_FlushTransmitFIFO(void);\r
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);\r
+void ETH_DMATransmissionCmd(FunctionalState NewState);\r
+void ETH_DMAReceptionCmd(FunctionalState NewState);\r
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);\r
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);\r
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);\r
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);\r
+uint32_t ETH_GetCurrentTxDescStartAddress(void);\r
+uint32_t ETH_GetCurrentRxDescStartAddress(void);\r
+uint32_t ETH_GetCurrentTxBufferAddress(void);\r
+uint32_t ETH_GetCurrentRxBufferAddress(void);\r
+void ETH_ResumeDMATransmission(void);\r
+void ETH_ResumeDMAReception(void);\r
+\r
+/** \r
+ * @brief PMT \r
+ */ \r
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);\r
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);\r
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);\r
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);\r
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);\r
+void ETH_PowerDownCmd(FunctionalState NewState);\r
+\r
+/** \r
+ * @brief MMC \r
+ */ \r
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);\r
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);\r
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);\r
+void ETH_MMCCountersReset(void);\r
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);\r
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);\r
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);\r
+\r
+/** \r
+ * @brief PTP \r
+ */ \r
+uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab);\r
+uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab);\r
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount);\r
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount);\r
+void ETH_EnablePTPTimeStampAddend(void);\r
+void ETH_EnablePTPTimeStampInterruptTrigger(void);\r
+void ETH_EnablePTPTimeStampUpdate(void);\r
+void ETH_InitializePTPTimeStamp(void);\r
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);\r
+void ETH_PTPTimeStampCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);\r
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);\r
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);\r
+void ETH_SetPTPTimeStampAddend(uint32_t Value);\r
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);\r
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32_ETH_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_eth.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 11/20/2009\r
+ * @brief This file provides all the ETH firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32_eth.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32_ETH_Driver\r
+ * @brief ETH driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_Private_Defines\r
+ * @{\r
+ */ \r
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */\r
+ETH_DMADESCTypeDef *DMATxDescToSet;\r
+ETH_DMADESCTypeDef *DMARxDescToGet;\r
+ETH_DMADESCTypeDef *DMAPTPTxDescToSet;\r
+ETH_DMADESCTypeDef *DMAPTPRxDescToGet;\r
+\r
+/* ETHERNET MAC address offsets */\r
+#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */\r
+#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */\r
+\r
+/* ETHERNET MACMIIAR register Mask */\r
+#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) \r
+\r
+/* ETHERNET MACCR register Mask */\r
+#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) \r
+\r
+/* ETHERNET MACFCR register Mask */\r
+#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)\r
+\r
+/* ETHERNET DMAOMR register Mask */\r
+#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)\r
+\r
+/* ETHERNET Remote Wake-up frame register length */\r
+#define ETH_WAKEUP_REGISTER_LENGTH 8\r
+\r
+/* ETHERNET Missed frames counter Shift */\r
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17\r
+\r
+/* ETHERNET DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3\r
+\r
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16\r
+\r
+/* ETHERNET DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16\r
+\r
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16\r
+\r
+/* ETHERNET errors */\r
+#define ETH_ERROR ((uint32_t)0)\r
+#define ETH_SUCCESS ((uint32_t)1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_Variables\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_FunctionPrototypes\r
+ * @{\r
+ */ \r
+ \r
+#ifndef USE_Delay\r
+static void ETH_Delay(__IO uint32_t nCount);\r
+#endif /* USE_Delay*/\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the ETHERNET peripheral registers to their default reset values.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void ETH_DeInit(void)\r
+{\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETHERNET peripheral according to the specified\r
+ * parameters in the ETH_InitStruct .\r
+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains\r
+ * the configuration information for the specified ETHERNET peripheral.\r
+ * @param PHYAddress: external PHY address \r
+ * @retval ETH_ERROR: Ethernet initialization failed\r
+ * ETH_SUCCESS: Ethernet successfully initialized \r
+ */\r
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)\r
+{\r
+ uint32_t RegValue = 0, tmpreg = 0;\r
+ __IO uint32_t i = 0;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ uint32_t hclk = 60000000;\r
+ __IO uint32_t timeout = 0;\r
+ /* Check the parameters */\r
+ /* MAC --------------------------*/ \r
+ assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));\r
+ assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));\r
+ assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));\r
+ assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));\r
+ assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));\r
+ assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); \r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));\r
+ /* DMA --------------------------*/\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); \r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); \r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); \r
+ /*-------------------------------- MAC Config ------------------------------*/ \r
+ /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tmpreg &= MACMIIAR_CR_MASK;\r
+ /* Get hclk frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ hclk = rcc_clocks.HCLK_Frequency;\r
+ /* Set CR bits depending on hclk value */\r
+ if((hclk >= 20000000)&&(hclk < 35000000))\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if((hclk >= 35000000)&&(hclk < 60000000))\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */ \r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; \r
+ } \r
+ else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */\r
+ {\r
+ /* CSR Clock Range between 60-72 MHz */ \r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; \r
+ }\r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ ETH->MACMIIAR = (uint32_t)tmpreg; \r
+ /*-------------------- PHY initialization and configuration ----------------*/\r
+ /* Put the PHY in reset mode */\r
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Delay to assure PHY reset */\r
+ _eth_delay_(PHY_ResetDelay);\r
+ \r
+ \r
+ if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)\r
+ { \r
+ /* We wait for linked satus... */\r
+ do\r
+ {\r
+ timeout++;\r
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ /* Reset Timeout counter */\r
+ timeout = 0;\r
+ \r
+ /* Enable Auto-Negotiation */\r
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Wait until the autonegotiation will be completed */\r
+ do\r
+ {\r
+ timeout++;\r
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); \r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ /* Reset Timeout counter */\r
+ timeout = 0;\r
+ \r
+ /* Read the result of the autonegotiation */\r
+ RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);\r
+ \r
+ /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */\r
+ if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)\r
+ {\r
+ /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */\r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */\r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; \r
+ }\r
+ /* Configure the MAC with the speed fixed by the autonegotiation process */\r
+ if(RegValue & PHY_Speed_Status)\r
+ { \r
+ /* Set Ethernet speed to 10M following the autonegotiation */ \r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M; \r
+ }\r
+ else\r
+ { \r
+ /* Set Ethernet speed to 100M following the autonegotiation */ \r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_100M; \r
+ } \r
+ }\r
+ else\r
+ {\r
+ if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |\r
+ (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+ /* Delay to assure PHY configuration */\r
+ _eth_delay_(PHY_ConfigDelay);\r
+ \r
+ }\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */ \r
+ tmpreg = ETH->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH_Watchdog value */\r
+ /* Set the JD: bit according to ETH_Jabber value */\r
+ /* Set the IFG bit according to ETH_InterFrameGap value */ \r
+ /* Set the DCRS bit according to ETH_CarrierSense value */ \r
+ /* Set the FES bit according to ETH_Speed value */ \r
+ /* Set the DO bit according to ETH_ReceiveOwn value */ \r
+ /* Set the LM bit according to ETH_LoopbackMode value */ \r
+ /* Set the DM bit according to ETH_Mode value */ \r
+ /* Set the IPC bit according to ETH_ChecksumOffload value */ \r
+ /* Set the DR bit according to ETH_RetryTransmission value */ \r
+ /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ \r
+ /* Set the BL bit according to ETH_BackOffLimit value */ \r
+ /* Set the DC bit according to ETH_DeferralCheck value */ \r
+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | \r
+ ETH_InitStruct->ETH_Jabber | \r
+ ETH_InitStruct->ETH_InterFrameGap |\r
+ ETH_InitStruct->ETH_CarrierSense |\r
+ ETH_InitStruct->ETH_Speed | \r
+ ETH_InitStruct->ETH_ReceiveOwn |\r
+ ETH_InitStruct->ETH_LoopbackMode |\r
+ ETH_InitStruct->ETH_Mode | \r
+ ETH_InitStruct->ETH_ChecksumOffload | \r
+ ETH_InitStruct->ETH_RetryTransmission | \r
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip | \r
+ ETH_InitStruct->ETH_BackOffLimit | \r
+ ETH_InitStruct->ETH_DeferralCheck);\r
+ /* Write to ETHERNET MACCR */\r
+ ETH->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r
+ /* Set the RA bit according to ETH_ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH_PassControlFrames value */\r
+ /* Set the DBF bit according to ETH_BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH_DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH_PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */ \r
+ ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | \r
+ ETH_InitStruct->ETH_SourceAddrFilter |\r
+ ETH_InitStruct->ETH_PassControlFrames |\r
+ ETH_InitStruct->ETH_BroadcastFramesReception | \r
+ ETH_InitStruct->ETH_DestinationAddrFilter |\r
+ ETH_InitStruct->ETH_PromiscuousMode |\r
+ ETH_InitStruct->ETH_MulticastFramesFilter |\r
+ ETH_InitStruct->ETH_UnicastFramesFilter); \r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;\r
+ /* Write to ETHERNET MACHTLR */\r
+ ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACFCR value */ \r
+ tmpreg = ETH->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= MACFCR_CLEAR_MASK;\r
+ \r
+ /* Set the PT bit according to ETH_PauseTime value */\r
+ /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH_PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH_ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH_TransmitFlowControl value */ \r
+ tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | \r
+ ETH_InitStruct->ETH_ZeroQuantaPause |\r
+ ETH_InitStruct->ETH_PauseLowThreshold |\r
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect | \r
+ ETH_InitStruct->ETH_ReceiveFlowControl |\r
+ ETH_InitStruct->ETH_TransmitFlowControl); \r
+ /* Write to ETHERNET MACFCR */\r
+ ETH->MACFCR = (uint32_t)tmpreg;\r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ /* Set the ETV bit according to ETH_VLANTagComparison value */\r
+ /* Set the VL bit according to ETH_VLANTagIdentifier value */ \r
+ ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | \r
+ ETH_InitStruct->ETH_VLANTagIdentifier); \r
+ \r
+ /*-------------------------------- DMA Config ------------------------------*/\r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */ \r
+ tmpreg = ETH->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= DMAOMR_CLEAR_MASK;\r
+ \r
+ /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH_ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH_FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH_TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH_TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH_ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH_ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH_SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | \r
+ ETH_InitStruct->ETH_ReceiveStoreForward |\r
+ ETH_InitStruct->ETH_FlushReceivedFrame |\r
+ ETH_InitStruct->ETH_TransmitStoreForward | \r
+ ETH_InitStruct->ETH_TransmitThresholdControl |\r
+ ETH_InitStruct->ETH_ForwardErrorFrames |\r
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |\r
+ ETH_InitStruct->ETH_ReceiveThresholdControl | \r
+ ETH_InitStruct->ETH_SecondFrameOperate); \r
+ /* Write to ETHERNET DMAOMR */\r
+ ETH->DMAOMR = (uint32_t)tmpreg;\r
+ \r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/ \r
+ /* Set the AAL bit according to ETH_AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH_FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */\r
+ /* Set the DSL bit according to ETH_DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH_DMAArbitration value */ \r
+ ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | \r
+ ETH_InitStruct->ETH_FixedBurst |\r
+ ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ ETH_InitStruct->ETH_TxDMABurstLength | \r
+ (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |\r
+ ETH_InitStruct->ETH_DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ \r
+ /* Return Ethernet configuration success */\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ETH_InitStruct member with its default value.\r
+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)\r
+{\r
+ /* ETH_InitStruct members default value */\r
+ /*------------------------ MAC -----------------------------------*/ \r
+ ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; \r
+ ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; \r
+ ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; \r
+ ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; \r
+ ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; \r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M; \r
+ ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; \r
+ ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; \r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; \r
+ ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; \r
+ ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; \r
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; \r
+ ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; \r
+ ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; \r
+ ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; \r
+ ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; \r
+ ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; \r
+ ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;\r
+ ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; \r
+ ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; \r
+ ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; \r
+ ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; \r
+ ETH_InitStruct->ETH_HashTableHigh = 0x0; \r
+ ETH_InitStruct->ETH_HashTableLow = 0x0; \r
+ ETH_InitStruct->ETH_PauseTime = 0x0; \r
+ ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; \r
+ ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; \r
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; \r
+ ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; \r
+ ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; \r
+ ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; \r
+ ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; \r
+ /*------------------------ DMA -----------------------------------*/ \r
+ ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; \r
+ ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; \r
+ ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; \r
+ ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; \r
+ ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; \r
+ ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; \r
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; \r
+ ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; \r
+ ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;\r
+ ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;\r
+ ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;\r
+ ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;\r
+ ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;\r
+ ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;\r
+ ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;\r
+}\r
+\r
+/**\r
+ * @brief Enables ENET MAC and DMA reception/transmission \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_Start(void)\r
+{\r
+ /* Enable transmit state machine of the MAC for transmission on the MII */ \r
+ ETH_MACTransmissionCmd(ENABLE);\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO();\r
+ /* Enable receive state machine of the MAC for reception from the MII */ \r
+ ETH_MACReceptionCmd(ENABLE);\r
+ \r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionCmd(ENABLE); \r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionCmd(ENABLE); \r
+}\r
+\r
+/**\r
+ * @brief Transmits a packet, from application buffer, pointed by ppkt.\r
+ * @param ppkt: pointer to the application's packet buffer to transmit.\r
+ * @param FrameLength: Tx Packet size.\r
+ * @retval ETH_ERROR: in case of Tx desc owned by DMA\r
+ * ETH_SUCCESS: for correct transmission\r
+ */\r
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)\r
+{ \r
+ uint32_t offset = 0;\r
+ \r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return ERROR: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ \r
+ for(offset=0; offset<FrameLength; offset++) \r
+ {\r
+ (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));\r
+ }\r
+ \r
+ /* Setting the Frame Length: bits[12:0] */\r
+ DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);\r
+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ \r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ ETH->DMATPDR = 0;\r
+ }\r
+ \r
+ /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ \r
+ /* Chained Mode */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)\r
+ { \r
+ /* Selects the next DMA Tx descriptor list for next buffer to send */ \r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); \r
+ }\r
+ else /* Ring Mode */\r
+ { \r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); \r
+ }\r
+ else\r
+ { \r
+ /* Selects the next DMA Tx descriptor list for next buffer to send */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS; \r
+}\r
+\r
+/**\r
+ * @brief Receives a packet and copies it to memory pointed by ppkt.\r
+ * @param ppkt: pointer to the application packet receive buffer.\r
+ * @retval ETH_ERROR: if there is error in reception\r
+ * framelength: received packet size if packet reception is correct\r
+ */\r
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)\r
+{ \r
+ uint32_t offset = 0, framelength = 0;\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return error: OWN bit set */\r
+ return ETH_ERROR; \r
+ }\r
+ \r
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && \r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && \r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) \r
+ { \r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;\r
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */\r
+ for(offset=0; offset<framelength; offset++) \r
+ {\r
+ (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return ERROR */\r
+ framelength = ETH_ERROR;\r
+ }\r
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN; \r
+ \r
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */\r
+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) \r
+ {\r
+ /* Clear RBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_RBUS;\r
+ /* Resume DMA reception */\r
+ ETH->DMARPDR = 0;\r
+ }\r
+ \r
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ \r
+ /* Chained Mode */\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)\r
+ { \r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */ \r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); \r
+ }\r
+ else /* Ring Mode */\r
+ { \r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); \r
+ }\r
+ else\r
+ { \r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ \r
+ /* Return Frame Length/ERROR */\r
+ return (framelength); \r
+}\r
+\r
+/**\r
+ * @brief Get the size of received the received packet.\r
+ * @param None\r
+ * @retval framelength: received packet size \r
+ */\r
+uint32_t ETH_GetRxPktSize(void)\r
+{\r
+ uint32_t frameLength = 0;\r
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))\r
+ {\r
+ /* Get the size of the packet: including 4 bytes of the CRC */\r
+ frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);\r
+ }\r
+ \r
+ /* Return Frame Length */ \r
+ return frameLength;\r
+}\r
+\r
+/**\r
+ * @brief Drop a Received packet (too small packet, etc...)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_DropRxPkt(void)\r
+{\r
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN; \r
+ /* Chained Mode */\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);\r
+ }\r
+ else /* Ring Mode */\r
+ {\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read: this will\r
+ be the first Rx descriptor in this case */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ }\r
+ }\r
+}\r
+\r
+/*--------------------------------- PHY ------------------------------------*/\r
+/**\r
+ * @brief Read a PHY register\r
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. \r
+ * This parameter can be one of the following values: 0,..,31 \r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * @arg PHY_BCR: Tranceiver Basic Control Register \r
+ * @arg PHY_BSR: Tranceiver Basic Status Register \r
+ * @arg PHY_SR : Tranceiver Status Register \r
+ * @arg More PHY register could be read depending on the used PHY\r
+ * @retval ETH_ERROR: in case of timeout\r
+ * MAC MIIDR register value: Data read from the selected PHY register (correct read )\r
+ */\r
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)\r
+{\r
+ uint32_t tmpreg = 0; \r
+__IO uint32_t timeout = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ assert_param(IS_ETH_PHY_REG(PHYReg));\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH->MACMIIAR;\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~MACMIIAR_CR_MASK;\r
+ /* Prepare the MII address register value */\r
+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ /* Write the result value into the MII Address register */\r
+ ETH->MACMIIAR = tmpreg;\r
+ /* Check for the Busy flag */\r
+ do\r
+ {\r
+ timeout++;\r
+ tmpreg = ETH->MACMIIAR;\r
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return (uint16_t)ETH_ERROR;\r
+ }\r
+ \r
+ /* Return data register value */\r
+ return (uint16_t)(ETH->MACMIIDR);\r
+}\r
+\r
+/**\r
+ * @brief Write to a PHY register\r
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. \r
+ * This parameter can be one of the following values: 0,..,31\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * @arg PHY_BCR : Tranceiver Control Register \r
+ * @arg More PHY register could be written depending on the used PHY\r
+ * @param PHYValue: the value to write\r
+ * @retval ETH_ERROR: in case of timeout\r
+ * ETH_SUCCESS: for correct write\r
+ */\r
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)\r
+{\r
+ uint32_t tmpreg = 0; \r
+ __IO uint32_t timeout = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ assert_param(IS_ETH_PHY_REG(PHYReg));\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH->MACMIIAR;\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~MACMIIAR_CR_MASK;\r
+ /* Prepare the MII register address value */\r
+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ /* Give the value to the MII data register */\r
+ ETH->MACMIIDR = PHYValue;\r
+ /* Write the result value into the MII Address register */\r
+ ETH->MACMIIAR = tmpreg;\r
+ /* Check for the Busy flag */\r
+ do\r
+ {\r
+ timeout++;\r
+ tmpreg = ETH->MACMIIAR;\r
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_WRITE_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PHY loopBack mode.\r
+ * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal\r
+ * loopback at MII level\r
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. \r
+ * This parameter can be one of the following values: \r
+ * @param NewState: new state of the PHY loopBack mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval ETH_ERROR: in case of bad PHY configuration\r
+ * ETH_SUCCESS: for correct PHY configuration\r
+ */\r
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Get the PHY configuration to update it */\r
+ tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PHY loopback mode */\r
+ tmpreg |= PHY_Loopback; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the PHY loopback mode: normal mode */\r
+ tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);\r
+ }\r
+ /* Update the PHY control register with the new configuration */\r
+ if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)\r
+ {\r
+ return ETH_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* Return SUCCESS */\r
+ return ETH_ERROR; \r
+ } \r
+}\r
+\r
+/*--------------------------------- MAC ------------------------------------*/\r
+/**\r
+ * @brief Enables or disables the MAC transmission.\r
+ * @param NewState: new state of the MAC transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACTransmissionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC transmission */\r
+ ETH->MACCR |= ETH_MACCR_TE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC transmission */\r
+ ETH->MACCR &= ~ETH_MACCR_TE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC reception.\r
+ * @param NewState: new state of the MAC reception.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACReceptionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC reception */\r
+ ETH->MACCR |= ETH_MACCR_RE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC reception */\r
+ ETH->MACCR &= ~ETH_MACCR_RE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.\r
+ * @param None\r
+ * @retval The new state of flow control busy status bit (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetFlowControlBusyStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* The Flow Control register should not be written to until this bit is cleared */\r
+ if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Initiate a Pause Control Frame (Full-duplex only).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_InitiatePauseControlFrame(void) \r
+{ \r
+ /* When Set In full duplex MAC initiates pause control frame */\r
+ ETH->MACFCR |= ETH_MACFCR_FCBBPA; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only).\r
+ * @param NewState: new state of the MAC BackPressure operation activation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_BackPressureActivationCmd(FunctionalState NewState) \r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Activate the MAC BackPressure operation */\r
+ /* In Half duplex: during backpressure, when the MAC receives a new frame,\r
+ the transmitter starts sending a JAM pattern resulting in a collision */\r
+ ETH->MACFCR |= ETH_MACFCR_FCBBPA; \r
+ }\r
+ else\r
+ {\r
+ /* Desactivate the MAC BackPressure operation */\r
+ ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.\r
+ * @param ETH_MAC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag \r
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag \r
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag \r
+ * @arg ETH_MAC_FLAG_MMC : MMC flag \r
+ * @arg ETH_MAC_FLAG_PMT : PMT flag \r
+ * @retval The new state of ETHERNET MAC flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); \r
+ if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not.\r
+ * @param ETH_MAC_IT: specifies the interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt \r
+ * @arg ETH_MAC_IT_MMCR : MMC receive interrupt \r
+ * @arg ETH_MAC_IT_MMC : MMC interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt \r
+ * @retval The new state of ETHERNET MAC interrupt (SET or RESET).\r
+ */\r
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); \r
+ if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ETHERNET MAC interrupts.\r
+ * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt \r
+ * @param NewState: new state of the specified ETHERNET MAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MAC interrupts */\r
+ ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MAC interrupts */\r
+ ETH->MACIMR |= ETH_MAC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param MacAddr: The MAC addres to configure.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0 : MAC Address0 \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param Addr: Pointer on MAC address buffer data (6 bytes).\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+ \r
+ /* Calculate the selectecd MAC address high register */\r
+ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];\r
+ /* Load the selectecd MAC address high register */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;\r
+ /* Calculate the selectecd MAC address low register */\r
+ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];\r
+ \r
+ /* Load the selectecd MAC address low register */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Get the selected MAC address.\r
+ * @param MacAddr: The MAC addres to return.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0 : MAC Address0 \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param Addr: Pointer on MAC address buffer data (6 bytes).\r
+ * @retval None\r
+ */\r
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+ \r
+ /* Get the selectecd MAC address high register */\r
+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));\r
+ \r
+ /* Calculate the selectecd MAC address buffer */\r
+ Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);\r
+ Addr[4] = (tmpreg & (uint8_t)0xFF);\r
+ /* Load the selectecd MAC address low register */\r
+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));\r
+ /* Calculate the selectecd MAC address buffer */\r
+ Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);\r
+ Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);\r
+ Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);\r
+ Addr[0] = (tmpreg & (uint8_t)0xFF);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Address filter module uses the specified\r
+ * ETHERNET MAC address for perfect filtering \r
+ * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param NewState: new state of the specified ETHERNET MAC address use.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MAC address for perfect filtering */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MAC address for perfect filtering */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the filter type for the specified ETHERNET MAC address \r
+ * @param MacAddr: specifies the ETHERNET MAC address \r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param Filter: specifies the used frame received field for comparaison \r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the\r
+ * SA fields of the received frame.\r
+ * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the\r
+ * DA fields of the received frame.\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));\r
+ \r
+ if (Filter != ETH_MAC_AddressFilter_DA)\r
+ {\r
+ /* The selected ETHERNET MAC address is used to compare with the SA fields of the\r
+ received frame. */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;\r
+ }\r
+ else\r
+ {\r
+ /* The selected ETHERNET MAC address is used to compare with the DA fields of the\r
+ received frame. */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the filter type for the specified ETHERNET MAC address \r
+ * @param MacAddr: specifies the ETHERNET MAC address \r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param MaskByte: specifies the used address bytes for comparaison \r
+ * This parameter can be any combination of the following values: \r
+ * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].\r
+ * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].\r
+ * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].\r
+ * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].\r
+ * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].\r
+ * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));\r
+ \r
+ /* Clear MBC bits in the selected MAC address high register */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);\r
+ /* Set the selected Filetr mask bytes */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;\r
+}\r
+/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param DMATxDescTab: Pointer on the first Tx desc list \r
+ * @param TxBuff: Pointer on the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab + i;\r
+ /* Set Second Address Chained bit */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TCH; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; \r
+ }\r
+ }\r
+ \r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in ring mode.\r
+ * @param DMATxDescTab: Pointer on the first Tx desc list \r
+ * @param TxBuff1: Pointer on the first TxBuffer1 list \r
+ * @param TxBuff2: Pointer on the first TxBuffer2 list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct\r
+ * for the number of Words to skip between two unchained descriptors. \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab + i;\r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Set Buffer2 address pointer */\r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base\r
+ address of the list, creating a Desciptor Ring */\r
+ if(i == (TxBuffCount-1))\r
+ {\r
+ /* Set Transmit End of Ring bit */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TER;\r
+ }\r
+ }\r
+ \r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param ETH_DMATxDescFlag: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine\r
+ * @arg ETH_DMATxDesc_IC : Interrupt on completetion\r
+ * @arg ETH_DMATxDesc_LS : Last Segment\r
+ * @arg ETH_DMATxDesc_FS : First Segment\r
+ * @arg ETH_DMATxDesc_DC : Disable CRC\r
+ * @arg ETH_DMATxDesc_DP : Disable Pad\r
+ * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable\r
+ * @arg ETH_DMATxDesc_TER : Transmit End of Ring\r
+ * @arg ETH_DMATxDesc_TCH : Second Address Chained\r
+ * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status\r
+ * @arg ETH_DMATxDesc_IHE : IP Header Error\r
+ * @arg ETH_DMATxDesc_ES : Error summary\r
+ * @arg ETH_DMATxDesc_JT : Jabber Timeout\r
+ * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush\r
+ * @arg ETH_DMATxDesc_PCE : Payload Checksum Error\r
+ * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission\r
+ * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver\r
+ * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision\r
+ * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions\r
+ * @arg ETH_DMATxDesc_VF : VLAN Frame\r
+ * @arg ETH_DMATxDesc_CC : Collision Count \r
+ * @arg ETH_DMATxDesc_ED : Excessive Deferral\r
+ * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory\r
+ * @arg ETH_DMATxDesc_DB : Deferred Bit\r
+ * @retval The new state of ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));\r
+ \r
+ if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor \r
+ * @retval The Transmit descriptor collision counter value.\r
+ */\r
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)\r
+{\r
+ /* Return the Receive descriptor frame length */\r
+ return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);\r
+}\r
+\r
+/**\r
+ * @brief Set the specified DMA Tx Desc Own bit.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @retval None\r
+ */\r
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)\r
+{\r
+ /* Set the DMA Tx Desc Own bit */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_OWN;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @param NewState: new state of the DMA Tx Desc transmit interrupt.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA Tx Desc Transmit interrupt */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_IC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA Tx Desc Transmit interrupt */\r
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment \r
+ * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));\r
+ \r
+ /* Selects the DMA Tx Desc Frame segment */\r
+ DMATxDesc->Status |= DMATxDesc_FrameSegment;\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor \r
+ * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass\r
+ * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum\r
+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));\r
+ \r
+ /* Set the selected DMA Tx desc checksum insertion control */\r
+ DMATxDesc->Status |= DMATxDesc_Checksum;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc CRC.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc CRC.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc CRC */\r
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc CRC */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_DC; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc end of ring.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc end of ring.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc end of ring */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TER; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc end of ring */\r
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc second address chained.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc second address chained.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc second address chained */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TCH; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc second address chained */\r
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */\r
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/\r
+ DMATxDesc->Status |= ETH_DMATxDesc_DP; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc time stamp.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc time stamp.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc time stamp */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TTSE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc time stamp */\r
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @param BufferSize1: specifies the Tx desc buffer1 size.\r
+ * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));\r
+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));\r
+ \r
+ /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */\r
+ DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param DMARxDescTab: Pointer on the first Rx desc list \r
+ * @param RxBuff: Pointer on the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+ \r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab; \r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); \r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); \r
+ }\r
+ }\r
+ \r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in ring mode.\r
+ * @param DMARxDescTab: Pointer on the first Rx desc list \r
+ * @param RxBuff1: Pointer on the first RxBuffer1 list \r
+ * @param RxBuff2: Pointer on the first RxBuffer2 list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct\r
+ * for the number of Words to skip between two unchained descriptors. \r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab; \r
+ /* Fill each DMARxDesc descriptor with the right values */ \r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i; \r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN; \r
+ /* Set Buffer1 size */\r
+ DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); \r
+ \r
+ /* Set Buffer2 address pointer */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); \r
+ \r
+ /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base\r
+ address of the list, creating a Desciptor Ring */\r
+ if(i == (RxBuffCount-1))\r
+ {\r
+ /* Set Receive End of Ring bit */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;\r
+ }\r
+ }\r
+ \r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor\r
+ * @param ETH_DMARxDescFlag: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine \r
+ * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame\r
+ * @arg ETH_DMARxDesc_ES: Error summary\r
+ * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame\r
+ * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame\r
+ * @arg ETH_DMARxDesc_LE: Frame size not matching with length field\r
+ * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow\r
+ * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame\r
+ * @arg ETH_DMARxDesc_FS: First descriptor of the frame\r
+ * @arg ETH_DMARxDesc_LS: Last descriptor of the frame\r
+ * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error \r
+ * @arg ETH_DMARxDesc_LC: Late collision occurred during reception\r
+ * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3\r
+ * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception\r
+ * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface\r
+ * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits\r
+ * @arg ETH_DMARxDesc_CE: CRC error\r
+ * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error\r
+ * @retval The new state of ETH_DMARxDescFlag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));\r
+ if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified DMA Rx Desc Own bit.\r
+ * @param DMARxDesc: Pointer on a Rx desc\r
+ * @retval None\r
+ */\r
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)\r
+{\r
+ /* Set the DMA Rx Desc Own bit */\r
+ DMARxDesc->Status |= ETH_DMARxDesc_OWN;\r
+}\r
+\r
+/**\r
+ * @brief Returns the specified DMA Rx Desc frame length.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor \r
+ * @retval The Rx descriptor received frame length.\r
+ */\r
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)\r
+{\r
+ /* Return the Receive descriptor frame length */\r
+ return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMA Rx Desc receive interrupt.\r
+ * @param DMARxDesc: Pointer on a Rx desc\r
+ * @param NewState: new state of the specified DMA Rx Desc interrupt.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA Rx Desc receive interrupt */\r
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA Rx Desc receive interrupt */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Rx Desc end of ring.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor\r
+ * @param NewState: new state of the specified DMA Rx Desc end of ring.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Rx Desc end of ring */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Rx Desc end of ring */\r
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Rx Desc second address chained.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor\r
+ * @param NewState: new state of the specified DMA Rx Desc second address chained.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Rx Desc second address chained */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Rx Desc second address chained */\r
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the specified ETHERNET DMA Rx Desc buffer size.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor \r
+ * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.\r
+ * This parameter can be any one of the following values:\r
+ * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1\r
+ * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 \r
+ * @retval The Receive descriptor frame length.\r
+ */\r
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));\r
+ \r
+ if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)\r
+ {\r
+ /* Return the DMA Rx Desc buffer2 size */\r
+ return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); \r
+ }\r
+ else\r
+ {\r
+ /* Return the DMA Rx Desc buffer1 size */\r
+ return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); \r
+ }\r
+}\r
+\r
+/*--------------------------------- DMA ------------------------------------*/\r
+/**\r
+ * @brief Resets all MAC subsystem internal registers and logic.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_SoftwareReset(void)\r
+{\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ ETH->DMABMR |= ETH_DMABMR_SR;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET software reset bit is set or not.\r
+ * @param None\r
+ * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetSoftwareResetStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.\r
+ * @param ETH_DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag\r
+ * @arg ETH_DMA_FLAG_PMT : PMT flag \r
+ * @arg ETH_DMA_FLAG_MMC : MMC flag \r
+ * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access\r
+ * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr\r
+ * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA\r
+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag\r
+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag \r
+ * @arg ETH_DMA_FLAG_ER : Early receive flag \r
+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag \r
+ * @arg ETH_DMA_FLAG_ET : Early transmit flag \r
+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag \r
+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag \r
+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_R : Receive flag \r
+ * @arg ETH_DMA_FLAG_TU : Underflow flag \r
+ * @arg ETH_DMA_FLAG_RO : Overflow flag \r
+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag \r
+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag \r
+ * @arg ETH_DMA_FLAG_T : Transmit flag \r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)\r
+{ \r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));\r
+ if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET\92s DMA pending flag.\r
+ * @param ETH_DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag\r
+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag \r
+ * @arg ETH_DMA_FLAG_ER : Early receive flag \r
+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag \r
+ * @arg ETH_DMA_FLAG_ETI : Early transmit flag \r
+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag \r
+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag \r
+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_R : Receive flag \r
+ * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag \r
+ * @arg ETH_DMA_FLAG_RO : Receive Overflow flag \r
+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag \r
+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag \r
+ * @arg ETH_DMA_FLAG_T : Transmit flag\r
+ * @retval None\r
+ */\r
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));\r
+ \r
+ /* Clear the selected ETHERNET DMA FLAG */\r
+ ETH->DMASR = (uint32_t) ETH_DMA_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not.\r
+ * @param ETH_DMA_IT: specifies the interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt\r
+ * @arg ETH_DMA_IT_PMT : PMT interrupt \r
+ * @arg ETH_DMA_IT_MMC : MMC interrupt\r
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary \r
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary \r
+ * @arg ETH_DMA_IT_ER : Early receive interrupt \r
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt \r
+ * @arg ETH_DMA_IT_ET : Early transmit interrupt \r
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt \r
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt \r
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_R : Receive interrupt \r
+ * @arg ETH_DMA_IT_TU : Underflow interrupt \r
+ * @arg ETH_DMA_IT_RO : Overflow interrupt \r
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt \r
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt \r
+ * @arg ETH_DMA_IT_T : Transmit interrupt \r
+ * @retval The new state of ETH_DMA_IT (SET or RESET).\r
+ */\r
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)\r
+{ \r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));\r
+ if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET\92s DMA IT pending bit.\r
+ * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary \r
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary \r
+ * @arg ETH_DMA_IT_ER : Early receive interrupt \r
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt \r
+ * @arg ETH_DMA_IT_ETI : Early transmit interrupt \r
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt \r
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt \r
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_R : Receive interrupt \r
+ * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt \r
+ * @arg ETH_DMA_IT_RO : Receive Overflow interrupt \r
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt \r
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt \r
+ * @arg ETH_DMA_IT_T : Transmit interrupt\r
+ * @retval None\r
+ */\r
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));\r
+ \r
+ /* Clear the selected ETHERNET DMA IT */\r
+ ETH->DMASR = (uint32_t) ETH_DMA_IT;\r
+}\r
+\r
+/**\r
+ * @brief Returns the ETHERNET DMA Transmit Process State.\r
+ * @param None\r
+ * @retval The new ETHERNET DMA Transmit Process State:\r
+ * This can be one of the following values:\r
+ * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued\r
+ * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor \r
+ * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status\r
+ * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory\r
+ * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe\r
+ * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor \r
+ */\r
+uint32_t ETH_GetTransmitProcessState(void)\r
+{\r
+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); \r
+}\r
+\r
+/**\r
+ * @brief Returns the ETHERNET DMA Receive Process State.\r
+ * @param None\r
+ * @retval The new ETHERNET DMA Receive Process State:\r
+ * This can be one of the following values:\r
+ * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued\r
+ * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor \r
+ * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet\r
+ * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable\r
+ * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor\r
+ * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory \r
+ */\r
+uint32_t ETH_GetReceiveProcessState(void)\r
+{\r
+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); \r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void ETH_FlushTransmitFIFO(void)\r
+{\r
+ /* Set the Flush Transmit FIFO bit */\r
+ ETH->DMAOMR |= ETH_DMAOMR_FTF; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not.\r
+ * @param None \r
+ * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)\r
+{ \r
+ FlagStatus bitstatus = RESET;\r
+ if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA transmission.\r
+ * @param NewState: new state of the DMA transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATransmissionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transmission */\r
+ ETH->DMAOMR |= ETH_DMAOMR_ST; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transmission */\r
+ ETH->DMAOMR &= ~ETH_DMAOMR_ST;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA reception.\r
+ * @param NewState: new state of the DMA reception.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMAReceptionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA reception */\r
+ ETH->DMAOMR |= ETH_DMAOMR_SR; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA reception */\r
+ ETH->DMAOMR &= ~ETH_DMAOMR_SR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ETHERNET DMA interrupts.\r
+ * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary \r
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary \r
+ * @arg ETH_DMA_IT_ER : Early receive interrupt \r
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt \r
+ * @arg ETH_DMA_IT_ET : Early transmit interrupt \r
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt \r
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt \r
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_R : Receive interrupt \r
+ * @arg ETH_DMA_IT_TU : Underflow interrupt \r
+ * @arg ETH_DMA_IT_RO : Overflow interrupt \r
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt \r
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt \r
+ * @arg ETH_DMA_IT_T : Transmit interrupt\r
+ * @param NewState: new state of the specified ETHERNET DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET DMA interrupts */\r
+ ETH->DMAIER |= ETH_DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET DMA interrupts */\r
+ ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.\r
+ * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter\r
+ * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter\r
+ * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));\r
+ \r
+ if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.\r
+ * @param None\r
+ * @retval The value of Rx overflow Missed Frame Counter.\r
+ */\r
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)\r
+{\r
+ return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.\r
+ * @param None\r
+ * @retval The value of Buffer unavailable Missed Frame Counter.\r
+ */\r
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)\r
+{\r
+ return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHTDR register value.\r
+ * @param None\r
+ * @retval The value of the current Tx desc start address.\r
+ */\r
+uint32_t ETH_GetCurrentTxDescStartAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHTDR));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHRDR register value.\r
+ * @param None\r
+ * @retval The value of the current Rx desc start address.\r
+ */\r
+uint32_t ETH_GetCurrentRxDescStartAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHRDR));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHTBAR register value.\r
+ * @param None\r
+ * @retval The value of the current Tx buffer address.\r
+ */\r
+uint32_t ETH_GetCurrentTxBufferAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHTBAR));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHRBAR register value.\r
+ * @param None\r
+ * @retval The value of the current Rx buffer address.\r
+ */\r
+uint32_t ETH_GetCurrentRxBufferAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHRBAR));\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register\r
+ * (the data written could be anything). This forces the DMA to resume transmission.\r
+ * @param None\r
+ * @retval None.\r
+ */\r
+void ETH_ResumeDMATransmission(void)\r
+{\r
+ ETH->DMATPDR = 0;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register\r
+ * (the data written could be anything). This forces the DMA to resume reception.\r
+ * @param None\r
+ * @retval None.\r
+ */\r
+void ETH_ResumeDMAReception(void)\r
+{\r
+ ETH->DMARPDR = 0;\r
+}\r
+\r
+/*--------------------------------- PMT ------------------------------------*/\r
+/**\r
+ * @brief Reset Wakeup frame filter register pointer.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)\r
+{ \r
+ /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; \r
+}\r
+\r
+/**\r
+ * @brief Populates the remote wakeup frame registers.\r
+ * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).\r
+ * @retval None\r
+ */\r
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)\r
+{\r
+ uint32_t i = 0;\r
+ \r
+ /* Fill Remote Wake-up Frame Filter register with Buffer data */\r
+ for(i =0; i<ETH_WAKEUP_REGISTER_LENGTH; i++)\r
+ {\r
+ /* Write each time to the same register */ \r
+ ETH->MACRWUFFR = Buffer[i];\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param NewState: new state of the MAC Global Unicast Wake-Up.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Global Unicast Wake-Up */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Global Unicast Wake-Up */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.\r
+ * @param ETH_PMT_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset \r
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received \r
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received\r
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));\r
+ \r
+ if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC Wake-Up Frame Detection.\r
+ * @param NewState: new state of the MAC Wake-Up Frame Detection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Wake-Up Frame Detection */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Wake-Up Frame Detection */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC Magic Packet Detection.\r
+ * @param NewState: new state of the MAC Magic Packet Detection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Magic Packet Detection */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Magic Packet Detection */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC Power Down.\r
+ * @param NewState: new state of the MAC Power Down.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_PowerDownCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Power Down */\r
+ /* This puts the MAC in power down mode */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Power Down */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;\r
+ }\r
+}\r
+\r
+/*--------------------------------- MMC ------------------------------------*/\r
+/**\r
+ * @brief Enables or disables the MMC Counter Freeze.\r
+ * @param NewState: new state of the MMC Counter Freeze.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MMC Counter Freeze */\r
+ ETH->MMCCR |= ETH_MMCCR_MCF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MMC Counter Freeze */\r
+ ETH->MMCCR &= ~ETH_MMCCR_MCF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MMC Reset On Read.\r
+ * @param NewState: new state of the MMC Reset On Read.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MMC Counter reset on read */\r
+ ETH->MMCCR |= ETH_MMCCR_ROR; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MMC Counter reset on read */\r
+ ETH->MMCCR &= ~ETH_MMCCR_ROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MMC Counter Stop Rollover.\r
+ * @param NewState: new state of the MMC Counter Stop Rollover.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Disable the MMC Counter Stop Rollover */\r
+ ETH->MMCCR &= ~ETH_MMCCR_CSR;\r
+ }\r
+ else\r
+ {\r
+ /* Enable the MMC Counter Stop Rollover */\r
+ ETH->MMCCR |= ETH_MMCCR_CSR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Resets the MMC Counters.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_MMCCountersReset(void)\r
+{\r
+ /* Resets the MMC Counters */\r
+ ETH->MMCCR |= ETH_MMCCR_CR; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ETHERNET MMC interrupts.\r
+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of Tx interrupt or \r
+ * any combination of Rx interrupt (but not both)of the following values: \r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @param NewState: new state of the specified ETHERNET MMC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)\r
+ {\r
+ /* Remove egister mak from IT */\r
+ ETH_MMC_IT &= 0xEFFFFFFF;\r
+ \r
+ /* ETHERNET MMC Rx interrupts selected */\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCRIMR |= ETH_MMC_IT; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* ETHERNET MMC Tx interrupts selected */\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCTIMR |= ETH_MMC_IT; \r
+ } \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MMC IT is set or not.\r
+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value \r
+ * @retval The value of ETHERNET MMC IT (SET or RESET).\r
+ */\r
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); \r
+ \r
+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)\r
+ {\r
+ /* ETHERNET MMC Rx interrupts selected */\r
+ /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ \r
+ if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* ETHERNET MMC Tx interrupts selected */\r
+ /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ \r
+ if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ } \r
+ } \r
+ \r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Get the specified ETHERNET MMC register value.\r
+ * @param ETH_MMCReg: specifies the ETHERNET MMC register.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMCCR : MMC CR register \r
+ * @arg ETH_MMCRIR : MMC RIR register \r
+ * @arg ETH_MMCTIR : MMC TIR register \r
+ * @arg ETH_MMCRIMR : MMC RIMR register \r
+ * @arg ETH_MMCTIMR : MMC TIMR register \r
+ * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register \r
+ * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register \r
+ * @arg ETH_MMCTGFCR : MMC TGFCR register\r
+ * @arg ETH_MMCRFCECR : MMC RFCECR register \r
+ * @arg ETH_MMCRFAECR : MMC RFAECR register \r
+ * @arg ETH_MMCRGUFCR : MMC RGUFCRregister \r
+ * @retval The value of ETHERNET MMC Register value.\r
+ */\r
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));\r
+ \r
+ /* Return the selected register value */\r
+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));\r
+}\r
+/*--------------------------------- PTP ------------------------------------*/\r
+\r
+/**\r
+ * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_EnablePTPTimeStampAddend(void)\r
+{\r
+ /* Enable the PTP block update with the Time Stamp Addend register value */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; \r
+}\r
+\r
+/**\r
+ * @brief Enable the PTP Time Stamp interrupt trigger\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_EnablePTPTimeStampInterruptTrigger(void)\r
+{\r
+ /* Enable the PTP target time interrupt */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; \r
+}\r
+\r
+/**\r
+ * @brief Updated the PTP system time with the Time Stamp Update register value.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_EnablePTPTimeStampUpdate(void)\r
+{\r
+ /* Enable the PTP system time update with the Time Stamp Update register value */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; \r
+}\r
+\r
+/**\r
+ * @brief Initialize the PTP Time Stamp\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_InitializePTPTimeStamp(void)\r
+{\r
+ /* Initialize the PTP Time Stamp */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; \r
+}\r
+\r
+/**\r
+ * @brief Selects the PTP Update method\r
+ * @param UpdateMethod: the PTP Update method\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTP_FineUpdate : Fine Update method \r
+ * @arg ETH_PTP_CoarseUpdate : Coarse Update method \r
+ * @retval None\r
+ */\r
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));\r
+ \r
+ if (UpdateMethod != ETH_PTP_CoarseUpdate)\r
+ {\r
+ /* Enable the PTP Fine Update method */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PTP Coarse Update method */\r
+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PTP time stamp for transmit and receive frames.\r
+ * @param NewState: new state of the PTP time stamp for transmit and receive frames\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_PTPTimeStampCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PTP time stamp for transmit and receive frames */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PTP time stamp for transmit and receive frames */\r
+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET PTP flag is set or not.\r
+ * @param ETH_PTP_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTP_FLAG_TSARU : Addend Register Update \r
+ * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable \r
+ * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update \r
+ * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize \r
+ * @retval The new state of ETHERNET PTP Flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));\r
+ \r
+ if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Sets the system time Sub-Second Increment value.\r
+ * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));\r
+ /* Set the PTP Sub-Second Increment Register */\r
+ ETH->PTPSSIR = SubSecondValue; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Time Stamp update sign and values.\r
+ * @param Sign: specifies the PTP Time update value sign.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTP_PositiveTime : positive time value. \r
+ * @arg ETH_PTP_NegativeTime : negative time value. \r
+ * @param SecondValue: specifies the PTP Time update second value. \r
+ * @param SubSecondValue: specifies the PTP Time update sub-second value.\r
+ * This parameter is a 31 bit value, bit32 correspond to the sign.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); \r
+ assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); \r
+ /* Set the PTP Time Update High Register */\r
+ ETH->PTPTSHUR = SecondValue;\r
+ \r
+ /* Set the PTP Time Update Low Register with sign */\r
+ ETH->PTPTSLUR = Sign | SubSecondValue; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Time Stamp Addend value.\r
+ * @param Value: specifies the PTP Time Stamp Addend Register value.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPTimeStampAddend(uint32_t Value)\r
+{\r
+ /* Set the PTP Time Stamp Addend Register */\r
+ ETH->PTPTSAR = Value; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Target Time registers values.\r
+ * @param HighValue: specifies the PTP Target Time High Register value.\r
+ * @param LowValue: specifies the PTP Target Time Low Register value.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)\r
+{\r
+ /* Set the PTP Target Time High Register */\r
+ ETH->PTPTTHR = HighValue;\r
+ /* Set the PTP Target Time Low Register */\r
+ ETH->PTPTTLR = LowValue; \r
+}\r
+\r
+/**\r
+ * @brief Get the specified ETHERNET PTP register value.\r
+ * @param ETH_PTPReg: specifies the ETHERNET PTP register.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTPTSCR : Sub-Second Increment Register \r
+ * @arg ETH_PTPSSIR : Sub-Second Increment Register \r
+ * @arg ETH_PTPTSHR : Time Stamp High Register\r
+ * @arg ETH_PTPTSLR : Time Stamp Low Register \r
+ * @arg ETH_PTPTSHUR : Time Stamp High Update Register \r
+ * @arg ETH_PTPTSLUR : Time Stamp Low Update Register\r
+ * @arg ETH_PTPTSAR : Time Stamp Addend Register\r
+ * @arg ETH_PTPTTHR : Target Time High Register \r
+ * @arg ETH_PTPTTLR : Target Time Low Register \r
+ * @retval The value of ETHERNET PTP Register value.\r
+ */\r
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));\r
+ \r
+ /* Return the selected register value */\r
+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode with PTP.\r
+ * @param DMATxDescTab: Pointer on the first Tx desc list \r
+ * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list\r
+ * @param TxBuff: Pointer on the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,\r
+ uint8_t* TxBuff, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+ DMAPTPTxDescToSet = DMAPTPTxDescTab;\r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab+i;\r
+ /* Set Second Address Chained bit and enable PTP */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; \r
+ }\r
+ /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */\r
+ (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;\r
+ (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;\r
+ }\r
+ /* Store on the last DMAPTPTxDescTab desc status record the first list address */\r
+ (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;\r
+\r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param DMARxDescTab: Pointer on the first Rx desc list \r
+ * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list\r
+ * @param RxBuff: Pointer on the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,\r
+ uint8_t *RxBuff, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+ \r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab; \r
+ DMAPTPRxDescToGet = DMAPTPRxDescTab;\r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); \r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); \r
+ }\r
+ /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */\r
+ (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;\r
+ (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;\r
+ }\r
+ /* Store on the last DMAPTPRxDescTab desc status record the first list address */\r
+ (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;\r
+\r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab; \r
+}\r
+\r
+/**\r
+ * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values.\r
+ * @param ppkt: pointer to application packet buffer to transmit.\r
+ * @param FrameLength: Tx Packet size.\r
+ * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.\r
+ * @retval ETH_ERROR: in case of Tx desc owned by DMA\r
+ * ETH_SUCCESS: for correct transmission\r
+ */\r
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)\r
+{\r
+ uint32_t offset = 0, timeout = 0;\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return ERROR: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ \r
+ for(offset=0; offset<FrameLength; offset++)\r
+ {\r
+ (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));\r
+ }\r
+ /* Setting the Frame Length: bits[12:0] */\r
+ DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);\r
+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ \r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ ETH->DMATPDR = 0;\r
+ }\r
+ /* Wait for ETH_DMATxDesc_TTSS flag to be set */\r
+ do\r
+ {\r
+ timeout++;\r
+ } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ /* Clear the DMATxDescToSet status register TTSS flag */\r
+ DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;\r
+ *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;\r
+ *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;\r
+ /* Update the ENET DMA current descriptor */\r
+ /* Chained Mode */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)\r
+ { \r
+ /* Selects the next DMA Tx descriptor list for next buffer read */ \r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);\r
+ if(DMAPTPTxDescToSet->Status != 0)\r
+ { \r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);\r
+ }\r
+ else\r
+ {\r
+ DMAPTPTxDescToSet++;\r
+ }\r
+ }\r
+ else /* Ring Mode */\r
+ { \r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Tx descriptor list for next buffer read: this will\r
+ be the first Tx descriptor in this case */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); \r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Tx descriptor list for next buffer read */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/**\r
+ * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values.\r
+ * @param ppkt: pointer to application packet receive buffer. \r
+ * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.\r
+ * @retval ETH_ERROR: if there is error in reception\r
+ * framelength: received packet size if packet reception is correct\r
+ */\r
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)\r
+{\r
+ uint32_t offset = 0, framelength = 0;\r
+ /* Check if the descriptor is owned by the ENET or CPU */\r
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return error: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))\r
+ {\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;\r
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ \r
+ for(offset=0; offset<framelength; offset++)\r
+ {\r
+ (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return ERROR */\r
+ framelength = ETH_ERROR;\r
+ }\r
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */\r
+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear RBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_RBUS;\r
+ /* Resume DMA reception */\r
+ ETH->DMARPDR = 0;\r
+ }\r
+ *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;\r
+ *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;\r
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;\r
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */\r
+ /* Chained Mode */\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);\r
+ if(DMAPTPRxDescToGet->Status != 0)\r
+ {\r
+ DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);\r
+ }\r
+ else\r
+ {\r
+ DMAPTPRxDescToGet++;\r
+ }\r
+ }\r
+ else /* Ring Mode */\r
+ {\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ /* Return Frame Length/ERROR */\r
+ return (framelength);\r
+}\r
+\r
+#ifndef USE_Delay\r
+/**\r
+ * @brief Inserts a delay time.\r
+ * @param nCount: specifies the delay time length.\r
+ * @retval None\r
+ */\r
+static void ETH_Delay(__IO uint32_t nCount)\r
+{\r
+ __IO uint32_t index = 0; \r
+ for(index = nCount; index != 0; index--)\r
+ {\r
+ }\r
+}\r
+#endif /* USE_Delay*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
#include "stack.h"\r
\r
.extern os_sys\r
+.extern TailChaining\r
\r
.syntax unified\r
.cpu cortex-m3\r
\r
.global Irq_Handler\r
.type Irq_Handler, %function\r
+ .global SVC_Handler\r
+ .type SVC_Handler, %function\r
+ .global PendSV_Handler\r
+ .type PendSV_Handler, %function\r
\r
#define IRQ_ENABLE() cpsie i\r
#define IRQ_DISABLE() cpsid i\r
// lr\r
#define REG_SAVE r4-r8,r10,r11\r
\r
+SVC_Handler: \r
+ add sp,sp,#(8*4) /* remove one interrupt frame from the stack */\r
+ bx lr /* return to the preempted task */\r
\r
-Irq_Handler:\r
+PendSV_Handler:\r
+ IRQ_DISABLE()\r
+ push {REG_SAVE,lr}\r
+ sub.w sp,sp,#C_SIZE\r
+ mov.w r4,#LC_PATTERN\r
+ str r4,[sp,#C_CONTEXT_OFFS] \r
+ mov r2,sp // stack as first arg\r
+\r
+ mov r1,#0x01000000 // make up a task xPSR that has only the T bit set \r
+ ldr r0,=TailChaining // load the address of scheduler wrapper (new PC) \r
+ push {r0-r1} // push xPSR,PC \r
+ sub sp,sp,#(5*4) // don't care for lr,r12,r3,r2,r1\r
+ push {r2} // stack as first arg\r
+ bx lr // interrupt return to the scheduler wrapper\r
+ \r
+Irq_Handler: \r
push {REG_SAVE,lr}\r
sub.w sp,sp,#C_SIZE\r
mov.w r4,#LC_PATTERN\r
str r4,[sp,#C_CONTEXT_OFFS] \r
mov r0,sp // stack as first arg\r
- \r
-// When at interrupt nest count = 0, load interrupt stack \r
+\r
+ // When at interrupt nest count = 0, load interrupt stack \r
ldr r4,=os_sys\r
ldr r5,[r4,#SYS_INT_NEST_CNT]\r
cmp r5, #0\r
- bgt arggg\r
- \r
- ldr sp,[r4,#SYS_INT_STACK] \r
- \r
+ bgt arggg \r
+ ldr sp,[r4,#SYS_INT_STACK] \r
arggg: \r
bl Irq_Entry\r
mov sp, r0 // pop from returned stack\r
/* Do a normal exception return */\r
add.w sp,sp,#C_SIZE\r
pop {REG_SAVE,lr}\r
- bx lr\r
-\r
-// b os_lc_restore\r
- \r
+ bx lr \r
\r
/**\r
* Fake an interrupt stack to be able to return to thread mode.\r
*/\r
os_sc_restore:\r
add.w sp,sp,#C_SIZE\r
-\r
pop {REG_SAVE,lr}\r
bx lr\r
\r
add.w sp,sp,#C_SIZE\r
/* Pop function stack (LR will be 0xffff_fff9 here, just ignore */\r
pop {REG_SAVE,lr}\r
- \r
- /* If we were in handler mode a "bx lr" would pop back all the registers\r
- * that were automatically pushed by the CPU. Now we have to do this \r
- * manually instead. \r
- * The problem here is PSR since its not a register that we can pop\r
- * back so we have to do it manually, use r0 as scratch */\r
- \r
- /* Grab stack xPSR and move to psr */\r
- /* TODO: Does this enable interrupts?? */\r
- ldr r0,[sp,#28]\r
- msr apsr,r0\r
- \r
- /* Update bit[0] of PC.\r
- *\r
- * From "3.3.1 STM32F10xxx Cortex-M3 programming manual"\r
- * Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must\r
- * be 1 for correct execution, because this bit indicates the required instruction set, and the\r
- * Cortex-M3 processor only supports thumb instructions. */\r
- ldr r0,[sp,#24]\r
- orr r0,r0,#1\r
- str r0,[sp,#24]\r
- \r
- /* Pop part of the exception stack */\r
- pop {r0-r3,r12,lr}\r
- \r
- add.w sp,sp,#(2*4) /* Adjust for xPSR and PC */\r
- /* We do return directly to the preempted task here, so enable interrupts */\r
- cpsie i /* Enable interrupts */\r
+ IRQ_ENABLE() /* Enable interrupts to allow svc */\r
+ svc 0 /* cause exception to return to the preempted task */\r
\r
- /* Jump to PC from PC on stack (the branch value on the stack must be + 1 to\r
- * stay in thumb mode) */\r
- ldr pc,[sp,#-8]\r
\r
\r
\r
*/\r
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
+ uint32_t prio = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);\r
+\r
if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = prio; } /* set Priority for Cortex-M3 System Interrupts */\r
else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ NVIC->IP[(uint32_t)(IRQn)] = prio; } /* set Priority for device specific Interrupts */\r
}\r
\r
/**\r
if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
\r
SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ //NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
return (0); /* Function successful */\r
extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
-/*
-* PRIGROUP[2:0] Group prios Sub prios
-* 0b011 16 None
-* 0b100 8 2
-* 0b101 4 4
-* 0b110 2 8
-* 0b111 None 16
-*/
-#define AIRCR_VECTKEY ((uint32_t)0x05FA0000)
-
-/** Set NVIC prio group */
-static void NVIC_SetPrioGroup(uint32_t prioGroup)
+/**
+ * Init NVIC vector. We do not use subpriority
+ *
+ * @param vector The IRQ number
+ * @param prio NVIC priority, 0-31, 0-high prio
+ */
+static void NVIC_InitVector(IRQn_Type vector, uint32_t prio)
{
- SCB->AIRCR = AIRCR_VECTKEY | (prioGroup<<8);
+ // Set prio
+ NVIC_SetPriority(vector,prio);
+
+ // Enable
+ NVIC->ISER[vector >> 5] = (uint32_t)1 << (vector & (uint8_t)0x1F);
}
+/*
+PRIGROUP
+0 7.1 indicates seven bits of pre-emption priority, one bit of subpriority
+1 6.2 indicates six bits of pre-emption priority, two bits of subpriority
+2 5.3 indicates five bits of pre-emption priority, three bits of subpriority
+3 4.4 indicates four bits of pre-emption priority, four bits of subpriority
+4 3.5 indicates three bits of pre-emption priority, five bits of subpriority
+5 2.6 indicates two bits of pre-emption priority, six bits of subpriority
+6 1.7 indicates one bit of pre-emption priority, seven bits of subpriority
+7 0.8 indicates no pre-emption priority, eight bits of subpriority.
+*/
void Irq_Init( void ) {
- NVIC_SetPrioGroup(3); // No sub prioritys
+ NVIC_SetPriorityGrouping(0);
+ NVIC_SetPriority(SVCall_IRQn, 0xff); // Set lowest prio
+ NVIC_SetPriority(PendSV_IRQn, 0xff); // Set lowest prio
+
+ /* Stop counters and watchdogs when halting in debug */
+ DBGMCU->CR |= 0x00ffffff00;
}
void Irq_EOI( void ) {
return (SCB->ICSR & ICSR_VECTACTIVE);
}
-/**
- * Init NVIC vector. We do not use subriority
- *
- */
-
-/**
- * Init NVIC vector. We do not use subpriority
- *
- * @param vector The IRQ number
- * @param prio NVIC priority, 0-15, 0-high prio
- */
-static void NVIC_InitVector(IRQn_Type vector, uint32_t prio)
-{
- // Set prio
- NVIC_SetPriority(vector,prio);
- //NVIC->IP[vector] = prio;
-
- // Enable
- //NVIC_EnableIRQ(vector);
- NVIC->ISER[vector >> 5] = (uint32_t)1 << (vector & (uint8_t)0x1F);
-}
/**
*
* The stack holds C, NVGPR, VGPR and the EXC frame.
*
*/
-void *Irq_Entry( void *stack_p )
-{
+void *Irq_Entry( void *stack_p ){
uint32_t vector = 0;
- uint32_t *stack;
Irq_Disable();
- stack = (uint32_t *)stack_p;
/* 0. Set the default handler here....
* 1. Grab the vector from the interrupt controller
vector = NVIC_GetActiveVector();
- stack = Os_Isr(stack, (void *)Irq_VectorTable[vector]);
+ Os_Isr_cm3((void *)Irq_VectorTable[vector]);
Irq_Enable();
- return stack;
+
+ return stack_p;
}
/**
}
/**
- * NVIC prio have priority 0-15, 0-highest priority.
+ * NVIC prio have priority 0-31, 0-highest priority.
* Autosar does it the other way around, 0-Lowest priority
+ * NOTE: prio 255 is reserved for SVC and PendSV
*
* Autosar NVIC
* 31 0
- * 30 0
+ * 30 1
* ..
- * 0 15
- * 0 15
+ * 0 31
* @param prio
* @return
*/
static inline int osPrioToCpuPio( uint8_t prio ) {
assert(prio<32);
prio = 31 - prio;
- return (prio>>1);
+ return prio;
}
/**
.size g_pfnVectors, .-g_pfnVectors\r
\r
.extern Irq_Handler\r
+ .extern SVC_Handler\r
+ .extern PendSV_Handler\r
\r
.word _estack\r
.word Reset_Handler\r
-\r
/**\r
******************************************************************************\r
* @file stm32f10x.h\r
* @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
* This file contains all the peripheral register's definitions, bits \r
- * definitions and memory mapping for STM32F10x Connectivity line, High\r
- * density, Medium density and Low density devices.\r
+ * definitions and memory mapping for STM32F10x Connectivity line, \r
+ * High density, High density value line, Medium density, \r
+ * Medium density Value line, Low density, Low density Value line \r
+ * and XL-density devices.\r
****************************************************************************** \r
*\r
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
*\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
******************************************************************************\r
*/\r
\r
application \r
*/\r
\r
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)\r
- /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */\r
- #define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */\r
- /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */\r
- /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) \r
+ /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */\r
+ /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ \r
+ /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */\r
+ /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ \r
+ /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */\r
+ /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ \r
+ /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */\r
+ /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */\r
#endif\r
/* Tip: To avoid modifying this file each time you need to switch between these\r
devices, you can define the device in your toolchain compiler preprocessor.\r
\r
- - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
where the Flash memory density ranges between 16 and 32 Kbytes.\r
- - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash\r
+ memory density ranges between 16 and 32 Kbytes.\r
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
where the Flash memory density ranges between 64 and 128 Kbytes.\r
- - High density devices are STM32F101xx and STM32F103xx microcontrollers where\r
+ - Medium-density value line devices are STM32F100xx microcontrollers where the \r
+ Flash memory density ranges between 64 and 128 Kbytes. \r
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where\r
the Flash memory density ranges between 256 and 512 Kbytes.\r
+ - High-density value line devices are STM32F100xx microcontrollers where the \r
+ Flash memory density ranges between 256 and 512 Kbytes. \r
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where\r
+ the Flash memory density ranges between 512 and 1024 Kbytes.\r
- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\r
*/\r
\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)\r
+ #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"\r
+#endif\r
+\r
#if !defined USE_STDPERIPH_DRIVER\r
/**\r
* @brief Comment the line below if you will not use the peripherals drivers.\r
Tip: To avoid modifying this file each time you need to use different HSE, you\r
can define the HSE value in your toolchain compiler preprocessor.\r
*/ \r
-#if !defined HSE_Value\r
+#if !defined HSE_VALUE\r
#ifdef STM32F10X_CL \r
- #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
#else \r
- #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
#endif /* STM32F10X_CL */\r
-#endif /* HSE_Value */\r
+#endif /* HSE_VALUE */\r
\r
\r
/**\r
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
Timeout value \r
*/\r
-#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
\r
-#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\r
+#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\r
\r
/**\r
* @brief STM32F10x Standard Peripheral Library version number\r
*/\r
#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */\r
-#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */\r
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */\r
#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */\r
#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\\r
| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\\r
/**\r
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals \r
*/\r
-#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */\r
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
+#ifdef STM32F10X_XL\r
+ #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */\r
+#else\r
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */\r
+#endif /* STM32F10X_XL */\r
+/* NOTE We use 7 bits preemption since 8 bits premtion isn't configurable */\r
+#define __NVIC_PRIO_BITS 7 /*!< STM32 uses 7 Bits for the Priority Levels */\r
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
\r
/**\r
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
\r
#ifdef STM32F10X_LD\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
#endif /* STM32F10X_LD */ \r
\r
+#ifdef STM32F10X_LD_VL\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */ \r
+#endif /* STM32F10X_LD_VL */\r
+\r
#ifdef STM32F10X_MD\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
#endif /* STM32F10X_MD */ \r
\r
+#ifdef STM32F10X_MD_VL\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */ \r
+#endif /* STM32F10X_MD_VL */\r
+\r
#ifdef STM32F10X_HD\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
#endif /* STM32F10X_HD */ \r
\r
+#ifdef STM32F10X_HD_VL\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
+ TIM12_IRQn = 43, /*!< TIM12 global Interrupt */\r
+ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */\r
+ TIM14_IRQn = 45, /*!< TIM14 global Interrupt */\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */ \r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 Interrupt */ \r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
+ DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is \r
+ mapped at postion 60 only if the MISC_REMAP bit in \r
+ the AFIO_MAPR2 register is set) */ \r
+#endif /* STM32F10X_HD_VL */\r
+\r
+#ifdef STM32F10X_XL\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
+#endif /* STM32F10X_XL */ \r
+\r
#ifdef STM32F10X_CL\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
typedef __I uint16_t vuc16; /*!< Read Only */\r
typedef __I uint8_t vuc8; /*!< Read Only */\r
\r
-#if !defined(FALSE)\r
-#ifndef __cplusplus\r
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
-#endif\r
-#endif\r
-\r
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
\r
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
\r
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
\r
+/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */\r
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT\r
+#define HSE_Value HSE_VALUE\r
+#define HSI_Value HSI_VALUE\r
/**\r
* @}\r
*/\r
__IO uint16_t DR42;\r
uint16_t RESERVED45; \r
} BKP_TypeDef;\r
-\r
+ \r
/** \r
* @brief Controller Area Network TxMailBox \r
*/\r
#endif /* STM32F10X_CL */ \r
} CAN_TypeDef;\r
\r
+/** \r
+ * @brief Consumer Electronics Control (CEC)\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CFGR;\r
+ __IO uint32_t OAR;\r
+ __IO uint32_t PRES;\r
+ __IO uint32_t ESR;\r
+ __IO uint32_t CSR;\r
+ __IO uint32_t TXD;\r
+ __IO uint32_t RXD; \r
+} CEC_TypeDef;\r
+\r
/** \r
* @brief CRC calculation unit \r
*/\r
__IO uint32_t DHR8RD;\r
__IO uint32_t DOR1;\r
__IO uint32_t DOR2;\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ __IO uint32_t SR;\r
+#endif\r
} DAC_TypeDef;\r
\r
/** \r
__IO uint32_t RESERVED;\r
__IO uint32_t OBR;\r
__IO uint32_t WRPR;\r
+#ifdef STM32F10X_XL\r
+ uint32_t RESERVED1[8]; \r
+ __IO uint32_t KEYR2;\r
+ uint32_t RESERVED2; \r
+ __IO uint32_t SR2;\r
+ __IO uint32_t CR2;\r
+ __IO uint32_t AR2; \r
+#endif /* STM32F10X_XL */ \r
} FLASH_TypeDef;\r
\r
/** \r
__IO uint32_t EVCR;\r
__IO uint32_t MAPR;\r
__IO uint32_t EXTICR[4];\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t MAPR2; \r
} AFIO_TypeDef;\r
/** \r
* @brief Inter-integrated Circuit Interface\r
__IO uint32_t APB1ENR;\r
__IO uint32_t BDCR;\r
__IO uint32_t CSR;\r
+\r
#ifdef STM32F10X_CL \r
__IO uint32_t AHBRSTR;\r
__IO uint32_t CFGR2;\r
#endif /* STM32F10X_CL */ \r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) \r
+ uint32_t RESERVED0;\r
+ __IO uint32_t CFGR2;\r
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ \r
} RCC_TypeDef;\r
\r
/** \r
* @{\r
*/\r
\r
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */\r
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */\r
\r
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */\r
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\r
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+\r
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
\r
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
\r
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)\r
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)\r
\r
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)\r
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)\r
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)\r
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)\r
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)\r
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)\r
\r
#define SDIO_BASE (PERIPH_BASE + 0x18000)\r
\r
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
#define RTC ((RTC_TypeDef *) RTC_BASE)\r
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
#define BKP ((BKP_TypeDef *) BKP_BASE)\r
#define PWR ((PWR_TypeDef *) PWR_BASE)\r
#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)\r
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
#define USART1 ((USART_TypeDef *) USART1_BASE)\r
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\r
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\r
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/\r
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */\r
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */\r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */\r
+\r
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */\r
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */\r
+\r
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */\r
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */\r
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */\r
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */\r
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */\r
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */\r
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */\r
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */\r
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */\r
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */\r
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */\r
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */\r
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */\r
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */\r
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */\r
+\r
+/*!< MCO configuration */\r
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
#else\r
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */\r
#endif /* STM32F10X_CL */\r
\r
/***************** Bit definition for RCC_APB2RSTR register *****************/\r
-#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */\r
-#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */\r
-#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */\r
-#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */\r
-#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */\r
-#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */\r
-#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */\r
-#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */\r
-#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */\r
-#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */\r
-\r
-#ifndef STM32F10X_LD\r
- #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */\r
+#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */\r
+#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */\r
+#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */\r
+#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */\r
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
+#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */\r
+#endif\r
\r
-#ifdef STM32F10X_HD\r
- #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */\r
- #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */\r
- #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */\r
- #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */\r
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */\r
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */\r
+#endif\r
+\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
+ #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */\r
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */\r
+ #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */\r
+ #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */\r
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */\r
+#endif\r
+\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */\r
+ #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */\r
+ #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */\r
+#endif /* STM32F10X_XL */\r
\r
/***************** Bit definition for RCC_APB1RSTR register *****************/\r
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */\r
+#endif\r
+\r
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */\r
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
\r
-#ifndef STM32F10X_LD\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */\r
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
-#endif /* STM32F10X_HD */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)\r
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */\r
#endif\r
\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)\r
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */\r
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
#endif\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
+ #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ \r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */\r
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */\r
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */\r
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */\r
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ \r
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */\r
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ \r
+#endif\r
+\r
#ifdef STM32F10X_CL\r
- #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */\r
+ #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */\r
#endif /* STM32F10X_CL */\r
\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */\r
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */\r
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */\r
+#endif /* STM32F10X_XL */\r
+\r
/****************** Bit definition for RCC_AHBENR register ******************/\r
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */\r
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */\r
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */\r
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */\r
\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)\r
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */\r
#endif\r
\r
-#ifdef STM32F10X_HD\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */\r
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */\r
-#endif /* STM32F10X_HD */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */\r
+#endif\r
\r
#ifdef STM32F10X_CL\r
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */\r
#endif /* STM32F10X_CL */\r
\r
/****************** Bit definition for RCC_APB2ENR register *****************/\r
-#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */\r
-#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */\r
-#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */\r
-#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */\r
-#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */\r
-#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */\r
-#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */\r
-#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */\r
-#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */\r
-#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */\r
-\r
-#ifndef STM32F10X_LD\r
- #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */\r
+#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */\r
+#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */\r
+#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */\r
+#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */\r
+#endif\r
\r
-#ifdef STM32F10X_HD\r
- #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */\r
- #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */\r
- #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */\r
- #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */\r
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */\r
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */\r
+#endif\r
+\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
+ #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */\r
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */\r
+ #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */\r
+ #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */\r
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */\r
+#endif\r
+\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */\r
+ #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */\r
+ #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */\r
+#endif\r
\r
/***************** Bit definition for RCC_APB1ENR register ******************/\r
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */\r
+#endif\r
+\r
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */\r
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
\r
-#ifndef STM32F10X_LD\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
-#endif /* STM32F10X_HD */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
\r
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)\r
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */\r
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
#endif\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
+ #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ \r
+#endif\r
+\r
+#ifdef STM32F10X_HD_VL\r
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */\r
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */\r
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */\r
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */\r
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ \r
+#endif /* STM32F10X_HD_VL */\r
+\r
#ifdef STM32F10X_CL\r
- #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */\r
+ #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */\r
#endif /* STM32F10X_CL */\r
\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */\r
+#endif /* STM32F10X_XL */\r
+\r
/******************* Bit definition for RCC_BDCR register *******************/\r
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */\r
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */\r
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */\r
#endif /* STM32F10X_CL */\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/******************* Bit definition for RCC_CFGR2 register ******************/\r
+/*!< PREDIV1 configuration */\r
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */\r
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */\r
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */\r
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */\r
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */\r
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */\r
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */\r
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */\r
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */\r
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */\r
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */\r
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */\r
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */\r
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */\r
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */\r
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */\r
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */\r
+#endif\r
+ \r
/******************************************************************************/\r
/* */\r
/* General Purpose and Alternate Function I/O */\r
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */\r
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/****************** Bit definition for AFIO_MAPR2 register ******************/\r
+#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */\r
+#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */\r
+#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */\r
+#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */\r
+#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */\r
+#endif\r
+\r
+#ifdef STM32F10X_HD_VL\r
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */\r
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */\r
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */\r
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */\r
+#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */\r
+#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */\r
+#endif\r
+\r
+#ifdef STM32F10X_XL \r
+/****************** Bit definition for AFIO_MAPR2 register ******************/\r
+#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */\r
+#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */\r
+#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */\r
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */\r
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */\r
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */\r
+#endif\r
+\r
/******************************************************************************/\r
/* */\r
/* SystemTick */\r
/******************* Bit definition for DAC_DOR2 register *******************/\r
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CEC */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for CEC_CFGR register ******************/\r
+#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */\r
+#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */\r
+#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */\r
+#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */\r
+\r
+/******************** Bit definition for CEC_OAR register ******************/\r
+#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */\r
+#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+\r
+/******************** Bit definition for CEC_PRES register ******************/\r
+#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */\r
+\r
+/******************** Bit definition for CEC_ESR register ******************/\r
+#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */\r
+#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */\r
+#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */\r
+#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */\r
+#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */\r
+#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */\r
+#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */\r
+\r
+/******************** Bit definition for CEC_CSR register ******************/\r
+#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */\r
+#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */\r
+#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */\r
+#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */\r
+#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */\r
+#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */\r
+#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */\r
+#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */\r
+\r
+/******************** Bit definition for CEC_TXD register ******************/\r
+#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */\r
+\r
+/******************** Bit definition for CEC_RXD register ******************/\r
+#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */\r
+\r
/******************************************************************************/\r
/* */\r
/* TIM */\r
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
\r
/******************* Bit definition for TIM_CNT register ********************/\r
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BCR2 register *******************/\r
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BCR3 register *******************/\r
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BCR4 register *******************/\r
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BTR1 register ******************/\r
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */\r
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */\r
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */\r
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */\r
\r
/****************** Bit definition for USART_CR2 register *******************/\r
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */\r
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */\r
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */\r
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */\r
\r
/****************** Bit definition for USART_GTPR register ******************/\r
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */\r
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */\r
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */\r
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */\r
\r
/******************************************************************************/\r
/* */\r
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */\r
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */\r
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */\r
-#define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */\r
+#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */\r
\r
/****************** Bit definition for FLASH_WRPR register ******************/\r
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */\r
* @}\r
*/\r
\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
\r
SysTick_Config(period_ticks);\r
\r
- /* Set SysTick Priority to 3 */\r
- NVIC_SetPriority(SysTick_IRQn, 0x0C);\r
-\r
#if 0\r
// SysTick interrupt each 250ms with counter clock equal to 9MHz\r
if (SysTick_Config((SystemFrequency / 8) / 4)) {\r
\r
.text :\r
{\r
+ . = ALIGN(4);\r
*(.text .text.* );\r
*(.glue_7) /* TODO */\r
*(.glue_7t) /* TODO */\r
SORT(*)(.test_etask);\r
\r
/* ST/ARM special variable to initialize .data */\r
+ . = ALIGN(4);\r
_etext = .;\r
} > flash\r
\r
\r
/* Read-only data section. */\r
.rodata : { \r
+ . = ALIGN(4);\r
*(.rodata .rodata.* .gnu.linkonce.r.*)\r
+ . = ALIGN(4);\r
_sidata = ALIGN(.,4);\r
} > flash\r
\r
- .data : AT(ALIGN(LOADADDR(.rodata)+SIZEOF(.rodata),4)) {\r
+ .data : AT ( _sidata )\r
+ {\r
+ . = ALIGN(4);\r
_sdata = .; \r
*(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ . = ALIGN(4);\r
_edata = .; \r
} > ram\r
\r
.t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
.bss : {\r
+ . = ALIGN(4);\r
_sbss = ., \r
*(.bss .bss.* COMMON .gnu.linkonce.b.*);\r
+ . = ALIGN(4);\r
_ebss = .; \r
} > ram\r
\r
\r
if (E_OK == Adc_CheckReadGroup (group))\r
{\r
- if ((ADC_CONV_MODE_CONTINOUS == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
+ if ((ADC_CONV_MODE_CONTINUOUS == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
((ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
(ADC_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
{\r
level = STD_LOW;\r
}\r
\r
- cleanup: return (level);\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return (level);\r
}\r
\r
void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level)\r
\r
Dio_WritePort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId), portVal);\r
\r
- cleanup: return;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
}\r
\r
Dio_PortLevelType Dio_ReadPort(Dio_PortType portId)\r
else if(portId == DIO_PORT_T){level = PTT;}\r
else if(portId == DIO_PORT_H){level = PTH;}\r
\r
- cleanup: return level;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
}\r
\r
void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level)\r
else if(portId == DIO_PORT_T){PTT = level;}\r
else if(portId == DIO_PORT_H){PTH = level;}\r
\r
- cleanup: return;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
}\r
\r
Dio_PortLevelType Dio_ReadChannelGroup(\r
// Shift down\r
level = level >> channelGroupIdPtr->offset;\r
\r
- cleanup: return level;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
}\r
\r
void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr,\r
\r
Dio_WritePort(channelGroupIdPtr->port, portVal);\r
\r
- cleanup: return;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
}\r
\r
_portState = PORT_INITIALIZED;\r
_configPtr = configType;\r
- cleanup: return;\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+ cleanup:\r
+#endif\r
+ return;\r
}\r
\r
/** @req PORT141 */\r
DDRT = curValue;\r
#endif\r
\r
- cleanup: return;\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+ cleanup:\r
+#endif\r
+ return;\r
}\r
\r
/** req PORT143 */\r
#include "regs.h"\r
#include "arc.h"\r
\r
-#if PWM_DEV_EROR_DETECT==STD_ON\r
+#if PWM_DEV_ERROR_DETECT==STD_ON\r
#define PWM_VALIDATE(_exp, _errid) \\r
if (!(_exp)) { \\r
Pwm_ReportError(_errid); \\r
#define Pwm_VALIDATE_INITIALIZED() PWM_VALIDATE(Pwm_ModuleState == PWM_STATE_INITIALIZED, PWM_E_UNINIT)\r
#define Pwm_VALIDATE_UNINITIALIZED() PWM_VALIDATE(Pwm_ModuleState != PWM_STATE_INITIALIZED, PWM_E_ALREADY_INITIALIZED)\r
#else\r
+ #define PWM_VALIDATE(_exp, _errid)\r
#define Pwm_VALIDATE_CHANNEL(ch)\r
#define Pwm_VALIDATE_INITIALIZED()\r
#define Pwm_VALIDATE_UNINITIALIZED()\r
Pwm_ChannelType channel_iterator;\r
\r
Pwm_VALIDATE_UNINITIALIZED();\r
- #if PWM_DEV_EROR_DETECT==STD_ON\r
+ #if PWM_DEV_ERROR_DETECT==STD_ON\r
/*\r
* PWM046: If development error detection is enabled for the Pwm module,\r
* the function Pwm_Init shall raise development error PWM_E_PARAM_CONFIG\r
--- /dev/null
+#ifndef _REGS_HCS12D_H_\r
+#define _REGS_HCS12D_H_\r
+\r
+#define IO_BASE 0\r
+\r
+#define ienable() __asm("cli");\r
+#define idisable() __asm("orcc #0x10")\r
+#define xenable() __asm("andcc #0xbf")\r
+#define xdisable()__asm("orcc #0x40")\r
+\r
+/**\r
+ * constant offsets to use where a C expression doesn't work\r
+ * You may use it with GEL\r
+ */\r
+#define M6811_PORTA 0x00\r
+#define M6811_PORTB 0x01\r
+#define M6811_PTT 0x240\r
+#define M6811_PTM 0x250\r
+#define M6811_PTP 0x258\r
+#define M6811_PTH 0x260\r
+\r
+#define PORTIO_8 *(volatile unsigned char *)\r
+#define PORTIO_16 *(volatile unsigned short int *)\r
+\r
+\r
+/* \r
+ * Core HC12 Registers\r
+ */\r
+#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
+#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
+#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
+#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
+#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
+#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
+#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
+#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
+#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
+#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
+#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
+#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
+#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
+#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
+#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
+#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
+#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
+#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
+#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
+#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
+#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
+#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
+#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
+#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
+\r
+// Bitflags - PEAR\r
+#define NOACCE 0x80\r
+#define PIPOE 0x20\r
+#define NECLK 0x10\r
+#define LSTRE 0x08\r
+#define RDWE 0x04\r
+\r
+// INTCR bitflags\r
+#define IRQE 0x80\r
+#define IRQEN 0x40\r
+#define DLY 0x20\r
+\r
+// BKP Module\r
+#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
+#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
+#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
+#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
+#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
+#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
+\r
+// MEBI Module \r
+#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
+#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
+#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
+\r
+// CRG Module \r
+#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
+#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
+#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
+#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
+#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
+#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
+#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
+#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
+#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
+#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
+#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
+#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
+\r
+// CRG bitflags\r
+#define RTIF 0x80\r
+#define RTIE 0x80\r
+#define LOCK 0x08\r
+#define AUTO 0x20\r
+#define PLLSEL 0x80\r
+\r
+// COPCTL bitflags\r
+#define WCOP 0x80\r
+#define RSBCK 0x40\r
+\r
+// ECT Module\r
+#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
+#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
+#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
+#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
+#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
+#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
+#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
+#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
+#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
+#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
+#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
+#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
+#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
+#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
+#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
+#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
+#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
+#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
+#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
+#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
+#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
+#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
+#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
+#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
+#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
+#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
+#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
+#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
+#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
+#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
+#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
+#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
+#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
+#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
+#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
+#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
+#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
+#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
+#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
+#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
+#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
+#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
+#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
+#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
+#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
+#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
+#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
+\r
+#define TEN 0x80\r
+#define TSFRZ 0x20\r
+#define TOI 0x80\r
+#define MCZI 0x80\r
+#define MODMC 0x40\r
+#define MCEN 0x4\r
+#define MCPR1 0x2\r
+#define MCPR0 0x1\r
+\r
+#define MCPRE_VAL_1 0\r
+#define MCPRE_VAL_4 MCPR0\r
+#define MCPRE_VAL_8 MCPR1\r
+#define MCPRE_VAL_16 MCPR0 | MCPR1\r
+\r
+// ATD0 Module \r
+#define ATD0_BASE (IO_BASE + 0x80)\r
+#define ATD0CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D0 control register 0 */\r
+#define ATD0CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D0 control register 1 */\r
+#define ATD0CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D0 control register 2 */\r
+#define ATD0CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D0 control register 3 */\r
+#define ATD0CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D0 control register 4 */\r
+#define ATD0CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D0 control register 5 */\r
+#define ATD0STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D0 status register 0 */\r
+#define ATD0STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D0 status register 1 */\r
+#define ATD0TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D0 test register 0 */\r
+#define ATD0TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D0 test register 1 */\r
+#define ATD0DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D0 interrupt enable */\r
+#define PORTAD0 PORTIO_8(IO_BASE + 0x8f) /* port AD0 data input register */\r
+#define ATD0DR0 PORTIO_16(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR0H PORTIO_8(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR1 PORTIO_16(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR1H PORTIO_8(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR2 PORTIO_16(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR2H PORTIO_8(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR3 PORTIO_16(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR3H PORTIO_8(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR4 PORTIO_16(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR4H PORTIO_8(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+#define ATD0DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+\r
+// ATDnCTL5 bitflags\r
+#define DJM 0x80\r
+#define DSGN 0x40\r
+#define SCAN 0x20\r
+#define MULT 0x10\r
+\r
+// ATDnSTAT0 bitflags\r
+#define SCF 0x80\r
+#define ETORF 0x20\r
+#define FIFOR 0x10\r
+\r
+// PWM Module \r
+#define PWME PORTIO_8(IO_BASE + 0xa0) /* PWM Enable */\r
+#define PWMPOL PORTIO_8(IO_BASE + 0xa1) /* PWM Clock Polarity */\r
+#define PWMCLK PORTIO_8(IO_BASE + 0xa2) /* PWM Clocks */\r
+#define PWMPRCLK PORTIO_8(IO_BASE + 0xa3) /* PWM prescale clock select */\r
+#define PWMCAE PORTIO_8(IO_BASE + 0xa4) /* PWM center align enable */\r
+#define PWMCTL PORTIO_8(IO_BASE + 0xa5) /* PWM Control Register */\r
+#define PWMTST PORTIO_8(IO_BASE + 0xa6) /* PWM Test Register */\r
+#define PWMPRSC PORTIO_8(IO_BASE + 0xa7) /* PWM Test Register */\r
+#define PWMSCLA PORTIO_8(IO_BASE + 0xa8) /* PWM scale A */\r
+#define PWMSCLB PORTIO_8(IO_BASE + 0xa9) /* PWM scale B */\r
+#define PWMSCNTA PORTIO_8(IO_BASE + 0xaa) /* PWM Test Register A */\r
+#define PWMSCNTB PORTIO_8(IO_BASE + 0xab) /* PWM Test Register B */\r
+#define PWMCNT0 PORTIO_8(IO_BASE + 0xac) /* PWM Channel Counter 0 */\r
+#define PWMCNT1 PORTIO_8(IO_BASE + 0xad) /* PWM Channel Counter 1 */\r
+#define PWMCNT2 PORTIO_8(IO_BASE + 0xae) /* PWM Channel Counter 2 */\r
+#define PWMCNT3 PORTIO_8(IO_BASE + 0xaf) /* PWM Channel Counter 3 */\r
+#define PWMCNT4 PORTIO_8(IO_BASE + 0xb0) /* PWM Channel Counter 4 */\r
+#define PWMCNT5 PORTIO_8(IO_BASE + 0xb1) /* PWM Channel Counter 5 */\r
+#define PWMCNT6 PORTIO_8(IO_BASE + 0xb2) /* PWM Channel Counter 6 */\r
+#define PWMCNT7 PORTIO_8(IO_BASE + 0xb3) /* PWM Channel Counter 7 */\r
+#define PWMPER0 PORTIO_8(IO_BASE + 0xb4) /* PWM Channel Period 0 */\r
+#define PWMPER1 PORTIO_8(IO_BASE + 0xb5) /* PWM Channel Period 1 */\r
+#define PWMPER2 PORTIO_8(IO_BASE + 0xb6) /* PWM Channel Period 2 */\r
+#define PWMPER3 PORTIO_8(IO_BASE + 0xb7) /* PWM Channel Period 3 */\r
+#define PWMPER4 PORTIO_8(IO_BASE + 0xb8) /* PWM Channel Period 4 */\r
+#define PWMPER5 PORTIO_8(IO_BASE + 0xb9) /* PWM Channel Period 5 */\r
+#define PWMPER6 PORTIO_8(IO_BASE + 0xba) /* PWM Channel Period 6 */\r
+#define PWMPER7 PORTIO_8(IO_BASE + 0xbb) /* PWM Channel Period 7 */\r
+#define PWMDTY0 PORTIO_8(IO_BASE + 0xbc) /* PWM Channel Duty 0 */\r
+#define PWMDTY1 PORTIO_8(IO_BASE + 0xbd) /* PWM Channel Duty 1 */\r
+#define PWMDTY2 PORTIO_8(IO_BASE + 0xbe) /* PWM Channel Duty 2 */\r
+#define PWMDTY3 PORTIO_8(IO_BASE + 0xbf) /* PWM Channel Duty 3 */\r
+#define PWMDTY4 PORTIO_8(IO_BASE + 0xc0) /* PWM Channel Duty 4 */\r
+#define PWMDTY5 PORTIO_8(IO_BASE + 0xc1) /* PWM Channel Duty 5 */\r
+#define PWMDTY6 PORTIO_8(IO_BASE + 0xc2) /* PWM Channel Duty 6 */\r
+#define PWMDTY7 PORTIO_8(IO_BASE + 0xc3) /* PWM Channel Duty 7 */\r
+#define PWMSDN PORTIO_8(IO_BASE + 0xc4) /* PWM shutdown register */\r
+\r
+#define PWMCNT01_16BIT PORTIO_16(IO_BASE + 0xac) /* pwm channel 0,1 counter, 16bit */\r
+#define PWMCNT23_16BIT PORTIO_16(IO_BASE + 0xae) /* pwm channel 2,3 counter, 16bit */\r
+#define PWMCNT45_16BIT PORTIO_16(IO_BASE + 0xb0) /* pwm channel 4,5 counter, 16bit */\r
+#define PWMCNT67_16BIT PORTIO_16(IO_BASE + 0xb2) /* pwm channel 6,7 counter, 16bit */\r
+#define PWMPER01_16BIT PORTIO_16(IO_BASE + 0xb4) /* pwm channel 0,1 period, 16bit */\r
+#define PWMPER23_16BIT PORTIO_16(IO_BASE + 0xb6) /* pwm channel 2,3 period, 16bit */\r
+#define PWMPER45_16BIT PORTIO_16(IO_BASE + 0xb8) /* pwm channel 4,5 period, 16bit */\r
+#define PWMPER67_16BIT PORTIO_16(IO_BASE + 0xba) /* pwm channel 6,7 period, 16bit */\r
+#define PWMDTY01_16BIT PORTIO_16(IO_BASE + 0xbc) /* pwm channel 0,1 duty cycle, 16bit */\r
+#define PWMDTY23_16BIT PORTIO_16(IO_BASE + 0xbe) /* pwm channel 2,3 duty cycle, 16bit */\r
+#define PWMDTY45_16BIT PORTIO_16(IO_BASE + 0xc0) /* pwm channel 4,5 duty cycle, 16bit */\r
+#define PWMDTY67_16BIT PORTIO_16(IO_BASE + 0xc2) /* pwm channel 6,7 duty cycle, 16bit */\r
+\r
+\r
+\r
+// SCI register offsets\r
+#define _SCIBD 0x0 /* SCI baud rate high */\r
+#define _SCIBDH 0x0 /* SCI baud rate high */\r
+#define _SCIBDL 0x1 /* SCI baud rate low */\r
+#define _SCICR1 0x2 /* SCI control register 1 */\r
+#define _SCICR2 0x3 /* SCI control register 2 */\r
+#define _SCISR1 0x4 /* SCI status register 1 */\r
+#define _SCISR2 0x5 /* SCI status register 2 */\r
+#define _SCIDRH 0x6 /* SCI data register high */\r
+#define _SCIDRL 0x7 /* SCI data register low */\r
+\r
+// SCI0 Module\r
+#define SCI0_BASE (IO_BASE + 0xc8)\r
+#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
+#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
+#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
+#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
+#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
+#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
+#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
+\r
+// SCI1 Module \r
+#define SCI1_BASE (IO_BASE + 0xd0)\r
+#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
+#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
+#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
+#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
+#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
+#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
+#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
+#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
+#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
+\r
+// SCInSR1\r
+#define TDRE 0x80\r
+#define RDRF 0x20\r
+#define IDLE 0x10\r
+\r
+// SPI register offsets\r
+#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
+#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
+#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
+#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
+#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
+\r
+// SPI0 Module \r
+#define SPI0_BASE (IO_BASE + 0xd8)\r
+#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
+#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
+#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
+#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
+#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
+\r
+// SPInCR1\r
+#define SPIE 0x80\r
+#define SPE 0x40\r
+#define SPTIE 0x20\r
+#define MSTR 0x10\r
+#define CPOL 0x08\r
+#define CPHA 0x04\r
+#define SSOE 0x02\r
+#define LSBFE 0x01\r
+\r
+// SPInSR\r
+#define SPIF 0x80\r
+#define SPTEF 0x20\r
+#define MODF 0x10\r
+\r
+// I2C Module \r
+#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
+#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
+#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
+#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
+#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
+\r
+// IBSR\r
+#define TCF 0x80\r
+#define IAAS 0x40\r
+#define IBB 0x20\r
+#define IBAL 0x10\r
+#define SRW 0x04\r
+#define IBIF 0x02\r
+#define RXAK 0x01\r
+\r
+// BDLC Module\r
+#define DLCBCR1 PORTIO_8(IO_BASE + 0xe8) /* BDLC control register 1 */\r
+#define DLCBSVR PORTIO_8(IO_BASE + 0xe9) /* BDLC state vector register */\r
+#define DLCBCR2 PORTIO_8(IO_BASE + 0xea) /* BDLC control register 2 */\r
+#define DLCBDR PORTIO_8(IO_BASE + 0xeb) /* BDLC data register */\r
+#define DLCBARD PORTIO_8(IO_BASE + 0xec) /* BDLC analog round trip delay */\r
+#define DLCBRSR PORTIO_8(IO_BASE + 0xed) /* BDLC rate select register */\r
+#define DLCSCR PORTIO_8(IO_BASE + 0xee) /* BDLC control register */\r
+#define DLCBSTAT PORTIO_8(IO_BASE + 0xef) /* BDLC status register */\r
+\r
+// SPI1 Module\r
+#define SPI1_BASE (IO_BASE + 0xf0)\r
+#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
+#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
+#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
+#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
+#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
+\r
+// SPI2 Module\r
+#define SPI2_BASE (IO_BASE + 0xf8)\r
+#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
+#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
+#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
+#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
+#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
+\r
+// FLC Module\r
+#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
+#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
+#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
+#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
+#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
+#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
+\r
+// EEPROM Module\r
+#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
+#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
+#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
+#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
+#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
+\r
+// ATD1 Module \r
+#define ATD1_BASE (IO_BASE + 0x120)\r
+#define ATD1CTL0 PORTIO_8(IO_BASE + 0x120) /* A/D1 control register 0 */\r
+#define ATD1CTL1 PORTIO_8(IO_BASE + 0x121) /* A/D1 control register 1 */\r
+#define ATD1CTL2 PORTIO_8(IO_BASE + 0x122) /* A/D1 control register 2 */\r
+#define ATD1CTL3 PORTIO_8(IO_BASE + 0x123) /* A/D1 control register 3 */\r
+#define ATD1CTL4 PORTIO_8(IO_BASE + 0x124) /* A/D1 control register 4 */\r
+#define ATD1CTL5 PORTIO_8(IO_BASE + 0x125) /* A/D1 control register 5 */\r
+#define ATD1STAT0 PORTIO_8(IO_BASE + 0x126) /* A/D1 status register 0 */\r
+#define ATD1STAT1 PORTIO_8(IO_BASE + 0x127) /* A/D1 status register 1 */\r
+#define ATD1TEST0 PORTIO_8(IO_BASE + 0x128) /* A/D1 test register 0 */\r
+#define ATD1TEST1 PORTIO_8(IO_BASE + 0x129) /* A/D1 test register 1 */\r
+#define ATD1DIEN PORTIO_8(IO_BASE + 0x12d) /* A/D1 interrupt enable */\r
+#define PORTAD1 PORTIO_8(IO_BASE + 0x12f) /* port AD1 data input register */\r
+#define ATD1DR0 PORTIO_16(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR0H PORTIO_8(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR1 PORTIO_16(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR1H PORTIO_8(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR2 PORTIO_16(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR2H PORTIO_8(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR3 PORTIO_16(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR3H PORTIO_8(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR4 PORTIO_16(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR4H PORTIO_8(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR5 PORTIO_16(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR5H PORTIO_8(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR6 PORTIO_16(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR6H PORTIO_8(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR7 PORTIO_16(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+#define ATD1DR7H PORTIO_8(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+\r
+// CAN0 Module \r
+#define CAN0_BASE (IO_BASE + 0x140)\r
+#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
+#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
+#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
+#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
+#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
+#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
+#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
+#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
+#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
+#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
+#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
+#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
+#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
+#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
+#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
+#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
+#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
+#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
+#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
+#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
+#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
+#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
+#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
+#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
+#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
+#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
+#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
+#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
+#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
+#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
+#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
+#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
+\r
+// CAN1 Module \r
+#define CAN1_BASE (IO_BASE + 0x180)\r
+#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
+#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
+#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
+#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
+#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
+#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
+#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
+#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
+#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
+#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
+#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
+#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
+#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
+#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
+#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
+#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
+#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
+#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
+#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
+#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
+#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
+#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
+#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
+#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
+#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
+#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
+#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
+#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
+#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
+#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
+#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
+#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
+\r
+// CAN2 Module \r
+#define CAN2_BASE (IO_BASE + 0x1c0)\r
+#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
+#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
+#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
+#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
+#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
+#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
+#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
+#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
+#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
+#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
+#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
+#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
+#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
+#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
+#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
+#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
+#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
+#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
+#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
+#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
+#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
+#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
+#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
+#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
+#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
+#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
+#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
+#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
+#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
+#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
+#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
+#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
+\r
+// CAN3 Module \r
+#define CAN3_BASE (IO_BASE + 0x200)\r
+#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
+#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
+#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
+#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
+#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
+#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
+#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
+#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
+#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
+#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
+#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
+#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
+#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
+#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
+#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
+#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
+#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
+#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
+#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
+#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
+#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
+#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
+#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
+#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
+#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
+#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
+#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
+#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
+#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
+#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
+#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
+#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
+\r
+\r
+// Port T register offsets\r
+#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
+#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
+#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
+#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
+#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
+#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
+\r
+// Port S\r
+#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
+#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
+#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
+#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
+#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
+#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
+#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
+\r
+// Port M\r
+#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
+#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
+#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
+#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
+#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
+#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
+#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
+\r
+#define MODDR PORTIO_8(IO_BASE + 0x257) /* Module routing register */\r
+\r
+// Port P\r
+#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
+#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
+#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
+#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
+#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
+#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
+#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
+#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
+\r
+// Port H\r
+#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
+#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
+#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
+#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
+#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
+#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
+#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
+#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
+\r
+// Port J\r
+#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
+#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
+#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
+#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
+#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
+#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
+#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
+#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
+\r
+\r
+\r
+// CAN4 Module \r
+#define CAN4_BASE (IO_BASE + 0x280)\r
+#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
+#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
+#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
+#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
+#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
+#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
+#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
+#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
+#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
+#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
+#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
+#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
+#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
+#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
+#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
+#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
+#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
+#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
+#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
+#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
+#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
+#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
+#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
+#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
+#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
+#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
+#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
+#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
+#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
+#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
+#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
+#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
+\r
+\r
+\r
+# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
+# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
+# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
+# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
+# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
+# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+\r
+#endif /* ifndef _REGS_HCS12D_H_ */\r
--- /dev/null
+#ifndef _REGS_HCS12XD_H_\r
+#define _REGS_HCS12XD_H_\r
+\r
+#define IO_BASE 0\r
+\r
+#define ienable() __asm("cli");\r
+#define idisable() __asm("orcc #0x10")\r
+#define xenable() __asm("andcc #0xbf")\r
+#define xdisable()__asm("orcc #0x40")\r
+\r
+/**\r
+ * constant offsets to use where a C expression doesn't work\r
+ * You may use it with GEL\r
+ */\r
+#define M6811_PORTA 0x00\r
+#define M6811_PORTB 0x01\r
+#define M6811_PTT 0x240\r
+#define M6811_PTM 0x250\r
+#define M6811_PTP 0x258\r
+#define M6811_PTH 0x260\r
+\r
+#define PORTIO_8 *(volatile unsigned char *)\r
+#define PORTIO_16 *(volatile unsigned short int *)\r
+\r
+\r
+/* \r
+ * Core HC12 Registers\r
+ */\r
+#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
+#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
+#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
+#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
+#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
+#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
+#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
+#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
+#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
+#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
+#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
+#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
+#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
+#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
+#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
+#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
+#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
+#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
+#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
+#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
+#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
+#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
+#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
+#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
+\r
+// Bitflags - PEAR\r
+#define NOACCE 0x80\r
+#define PIPOE 0x20\r
+#define NECLK 0x10\r
+#define LSTRE 0x08\r
+#define RDWE 0x04\r
+\r
+// INTCR bitflags\r
+#define IRQE 0x80\r
+#define IRQEN 0x40\r
+#define DLY 0x20\r
+\r
+// BKP Module\r
+#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
+#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
+#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
+#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
+#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
+#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
+\r
+// MEBI Module \r
+#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
+#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
+#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
+\r
+// CRG Module \r
+#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
+#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
+#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
+#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
+#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
+#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
+#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
+#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
+#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
+#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
+#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
+#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
+\r
+// CRG bitflags\r
+#define RTIF 0x80\r
+#define RTIE 0x80\r
+#define LOCK 0x08\r
+#define AUTO 0x20\r
+#define PLLSEL 0x80\r
+\r
+// COPCTL bitflags\r
+#define WCOP 0x80\r
+#define RSBCK 0x40\r
+\r
+// ECT Module\r
+#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
+#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
+#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
+#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
+#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
+#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
+#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
+#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
+#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
+#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
+#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
+#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
+#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
+#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
+#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
+#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
+#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
+#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
+#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
+#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
+#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
+#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
+#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
+#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
+#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
+#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
+#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
+#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
+#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
+#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
+#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
+#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
+#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
+#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
+#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
+#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
+#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
+#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
+#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
+#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
+#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
+#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
+#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
+#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
+#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
+#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
+#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
+\r
+#define TEN 0x80\r
+#define TSFRZ 0x20\r
+#define TOI 0x80\r
+#define MCZI 0x80\r
+#define MODMC 0x40\r
+#define MCEN 0x4\r
+#define MCPR1 0x2\r
+#define MCPR0 0x1\r
+\r
+#define MCPRE_VAL_1 0\r
+#define MCPRE_VAL_4 MCPR0\r
+#define MCPRE_VAL_8 MCPR1\r
+#define MCPRE_VAL_16 MCPR0 | MCPR1\r
+\r
+// ATD1 Module\r
+#define ATD1_BASE (IO_BASE + 0x80)\r
+#define ATD1CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D1 control register 0 */\r
+#define ATD1CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D1 control register 1 */\r
+#define ATD1CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D1 control register 2 */\r
+#define ATD1CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D1 control register 3 */\r
+#define ATD1CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D1 control register 4 */\r
+#define ATD1CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D1 control register 5 */\r
+#define ATD1STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D1 status register 0 */\r
+#define ATD1STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D1 status register 1 */\r
+#define ATD1TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D1 test register 0 */\r
+#define ATD1TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D1 test register 1 */\r
+#define ATD1DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D1 interrupt enable */\r
+#define PORTAD1 PORTIO_8(IO_BASE + 0x8f) /* port AD1 data input register */\r
+#define ATD1DR0 PORTIO_16(IO_BASE + 0x90) /* A/D1 result 0 */\r
+#define ATD1DR0H PORTIO_8(IO_BASE + 0x90) /* A/D1 result 0 */\r
+#define ATD1DR1 PORTIO_16(IO_BASE + 0x92) /* A/D1 result 1 */\r
+#define ATD1DR1H PORTIO_8(IO_BASE + 0x92) /* A/D1 result 1 */\r
+#define ATD1DR2 PORTIO_16(IO_BASE + 0x94) /* A/D1 result 2 */\r
+#define ATD1DR2H PORTIO_8(IO_BASE + 0x94) /* A/D1 result 2 */\r
+#define ATD1DR3 PORTIO_16(IO_BASE + 0x96) /* A/D1 result 3 */\r
+#define ATD1DR3H PORTIO_8(IO_BASE + 0x96) /* A/D1 result 3 */\r
+#define ATD1DR4 PORTIO_16(IO_BASE + 0x98) /* A/D1 result 4 */\r
+#define ATD1DR4H PORTIO_8(IO_BASE + 0x98) /* A/D1 result 4 */\r
+#define ATD1DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D1 result 5 */\r
+#define ATD1DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D1 result 5 */\r
+#define ATD1DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D1 result 6 */\r
+#define ATD1DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D1 result 6 */\r
+#define ATD1DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D1 result 7 */\r
+#define ATD1DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D1 result 7 */\r
+\r
+// ATDnCTL5 bitflags\r
+#define DJM 0x80\r
+#define DSGN 0x40\r
+#define SCAN 0x20\r
+#define MULT 0x10\r
+\r
+// ATDnSTAT0 bitflags\r
+#define SCF 0x80\r
+#define ETORF 0x20\r
+#define FIFOR 0x10\r
+\r
+// PWM Module \r
+#define PWME PORTIO_8(IO_BASE + 0x300) /* PWM Enable */\r
+#define PWMPOL PORTIO_8(IO_BASE + 0x301) /* PWM Clock Polarity */\r
+#define PWMCLK PORTIO_8(IO_BASE + 0x302) /* PWM Clocks */\r
+#define PWMPRCLK PORTIO_8(IO_BASE + 0x303) /* PWM prescale clock select */\r
+#define PWMCAE PORTIO_8(IO_BASE + 0x304) /* PWM center align enable */\r
+#define PWMCTL PORTIO_8(IO_BASE + 0x305) /* PWM Control Register */\r
+#define PWMTST PORTIO_8(IO_BASE + 0x306) /* PWM Test Register */\r
+#define PWMPRSC PORTIO_8(IO_BASE + 0x307) /* PWM Test Register */\r
+#define PWMSCLA PORTIO_8(IO_BASE + 0x308) /* PWM scale A */\r
+#define PWMSCLB PORTIO_8(IO_BASE + 0x309) /* PWM scale B */\r
+#define PWMSCNTA PORTIO_8(IO_BASE + 0x30a) /* PWM Test Register A */\r
+#define PWMSCNTB PORTIO_8(IO_BASE + 0x30b) /* PWM Test Register B */\r
+#define PWMCNT0 PORTIO_8(IO_BASE + 0x30c) /* PWM Channel Counter 0 */\r
+#define PWMCNT1 PORTIO_8(IO_BASE + 0x30d) /* PWM Channel Counter 1 */\r
+#define PWMCNT2 PORTIO_8(IO_BASE + 0x30e) /* PWM Channel Counter 2 */\r
+#define PWMCNT3 PORTIO_8(IO_BASE + 0x30f) /* PWM Channel Counter 3 */\r
+#define PWMCNT4 PORTIO_8(IO_BASE + 0x310) /* PWM Channel Counter 4 */\r
+#define PWMCNT5 PORTIO_8(IO_BASE + 0x311) /* PWM Channel Counter 5 */\r
+#define PWMCNT6 PORTIO_8(IO_BASE + 0x312) /* PWM Channel Counter 6 */\r
+#define PWMCNT7 PORTIO_8(IO_BASE + 0x313) /* PWM Channel Counter 7 */\r
+#define PWMPER0 PORTIO_8(IO_BASE + 0x314) /* PWM Channel Period 0 */\r
+#define PWMPER1 PORTIO_8(IO_BASE + 0x315) /* PWM Channel Period 1 */\r
+#define PWMPER2 PORTIO_8(IO_BASE + 0x316) /* PWM Channel Period 2 */\r
+#define PWMPER3 PORTIO_8(IO_BASE + 0x317) /* PWM Channel Period 3 */\r
+#define PWMPER4 PORTIO_8(IO_BASE + 0x318) /* PWM Channel Period 4 */\r
+#define PWMPER5 PORTIO_8(IO_BASE + 0x319) /* PWM Channel Period 5 */\r
+#define PWMPER6 PORTIO_8(IO_BASE + 0x31a) /* PWM Channel Period 6 */\r
+#define PWMPER7 PORTIO_8(IO_BASE + 0x31b) /* PWM Channel Period 7 */\r
+#define PWMDTY0 PORTIO_8(IO_BASE + 0x31c) /* PWM Channel Duty 0 */\r
+#define PWMDTY1 PORTIO_8(IO_BASE + 0x31d) /* PWM Channel Duty 1 */\r
+#define PWMDTY2 PORTIO_8(IO_BASE + 0x31e) /* PWM Channel Duty 2 */\r
+#define PWMDTY3 PORTIO_8(IO_BASE + 0x31f) /* PWM Channel Duty 3 */\r
+#define PWMDTY4 PORTIO_8(IO_BASE + 0x320) /* PWM Channel Duty 4 */\r
+#define PWMDTY5 PORTIO_8(IO_BASE + 0x321) /* PWM Channel Duty 5 */\r
+#define PWMDTY6 PORTIO_8(IO_BASE + 0x322) /* PWM Channel Duty 6 */\r
+#define PWMDTY7 PORTIO_8(IO_BASE + 0x323) /* PWM Channel Duty 7 */\r
+#define PWMSDN PORTIO_8(IO_BASE + 0x324) /* PWM shutdown register */\r
+\r
+#define PWMCNT01_16BIT PORTIO_16(IO_BASE + 0x30c) /* pwm channel 0,1 counter, 16bit */\r
+#define PWMCNT23_16BIT PORTIO_16(IO_BASE + 0x30e) /* pwm channel 2,3 counter, 16bit */\r
+#define PWMCNT45_16BIT PORTIO_16(IO_BASE + 0x310) /* pwm channel 4,5 counter, 16bit */\r
+#define PWMCNT67_16BIT PORTIO_16(IO_BASE + 0x312) /* pwm channel 6,7 counter, 16bit */\r
+#define PWMPER01_16BIT PORTIO_16(IO_BASE + 0x314) /* pwm channel 0,1 period, 16bit */\r
+#define PWMPER23_16BIT PORTIO_16(IO_BASE + 0x316) /* pwm channel 2,3 period, 16bit */\r
+#define PWMPER45_16BIT PORTIO_16(IO_BASE + 0x318) /* pwm channel 4,5 period, 16bit */\r
+#define PWMPER67_16BIT PORTIO_16(IO_BASE + 0x31a) /* pwm channel 6,7 period, 16bit */\r
+#define PWMDTY01_16BIT PORTIO_16(IO_BASE + 0x31c) /* pwm channel 0,1 duty cycle, 16bit */\r
+#define PWMDTY23_16BIT PORTIO_16(IO_BASE + 0x31e) /* pwm channel 2,3 duty cycle, 16bit */\r
+#define PWMDTY45_16BIT PORTIO_16(IO_BASE + 0x320) /* pwm channel 4,5 duty cycle, 16bit */\r
+#define PWMDTY67_16BIT PORTIO_16(IO_BASE + 0x322) /* pwm channel 6,7 duty cycle, 16bit */\r
+\r
+\r
+\r
+// SCI register offsets\r
+#define _SCIBD 0x0 /* SCI baud rate high */\r
+#define _SCIBDH 0x0 /* SCI baud rate high */\r
+#define _SCIBDL 0x1 /* SCI baud rate low */\r
+#define _SCICR1 0x2 /* SCI control register 1 */\r
+#define _SCICR2 0x3 /* SCI control register 2 */\r
+#define _SCISR1 0x4 /* SCI status register 1 */\r
+#define _SCISR2 0x5 /* SCI status register 2 */\r
+#define _SCIDRH 0x6 /* SCI data register high */\r
+#define _SCIDRL 0x7 /* SCI data register low */\r
+\r
+// SCI0 Module\r
+#define SCI0_BASE (IO_BASE + 0xc8)\r
+#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
+#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
+#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
+#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
+#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
+#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
+#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
+\r
+// SCI1 Module \r
+#define SCI1_BASE (IO_BASE + 0xd0)\r
+#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
+#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
+#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
+#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
+#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
+#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
+#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
+#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
+#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
+\r
+// SCInSR1\r
+#define TDRE 0x80\r
+#define RDRF 0x20\r
+#define IDLE 0x10\r
+\r
+// SPI register offsets\r
+#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
+#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
+#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
+#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
+#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
+\r
+// SPI0 Module \r
+#define SPI0_BASE (IO_BASE + 0xd8)\r
+#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
+#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
+#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
+#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
+#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
+\r
+// SPInCR1\r
+#define SPIE 0x80\r
+#define SPE 0x40\r
+#define SPTIE 0x20\r
+#define MSTR 0x10\r
+#define CPOL 0x08\r
+#define CPHA 0x04\r
+#define SSOE 0x02\r
+#define LSBFE 0x01\r
+\r
+// SPInSR\r
+#define SPIF 0x80\r
+#define SPTEF 0x20\r
+#define MODF 0x10\r
+\r
+// I2C Module \r
+#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
+#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
+#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
+#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
+#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
+\r
+// IBSR\r
+#define TCF 0x80\r
+#define IAAS 0x40\r
+#define IBB 0x20\r
+#define IBAL 0x10\r
+#define SRW 0x04\r
+#define IBIF 0x02\r
+#define RXAK 0x01\r
+\r
+// SPI1 Module\r
+#define SPI1_BASE (IO_BASE + 0xf0)\r
+#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
+#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
+#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
+#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
+#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
+\r
+// SPI2 Module\r
+#define SPI2_BASE (IO_BASE + 0xf8)\r
+#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
+#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
+#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
+#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
+#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
+\r
+// FLC Module\r
+#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
+#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
+#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
+#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
+#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
+#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
+\r
+// EEPROM Module\r
+#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
+#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
+#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
+#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
+#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
+\r
+// ATD0 Module\r
+#define ATD0_BASE (IO_BASE + 0x2C0)\r
+#define ATD0CTL0 PORTIO_8(IO_BASE + 0x2C0) /* A/D0 control register 0 */\r
+#define ATD0CTL1 PORTIO_8(IO_BASE + 0x2C1) /* A/D0 control register 1 */\r
+#define ATD0CTL2 PORTIO_8(IO_BASE + 0x2C2) /* A/D0 control register 2 */\r
+#define ATD0CTL3 PORTIO_8(IO_BASE + 0x2C3) /* A/D0 control register 3 */\r
+#define ATD0CTL4 PORTIO_8(IO_BASE + 0x2C4) /* A/D0 control register 4 */\r
+#define ATD0CTL5 PORTIO_8(IO_BASE + 0x2C5) /* A/D0 control register 5 */\r
+#define ATD0STAT0 PORTIO_8(IO_BASE + 0x2C6) /* A/D0 status register 0 */\r
+#define ATD0STAT1 PORTIO_8(IO_BASE + 0x2C7) /* A/D0 status register 1 */\r
+#define ATD0TEST0 PORTIO_8(IO_BASE + 0x2C8) /* A/D0 test register 0 */\r
+#define ATD0TEST1 PORTIO_8(IO_BASE + 0x2C9) /* A/D0 test register 1 */\r
+#define ATD0DIEN PORTIO_8(IO_BASE + 0x2Cd) /* A/D0 interrupt enable */\r
+#define PORTAD0 PORTIO_8(IO_BASE + 0x2Cf) /* port AD0 data input register */\r
+#define ATD0DR0 PORTIO_16(IO_BASE + 0x2d0) /* A/D0 result 0 */\r
+#define ATD0DR0H PORTIO_8(IO_BASE + 0x2d0) /* A/D0 result 0 */\r
+#define ATD0DR1 PORTIO_16(IO_BASE + 0x2d2) /* A/D0 result 1 */\r
+#define ATD0DR1H PORTIO_8(IO_BASE + 0x2d2) /* A/D0 result 1 */\r
+#define ATD0DR2 PORTIO_16(IO_BASE + 0x2d4) /* A/D0 result 2 */\r
+#define ATD0DR2H PORTIO_8(IO_BASE + 0x2d4) /* A/D0 result 2 */\r
+#define ATD0DR3 PORTIO_16(IO_BASE + 0x2d6) /* A/D0 result 3 */\r
+#define ATD0DR3H PORTIO_8(IO_BASE + 0x2d6) /* A/D0 result 3 */\r
+#define ATD0DR4 PORTIO_16(IO_BASE + 0x2d8) /* A/D0 result 4 */\r
+#define ATD0DR4H PORTIO_8(IO_BASE + 0x2d8) /* A/D0 result 4 */\r
+#define ATD0DR5 PORTIO_16(IO_BASE + 0x2da) /* A/D0 result 5 */\r
+#define ATD0DR5H PORTIO_8(IO_BASE + 0x2da) /* A/D0 result 5 */\r
+#define ATD0DR6 PORTIO_16(IO_BASE + 0x2dc) /* A/D0 result 6 */\r
+#define ATD0DR6H PORTIO_8(IO_BASE + 0x2dc) /* A/D0 result 6 */\r
+#define ATD0DR7 PORTIO_16(IO_BASE + 0x2de) /* A/D0 result 7 */\r
+#define ATD0DR7H PORTIO_8(IO_BASE + 0x2de) /* A/D0 result 7 */\r
+\r
+// CAN0 Module \r
+#define CAN0_BASE (IO_BASE + 0x140)\r
+#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
+#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
+#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
+#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
+#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
+#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
+#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
+#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
+#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
+#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
+#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
+#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
+#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
+#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
+#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
+#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
+#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
+#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
+#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
+#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
+#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
+#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
+#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
+#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
+#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
+#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
+#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
+#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
+#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
+#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
+#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
+#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
+\r
+// CAN1 Module \r
+#define CAN1_BASE (IO_BASE + 0x180)\r
+#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
+#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
+#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
+#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
+#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
+#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
+#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
+#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
+#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
+#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
+#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
+#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
+#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
+#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
+#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
+#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
+#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
+#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
+#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
+#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
+#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
+#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
+#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
+#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
+#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
+#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
+#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
+#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
+#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
+#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
+#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
+#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
+\r
+// CAN2 Module \r
+#define CAN2_BASE (IO_BASE + 0x1c0)\r
+#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
+#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
+#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
+#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
+#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
+#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
+#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
+#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
+#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
+#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
+#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
+#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
+#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
+#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
+#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
+#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
+#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
+#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
+#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
+#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
+#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
+#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
+#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
+#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
+#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
+#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
+#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
+#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
+#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
+#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
+#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
+#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
+\r
+// CAN3 Module \r
+#define CAN3_BASE (IO_BASE + 0x200)\r
+#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
+#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
+#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
+#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
+#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
+#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
+#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
+#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
+#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
+#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
+#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
+#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
+#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
+#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
+#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
+#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
+#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
+#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
+#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
+#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
+#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
+#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
+#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
+#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
+#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
+#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
+#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
+#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
+#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
+#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
+#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
+#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
+\r
+\r
+// Port T register offsets\r
+#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
+#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
+#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
+#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
+#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
+#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
+\r
+// Port S\r
+#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
+#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
+#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
+#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
+#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
+#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
+#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
+\r
+// Port M\r
+#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
+#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
+#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
+#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
+#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
+#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
+#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
+\r
+#define MODDR PORTIO_8(IO_BASE + 0x257) /* Module routing register */\r
+\r
+// Port P\r
+#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
+#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
+#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
+#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
+#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
+#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
+#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
+#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
+\r
+// Port H\r
+#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
+#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
+#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
+#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
+#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
+#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
+#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
+#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
+\r
+// Port J\r
+#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
+#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
+#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
+#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
+#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
+#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
+#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
+#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
+\r
+\r
+\r
+// CAN4 Module \r
+#define CAN4_BASE (IO_BASE + 0x280)\r
+#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
+#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
+#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
+#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
+#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
+#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
+#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
+#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
+#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
+#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
+#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
+#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
+#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
+#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
+#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
+#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
+#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
+#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
+#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
+#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
+#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
+#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
+#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
+#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
+#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
+#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
+#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
+#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
+#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
+#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
+#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
+#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
+\r
+\r
+\r
+# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
+# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
+# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
+# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
+# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
+# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+\r
+#endif /* ifndef _REGS_HCS12XD_H_ */\r
}\r
\r
void *Os_ArchGetStackPtr( void ) {\r
+ void* val;\r
\r
-// return (void *)__get_MSP();\r
+ asm("sts _.tmp");\r
+ asm volatile("movw _.tmp, %0":"=m" (val));\r
+\r
+ return val;\r
}\r
\r
unsigned int Os_ArchGetScSize( void ) {\r
*/\r
\r
void Os_ArchSetTaskEntry(OsPcbType *pcbPtr ) {\r
- uint16_t *context_words = (uint16_t *)pcbPtr->stack.curr;\r
uint8_t *context_bytes = (uint8_t *)pcbPtr->stack.curr;\r
+ uint16_t temp;\r
\r
/* Set Return to start function */\r
\r
context_bytes[8] = OS_KERNEL_CODE_PPAGE;\r
\r
if( pcbPtr->proc_type == PROC_EXTENDED ) {\r
- context_words[8] = (uint16_t)Os_TaskStartExtended;\r
+ temp = (uint16_t)Os_TaskStartExtended;\r
+ context_bytes[HIGH_BYTE_RETURN_ADRESS] = temp >> 8;\r
+ context_bytes[LOW_BYTE_RETURN_ADRESS] = temp & 0xFF;\r
} else if( pcbPtr->proc_type == PROC_BASIC ) {\r
- context_words[8] = (uint16_t)Os_TaskStartBasic;\r
+ temp = (uint16_t)Os_TaskStartBasic;\r
+ context_bytes[HIGH_BYTE_RETURN_ADRESS] = temp >> 8;\r
+ context_bytes[LOW_BYTE_RETURN_ADRESS] = temp & 0xFF;\r
}\r
}\r
\r
\r
#define _ASSEMBLER_\r
#include "kernel_offset.h"\r
+#include "context.h"\r
#include "asm_hc1x.sx"\r
#include "context.sx"\r
\r
#define SC_PATTERN 0xde\r
#define LC_PATTERN 0xad\r
\r
-#define CONTEXT_SIZE_W 9\r
-\r
+#if defined(CFG_HCS12D)\r
+#define Y_SP_OFFSET 6 // The offset from P to Y in the context\r
+#define CONTEXT_SIZE_W 9 // The context size in words\r
+#define HIGH_BYTE_RETURN_ADRESS 16 // The offset in the context that contains the high order byte of return address\r
+#define LOW_BYTE_RETURN_ADRESS 17 // The offset in the context that contains the low order byte of return address\r
+\r
+#elif defined(CFG_HCS12XD)\r
+#define Y_SP_OFFSET 7 // The offset from P to Y in the context\r
+#define CONTEXT_SIZE_W 10 // The context size in words ( Actual size 9+1/2)\r
+#define HIGH_BYTE_RETURN_ADRESS 17 // The offset in the context that contains the high order byte of return address\r
+#define LOW_BYTE_RETURN_ADRESS 18 // The offset in the context that contains the low order byte of return address\r
+#else\r
+#error "HC1X: Subarchitecture not defined."\r
+#endif\r
\r
#endif /* CONTEXT_H_ */\r
sty 1, -sp // save Y -> ctx(Y)\r
stx 2, -sp // save X -> ctx(X)\r
stab 2, -sp // save B -> ctx(B) (skipping ctx(A))\r
+#ifdef CFG_HCS12D\r
pshc // save CCR -> ctx(CCR)\r
+#endif\r
+#ifdef CFG_HCS12XD \r
+ .short 0x1839 // save CCR -> ctx(CCR)\r
+#endif \r
psha // save P -> ctx(P) *\r
movw _.tmp ,2,-sp // save tmp -> ctx(tmp)\r
movw _.xy, 2,-sp // save xy -> ctx(xy)\r
movw 2,sp+, _.z // load z <- ctx(z)\r
movw 2,sp+, _.xy // load xy <- ctx(xy)\r
movw 2,sp+, _.tmp // load tmp <- ctx(tmp)\r
- ldy 6,sp // load Y <- ctx(Y)\r
- movb 1,sp+, 6,sp // move ctx(P) -> callctx(P)\r
- pulc // load CCR <- ctx(CCR)\r
+ ldy Y_SP_OFFSET,sp // load Y <- ctx(Y)\r
+ movb 1,sp+, Y_SP_OFFSET,sp // move ctx(P) -> callctx(P)\r
+#ifdef CFG_HCS12D\r
+ pulc // save CCR -> ctx(CCR)\r
+#endif\r
+#ifdef CFG_HCS12XD\r
+ .short 0x1838 // load CCR <- ctx(CCR)\r
+#endif\r
puld // load D <- ctx(D)\r
pulx // load X <- ctx(X)\r
ins // skipping ctx(Yh)\r
bad_irq_context_bank = (bank_and_ccr & 0xFF00) >> 8;\r
bad_irq_context_address = *(stack + 8);\r
\r
- for (;;);\r
+ for (;;)\r
+ asm("BGND"); // Jump to debugger\r
}\r
\r
void *Irq_Entry( uint8_t irq_nr, void *stack )\r
* @param vector\r
*/\r
void Irq_GenerateSoftInt( IrqType vector ) {\r
- (void)vector;\r
+ if (vector == IRQ_TYPE_SWI)\r
+ {\r
+ asm("swi");\r
+ }\r
+\r
+ if (vector == IRQ_TYPE_ILLEGAL)\r
+ {\r
+ asm(".short 0x1830"); // Trap instruction\r
+ }\r
}\r
\r
/**\r
\r
\r
/* PPAGE memory banks */\r
-\r
- .bank8 :\r
+ .bank_A :\r
{\r
- *(.bank8)\r
- *(.text.bank8*)\r
+ *(.bank_A)\r
+ *(.text.bank_A*)\r
\r
- /* BANK8 MODULES */\r
+ /* BANK_A MODULES */\r
Os_Cfg.o(.text)\r
EcuM.o(.text)\r
EcuM_Cfg.o(.text)\r
alarm.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank8 AT>bank8_lma =0xff\r
+ } > bank_A AT>bank_A_lma =0xff\r
\r
- .bank9 :\r
+ .bank_B :\r
{\r
- *(.bank9)\r
- *(.text.bank9*)\r
+ *(.bank_B)\r
+ *(.text.bank_B*)\r
\r
- /* BANK9 MODULES */\r
+ /* BANK_B MODULES */\r
resource.o(.text)\r
sched_table.o(.text)\r
counter.o(.text)\r
newlib_port.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank9 AT>bank9_lma =0xff\r
+ } > bank_B AT>bank_B_lma =0xff\r
\r
\r
- .bank10 :\r
+ .bank_C :\r
{\r
- *(.bank10)\r
- *(.text.bank10*)\r
+ *(.bank_C)\r
+ *(.text.bank_C*)\r
\r
- /* BANK10 MODULES */ \r
+ /* BANK_C MODULES */\r
+ printf.o(.text) \r
*_memcpy.o(.text)\r
*_memset.o(.text)\r
*_abort.o(.text)\r
*_memcpy.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank10 AT>bank10_lma =0xff\r
+ } > bank_C AT>bank_C_lma =0xff\r
\r
\r
- .bank11 :\r
+ .bank_D :\r
{\r
- *(.bank11)\r
- *(.text.bank11*)\r
+ *(.bank_D)\r
+ *(.text.bank_D*)\r
\r
- /* BANK11 MODULES */\r
+ /* BANK_D MODULES */\r
Can*.o(.text)\r
Pdu*.o(.text)\r
Dio*.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank11 AT>bank11_lma =0xff\r
+ } > bank_D AT>bank_D_lma =0xff\r
\r
\r
- .bank12 :\r
+ .bank_E :\r
{\r
- *(.bank12)\r
- *(.text.bank12*)\r
+ *(.bank_E)\r
+ *(.text.bank_E*)\r
\r
- /* BANK12 MODULES */\r
- Com*.o(.text)\r
+ /* BANK_E MODULES */\r
Port*.o(.text)\r
+ Com*.o(.text)\r
+ test_*.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank12 AT>bank12_lma =0xff\r
+ } > bank_E AT>bank_E_lma =0xff\r
\r
\r
- .bank13 :\r
+ .bank_F :\r
{\r
- *(.bank13)\r
- *(.text.bank13*)\r
+ *(.bank_F)\r
+ *(.text.bank_F*)\r
\r
- /* BANK13 MODULES */\r
+ /* BANK_F MODULES */\r
Adc*.o(.text)\r
- . = ALIGN(2);\r
- } > bank13 AT>bank13_lma =0xff\r
+ Dem*.o(.text)\r
+ IoHwAb*.o(.text)\r
+ . = ALIGN(2);\r
+ } > bank_F AT>bank_F_lma =0xff\r
\r
\r
/* Start of text section. */\r
.stext :\r
{\r
*(.stext)\r
- } > text AT>bank14_lma\r
+ } > text AT>bank_FIX1_lma\r
.init :\r
{\r
*(.init)\r
- } AT>bank14_lma =0\r
+ } AT>bank_FIX1_lma =0\r
.text :\r
{\r
/* Put startup code at beginning so that _start keeps same address. */\r
_etext = .;\r
PROVIDE (etext = .);\r
. = ALIGN(2);\r
- } > text AT>bank14_lma =0xa7a7a7a7\r
+ } > text AT>bank_FIX1_lma =0xa7a7a7a7\r
\r
.eh_frame :\r
{\r
KEEP (*(.eh_frame))\r
- } > text AT>bank14_lma\r
+ } > text AT>bank_FIX1_lma\r
\r
.gcc_except_table :\r
{\r
*(.gcc_except_table)\r
- } > text AT>bank14_lma\r
+ } > text AT>bank_FIX1_lma\r
\r
.rodata :\r
{\r
*(.rodata.*)\r
*(.gnu.linkonce.r*)\r
. = ALIGN(2);\r
- } > text_h AT>bank15_lma =0xffffffff\r
+ } > text_h AT>bank_FIX2_lma =0xffffffff\r
\r
.rodata1 :\r
{\r
*(.rodata1)\r
. = ALIGN(2);\r
- } > text_h AT>bank15_lma =0xffffffff\r
+ } > text_h AT>bank_FIX2_lma =0xffffffff\r
\r
/* Constructor and destructor tables are in ROM. */\r
/*\r
_edata = .;\r
PROVIDE (edata = .);\r
. = ALIGN(2);\r
- } > data AT>bank15_lma =0xffffffff\r
+ } > data AT>bank_FIX2_lma =0xffffffff\r
__data_section_size = SIZEOF(.data);\r
PROVIDE (__data_section_size = SIZEOF(.data));\r
__data_image_end = __data_image + __data_section_size;\r
*(.dem_eventmemory_pri)\r
} > data\r
\r
+ .noice_port 0x2000 :\r
+ {\r
+ *(.noice_port)\r
+ } > data\r
+ \r
/* SCz: this does not work yet... This is supposed to force the loading\r
of _map_data.o (from libgcc.a) when the .data section is not empty.\r
By doing so, this should bring the code that copies the .data section\r
*(.gnu.linkonce.b.*)\r
*(COMMON)\r
PROVIDE (_end = .);\r
- } > data AT>bank15_lma\r
+ } > data AT>bank_FIX2_lma\r
__bss_size = SIZEOF(.bss);\r
PROVIDE (__bss_size = SIZEOF(.bss));\r
.eeprom :\r
* High: 8x128K\r
*/\r
\r
-#define H7F_REG_BASE 0xFFFF8000\r
+#define H7F_REG_BASE (UINT32)&FLASH\r
#define MAIN_ARRAY_BASE 0x00000000\r
-#define SHADOW_ROW_BASE 0x00FF8000\r
+\r
+#ifdef CFG_MPC5516\r
+#define SHADOW_ROW_BASE 0x00FF8000\r
+#elif defined(CFG_MPC5567)\r
+#define SHADOW_ROW_BASE 0x00FFFC00\r
+#endif\r
+\r
#define SHADOW_ROW_SIZE 0x00008000\r
#define FLASH_PAGE_SIZE H7FB_PAGE_SIZE\r
\r
return _rv; \\r
}\r
\r
+#define FLS_VALIDATE_READ_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\\r
+ int sectorIndex;\\r
+ int addrOk=0;\\r
+ const Fls_SectorType* sector;\\r
+ for (sectorIndex=0; sectorIndex<Fls_Global.config->FlsSectorListSize;sectorIndex++) {\\r
+ sector = &Fls_Global.config->FlsSectorList[sectorIndex];\\r
+ if((((uint32)_addr-sector->FlsSectorStartaddress) / sector->FlsSectorSize)<sector->FlsNumberOfSectors){\\r
+ /* Within the right adress space */\\r
+ addrOk=1;\\r
+ }\\r
+ }\\r
+ if (1!=addrOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_ADDRESS ); \\r
+ return _rv; \\r
+ }\r
+\r
#define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\\r
int i;\\r
int lengthOk=0;\\r
return _rv; \\r
}\r
\r
+#define FLS_VALIDATE_READ_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\\r
+ int i;\\r
+ int lengthOk=0;\\r
+ const Fls_SectorType* sectorPtr= &Fls_Global.config->FlsSectorList[0];\\r
+ for (i=0; i<Fls_Global.config->FlsSectorListSize;i++) {\\r
+ if ((sectorPtr->FlsSectorStartaddress + (sectorPtr->FlsNumberOfSectors * sectorPtr->FlsSectorSize))>=(uint32_t)(_addr+(_length))){\\r
+ lengthOk=1;\\r
+ }\\r
+ sectorPtr++;\\r
+ }\\r
+ if (!lengthOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_LENGTH ); \\r
+ return _rv; \\r
+ }\r
+\r
#define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)\\r
int i;\\r
int lengthOk=0;\\r
#else\r
#define FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(_addr, _api, _rv)\r
#define FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\r
+ #define FLS_VALIDATE_READ_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\r
#define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)\r
#define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\r
+ #define FLS_VALIDATE_READ_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\r
#define FLS_VALIDATE_STATUS_UNINIT_W_RV(_status, _api, _rv)\r
#define FLS_VALIDATE_STATUS_BUSY(_status, _api)\r
#define FLS_VALIDATE_STATUS_BUSY_W_RV(_status, _api, _rv)\r
Fls_Global.jobResultType = MEMIF_JOB_OK;\r
Fls_Global.jobType = FLS_JOB_NONE;\r
Fls_Global.status = MEMIF_IDLE;\r
- FEE_JOB_END_NOTIFICATION();\r
+// FEE_JOB_END_NOTIFICATION();\r
} else if( flashStatus == H7F_BUSY ) {\r
/* Busy, Do nothing */\r
} else {\r
Fls_Global.jobResultType = MEMIF_JOB_OK;\r
Fls_Global.jobType = FLS_JOB_NONE;\r
Fls_Global.status = MEMIF_IDLE;\r
- FEE_JOB_END_NOTIFICATION();\r
+// FEE_JOB_END_NOTIFICATION();\r
} else if( flashStatus == H7F_BUSY ) {\r
/* Busy, Do nothing */\r
} else {\r
{\r
FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_READ_ID, E_NOT_OK);\r
FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_READ_ID, E_NOT_OK);\r
- FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_READ_ID, E_NOT_OK);\r
- FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_READ_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_READ_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_READ_ID, E_NOT_OK);\r
FLS_VALIDATE_PARAM_DATA_W_RV((void*)SourceAddress, FLS_READ_ID, E_NOT_OK)\r
\r
// Always check if status is not busy\r
{\r
FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_COMPARE_ID, E_NOT_OK);\r
FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_COMPARE_ID, E_NOT_OK);\r
- FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_COMPARE_ID, E_NOT_OK);\r
- FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_COMPARE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_READ_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_COMPARE_ID, E_NOT_OK);\r
+ FLS_VALIDATE_READ_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_COMPARE_ID, E_NOT_OK);\r
FLS_VALIDATE_PARAM_DATA_W_RV((void*)SourceAddress,FLS_COMPARE_ID, E_NOT_OK)\r
\r
// Always check if status is not busy\r
return H7F_BUSY;\r
}\r
\r
+EXIT_EHV:\r
/* Clear MCR-PGM bit */\r
H7FMCR_BIT_CLEAR (MCRAddress, H7F_MCR_PGM);\r
\r
// Clear our struct....\r
memset( pInfo,0x0,sizeof(Fls_ProgInfoType) );\r
\r
-EXIT_EHV:\r
return returnCode;\r
}\r
\r
*/\r
void Fls_H7F_SetLock ( Fls_EraseBlockType *blocks, UINT8 logic )\r
{\r
- vuint32_t *reg;\r
+ vuint32_t *reg, *sreg;\r
struct FLASH_tag *flashHw = &FLASH;\r
\r
if( (blocks->lowEnabledBlocks != 0 ) ||\r
(blocks->midEnabledBlocks != 0 ) ||\r
(blocks->shadowBlocks != 0 ) )\r
{\r
- reg = &(flashHw->LMLR.R);\r
+ reg = &(flashHw->LMLR.R);\r
+ sreg = &(flashHw->SLMLR.R);\r
\r
// Check if sector is locked\r
if( !(*reg & 0x80000000 )) {\r
- // Unlock the sector with password\r
- *reg = FLASH_LMLR_PASSWORD;\r
- }\r
+ // Unlock the sector with password\r
+ *reg = FLASH_LMLR_PASSWORD;\r
+ }\r
+ if( !(*sreg & 0x80000000 )) {\r
+ // Unlock the sector with password\r
+ *sreg = FLASH_SLMLR_PASSWORD;\r
+ }\r
\r
// set/clear them\r
if( logic ) {\r
((~blocks->lowEnabledBlocks) & H7F_LML_LLOCK) |\r
((~blocks->shadowBlocks) & H7F_LML_SLOCK) ;\r
}\r
+ if( logic ) {\r
+ *sreg |= ((blocks->midEnabledBlocks<<16)& H7F_LML_MLOCK) +\r
+ (blocks->lowEnabledBlocks & H7F_LML_LLOCK) +\r
+ (blocks->shadowBlocks & H7F_LML_SLOCK);\r
+ } else {\r
+ *sreg &= ((~blocks->midEnabledBlocks<<16) & H7F_LML_MLOCK) |\r
+ ((~blocks->lowEnabledBlocks) & H7F_LML_LLOCK) |\r
+ ((~blocks->shadowBlocks) & H7F_LML_SLOCK) ;\r
+ }\r
}\r
#if 0\r
else {\r
* Copyright (C) 2009 ArcCore AB <contact@arccore.com> \r
*/\r
\r
+#include "Calibration_Settings.h"\r
/* Undef sections/keywords */ \r
#undef PPC\r
\r
OUTPUT_ARCH(powerpc)\r
ENTRY(_start)\r
\r
-\r
-\r
MEMORY\r
{\r
#include "memory.ldf"\r
}\r
-\r
SECTIONS\r
{\r
.rcw : { *(.rcw) }> rcw\r
-\r
+#if defined(USE_FEE)\r
+#include "Fee_Memory_Cfg.h"\r
+ .fee_bank1 FEE_BANK1_OFFSET : {\r
+ . = . + FEE_BANK1_LENGTH;\r
+ }\r
+ .fee_bank2 FEE_BANK2_OFFSET : {\r
+ . = . + FEE_BANK2_LENGTH;\r
+ }\r
+#endif\r
.text :\r
{\r
*(.text .text.* .init .fini* .eini* .gnu.linkonce* .gnu.warning);\r
. = . + ALIGN(8);\r
__DATA_ROM = .;\r
} > flash\r
-\r
+#ifdef CALIBRATION_ACTIVE\r
+ .calibration : AT(ORIGIN(flash_calibration_area_0)) {\r
+ __CALIB_RAM_START = .;\r
+ *(.calibration)\r
+ __CALIB_RAM_END = .;\r
+ } > ram\r
+ __CALIB_ROM_START = ORIGIN(flash_calibration_area_0);\r
+#endif\r
.data : AT(ALIGN(LOADADDR(.sbss2)+SIZEOF(.sbss2),4)) {\r
__DATA_RAM = .; *(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
- } > ram\r
+ } > ram\r
\r
.sdata : AT(ALIGN(LOADADDR(.data)+SIZEOF(.data),4)) {\r
__SDATA_START__ = .;\r
obj-$(CFG_PPC) += crt0.o\r
-obj-$(CFG_HCS12D) += crt0.o\r
-vpath-$(CFG_ARM_CM3) += $(ARCH_PATH-y)kernel\r
+obj-$(CFG_HC1X) += crt0.o\r
+vpath-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32F10x_StdPeriph_Driver/src\r
+vpath-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32_ETH_Driver/src\r
+inc-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32F10x_StdPeriph_Driver/inc\r
+inc-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32_ETH_Driver/inc\r
obj-$(CFG_ARM_CM3) += core_cm3.o\r
obj-$(CFG_ARM_CM3) += startup_stm32f10x.o\r
+#stm32 lib files needed by drivers\r
+obj-$(CFG_ARM_CM3) += stm32f10x_rcc.o\r
+obj-$(CFG_ARM_CM3)-$(USE_CAN) += stm32f10x_can.o\r
+obj-$(CFG_ARM_CM3)-$(USE_DIO) += stm32f10x_gpio.o\r
+obj-$(CFG_ARM_CM3)-$(USE_ADC) += stm32f10x_adc.o\r
+obj-$(CFG_ARM_CM3)-$(USE_ADC) += stm32f10x_dma.o\r
+obj-$(CFG_ARM_CM3)-$(USE_FLS) += stm32f10x_flash.o\r
+obj-$(CFG_ARM_CM3)-$(USE_PWM) += stm32f10x_tim.o\r
+obj-$(CFG_ARM_CM3)-$(USE_LWIP) += stm32_eth.o\r
+\r
obj-$(USE_TTY_TMS570_KEIL) += GLCD.o\r
obj-$(USE_TTY_TMS570_KEIL) += emif.o\r
\r
endif\r
\r
#Ecu\r
-#obj-y += EcuM_$(BOARDDIR).o\r
obj-$(USE_ECUM) += EcuM.o\r
+obj-$(USE_ECUM) += EcuM_Main.o\r
obj-$(USE_ECUM) += EcuM_Cfg.o\r
obj-$(USE_ECUM) += EcuM_Callout_template.o\r
inc-$(USE_ECUM) += $(ROOTDIR)/system/EcuM\r
inc-$(USE_TCF) += $(ROOTDIR)/common/tcf\r
vpath-$(USE_TCF) += $(ROOTDIR)/common/tcf\r
\r
+#SLEEP\r
+obj-$(USE_SLEEP) += sleep.o\r
+\r
+\r
# Newlib overrides (overridden by default)\r
ifneq ($(CFG_STANDARD_NEWLIB),y)\r
obj-y += xtoa.o\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-// This file is just examples of implementation for the stubs needed by\r
-// the EcuM. Every application should use an own version of this\r
-// file to implement the setup and tear down of the system.\r
-\r
-\r
+/*
+* Configuration of module EcuM (EcuM_Callout_template.c)
+*
+* Created by:
+* Configured for (MCU): MPC5567
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue May 25 11:41:52 CEST 2010
+*/
+
+\r
+#warning "This default file may only be used as an example!"
+
#include "EcuM.h"\r
#include "Det.h"\r
#if defined(USE_DEM)\r
#endif\r
#if defined(USE_IOHWAB)\r
#include "IoHwAb.h"\r
-#endif\r
-#if defined(USE_COMM)\r
-#include "ComM.h"\r
-#endif\r
-#if defined(USE_NM)\r
-#include "Nm.h"\r
-#endif\r
-#if defined(USE_CANNM)\r
-#include "CanNm.h"\r
-#endif\r
-#if defined(USE_CANSM)\r
-#include "CanSM.h"\r
-#endif\r
-#if defined(USE_LINSM)\r
-#include "LinSM.h"\r
-#endif\r
-\r
-\r
+#endif
+#if defined(USE_FLS)
+#include "Fls.h"
+#endif
+#if defined(USE_EEP)
+#include "Eep.h"
+#endif
+#if defined(USE_FEE)
+#include "Fee.h"
+#endif\r
+#if defined(USE_EA)
+#include "Ea.h"
+#endif
+#if defined(USE_NVM)
+#include "NvM.h"
+#endif
\r
void EcuM_AL_DriverInitZero()\r
{\r
\r
#if defined(USE_FLS)\r
// Setup Flash\r
- FlashInit(ConfigPtr->FlashConfig);\r
-#endif\r
-\r
- // Setup NVRAM Manaager\r
- // TODO\r
-\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+#if defined(USE_FEE)
+ // Setup FEE
+ Fee_Init();
+#endif
+
+#if defined(USE_EA)
+ // Setup EA
+ Ea_init();
+#endif
+
+#if defined(USE_NVM)
+ // Setup NVRAM Manager and start the read all job
+ NvM_Init();
+ NvM_ReadAll();
+#endif
+
// Setup CAN tranceiver\r
// TODO\r
\r
#if defined(USE_CANTP)\r
// Setup CAN TP\r
CanTp_Init();\r
-#endif\r
-\r
-#if defined(USE_CANSM)\r
- CanSM_Init(ConfigPtr->CanSMConfig);\r
-#endif\r
+#endif
\r
// Setup LIN\r
// TODO\r
PduR_Init(ConfigPtr->PduRConfig);\r
#endif\r
\r
-#if defined(USE_CANNM)\r
- // Setup Can Network Manager\r
- CanNm_Init(ConfigPtr->CanNmConfig);\r
-#endif\r
-\r
-#if defined(USE_NM)\r
- // Setup Network Management Interface\r
- Nm_Init(ConfigPtr->NmConfig);\r
-#endif\r
-\r
#if defined(USE_COM)\r
// Setup COM layer\r
Com_Init(ConfigPtr->ComConfig);\r
// Setup IO hardware abstraction layer\r
IoHwAb_Init();\r
#endif\r
+\r
}\r
\r
-void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType ConfigPtr)\r
{\r
#if defined(USE_DEM)\r
// Setup DEM\r
Dem_Init();\r
#endif\r
\r
- // Setup FIM\r
-\r
-#if defined(USE_COMM)\r
- // Setup Communication Manager\r
- ComM_Init(ConfigPtr->ComMConfig);\r
+#if defined(USE_CANIF)\r
+ // Startup the CAN interafce; due to the missing COM manager\r
+ //CanIf_InitController(CAN_CTRL_A, 0);\r
+ //CanIf_SetControllerMode(CAN_CTRL_A, CANIF_CS_STARTED);\r
#endif\r
}\r
+
+void EcuM_OnEnterRUN(void)
+{
+
+}
+
+void EcuM_OnExitRun(void)
+{
+
+}
+
+void EcuM_OnExitPostRun(void)
+{
+
+}
+
+void EcuM_OnPrepShutdown(void)
+{
+
+}
+
+void EcuM_OnGoSleep(void)
+{
+
+}
+
+void EcuM_OnGoOffOne(void)
+{
+
+}
+
+void EcuM_OnGoOffTwo(void)
+{
+
+}
+
+void EcuM_AL_SwitchOff(void)
+{
+
+}
--- /dev/null
+/*
+* Configuration of module EcuM (EcuM_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): MPC5567
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue May 25 11:41:52 CEST 2010
+*/
+
+\r
+\r
+#warning "This default file may only be used as an example!"
+
+#include "EcuM.h"\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultShutdownMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = 10000,
+ .EcuMNvramWriteAllTimeout = 10000,
+ .EcuMRunSelfRequestPeriod = 10000,
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)
+ .FlashConfig = FlsConfigSet,
+#endif
+
+};\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Thu Oct 14 15:29:52 CEST 2010\r
+ */\r
+\r
+
+#warning "This default file may only be used as an example!"\r
+\r
+#if (ECUM_SW_MAJOR_VERSION != 1)
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD 200\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/*
+* Configuration of module EcuM (EcuM_Generated_Types.h)
+*
+* Created by:
+* Configured for (MCU): MPC5567
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue May 25 11:41:52 CEST 2010
+*/
+
+
+#warning "This default file may only be used as an example!"
+
+#if (ECUM_SW_MAJOR_VERSION != 1)
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_FLS)
+#include "Fls.h"
+#endif
+\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultShutdownMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunSelfRequestPeriod;
+ uint32 EcuMNvramReadAllTimeout;
+ uint32 EcuMNvramWriteAllTimeout;
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)
+ const Fls_ConfigType* FlashConfig;
+#endif
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
# System + Communication + Diagnostic
MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE
# Additional
-MOD_AVAIL+=RAMLOG
+MOD_AVAIL+=RAMLOG
# Needed by us (These become USE_XXX=y and def-y += USE_XXX )
{\r
ADC_CONV_MODE_DISABLED,\r
ADC_CONV_MODE_ONESHOT = 1,\r
- ADC_CONV_MODE_CONTINOUS = 9,\r
+ ADC_CONV_MODE_CONTINUOUS = 9,\r
} Adc_GroupConvModeType;\r
\r
typedef struct\r
* the detection of all development errors\r
*/\r
/** Enable Development Error Trace */\r
-#define PWM_DEV_EROR_DETECT STD_ON\r
+#define PWM_DEV_ERROR_DETECT STD_ON\r
/** Build GetOutputState()\r
* Note: Not supported since pwm module doesn't support reading output.\r
*/\r
vectors (rx) : ORIGIN = 0xff80, LENGTH = 0x80\r
\r
/* Flash memory banks VMA:s */\r
-bank8 (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
-bank9 (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
-bank10 (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
-bank11 (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
-bank12 (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
-bank13 (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+bank_A (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+bank_B (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+bank_C (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+bank_D (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+bank_E (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+bank_F (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
\r
-bank14 (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
-bank15 (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
+bank_FIX1 (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+bank_FIX2 (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
\r
/* Flash memory banks LMA:s */\r
/* iSystem winIDEA */\r
-bank8_lma (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
-bank9_lma (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
-bank10_lma (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
-bank11_lma (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
-bank12_lma (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
-bank13_lma (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+bank_A_lma (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+bank_B_lma (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+bank_C_lma (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+bank_D_lma (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+bank_E_lma (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+bank_F_lma (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
\r
-bank14_lma (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
-bank15_lma (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
+bank_FIX1_lma (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+bank_FIX2_lma (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
vectors_lma (rx) : ORIGIN = 0x10ff80, LENGTH = 0x80\r
\r
/* Freescale Codewarrior Hiwave (s19, TBDML)\r
-bank8_lma (rx) : ORIGIN = 0x388000, LENGTH = 16k\r
-bank9_lma (rx) : ORIGIN = 0x398000, LENGTH = 16k\r
-bank10_lma (rx) : ORIGIN = 0x3a8000, LENGTH = 16k\r
-bank11_lma (rx) : ORIGIN = 0x3b8000, LENGTH = 16k\r
-bank12_lma (rx) : ORIGIN = 0x3c8000, LENGTH = 16k\r
-bank13_lma (rx) : ORIGIN = 0x3d8000, LENGTH = 16k\r
+bank_A_lma (rx) : ORIGIN = 0x388000, LENGTH = 16k\r
+bank_B_lma (rx) : ORIGIN = 0x398000, LENGTH = 16k\r
+bank_C_lma (rx) : ORIGIN = 0x3a8000, LENGTH = 16k\r
+bank_D_lma (rx) : ORIGIN = 0x3b8000, LENGTH = 16k\r
+bank_E_lma (rx) : ORIGIN = 0x3c8000, LENGTH = 16k\r
+bank_F_lma (rx) : ORIGIN = 0x3d8000, LENGTH = 16k\r
\r
-bank14_lma (rx) : ORIGIN = 0x3e8000, LENGTH = 16k\r
-bank15_lma (rx) : ORIGIN = 0x3f8002, LENGTH = 16k-0x102\r
+bank_FIX1_lma (rx) : ORIGIN = 0x3e8000, LENGTH = 16k\r
+bank_FIX2_lma (rx) : ORIGIN = 0x3f8002, LENGTH = 16k-0x102\r
vectors_lma (rx) : ORIGIN = 0x3fff80, LENGTH = 0x80\r
-*/
\ No newline at end of file
+*/\r
--- /dev/null
+\r
+Elmicro T-board HC12X Controller Module with MC9SX12DP512\r
+\r
+http://elmicro.com/en/hcs12tb.html#s12x\r
+\r
+MC9SX12DP512 Microcontroller Info:\r
+ MC9SX12DP512 MCU with LQFP112 package\r
+ 512 KB Flash\r
+ 4 KB EEPROM\r
+ 14 KB RAM\r
+ 3x SPI\r
+ 2x SCI\r
+ 5x CAN\r
+ Enhanced Capture Timer\r
+ 8 Channel PWM\r
+ 16 Channel 10 Bit A/D-Converter\r
+ \r
+ \r
+Board Features:\r
+ 16 MHz Quarz Clock (8 MHz System Clock)\r
+ Two RS232 Ports with Transceiver MAX232A\r
+ PCA82C251 CAN Physical Interface\r
+ Special Reset Controller\r
+ Reset Switch\r
+ LED, DIP and Potentiomer I/O\r
+ Operating Mode selectable via jumpers\r
+ BDM (Background Debug Mode) connector\r
+ All controller pins are available at two double row headers\r
+ 5V power supply\r
+ Credit card size: 86mm x 54mm\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=hcs12d\r
+ARCH_FAM=hc1x\r
+ARCH_MCU=MC912DG128A\r
+\r
+# CFG (y/n) macros (These become CFG_XXX=y and def-y += CFG_XXX ) \r
+CFG=HC1X HCS12XD MC912XDP512 BRD_HCS12X_ELMICRO_TBOARD SIMULATOR\r
+\r
+# What buildable modules does this board have, \r
+# default or private (These become MOD_XXX=y )\r
+MOD_AVAIL+=KERNEL MCU GPT DIO PORT COM CAN CANIF PWM ADC DEM DCM PDUR COMM NM CANNM CANSM CANTP RTE IOHWAB DET ECUM RAMLOG\r
+\r
+# Needed by us (These become USE_XXX=y and def-y += USE_XXX )\r
+MOD_USE=KERNEL MCU\r
--- /dev/null
+/*\r
+ * Configuration of module Adc (Adc_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 10:10:57 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Adc.h"\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+void Adc_ATDCallback (void);\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration[] =\r
+{\r
+ {\r
+ .convTime = ADC_CONVERSION_TIME_4_CLOCKS,\r
+ .resolution = ADC_RESOLUTION_10_BIT,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ },\r
+};\r
+const Adc_ChannelType Adc_ATDGroupChannelList[ADC_NBR_OF_ATDGROUP_CHANNELS] =\r
+{\r
+ ADC_CH2,\r
+};\r
+\r
+Adc_ValueGroupType Adc_ATDGroupBuffer [sizeof(Adc_ATDGroupChannelList)/sizeof(Adc_ATDGroupChannelList[0])];\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ {\r
+ .conversionMode = ADC_CONV_MODE_CONTINUOUS,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ .groupCallback = Adc_ATDCallback,\r
+ .channelList = Adc_ATDGroupChannelList,\r
+ .resultBuffer = Adc_ATDGroupBuffer, \r
+ .numberOfChannels = sizeof(Adc_ATDGroupChannelList)/sizeof(Adc_ATDGroupChannelList[0]),\r
+ .status = &AdcGroupStatus[0], \r
+ },\r
+};\r
+\r
+const Adc_ConfigType AdcConfig[] =\r
+{\r
+ {\r
+ .hwConfigPtr = AdcHWUnitConfiguration,\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ }\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Adc (Adc_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 10:10:57 CET 2010\r
+ */\r
+\r
+
+#if (ADC_SW_MAJOR_VERSION != 1)
+#error "Adc: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define ADC_DEINIT_API STD_OFF\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_OFF\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_NONE\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_NOF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_4_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_16_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+\r
+typedef enum\r
+{\r
+ ADC_RESOLUTION_10_BIT,\r
+ ADC_RESOLUTION_8_BIT,\r
+}Adc_ResolutionType;\r
+\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINUOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+typedef struct\r
+{\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ void (*groupCallback)(void);\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+} Adc_GroupDefType;\r
+\r
+#define ADC_NBR_OF_ATDGROUP_CHANNELS 1 \r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0, \r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType convTime;\r
+ Adc_ResolutionType resolution;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig[];\r
+\r
+#endif /* ADC_CFG_H_ */\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+
+#if (CAN_SW_MAJOR_VERSION != 1)
+#error "Can: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_ON\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF // Not supported\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+typedef enum {\r
+ CAN_CTRL_0 = 0,\r
+ CAN_CTRL_1 = 1,\r
+ CAN_CTRL_2 = 2,\r
+ CAN_CTRL_3 = 3,\r
+ CAN_CTRL_4 = 4,\r
+ CAN_CONTROLLER_CNT = 5\r
+}CanControllerIdType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ TxBox,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ RxBox,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+typedef struct\r
+{\r
+ uint8 idmr[8]; // Identifier Mask Register, 1 = ignore corresponding acceptance code register bit\r
+ uint8 idar[8]; // Identifier Acceptance Register\r
+ Can_Arc_IDAMType idam;\r
+} Can_FilterMaskType;\r
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
+\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_CAN0_Mask_1 = {\r
+ {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF},\r
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0},\r
+ CAN_ARC_IDAM_2_32BIT\r
+};\r
+\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CAN0[] = {\r
+ {\r
+ .CanObjectId = RxBox,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_CAN0_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = TxBox,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_CAN0_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_0,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CAN0[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 15 12:06:55 CET 2010\r
+ */\r
+\r
+
+#if (DIO_SW_MAJOR_VERSION != 1)
+#error "Dio: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define DIO_VERSION_INFO_API STD_OFF\r
+#define DIO_DEV_ERROR_DETECT STD_OFF\r
+\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ DIO_PORT_A = 0,\r
+ DIO_PORT_E = 1,\r
+ DIO_PORT_B = 2,\r
+ DIO_PORT_H = 3,\r
+ DIO_PORT_J = 4,\r
+ DIO_PORT_K = 5,\r
+ DIO_PORT_M = 6,\r
+ DIO_PORT_P = 7,\r
+ DIO_PORT_S = 8,\r
+ DIO_PORT_T = 9,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_DI_PH0 24\r
+#define DIO_CHANNEL_NAME_DI_PH1 25\r
+#define DIO_CHANNEL_NAME_DI_PH2 26\r
+#define DIO_CHANNEL_NAME_DI_PH3 27\r
+#define DIO_CHANNEL_NAME_DI_PH4 28\r
+#define DIO_CHANNEL_NAME_DI_PH5 29\r
+#define DIO_CHANNEL_NAME_DI_PH6 30\r
+#define DIO_CHANNEL_NAME_DI_PH7 31\r
+#define DIO_CHANNEL_NAME_DO_PB0 16\r
+#define DIO_CHANNEL_NAME_DO_PB1 17\r
+#define DIO_CHANNEL_NAME_DO_PB2 18\r
+#define DIO_CHANNEL_NAME_DO_PB3 19\r
+#define DIO_CHANNEL_NAME_DO_PB4 20\r
+#define DIO_CHANNEL_NAME_DO_PB5 21\r
+#define DIO_CHANNEL_NAME_DO_PB6 22\r
+#define DIO_CHANNEL_NAME_DO_PB7 23\r
+#define DIO_CHANNEL_NAME_DI_PT0 72\r
+#define DIO_CHANNEL_NAME_DI_PT1 73\r
+#define DIO_CHANNEL_NAME_DO_PT2 74\r
+\r
+// Channel group\r
+#define DIO_GROUP_NAME_DI_DIP (&DioConfigData[0])\r
+#define DIO_GROUP_NAME_DO_LEDBAR (&DioConfigData[1])\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_DipSwitch (DIO_PORT_H)\r
+#define DIO_PORT_NAME_LEDBar (DIO_PORT_B)\r
+#define DIO_PORT_NAME_Timer (DIO_PORT_T)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 15 12:06:55 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_DI_PH0,\r
+ DIO_CHANNEL_NAME_DI_PH1,\r
+ DIO_CHANNEL_NAME_DI_PH2,\r
+ DIO_CHANNEL_NAME_DI_PH3,\r
+ DIO_CHANNEL_NAME_DI_PH4,\r
+ DIO_CHANNEL_NAME_DI_PH5,\r
+ DIO_CHANNEL_NAME_DI_PH6,\r
+ DIO_CHANNEL_NAME_DI_PH7,\r
+ DIO_CHANNEL_NAME_DO_PB0,\r
+ DIO_CHANNEL_NAME_DO_PB1,\r
+ DIO_CHANNEL_NAME_DO_PB2,\r
+ DIO_CHANNEL_NAME_DO_PB3,\r
+ DIO_CHANNEL_NAME_DO_PB4,\r
+ DIO_CHANNEL_NAME_DO_PB5,\r
+ DIO_CHANNEL_NAME_DO_PB6,\r
+ DIO_CHANNEL_NAME_DO_PB7,\r
+ DIO_CHANNEL_NAME_DI_PT0,\r
+ DIO_CHANNEL_NAME_DI_PT1,\r
+ DIO_CHANNEL_NAME_DO_PT2,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_DipSwitch, \r
+ DIO_PORT_NAME_LEDBar, \r
+ DIO_PORT_NAME_Timer, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = { \r
+ { \r
+ .port = DIO_PORT_NAME_DipSwitch,\r
+ .mask = 255, \r
+ .offset = 0, \r
+ }, \r
+ { \r
+ .port = DIO_PORT_NAME_LEDBar,\r
+ .mask = 255, \r
+ .offset = 0, \r
+ }, \r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = DIO_END_OF_LIST, \r
+ .mask = DIO_END_OF_LIST, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+/*\r
+ * Configuration of module Gpt (Gpt_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Gpt (Gpt_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+
+#if (GPT_SW_MAJOR_VERSION != 1)
+#error "Gpt: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Std_Types.h"\r
+\r
+\r
+#define GPT_VARIANT_PC STD_OFF\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+/** HW PIT channels */\r
+#define GPT_CHANNEL_RTI 0\r
+#define GPT_CHANNEL_0 0\r
+#define GPT_CHANNEL_1 1\r
+#define GPT_CHANNEL_2 2\r
+#define GPT_CHANNEL_3 3\r
+#define GPT_CHANNEL_4 4\r
+#define GPT_CHANNEL_5 5\r
+#define GPT_CHANNEL_6 6\r
+#define GPT_CHANNEL_7 7\r
+\r
+#define GPT_CHANNEL_CNT 8\r
+\r
+#if defined(CFG_MPC55XX)\r
+#define GPT_CHANNEL_DEC 9\r
+#endif\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+\r
+#define GPT_DEV_ERROR_DETECT STD_OFF\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+#define GPT_DEINIT_API STD_OFF\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_OFF\r
+#define GPT_TIME_REMAINING_API STD_OFF\r
+#define GPT_TIME_ELAPSED_API STD_OFF\r
+#define GPT_VERSION_INFO_API STD_OFF\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+typedef struct {\r
+ uint32 GptChannelClkSrc;\r
+ Gpt_ChannelType GptChannelId;\r
+ Gpt_ChannelMode GptChannelMode;\r
+ void (*GptNotification)();\r
+ uint32 GptChannelPrescale;\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 1,\r
+ .Pll2 = 2,\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+
+#if (MCU_SW_MAJOR_VERSION != 2)
+#error "Mcu: Configuration file version differs from BSW version."
+#endif
+\r
+#warning "This default file may only be used as an example!"
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON \r
+#define MCU_PERFORM_RESET_API STD_OFF\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_Clock = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Port.h"\r
+\r
+#define PORT_UNDEFINED 0x00\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .corePullUpRegister = 0x90,\r
+ .coreReducedDriveRegister = 0x00,\r
+ .modeRoutingRegister = 0x00,\r
+\r
+ #if ( PORTA_CONFIGURABLE == STD_ON )\r
+ .portADirection = PORT_UNDEFINED,\r
+ .portAOutValue = PORT_UNDEFINED,\r
+ .portAMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTB_CONFIGURABLE == STD_ON )\r
+ .portBDirection = 0xFF,\r
+ .portBOutValue = PORT_UNDEFINED,\r
+ .portBMask = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTE_CONFIGURABLE == STD_ON )\r
+ .portEDirection = PORT_UNDEFINED,\r
+ .portEOutValue = PORT_UNDEFINED,\r
+ .portEMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTK_CONFIGURABLE == STD_ON )\r
+ .portKDirection = PORT_UNDEFINED,\r
+ .portKOutValue = PORT_UNDEFINED,\r
+ .portKMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTH_CONFIGURABLE == STD_ON )\r
+ .portHDirection = 0x0,\r
+ .portHOutValue = 0x0,\r
+ .portHMask = 0x0,\r
+ .portHPullEnableRegister = 0xFF,\r
+ .portHPullPolarityRegsiter = 0x0,\r
+ .portHReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ .portJDirection = 0x80,\r
+ .portJOutValue = 0xC0,\r
+ .portJMask = 0x40,\r
+ .portJPullEnableRegister = 0x0,\r
+ .portJPullPolarityRegsiter 0x0,\r
+ .portJReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTM_CONFIGURABLE == STD_ON )\r
+ .portMDirection = 0x0,\r
+ .portMOutValue = 0xC3,\r
+ .portMMask = 0x0,\r
+ .portMPullEnableRegister = 0x0,\r
+ .portMPullPolarityRegsiter = 0x0,\r
+ .portMWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portMReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTP_CONFIGURABLE == STD_ON )\r
+ .portPDirection = PORT_UNDEFINED,\r
+ .portPOutValue = PORT_UNDEFINED,\r
+ .portPMask = PORT_UNDEFINED,\r
+ .portPPullEnableRegister = PORT_UNDEFINED,\r
+ .portPPullPolarityRegsiter = PORT_UNDEFINED,\r
+ .portPReducedDriveRegister = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTS_CONFIGURABLE == STD_ON )\r
+ .portSDirection = 0x0,\r
+ .portSOutValue = 0xF,\r
+ .portSMask = 0x0,\r
+ .portSPullEnableRegister = 0x5,\r
+ .portSPullPolarityRegsiter = 0x0,\r
+ .portSWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portSReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTT_CONFIGURABLE == STD_ON )\r
+ .portTDirection = 0x4,\r
+ .portTOutValue = 0x3,\r
+ .portTMask = 0x0,\r
+ .portTPullEnableRegister = 0x0,\r
+ .portTPullPolarityRegsiter = 0x0,\r
+ .portTReducedDriveRegister = 0x0,\r
+ #endif\r
+};\r
+\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+
+#if (PORT_SW_MAJOR_VERSION != 1)
+#error "Port: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+\r
+/** Parameter to enable/disable configuration on a port */\r
+#define PORTA_CONFIGURABLE STD_OFF\r
+#define PORTB_CONFIGURABLE STD_ON\r
+#define PORTE_CONFIGURABLE STD_OFF\r
+#define PORTK_CONFIGURABLE STD_OFF\r
+#define PORTH_CONFIGURABLE STD_ON\r
+#define PORTJ_CONFIGURABLE STD_ON\r
+#define PORTM_CONFIGURABLE STD_ON\r
+#define PORTP_CONFIGURABLE STD_OFF\r
+#define PORTS_CONFIGURABLE STD_ON\r
+#define PORTT_CONFIGURABLE STD_ON\r
+\r
+#define PORT_A_BASE 0x0100\r
+#define PORT_B_BASE 0x0200\r
+#define PORT_E_BASE 0x0300\r
+#define PORT_K_BASE 0x0400\r
+#define PORT_H_BASE 0x0500\r
+#define PORT_J_BASE 0x0600\r
+#define PORT_M_BASE 0x0700\r
+#define PORT_P_BASE 0x0800\r
+#define PORT_S_BASE 0x0900\r
+#define PORT_T_BASE 0x0A00\r
+#define PORT_BITMASK 0x00FF\r
+#define PORT_BASEMASK 0xFF00;\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum\r
+{\r
+ PORT_PA0 = PORT_A_BASE,\r
+ PORT_PA1,\r
+ PORT_PA2,\r
+ PORT_PA3,\r
+ PORT_PA4,\r
+ PORT_PA5,\r
+ PORT_PA6,\r
+ PORT_PA7,\r
+ PORT_PB0 = PORT_B_BASE,\r
+ PORT_PB1,\r
+ PORT_PB2,\r
+ PORT_PB3,\r
+ PORT_PB4,\r
+ PORT_PB5,\r
+ PORT_PB6,\r
+ PORT_PB7,\r
+ PORT_PE0 = PORT_E_BASE,\r
+ PORT_PE1,\r
+ PORT_PE2,\r
+ PORT_PE3,\r
+ PORT_PE4,\r
+ PORT_PE5,\r
+ PORT_PE6,\r
+ PORT_PE7,\r
+ PORT_PH0 = PORT_H_BASE,\r
+ PORT_PH1,\r
+ PORT_PH2,\r
+ PORT_PH3,\r
+ PORT_PH4,\r
+ PORT_PH5,\r
+ PORT_PH6,\r
+ PORT_PH7,\r
+ PORT_PJ0 = PORT_J_BASE,\r
+ PORT_PJ1,\r
+ PORT_PJ2,\r
+ PORT_PJ3,\r
+ PORT_PJ4,\r
+ PORT_PJ5,\r
+ PORT_PJ6,\r
+ PORT_PJ7,\r
+ PORT_PK0 = PORT_K_BASE,\r
+ PORT_PK1,\r
+ PORT_PK2,\r
+ PORT_PK3,\r
+ PORT_PK4,\r
+ PORT_PK5,\r
+ PORT_PK6,\r
+ PORT_PK7,\r
+ PORT_PM0 = PORT_M_BASE,\r
+ PORT_PM1,\r
+ PORT_PM2,\r
+ PORT_PM3,\r
+ PORT_PM4,\r
+ PORT_PM5,\r
+ PORT_PM6,\r
+ PORT_PM7,\r
+ PORT_PP0 = PORT_P_BASE,\r
+ PORT_PP1,\r
+ PORT_PP2,\r
+ PORT_PP3,\r
+ PORT_PP4,\r
+ PORT_PP5,\r
+ PORT_PP6,\r
+ PORT_PP7,\r
+ PORT_PS0 = PORT_S_BASE,\r
+ PORT_PS1,\r
+ PORT_PS2,\r
+ PORT_PS3,\r
+ PORT_PS4,\r
+ PORT_PS5,\r
+ PORT_PS6,\r
+ PORT_PS7,\r
+ PORT_PT0 = PORT_T_BASE,\r
+ PORT_PT1,\r
+ PORT_PT2,\r
+ PORT_PT3,\r
+ PORT_PT4,\r
+ PORT_PT5,\r
+ PORT_PT6,\r
+ PORT_PT7,\r
+} Port_PinType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct\r
+{\r
+ const uint8_t corePullUpRegister; // PUCR\r
+ const uint8_t coreReducedDriveRegister; // RDRIV\r
+ const uint8_t modeRoutingRegister; // MODRR\r
+\r
+ /**\r
+ * Every port has:\r
+ * a direction (input or output)\r
+ * a default out value\r
+ * a mask that is 0 if the direction is allowed to change during runtime\r
+ *\r
+ * Some ports have:\r
+ * a reduced drive conf (power saving)\r
+ * a pull enable conf (enable pull-up/pull-down\r
+ * a pull direction conf (pull-up or pull-down)\r
+ * a wired mode (enable open drain outputs)\r
+ */\r
+#if ( PORTA_CONFIGURABLE == STD_ON )\r
+ const uint8_t portADirection;\r
+ const uint8_t portAOutValue;\r
+ const uint8_t portAMask;\r
+#endif\r
+\r
+#if ( PORTB_CONFIGURABLE == STD_ON )\r
+ const uint8_t portBDirection;\r
+ const uint8_t portBOutValue;\r
+ const uint8_t portBMask;\r
+#endif\r
+\r
+#if ( PORTE_CONFIGURABLE == STD_ON )\r
+ const uint8_t portEDirection;\r
+ const uint8_t portEOutValue;\r
+ const uint8_t portEMask;\r
+#endif\r
+\r
+#if ( PORTK_CONFIGURABLE == STD_ON )\r
+ const uint8_t portKDirection;\r
+ const uint8_t portKOutValue;\r
+ const uint8_t portKMask;\r
+#endif\r
+\r
+#if ( PORTH_CONFIGURABLE == STD_ON )\r
+ const uint8_t portHDirection;\r
+ const uint8_t portHOutValue;\r
+ const uint8_t portHMask;\r
+ const uint8_t portHPullEnableRegister;\r
+ const uint8_t portHPullPolarityRegsiter;\r
+ const uint8_t portHReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ const uint8_t portJDirection;\r
+ const uint8_t portJOutValue;\r
+ const uint8_t portJMask;\r
+ const uint8_t portJPullEnableRegister;\r
+ const uint8_t portJPullPolarityRegsiter;\r
+ const uint8_t portJReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTM_CONFIGURABLE == STD_ON )\r
+ const uint8_t portMDirection;\r
+ const uint8_t portMOutValue;\r
+ const uint8_t portMMask;\r
+ const uint8_t portMPullEnableRegister;\r
+ const uint8_t portMPullPolarityRegsiter;\r
+ const uint8_t portMWiredModeRegsiter;\r
+ const uint8_t portMReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTP_CONFIGURABLE == STD_ON )\r
+ const uint8_t portPDirection;\r
+ const uint8_t portPOutValue;\r
+ const uint8_t portPMask;\r
+ const uint8_t portPPullEnableRegister;\r
+ const uint8_t portPPullPolarityRegsiter;\r
+ const uint8_t portPReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTS_CONFIGURABLE == STD_ON )\r
+ const uint8_t portSDirection;\r
+ const uint8_t portSOutValue;\r
+ const uint8_t portSMask;\r
+ const uint8_t portSPullEnableRegister;\r
+ const uint8_t portSPullPolarityRegsiter;\r
+ const uint8_t portSWiredModeRegsiter;\r
+ const uint8_t portSReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTT_CONFIGURABLE == STD_ON )\r
+ const uint8_t portTDirection;\r
+ const uint8_t portTOutValue;\r
+ const uint8_t portTMask;\r
+ const uint8_t portTPullEnableRegister;\r
+ const uint8_t portTPullPolarityRegsiter;\r
+ const uint8_t portTReducedDriveRegister;\r
+#endif\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_SDA PORT_PJ6 \r
+#define PORT_PIN_NAME_SCL PORT_PJ7 \r
+#define PORT_PIN_NAME_TXD PORT_PM1 \r
+#define PORT_PIN_NAME_RXD PORT_PM0 \r
+#define PORT_PIN_NAME_PB0 PORT_PB0 \r
+#define PORT_PIN_NAME_PB1 PORT_PB1 \r
+#define PORT_PIN_NAME_PB2 PORT_PB2 \r
+#define PORT_PIN_NAME_PB3 PORT_PB3 \r
+#define PORT_PIN_NAME_PB4 PORT_PB4 \r
+#define PORT_PIN_NAME_PB5 PORT_PB5 \r
+#define PORT_PIN_NAME_PB6 PORT_PB6 \r
+#define PORT_PIN_NAME_PB7 PORT_PB7 \r
+#define PORT_PIN_NAME_PH0 PORT_PH0 \r
+#define PORT_PIN_NAME_PH1 PORT_PH1 \r
+#define PORT_PIN_NAME_PH2 PORT_PH2 \r
+#define PORT_PIN_NAME_PH3 PORT_PH3 \r
+#define PORT_PIN_NAME_PH4 PORT_PH4 \r
+#define PORT_PIN_NAME_PH5 PORT_PH5 \r
+#define PORT_PIN_NAME_PH6 PORT_PH6 \r
+#define PORT_PIN_NAME_PH7 PORT_PH7 \r
+#define PORT_PIN_NAME_PT0 PORT_PT0 \r
+#define PORT_PIN_NAME_PT1 PORT_PT1 \r
+#define PORT_PIN_NAME_BEEPER PORT_PT2 \r
+#define PORT_PIN_NAME_RXD0 PORT_PS0 \r
+#define PORT_PIN_NAME_TXD0 PORT_PS1 \r
+#define PORT_PIN_NAME_RXD1 PORT_PS2 \r
+#define PORT_PIN_NAME_TXD1 PORT_PS3 \r
+#define PORT_PIN_NAME_PM6 PORT_PM6 \r
+#define PORT_PIN_NAME_PM7 PORT_PM7 \r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 09:10:16 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Pwm.h"\r
+\r
+const Pwm_ConfigType PwmConfig =\r
+{\r
+ .channels = { \r
+ {\r
+ .channel = GREENLED,\r
+ DUTY_AND_PERIOD(4096,188.0),\r
+ .centerAlign = STD_OFF,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = STD_ON,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD\r
+ }, \r
+ {\r
+ .channel = REDLED,\r
+ DUTY_AND_PERIOD(24576,188.0),\r
+ .centerAlign = STD_OFF,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = STD_ON,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD\r
+ },\r
+ },\r
+ .busPrescalerA = PRESCALER_128,\r
+ .busPrescalerB = PRESCALER_2,\r
+ .prescalerA = 1,\r
+ .prescalerB = 1,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 09:10:16 CET 2010\r
+ */\r
+\r
+
+#if (PWM_SW_MAJOR_VERSION != 1)
+#error "Pwm: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define PWM_DEV_ERROR_DETECT STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_OFF\r
+#define PWM_FREEZE_ENABLE STD_OFF\r
+\r
+// Define what API functions to enable.\r
+#define PWM_GET_OUTPUT_STATE STD_OFF\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+#define PWM_DEINIT STD_OFF\r
+#define PWM_DUTYCYCLE STD_ON\r
+#define PWM_SET_OUTPUT_TO_IDLE STD_OFF\r
+#define PWM_VERSION_INFO_API STD_OFF\r
+\r
+\r
+\r
+/**\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/**\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == channel id.\r
+ */\r
+typedef uint8 Pwm_ChannelType;\r
+\r
+/**\r
+ * PWM070: All time units used within the API services of the PWM module shall\r
+ * be of the unit ticks.\r
+ */\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ GREENLED = 1 ,\r
+ REDLED = 0 ,\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+/* 1 =PWMchannel output is high at the beginning of the period, then goes low when the duty count\r
+is reached. */\r
+#define POLARITY_NORMAL 1\r
+#define POLARITY_INVERSED 0\r
+\r
+/**\r
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,\r
+ * the following macro can be used to convert between that format and the\r
+ * driver format.\r
+ */\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (uint8)((uint32)((uint32)_duty*(uint32)_period)>>15), .period = _period\r
+\r
+\r
+typedef struct {\r
+ /** Number of duty ticks */\r
+ uint8_t duty;\r
+ /** Length of period, in ticks */\r
+ uint8_t period;\r
+ /** Center or left align */\r
+ uint8_t centerAlign:1;\r
+ /** Polarity of the channel */\r
+ uint8_t polarity:1;\r
+ /** Scaled clock enabled */\r
+ uint8_t scaledClockEnable:1;\r
+ /** idle state */\r
+ uint8_t idleState:1;\r
+\r
+ uint8_t reserved:4;\r
+\r
+ Pwm_ChannelClassType class;\r
+\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+typedef enum{\r
+ PRESCALER_1 = 0,\r
+ PRESCALER_2 = 1,\r
+ PRESCALER_4 = 2,\r
+ PRESCALER_8 = 3,\r
+ PRESCALER_16 = 4,\r
+ PRESCALER_32 = 5,\r
+ PRESCALER_64 = 6,\r
+ PRESCALER_128 = 7,\r
+}Pwm_PrescalerType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType channels[PWM_NUMBER_OF_CHANNELS];\r
+ Pwm_PrescalerType busPrescalerA;\r
+ Pwm_PrescalerType busPrescalerB;\r
+ uint8_t prescalerA;\r
+ uint8_t prescalerB;\r
+} Pwm_ConfigType;\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+\r
+/* The board Elmicro HCS12 T-Board comes with HCS12X512DP.\r
+ * This memory mapping is for that CPU.\r
+ */\r
+ \r
+page0 (rwx) : ORIGIN = 0x0, LENGTH = 2k\r
+\r
+/* RAM */\r
+data (rwx) : ORIGIN = 0x1000, LENGTH = 12k\r
+\r
+eeprom (rx): ORIGIN = 0x0800, LENGTH = 2k\r
+text (rx) : ORIGIN = 0x4000, LENGTH = 48k\r
+ \r
+/* high fixed bank, reserve 0x100 vectors and security. */\r
+text_h (rx) : ORIGIN = 0xc002, LENGTH = 16k-0x102\r
+vectors (rx) : ORIGIN = 0xff80, LENGTH = 0x80\r
+ \r
+/* Flash memory banks VMA:s */\r
+bank_A (rx) : ORIGIN = 0x790000, LENGTH = 16k /* Page E0 */\r
+bank_B (rx) : ORIGIN = 0x794000, LENGTH = 16k /* Page E1 */\r
+bank_C (rx) : ORIGIN = 0x798000, LENGTH = 16k /* Page E2 */\r
+bank_D (rx) : ORIGIN = 0x79c000, LENGTH = 16k /* Page E3 */\r
+bank_E (rx) : ORIGIN = 0x7A0000, LENGTH = 16k /* Page E4 */\r
+bank_F (rx) : ORIGIN = 0x7A4000, LENGTH = 16k /* Page E5 */\r
+bank_G (rx) : ORIGIN = 0x7A8000, LENGTH = 16k /* Page E6 */\r
+bank_H (rx) : ORIGIN = 0x7Ac000, LENGTH = 16k /* Page E7 */\r
+bank_I (rx) : ORIGIN = 0x7B0000, LENGTH = 16k /* Page E8 */\r
+bank_J (rx) : ORIGIN = 0x7B4000, LENGTH = 16k /* Page E9 */\r
+bank_K (rx) : ORIGIN = 0x7B8000, LENGTH = 16k /* Page EA */\r
+bank_L (rx) : ORIGIN = 0x7Bc000, LENGTH = 16k /* Page EB */\r
+bank_M (rx) : ORIGIN = 0x7C0000, LENGTH = 16k /* Page EC */\r
+bank_N (rx) : ORIGIN = 0x7C4000, LENGTH = 16k /* Page ED */\r
+bank_O (rx) : ORIGIN = 0x7C8000, LENGTH = 16k /* Page EE */\r
+bank_P (rx) : ORIGIN = 0x7Cc000, LENGTH = 16k /* Page EF */\r
+ \r
+bank_Q (rx) : ORIGIN = 0x7D0000, LENGTH = 16k /* Page F0 */\r
+bank_R (rx) : ORIGIN = 0x7D4000, LENGTH = 16k /* Page F1 */\r
+bank_S (rx) : ORIGIN = 0x7D8000, LENGTH = 16k /* Page F2 */\r
+bank_T (rx) : ORIGIN = 0x7Dc000, LENGTH = 16k /* Page F3 */\r
+bank_U (rx) : ORIGIN = 0x7E0000, LENGTH = 16k /* Page F4 */\r
+bank_V (rx) : ORIGIN = 0x7E4000, LENGTH = 16k /* Page F5 */\r
+bank_W (rx) : ORIGIN = 0x7E8000, LENGTH = 16k /* Page F6 */\r
+bank_X (rx) : ORIGIN = 0x7Ec000, LENGTH = 16k /* Page F7 */\r
+bank_Y (rx) : ORIGIN = 0x7F0000, LENGTH = 16k /* Page F8 */\r
+bank_Z (rx) : ORIGIN = 0x7F4000, LENGTH = 16k /* Page F9 */\r
+bank_AA (rx) : ORIGIN = 0x7F8000, LENGTH = 16k /* Page FA */\r
+bank_AB (rx) : ORIGIN = 0x7Fc000, LENGTH = 16k /* Page FB */\r
+bank_AC (rx) : ORIGIN = 0x800000, LENGTH = 16k /* Page FC */\r
+bank_FIX1 (rx) : ORIGIN = 0x804000, LENGTH = 16k /* Page FD */\r
+/* bankxx (rx) : ORIGIN = 0x808000, LENGTH = 16k /* Page FE Not used Why?*/\r
+bank_FIX2 (rx) : ORIGIN = 0x80c002, LENGTH = 16k-0x102 /* Page FF */\r
+ \r
+/* NoICE Elf loading */ \r
+\r
+bank_A_lma (rx) : ORIGIN = 0x790000, LENGTH = 16k /* Page E0 */ \r
+bank_B_lma (rx) : ORIGIN = 0x794000, LENGTH = 16k /* Page E1 */\r
+bank_C_lma (rx) : ORIGIN = 0x798000, LENGTH = 16k /* Page E2 */\r
+bank_D_lma (rx) : ORIGIN = 0x79c000, LENGTH = 16k /* Page E3 */\r
+bank_E_lma (rx) : ORIGIN = 0x7A0000, LENGTH = 16k /* Page E4 */\r
+bank_F_lma (rx) : ORIGIN = 0x7A4000, LENGTH = 16k /* Page E5 */\r
+bank_G_lma (rx) : ORIGIN = 0x7A8000, LENGTH = 16k /* Page E6 */\r
+bank_H_lma (rx) : ORIGIN = 0x7Ac000, LENGTH = 16k /* Page E7 */\r
+bank_I_lma (rx) : ORIGIN = 0x7B0000, LENGTH = 16k /* Page E8 */\r
+bank_J_lma (rx) : ORIGIN = 0x7B4000, LENGTH = 16k /* Page E9 */\r
+bank_K_lma (rx) : ORIGIN = 0x7B8000, LENGTH = 16k /* Page EA */\r
+bank_L_lma (rx) : ORIGIN = 0x7Bc000, LENGTH = 16k /* Page EB */\r
+bank_M_lma (rx) : ORIGIN = 0x7C0000, LENGTH = 16k /* Page EC */\r
+bank_N_lma (rx) : ORIGIN = 0x7C4000, LENGTH = 16k /* Page ED */\r
+bank_O_lma (rx) : ORIGIN = 0x7C8000, LENGTH = 16k /* Page EE */\r
+bank_P_lma (rx) : ORIGIN = 0x7Cc000, LENGTH = 16k /* Page EF */\r
+\r
+bank_Q_lma (rx) : ORIGIN = 0x7D0000, LENGTH = 16k /* Page F0 */\r
+bank_R_lma (rx) : ORIGIN = 0x7D4000, LENGTH = 16k /* Page F1 */\r
+bank_S_lma (rx) : ORIGIN = 0x7D8000, LENGTH = 16k /* Page F2 */\r
+bank_T_lma (rx) : ORIGIN = 0x7Dc000, LENGTH = 16k /* Page F3 */\r
+bank_U_lma (rx) : ORIGIN = 0x7E0000, LENGTH = 16k /* Page F4 */\r
+bank_V_lma (rx) : ORIGIN = 0x7E4000, LENGTH = 16k /* Page F5 */\r
+bank_W_lma (rx) : ORIGIN = 0x7E8000, LENGTH = 16k /* Page F6 */\r
+bank_X_lma (rx) : ORIGIN = 0x7Ec000, LENGTH = 16k /* Page F7 */\r
+bank_Y_lma (rx) : ORIGIN = 0x7F0000, LENGTH = 16k /* Page F8 */\r
+bank_Z_lma (rx) : ORIGIN = 0x7F4000, LENGTH = 16k /* Page F9 */\r
+bank_AA_lma (rx) : ORIGIN = 0x7F8000, LENGTH = 16k /* Page FA */\r
+bank_AB_lma (rx) : ORIGIN = 0x7Fc000, LENGTH = 16k /* Page FB */\r
+bank_AC_lma (rx) : ORIGIN = 0x800000, LENGTH = 16k /* Page FC */\r
+bank_FIX1_lma (rx) : ORIGIN = 0x804000, LENGTH = 16k /* Page FD */\r
+/* bankxx_lma (rx) : ORIGIN = 0x808000, LENGTH = 16k /* Page FE Not used Why?*/\r
+bank_FIX2_lma (rx) : ORIGIN = 0x80c002, LENGTH = 16k-0x102 /* Page FF */\r
+vectors_lma (rx) : ORIGIN = 0x80ff80, LENGTH = 0x80\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>tboard_config</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="303715fd-6599-41c2-8c4e-d60c4b84b8de">\r
+ <SHORT-NAME>tboard_config</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">HCS12</SD>\r
+ <SD GID="GENDIR">/arc/boards/hcs12x_elmicro_tboard/config</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/tboard_config/SwComposition_tboard_config</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Mcu</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Port</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Dio</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Adc</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Pwm</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Gpt</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Can</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="fb9da4ba-41cc-4e91-8312-d2174ffea2e3">\r
+ <SHORT-NAME>SwComposition_tboard_config</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="869ab916-7358-4197-8551-225ce5236114">\r
+ <SHORT-NAME>Mcu</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Mcu</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="0202b255-3c62-4340-b071-021e6f6e5754">\r
+ <SHORT-NAME>McuGeneralConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuGeneralConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="3a863a59-9129-4971-bf33-1b2597733829">\r
+ <SHORT-NAME>McuModuleConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSrcFailureNotification</DEFINITION-REF>\r
+ <VALUE>DISABLED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuNumberOfMcuModes</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuRamSectors</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuResetSetting</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="42876123-e30b-411f-8916-e7ec0e06224e">\r
+ <SHORT-NAME>McuClockSettingConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuDefaultClockReference</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Mcu/McuModuleConfiguration/McuClockSettingConfig/Clock</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="48533cbf-b37f-4bdd-bef2-1c1d6f7c38f0">\r
+ <SHORT-NAME>Clock</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>1.6E7</VALUE>\r
+ </FLOAT-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllClock</DEFINITION-REF>\r
+ <VALUE>48000000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0e26b112-e113-4683-bc63-25ab38641c7b">\r
+ <SHORT-NAME>McuModeSettingConf</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="a06e6eca-b8f3-40ee-b70a-526e9d07d86d">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="256a7c74-3a97-4041-a4f6-fdab77196a48">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fe36d864-a9cf-47e9-99f4-179f339fea26">\r
+ <SHORT-NAME>II2C</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="13de6916-4779-4cf9-aa84-6423f24b5c75">\r
+ <SHORT-NAME>SDA</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>38</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d40af306-47db-4163-866b-ed234f4d54aa">\r
+ <SHORT-NAME>SCL</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>39</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c9118c42-7541-4c3e-aee5-9b33fb38e7de">\r
+ <SHORT-NAME>CAN0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="48995106-5317-492c-a8be-9dc90f86dce9">\r
+ <SHORT-NAME>TXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>49</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f355a281-9d29-4662-bd38-93b45a67b181">\r
+ <SHORT-NAME>RXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="970071df-1367-4fa6-b8ba-d12184ac9016">\r
+ <SHORT-NAME>LEDBAR</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="e75826c4-11e9-4c78-a62e-f64155f4d104">\r
+ <SHORT-NAME>PB0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f13211c5-d930-4315-88ac-f7baf7a013e1">\r
+ <SHORT-NAME>PB1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>17</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1bc00010-6ebe-436f-92e1-2d6c0895aa46">\r
+ <SHORT-NAME>PB2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>18</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0009d8fa-ebd5-451b-83f7-8a7e7fcc0ced">\r
+ <SHORT-NAME>PB3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>19</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="68143d0f-27ba-4bae-ad00-b8ca9392392d">\r
+ <SHORT-NAME>PB4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6367f310-133b-4b10-9275-5519396b82ff">\r
+ <SHORT-NAME>PB5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>21</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="59aa2eb4-ebde-472b-b5c1-ceecfce4336d">\r
+ <SHORT-NAME>PB6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>22</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4a169d18-36d5-40a7-8831-faf22622a866">\r
+ <SHORT-NAME>PB7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>23</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a0e9802a-f4ed-4ad3-b495-49157e822336">\r
+ <SHORT-NAME>DIPSW</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="27cbd4e4-129a-4364-be2b-a0054fb86cbe">\r
+ <SHORT-NAME>PH0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>24</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="30a97936-de39-42de-a3a9-d1e30f12af4d">\r
+ <SHORT-NAME>PH1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>25</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="084b83ee-4c09-4111-b19d-276dab9070ae">\r
+ <SHORT-NAME>PH2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>26</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7f90b11-a909-451c-a93e-b0bbe01df46a">\r
+ <SHORT-NAME>PH3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>27</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="417bb21d-caf2-48c2-a198-814203dc94da">\r
+ <SHORT-NAME>PH4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>28</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6e4f5953-9390-42fd-b33d-86736b010307">\r
+ <SHORT-NAME>PH5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>29</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="02660e29-0e6a-4781-98c8-74a3c9b908ef">\r
+ <SHORT-NAME>PH6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d85861f9-9523-45ad-aa84-44647733487b">\r
+ <SHORT-NAME>PH7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>31</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="103ee4c6-92df-4eae-b87a-096ccf9b56e2">\r
+ <SHORT-NAME>TIMER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="18f35583-11aa-4af3-a7cb-6bf56494047e">\r
+ <SHORT-NAME>PT0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>72</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="58635cff-b40b-41d7-879a-ea79efc33e06">\r
+ <SHORT-NAME>PT1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>73</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="99e5f077-39d8-48c6-8085-6b0764b0c48d">\r
+ <SHORT-NAME>BEEPER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>74</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="95d6d2f4-2db4-4495-84ed-fa8032997f5b">\r
+ <SHORT-NAME>PWM</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="89bf9c10-ceb3-4d60-961c-1051ed4b031d">\r
+ <SHORT-NAME>PP0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="182cd6da-fc4c-4b21-8ad3-57e3e8c3568a">\r
+ <SHORT-NAME>PP1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a1fa03c0-2470-4914-aabd-17c992c74a92">\r
+ <SHORT-NAME>SCI0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9b4e54e6-bc5b-4ccb-b5d9-33670baae41c">\r
+ <SHORT-NAME>RXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1ae13d69-adf7-481a-929d-0c916d37daee">\r
+ <SHORT-NAME>TXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1d78b7b3-38f6-486c-89b2-3369eab9e7df">\r
+ <SHORT-NAME>SCI1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="19e08fdf-14d6-4cfe-aa28-969f9479fde7">\r
+ <SHORT-NAME>RXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>58</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="580e6d9e-8812-438d-9b01-94f8b2cda75f">\r
+ <SHORT-NAME>TXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>59</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="218ea307-52d6-4837-abfb-080872edd058">\r
+ <SHORT-NAME>PM6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>54</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ac024e84-9ae2-4303-a186-6a93ffc0902b">\r
+ <SHORT-NAME>PM7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM7</VALUE>\r
+ </STRING-VALUE>\r
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+ <VALUE>55</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
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+ <CONTAINER UUID="19e54a5c-c778-4d34-88ae-80eaf1fff9d8">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="a1348e64-fb51-4549-9d69-1b3da6d3ec94">\r
+ <SHORT-NAME>Dio</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
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+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
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+ </ADMIN-DATA>\r
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+ <CONTAINERS>\r
+ <CONTAINER UUID="4037aeab-f046-4253-9082-473b45fccdf9">\r
+ <SHORT-NAME>DioGeneral</SHORT-NAME>\r
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+ <BOOLEAN-VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <CONTAINER UUID="cb003b50-d676-4dff-86ae-f975f01ee955">\r
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+ <VALUE>DIO_PORT_H</VALUE>\r
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+ <VALUE>255</VALUE>\r
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+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/ArcAdcConvTime</DEFINITION-REF>\r
+ <VALUE>4_CLOCKS</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/ArcAdcPrescaleDivideFactor</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9396794a-d8ed-4a2e-a8d6-8e9da5973fda">\r
+ <SHORT-NAME>ATD</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/ArcAdcChannelId</DEFINITION-REF>\r
+ <VALUE>ADC_CH2</VALUE>\r
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+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2feb004b-6700-4a45-9aaf-dd8580c90574">\r
+ <SHORT-NAME>ATDGroup</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupAccessMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupConversionMode</DEFINITION-REF>\r
+ <VALUE>ADC_CONV_MODE_CONTINUOUS</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupReplacement</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupTriggSrc</DEFINITION-REF>\r
+ <VALUE>ADC_TRIGG_SRC_SW</VALUE>\r
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+ <FUNCTION-NAME-VALUE>\r
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+ <VALUE>ATDCallback</VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <LINKER-SYMBOL-VALUE>\r
+ <DEFINITION-REF DEST="LINKER-SYMBOL-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcResultBufferPointer</DEFINITION-REF>\r
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+ </LINKER-SYMBOL-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcStreamingBufferMode</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcStreamingNumSamples</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
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+ <VALUE-REF DEST="CONTAINER">/tboard_config/Adc/AdcConfigSet/ATD_BLOCK/ATD</VALUE-REF>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7415dd0-c862-4cd0-9fb4-cd5555390325">\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcEnableQueuing</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcEnableStartStopGroupApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcGrpNotifCapability</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcHwTriggerApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcPriorityImplementation</DEFINITION-REF>\r
+ <VALUE>ADC_PRIORITY_NONE</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcReadGroupApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <SHORT-NAME>AdcPublishedInformation</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcPublishedInformation/AdcChannelValueSigned</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcPublishedInformation/AdcGroupFirstChannelFixed</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcPublishedInformation/AdcMaxChannelResolution</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="17747ce9-57d3-476c-8203-8c93cd2a5dcc">\r
+ <SHORT-NAME>Pwm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Pwm</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="ecc119e4-7869-41cc-af30-3792813737cf">\r
+ <SHORT-NAME>PwmChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="0d1ebc17-ef4d-4193-a492-7d8291ed2dca">\r
+ <SHORT-NAME>GreenLED</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmCenterAlign</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmScaledClockEnable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>4096</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
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+ <VALUE>188.0</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>POLARITY_NORMAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a05dbf4b-56e8-4e6b-8139-4864371f67c2">\r
+ <SHORT-NAME>RedLED</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmCenterAlign</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmScaledClockEnable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>24576</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
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+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>188.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>POLARITY_NORMAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c2a3ced7-5cde-4ca0-804f-9adeb4730fc4">\r
+ <SHORT-NAME>PwmConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmGetOutputState</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetDutyCycle</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetOutputToIdle</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetPeriodAndDuty</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="b4c0e419-333e-4370-8f36-28034d382f59">\r
+ <SHORT-NAME>PwmGeneral</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmFreezeEnable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDevErorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <VALUE>1</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmNotificationSupported</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmPeriodUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerA</DEFINITION-REF>\r
+ <VALUE>PRESCALER_128</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerB</DEFINITION-REF>\r
+ <VALUE>PRESCALER_2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerA</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerB</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="ef790408-8b7e-4a19-b347-51b4d423a531">\r
+ <SHORT-NAME>Gpt</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Gpt</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="98ae7b15-0802-4475-9429-0d1901fca0ff">\r
+ <SHORT-NAME>GptChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Gpt/GptChannelConfigSet</DEFINITION-REF>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="41029a14-7132-481b-93f9-56bb91cd516a">\r
+ <SHORT-NAME>GptConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptEnableDisableNotificationApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptTimeElapsedApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptTimeRemainingApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptWakeupFunctionalityApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <SHORT-NAME>GptDriverConfiguration</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptDriverConfiguration/GptDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptDriverConfiguration/GptReportWakeupSource</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="84bdd5be-ae8f-4920-8123-425502312b34">\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Can</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="bba8d9ee-ff87-446d-853b-536a783c874f">\r
+ <SHORT-NAME>CanConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a5208169-71d2-4f2e-b5fd-766509996c65">\r
+ <SHORT-NAME>CAN0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerActivation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerLoopback</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerBaudRate</DEFINITION-REF>\r
+ <VALUE>125</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanHWControllerId</DEFINITION-REF>\r
+ <VALUE>CAN_CTRL_0</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerPropSeg</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg1</DEFINITION-REF>\r
+ <VALUE>12</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg2</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="cd47453b-40ae-4958-bdb2-2c96b17c7952">\r
+ <SHORT-NAME>Mask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12IdamMaskType</DEFINITION-REF>\r
+ <VALUE>CAN_ARC_IDAM_2_32BIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12ArcIdmrValue</DEFINITION-REF>\r
+ <VALUE>18446744073709551615</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12ArcIdarValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a77c39d5-4ea7-4321-83c5-bbe27d61c01b">\r
+ <SHORT-NAME>RxBox</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>RECEIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ef1a36b6-b037-4177-99f8-3ae349f6157c">\r
+ <SHORT-NAME>TxBox</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>TRANSMIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b5becc71-8e43-478d-aee9-bde788df0dad">\r
+ <SHORT-NAME>CanGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanDevErrorDetection</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanMultiplexedTransmission</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+#undef CALIBRATION_ACTIVE\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/** @addtogroup EcuM ECU State Manager\r
- * @{ */\r
-\r
-/** @file EcuM_Cfg.h\r
- * Definitions of configuration parameters for ECU State Manager.\r
- * Initialization sequences are defined in EcuM_Callout_template.c\r
- */\r
-\r
-#warning "This default file may only be used as an example!"\r
-\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
-\r
-/** Build version info API */\r
-#define ECUM_VERSION_INFO_API STD_ON\r
-/** Using NVRAM Manager */\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-/** Enable Development Error Trace */\r
-#define ECUM_DEV_ERROR_DETECT STD_ON\r
-\r
-#include "EcuM_Generated_Types.h"\r
-\r
-#endif /*ECUM_CFG_H_*/\r
-/** @} */\r
\r
/* MPC55xx Reset Control Word(RCW) */\r
rcw : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash_calibration_area_0(R) : ORIGIN = 0x00004000, LENGTH = 32K\r
flash(R) : ORIGIN = 0x00000008, LENGTH = 1M\r
/* 5516S, 48K\r
* 5517S,5516G,5516E, 64K RAM\r
--- /dev/null
+#undef CALIBRATION_ACTIVE\r
\r
/* MPC55xx Reset Control Word(RCW) */\r
rcw : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash_calibration_area_0(R) : ORIGIN = 0x00004000, LENGTH = 32K\r
flash(R) : ORIGIN = 0x00000008, LENGTH = 1M\r
/* 5516S, 48K\r
* 5517S,5516G,5516E, 64K RAM\r
--- /dev/null
+#undef CALIBRATION_ACTIVE\r
# default or private\r
\r
# Memory + Peripherals\r
-MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG \r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG FLS \r
# System + Communication + Diagnostic\r
MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
# Additional\r
--- /dev/null
+#undef CALIBRATION_ACTIVE\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#warning "This default file may only be used as an example!"\r
-\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
-\r
-#define ECUM_VERSION_INFO_API STD_ON\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-#define ECUM_DEV_ERROR_DETECT STD_ON\r
-\r
-#include "EcuM_Generated_Types.h"\r
-\r
-#endif /*ECUM_CFG_H_*/\r
\r
\r
\r
-#warning "This default file may only be used as an example!"\r
-\r
#include "Fls.h"\r
+#include "Fls_Cfg.h"\r
#include <stdlib.h>\r
\r
\r
\r
\r
const Fls_SectorType fls_evbSectorList[] = {\r
- { // L0->L7\r
- .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
- .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
- .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
- // Number of continuous sectors with the above characteristics.\r
- .FlsNumberOfSectors = (uint32)8,// L0->L7 , 8 sectors\r
- },\r
- { // L8,L9\r
- .FlsSectorStartaddress = (Fls_AddressType)0x00020000,\r
- .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
- .FlsSectorSize = (Fls_LengthType)(64 KB), // 64Kbyte\r
- .FlsNumberOfSectors = (uint32)2,// L8,L9 , 2 sectors\r
- },\r
- { // M0->H7\r
- .FlsSectorStartaddress = (Fls_AddressType)0x00040000,\r
- .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ { // L0\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)1,// L0 , 1 sectors\r
+ },\r
+ { // L1-L2\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00004000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(48 KB), // 48Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)2,// L1->L2 , 2 sectors\r
+ },\r
+ { // L3\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x0001C000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)8,// L0->L7 , 8 sectors\r
+ },\r
+ { // L4-L5\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00020000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(128 KB), // 128Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)2,// L4->L5 , 8 sectors\r
+ },\r
+ { // H0->H11\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00060000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
.FlsSectorSize = (Fls_LengthType)(128 KB), // 128Kbyte\r
- .FlsNumberOfSectors = (uint32)6,// M0->H7\r
+ .FlsNumberOfSectors = (uint32)12,// H0->H11\r
}\r
};\r
\r
/*\r
* Block to partition map\r
*/\r
-uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,2,2,3,3,4,4,5,5,6,6,7,7,8,8 };\r
+uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9 };\r
\r
const Fls_ConfigType FlsConfigSet[]=\r
{\r
\r
\r
\r
-\r
-#warning "This default file may only be used as an example!"\r
-\r
#ifndef FLS_CFG_H_\r
#define FLS_CFG_H_\r
\r
\r
/* MPC55xx Reset Control Word(RCW) */\r
rcw : ORIGIN = 0x00000000, LENGTH = 0x8\r
-flash(R) : ORIGIN = 0x00000008, LENGTH = 2M\r
+flash_calibration_area_0(R) : ORIGIN = 0x00004000, LENGTH = 48K\r
+flash(R) : ORIGIN = 0x00040000, LENGTH = 2M\r
/* 5516S, 48K\r
* 5517S,5516G,5516E, 64K RAM\r
* 5517G,E , 80K RAM\r
--- /dev/null
+#undef CALIBRATION_ACTIVE\r
\r
/* MPC55xx Reset Control Word(RCW) */\r
rcw : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash_calibration_area_0(R) : ORIGIN = 0x00004000, LENGTH = 48K\r
flash(R) : ORIGIN = 0x00000008, LENGTH = 0x100000\r
/* 5516S, 48K\r
* 5517S,5516G,5516E, 64K RAM\r
# What buildable modules does this board have, \r
# default or private\r
\r
-MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM \r
+MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM GPT \r
# System + Communication + Diagnostic\r
MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
# Additional\r
DIO_CHANNEL_F14,\r
DIO_CHANNEL_F15,\r
\r
-} Dio_ChannelType;\r
+} Dio_Hw_ChannelType;\r
//@}\r
\r
/** HW specific DIO port definitions. */\r
DIO_PORT_D,\r
DIO_PORT_E,\r
DIO_PORT_F,\r
-} Dio_PortType;\r
+} Dio_Hw_PortType;\r
\r
-/** @req DIO021 */\r
-/** @req DIO022 */\r
-typedef struct\r
-{\r
- Dio_PortType port;\r
- uint16 offset;\r
- uint16 mask;\r
-} Dio_ChannelGroupType;\r
-\r
-/** @req DIO023 */\r
-typedef uint16 Dio_LevelType;\r
-\r
-/** @req DIO024 */\r
-typedef uint16 Dio_PortLevelType;\r
-\r
-#define LED_CHANNEL (DIO_CHANNEL_B13)\r
+#define LED_CHANNEL1 (DIO_CHANNEL_B13)\r
+#define LED_CHANNEL2 (DIO_CHANNEL_B14)\r
\r
#define LED_PORT (DIO_PORT_B)\r
\r
\r
const Dio_ChannelType DioChannelConfigData[] =\r
{\r
- LED_CHANNEL,\r
+ LED_CHANNEL1,\r
+ LED_CHANNEL2,\r
DIO_END_OF_LIST,\r
};\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+\r
+extern void Gpt2Notification(void);\r
+extern void OneWireEventhandler(void);\r
+extern void OneWireSequenceHandler(void);\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_TIM_2,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_TIM_3,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = OneWireSequenceHandler,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },\r
+ {\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Gpt GPT Driver\r
+ * @{ */\r
+\r
+/** @file Gpt_Cfg.h\r
+ * Definitions of configuration parameters for GPT Driver.\r
+ */\r
+\r
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Configuration is pre-compile only. Not supported. */\r
+#define GPT_VARIANT_PC STD_OFF\r
+/** Configuration is a mix of pre-compile and post-build */\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/** HW PIT channels */\r
+#define GPT_CHANNEL_TIM_1 0\r
+#define GPT_CHANNEL_TIM_2 1\r
+#define GPT_CHANNEL_TIM_3 2\r
+#define GPT_CHANNEL_TIM_4 3\r
+\r
+#define GPT_CHANNEL_CNT (GPT_CHANNEL_TIM_4 + 1)\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+/** Enable Development Error Trace */\r
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+/** Enables/Disables wakeup source reporting. Not supported. */\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+/** Build DeInit API */\r
+#define GPT_DEINIT_API STD_ON\r
+/** Build notification API */\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
+/** Build time remaining API */\r
+#define GPT_TIME_REMAINING_API STD_ON\r
+/** Build time elapsed API */\r
+#define GPT_TIME_ELAPSED_API STD_ON\r
+/** Build version info API */\r
+#define GPT_VERSION_INFO_API STD_ON\r
+/** Build wakeup API. Not supported */\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+/** This container contains the channel-wide configuration (parameters) of the\r
+ * GPT Driver */\r
+typedef struct {\r
+ /** GPT187: The GPT module specific clock input for the timer unit can\r
+ * statically be configured and allows to select different clock sources\r
+ * (external clock, internal GPT specific clock) per channel */\r
+ uint32 GptChannelClkSrc;\r
+\r
+ /** Channel Id of the GPT channel. */\r
+ Gpt_ChannelType GptChannelId;\r
+\r
+ /** Specifies the behaviour of the timer channel after the timeout has expired. */\r
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ /** Function pointer to callback function */\r
+ void (*GptNotification)();\r
+\r
+ /** GPT module specific prescaler factor per channel */\r
+ uint32 GptChannelPrescale;\r
+\r
+ /** GPT188: Enables wakeup capability of CPU for a channel when timeout\r
+ * period expires. This might be different to enabling the notification\r
+ * depending on hardware capabilities. Not supported. */\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+/** The list of channel configurations */\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
+/** @} */\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-#include "Port_Cfg.h"\r
-\r
-\r
-typedef enum {\r
- PORTA,\r
- PORTB,\r
- PORTC,\r
- PORTD,\r
- PORTE,\r
- NUMBER_OF_PORTS\r
-} Port_PortType;\r
-\r
-const u32 remaps[] = {\r
- GPIO_Remap1_CAN1,\r
- GPIO_PartialRemap2_TIM2,\r
-};\r
-\r
-const Port_PortConfigType porta = {\r
- .port = GPIOA,\r
- .pinCount = 1,\r
- .pins = {\r
- {\r
- .GPIO_Pin = GPIO_Pin_1,\r
- .GPIO_Mode = GPIO_Mode_AIN,\r
- .GPIO_Speed = GPIO_Speed_2MHz\r
- },\r
- }\r
-};\r
-\r
-\r
-const Port_PortConfigType portb = {\r
- .port = GPIOB,\r
- .pinCount = 4,\r
- .pins = {\r
- /* PB8 is CAN1_RX, remapped: */\r
- {\r
- .GPIO_Pin = GPIO_Pin_8,\r
- .GPIO_Mode = GPIO_Mode_IPU,\r
- .GPIO_Speed = GPIO_Speed_10MHz\r
- },\r
- /* PB9 is CAN1_TX, remapped: */\r
- {\r
- .GPIO_Pin = GPIO_Pin_9,\r
- .GPIO_Mode = GPIO_Mode_AF_PP,\r
- .GPIO_Speed = GPIO_Speed_10MHz\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11,\r
- .GPIO_Mode = GPIO_Mode_AF_PP,\r
- .GPIO_Speed = GPIO_Speed_50MHz\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15,\r
- .GPIO_Mode = GPIO_Mode_Out_PP,\r
- .GPIO_Speed = GPIO_Speed_10MHz\r
- },\r
-\r
- }\r
-};\r
-\r
-const Port_PortConfigType portc = {\r
- .port = GPIOC,\r
- .pinCount = 1,\r
- .pins = {\r
- {\r
- .GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12,\r
- .GPIO_Mode = GPIO_Mode_Out_PP,\r
- .GPIO_Speed = GPIO_Speed_10MHz,\r
- },\r
-\r
- }\r
-};\r
-\r
-const Port_PortConfigType portd = {\r
- .port = GPIOD,\r
- .pinCount = 1,\r
- .pins = {\r
- {\r
- .GPIO_Pin = 0xffff,\r
- .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
- .GPIO_Speed = GPIO_Speed_2MHz,\r
- },\r
- }\r
-};\r
-\r
-const Port_PortConfigType porte = {\r
- .port = GPIOE,\r
- .pinCount = 1,\r
- .pins = {\r
- {\r
- .GPIO_Pin = 0xffff,\r
- .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
- .GPIO_Speed = GPIO_Speed_2MHz,\r
- },\r
- }\r
-};\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
\r
-const Port_ConfigType PortConfigData = {\r
- .portCount = NUMBER_OF_PORTS,\r
- .ports = {\r
- &porta,\r
- &portb,\r
- &portc,\r
- &portd,\r
- &porte\r
- },\r
-\r
- .remapCount = sizeof(remaps) / sizeof(u32),\r
- .remaps = &remaps[0]\r
+#include "Port_Cfg.h"\r
+#include "stm32f10x_gpio.h"
+
+
+const uint32 remaps[] = {
+ GPIO_Remap1_CAN1,
+ GPIO_PartialRemap2_TIM2,
+};
+
+const GpioPinCnfMode_Type GPIOConf[] =
+{
+ /*GPIOA*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOB*/
+ {
+ .GpioPinCnfMode_15 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_14 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_12 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_11 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_10 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_9 = GPIO_OUTPUT_10MHz_MODE | GPIO_ALT_PUSHPULL_CNF,/* PB9 is CAN1_TX, remapped: */
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF,/* PB8 is CAN1_RX, remapped: */
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOC*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_11 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_10 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_OUTPUT_2MHz_MODE | GPIO_INPUT_PULLUP_CNF,
+ .GpioPinCnfMode_3 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_2 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_1 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_0 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ },
+ /*GPIOD*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOE*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOF*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOG*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ }
+};
+
+const GpioPinOutLevel_Type GPIOOutConf[] =
+{
+ /* GPIOA */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOB */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOC */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOD */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOE */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOF */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOG */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+};
+
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = 7, // TODO Replace with sizeof expression\r
+ .padConfig = GPIOConf,
+ .outConfig = GPIOOutConf,\r
+
+ .remapCount = sizeof(remaps) / sizeof(uint32),
+ .remaps = &remaps[0]
};\r
\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Port Port Driver
+ * @{ */
+
+/** @file Port_Cfg.h
+ * Definitions of configuration parameters for Port Driver.
+ */
+
#ifndef PORT_CFG_H_\r
#define PORT_CFG_H_\r
\r
#include "Std_Types.h"\r
-#include "stm32f10x_gpio.h"\r
-\r
-/** Build version info API */\r
-#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */\r
-/** Enable Development Error Trace */\r
-#define PORT_DEV_ERROR_DETECT STD_ON\r
-/** Build change pin direction API */\r
-#define PORT_SET_PIN_DIRECTION_API STD_ON\r
-/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
-#define PORT_SET_PIN_MODE_API STD_ON\r
-\r
-/** @req PORT124 */\r
-typedef uint8 Port_PinModeType;\r
-\r
-/** HW specific symbolic names of pins */\r
-/** @req PORT013 */\r
-typedef enum{\r
- PIN1,\r
-} Port_PinType;\r
+
+/** Build version info API */
+#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */
+/** Enable Development Error Trace */
+#define PORT_DEV_ERROR_DETECT STD_ON
+/** Build change pin direction API */
+#define PORT_SET_PIN_DIRECTION_API STD_ON
+/** Allow Pin mode changes during runtime (not avail on this CPU) */
+#define PORT_SET_PIN_MODE_API STD_OFF
+
+#define GPIO_INPUT_MODE (0)
+#define GPIO_OUTPUT_10MHz_MODE (1)
+#define GPIO_OUTPUT_2MHz_MODE (2)
+#define GPIO_OUTPUT_50MHz_MODE (3)
+
+/* Valid for input modes. */
+#define GPIO_ANALOG_INPUT_CNF (0 << 2)
+#define GPIO_FLOATING_INPUT_CNF (1 << 2)
+#define GPIO_INPUT_PULLUP_CNF (2 << 2)
+#define GPIO_RESERVED_CNF (3 << 2)
+
+/* Valid for output modes. */
+#define GPIO_OUTPUT_PUSHPULL_CNF (0 << 2)
+#define GPIO_OUTPUT_OPENDRAIN_CNF (1 << 2)
+#define GPIO_ALT_PUSHPULL_CNF (2 << 2)
+#define GPIO_ALT_OPENDRAIN_CNF (3 << 2)
+
+#define GPIO_OUTPUT_LOW (0)
+#define GPIO_OUTPUT_HIGH (1)
+
+typedef struct
+{
+ uint8_t GpioPinCnfMode_0:4;
+ uint8_t GpioPinCnfMode_1:4;
+ uint8_t GpioPinCnfMode_2:4;
+ uint8_t GpioPinCnfMode_3:4;
+ uint8_t GpioPinCnfMode_4:4;
+ uint8_t GpioPinCnfMode_5:4;
+ uint8_t GpioPinCnfMode_6:4;
+ uint8_t GpioPinCnfMode_7:4;
+ uint8_t GpioPinCnfMode_8:4;
+ uint8_t GpioPinCnfMode_9:4;
+ uint8_t GpioPinCnfMode_10:4;
+ uint8_t GpioPinCnfMode_11:4;
+ uint8_t GpioPinCnfMode_12:4;
+ uint8_t GpioPinCnfMode_13:4;
+ uint8_t GpioPinCnfMode_14:4;
+ uint8_t GpioPinCnfMode_15:4;
+}GpioPinCnfMode_Type;
+
+typedef struct
+{
+ uint8_t GpioPinOutLevel_0:1;
+ uint8_t GpioPinOutLevel_1:1;
+ uint8_t GpioPinOutLevel_2:1;
+ uint8_t GpioPinOutLevel_3:1;
+ uint8_t GpioPinOutLevel_4:1;
+ uint8_t GpioPinOutLevel_5:1;
+ uint8_t GpioPinOutLevel_6:1;
+ uint8_t GpioPinOutLevel_7:1;
+ uint8_t GpioPinOutLevel_8:1;
+ uint8_t GpioPinOutLevel_9:1;
+ uint8_t GpioPinOutLevel_10:1;
+ uint8_t GpioPinOutLevel_11:1;
+ uint8_t GpioPinOutLevel_12:1;
+ uint8_t GpioPinOutLevel_13:1;
+ uint8_t GpioPinOutLevel_14:1;
+ uint8_t GpioPinOutLevel_15:1;
+}GpioPinOutLevel_Type;
+
+/* To be compatible with Port.h */
+typedef uint8_t Port_PinType;
\r
-/* Configuration of one specific port */\r
-typedef struct {\r
- uint16_t pinCount;\r
- GPIO_TypeDef *port;\r
- const GPIO_InitTypeDef pins[];\r
-\r
-} Port_PortConfigType;\r
-\r
-/** Top level configuration container */\r
-/** @req PORT073 */\r
-typedef struct {\r
- uint16_t remapCount;\r
- const uint32_t* remaps;\r
-\r
- uint16_t portCount;\r
- const Port_PortConfigType* ports[];\r
+/** Top level configuration container */
+typedef struct\r
+{
+ /** Total number of pins */
+ uint16_t padCnt;
+ /** List of pin configurations */
+ const GpioPinCnfMode_Type *padConfig;
+ const GpioPinOutLevel_Type *outConfig;
+ /** Total number of pin default levels */\r
+
+ uint16_t remapCount;
+ const uint32_t* remaps;
} Port_ConfigType;\r
-\r
-/** Instance of the top level configuration container */\r
+
+/** Instance of the top level configuration container */
extern const Port_ConfigType PortConfigData;\r
\r
#endif /*PORT_CFG_H_*/\r
+/** @} */
\r
CFG=ARM ARM_CM3\r
# Add our board \r
-CFG+=BRD_STM32_MCBSTM32 \r
+CFG+=BRD_STM32_STM3210C \r
\r
# \r
# ST have devided devices into ( See chapter 6 in Ref manual )\r
# What buildable modules does this board have, \r
# default or private\r
\r
-MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM \r
+MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM GPT \r
# System + Communication + Diagnostic\r
MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
# Additional\r
-MOD_AVAIL+=RAMLOG TCF LWIP\r
+MOD_AVAIL+=RAMLOG TCF LWIP SLEEP RTE\r
\r
#\r
# Extra defines \r
DIO_CHANNEL_F14,\r
DIO_CHANNEL_F15,\r
\r
-} Dio_ChannelType;\r
+} Dio_Hw_ChannelType;\r
//@}\r
\r
/** HW specific DIO port definitions. */\r
DIO_PORT_D,\r
DIO_PORT_E,\r
DIO_PORT_F,\r
-} Dio_PortType;\r
+} Dio_Hw_PortType;\r
\r
-/** @req DIO021 */\r
-/** @req DIO022 */\r
-typedef struct\r
-{\r
- Dio_PortType port;\r
- uint16 offset;\r
- uint16 mask;\r
-} Dio_ChannelGroupType;\r
-\r
-/** @req DIO023 */\r
-typedef uint16 Dio_LevelType;\r
-\r
-/** @req DIO024 */\r
-typedef uint16 Dio_PortLevelType;\r
-\r
-#define LED_CHANNEL1 (DIO_CHANNEL_D3)\r
-#define LED_CHANNEL2 (DIO_CHANNEL_D4)\r
-#define LED_CHANNEL3 (DIO_CHANNEL_D7)\r
-#define LED_CHANNEL4 (DIO_CHANNEL_D13)\r
+#define LED_CHANNEL1 (DIO_CHANNEL_D7)\r
+#define LED_CHANNEL2 (DIO_CHANNEL_D13)\r
+#define LED_CHANNEL3 (DIO_CHANNEL_D3)\r
+#define LED_CHANNEL4 (DIO_CHANNEL_D4)\r
\r
#define LED_PORT (DIO_PORT_D)\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+\r
+extern void Gpt2Notification(void);\r
+extern void OneWireEventhandler(void);\r
+extern void OneWireSequenceHandler(void);\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_TIM_2,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_TIM_3,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = OneWireSequenceHandler,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },\r
+ {\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Gpt GPT Driver\r
+ * @{ */\r
+\r
+/** @file Gpt_Cfg.h\r
+ * Definitions of configuration parameters for GPT Driver.\r
+ */\r
+\r
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Configuration is pre-compile only. Not supported. */\r
+#define GPT_VARIANT_PC STD_OFF\r
+/** Configuration is a mix of pre-compile and post-build */\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/** HW PIT channels */\r
+#define GPT_CHANNEL_TIM_1 0\r
+#define GPT_CHANNEL_TIM_2 1\r
+#define GPT_CHANNEL_TIM_3 2\r
+#define GPT_CHANNEL_TIM_4 3\r
+\r
+#define GPT_CHANNEL_CNT (GPT_CHANNEL_TIM_4 + 1)\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+/** Enable Development Error Trace */\r
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+/** Enables/Disables wakeup source reporting. Not supported. */\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+/** Build DeInit API */\r
+#define GPT_DEINIT_API STD_ON\r
+/** Build notification API */\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
+/** Build time remaining API */\r
+#define GPT_TIME_REMAINING_API STD_ON\r
+/** Build time elapsed API */\r
+#define GPT_TIME_ELAPSED_API STD_ON\r
+/** Build version info API */\r
+#define GPT_VERSION_INFO_API STD_ON\r
+/** Build wakeup API. Not supported */\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+/** This container contains the channel-wide configuration (parameters) of the\r
+ * GPT Driver */\r
+typedef struct {\r
+ /** GPT187: The GPT module specific clock input for the timer unit can\r
+ * statically be configured and allows to select different clock sources\r
+ * (external clock, internal GPT specific clock) per channel */\r
+ uint32 GptChannelClkSrc;\r
+\r
+ /** Channel Id of the GPT channel. */\r
+ Gpt_ChannelType GptChannelId;\r
+\r
+ /** Specifies the behaviour of the timer channel after the timeout has expired. */\r
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ /** Function pointer to callback function */\r
+ void (*GptNotification)();\r
+\r
+ /** GPT module specific prescaler factor per channel */\r
+ uint32 GptChannelPrescale;\r
+\r
+ /** GPT188: Enables wakeup capability of CPU for a channel when timeout\r
+ * period expires. This might be different to enabling the notification\r
+ * depending on hardware capabilities. Not supported. */\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+/** The list of channel configurations */\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
+/** @} */\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-#include "Port_Cfg.h"\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
\r
-\r
-typedef enum {\r
- PORTA,\r
- PORTB,\r
- PORTC,\r
- PORTD,\r
- PORTE,\r
- NUMBER_OF_PORTS\r
-} Port_PortType;\r
-\r
-const u32 remaps[] = {\r
- GPIO_Remap_ETH,\r
- GPIO_Remap2_CAN1,\r
-};\r
-\r
-const Port_PortConfigType porta = {\r
- .port = GPIOA,\r
- .pinCount = 3,\r
- .pins = {\r
- {\r
- .GPIO_Pin = GPIO_Pin_2,\r
- .GPIO_Mode = GPIO_Mode_AF_PP,\r
- .GPIO_Speed = GPIO_Speed_50MHz\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3,\r
- .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
- .GPIO_Speed = GPIO_Speed_50MHz\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_8,\r
- .GPIO_Mode = GPIO_Mode_AF_PP,\r
- .GPIO_Speed = GPIO_Speed_50MHz\r
- },\r
- }\r
-};\r
-\r
-const Port_PortConfigType portb = {\r
- .port = GPIOB,\r
- .pinCount = 2,\r
- .pins = {\r
- {\r
- .GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13,\r
- .GPIO_Mode = GPIO_Mode_AF_PP,\r
- .GPIO_Speed = GPIO_Speed_50MHz\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_10,\r
- .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
- .GPIO_Speed = GPIO_Speed_50MHz\r
- },\r
-\r
- }\r
-};\r
-\r
-const Port_PortConfigType portc = {\r
- .port = GPIOC,\r
- .pinCount = 3,\r
- .pins = {\r
- {\r
- .GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2,\r
- .GPIO_Mode = GPIO_Mode_AF_PP,\r
- .GPIO_Speed = GPIO_Speed_50MHz,\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_3,\r
- .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
- .GPIO_Speed = GPIO_Speed_50MHz,\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_4,\r
- .GPIO_Mode = GPIO_Mode_AIN,\r
- .GPIO_Speed = GPIO_Speed_10MHz,\r
- },\r
-\r
- }\r
-};\r
-\r
-const Port_PortConfigType portd = {\r
- .port = GPIOD,\r
- .pinCount = 4,\r
- .pins = {\r
- {\r
- .GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12,\r
- .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
- .GPIO_Speed = GPIO_Speed_50MHz,\r
- },\r
- /* PD0 is CAN1_RX, remapped: */\r
- {\r
- .GPIO_Pin = GPIO_Pin_0,\r
- .GPIO_Mode = GPIO_Mode_IPU,\r
- .GPIO_Speed = GPIO_Speed_10MHz\r
- },\r
- /* PD1 is CAN1_TX, remapped: */\r
- {\r
- .GPIO_Pin = GPIO_Pin_1,\r
- .GPIO_Mode = GPIO_Mode_AF_PP,\r
- .GPIO_Speed = GPIO_Speed_10MHz\r
- },\r
- {\r
- .GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_7 | GPIO_Pin_13,\r
- .GPIO_Mode = GPIO_Mode_Out_PP,\r
- .GPIO_Speed = GPIO_Speed_10MHz\r
- },\r
- }\r
+#include "Port_Cfg.h"
+#include "stm32f10x_gpio.h"
+
+
+const uint32 remaps[] = {
+ GPIO_Remap_ETH,
+ GPIO_Remap2_CAN1,
+ GPIO_Remap_CAN2,
};\r
-\r
-const Port_PortConfigType porte = {\r
- .port = GPIOE,\r
- .pinCount = 1,\r
- .pins = {\r
- {\r
- .GPIO_Pin = 0xffff,\r
- .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
- .GPIO_Speed = GPIO_Speed_2MHz,\r
- },\r
- }\r
-};\r
-\r
-const Port_ConfigType PortConfigData = {\r
- .portCount = NUMBER_OF_PORTS,\r
- .ports = {\r
- &porta,\r
- &portb,\r
- &portc,\r
- &portd,\r
- &porte\r
- },\r
-\r
- .remapCount = sizeof(remaps) / sizeof(u32),\r
+
+const GpioPinCnfMode_Type GPIOConf[] =
+{
+ /*GPIOA*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOB*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_12 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_11 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_OUTPUT_10MHz_MODE | GPIO_ALT_PUSHPULL_CNF,/* PB6 is CAN2_TX, remapped: */
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF,/* PB5 is CAN2_RX, remapped: */
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOC*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_ANALOG_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_1 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOD*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_3 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_OUTPUT_10MHz_MODE | GPIO_ALT_PUSHPULL_CNF,/* PD1 is CAN1_TX, remapped: */
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF,/* PD0 is CAN1_RX, remapped: */
+ },
+ /*GPIOE*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOF*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOG*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ }
+};
+
+const GpioPinOutLevel_Type GPIOOutConf[] =
+{
+ /* GPIOA */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOB */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOC */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOD */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOE */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOF */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOG */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+};
+
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = 7, // TODO Replace with sizeof expression\r
+ .padConfig = GPIOConf,
+ .outConfig = GPIOOutConf,
+
+ .remapCount = sizeof(remaps) / sizeof(uint32),
.remaps = &remaps[0]\r
};\r
\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Port Port Driver
+ * @{ */
+
+/** @file Port_Cfg.h
+ * Definitions of configuration parameters for Port Driver.
+ */
+
#ifndef PORT_CFG_H_\r
#define PORT_CFG_H_\r
\r
#include "Std_Types.h"\r
-#include "stm32f10x_gpio.h"\r
-\r
-/** Build version info API */\r
-#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */\r
-/** Enable Development Error Trace */\r
-#define PORT_DEV_ERROR_DETECT STD_ON\r
-/** Build change pin direction API */\r
-#define PORT_SET_PIN_DIRECTION_API STD_ON\r
-/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
-#define PORT_SET_PIN_MODE_API STD_ON\r
-\r
-/** HW specific symbolic names of pins */\r
-/** @req PORT013 */\r
-typedef enum{\r
- PIN1,\r
-} Port_PinType;\r
+
+/** Build version info API */
+#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */
+/** Enable Development Error Trace */
+#define PORT_DEV_ERROR_DETECT STD_ON
+/** Build change pin direction API */
+#define PORT_SET_PIN_DIRECTION_API STD_ON
+/** Allow Pin mode changes during runtime (not avail on this CPU) */
+#define PORT_SET_PIN_MODE_API STD_OFF
+
+#define GPIO_INPUT_MODE (0)
+#define GPIO_OUTPUT_10MHz_MODE (1)
+#define GPIO_OUTPUT_2MHz_MODE (2)
+#define GPIO_OUTPUT_50MHz_MODE (3)
+
+/* Valid for input modes. */
+#define GPIO_ANALOG_INPUT_CNF (0 << 2)
+#define GPIO_FLOATING_INPUT_CNF (1 << 2)
+#define GPIO_INPUT_PULLUP_CNF (2 << 2)
+#define GPIO_RESERVED_CNF (3 << 2)
+
+/* Valid for output modes. */
+#define GPIO_OUTPUT_PUSHPULL_CNF (0 << 2)
+#define GPIO_OUTPUT_OPENDRAIN_CNF (1 << 2)
+#define GPIO_ALT_PUSHPULL_CNF (2 << 2)
+#define GPIO_ALT_OPENDRAIN_CNF (3 << 2)
+
+#define GPIO_OUTPUT_LOW (0)
+#define GPIO_OUTPUT_HIGH (1)
+
+typedef struct
+{
+ uint8_t GpioPinCnfMode_0:4;
+ uint8_t GpioPinCnfMode_1:4;
+ uint8_t GpioPinCnfMode_2:4;
+ uint8_t GpioPinCnfMode_3:4;
+ uint8_t GpioPinCnfMode_4:4;
+ uint8_t GpioPinCnfMode_5:4;
+ uint8_t GpioPinCnfMode_6:4;
+ uint8_t GpioPinCnfMode_7:4;
+ uint8_t GpioPinCnfMode_8:4;
+ uint8_t GpioPinCnfMode_9:4;
+ uint8_t GpioPinCnfMode_10:4;
+ uint8_t GpioPinCnfMode_11:4;
+ uint8_t GpioPinCnfMode_12:4;
+ uint8_t GpioPinCnfMode_13:4;
+ uint8_t GpioPinCnfMode_14:4;
+ uint8_t GpioPinCnfMode_15:4;
+}GpioPinCnfMode_Type;
+
+typedef struct
+{
+ uint8_t GpioPinOutLevel_0:1;
+ uint8_t GpioPinOutLevel_1:1;
+ uint8_t GpioPinOutLevel_2:1;
+ uint8_t GpioPinOutLevel_3:1;
+ uint8_t GpioPinOutLevel_4:1;
+ uint8_t GpioPinOutLevel_5:1;
+ uint8_t GpioPinOutLevel_6:1;
+ uint8_t GpioPinOutLevel_7:1;
+ uint8_t GpioPinOutLevel_8:1;
+ uint8_t GpioPinOutLevel_9:1;
+ uint8_t GpioPinOutLevel_10:1;
+ uint8_t GpioPinOutLevel_11:1;
+ uint8_t GpioPinOutLevel_12:1;
+ uint8_t GpioPinOutLevel_13:1;
+ uint8_t GpioPinOutLevel_14:1;
+ uint8_t GpioPinOutLevel_15:1;
+}GpioPinOutLevel_Type;
+
+/* To be compatible with Port.h */
+typedef uint8_t Port_PinType;
\r
-/* Configuration of one specific port */\r
-typedef struct {\r
- uint16_t pinCount;\r
- GPIO_TypeDef *port;\r
- const GPIO_InitTypeDef pins[];\r
+/** Top level configuration container */
+typedef struct\r
+{
+ /** Total number of pins */
+ uint16_t padCnt;
+ /** List of pin configurations */
+ const GpioPinCnfMode_Type *padConfig;
+ const GpioPinOutLevel_Type *outConfig;
+ /** Total number of pin default levels */
+
+ uint16_t remapCount;
+ const uint32_t* remaps;
\r
-} Port_PortConfigType;\r
-\r
-/** Top level configuration container */\r
-/** @req PORT073 */\r
-typedef struct {\r
- uint16_t remapCount;\r
- const uint32_t* remaps;\r
-\r
- uint16_t portCount;\r
- const Port_PortConfigType* ports[];\r
} Port_ConfigType;\r
-\r
-/** Instance of the top level configuration container */\r
+
+/** Instance of the top level configuration container */
extern const Port_ConfigType PortConfigData;\r
\r
#endif /*PORT_CFG_H_*/\r
+/** @} */
/* TODO: Not threadsafe, add DisableAllInterrts()/EnableAllInterrupts() */
+CirqBufferType CirqBuffStatCreate(void *buffer, int maxCnt, size_t dataSize) {
+ CirqBufferType cirqbuffer;
+ cirqbuffer.bufStart = buffer;
+ cirqbuffer.maxCnt = maxCnt;
+ cirqbuffer.bufEnd = (char *)cirqbuffer.bufStart + dataSize*maxCnt;
+ cirqbuffer.head = cirqbuffer.bufStart;
+ cirqbuffer.tail = cirqbuffer.bufStart;
+ cirqbuffer.dataSize = dataSize;
+ cirqbuffer.currCnt = 0;
+ return cirqbuffer;
+}
-CirqBufferDynType *CirqBuffDynCreate( size_t size, size_t dataSize ) {
- CirqBufferDynType *cPtr;
- cPtr = malloc(sizeof(CirqBufferDynType));
+CirqBufferType *CirqBuffDynCreate( size_t size, size_t dataSize ) {
+ CirqBufferType *cPtr;
+ cPtr = malloc(sizeof(CirqBufferType));
if( cPtr == NULL ) {
return NULL;
}
return cPtr;
}
-int CirqBuffDynDestroy(CirqBufferDynType *cPtr ) {
+
+
+int CirqBuffDynDestroy(CirqBufferType *cPtr ) {
free(cPtr->bufStart);
free(cPtr);
return 0;
}
-int CirqBuffDynPush( CirqBufferDynType *cPtr, void *dataPtr ) {
+int CirqBuffPush( CirqBufferType *cPtr, void *dataPtr ) {
uint32_t flags;
Irq_Save(flags);
if( (cPtr->currCnt == cPtr->maxCnt) || (cPtr==NULL) ) {
return 0;
}
-int CirqBuffDynPop(CirqBufferDynType *cPtr, void *dataPtr ) {
+int CirqBuffPop(CirqBufferType *cPtr, void *dataPtr ) {
uint32_t flags;
Irq_Save(flags);
if( (cPtr->currCnt == 0) || (cPtr==NULL) ) {
return 0;
}
+
+
#ifdef _TEST_CIRQ_BUFFER_DYN_
int main( void ) {
- CirqBufferDynType *cPtr;
+ CirqBufferType *cPtr;
uint8_t *dataPtr;
int rv;
dataPtr = malloc(DATA_SIZE);
dataPtr[0] = 1;
- rv = CirqBuffDynPush(cPtr,dataPtr);
+ rv = CirqBuffPush(cPtr,dataPtr);
assert(rv == 0);
free(dataPtr);
dataPtr = malloc(DATA_SIZE);
dataPtr[0] = 2;
- rv = CirqBuffDynPush(cPtr,dataPtr);
+ rv = CirqBuffPush(cPtr,dataPtr);
assert(rv == 0);
free(dataPtr);
dataPtr = malloc(DATA_SIZE);
- rv = CirqBuffDynPop(cPtr,dataPtr);
+ rv = CirqBuffPop(cPtr,dataPtr);
assert( dataPtr[0] == 1);
assert(rv == 0);
free(dataPtr);
dataPtr = malloc(DATA_SIZE);
- rv = CirqBuffDynPop(cPtr,dataPtr);
+ rv = CirqBuffPop(cPtr,dataPtr);
assert( dataPtr[0] == 2);
assert(rv == 0);
free(dataPtr);
\r
#define FILE_RAMLOG 3\r
\r
+/* Location MUST match NoICE configuration */\r
+#ifdef USE_TTY_NOICE\r
+static volatile char VUART_TX __attribute__ ((section (".noice_port")));\r
+static volatile char VUART_RX __attribute__ ((section (".noice_port")));\r
+volatile unsigned char START_VUART = 0;\r
+#endif\r
+\r
/*\r
* T32 stuff\r
*/\r
(void)g_TRBuffer[0];\r
#endif\r
\r
+#ifdef USE_TTY_NOICE\r
+ // Not tested at all\r
+ int retval;\r
+ while (VUART_RX != 0)\r
+ {\r
+ }\r
+\r
+ retval = VUART_RX;\r
+ VUART_RX = 0;\r
+#endif\r
+\r
/* Only support write for now, return 0 read */\r
return 0;\r
}\r
\r
\r
if( fd <= STDERR_FILENO ) {\r
+#ifdef USE_TTY_NOICE\r
+ char *buf1 = (char *)_buf;\r
+ if (START_VUART)\r
+ {\r
+ for (int i = 0; i < nbytes; i++) {\r
+ char c = buf1[i];\r
+ if (c == '\n')\r
+ {\r
+ while (VUART_TX != 0)\r
+ {\r
+ }\r
+\r
+ VUART_TX = '\r';\r
+ }\r
+\r
+ while (VUART_TX != 0)\r
+ {\r
+ }\r
+\r
+ VUART_TX = c;\r
+ }\r
+ }\r
+#endif\r
+\r
#ifdef USE_TTY_WINIDEA\r
if (g_TConn)\r
{\r
\r
//#define HOST_TEST 1\r
\r
-int arc_putchar(int fd, int c);\r
+int arc_putchar(_PTR fd, int c);\r
int print(FILE *file, char **buffer, size_t n, const char *format, va_list ap);\r
\r
int printf(const char *format, ...) {\r
}\r
\r
/* Find flags */\r
- switch (ch) {\r
- case '0':\r
+ if (ch == '0')\r
+ {\r
flags = FL_ZERO;\r
- break;\r
- case ' ':\r
+ }\r
+ else if (ch == ' ')\r
+ {\r
flags = FL_SPACE;\r
- break;\r
- case '-':\r
+ }\r
+ else if (ch == '-')\r
+ {\r
flags = FL_ALIGN_LEFT;\r
- break;\r
- default:\r
+ }\r
+ else\r
+ {\r
/* Not supported or no flag */\r
flags = FL_NONE;\r
format--;\r
- break;\r
}\r
\r
ch = *format++;\r
}\r
\r
/* Find type */\r
- switch (ch) {\r
- case 'c':\r
+ if (ch =='c')\r
+ {\r
emitChar(file,buffer,(char )va_arg( ap, int ),&left);\r
- break;\r
- case 'd':\r
+ }\r
+ else if (ch == 'd')\r
+ {\r
flags |= FL_TYPE_SIGNED_INT;\r
emitInt(file,buffer,va_arg( ap, int ),10,width,flags,&left);\r
- break;\r
- case 'u':\r
+ }\r
+ else if (ch == 'u')\r
+ {\r
flags |= FL_TYPE_UNSIGNED_INT;\r
emitInt(file,buffer,va_arg( ap, int ),10,width,flags,&left);\r
- break;\r
- case 'x':\r
+ }\r
+ else if (ch == 'x')\r
+ {\r
flags |= FL_TYPE_UNSIGNED_INT;\r
emitInt(file,buffer,va_arg( ap, int ),16,width,flags,&left);\r
- break;\r
- case 'p':\r
+ }\r
+ else if (ch == 'p')\r
+ {\r
flags |= FL_TYPE_POINTER;\r
emitInt(file,buffer,va_arg( ap, int ),16,width,flags,&left);\r
- break;\r
- case 's':\r
+ }\r
+ else if (ch == 's')\r
+ {\r
str = (char *)va_arg( ap, int );\r
\r
if( str == NULL ) {\r
}\r
\r
emitString(file,buffer,str,width,flags,&left);\r
- break;\r
- default:\r
+ }\r
+ else\r
+ {\r
assert(0); // oops\r
- break;\r
}\r
-\r
} else {\r
flags = FL_NONE;\r
emitChar(file,buffer,ch,&left);\r
return E_OK;\r
}\r
\r
+char tmp_stream[200] = "";\r
uint16_t handle_StreamsCommand(TCF_Command* command, char* buf) {\r
- char tmp[200] = "";\r
TCF_Streams_Command streams_cmd;\r
\r
/* Start building return message */\r
}\r
\r
/* Add data field */\r
- strcat(buf, JSON_Stringify);\r
- int len = TCF_TTY_ReadString(tmp, 199);\r
- tmp[len] = '\0'; /* Terminate to be sure */\r
- strcat(buf, tmp);\r
- strcat(buf, JSON_Stringify);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_Stringify);\r
+ int len = TCF_TTY_ReadString(tmp_stream, 199);\r
+ if(len >= 200){\r
+ return 0;\r
+ }\r
+ tmp_stream[len] = '\0'; /* Terminate to be sure */\r
+ mystrcat(buf, tmp_stream);\r
+ mystrcat(buf, JSON_Stringify);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
- //strcat(buf, Streams_LostSize);\r
- ultoa(0,tmp,10);\r
- strcat(buf,tmp);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ //mystrcat(buf, Streams_LostSize);\r
+ ultoa(0,tmp_stream,10);\r
+ mystrcat(buf,tmp_stream);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
- //strcat(buf, Streams_EOS);\r
- strcat(buf, Streams_false);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ //mystrcat(buf, Streams_EOS);\r
+ mystrcat(buf, Streams_false);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
} else if (strcmp(command->commandName, Streams_Write) == 0) {\r
/* C \95 <token> \95 Streams \95 write \95 <string: stream ID> \95 <int: size> \95 <string: data> \95 */\r
/* R \95 <token> \95 <error report> */\r
}\r
\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
} else if (strcmp(command->commandName, Streams_Subscribe) == 0) {\r
/* R \95 <token> \95 <error report> */\r
if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
return 0;\r
}\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
}else if (strcmp(command->commandName, Streams_Unsubscribe) == 0) {\r
/* R \95 <token> \95 <error report> */\r
if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
return 0;\r
}\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
}else if (strcmp(command->commandName, Streams_Connect) == 0) {\r
/* R \95 <token> \95 <error report> */\r
if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
return 0;\r
}\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
}else if (strcmp(command->commandName, Streams_Disconnect) == 0) {\r
/* R \95 <token> \95 <error report> */\r
if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
return 0;\r
}\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
}\r
\r
convert_to_tcf_message(buf);\r
switch(state)\r
{\r
case ST_READY:\r
- strcat(buf,"\"D\"");\r
+ mystrcat(buf,"\"D\"");\r
break;\r
case ST_WAITING:\r
- strcat(buf,"\"S\"");\r
+ mystrcat(buf,"\"S\"");\r
break;\r
case ST_SUSPENDED:\r
- strcat(buf,"\"T\"");\r
+ mystrcat(buf,"\"T\"");\r
break;\r
case ST_RUNNING:\r
- strcat(buf,"\"R\"");\r
+ mystrcat(buf,"\"R\"");\r
break;\r
case ST_NOT_STARTED:\r
- strcat(buf,"\"T\"");\r
+ mystrcat(buf,"\"T\"");\r
break;\r
}\r
}\r
boolean first = TRUE;\r
\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
/* Add data field */\r
- strcat(buf, JSON_ListStart);\r
+ mystrcat(buf, JSON_ListStart);\r
TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {\r
if(iterPcbPtr->proc_type < 4)\r
{\r
if(first){\r
first = FALSE;\r
}else{\r
- strcat(buf, JSON_Separator);\r
+ mystrcat(buf, JSON_Separator);\r
}\r
- strcat(buf, JSON_Stringify);\r
- strcat(buf, iterPcbPtr->name);\r
- strcat(buf, JSON_Stringify);\r
+ mystrcat(buf, JSON_Stringify);\r
+ mystrcat(buf, iterPcbPtr->name);\r
+ mystrcat(buf, JSON_Stringify);\r
}\r
}\r
- strcat(buf, JSON_ListEnd);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_ListEnd);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
} else if (strcmp(command->commandName, TCF_getContext) == 0) {\r
char tmp[20] = "";\r
\r
/* Add error field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
/* Add data field */\r
char *arg = command->arguments + 1; /* add 1 for " */\r
break;\r
}\r
}\r
- strcat(buf, JSON_ObjStart);\r
- strcat(buf, TCF_ID);\r
- strcat(buf, command->arguments);\r
+ mystrcat(buf, JSON_ObjStart);\r
+ mystrcat(buf, TCF_ID);\r
+ mystrcat(buf, command->arguments);\r
\r
- strcat(buf, JSON_Separator);\r
- strcat(buf, TCF_File);\r
- strcat(buf, command->arguments);\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, TCF_File);\r
+ mystrcat(buf, command->arguments);\r
\r
- strcat(buf, JSON_Separator);\r
- strcat(buf, SysMon_PID);\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_PID);\r
ultoa(iterPcbPtr->pid,tmp,10);\r
- strcat(buf, tmp);\r
+ mystrcat(buf, tmp);\r
\r
- strcat(buf, JSON_Separator);\r
- strcat(buf, SysMon_Prio);\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Prio);\r
ultoa(iterPcbPtr->prio,tmp,10);\r
- strcat(buf, tmp);\r
+ mystrcat(buf, tmp);\r
\r
- strcat(buf, JSON_Separator);\r
- strcat(buf, SysMon_Stackstart);\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Stackstart);\r
ultoa((uint32_t)iterPcbPtr->stack.top,tmp,10);\r
- strcat(buf, tmp);\r
+ mystrcat(buf, tmp);\r
\r
-/* strcat(buf, JSON_Separator);\r
- strcat(buf, SysMon_Stackend);\r
+/* mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Stackend);\r
ultoa((uint32_t)iterPcbPtr->stack.top + iterPcbPtr->stack.size,tmp,10);\r
- strcat(buf, tmp);\r
+ mystrcat(buf, tmp);\r
\r
- strcat(buf, JSON_Separator);\r
- strcat(buf, SysMon_Stackcurr);\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Stackcurr);\r
ultoa((uint32_t)iterPcbPtr->stack.curr,tmp,10);\r
- strcat(buf, tmp);\r
+ mystrcat(buf, tmp);\r
*/\r
- strcat(buf, JSON_Separator);\r
- strcat(buf, SysMon_State);\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_State);\r
AddState(buf,iterPcbPtr->state);\r
\r
- strcat(buf, JSON_ObjEnd);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_ObjEnd);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
}\r
\r
convert_to_tcf_message(buf);\r
int num;\r
};\r
\r
+char *mystrcat(char *s1, const char *s2)\r
+{\r
+ char *s;\r
+\r
+ for(s = s1;*s;++s)\r
+ ;\r
+\r
+ while(*s2)\r
+ *s++ = *s2++;\r
+ *s = '\0';\r
+\r
+ return s1;\r
+}\r
+\r
+\r
uint16_t message_length(const char* msg, uint16_t max_length) {\r
uint16_t i;\r
for (i = 0; i < max_length; ++i) {\r
\r
void start_tcf_field(char* start, char* field) {\r
strcpy(start, field);\r
- strcat(start, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(start, TCF_S_EOFIELD_MARKER);\r
}\r
\r
void append_tcf_field(char* start, char* field) {\r
- strcat(start, field);\r
- strcat(start, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(start, field);\r
+ mystrcat(start, TCF_S_EOFIELD_MARKER);\r
}\r
\r
void convert_to_tcf_message(char* start) {\r
- strcat(start, TCF_S_EOM);\r
+ mystrcat(start, TCF_S_EOM);\r
size_t length = strlen(start);\r
int i;\r
for (i = 0; i < length; ++i) {\r
append_tcf_field(buf, command->token); /* Token */\r
\r
/* Add error field */\r
- strcat(buf, JSON_ObjStart);\r
+ mystrcat(buf, JSON_ObjStart);\r
\r
- strcat(buf, TCF_Code);\r
+ mystrcat(buf, TCF_Code);\r
ultoa(TCF_UNSUPPORTED,tmp,10);\r
- strcat(buf, tmp);\r
+ mystrcat(buf, tmp);\r
\r
- strcat(buf, JSON_ObjEnd);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_ObjEnd);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
/* Add data field */\r
- strcat(buf, JSON_null);\r
- strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
\r
convert_to_tcf_message(buf);\r
uint16_t len = message_length(buf, TCF_MAX_FIELD_LENGTH);\r
}\r
\r
/* Not reentrant so buffers can be static */\r
-static char outbuf[TCF_MAX_FIELD_LENGTH] = "";\r
+char outbuf[TCF_MAX_FIELD_LENGTH] = "";\r
\r
static void handle_event(char *buf, uint16_t len)\r
{\r
\r
static void handle_incoming(const void* buf, uint16_t len) {\r
char *msg = (char *)buf;\r
-\r
if(len > 0){\r
do{\r
- char c = msg[0];\r
- if (c == 'C') {\r
+ if ((msg[0] == 'C') && (msg[1] == '\0')) {\r
handle_command(msg, len);\r
- } else if (c == 'E') {\r
+ } else if ((msg[0] == 'E') && (msg[1] == '\0')) {\r
handle_event(msg, len);\r
- }\r
+ }else{\r
+ len=0;\r
+ }\r
\r
/* Check if more than one message in buffer */\r
- msg = get_next_tcf_msg(msg, &len);\r
+ if(len > 0){\r
+ msg = get_next_tcf_msg(msg, &len);\r
+ }\r
}while((msg != NULL) && (len > 0));\r
}\r
}\r
uint16_t handle_FileSystemCommand(TCF_Command* command, char* buf);\r
uint16_t handle_FileSystemEvent(TCF_Event* event, char* buf);\r
\r
+char *mystrcat(char *s1, const char *s2);\r
+\r
#endif /* TCF_H_ */\r
void StartupHook( void ) {\r
LDEBUG_PRINTF("## StartupHook\n");\r
\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
+// uint32_t sys_freq = McuE_GetSystemClock();\r
\r
LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
}\r
#elif defined(CFG_BRD_MPC5567QRTECH)\r
#define LED_CHANNEL DIO_CHANNEL_NAME_LED_K2\r
\r
+#elif defined(CFG_BRD_HCS12X_ELMICRO_TBOARD)\r
+#define LED_CHANNEL DIO_CHANNEL_NAME_DO_PB0\r
+\r
+#elif defined(CFG_BRD_STM32_STM3210C)\r
+#define LED_CHANNEL LED_CHANNEL1\r
+\r
+#elif defined(CFG_BRD_STM32_MCBSTM32)\r
+#define LED_CHANNEL LED_CHANNEL1\r
+\r
#else\r
#warning "Unknown board or CFG_BRD_* undefined"\r
\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
#include "Os.h"\r
-#include "os_config_macros.h"\r
\r
#include "EcuM.h"\r
-#include <stdio.h>\r
-#include <assert.h>\r
#include "blinker_main.h"\r
#include "debug.h"\r
-#include "WdgM.h"\r
\r
\r
void OsIdle( void ) {\r
\r
void bTask10( void ) {\r
\r
- WdgM_MainFunction_Trigger();\r
-\r
TerminateTask();\r
}\r
\r
*/\r
void bTask25( void ) {\r
\r
- WdgM_UpdateAliveCounter(WDBG_ALIVE_LOOP_BLINK_COMPONENT);\r
blinker_component_main();\r
\r
TerminateTask();\r
\r
void bTask100( void ) {\r
\r
- WdgM_MainFunction_AliveSupervision();\r
-\r
TerminateTask();\r
}\r
/*\r
SetRelAlarm(ALARM_ID_alarm25, 25, 25); // ADC data acquisition\r
SetRelAlarm(ALARM_ID_alarm100, 100, 100); // ADC data acquisition\r
\r
- WdgM_ActivateAliveSupervision(WDBG_ALIVE_LOOP_BLINK_COMPONENT);\r
-\r
// End of startup_task().\r
TerminateTask();\r
}\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="b715bb9d-eec4-4ac5-acdb-a63c2c5c7b2f">\r
- <SHORT-NAME>blinker_node</SHORT-NAME>\r
+ <SHORT-NAME>blinker_node_hcs12</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<ELEMENTS>\r
<ECU-CONFIGURATION UUID="194b9abc-510c-4b5e-8486-65c5b26772af">\r
- <SHORT-NAME>blinker_node</SHORT-NAME>\r
+ <SHORT-NAME>blinker_node_hcs12</SHORT-NAME>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
<MODULE-REFS>\r
- <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_hcs12/Os</MODULE-REF>\r
</MODULE-REFS>\r
</ECU-CONFIGURATION>\r
- <MODULE-CONFIGURATION UUID="3633db49-329b-4569-8ee7-a7795b97cfb3">\r
+ <MODULE-CONFIGURATION UUID="4fe46a12-0672-428f-99e3-c4ca6570a776">\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
- <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
<DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
<CONTAINERS>\r
- <CONTAINER UUID="22a1bd13-4119-4c40-84a1-bf19c3b548e4">\r
+ <CONTAINER UUID="80853be9-55dc-435f-95ed-9a1c90750299">\r
<SHORT-NAME>OsOS</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
<PARAMETER-VALUES>\r
</INTEGER-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
- <VALUE>2048</VALUE>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
</INTEGER-VALUE>\r
<BOOLEAN-VALUE>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
- <VALUE>true</VALUE>\r
+ <VALUE>false</VALUE>\r
</BOOLEAN-VALUE>\r
<BOOLEAN-VALUE>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
</BOOLEAN-VALUE>\r
</PARAMETER-VALUES>\r
<SUB-CONTAINERS>\r
- <CONTAINER UUID="1e94709e-d025-4e1a-9fd9-bb0092b52ac2">\r
+ <CONTAINER UUID="7f1dfe11-aeff-4131-89a9-2fbe9a87f01f">\r
<SHORT-NAME>OsHooks</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
<PARAMETER-VALUES>\r
</CONTAINER>\r
</SUB-CONTAINERS>\r
</CONTAINER>\r
- <CONTAINER UUID="8dd8fa9c-8203-48d9-b607-dbf36364f60e">\r
+ <CONTAINER UUID="77224460-9071-4c32-9ba5-5ee19d0a5be2">\r
+ <SHORT-NAME>alarm25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_hcs12/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="28398b0a-02ef-4aa0-9f06-90c0683ad934">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_hcs12/Os/bTask25</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b4e4c707-af7c-4d9f-a156-1507283b4ebe">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="44a8dc3f-2e97-4bb7-8139-57852146269a">\r
<SHORT-NAME>bTask25</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
<PARAMETER-VALUES>\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
- <VALUE>2048</VALUE>\r
+ <VALUE>512</VALUE>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
</ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
- <CONTAINER UUID="e33395cc-d24f-4396-9143-dc526ab1be98">\r
+ <CONTAINER UUID="f9e78da1-ee81-40a0-940b-3e04d9e9034c">\r
<SHORT-NAME>bTask100</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
<PARAMETER-VALUES>\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
- <VALUE>2048</VALUE>\r
+ <VALUE>512</VALUE>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
</ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
- <CONTAINER UUID="f18ef7d7-7fb4-40f9-95fa-a04be86a9935">\r
+ <CONTAINER UUID="157c6a3d-f8ad-4493-9d76-a8f9411066aa">\r
<SHORT-NAME>bTask10</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
<PARAMETER-VALUES>\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
- <VALUE>2048</VALUE>\r
+ <VALUE>512</VALUE>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
</ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
- <CONTAINER UUID="ce065515-397f-4172-8266-8eb9b51ac4df">\r
+ <CONTAINER UUID="ace8439e-ddb7-4bd7-b9e5-643a759f3e55">\r
<SHORT-NAME>Startup</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
<PARAMETER-VALUES>\r
</INTEGER-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
- <VALUE>1</VALUE>\r
+ <VALUE>2</VALUE>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
- <VALUE>2048</VALUE>\r
+ <VALUE>256</VALUE>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
</ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
<SUB-CONTAINERS>\r
- <CONTAINER UUID="9f004177-c0ab-444e-808f-afc44e967fd2">\r
+ <CONTAINER UUID="40214336-c4be-4506-8ccc-75ff014f39fe">\r
<SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
</CONTAINER>\r
</SUB-CONTAINERS>\r
</CONTAINER>\r
- <CONTAINER UUID="f88f6c29-cbd6-469a-9c23-1a574adcce63">\r
- <SHORT-NAME>OsTick</SHORT-NAME>\r
- <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
- <PARAMETER-VALUES>\r
- <INTEGER-VALUE>\r
- <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
- <VALUE>65535</VALUE>\r
- </INTEGER-VALUE>\r
- <INTEGER-VALUE>\r
- <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
- <VALUE>0</VALUE>\r
- </INTEGER-VALUE>\r
- <INTEGER-VALUE>\r
- <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
- <VALUE>0</VALUE>\r
- </INTEGER-VALUE>\r
- <ENUMERATION-VALUE>\r
- <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
- <VALUE>OS-TICK</VALUE>\r
- </ENUMERATION-VALUE>\r
- </PARAMETER-VALUES>\r
- </CONTAINER>\r
- <CONTAINER UUID="b19901ff-471a-46bd-95b7-27d01a84d72e">\r
- <SHORT-NAME>alarm25</SHORT-NAME>\r
- <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
- <REFERENCE-VALUES>\r
- <REFERENCE-VALUE>\r
- <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
- <VALUE-REF DEST="CONTAINER">/blinker_node/Os/OsTick</VALUE-REF>\r
- </REFERENCE-VALUE>\r
- </REFERENCE-VALUES>\r
- <SUB-CONTAINERS>\r
- <CONTAINER UUID="d2b4563e-166d-425e-ad2f-9002b3709aaf">\r
- <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
- <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
- <REFERENCE-VALUES>\r
- <REFERENCE-VALUE>\r
- <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
- <VALUE-REF DEST="CONTAINER">/blinker_node/Os/bTask25</VALUE-REF>\r
- </REFERENCE-VALUE>\r
- </REFERENCE-VALUES>\r
- </CONTAINER>\r
- </SUB-CONTAINERS>\r
- </CONTAINER>\r
- <CONTAINER UUID="84cfef77-eaad-4c89-a71a-69960ec6d89c">\r
+ <CONTAINER UUID="08cf618f-ebe2-483c-8ba5-fde04f3c6160">\r
<SHORT-NAME>alarm10</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
<REFERENCE-VALUES>\r
<REFERENCE-VALUE>\r
<DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
- <VALUE-REF DEST="CONTAINER">/blinker_node/Os/OsTick</VALUE-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_hcs12/Os/OsTick</VALUE-REF>\r
</REFERENCE-VALUE>\r
</REFERENCE-VALUES>\r
<SUB-CONTAINERS>\r
- <CONTAINER UUID="93b42d8b-fcb7-4829-87c5-2fc9abdff68c">\r
+ <CONTAINER UUID="8a235c19-4b95-4bf1-a309-f15916dd2d8d">\r
<SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
<REFERENCE-VALUES>\r
<REFERENCE-VALUE>\r
<DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
- <VALUE-REF DEST="CONTAINER">/blinker_node/Os/bTask10</VALUE-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_hcs12/Os/bTask10</VALUE-REF>\r
</REFERENCE-VALUE>\r
</REFERENCE-VALUES>\r
</CONTAINER>\r
</SUB-CONTAINERS>\r
</CONTAINER>\r
- <CONTAINER UUID="8400ccd3-846f-4ec8-ab24-a8049347b3ac">\r
+ <CONTAINER UUID="0f791241-110b-4cac-9e54-b41ad56c7f05">\r
<SHORT-NAME>alarm100</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
<REFERENCE-VALUES>\r
<REFERENCE-VALUE>\r
<DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
- <VALUE-REF DEST="CONTAINER">/blinker_node/Os/OsTick</VALUE-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_hcs12/Os/OsTick</VALUE-REF>\r
</REFERENCE-VALUE>\r
</REFERENCE-VALUES>\r
<SUB-CONTAINERS>\r
- <CONTAINER UUID="975669f6-7d28-46a6-8186-bd9ac973196e">\r
+ <CONTAINER UUID="3eb17f20-d68e-4d62-87e3-6775933e93a2">\r
<SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
<REFERENCE-VALUES>\r
<REFERENCE-VALUE>\r
<DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
- <VALUE-REF DEST="CONTAINER">/blinker_node/Os/bTask100</VALUE-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_hcs12/Os/bTask100</VALUE-REF>\r
</REFERENCE-VALUE>\r
</REFERENCE-VALUES>\r
</CONTAINER>\r
</MODULE-CONFIGURATION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="b715bb9d-eec4-4ac5-acdb-a63c2c5c7b2f">\r
<SHORT-NAME>blinker_node_ppc</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<ELEMENTS>\r
<ECU-CONFIGURATION UUID="194b9abc-510c-4b5e-8486-65c5b26772af">\r
- <SHORT-NAME>blinker_node_ppc</SHORT-NAME>\r
+ <SHORT-NAME>blinker_node_hcs12</SHORT-NAME>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
</MODULE-CONFIGURATION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=ECUM KERNEL MCU WDG WDGM PORT DIO DET\r
+MOD_USE+=ECUM KERNEL MCU PORT DIO DET\r
\r
SELECT_CONSOLE = RAMLOG\r
SELECT_OS_CONSOLE = RAMLOG\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#include "WdgM_Cfg.h"\r
-\r
-Wdgm_SupervisionType Wdgm_Supervision[WDBG_NBR_OF_ALIVE_SIGNALS];\r
-\r
-\r
-const WdgM_SupervisedEntityType WdgM_SupervisedEntity [WDBG_NBR_OF_ALIVE_SIGNALS] =\r
-{\r
- {\r
- .WdgM_SupervisedEntityID = WDBG_ALIVE_LOOP_BLINK_COMPONENT,\r
- .WdgM_ActivationStatus = WDBG_SUPERVISION_DISABLED,\r
- .WdgM_ExpectedAliveIndications = 4,\r
- .WdgM_SupervisionReferenceCycle = 1,\r
- .WdgM_FailedSupervisionReferenceCycleTolerance = 1,\r
- .WdgM_MinMargin = 1,\r
- .WdgM_MaxMargin = 1\r
- },\r
-};\r
-\r
-const WdgM_ConfigType WdgMAliveSupervision =\r
-{\r
- .WdgM_SupervisionCycle = 1,\r
- .WdgM_NumberOfSupervisedEntities = WDBG_NBR_OF_ALIVE_SIGNALS,\r
- .WdgM_ExpiredSupervisionCycleTolerance = 1,\r
- .WdgM_SupervisedEntityPtr = WdgM_SupervisedEntity,\r
- .Wdgm_SupervisionPtr = Wdgm_Supervision\r
-};\r
-\r
-\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:08:51 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,256);\r
+DECLARE_STACK(bTask10,512);\r
+DECLARE_STACK(bTask100,512);\r
+DECLARE_STACK(bTask25,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:08:51 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000
\ No newline at end of file
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 10:51:58 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:20 CET 2010\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 10:51:58 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:20 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:36 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,2048);\r
+DECLARE_STACK(bTask10,2048);\r
+DECLARE_STACK(bTask100,2048);\r
+DECLARE_STACK(bTask25,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:36 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:20 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,2048);\r
+DECLARE_STACK(bTask10,2048);\r
+DECLARE_STACK(bTask100,2048);\r
+DECLARE_STACK(bTask25,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:20 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 1024\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:20 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,2048);\r
+DECLARE_STACK(bTask10,2048);\r
+DECLARE_STACK(bTask100,2048);\r
+DECLARE_STACK(bTask25,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 24 20:34:20 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Nov 12 16:40:24 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,512);\r
+DECLARE_STACK(etask_1,512);\r
+DECLARE_STACK(etask_2,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/* \r
+* Configuration of module Os (Os_Cfg.h)\r
+* \r
+* Created by: ArcCore AB\r
+* Configured for (MCU): Undefined MCU\r
+* \r
+* Module editor vendor: ArcCore\r
+* Module editor version: 2.0.7\r
+* \r
+* Copyright ArcCore AB 2010\r
+* Generated by Arctic Studio (http://arccore.com)\r
+* on Mon May 03 11:25:22 CEST 2010\r
+*/\r
+\r
+\r
+#if (OS_SW_MAJOR_VERSION != 2) \r
+#error "Os: Configuration file version differs from BSW version."\r
+#endif\r
+\r
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 200\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000
\ No newline at end of file
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:52:29 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:52:29 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
\r
\r
/*\r
- * WdgM_Lcfg.h\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
*\r
- * Created on: 2009-jul-22\r
- * Author: rosa\r
*/\r
+#ifndef _DET_CFG_H_\r
+#define _DET_CFG_H_\r
+\r
+#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
\r
-#ifndef WDGM_LCFG_H_\r
-#define WDGM_LCFG_H_\r
+#define DET_DEINIT_API STD_ON // Enable/Disable the Det_DeInit function\r
\r
-typedef enum\r
-{\r
- WDBG_ALIVE_LOOP_BLINK_COMPONENT,\r
- WDBG_NBR_OF_ALIVE_SIGNALS\r
-}WdgM_SupervisedEntityIdType;\r
+#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
\r
-#endif /* WDGM_LCFG_H_ */\r
+#endif /*_DET_CFG_H_*/\r
--- /dev/null
+/* \r
+* Configuration of module Os (Os_Cfg.c)\r
+* \r
+* Created by: ArcCore AB\r
+* Configured for (MCU): Undefined MCU\r
+* \r
+* Module editor vendor: ArcCore\r
+* Module editor version: 2.0.7\r
+* \r
+* Copyright ArcCore AB 2010\r
+* Generated by Arctic Studio (http://arccore.com)\r
+* on Mon May 03 11:28:16 CEST 2010\r
+*/\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE( \r
+ RES_SCHEDULER,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,512);\r
+DECLARE_STACK(etask_1,512);\r
+DECLARE_STACK(etask_2,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/* \r
+* Configuration of module Os (Os_Cfg.h)\r
+* \r
+* Created by: ArcCore AB\r
+* Configured for (MCU): Undefined MCU\r
+* \r
+* Module editor vendor: ArcCore\r
+* Module editor version: 2.0.7\r
+* \r
+* Copyright ArcCore AB 2010\r
+* Generated by Arctic Studio (http://arccore.com)\r
+* on Mon May 03 11:28:16 CEST 2010\r
+*/\r
+\r
+\r
+#if (OS_SW_MAJOR_VERSION != 2) \r
+#error "Os: Configuration file version differs from BSW version."\r
+#endif\r
+\r
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 200\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1400
\ No newline at end of file
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:51:31 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:51:31 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+#ifndef CALIBRATIONDATA_H_\r
+#define CALIBRATIONDATA_H_\r
+\r
+#include "Calibration_Settings.h"\r
+\r
+#ifdef CALIBRATION_ACTIVE\r
+/* Section data from linker script. */\r
+extern char __CALIB_RAM_START;\r
+extern char __CALIB_RAM_END;\r
+extern char __CALIB_ROM_START;\r
+#define ARC_DECLARE_CALIB(type, name) type __attribute__((section (".calibration"))) name\r
+#else\r
+#define ARC_DECLARE_CALIB(type, name) const type name\r
+#endif /* CALIBRATION_ACTIVE */\r
+\r
+\r
+\r
+#endif /* CALIBRATIONDATA_H_ */\r
\r
/** @name Service id's */\r
//@{\r
+#define ECUM_REQUESTRUN_ID (0x03)\r
+#define ECUM_RELEASERUN_ID (0x04)\r
+#define ECUM_SELECTSHUTDOWNTARGET_ID (0x06)\r
#define ECUM_GETSTATE_ID (0x07)\r
+#define ECUM_GETSHUTDOWNTARGET_ID (0x09)\r
+#define ECUM_COMM_REQUESTRUN_ID (0x0e)\r
+#define ECUM_REQUESTPOSTRUN_ID (0x0a)\r
+#define ECUM_RELEASEPOSTRUN_ID (0x0b)\r
#define ECUM_SELECTAPPMODE_ID (0x0f)\r
+#define ECUM_COMM_RELEASERUN_ID (0x10)\r
#define ECUM_GETAPPMODE_ID (0x11)\r
#define ECUM_SELECT_BOOTARGET_ID (0x12)\r
#define ECUM_GET_BOOTARGET_ID (0x13)\r
#define ECUM_MAINFUNCTION_ID (0x18)\r
+#define ECUM_COMM_HASREQUESTEDRUN_ID (0x1b)\r
\r
/** Possible states */\r
typedef enum {\r
//#include "Spi.h"\r
#include "Std_Types.h"\r
#include "Det.h"\r
-//#include "MemIf_Types.h"\r
+#include "MemIf_Types.h"\r
#if defined(USE_DEM)\r
#include "Dem.h"\r
#endif\r
MemIf_StatusType Fls_GetStatus( void );\r
#endif\r
\r
-#if ( FLS_GET_JOB_RESULT_API == STD_ON )\r
+#if ( 1 )\r
MemIf_JobResultType Fls_GetJobResult( void );\r
#endif\r
\r
# define Pwm_ReportError(ErrorId)\r
#endif\r
\r
+#if PWM_DEV_ERROR_DETECT==STD_ON\r
+# define Pwm_ReportError(ErrorId) Det_ReportError( MODULE_ID_PWM, 0, 0, ErrorId);\r
+#else\r
+# define Pwm_ReportError(ErrorId)\r
+#endif\r
+\r
/**************************************************************\r
* Type definitions\r
**************************************************************/\r
/* Buffer start/stop */
void *bufStart;
void *bufEnd;
-} CirqBufferDynType;
-
-CirqBufferDynType *CirqBuffDynCreate( size_t size, size_t dataSize );
-int CirqBuffDynDestroy(CirqBufferDynType *cPtr );
-int CirqBuffDynPush( CirqBufferDynType *cPtr, void *dataPtr );
-int CirqBuffDynPop(CirqBufferDynType *cPtr, void *dataPtr );
-
-/* TODO: Static implementation */
+} CirqBufferType;
+/* Dynamic implementation */
+CirqBufferType *CirqBuffDynCreate( size_t size, size_t dataSize );
+int CirqBuffDynDestroy(CirqBufferType *cPtr );
+/* Static implementation */
+CirqBufferType CirqBuffStatCreate(void *buffer, int maxCnt, size_t dataSize);
+int CirqBuffPush( CirqBufferType *cPtr, void *dataPtr );
+int CirqBuffPop(CirqBufferType *cPtr, void *dataPtr );
#endif /* CIRQ_BUFFER_H_ */
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
#ifndef _REGS_H_\r
#define _REGS_H_\r
\r
-#define IO_BASE 0\r
-\r
-#define ienable() __asm("cli");\r
-#define idisable() __asm("orcc #0x10")\r
-#define xenable() __asm("andcc #0xbf")\r
-#define xdisable()__asm("orcc #0x40")\r
-\r
-/**\r
- * constant offsets to use where a C expression doesn't work\r
- * You may use it with GEL\r
- */\r
-#define M6811_PORTA 0x00\r
-#define M6811_PORTB 0x01\r
-#define M6811_PTT 0x240\r
-#define M6811_PTM 0x250\r
-#define M6811_PTP 0x258\r
-#define M6811_PTH 0x260\r
-\r
-#define PORTIO_8 *(volatile unsigned char *)\r
-#define PORTIO_16 *(volatile unsigned short int *)\r
-\r
-\r
-/* \r
- * Core HC12 Registers\r
- */\r
-#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
-#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
-#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
-#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
-#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
-#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
-#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
-#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
-#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
-#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
-#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
-#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
-#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
-#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
-#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
-#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
-#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
-#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
-#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
-#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
-#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
-#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
-#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
-#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
-\r
-// Bitflags - PEAR\r
-#define NOACCE 0x80\r
-#define PIPOE 0x20\r
-#define NECLK 0x10\r
-#define LSTRE 0x08\r
-#define RDWE 0x04\r
-\r
-// INTCR bitflags\r
-#define IRQE 0x80\r
-#define IRQEN 0x40\r
-#define DLY 0x20\r
-\r
-// BKP Module\r
-#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
-#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
-#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
-#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
-#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
-#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
-\r
-// MEBI Module \r
-#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
-#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
-#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
-\r
-// CRG Module \r
-#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
-#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
-#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
-#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
-#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
-#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
-#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
-#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
-#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
-#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
-#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
-#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
-\r
-// CRG bitflags\r
-#define RTIF 0x80\r
-#define RTIE 0x80\r
-#define LOCK 0x08\r
-#define AUTO 0x20\r
-#define PLLSEL 0x80\r
-\r
-// COPCTL bitflags\r
-#define WCOP 0x80\r
-#define RSBCK 0x40\r
-\r
-// ECT Module\r
-#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
-#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
-#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
-#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
-#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
-#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
-#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
-#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
-#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
-#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
-#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
-#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
-#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
-#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
-#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
-#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
-#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
-#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
-#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
-#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
-#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
-#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
-#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
-#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
-#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
-#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
-#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
-#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
-#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
-#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
-#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
-#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
-#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
-#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
-#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
-#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
-#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
-#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
-#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
-#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
-#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
-#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
-#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
-#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
-#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
-#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
-#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
-\r
-#define TEN 0x80\r
-#define TSFRZ 0x20\r
-#define TOI 0x80\r
-#define MCZI 0x80\r
-#define MODMC 0x40\r
-#define MCEN 0x4\r
-#define MCPR1 0x2\r
-#define MCPR0 0x1\r
-\r
-#define MCPRE_VAL_1 0\r
-#define MCPRE_VAL_4 MCPR0\r
-#define MCPRE_VAL_8 MCPR1\r
-#define MCPRE_VAL_16 MCPR0 | MCPR1\r
-\r
-// ATD0 Module \r
-#define ATD0_BASE (IO_BASE + 0x80)\r
-#define ATD0CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D0 control register 0 */\r
-#define ATD0CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D0 control register 1 */\r
-#define ATD0CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D0 control register 2 */\r
-#define ATD0CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D0 control register 3 */\r
-#define ATD0CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D0 control register 4 */\r
-#define ATD0CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D0 control register 5 */\r
-#define ATD0STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D0 status register 0 */\r
-#define ATD0STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D0 status register 1 */\r
-#define ATD0TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D0 test register 0 */\r
-#define ATD0TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D0 test register 1 */\r
-#define ATD0DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D0 interrupt enable */\r
-#define PORTAD0 PORTIO_8(IO_BASE + 0x8f) /* port AD0 data input register */\r
-#define ATD0DR0 PORTIO_16(IO_BASE + 0x90) /* A/D0 result 0 */\r
-#define ATD0DR0H PORTIO_8(IO_BASE + 0x90) /* A/D0 result 0 */\r
-#define ATD0DR1 PORTIO_16(IO_BASE + 0x92) /* A/D0 result 1 */\r
-#define ATD0DR1H PORTIO_8(IO_BASE + 0x92) /* A/D0 result 1 */\r
-#define ATD0DR2 PORTIO_16(IO_BASE + 0x94) /* A/D0 result 2 */\r
-#define ATD0DR2H PORTIO_8(IO_BASE + 0x94) /* A/D0 result 2 */\r
-#define ATD0DR3 PORTIO_16(IO_BASE + 0x96) /* A/D0 result 3 */\r
-#define ATD0DR3H PORTIO_8(IO_BASE + 0x96) /* A/D0 result 3 */\r
-#define ATD0DR4 PORTIO_16(IO_BASE + 0x98) /* A/D0 result 4 */\r
-#define ATD0DR4H PORTIO_8(IO_BASE + 0x98) /* A/D0 result 4 */\r
-#define ATD0DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D0 result 5 */\r
-#define ATD0DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D0 result 5 */\r
-#define ATD0DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D0 result 6 */\r
-#define ATD0DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D0 result 6 */\r
-#define ATD0DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D0 result 7 */\r
-#define ATD0DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D0 result 7 */\r
-\r
-// ATDnCTL5 bitflags\r
-#define DJM 0x80\r
-#define DSGN 0x40\r
-#define SCAN 0x20\r
-#define MULT 0x10\r
-\r
-// ATDnSTAT0 bitflags\r
-#define SCF 0x80\r
-#define ETORF 0x20\r
-#define FIFOR 0x10\r
-\r
-// PWM Module \r
-#define PWME PORTIO_8(IO_BASE + 0xa0) /* PWM Enable */\r
-#define PWMPOL PORTIO_8(IO_BASE + 0xa1) /* PWM Clock Polarity */\r
-#define PWMCLK PORTIO_8(IO_BASE + 0xa2) /* PWM Clocks */\r
-#define PWMPRCLK PORTIO_8(IO_BASE + 0xa3) /* PWM prescale clock select */\r
-#define PWMCAE PORTIO_8(IO_BASE + 0xa4) /* PWM center align enable */\r
-#define PWMCTL PORTIO_8(IO_BASE + 0xa5) /* PWM Control Register */\r
-#define PWMTST PORTIO_8(IO_BASE + 0xa6) /* PWM Test Register */\r
-#define PWMPRSC PORTIO_8(IO_BASE + 0xa7) /* PWM Test Register */\r
-#define PWMSCLA PORTIO_8(IO_BASE + 0xa8) /* PWM scale A */\r
-#define PWMSCLB PORTIO_8(IO_BASE + 0xa9) /* PWM scale B */\r
-#define PWMSCNTA PORTIO_8(IO_BASE + 0xaa) /* PWM Test Register A */\r
-#define PWMSCNTB PORTIO_8(IO_BASE + 0xab) /* PWM Test Register B */\r
-#define PWMCNT0 PORTIO_8(IO_BASE + 0xac) /* PWM Channel Counter 0 */\r
-#define PWMCNT1 PORTIO_8(IO_BASE + 0xad) /* PWM Channel Counter 1 */\r
-#define PWMCNT2 PORTIO_8(IO_BASE + 0xae) /* PWM Channel Counter 2 */\r
-#define PWMCNT3 PORTIO_8(IO_BASE + 0xaf) /* PWM Channel Counter 3 */\r
-#define PWMCNT4 PORTIO_8(IO_BASE + 0xb0) /* PWM Channel Counter 4 */\r
-#define PWMCNT5 PORTIO_8(IO_BASE + 0xb1) /* PWM Channel Counter 5 */\r
-#define PWMCNT6 PORTIO_8(IO_BASE + 0xb2) /* PWM Channel Counter 6 */\r
-#define PWMCNT7 PORTIO_8(IO_BASE + 0xb3) /* PWM Channel Counter 7 */\r
-#define PWMPER0 PORTIO_8(IO_BASE + 0xb4) /* PWM Channel Period 0 */\r
-#define PWMPER1 PORTIO_8(IO_BASE + 0xb5) /* PWM Channel Period 1 */\r
-#define PWMPER2 PORTIO_8(IO_BASE + 0xb6) /* PWM Channel Period 2 */\r
-#define PWMPER3 PORTIO_8(IO_BASE + 0xb7) /* PWM Channel Period 3 */\r
-#define PWMPER4 PORTIO_8(IO_BASE + 0xb8) /* PWM Channel Period 4 */\r
-#define PWMPER5 PORTIO_8(IO_BASE + 0xb9) /* PWM Channel Period 5 */\r
-#define PWMPER6 PORTIO_8(IO_BASE + 0xba) /* PWM Channel Period 6 */\r
-#define PWMPER7 PORTIO_8(IO_BASE + 0xbb) /* PWM Channel Period 7 */\r
-#define PWMDTY0 PORTIO_8(IO_BASE + 0xbc) /* PWM Channel Duty 0 */\r
-#define PWMDTY1 PORTIO_8(IO_BASE + 0xbd) /* PWM Channel Duty 1 */\r
-#define PWMDTY2 PORTIO_8(IO_BASE + 0xbe) /* PWM Channel Duty 2 */\r
-#define PWMDTY3 PORTIO_8(IO_BASE + 0xbf) /* PWM Channel Duty 3 */\r
-#define PWMDTY4 PORTIO_8(IO_BASE + 0xc0) /* PWM Channel Duty 4 */\r
-#define PWMDTY5 PORTIO_8(IO_BASE + 0xc1) /* PWM Channel Duty 5 */\r
-#define PWMDTY6 PORTIO_8(IO_BASE + 0xc2) /* PWM Channel Duty 6 */\r
-#define PWMDTY7 PORTIO_8(IO_BASE + 0xc3) /* PWM Channel Duty 7 */\r
-#define PWMSDN PORTIO_8(IO_BASE + 0xc4) /* PWM shutdown register */\r
-\r
-#define PWMCNT01_16BIT PORTIO_16(IO_BASE + 0xac) /* pwm channel 0,1 counter, 16bit */\r
-#define PWMCNT23_16BIT PORTIO_16(IO_BASE + 0xae) /* pwm channel 2,3 counter, 16bit */\r
-#define PWMCNT45_16BIT PORTIO_16(IO_BASE + 0xb0) /* pwm channel 4,5 counter, 16bit */\r
-#define PWMCNT67_16BIT PORTIO_16(IO_BASE + 0xb2) /* pwm channel 6,7 counter, 16bit */\r
-#define PWMPER01_16BIT PORTIO_16(IO_BASE + 0xb4) /* pwm channel 0,1 period, 16bit */\r
-#define PWMPER23_16BIT PORTIO_16(IO_BASE + 0xb6) /* pwm channel 2,3 period, 16bit */\r
-#define PWMPER45_16BIT PORTIO_16(IO_BASE + 0xb8) /* pwm channel 4,5 period, 16bit */\r
-#define PWMPER67_16BIT PORTIO_16(IO_BASE + 0xba) /* pwm channel 6,7 period, 16bit */\r
-#define PWMDTY01_16BIT PORTIO_16(IO_BASE + 0xbc) /* pwm channel 0,1 duty cycle, 16bit */\r
-#define PWMDTY23_16BIT PORTIO_16(IO_BASE + 0xbe) /* pwm channel 2,3 duty cycle, 16bit */\r
-#define PWMDTY45_16BIT PORTIO_16(IO_BASE + 0xc0) /* pwm channel 4,5 duty cycle, 16bit */\r
-#define PWMDTY67_16BIT PORTIO_16(IO_BASE + 0xc2) /* pwm channel 6,7 duty cycle, 16bit */\r
-\r
-\r
-\r
-// SCI register offsets\r
-#define _SCIBD 0x0 /* SCI baud rate high */\r
-#define _SCIBDH 0x0 /* SCI baud rate high */\r
-#define _SCIBDL 0x1 /* SCI baud rate low */\r
-#define _SCICR1 0x2 /* SCI control register 1 */\r
-#define _SCICR2 0x3 /* SCI control register 2 */\r
-#define _SCISR1 0x4 /* SCI status register 1 */\r
-#define _SCISR2 0x5 /* SCI status register 2 */\r
-#define _SCIDRH 0x6 /* SCI data register high */\r
-#define _SCIDRL 0x7 /* SCI data register low */\r
-\r
-// SCI0 Module\r
-#define SCI0_BASE (IO_BASE + 0xc8)\r
-#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
-#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
-#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
-#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
-#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
-#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
-#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
-#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
-#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
-\r
-// SCI1 Module \r
-#define SCI1_BASE (IO_BASE + 0xd0)\r
-#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
-#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
-#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
-#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
-#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
-#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
-#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
-#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
-#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
-\r
-// SCInSR1\r
-#define TDRE 0x80\r
-#define RDRF 0x20\r
-#define IDLE 0x10\r
-\r
-// SPI register offsets\r
-#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
-#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
-#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
-#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
-#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
-\r
-// SPI0 Module \r
-#define SPI0_BASE (IO_BASE + 0xd8)\r
-#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
-#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
-#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
-#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
-#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
-\r
-// SPInCR1\r
-#define SPIE 0x80\r
-#define SPE 0x40\r
-#define SPTIE 0x20\r
-#define MSTR 0x10\r
-#define CPOL 0x08\r
-#define CPHA 0x04\r
-#define SSOE 0x02\r
-#define LSBFE 0x01\r
-\r
-// SPInSR\r
-#define SPIF 0x80\r
-#define SPTEF 0x20\r
-#define MODF 0x10\r
-\r
-// I2C Module \r
-#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
-#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
-#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
-#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
-#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
-\r
-// IBSR\r
-#define TCF 0x80\r
-#define IAAS 0x40\r
-#define IBB 0x20\r
-#define IBAL 0x10\r
-#define SRW 0x04\r
-#define IBIF 0x02\r
-#define RXAK 0x01\r
-\r
-// BDLC Module\r
-#define DLCBCR1 PORTIO_8(IO_BASE + 0xe8) /* BDLC control register 1 */\r
-#define DLCBSVR PORTIO_8(IO_BASE + 0xe9) /* BDLC state vector register */\r
-#define DLCBCR2 PORTIO_8(IO_BASE + 0xea) /* BDLC control register 2 */\r
-#define DLCBDR PORTIO_8(IO_BASE + 0xeb) /* BDLC data register */\r
-#define DLCBARD PORTIO_8(IO_BASE + 0xec) /* BDLC analog round trip delay */\r
-#define DLCBRSR PORTIO_8(IO_BASE + 0xed) /* BDLC rate select register */\r
-#define DLCSCR PORTIO_8(IO_BASE + 0xee) /* BDLC control register */\r
-#define DLCBSTAT PORTIO_8(IO_BASE + 0xef) /* BDLC status register */\r
-\r
-// SPI1 Module\r
-#define SPI1_BASE (IO_BASE + 0xf0)\r
-#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
-#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
-#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
-#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
-#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
-\r
-// SPI2 Module\r
-#define SPI2_BASE (IO_BASE + 0xf8)\r
-#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
-#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
-#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
-#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
-#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
-\r
-// FLC Module\r
-#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
-#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
-#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
-#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
-#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
-#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
-\r
-// EEPROM Module\r
-#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
-#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
-#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
-#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
-#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
-\r
-// ATD1 Module \r
-#define ATD1_BASE (IO_BASE + 0x120)\r
-#define ATD1CTL0 PORTIO_8(IO_BASE + 0x120) /* A/D1 control register 0 */\r
-#define ATD1CTL1 PORTIO_8(IO_BASE + 0x121) /* A/D1 control register 1 */\r
-#define ATD1CTL2 PORTIO_8(IO_BASE + 0x122) /* A/D1 control register 2 */\r
-#define ATD1CTL3 PORTIO_8(IO_BASE + 0x123) /* A/D1 control register 3 */\r
-#define ATD1CTL4 PORTIO_8(IO_BASE + 0x124) /* A/D1 control register 4 */\r
-#define ATD1CTL5 PORTIO_8(IO_BASE + 0x125) /* A/D1 control register 5 */\r
-#define ATD1STAT0 PORTIO_8(IO_BASE + 0x126) /* A/D1 status register 0 */\r
-#define ATD1STAT1 PORTIO_8(IO_BASE + 0x127) /* A/D1 status register 1 */\r
-#define ATD1TEST0 PORTIO_8(IO_BASE + 0x128) /* A/D1 test register 0 */\r
-#define ATD1TEST1 PORTIO_8(IO_BASE + 0x129) /* A/D1 test register 1 */\r
-#define ATD1DIEN PORTIO_8(IO_BASE + 0x12d) /* A/D1 interrupt enable */\r
-#define PORTAD1 PORTIO_8(IO_BASE + 0x12f) /* port AD1 data input register */\r
-#define ATD1DR0 PORTIO_16(IO_BASE + 0x130) /* A/D1 result 0 */\r
-#define ATD1DR0H PORTIO_8(IO_BASE + 0x130) /* A/D1 result 0 */\r
-#define ATD1DR1 PORTIO_16(IO_BASE + 0x132) /* A/D1 result 1 */\r
-#define ATD1DR1H PORTIO_8(IO_BASE + 0x132) /* A/D1 result 1 */\r
-#define ATD1DR2 PORTIO_16(IO_BASE + 0x134) /* A/D1 result 2 */\r
-#define ATD1DR2H PORTIO_8(IO_BASE + 0x134) /* A/D1 result 2 */\r
-#define ATD1DR3 PORTIO_16(IO_BASE + 0x136) /* A/D1 result 3 */\r
-#define ATD1DR3H PORTIO_8(IO_BASE + 0x136) /* A/D1 result 3 */\r
-#define ATD1DR4 PORTIO_16(IO_BASE + 0x138) /* A/D1 result 4 */\r
-#define ATD1DR4H PORTIO_8(IO_BASE + 0x138) /* A/D1 result 4 */\r
-#define ATD1DR5 PORTIO_16(IO_BASE + 0x13a) /* A/D1 result 5 */\r
-#define ATD1DR5H PORTIO_8(IO_BASE + 0x13a) /* A/D1 result 5 */\r
-#define ATD1DR6 PORTIO_16(IO_BASE + 0x13c) /* A/D1 result 6 */\r
-#define ATD1DR6H PORTIO_8(IO_BASE + 0x13c) /* A/D1 result 6 */\r
-#define ATD1DR7 PORTIO_16(IO_BASE + 0x13e) /* A/D1 result 7 */\r
-#define ATD1DR7H PORTIO_8(IO_BASE + 0x13e) /* A/D1 result 7 */\r
-\r
-// CAN0 Module \r
-#define CAN0_BASE (IO_BASE + 0x140)\r
-#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
-#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
-#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
-#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
-#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
-#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
-#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
-#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
-#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
-#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
-#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
-#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
-#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
-#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
-#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
-#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
-#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
-#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
-#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
-#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
-#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
-#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
-#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
-#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
-#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
-#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
-#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
-#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
-#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
-#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
-#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
-#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
-\r
-// CAN1 Module \r
-#define CAN1_BASE (IO_BASE + 0x180)\r
-#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
-#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
-#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
-#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
-#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
-#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
-#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
-#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
-#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
-#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
-#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
-#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
-#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
-#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
-#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
-#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
-#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
-#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
-#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
-#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
-#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
-#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
-#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
-#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
-#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
-#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
-#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
-#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
-#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
-#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
-#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
-#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
-\r
-// CAN2 Module \r
-#define CAN2_BASE (IO_BASE + 0x1c0)\r
-#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
-#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
-#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
-#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
-#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
-#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
-#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
-#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
-#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
-#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
-#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
-#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
-#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
-#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
-#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
-#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
-#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
-#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
-#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
-#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
-#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
-#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
-#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
-#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
-#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
-#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
-#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
-#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
-#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
-#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
-#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
-#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
-\r
-// CAN3 Module \r
-#define CAN3_BASE (IO_BASE + 0x200)\r
-#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
-#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
-#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
-#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
-#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
-#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
-#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
-#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
-#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
-#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
-#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
-#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
-#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
-#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
-#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
-#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
-#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
-#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
-#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
-#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
-#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
-#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
-#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
-#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
-#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
-#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
-#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
-#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
-#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
-#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
-#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
-#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
-\r
-\r
-// Port T register offsets\r
-#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
-#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
-#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
-#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
-#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
-#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
-\r
-// Port S\r
-#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
-#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
-#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
-#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
-#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
-#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
-#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
-\r
-// Port M\r
-#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
-#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
-#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
-#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
-#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
-#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
-#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
-\r
-#define MODDR PORTIO_8(IO_BASE + 0x257) /* Module routing register */\r
-\r
-// Port P\r
-#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
-#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
-#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
-#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
-#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
-#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
-#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
-#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
-\r
-// Port H\r
-#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
-#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
-#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
-#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
-#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
-#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
-#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
-#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
-\r
-// Port J\r
-#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
-#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
-#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
-#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
-#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
-#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
-#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
-#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
-\r
-\r
-\r
-// CAN4 Module \r
-#define CAN4_BASE (IO_BASE + 0x280)\r
-#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
-#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
-#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
-#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
-#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
-#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
-#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
-#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
-#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
-#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
-#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
-#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
-#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
-#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
-#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
-#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
-#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
-#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
-#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
-#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
-#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
-#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
-#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
-#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
-#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
-#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
-#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
-#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
-#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
-#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
-#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
-#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
-\r
-\r
-\r
-# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
-# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
-# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
-# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
-# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
-# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+#if defined(CFG_HCS12D)\r
+#include "regs_hcs12d.h"\r
+#elif defined(CFG_HCS12XD)\r
+#include "regs_hcs12xd.h"\r
+#else\r
+#error NO MCU SELECTED!!!!\r
+#endif\r
\r
#endif /* ifndef _REGS_H_ */\r
\r
#define SLEEP(_x_) \\r
do{ \\r
- uint32_t pval = McuE_EnterCriticalSection(); \\r
TaskType task; \\r
GetTaskID(&task); \\r
- Sleep(_x_, task, EVENT_MASK_EVENT_SLEEP_ALARM ); \\r
- McuE_ExitCriticalSection(pval); \\r
- WaitEvent(EVENT_MASK_EVENT_SLEEP_ALARM); \\r
- ClearEvent(EVENT_MASK_EVENT_SLEEP_ALARM); \\r
+ Sleep(_x_, task, EVENT_MASK_SLEEP_ALARM ); \\r
+ WaitEvent(EVENT_MASK_SLEEP_ALARM); \\r
+ ClearEvent(EVENT_MASK_SLEEP_ALARM); \\r
}while(0);\r
\r
void Sleep(uint32_t nofTicks, TaskType TaskID, EventMaskType Mask );\r
+void SleepInit();\r
\r
#endif /* SLEEP_H_ */\r
$(foreach mod,$(MOD_AVAIL),$(eval $(call MOD_AVAIL_template,${mod})))\r
$(foreach mod,$(MOD_USE),$(eval $(call MOD_USE_template,${mod})))\r
$(foreach mod,$(CFG),$(eval $(call CFG_template,${mod})))\r
-def-y += $(ARCH) $(ARCH_FAM) $(ARCH_MCU) \r
+#def-y += $(ARCH) $(ARCH_FAM) $(ARCH_MCU) \r
\r
# Select console / debug\r
$(foreach mod,$(SELECT_OS_CONSOLE),$(eval $(call MOD_USE_template,${mod})))\r
# Preprocess linker files..\r
%.ldp: %.ldf\r
@echo " >> CPP $<"\r
- $(Q)$(CPP) -E -P -x assembler-with-cpp -o $@ $(addprefix -I ,$(inc-y)) $<\r
+ $(Q)$(CPP) -E -P -x assembler-with-cpp -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
\r
# @cat $@ \r
\r
$(Q)$(CC) $(LDFLAGS) -o $@ $(libpath-y) $(obj-y) $(lib-y) $(libitem-y) \r
else \r
$(Q)$(LD) $(LDFLAGS) -T $(ldcmdfile-y) -o $@ $(libpath-y) --start-group $(obj-y) $(lib-y) $(libitem-y) --end-group $(LDMAPFILE)\r
-ifdef CFG_MC912DG128A\r
+ifdef CFG_HC1X\r
@$(CROSS_COMPILE)objdump -h $@ | gawk -f $(ROOTDIR)/scripts/hc1x_memory.awk\r
else\r
@echo "Image size: (decimal)"\r
#include "Mcu.h"\r
#include "Det.h"\r
#include "irq.h"\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+#include "Nvm.h"\r
+#endif\r
\r
EcuM_GobalType internal_data;\r
\r
\r
// Set default application mode\r
internal_data.app_mode = internal_data.config->EcuMDefaultAppMode;\r
+#if defined(USE_COMM)\r
+ internal_data.run_comm_requests = 0;\r
+#endif\r
+ internal_data.run_requests = 0;\r
+ internal_data.postrun_requests = 0;\r
\r
internal_data.initiated = TRUE;\r
\r
void EcuM_StartupTwo()\r
{\r
#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
- uint32 timer;\r
+ extern CounterType Os_Arc_OsTickCounter;\r
+ TickType tickTimerStart, tickTimer, tickTimerElapsed;\r
+ StatusType tickTimerStatus;\r
+ static NvM_RequestResultType readAllResult;\r
#endif\r
\r
internal_data.current_state = ECUM_STATE_STARTUP_TWO;\r
\r
#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
// Start timer to wait for NVM job to complete\r
- timer = Os_SysTickGetValue();\r
+ tickTimerStatus = GetCounterValue(Os_Arc_OsTickCounter , &tickTimerStart);\r
+ if (tickTimerStatus != E_OK) {\r
+ // TODO: Generate error?\r
+ }\r
#endif\r
\r
// Prepare the system to startup RTE\r
#endif\r
\r
#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
- // Wait for the NVM job to terminate\r
- while(Os_SysTickGetValue()-timer < internal_data.config.EcuMNvramReadAllTimeout)\r
- {\r
- //TODO\r
- }\r
+ // Wait for the NVM job (NvmReadAll) to terminate\r
+ do {\r
+ NvM_GetErrorStatus(0, &readAllResult); // Read the multiblock status\r
+ tickTimer = tickTimerStart; // Save this because the GetElapsedCounterValue() will destroy it.\r
+ tickTimerStatus = GetElapsedCounterValue(Os_Arc_OsTickCounter, &tickTimer, &tickTimerElapsed);\r
+ if (tickTimerStatus != E_OK) {\r
+ // TODO: Generate error?\r
+ }\r
+ } while( (readAllResult == NVM_REQ_PENDING) && (tickTimerElapsed < internal_data.config->EcuMNvramReadAllTimeout) );\r
#endif\r
\r
// Initialize drivers that need NVRAM data\r
\r
// Indicate mode change to RTE\r
// TODO\r
+\r
+ // If coming from startup sequence, enter Run mode\r
+// if (internal_data.current_state == ECUM_STATE_STARTUP_TWO)\r
+ EcuM_enter_run_mode();\r
+\r
}\r
\r
// Typically called from OS shutdown hook\r
\r
Std_ReturnType EcuM_GetState(EcuM_StateType* state)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (state == NULL)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETSTATE_ID, ECUM_E_NULL_POINTER);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(state != NULL, ECUM_GETSTATE_ID, ECUM_E_NULL_POINTER, E_NOT_OK);\r
\r
*state = internal_data.current_state;\r
\r
\r
Std_ReturnType EcuM_SelectApplicationMode(AppModeType appMode)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_SELECTAPPMODE_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_SELECTAPPMODE_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
\r
// TODO Save this application mode for next startup\r
\r
\r
Std_ReturnType EcuM_GetApplicationMode(AppModeType* appMode)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETAPPMODE_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-\r
- if (appMode == NULL)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETAPPMODE_ID, ECUM_E_NULL_POINTER);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_GETAPPMODE_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(appMode != NULL, ECUM_GETAPPMODE_ID, ECUM_E_NULL_POINTER, E_NOT_OK);\r
\r
*appMode = internal_data.app_mode;\r
\r
\r
Std_ReturnType EcuM_SelectBootTarget(EcuM_BootTargetType target)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_SELECT_BOOTARGET_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_SELECT_BOOTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
\r
// TODO Do something great here\r
\r
\r
Std_ReturnType EcuM_GetBootTarget(EcuM_BootTargetType* target)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GET_BOOTARGET_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-\r
- if (target == NULL)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GET_BOOTARGET_ID, ECUM_E_NULL_POINTER);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_GET_BOOTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(target != NULL, ECUM_GET_BOOTARGET_ID, ECUM_E_NULL_POINTER, E_NOT_OK);\r
\r
// TODO Return selected boot target here\r
\r
return E_NOT_OK;\r
}\r
+\r
+\r
+Std_ReturnType EcuM_SelectShutdownTarget(EcuM_StateType target, uint8 mode)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_SELECTSHUTDOWNTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV((target == ECUM_STATE_OFF) || (target == ECUM_STATE_RESET) || (target == ECUM_STATE_SLEEP), ECUM_SELECTSHUTDOWNTARGET_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.shutdown_target = target;\r
+ internal_data.shutdown_mode = mode;\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType EcuM_GetShutdownTarget(EcuM_StateType *shutdownTarget, uint8 *sleepMode)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_GETSHUTDOWNTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+\r
+ *shutdownTarget = internal_data.shutdown_target;\r
+ *sleepMode = internal_data.shutdown_mode;\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType EcuM_RequestRUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_REQUESTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_REQUESTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_requests |= (uint32)1 << user;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_ReleaseRUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_RELEASERUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_RELEASERUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_requests &= ~((uint32)1 << user);\r
+\r
+ return E_OK;\r
+}\r
+\r
+#if defined(USE_COMM)\r
+Std_ReturnType EcuM_ComM_RequestRUN(NetworkHandleType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_COMM_REQUESTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < 32, ECUM_COMM_REQUESTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_comm_requests |= (uint32)1 << user;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_ComM_ReleaseRUN(NetworkHandleType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_COMM_RELEASERUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < 32, ECUM_COMM_RELEASERUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_comm_requests &= ~((uint32)1 << user);\r
+\r
+ return E_OK;\r
+}\r
+\r
+boolean EcuM_ComM_HasRequestedRUN(NetworkHandleType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_COMM_HASREQUESTEDRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < 32, ECUM_COMM_HASREQUESTEDRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ return (internal_data.run_comm_requests &((uint32)1 << user)) != 0;\r
+}\r
+#endif\r
+\r
+Std_ReturnType EcuM_RequestPOST_RUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_REQUESTPOSTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_REQUESTPOSTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.postrun_requests |= (uint32)1 << user;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_ReleasePOST_RUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_RELEASEPOSTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_RELEASEPOSTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.postrun_requests &= ~((uint32)1 << user);\r
+\r
+ return E_OK;\r
+}\r
+\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#include "EcuM.h"\r
-\r
-#if defined(USE_CANSM)\r
-extern const CanSM_ConfigType CanSM_Config;\r
-#endif\r
-#if defined(USE_COMM)\r
-extern const ComM_ConfigType ComM_Config;\r
-#endif\r
-#if defined(USE_NM)\r
-extern const Nm_ConfigType Nm_Config;\r
-#endif\r
-#if defined(USE_CANNM)\r
-extern const CanNm_ConfigType CanNm_Config;\r
-#endif\r
-\r
-EcuM_ConfigType EcuMConfig =\r
-{\r
- .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
- .EcuMDefaultShutdownMode = 0, // Don't care\r
- .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
-\r
-#if defined(USE_MCU)\r
- .McuConfig = McuConfigData,\r
-#endif\r
-#if defined(USE_PORT)\r
- .PortConfig = &PortConfigData,\r
-#endif\r
-#if defined(USE_CAN)\r
- .CanConfig = &CanConfigData,\r
-#endif\r
-#if defined(USE_CANIF)\r
- .CanIfConfig = &CanIf_Config,\r
-#endif\r
-#if defined(USE_CANSM)\r
- .CanSMConfig = &CanSM_Config,\r
-#endif\r
-#if defined(USE_CANNM)\r
- .CanNmConfig = &CanNm_Config,\r
-#endif\r
-#if defined(USE_COM)\r
- .ComConfig = &ComConfiguration,\r
-#endif\r
-#if defined(USE_COMM)\r
- .ComMConfig = &ComM_Config,\r
-#endif\r
-#if defined(USE_NM)\r
- .NmConfig = &Nm_Config,\r
-#endif\r
-#if defined(USE_PDUR)\r
- .PduRConfig = &PduR_Config,\r
-#endif\r
-#if defined(USE_DMA)\r
- .DmaConfig = DmaConfig,\r
-#endif\r
-#if defined(USE_ADC)\r
- .AdcConfig = AdcConfig,\r
-#endif\r
-#if defined(USE_PWM)\r
- .PwmConfig = &PwmConfig,\r
-#endif\r
-#if defined(USE_GPT)\r
- .GptConfig = GptConfigData,\r
-#endif\r
-};\r
-\r
-void EcuM_OnGoOffTwo( void ) {\r
-\r
-}\r
-\r
-void EcuM_AL_SwitchOff( void ) {\r
-\r
-}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
-\r
-#define ECUM_VERSION_INFO_API STD_ON\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-#define ECUM_DEV_ERROR_DETECT STD_ON\r
-\r
-#include "EcuM_Generated_Types.h"\r
-\r
-extern EcuM_ConfigType EcuMConfig;\r
-\r
-\r
-#endif /*ECUM_CFG_H_*/\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-#ifndef _ECUM_GENERATED_TYPES_H_\r
-#define _ECUM_GENERATED_TYPES_H_\r
-\r
-#if defined(USE_MCU)\r
-#include "Mcu.h"\r
-#endif\r
-#if defined(USE_PORT)\r
-#include "Port.h"\r
-#endif\r
-#if defined(USE_CAN)\r
-#include "Can.h"\r
-#endif\r
-#if defined(USE_CANIF)\r
-#include "CanIf.h"\r
-#endif\r
-#if defined(USE_PWM)\r
-#include "Pwm.h"\r
-#endif\r
-#if defined(USE_COM)\r
-#include "Com.h"\r
-#endif\r
-#if defined(USE_PDUR)\r
-#include "PduR.h"\r
-#endif\r
-#if defined(USE_DMA)\r
-#include "Dma.h"\r
-#endif\r
-#if defined(USE_ADC)\r
-#include "Adc.h"\r
-#endif\r
-#if defined(USE_GPT)\r
-#include "Gpt.h"\r
-#endif\r
-#if defined(USE_COMM)\r
-#include "ComM.h"\r
-#endif\r
-#if defined(USE_NM)\r
-#include "Nm.h"\r
-#endif\r
-#if defined(USE_CANNM)\r
-#include "CanNm.h"\r
-#endif\r
-#if defined(USE_CANSM)\r
-#include "CanSM.h"\r
-#endif\r
-#if defined(USE_LINSM)\r
-#include "LinSM.h"\r
-#endif\r
-\r
-typedef struct\r
-{\r
- EcuM_StateType EcuMDefaultShutdownTarget;\r
- uint8 EcuMDefaultShutdownMode;\r
- AppModeType EcuMDefaultAppMode;\r
-\r
-#if defined(USE_MCU)\r
- const Mcu_ConfigType* McuConfig;\r
-#endif\r
-#if defined(USE_PORT)\r
- const Port_ConfigType* PortConfig;\r
-#endif\r
-#if defined(USE_CAN)\r
- const Can_ConfigType* CanConfig;\r
-#endif\r
-#if defined(USE_CANIF)\r
- const CanIf_ConfigType* CanIfConfig;\r
-#endif\r
-#if defined(USE_CANSM)\r
- const CanSM_ConfigType* CanSMConfig;\r
-#endif\r
-#if defined(USE_NM)\r
- const Nm_ConfigType* NmConfig;\r
-#endif\r
-#if defined(USE_CANNM)\r
- const CanNm_ConfigType* CanNmConfig;\r
-#endif\r
-#if defined(USE_COMM)\r
- const ComM_ConfigType* ComMConfig;\r
-#endif\r
-#if defined(USE_COM)\r
- const Com_ConfigType* ComConfig;\r
-#endif\r
-#if defined(USE_PDUR)\r
- const PduR_PBConfigType* PduRConfig;\r
-#endif\r
-#if defined(USE_PWM)\r
- const Pwm_ConfigType* PwmConfig;\r
-#endif\r
-#if defined(USE_DMA)\r
- const Dma_ConfigType* DmaConfig;\r
-#endif\r
-#if defined(USE_ADC)\r
- const Adc_ConfigType* AdcConfig;\r
-#endif\r
-#if defined(USE_GPT)\r
- const Gpt_ConfigType* GptConfig;\r
-#endif\r
-} EcuM_ConfigType;\r
-\r
-#endif /*_ECUM_GENERATED_TYPES_H_*/\r
#ifndef _ECUM_INTERNALS_H_\r
#define _ECUM_INTERNALS_H_\r
\r
+#if ( ECUM_DEV_ERROR_DETECT == STD_ON )\r
+#include "Det.h"\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_ECUM, 0, _api, _err); \\r
+ }\r
+\r
+#define VALIDATE_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_ECUM, 0, _api, _err); \\r
+ return _rv; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_ECUM, 0, _api, _err); \\r
+ return; \\r
+ }\r
+#define DET_REPORTERROR(_module,_instance,_api,_err) Det_ReportError(_module,_instance,_api,_err)\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_RV(_exp,_api,_err,_rv )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_module,_instance,_api,_err)\r
+#endif\r
+\r
+\r
+\r
typedef struct\r
{\r
boolean initiated;\r
uint8 shutdown_mode;\r
AppModeType app_mode;\r
EcuM_StateType current_state;\r
+#if defined(USE_COMM)\r
+ uint32 run_comm_requests;\r
+#endif\r
+ uint32 run_requests;\r
+ uint32 postrun_requests;\r
} EcuM_GobalType;\r
\r
extern EcuM_GobalType internal_data;\r
\r
+void EcuM_enter_run_mode(void);\r
+\r
#endif /*_ECUM_INTERNALS_H_*/\r
\r
\r
#include "EcuM.h"\r
+#include "EcuM_Cbk.h"\r
#include "EcuM_Internals.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+#include "Nvm.h"\r
+#endif\r
+\r
+static uint32 internal_data_run_state_timeout = 0;\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+static uint32 internal_data_go_off_one_state_timeout = 0;\r
+#endif\r
+\r
+\r
+void EcuM_enter_run_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_APP_RUN;\r
+ EcuM_OnEnterRUN();\r
+ internal_data_run_state_timeout = internal_data.config->EcuMRunSelfRequestPeriod / ECUM_MAIN_FUNCTION_PERIOD;\r
+}\r
+\r
+static inline void enter_post_run_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_APP_POST_RUN;\r
+}\r
+\r
+static inline void enter_prep_shutdown_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_PREP_SHUTDOWN;\r
+ EcuM_OnPrepShutdown();\r
+}\r
+\r
+static inline void enter_go_sleep_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_GO_SLEEP;\r
+ void EcuM_OnGoSleep();\r
+}\r
+\r
+static inline void enter_go_off_one_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_GO_OFF_ONE;\r
+ EcuM_OnGoOffOne();\r
+\r
+#if defined(USE_COMM)\r
+ ComM_DeInit();\r
+#endif\r
+\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+\r
+ // Start NvM_WriteAll and timeout timer\r
+ NvM_WriteAll();\r
+\r
+ internal_data_go_off_one_state_timeout = internal_data.config->EcuMNvramWriteAllTimeout / ECUM_MAIN_FUNCTION_PERIOD;\r
+#endif\r
+}\r
+\r
+static inline boolean hasRunRequests(void)\r
+{\r
+ boolean result = internal_data.run_requests;\r
+\r
+#if defined(USE_COMM)\r
+ result |= internal_data.run_comm_requests;\r
+#endif\r
+\r
+ return (result != 0);\r
+}\r
+\r
+static inline boolean hasPostRunRequests(void)\r
+{\r
+ return (internal_data.postrun_requests != 0);\r
+}\r
\r
void EcuM_MainFunction(void)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data->initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_MAINFUNCTION_ID, ECUM_E_NOT_INITIATED);\r
- return;\r
- }\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+static NvM_RequestResultType writeAllResult;\r
#endif\r
\r
- // If coming from startup sequence, enter Run mode\r
- if (internal_data->current_state == ECUM_STATE_STARTUP_TWO)\r
- enter_run_mode();\r
+VALIDATE_NO_RV(internal_data.initiated, ECUM_MAINFUNCTION_ID, ECUM_E_NOT_INITIATED);\r
\r
- if (internal_data->current_state == ECUM_STATE_APP_RUN)\r
+ if (internal_data.current_state == ECUM_STATE_APP_RUN)\r
{\r
+ if (internal_data_run_state_timeout)\r
+ internal_data_run_state_timeout--;\r
+\r
if (!hasRunRequests() && (internal_data_run_state_timeout == 0))\r
{\r
+ EcuM_OnExitRun(); // ECUM_2865\r
enter_post_run_mode();\r
return;\r
}\r
}\r
\r
- if (internal_data->current_state == ECUM_STATE_APP_POST_RUN)\r
+ if (internal_data.current_state == ECUM_STATE_APP_POST_RUN)\r
{\r
if (hasRunRequests())\r
{\r
- enter_run_mode(); // ECUM_2866\r
+ EcuM_enter_run_mode(); // ECUM_2866\r
return;\r
}\r
\r
return;\r
}\r
}\r
+\r
+ if (internal_data.current_state == ECUM_STATE_PREP_SHUTDOWN)\r
+ {\r
+#if defined(USE_DEM)\r
+ // DEM shutdown\r
+ Dem_Shutdown();\r
+#endif\r
+\r
+ // Switch shutdown mode\r
+ if ((internal_data.shutdown_target == ECUM_STATE_OFF) || (internal_data.shutdown_target == ECUM_STATE_RESET)) {\r
+ enter_go_off_one_mode();\r
+ }\r
+\r
+ if (internal_data.shutdown_target == ECUM_STATE_SLEEP) {\r
+ enter_go_sleep_mode();\r
+ }\r
+ }\r
+\r
+ if (internal_data.current_state == ECUM_STATE_GO_OFF_ONE)\r
+ {\r
+#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+ if (internal_data_go_off_one_state_timeout)\r
+ internal_data_go_off_one_state_timeout--;\r
+\r
+ // Wait for the NVM job (NvmWriteAll) to terminate\r
+ NvM_GetErrorStatus(0, &writeAllResult);\r
+ if ((writeAllResult != NVM_REQ_PENDING) || (internal_data_go_off_one_state_timeout == 0))\r
+ {\r
+ ShutdownOS(E_OK);\r
+ }\r
+#else\r
+ ShutdownOS(E_OK);\r
+#endif\r
+ }\r
+\r
+ if (internal_data.current_state == ECUM_STATE_GO_SLEEP)\r
+ {\r
+ // TODO: Fill out\r
+ }\r
+\r
}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-/* Post Build time configuration */\r
-\r
-unsigned char ECUM_DEFAULT_APP_MODE = 0; \r
-unsigned char ECUM_DEFAULT_SHUTDOWN_TARGET = 0;\r
-unsigned char ECUM_RUN_SELF_REQUEST_PERIOD = 0;\r
\r
void OsTick( void );\r
\r
+#if defined(CFG_ARM_CM3)\r
+void Os_Isr_cm3( void *isr_p );\r
+void TailChaining(void *stack);\r
+#endif\r
+\r
void *Os_Isr( void *stack, void *pcb_p );\r
void Os_Dispatch( uint32_t op );\r
\r
*\r
* Use cases:\r
* 1. We don't have a RAMLOG (low on RAM) so we want to print to serial console:\r
- * #define CFG_OS_DEBUG\r
+ * #define CFG_OS_DEBUG = STD_ON\r
* #define USE_SERIAL_PORT\r
* #define SELECT_OS_CONSOLE=TTY_SERIAL0\r
* 2. We have a RAMLOG but we have a debugger connected and want the OS debug\r
* to go there instead:\r
- * #define CFG_OS_DEBUG\r
+ * #define CFG_OS_DEBUG = STD_ON\r
* #define USE_RAMLOG\r
* #define USE_TTY_T32\r
* #define SELECT_OS_CONSOLE=TTY_T32\r
* 3. We have only the ramlog:\r
- * #define CFG_OS_DEBUG\r
+ * #define CFG_OS_DEBUG = STD_ON\r
* #define USE_RAMLOG\r
* #define SELECT_OS_CONSOLE=TTY_RAMLOG\r
* 4. We use no debug.\r
*\r
*/\r
\r
-#if defined(CFG_OS_DEBUG)\r
+#if (CFG_OS_DEBUG == STD_ON)\r
# if (SELECT_OS_CONSOLE==RAMLOG)\r
# ifndef USE_RAMLOG\r
# error USE_RAMLOG must be defined.\r
#if defined(CFG_ARM_CM3)
extern void Irq_EOI2( void );
-#endif
+void TailChaining(void *stack)
+{
+ struct OsPcb *pPtr = NULL;
+
+ POSTTASKHOOK();
+
+ /* Save info for preempted pcb */
+ pPtr = get_curr_pcb();
+ pPtr->stack.curr = stack;
+ pPtr->state = ST_READY;
+ OS_DEBUG(D_TASK,"Preempted %s\n",pPtr->name);
+
+ Os_StackPerformCheck(pPtr);
+
+ /* We interrupted a task */
+ OsPcbType *new_pcb = Os_TaskGetTop();
+
+ Os_StackPerformCheck(new_pcb);
+
+ if( (new_pcb == os_sys.curr_pcb) ||
+ (os_sys.curr_pcb->scheduling == NON) ||
+ !Os_SchedulerResourceIsFree() )
+ {
+ /* Just bring the preempted task back to running */
+ Os_TaskSwapContextTo(NULL,os_sys.curr_pcb);
+ } else {
+ OS_DEBUG(D_TASK,"Found candidate %s\n",new_pcb->name);
+ Os_TaskSwapContextTo(NULL,new_pcb);
+ }
+}
+
+void Os_Isr_cm3( void *isr_p ) {
+
+ struct OsPcb *isrPtr;
+
+ os_sys.int_nest_cnt++;
+
+ /* Grab the ISR "pcb" */
+ isrPtr = (struct OsPcb *)isr_p;
+ isrPtr->state = ST_RUNNING;
+
+ if( isrPtr->proc_type & ( PROC_EXTENDED | PROC_BASIC ) ) {
+ assert(0);
+ }
+
+ Irq_Enable();
+ isrPtr->entry();
+ Irq_Disable();
+
+ /* Check so that ISR2 haven't disabled the interrupts */
+ /** @req OS368 */
+ if( Os_IrqAnyDisabled() ) {
+ Os_IrqClearAll();
+ ERRORHOOK(E_OS_DISABLEDINT);
+ }
+
+ /* Check so that the ISR2 have called ReleaseResource() for each GetResource() */
+ /** @req OS369 */
+ if( Os_TaskOccupiesResources(isrPtr) ) {
+ Os_ResourceFreeAll(isrPtr);
+ ERRORHOOK(E_OS_RESOURCE);
+ }
+
+ isrPtr->state = ST_SUSPENDED;
+
+ Irq_EOI();
+
+ --os_sys.int_nest_cnt;
+
+ /* Scheduling is done in PendSV handler for ARM CM3 */
+ *((uint32_t volatile *)0xE000ED04) = 0x10000000; // PendSV
+}
+#endif
/**
* Handle ISR type 2 interrupts from interrupt controller.
--os_sys.int_nest_cnt;
+#if defined(CFG_ARM_CM3)
+ /* Scheduling is done in PendSV handler for ARM CM3 */
+ *((uint32_t volatile *)0xE000ED04) = 0x10000000; // PendSV
+#else
// We have preempted a task
if( (os_sys.int_nest_cnt == 0) ) {
-
OsPcbType *new_pcb = Os_TaskGetTop();
Os_StackPerformCheck(new_pcb);
PRETASKHOOK();
} else {
OS_DEBUG(D_TASK,"Found candidate %s\n",new_pcb->name);
-#if defined(CFG_ARM_CM3)
- Irq_EOI2();
-#endif
Os_TaskSwapContextTo(NULL,new_pcb);
}
} else {
/* We have a nested interrupt, do nothing */
}
+#endif
return stack;
}
obj-y += asm_sample.o\r
#CFLAGS_asm_sample.o += -O3\r
obj-y += arch_krn.o\r
-obj-$(CFG_HCS12D) += arch_irq.o\r
+obj-$(CFG_HC1X) += arch_irq.o\r
#obj-y += stm32f10x_it.o\r
\r
# object files \r
&rfile="test_result.txt"\r
&testfiles=0.\r
\r
-&tdir="&cfg_project_path_g\system\kernel\testsystem"\r
-os cmd /c dir &tdir/B /A:D > &datafile\r
+&tdir="&cfg_project_path_g\binaries\*osek*.elf"\r
+os cmd /c dir &tdir/B /O:N > &datafile\r
\r
os cmd /c del &rfile\r
os cmd /c echo "" > &rfile\r
READ #10 &data\r
WHILE "&data"!=""\r
( \r
- &file="&cfg_project_path_g"+"/binaries/system_kernel_testsystem_"+"&data"+".elf"\r
+// &file="&cfg_project_path_g"+"/binaries/system_kernel_testsystem_"+"&data"+".elf"\r
+ &file="&cfg_project_path_g"+"/binaries/"+"&data"\r
+\r
IF OS.FILE("&file")\r
(\r
&tmpfile=os.tmpfile()\r
\r
\r
\r
+\r
+\r
projects / arc.git / commitdiff