\r
#ifndef __CM3_CORE_H__\r
#define __CM3_CORE_H__\r
+#include "stm32f10x.h"\r
+\r
+static inline unsigned long _Irq_Save(void)\r
+{\r
+ unsigned long val = __get_PRIMASK();\r
+ Irq_Disable();\r
+ return val;\r
+}\r
+\r
+/*-----------------------------------------------------------------*/\r
+\r
+static inline void _Irq_Restore(unsigned mask) {\r
+ __set_PRIMASK(mask);\r
+}\r
+\r
+\r
\r
#ifdef __cplusplus\r
extern "C" {\r
.type Reset_Handler, %function\r
Reset_Handler: \r
\r
-/* Copy the data segment initializers from flash to SRAM */ \r
+/* Copy the data segment initializers from flash to SRAM */\r
+ ldr r0, =_sdata /* r0 holds start of data in ram */\r
+ ldr r3, =_edata /* r3 holds end of data in ram */\r
+ ldr r5, =_sidata /* r5 start of data in flash */\r
movs r1, #0\r
b LoopCopyDataInit\r
\r
CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
+ ldr r4, [r5, r1] /* read current position in flash */\r
+ str r4, [r0, r1] /* store current position in ram */\r
+ adds r1, r1, #4 /* increment counter */\r
\r
LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
+ adds r2, r0, r1 /* are we at the final position? */\r
+ cmp r2, r3 /* ... */\r
+ bcc CopyDataInit /* nope, continue */\r
ldr r2, =_sbss\r
b LoopFillZerobss\r
+\r
/* Zero fill the bss segment. */ \r
FillZerobss:\r
movs r3, #0\r
. = ALIGN(4);\r
*(.rodata .rodata.* .gnu.linkonce.r.*)\r
. = ALIGN(4);\r
- _sidata = .;\r
+ _sidata = ALIGN(.,4);\r
} > flash\r
\r
.data : AT ( _sidata )\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Can.h"\r
+#include "core_cr4.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#include "Det.h"\r
+#include "CanIf_Cbk.h"\r
+#include "Os.h"\r
+#include "irq.h"\r
+#include "Mcu.h"\r
+\r
+#define DCAN1_MAX_MESSAGEBOXES 64\r
+#define DCAN2_MAX_MESSAGEBOXES 64\r
+#define DCAN3_MAX_MESSAGEBOXES 32\r
+\r
+#define CAN_TIMEOUT_DURATION 0xFFFFFFFF\r
+#define CAN_INSTANCE 0\r
+\r
+#define DCAN_IRQ_MASK 0x00000006\r
+\r
+\r
+#if !defined(USE_DEM)\r
+// If compiled without the DEM, calls to DEM are simply ignored.\r
+#define Dem_ReportErrorStatus(...)\r
+#endif\r
+\r
+/* Macro for waiting until busy flag is 0 */\r
+#define DCAN_WAIT_UNTIL_NOT_BUSY(ControllerId, IfRegId) \\r
+ { \\r
+ uint32 ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ while(CanRegs[ControllerId]->IFx[IfRegId].COM & 0x00008000) { \\r
+ ErrCounter--; \\r
+ if(ErrCounter == 0) { \\r
+ Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED); \\r
+ ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ return CAN_NOT_OK; \\r
+ } \\r
+ } \\r
+ }\r
+\r
+/* Macro for waiting until busy flag is 0 */\r
+#define DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(ControllerId, IfRegId) \\r
+ { \\r
+ uint32 ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ while(CanRegs[ControllerId]->IFx[IfRegId].COM & 0x00008000) { \\r
+ ErrCounter--; \\r
+ if(ErrCounter == 0) { \\r
+ Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED); \\r
+ ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ return; \\r
+ } \\r
+ } \\r
+ }\r
+\r
+\r
+\r
+// Array for easy access to DCAN register definitions.\r
+static Can_RegisterType* CanRegs[]=\r
+{\r
+ DCAN1_Base,\r
+ DCAN2_Base,\r
+ DCAN3_Base\r
+};\r
+\r
+typedef enum\r
+{\r
+ CAN_UNINIT,\r
+ CAN_READY\r
+} Can_StateType;\r
+\r
+\r
+typedef struct\r
+{\r
+ uint16 MaxBoxes;\r
+ uint32 WakeupSrc;\r
+ Can_PduType *PduPtr;\r
+ uint8 *CancelPtr;\r
+ uint8 *TxPtr; \r
+} Controller_PreConfigType;\r
+\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+/* Module is in uninitialized state */\r
+static Can_StateType ModuleState = CAN_UNINIT;\r
+#endif\r
+\r
+static CanIf_ControllerModeType ControllerMode[CAN_ARC_CTRL_CONFIG_CNT];\r
+\r
+/* Used to switch between IF1 and IF2 of DCAN */\r
+static uint8 IfRegId = 0;\r
+\r
+/* Used to order Data Bytes according to hardware registers in DCAN */\r
+static const uint8 ElementIndex[] = {3, 2, 1, 0, 7, 6, 5, 4};\r
+\r
+/* To save pointer to the configuration set */\r
+static const Can_ConfigType *CurConfig;\r
+\r
+/* To save the PduData of transmission objects */\r
+static Can_PduType PduInfoArray_1[DCAN1_MAX_MESSAGEBOXES];\r
+/* To save pending Cancel Requests of transmission objects */\r
+static uint8 CancelRqstArray_1[DCAN1_MAX_MESSAGEBOXES];\r
+/* To save pending Transmit Requests of transmission objects */\r
+static uint8 TxRqstArray_1[DCAN1_MAX_MESSAGEBOXES];\r
+\r
+static Can_PduType PduInfoArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+static uint8 CancelRqstArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+static uint8 TxRqstArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+\r
+static Can_PduType PduInfoArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+static uint8 CancelRqstArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+static uint8 TxRqstArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+\r
+\r
+/* Holds the Controller specific configuration */ \r
+static Controller_PreConfigType ControllerConfig[] =\r
+{\r
+ { // DCAN1\r
+ .MaxBoxes = DCAN1_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 0,\r
+ .PduPtr = PduInfoArray_1,\r
+ .CancelPtr = CancelRqstArray_1,\r
+ .TxPtr = TxRqstArray_1\r
+ },\r
+ { // DCAN2\r
+ .MaxBoxes = DCAN2_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 1,\r
+ .PduPtr = PduInfoArray_2,\r
+ .CancelPtr = CancelRqstArray_2,\r
+ .TxPtr = TxRqstArray_2\r
+ },\r
+ { // DCAN3\r
+ .MaxBoxes = DCAN3_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 1,\r
+ .PduPtr = PduInfoArray_3,\r
+ .CancelPtr = CancelRqstArray_3,\r
+ .TxPtr = TxRqstArray_3\r
+ }\r
+\r
+};\r
+\r
+/* Shadow Buffer is used for buffering of received data */ \r
+static uint8 RxShadowBuf[CAN_ARC_CTRL_CONFIG_CNT][8];\r
+\r
+/* Driver must know how often Can_DisableControllerInterrupts() has been called */\r
+static uint32 IntDisableCount[CAN_ARC_CTRL_CONFIG_CNT];\r
+\r
+\r
+static inline const Can_HardwareObjectType * Can_FindTxHoh(Can_Arc_HTHType hth) {\r
+ for (int i = 0; i < CAN_ARC_CTRL_CONFIG_CNT; i++) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[i].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT && hoh->CanObjectId == hth) {\r
+ return hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return 0;\r
+}\r
+\r
+static inline uint8 Can_FindControllerId(Can_Arc_HTHType hth) {\r
+ for (int i = 0; i < CAN_ARC_CTRL_CONFIG_CNT; i++) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[i].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT && hoh->CanObjectId == hth) {\r
+ return i;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return 0;\r
+}\r
+\r
+static inline const Can_HardwareObjectType * Can_FindRxHoh(CanControllerIdType Controller, uint8 msgNr) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_RECEIVE\r
+ && (hoh->Can_Arc_MbMask & (1 << (msgNr - 1))) ) {\r
+ return hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ return 0;\r
+}\r
+\r
+uint32 usedBoxes[64] = {0};\r
+\r
+void Can_InterruptHandler(CanControllerIdType controller)\r
+{\r
+ uint32 MsgNr;\r
+ uint32 MsgId;\r
+ uint8 MsgDlc;\r
+ uint8 DataByteIndex;\r
+ uint8 *SduPtr;\r
+\r
+ //Can_DisableControllerInterrupts(controller);\r
+\r
+ uint32 ir = CanRegs[controller]->IR;\r
+\r
+ if(ir == 0x8000)\r
+ {\r
+ uint32 sr = CanRegs[controller]->SR;\r
+ /* WakeUp Pending */\r
+ if(sr & 0x00000200) {\r
+ /* Set Init Bit, so that Controller is in Stop state */\r
+ CanRegs[controller]->CTL |= 0x1;\r
+ // EcuM_CheckWakeUp(ControllerConfig[0].WakeupSrc);\r
+\r
+ }\r
+ /* Bus Off */\r
+ if(sr & 0x00000080) {\r
+ Can_SetControllerMode(controller, CAN_T_STOP); // CANIF272\r
+ //CanIf_ControllerBusOff(0); // Not implemented in Arctic Core\r
+\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MsgNr = ir;\r
+\r
+\r
+ if (MsgNr == 0) {\r
+ usedBoxes[MsgNr]++;\r
+ } else {\r
+ usedBoxes[MsgNr]++;\r
+ }\r
+ \r
+\r
+ /* Read Arbitration, Control and Data Bits and clear IntPnd and NewDat*/\r
+ CanRegs[controller]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
+\r
+ /* Wait until Busy Flag is 0 */\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(controller, IfRegId);\r
+\r
+ /* Transmit Object */\r
+ if(CanRegs[controller]->IFx[IfRegId].ARB & 0x20000000)\r
+ {\r
+ /* Reset TxRqst-Array Element */\r
+ ControllerConfig[controller].TxPtr[MsgNr - 1] = 0;\r
+ /* A Message was successfully transmitted */\r
+ CanIf_TxConfirmation(ControllerConfig[controller].PduPtr[MsgNr - 1].swPduHandle);\r
+ }\r
+ /* Receive Object */\r
+ else\r
+ {\r
+ /* Extended Id */\r
+ if(CanRegs[controller]->IFx[IfRegId].ARB & 0x40000000)\r
+ {\r
+ /* Bring Id to standardized format (MSB marks extended Id) */\r
+ MsgId = (CanRegs[controller]->IFx[IfRegId].ARB & 0x1FFFFFFF) | 0x80000000;\r
+ }\r
+ /* Standard Id */\r
+ else\r
+ {\r
+ /* Bring Id to standardized format (MSB marks extended Id) */\r
+ MsgId = (CanRegs[controller]->IFx[IfRegId].ARB & 0x1FFC0000) >> 18;\r
+ }\r
+ /* DLC (Max 8) */\r
+ MsgDlc = CanRegs[controller]->IFx[IfRegId].MC & 0x000F;\r
+ if(MsgDlc > 8)\r
+ {\r
+ MsgDlc = 8;\r
+ }\r
+ /* Let SduPtr point to Shadow Buffer */\r
+ SduPtr = RxShadowBuf[controller];\r
+\r
+ /* Copy Message Data to Shadow Buffer */\r
+ for(DataByteIndex = 0; DataByteIndex < MsgDlc; DataByteIndex++)\r
+ {\r
+ SduPtr[DataByteIndex] = CanRegs[controller]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
+ }\r
+ /* Indicate successful Reception */\r
+ const Can_HardwareObjectType *hoh = Can_FindRxHoh(controller, MsgNr);\r
+ CanIf_RxIndication(hoh->CanObjectId, MsgId, MsgDlc, SduPtr);\r
+\r
+ }\r
+ }\r
+ //Can_EnableControllerInterrupts(controller);\r
+}\r
+\r
+void Can1_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN1);\r
+}\r
+\r
+void Can2_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN2);\r
+}\r
+\r
+void Can3_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN3);\r
+}\r
+\r
+uint32 Can_CalculateBTR(uint8 Controller) {\r
+\r
+ uint32 clock = McuE_GetPeripheralClock(PERIPHERAL_CLOCK_CAN);\r
+ uint32 tq1 = CanControllerConfigData[Controller].CanControllerPropSeg + CanControllerConfigData[Controller].CanControllerSeg1;\r
+ uint32 tq2 = CanControllerConfigData[Controller].CanControllerSeg2;\r
+ uint32 ntq = tq1 + tq2 + 1 + 1 + 1;\r
+ uint32 brp = clock / (CanControllerConfigData[Controller].CanControllerBaudRate * 1000 * ntq) - 1;\r
+\r
+ uint32 retVal = (brp | (tq1 << 8) | (tq2 << 12));\r
+ return retVal;\r
+}\r
+\r
+\r
+void Can_Init(const Can_ConfigType *Config)\r
+{\r
+ uint32 Controller;\r
+ uint8 MsgNr;\r
+ uint32 ErrCounter;\r
+ uint32 Eob;\r
+\r
+/* DET Error Check */\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(ModuleState != CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0, CAN_E_TRANSITION);\r
+ return;\r
+ }\r
+ if(Config == NULL)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0, CAN_E_PARAM_POINTER);\r
+ return;\r
+ }\r
+#endif \r
+ \r
+ // TODO This should be used instead of other variables in the Can_Lcfg file.\r
+ CurConfig = Config;\r
+\r
+ for(Controller = 0; Controller < CAN_ARC_CTRL_CONFIG_CNT; Controller++)\r
+ {\r
+ ErrCounter = CAN_TIMEOUT_DURATION;\r
+\r
+ /* Init, IE, AutomaticRetransmission, ConfChangeEnable, ABO Off,Parity On, SIE and EIE depending on ControllerConfig, loopback */\r
+#if(CAN_WAKEUP_SUPPORT == STD_ON)\r
+ CanRegs[Controller]->CTL = 0x02001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
+#else\r
+ CanRegs[Controller]->CTL = 0x00001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
+#endif \r
+ /* LEC 7, TxOk, RxOk, PER */\r
+ CanRegs[Controller]->SR = 0x0000011F;\r
+\r
+ /* Test Mode only for Development time: Silent Loopback */\r
+ if (CanControllerConfigData[Controller].Can_Arc_Loopback) {\r
+ CanRegs[Controller]->TR = 0x00000018;\r
+ }\r
+ \r
+\r
+ // Basic message object initialization\r
+ for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MaxBoxes; MsgNr++) {\r
+ /* Initialize the Arrays for Transmit and Cancellation handling */\r
+ *(ControllerConfig[Controller].CancelPtr + MsgNr) = 0;\r
+ *(ControllerConfig[Controller].TxPtr + MsgNr) = 0;\r
+ \r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ // Initialize all message objects for this controller to invalid state.\r
+ /* Valid = 0 */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0x00000000;\r
+ /* Start writing Arbitration Bits */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00A80000 | (MsgNr + 1);\r
+\r
+ /* Use IFx[0] and IFx[1] alternating */\r
+ IfRegId ^= 1;\r
+\r
+ }\r
+\r
+ /* Configure the HOHs for this controller. */\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ uint32 mbNr = 0;\r
+ uint32 nProcessedMb = 0;\r
+\r
+ // For every message object in this hoh\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ mbNr++;\r
+ if (!(mbMask & 1)) {\r
+ // This message object is not part of this hoh.\r
+ continue;\r
+ }\r
+ nProcessedMb++;\r
+\r
+ // Check if this is the last message box for this hoh.\r
+ if((mbMask != 1) &&\r
+ (hoh->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)) {\r
+ /* EndOfBlock Bit will not be set */\r
+ Eob = 0x00000000;\r
+ }\r
+ else\r
+ {\r
+ /* EndOfBlock Bit will be set */\r
+ Eob = 0x00000080;\r
+ }\r
+\r
+ /* DLC=8, Use Mask only for receive, Set RxIE/TxIE depending on pre-config settings, Eob */\r
+ CanRegs[Controller]->IFx[IfRegId].MC = 0x00000008 // DLC = 8\r
+ | 0x00001000 // umask = ON\r
+ | CanControllerConfigData[Controller].CanRxProcessing // Rx interrupt enabled\r
+ | (CanControllerConfigData[Controller].CanTxProcessing << 1) // Tx confirmation interrupt enabled\r
+ | (Eob & ~(hoh->CanObjectType >> 22)); // Eob, only for Rx.\r
+\r
+ //CanRegs[Controller]->IFx[IfRegId].MC = 0x00001008 | CanControllerConfigData[Controller].CanRxProcessing | (CanControllerConfigData[Controller].CanTxProcessing) | Eob & ~(hoh->CanObjectType >> 17);\r
+\r
+ if(hoh->CanIdType == CAN_ID_TYPE_STANDARD) /* Standard Identifiers */\r
+ {\r
+ /* Only Standard-Ids are accepted, Set Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0x80000000 | ((hoh->CanIdValue & 0x7FF) << 18) | hoh->CanObjectType;\r
+ }\r
+ else if(hoh->CanIdType == CAN_ID_TYPE_EXTENDED) /* Extended Identifiers */\r
+ {\r
+ /* Only Extended-Ids are accepted, Set Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFFF) | hoh->CanObjectType;\r
+ }\r
+ else /* Mixed Identifiers */\r
+ {\r
+ /* Standard- and Mixed-Ids are accepted, Set Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0x00000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFF) | hoh->CanObjectType;\r
+ }\r
+ /* Start writing Mask, Arb, Control and Id bits */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00F80000 | mbNr;\r
+\r
+ /* Use IFx[0] and IFx[1] alternating */\r
+ IfRegId ^= 1;\r
+\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+\r
+\r
+ /* Set Bit Timing Register */\r
+ CanRegs[Controller]->BTR = Can_CalculateBTR(Controller);\r
+\r
+ /* Reset CCE Bit */\r
+ CanRegs[Controller]->CTL &= ~0x00000040;\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ /* Switch Controller State to CANIF_CS_STOPPED */\r
+ ControllerMode[Controller] = CANIF_CS_STOPPED;\r
+#endif\r
+\r
+ // Install interrupt handlers\r
+ TaskType tid;\r
+ if (CanControllerConfigData[Controller].CanControllerId == DCAN1) {\r
+ tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2 ,"DCAN1Level0");\r
+ Irq_AttachIsr2(tid, NULL, 16);\r
+\r
+ tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2, "DCAN1Level1");\r
+ Irq_AttachIsr2(tid, NULL, 29);\r
+\r
+ } else if (CanControllerConfigData[Controller].CanControllerId == DCAN2) {\r
+ tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2 ,"DCAN2Level0");\r
+ Irq_AttachIsr2(tid, NULL, 35);\r
+\r
+ tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2, "DCAN2Level1");\r
+ Irq_AttachIsr2(tid, NULL, 42);\r
+\r
+ } else if (CanControllerConfigData[Controller].CanControllerId == DCAN3) {\r
+ tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2 ,"DCAN3Level0");\r
+ Irq_AttachIsr2(tid, NULL, 45);\r
+\r
+ tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2, "DCAN3Level1");\r
+ Irq_AttachIsr2(tid, NULL, 55);\r
+\r
+ }\r
+\r
+ }\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ /* Switch Module State to CAN_READY */\r
+ ModuleState = CAN_READY;\r
+#endif\r
+\r
+\r
+\r
+}\r
+\r
+\r
+\r
+void Can_InitController(uint8 Controller, const Can_ControllerConfigType* Config)\r
+{\r
+ uint8 MsgNr;\r
+ uint32 ErrCounter;\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(Config == NULL)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_PARAM_POINTER);\r
+ return;\r
+ }\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_UNINIT);\r
+ return;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_PARAM_CONTROLLER);\r
+ return;\r
+ }\r
+ if(ControllerMode[Controller] != CANIF_CS_STOPPED)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_TRANSITION);\r
+ return;\r
+ }\r
+#endif \r
+\r
+ ErrCounter = CAN_TIMEOUT_DURATION;\r
+ \r
+ //for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MessageBoxCount; MsgNr++)\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ uint32 nProcessedMb = 0;\r
+ MsgNr = 0;\r
+\r
+ // For every message object in this hoh\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ MsgNr++;\r
+ if (!(mbMask & 1)) {\r
+ // This message object is not part of this hoh.\r
+ continue;\r
+ }\r
+ nProcessedMb++;\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ /* Read actual MaskRegister value of MessageObject */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x004C0000 | (MsgNr);\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ CanRegs[Controller]->IFx[IfRegId].MASK &= 0xD0000000;\r
+ /* Set new Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK |= (*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF;\r
+ /* Write new Mask to MaskRegister */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr);\r
+\r
+ IfRegId ^= 1;\r
+ }\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ /* Set CCE Bit to allow access to BitTiming Register (Init already set, in mode "stopped") */\r
+ CanRegs[Controller]->CTL |= 0x00000040;\r
+ /* Set Bit Timing Register */\r
+ CanRegs[Controller]->BTR = Can_CalculateBTR(Controller);\r
+ /* Clear CCE Bit */\r
+ CanRegs[Controller]->CTL &= ~0x00000040;\r
+\r
+}\r
+\r
+\r
+Can_ReturnType Can_SetControllerMode(uint8 Controller, Can_StateTransitionType Transition)\r
+{\r
+ Can_ReturnType Status = CAN_OK;\r
+ uint32 ErrCounter = CAN_TIMEOUT_DURATION;\r
+ uint32 RegBuf;\r
+ \r
+#if(CAN_DEV_ERROR_DETECT == STD_ON) \r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_UNINIT);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_PARAM_CONTROLLER);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(((Transition == CAN_T_START ) && (ControllerMode[Controller] != CANIF_CS_STOPPED)) ||\r
+ ((Transition == CAN_T_STOP ) && (ControllerMode[Controller] != CANIF_CS_STARTED)) ||\r
+ ((Transition == CAN_T_SLEEP ) && (ControllerMode[Controller] != CANIF_CS_STOPPED)) ||\r
+ ((Transition == CAN_T_WAKEUP) && (ControllerMode[Controller] != CANIF_CS_SLEEP )))\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_TRANSITION);\r
+ return CAN_NOT_OK;\r
+ }\r
+#endif \r
+\r
+ switch(Transition)\r
+ {\r
+ case CAN_T_START:\r
+ /* Clear Init Bit */\r
+ CanRegs[Controller]->CTL &= ~0x00000001;\r
+ /* Clear Status Register */\r
+ CanRegs[Controller]->SR = 0x0000011F;\r
+\r
+ ControllerMode[Controller] = CANIF_CS_STARTED;\r
+ Can_EnableControllerInterrupts(Controller);\r
+ break;\r
+\r
+ case CAN_T_STOP:\r
+ /* Set Init Bit */\r
+ CanRegs[Controller]->CTL |= 0x00000001;\r
+ ControllerMode[Controller] = CANIF_CS_STOPPED;\r
+ Can_DisableControllerInterrupts(Controller);\r
+ break;\r
+\r
+ case CAN_T_SLEEP:\r
+ /* Set PDR Bit */\r
+ CanRegs[Controller]->CTL |= 0x01000000;\r
+ /* Save actual Register status */\r
+ RegBuf = CanRegs[Controller]->CTL;\r
+ /* Disable Status Interrupts and WUBA */\r
+ CanRegs[Controller]->CTL &= ~0x02000004;\r
+ /* Wait until Local Power Down Mode acknowledged */\r
+ while(!(CanRegs[Controller]->SR & 0x00000400))\r
+ {\r
+ /* Check if a WakeUp occurs */\r
+ if(CanRegs[Controller]->SR & 0x00000200)\r
+ {\r
+ Status = CAN_NOT_OK;\r
+ break;\r
+ }\r
+ ErrCounter--;\r
+ if(ErrCounter == 0)\r
+ {\r
+ Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
+ ErrCounter = CAN_TIMEOUT_DURATION;\r
+ Status = CAN_NOT_OK;\r
+ break;\r
+ }\r
+ }\r
+ /* Reset Control Register */\r
+ CanRegs[Controller]->CTL = RegBuf;\r
+ ControllerMode[Controller] = CANIF_CS_SLEEP;\r
+ break;\r
+\r
+ case CAN_T_WAKEUP:\r
+ /* Clear PDR Bit */\r
+ CanRegs[Controller]->CTL &= ~0x01000000;\r
+ ControllerMode[Controller] = CANIF_CS_STOPPED;\r
+ break;\r
+\r
+ default:\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ /* Invalid Transition */\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_TRANSITION);\r
+ return CAN_NOT_OK;\r
+#endif\r
+ break;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+void Can_DisableControllerInterrupts(uint8 Controller)\r
+{\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 4, CAN_E_UNINIT);\r
+ return;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 4, CAN_E_PARAM_CONTROLLER);\r
+ return;\r
+ }\r
+#endif \r
+ /* Clear IE */\r
+ CanRegs[Controller]->CTL &= ~DCAN_IRQ_MASK;\r
+ /* Increment Disable Counter */\r
+ IntDisableCount[Controller]++;\r
+}\r
+\r
+void Can_EnableControllerInterrupts(uint8 Controller)\r
+{\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 5, CAN_E_UNINIT);\r
+ return;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 5, CAN_E_PARAM_CONTROLLER);\r
+ return;\r
+ }\r
+#endif \r
+ if(IntDisableCount[Controller] > 0)\r
+ {\r
+ if(IntDisableCount[Controller] == 1)\r
+ {\r
+ /* Set IE */\r
+ CanRegs[Controller]->CTL |= DCAN_IRQ_MASK;\r
+ }\r
+ IntDisableCount[Controller]--;\r
+ }\r
+}\r
+\r
+\r
+void Can_Cbk_CheckWakeup(uint8 Controller)\r
+{\r
+ /* TODO not supported yet.\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0x0B, CAN_E_PARAM_CONTROLLER);\r
+ return CAN_NOT_OK;\r
+ }\r
+#endif\r
+ // Check WakeUpPending\r
+ if(CanRegs[Controller]->SR & 0x00000200)\r
+ {\r
+ return E_OK;\r
+ }\r
+ else\r
+ {\r
+ return E_NOT_OK;\r
+ }\r
+ */\r
+}\r
+\r
+\r
+Can_ReturnType Can_Write(Can_Arc_HTHType Hth, Can_PduType *PduInfo)\r
+{\r
+ uint8 ControllerId;\r
+ uint8 MsgNr;\r
+ uint32 ArbRegValue;\r
+ uint8 DataByteIndex;\r
+ uint8 *CurSduPtr;\r
+ Can_PduType *CurPduArrayPtr;\r
+ uint8 *CurCancelRqstPtr;\r
+ uint8 *CurTxRqstPtr;\r
+\r
+ CurSduPtr = PduInfo->sdu;\r
+ \r
+\r
+/* DET Error Check */\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(PduInfo == NULL || PduInfo->sdu == NULL)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_POINTER);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_UNINIT);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(PduInfo->length > 8)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_DLC);\r
+ return CAN_NOT_OK; \r
+ }\r
+#endif\r
+\r
+ ControllerId = Can_FindControllerId(Hth);\r
+ \r
+ const Can_HardwareObjectType *hoh = Can_FindTxHoh(Hth);\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(hoh->CanObjectType != CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_HANDLE);\r
+ return CAN_NOT_OK;\r
+ }\r
+#endif\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ MsgNr = 0;\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ MsgNr++;\r
+ if (!(mbMask & 1)) {\r
+ continue; // This message object is not part of this hoh.\r
+ }\r
+ }\r
+\r
+ CurPduArrayPtr = ControllerConfig[ControllerId].PduPtr + (MsgNr - 1);\r
+ CurCancelRqstPtr = ControllerConfig[ControllerId].CancelPtr + (MsgNr - 1);\r
+ CurTxRqstPtr = ControllerConfig[ControllerId].TxPtr + (MsgNr - 1);\r
+ \r
+ /* Bring Id Value to appropriate format and set ArbRegValue */\r
+ if( hoh->CanIdType == CAN_ID_TYPE_EXTENDED ) {\r
+ /* MsgVal, Ext, Transmit, Extended Id */ \r
+ ArbRegValue = 0xE0000000 | (PduInfo->id & 0x1FFFFFFF);\r
+ } else {\r
+ /* MsgVal, Std, Transmit, Standard Id */ \r
+ ArbRegValue = 0xA0000000 | ((PduInfo->id & 0x7FF) << 18);\r
+ }\r
+\r
+ /* Check if TxRqst Bit of MsgObject is set */\r
+ if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F)))\r
+ {\r
+ return CAN_BUSY;\r
+ }\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY(ControllerId, IfRegId);\r
+\r
+\r
+ /* Set NewDat, TxIE (dep on ControllerConfig), TxRqst, EoB and DLC */\r
+ CanRegs[ControllerId]->IFx[IfRegId].MC = 0x00000100 // Tx request\r
+ | 0x00000080 // Eob should be set to one for tx\r
+ | (0x000F & PduInfo->length) // Set DLC\r
+ | (CanControllerConfigData[ControllerId].CanTxProcessing << 1); // Tx confirmation interrupt enabled\r
+\r
+\r
+ /* Set ArbitrationRegister */\r
+ CanRegs[ControllerId]->IFx[IfRegId].ARB = ArbRegValue;\r
+\r
+ /* Set Databytes */\r
+ for(DataByteIndex = 0; DataByteIndex < PduInfo->length; DataByteIndex++)\r
+ {\r
+ CanRegs[ControllerId]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]] = *CurSduPtr++;\r
+ }\r
+\r
+ /* Start transmission to MessageRAM */\r
+ CanRegs[ControllerId]->IFx[IfRegId].COM = 0x00BF0000 | MsgNr;\r
+ \r
+ /* Save the PduInfo in PduArray, so that messages can be identified later */\r
+ *CurPduArrayPtr = *PduInfo;\r
+ /* TxRqstArray-Elements are used to identifiy transmitted objects in polling mode */\r
+ *CurTxRqstPtr = 1;\r
+ \r
+ IfRegId ^= 1;\r
+ \r
+ return CAN_OK;\r
+}\r
+\r
+\r
+void Can_MainFunction_Write()\r
+{\r
+ // Not supported\r
+}\r
+\r
+void Can_MainFunction_Read()\r
+{\r
+ // Not supported\r
+}\r
+\r
+void Can_MainFunction_BusOff()\r
+{\r
+ // Not supported\r
+}\r
+\r
+void Can_MainFunction_Wakeup()\r
+{\r
+ // Not supported\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Mcu.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#include <assert.h>\r
+#include "cpu.h"\r
+#include <string.h>\r
+#include "Ramlog.h"\r
+\r
+#include "core_cr4.h"\r
+\r
+//#define USE_TRACE 1\r
+//#define USE_LDEBUG_PRINTF 1\r
+#include "debug.h"\r
+\r
+/* PLLCTL1 register */\r
+#define MCU_RESET_ON_SLIP 0 // Reset on slip is off\r
+#define MCU_RESET_ON_SLIP_OFFSET 31 // Offset in PLLCTL1\r
+\r
+#define MCU_BYPASS_ON_SLIP 2 // Bypass on slip is off\r
+#define MCU_BYPASS_ON_SLIP_OFFSET 29 // Offset in PLLCTL1 (2 bits)\r
+\r
+#define MCU_RESET_ON_OSC_FAIL 0 // Reset on oscillator fail is off\r
+#define MCU_RESET_ON_OSC_FAIL_OFFSET 23 // Offset in PLLCTL1\r
+\r
+#define MCU_PLLDIV_OFFSET 24 // Offset in PLLCTL1 (5 bits)\r
+#define MCU_PLLDIV_MASK (0x1F << MCU_PLLDIV_OFFSET)\r
+#define MCU_REFCLKDIV_OFFSET 16 // Offset in PLLCTL1 (6 bits)\r
+#define MCU_REFCLKDIV_MASK (0x3F << MCU_REFCLKDIV_OFFSET)\r
+#define MCU_PLLMUL_OFFSET 0 // Offset in PLLCTL1 (16 bits)\r
+#define MCU_PLLMUL_MASK (0xFFFF << MCU_PLLMUL_OFFSET)\r
+\r
+/* PLLCTL2 register */\r
+#define MCU_FM_ENABLE 0 // Frequency modulation is off\r
+#define MCU_FM_ENABLE_OFFSET 31 // Offset in PLLCTL2\r
+\r
+#define MCU_SPREADING_RATE 0 // Spreading rate\r
+#define MCU_SPREADING_RATE_OFFSET 22 // Offset in PLLCTL2 (9 bits)\r
+\r
+#define MCU_BWADJ 0 // Bandwidth adjustment\r
+#define MCU_BWADJ_OFFSET 12 // Offset in PLLCTL2 (9 bits)\r
+\r
+#define MCU_ODPLL_OFFSET 9 // Offset in PLLCTL2 (3 bits)\r
+#define MCU_ODPLL_MASK (0x7 << MCU_ODPLL_OFFSET)\r
+\r
+#define MCU_SPREADING_AMOUNT 0 // Spreading amount\r
+#define MCU_SPREADING_AMOUT_OFFSET 0 // Offset in PLLCTL2 (9 bits)\r
+\r
+\r
+/* CSDIS (Clock source disable) register offsets */\r
+#define MCU_CLK_SOURCE_OSC_OFFSET 0\r
+#define MCU_CLK_SOURCE_FMZPLL_OFFSET 1\r
+#define MCU_CLK_SOURCE_LPO_OFFSET 4\r
+#define MCU_CLK_SOURCE_HPO_OFFSET 5\r
+#define MCU_CLK_SOURCE_FPLL_OFFSET 6\r
+\r
+\r
+#ifndef ARRAY_SIZE\r
+#define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))\r
+#endif\r
+\r
+/* Development error macros. */\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+\r
+#define CORE_CPUID_CORTEX_M3 0x411FC231UL\r
+\r
+typedef struct {\r
+ uint32 lossOfLockCnt;\r
+ uint32 lossOfClockCnt;\r
+} Mcu_Stats;\r
+\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+ * Type that holds all global data for Mcu\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Mcu_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Mcu_ConfigType *config;\r
+\r
+ Mcu_ClockType clockSetting;\r
+\r
+ Mcu_Stats stats;\r
+\r
+} Mcu_GlobalType;\r
+\r
+\r
+// Global config\r
+Mcu_GlobalType Mcu_Global =\r
+{\r
+ .initRun = 0,\r
+ .config = &McuConfigData[0],\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} core_info_t;\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} cpu_info_t;\r
+\r
+\r
+void Mcu_ConfigureFlash(void);\r
+\r
+\r
+\r
+/* Haven't found any ID accessable from memory.\r
+ * There is the DBGMCU_IDCODE (0xe0042000) found in RM0041 but it\r
+ * you can't read from that address..\r
+ */\r
+#if 0\r
+cpu_info_t cpu_info_list[] = {\r
+ {\r
+ .name = "????",\r
+ .pvr = 0,\r
+ },\r
+};\r
+#endif\r
+\r
+/* The supported cores\r
+ */\r
+core_info_t core_info_list[] = {\r
+ {\r
+ .name = "CORE_ARM_CORTEX_M3",\r
+ .pvr = CORE_CPUID_CORTEX_M3,\r
+ },\r
+};\r
+\r
+\r
+\r
+static core_info_t *Mcu_IdentifyCore(uint32 pvr)\r
+{\r
+\r
+\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ * Identify the core, just to check that we have support for it.\r
+ *\r
+ * @return\r
+ */\r
+static uint32 Mcu_CheckCpu( void ) {\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * Set bus clocks. SysClk,AHBClk,APB1Clk,APB2Clk\r
+ */\r
+static void SetClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+\r
+}\r
+\r
+/**\r
+ * Initialize Peripherals clocks\r
+ */\r
+static void InitPerClocks()\r
+{\r
+\r
+}\r
+\r
+/**\r
+ * Initialize Flash, PLL and clocks.\r
+ */\r
+static void InitMcuClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+\r
+ // INTCLK 1.63MHz - 6.53MHz\r
+ // NR (REFCLKDIV) 1 - 64\r
+ // INTCLK = CLKIN / REFCLKDIV;\r
+\r
+ // Output CLK 120MHz - 500MHz\r
+ // NF (PLLMUL) 92 - 184\r
+ // OutputCLK = INTCLK * PLLMUL;\r
+\r
+ // OD (ODPLL) 1 - 8\r
+ // R (PLLDIV) 1 - 32\r
+ // PLLCLK = OutputCLK / ODPLL / PLLDIV;\r
+\r
+ // Algorithm\r
+ // PLLCLK = (CLKIN * PLLMUL) / (REFCLKDIV * ODPLL * PLLDIV);\r
+\r
+\r
+ /** - Setup pll control register 1:\r
+ * - Setup reset on oscillator slip\r
+ * - Setup bypass on pll slip\r
+ * - Setup reset on oscillator fail\r
+ * - Setup Pll output clock divider\r
+ * - Setup reference clock divider\r
+ * - Setup Pll multiplier*\r
+ */\r
+ systemREG1->PLLCTL1 =\r
+ (MCU_RESET_ON_SLIP << MCU_RESET_ON_SLIP_OFFSET)\r
+ | (MCU_BYPASS_ON_SLIP << MCU_BYPASS_ON_SLIP_OFFSET)\r
+ | (MCU_RESET_ON_OSC_FAIL << MCU_RESET_ON_OSC_FAIL_OFFSET)\r
+ | ((clockSettingsPtr->Pll1 - 1) << MCU_REFCLKDIV_OFFSET)\r
+ | (((clockSettingsPtr->Pll2 - 1) * 256) << MCU_PLLMUL_OFFSET)\r
+ | ((clockSettingsPtr->Pll4 - 1) << MCU_PLLDIV_OFFSET);\r
+\r
+\r
+ /** Setup PLLCTL2\r
+ * - Setup internal Pll output divider\r
+ * - Enable/Disable frequency modulation (NOT USED)\r
+ * - Setup spreading rate (NOT USED)\r
+ * - Setup bandwidth adjustment (NOT USED)\r
+ * - Setup spreading amount (NOT USED)\r
+ */\r
+ systemREG1->PLLCTL2 =\r
+ (MCU_FM_ENABLE << MCU_FM_ENABLE_OFFSET)\r
+ | (MCU_SPREADING_RATE << MCU_SPREADING_RATE_OFFSET)\r
+ | (MCU_BWADJ << MCU_BWADJ_OFFSET)\r
+ | (MCU_SPREADING_AMOUNT << MCU_SPREADING_AMOUT_OFFSET)\r
+ | ((clockSettingsPtr->Pll3 - 1) << MCU_ODPLL_OFFSET);\r
+\r
+ /** - Wait for until clocks are locked */\r
+ while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF));\r
+\r
+\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_Init(const Mcu_ConfigType *configPtr)\r
+{\r
+ VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
+\r
+#if !defined(USE_SIMULATOR)\r
+ Mcu_CheckCpu();\r
+#endif\r
+\r
+ memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
+\r
+ /** Enable/Disable the right clocks\r
+ * 0 = enable, 1 = disable */\r
+ systemREG1->CSDIS =\r
+ (0 << MCU_CLK_SOURCE_OSC_OFFSET)\r
+ | (0 << MCU_CLK_SOURCE_FMZPLL_OFFSET)\r
+ | (1 << MCU_CLK_SOURCE_LPO_OFFSET)\r
+ | (0 << MCU_CLK_SOURCE_HPO_OFFSET)\r
+ | (1 << MCU_CLK_SOURCE_FPLL_OFFSET);\r
+\r
+\r
+ /** - Wait for until clocks are locked */\r
+ while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF));\r
+\r
+ /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */\r
+ systemREG1->GHVSRC = (SYS_PLL << 24U) // Selectes PLL clock (clock source 1) as wakeup clock source.\r
+ | (SYS_PLL << 16U) // Select PLL clock (clock source 1) as wakeup when GCLK is off as clock source.\r
+ | SYS_PLL; // Select PLL clock (clock source 1) as current clock source.\r
+\r
+ /** - Power-up clocks to all peripharals */\r
+ pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;\r
+\r
+ /** - Setup synchronous peripheral clock dividers for VCLK1 and VCLK2\r
+ * 1 = divide by 2\r
+ */\r
+ systemREG1->VCLKR = 1U;\r
+ systemREG1->VCLK2R = 1U;\r
+\r
+ /** - Setup RTICLK1 and RTICLK2 clocks */\r
+ systemREG1->RCLKSRC = (0U << 24U) // RTICLK2 divider is 1\r
+ | (SYS_VCLK << 16U) // Select VCLK as source for RTICLK2.\r
+ | (0U << 8U) // RTICLK2 divider is 1\r
+ | SYS_VCLK; // Select VCLK as source for RTICLK1.\r
+\r
+ /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */\r
+ systemREG1->VCLKASRC = (SYS_VCLK << 8U)\r
+ | SYS_VCLK;\r
+\r
+ /** - Enable Peripherals */\r
+ systemREG1->PENA = 1U;\r
+\r
+ Mcu_Global.config = configPtr;\r
+ Mcu_Global.initRun = 1;\r
+}\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DeInit()\r
+{\r
+ Mcu_Global.initRun = FALSE;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );\r
+\r
+ /* NOT SUPPORTED, reason: no support for external RAM */\r
+\r
+ return E_NOT_OK;\r
+}\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)\r
+{\r
+ Mcu_ClockSettingConfigType *clockSettingsPtr;\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );\r
+\r
+ Mcu_Global.clockSetting = ClockSetting;\r
+ clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
+\r
+ InitMcuClocks(clockSettingsPtr);\r
+ InitPerClocks(clockSettingsPtr);\r
+\r
+ return E_OK;\r
+\r
+\r
+\r
+\r
+\r
+ return E_OK;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DistributePllClock(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+Mcu_PllStatusType Mcu_GetPllStatus(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );\r
+\r
+ if ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) {\r
+ return MCU_PLL_UNLOCKED;\r
+ }\r
+\r
+ return MCU_PLL_LOCKED;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ *\r
+ * @return\r
+ */\r
+Mcu_ResetType Mcu_GetResetReason(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );\r
+ Mcu_ResetType reason = MCU_RESET_UNDEFINED;\r
+\r
+ if (systemREG1->SYSESR & 0x00008000) {\r
+ reason = MCU_POWER_ON_RESET;\r
+ systemREG1->SYSESR = 0x00008000;\r
+ } else if (systemREG1->SYSESR & 0x00004000) {\r
+ reason = MCU_OSC_FAILURE_RESET;\r
+ systemREG1->SYSESR = 0x00004000;\r
+ } else if (systemREG1->SYSESR & 0x00002000) {\r
+ reason = MCU_WATCHDOG_RESET;\r
+ systemREG1->SYSESR = 0x00002000;\r
+ } else if (systemREG1->SYSESR & 0x00000020) {\r
+ reason = MCU_CPU_RESET;\r
+ systemREG1->SYSESR = 0x00000020;\r
+ } else if (systemREG1->SYSESR & 0x00000010) {\r
+ reason = MCU_SW_RESET;\r
+ systemREG1->SYSESR = 0x00000010;\r
+ } else if (systemREG1->SYSESR & 0x00000008) {\r
+ reason = MCU_EXT_RESET;\r
+ systemREG1->SYSESR = 0x00000008;\r
+ } else if (systemREG1->SYSESR & 0x00000004) {\r
+ reason = MCU_VSW_RESET;\r
+ systemREG1->SYSESR = 0x00000004;\r
+ } else {\r
+ reason = MCU_RESET_UNDEFINED;\r
+ }\r
+\r
+/* USER CODE BEGIN (23) */\r
+/* USER CODE END */\r
+\r
+ return reason;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * Shall read the raw reset value from hardware register if the hardware\r
+ * supports this.\r
+ *\r
+ * @return\r
+ */\r
+\r
+Mcu_RawResetType Mcu_GetResetRawValue(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );\r
+\r
+ Mcu_RawResetType reason = 0xFFFFFFFF;\r
+ reason = systemREG1->SYSESR & 0x0000E03B;\r
+ systemREG1->SYSESR = 0x0000E03B;\r
+\r
+ return reason;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( MCU_PERFORM_RESET_API == STD_ON )\r
+/**\r
+ * Shell perform a microcontroller reset by using the hardware feature\r
+ * of the micro controller.\r
+ */\r
+void Mcu_PerformReset(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );\r
+ systemREG1->SYSECR = 0x00008000;\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_SetMode(const Mcu_ModeType McuMode)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * Get the system clock in Hz. It calculates the clock from the\r
+ * different register settings in HW.\r
+ */\r
+uint32_t McuE_GetSystemClock(void)\r
+{\r
+ uint32_t f_sys;\r
+\r
+ // PLLCLK = (CLKIN * PLLMUL) / (REFCLKDIV * ODPLL * PLLDIV);\r
+\r
+ uint32 odpll = ((systemREG1->PLLCTL2 & MCU_ODPLL_MASK) >> MCU_ODPLL_OFFSET) + 1;\r
+ uint32 plldiv = ((systemREG1->PLLCTL1 & MCU_PLLDIV_MASK) >> MCU_PLLDIV_OFFSET) + 1;\r
+ uint32 refclkdiv = ((systemREG1->PLLCTL1 & MCU_REFCLKDIV_MASK) >> MCU_REFCLKDIV_OFFSET) + 1;\r
+ uint32 pllmult = (((systemREG1->PLLCTL1 & MCU_PLLMUL_MASK) >> MCU_PLLMUL_OFFSET) / 256) + 1;\r
+\r
+ f_sys = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;\r
+ f_sys = f_sys * pllmult / (refclkdiv * odpll * plldiv);\r
+\r
+ return f_sys;\r
+}\r
+\r
+imask_t McuE_EnterCriticalSection()\r
+{\r
+ McuE_DisableInterrupts();\r
+ return 0;\r
+}\r
+\r
+void McuE_ExitCriticalSection(uint32_t old_state)\r
+{\r
+ McuE_EnableInterrupts();\r
+}\r
+\r
+/**\r
+ * Get the peripheral clock in Hz for a specific device\r
+ */\r
+uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
+{\r
+ if (type == PERIPHERAL_CLOCK_CAN) {\r
+ uint8 vclockDiv = systemREG1->VCLKR;\r
+ return McuE_GetSystemClock() / (vclockDiv + 1);\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * Function to setup the internal flash for optimal performance\r
+ */\r
+void Mcu_ConfigureFlash(void)\r
+{\r
+\r
+}\r
+\r
+void McuE_EnableInterrupts(void)\r
+{\r
+ Irq_Enable();\r
+}\r
+\r
+void McuE_DisableInterrupts(void)\r
+{\r
+ Irq_Disable();\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "internal.h"\r
+#include "stack.h"\r
+#include "core_cr4.h"\r
+\r
+\r
+/**\r
+ * Function make sure that we switch to supervisor mode(rfi) before\r
+ * we call a task for the first time.\r
+ */\r
+\r
+void Os_ArchFirstCall( void )\r
+{\r
+ // TODO: make switch here... for now just call func.\r
+ Irq_Enable();\r
+ os_sys.curr_pcb->entry();\r
+}\r
+\r
+void *Os_ArchGetStackPtr( void ) {\r
+\r
+ return (void *)0;\r
+}\r
+\r
+unsigned int Os_ArchGetScSize( void ) {\r
+ return SC_SIZE;\r
+}\r
+\r
+void Os_ArchSetTaskEntry(OsPcbType *pcbPtr ) {\r
+ // TODO: Add lots of things here, see ppc55xx\r
+ uint32_t *context = (uint32_t *)pcbPtr->stack.curr;\r
+\r
+ context[C_CONTEXT_OFFS/4] = SC_PATTERN;\r
+\r
+ /* Set LR to start function */\r
+ if( pcbPtr->proc_type == PROC_EXTENDED ) {\r
+ context[VGPR_LR_OFF/4] = (uint32_t)Os_TaskStartExtended;\r
+ } else if( pcbPtr->proc_type == PROC_BASIC ) {\r
+ context[VGPR_LR_OFF/4] = (uint32_t)Os_TaskStartBasic;\r
+ }\r
+\r
+}\r
+\r
+void Os_ArchSetupContext( OsPcbType *pcb ) {\r
+ // TODO: Add lots of things here, see ppc55xx\r
+ // uint32_t *context = (uint32_t *)pcb->stack.curr;\r
+\r
+}\r
+\r
+void Os_ArchInit( void ) {\r
+ // nothing to do here, yet :)\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#define _ASSEMBLER_\r
+#include "kernel_offset.h"\r
+#include "stack.h"\r
+\r
+.extern os_sys\r
+\r
+ .syntax unified\r
+ .cpu cortex-r4\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+ .section .text\r
+\r
+ .global Irq_Handler\r
+ .type Irq_Handler, %function\r
+ \r
+ .global Svc_Handler\r
+ .type Svc_Handler, %function \r
+\r
+ .global Data_Exc_Handler\r
+ .type Data_Exc_Handler, %function\r
+ \r
+ .global Prefetch_Exc_Handler\r
+ .type Prefetch_Exc_Handler, %function\r
+ \r
+ .global Dummy_Irq\r
+ .type Dummy_Irq, %function \r
+\r
+\r
+// Registers part of context.\r
+#define REG_SAVE r0-r12\r
+\r
+\r
+// A data exception handler. This let us put a breakpoint and return to the place where the exception was caught.\r
+// If DEBUG_EXCEPTIONS is off then just use the ordinary dummy irq.\r
+Data_Exc_Handler: \r
+#ifdef CFG_ARM_CR4_DEBUG_EXCEPTIONS\r
+ // Setup return address. This requires subtraction from LR.\r
+ sub lr, lr, #8\r
+ \r
+ // Store return stuff on system mode's stack\r
+ srsdb sp!, #31 // 31 = System mode\r
+ \r
+ // Switch to system mode.\r
+ cpsid i, #31 // 31 = system mode\r
+ \r
+ // Return using stuff from stack.\r
+ rfeia sp!\r
+#else\r
+ b Dummy_Irq\r
+#endif\r
+\r
+// A prefetch exception handler. This let us put a breakpoint and return to the place where the exception was caught.\r
+// If DEBUG_EXCEPTIONS is off then just use the ordinary dummy irq.\r
+Prefetch_Exc_Handler: \r
+#ifdef CFG_ARM_CR4_DEBUG_EXCEPTIONS \r
+\r
+ // Switch to system mode.\r
+ cpsid i, #31 // 31 = system mode\r
+ \r
+ // Setup return address. This requires subtraction from LR.\r
+ sub lr, lr, #4\r
+ \r
+ // Return to the place before the instruction that caused the interrupt.\r
+ MOVS PC, LR\r
+ \r
+#else\r
+ b Dummy_Irq\r
+#endif\r
+\r
+\r
+Irq_Handler:\r
+ // Setup return address. This requires subtraction from LR.\r
+ sub lr, lr, #4\r
+\r
+Svc_Handler:\r
+ // Store return stuff on system mode's stack\r
+ srsdb sp!, #31 // 31 = System mode\r
+ \r
+ // Switch to system mode.\r
+ cpsid i, #31 // 31 = system mode \r
+ \r
+ // Push registers on stack\r
+ push {REG_SAVE,lr}\r
+ \r
+ sub.w sp,sp,#C_SIZE\r
+ mov.w r4,#LC_PATTERN\r
+ str r4,[sp,#C_CONTEXT_OFFS]\r
+ \r
+ // Put stack as first arg to Irq_Entry \r
+ mov r0,sp \r
+ \r
+ // When at interrupt nest count = 0, load interrupt stack \r
+ ldr r4,=os_sys\r
+ ldr r5,[r4,#SYS_INT_NEST_CNT]\r
+ cmp r5, #0\r
+ bgt arggg\r
+ ldr sp,[r4,#SYS_INT_STACK] \r
+ \r
+arggg: \r
+ bl Irq_Entry\r
+ mov sp, r0 // pop from returned stack\r
+\r
+ /* Do a normal exception return */\r
+ add.w sp,sp,#C_SIZE\r
+ \r
+ // Restore registers\r
+ pop {REG_SAVE,lr}\r
+ \r
+ // Return using stuff from stack.\r
+ rfeia sp!\r
+ \r
+/**\r
+ * Fake an interrupt stack to be able to return to thread mode.\r
+ *\r
+ * Arm stack look like:\r
+ * xPSR\r
+ * PC\r
+ * LR\r
+ * r12\r
+ * r3\r
+ * r2\r
+ * r1\r
+ * r0\r
+ *\r
+ * Don't really know what bits matter on the xPSR here. Not setting\r
+ * the EPSR[T] is really bad since it will generate a INVSTATE exception.\r
+ */\r
+ .global Irq_EOI2\r
+ .type Irq_EOI2, %function\r
+\r
+Irq_EOI2:\r
+ mov.w r1,0x01000000 /* EPSR[T] bit */\r
+ mov r0,lr\r
+ push {r0,r1} /* Push PC and xPSR */\r
+ sub.w sp,sp,#(6*4) /* r0,r1,r2,r3, r12,lr,pc,xPSR */\r
+ mov.w lr,#0xfffffff9 /* interrupt return with stack=MSR */\r
+ bx lr /* do return */\r
+\r
+\r
+/**\r
+ * Os_ArchSetSpAndCall\r
+ *\r
+ * @param sp Pointer to the stack\r
+ * @param f Pointer to the function to call\r
+ */\r
+\r
+ .global Os_ArchSetSpAndCall\r
+ .type Os_ArchSetSpAndCall, %function\r
+Os_ArchSetSpAndCall:\r
+ mov.w sp,r0\r
+ mov.w lr,r1\r
+ bx lr\r
+\r
+/**\r
+ * Os_ArchSwapContext\r
+ *\r
+ * @param r0 - pcb for old task\r
+ * @param r1 - pcb for new task\r
+ *\r
+ * -------------- higher addr\r
+ * r4-r8,etc\r
+ * -------\r
+ * 4 - Large or Small context indicator\r
+ * 0 - ?\r
+ * ----------\r
+ *\r
+ */\r
+ .global Os_ArchSwapContext\r
+ .type Os_ArchSwapContext, %function\r
+Os_ArchSwapContext:\r
+ // Save function call registers\r
+ push {REG_SAVE,lr}\r
+\r
+ // Store the context frame\r
+ sub.w sp,sp,#C_SIZE\r
+\r
+ // Save small-context indicator\r
+ mov.w r4,#SC_PATTERN\r
+ str r4,[sp,#C_CONTEXT_OFFS]\r
+ // ---> We have saved NVGPR+C\r
+\r
+ // store old stack for old task\r
+ mov.w r4,sp\r
+ str r4,[r0,#PCB_STACK_CURR_P]\r
+\r
+ // Flow down\r
+ // R1 - new PCB\r
+ .global Os_ArchSwapContextTo\r
+ .type Os_ArchSwapContextTo, %function\r
+Os_ArchSwapContextTo:\r
+\r
+ // Get stack for new task\r
+ ldr r2,[r1,#PCB_STACK_CURR_P]\r
+ mov.w sp,r2\r
+ \r
+ // Set new current pcb\r
+ ldr r5,= os_sys\r
+ str r1,[r5,#SYS_CURR_PCB_P]\r
+\r
+ // Restore C context\r
+ ldr r6,[sp,#C_CONTEXT_OFFS]\r
+ cmp r6,#SC_PATTERN\r
+ beq os_sc_restore\r
+ cmp r6,#LC_PATTERN\r
+ beq os_lc_restore\r
+ \r
+os_stack_problem:\r
+// TODO: Jump to error handler\r
+ b os_stack_problem\r
+\r
+\r
+/* Restore the small context. Cases:\r
+ * - "Normal" context switch between processes.\r
+ * - We are in handler mode (this task preemted another task in interrupt\r
+ * context). We need to terminate handler mode ( set to LR=0xffff_fff9 )\r
+ * and\r
+ */\r
+os_sc_restore:\r
+ add.w sp,sp,#C_SIZE\r
+ pop {REG_SAVE,lr}\r
+ bx lr\r
+\r
+\r
+/* Restore the large context. Cases:\r
+ * 1. Directly from Irq_Handler()\r
+ * (the preempted task got swapped in directly)\r
+ * 2. The preempted task, got preemted by a task and\r
+ * we have already returned from handler mode.\r
+ *\r
+ * NOTE ! Only case 2 is covered here, case 1 is handled in Irq_Handler\r
+ * prologue\r
+ */\r
+ \r
+os_lc_restore:\r
+ /* Do a normal exception return */\r
+ add.w sp,sp,#C_SIZE\r
+ \r
+ // Restore registers\r
+ pop {REG_SAVE,lr}\r
+ \r
+ /* Enable interrupts */\r
+ //cpsie i \r
+\r
+ // Return using stuff from stack.\r
+ rfeia sp!\r
+\r
+ \r
+/* Interrupt routine used to catch unused interrupts and exceptions */\r
+Dummy_Irq:\r
+ /* Go back to sys mode for easier debugging.\r
+ Save link register*/\r
+ mov r3, lr\r
+ /* We don't want to use the IRQ mode\r
+ so swich back to sys mode. */\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ /* Restore link register again */\r
+ mov lr, r3\r
+ b Dummy_Irq\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+\r
+#define DECLARE(_sym,_val) \\r
+ __asm("#define " #_sym " %0 ": : "i" (_val))\r
+\r
+\r
+#include "stack.h"\r
+\r
+void arch_foo(void) {\r
+ /* StackNvgprType */\r
+ DECLARE(STACK_NVGPR_R4, offsetof(StackNvgprType, r4));\r
+ DECLARE(STACK_NVGPR_R5, offsetof(StackNvgprType, r5));\r
+ DECLARE(STACK_NVGPR_R6, offsetof(StackNvgprType, r6));\r
+ DECLARE(STACK_NVGPR_R7, offsetof(StackNvgprType, r7));\r
+ DECLARE(STACK_NVGPR_R8, offsetof(StackNvgprType, r8));\r
+ DECLARE(STACK_NVGPR_R10, offsetof(StackNvgprType, r10));\r
+ DECLARE(STACK_NVGPR_R11, offsetof(StackNvgprType, r11));\r
+ DECLARE(STACK_NVGPR_VA, offsetof(StackNvgprType, va));\r
+\r
+ /* StackCallAndContextType */\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef CORE_CR4_H_\r
+#define CORE_CR4_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+typedef volatile struct vimBase\r
+{\r
+ unsigned : 24U; /* 0x0000 */\r
+ unsigned IRQIVEC : 8U; /* 0x0000 */\r
+ unsigned : 24U; /* 0x0004 */\r
+ unsigned FIQIVEC : 8U; /* 0x0004 */\r
+ unsigned : 32U; /* 0x0008 */\r
+ unsigned : 32U; /* 0x000C */\r
+ unsigned FIRQPR0; /* 0x0010 */\r
+ unsigned FIRQPR1; /* 0x0014 */\r
+ unsigned FIRQPR2; /* 0x0018 */\r
+ unsigned FIRQPR3; /* 0x001C */\r
+ unsigned INTREQ0; /* 0x0020 */\r
+ unsigned INTREQ1; /* 0x0024 */\r
+ unsigned INTREQ2; /* 0x0028 */\r
+ unsigned INTREQ3; /* 0x002C */\r
+ unsigned REQMASKSET0; /* 0x0030 */\r
+ unsigned REQMASKSET1; /* 0x0034 */\r
+ unsigned REQMASKSET2; /* 0x0038 */\r
+ unsigned REQMASKSET3; /* 0x003C */\r
+ unsigned REQMASKCLR0; /* 0x0040 */\r
+ unsigned REQMASKCLR1; /* 0x0044 */\r
+ unsigned REQMASKCLR2; /* 0x0048 */\r
+ unsigned REQMASKCLR3; /* 0x004C */\r
+ unsigned WAKEMASKSET0; /* 0x0050 */\r
+ unsigned WAKEMASKSET1; /* 0x0054 */\r
+ unsigned WAKEMASKSET2; /* 0x0058 */\r
+ unsigned WAKEMASKSET3; /* 0x005C */\r
+ unsigned WAKEMASKCLR0; /* 0x0060 */\r
+ unsigned WAKEMASKCLR1; /* 0x0064 */\r
+ unsigned WAKEMASKCLR2; /* 0x0068 */\r
+ unsigned WAKEMASKCLR3; /* 0x006C */\r
+ unsigned IRQVECREG; /* 0x0070 */\r
+ unsigned FIQVECREQ; /* 0x0074 */\r
+ unsigned : 9U; /* 0x0078 */\r
+ unsigned CAPEVTSRC1 : 7U; /* 0x0078 */\r
+ unsigned : 9U; /* 0x0078 */\r
+ unsigned CAPEVTSRC0 : 7U; /* 0x0078 */\r
+ unsigned : 32U; /* 0x007C */\r
+ unsigned char CHANMAP[64U]; /* 0x0080-0x017C */\r
+} vimBASE_t;\r
+\r
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)\r
+\r
+\r
+\r
+typedef volatile struct rtiBase\r
+{\r
+ unsigned GCTRL; /**< 0x0000: Global Control Register */\r
+ unsigned TBCTRL; /**< 0x0004: Timebase Control Register */\r
+ unsigned CAPCTRL; /**< 0x0008: Capture Control Register */\r
+ unsigned COMPCTRL; /**< 0x000C: Compare Control Register */\r
+ struct\r
+ {\r
+ unsigned FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */\r
+ unsigned UCx; /**< 0x0014,0x0034: Up Counter x Register */\r
+ unsigned CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */\r
+ unsigned : 32; /**< 0x001C,0x003C: Reserved */\r
+ unsigned CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */\r
+ unsigned CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */\r
+ unsigned : 32; /**< 0x0028,0x0048: Reserved */\r
+ unsigned : 32; /**< 0x002C,0x004C: Reserved */\r
+ } CNT[2U]; /**< Counter x selection:\r
+ - 0: Counter 0\r
+ - 1: Counter 1 */\r
+ struct\r
+ {\r
+ unsigned COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */\r
+ unsigned UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */\r
+ } CMP[4U]; /**< Compare x selection:\r
+ - 0: Compare 0\r
+ - 1: Compare 1\r
+ - 2: Compare 2\r
+ - 3: Compare 3 */\r
+ unsigned TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */\r
+ unsigned TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */\r
+ unsigned : 32; /**< 0x0078: Reserved */\r
+ unsigned : 32; /**< 0x007C: Reserved */\r
+ unsigned SETINT; /**< 0x0080: Set/Status Interrupt Register */\r
+ unsigned CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */\r
+ unsigned INTFLAG; /**< 0x008C: Interrupt Flag Register */\r
+} rtiBASE_t;\r
+\r
+/** @def rtiREG1\r
+* @brief RTI1 Register Frame Pointer\r
+*\r
+* This pointer is used by the RTI driver to access the RTI1 registers.\r
+*/\r
+#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00)\r
+\r
+\r
+enum systemClockSource\r
+{\r
+ SYS_OSC = 0, /**< Alias for oscillator clock Source */\r
+ SYS_PLL = 1, /**< Alias for Pll clock Source */\r
+ SYS_O32 = 2, /**< Alias for 32 kHz oscillator clock Source */\r
+ SYS_EXTERNAL = 3, /**< Alias for external clock Source */\r
+ SYS_LPO_LOW = 4, /**< Alias for low power oscillator low clock Source */\r
+ SYS_LPO_HIGH = 5, /**< Alias for low power oscillator high clock Source */\r
+ SYS_FR_PLL = 6, /**< Alias for flexray pll clock Source */\r
+ SYS_VCLK = 9 /**< Alias for synchronous VCLK1 clock Source */\r
+};\r
+\r
+typedef volatile struct systemBase1\r
+{\r
+ unsigned SYSPC1; /* 0x0000 */\r
+ unsigned SYSPC2; /* 0x0004 */\r
+ unsigned SYSPC3; /* 0x0008 */\r
+ unsigned SYSPC4; /* 0x000C */\r
+ unsigned SYSPC5; /* 0x0010 */\r
+ unsigned SYSPC6; /* 0x0014 */\r
+ unsigned SYSPC7; /* 0x0018 */\r
+ unsigned SYSPC8; /* 0x001C */\r
+ unsigned SYSPC9; /* 0x0020 */\r
+ unsigned SSWPLL1; /* 0x0024 */\r
+ unsigned SSWPLL2; /* 0x0028 */\r
+ unsigned SSWPLL3; /* 0x002C */\r
+ unsigned CSDIS; /* 0x0030 */\r
+ unsigned CSDISSET; /* 0x0034 */\r
+ unsigned CSDISCLR; /* 0x0038 */\r
+ unsigned CSDDIS; /* 0x003C */\r
+ unsigned CSDDISSET; /* 0x0040 */\r
+ unsigned CSDDISCLR; /* 0x0044 */\r
+ unsigned GHVSRC; /* 0x0048 */\r
+ unsigned VCLKASRC; /* 0x004C */\r
+ unsigned RCLKSRC; /* 0x0050 */\r
+ unsigned CSVSTAT; /* 0x0054 */\r
+ unsigned MSTGCR; /* 0x0058 */\r
+ unsigned MINITGCR; /* 0x005C */\r
+ unsigned MSINENA; /* 0x0060 */\r
+ unsigned MSTFAIL; /* 0x0064 */\r
+ unsigned MSTCGSTAT; /* 0x0068 */\r
+ unsigned MINISTAT; /* 0x006C */\r
+ unsigned PLLCTL1; /* 0x0070 */\r
+ unsigned PLLCTL2; /* 0x0074 */\r
+ unsigned UERFLAG; /* 0x0078 */\r
+ unsigned DIEIDL; /* 0x007C */\r
+ unsigned DIEIDH; /* 0x0080 */\r
+ unsigned VRCTL; /* 0x0084 */\r
+ unsigned LPOMONCTL; /* 0x0088 */\r
+ unsigned CLKTEST; /* 0x008C */\r
+ unsigned DFTCTRLREG1; /* 0x0090 */\r
+ unsigned DFTCTRLREG2; /* 0x0094 */\r
+ unsigned : 32U; /* 0x0098 */\r
+ unsigned : 32U; /* 0x009C */\r
+ unsigned GPREG1; /* 0x00A0 */\r
+ unsigned BTRMSEL; /* 0x00A4 */\r
+ unsigned IMPFASTS; /* 0x00A8 */\r
+ unsigned IMPFTADD; /* 0x00AC */\r
+ unsigned SSISR1; /* 0x00B0 */\r
+ unsigned SSISR2; /* 0x00B4 */\r
+ unsigned SSISR3; /* 0x00B8 */\r
+ unsigned SSISR4; /* 0x00BC */\r
+ unsigned RAMGCR; /* 0x00C0 */\r
+ unsigned BMMCR1; /* 0x00C4 */\r
+ unsigned BMMCR2; /* 0x00C8 */\r
+ unsigned MMUGCR; /* 0x00CC */\r
+#ifdef _little_endian__\r
+ unsigned : 8U; /* 0x00D0 */\r
+ unsigned PENA : 1U; /* 0x00D0 */\r
+ unsigned : 7U; /* 0x00D0 */\r
+ unsigned VCLKR : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLK2R : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+#else\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLK2R : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLKR : 4U; /* 0x00D0 */\r
+ unsigned : 7U; /* 0x00D0 */\r
+ unsigned PENA : 1U; /* 0x00D0 */\r
+ unsigned : 8U; /* 0x00D0 */\r
+#endif\r
+ unsigned : 32U; /* 0x00D4 */\r
+ unsigned DSPGCR; /* 0x00D8 */\r
+ unsigned DEVCR1; /* 0x00DC */\r
+ unsigned SYSECR; /* 0x00E0 */\r
+ unsigned SYSESR; /* 0x00E4 */\r
+ unsigned ITIFLAG; /* 0x00E8 */\r
+ unsigned GBLSTAT; /* 0x00EC */\r
+ unsigned DEV; /* 0x00F0 */\r
+ unsigned SSIVEC; /* 0x00F4 */\r
+ unsigned SSIF; /* 0x00F8 */\r
+} systemBASE1_t;\r
+\r
+\r
+/** @def systemREG1\r
+* @brief System Register Frame 1 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 1 registers.\r
+*/\r
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)\r
+\r
+\r
+/** @def PRE1\r
+* @brief Alias name for RTI1CLK PRE clock source\r
+*\r
+* This is an alias name for the RTI1CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define PRE1 SYS_PLL\r
+\r
+/** @def PRE2\r
+* @brief Alias name for RTI2CLK pre clock source\r
+*\r
+* This is an alias name for the RTI2CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define PRE2 SYS_PLL\r
+\r
+typedef volatile struct systemBase2\r
+{\r
+ unsigned PLLCTL3; /* 0x0000 */\r
+ unsigned : 32U; /* 0x0004 */\r
+ unsigned STCCLKDIV; /* 0x0008 */\r
+ unsigned CLKHB_GLBREG; /* 0x000C */\r
+ unsigned CLKHB_RTIDREG; /* 0x0010 */\r
+ unsigned HBCD_STAT; /* 0x0014 */\r
+ unsigned : 32U; /* 0x0018 */\r
+ unsigned : 32U; /* 0x001C */\r
+ unsigned CLKTRMI1; /* 0x0020 */\r
+ unsigned ECPCNTRL0; /* 0x0024 */\r
+ unsigned ECPCNTRL1; /* 0x0028 */\r
+ unsigned ECPCNTRL2; /* 0x002C */\r
+ unsigned ECPCNTRL3; /* 0x0030 */\r
+} systemBASE2_t;\r
+\r
+\r
+/** @def systemREG2\r
+* @brief System Register Frame 2 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 2 registers.\r
+*/\r
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)\r
+\r
+typedef volatile struct pcrBase\r
+{\r
+ unsigned PMPROTSET0; /* 0x0000 */\r
+ unsigned PMPROTSET1; /* 0x0004 */\r
+ unsigned : 32U; /* 0x0008 */\r
+ unsigned : 32U; /* 0x000C */\r
+ unsigned PMPROTCLR0; /* 0x0010 */\r
+ unsigned PMPROTCLR1; /* 0x0014 */\r
+ unsigned : 32U; /* 0x0018 */\r
+ unsigned : 32U; /* 0x001C */\r
+ unsigned PPROTSET0; /* 0x0020 */\r
+ unsigned PPROTSET1; /* 0x0024 */\r
+ unsigned PPROTSET2; /* 0x0028 */\r
+ unsigned PPROTSET3; /* 0x002C */\r
+ unsigned : 32U; /* 0x0030 */\r
+ unsigned : 32U; /* 0x0034 */\r
+ unsigned : 32U; /* 0x0038 */\r
+ unsigned : 32U; /* 0x003C */\r
+ unsigned PPROTCLR0; /* 0x0040 */\r
+ unsigned PPROTCLR1; /* 0x0044 */\r
+ unsigned PPROTCLR2; /* 0x0048 */\r
+ unsigned PPROTCLR3; /* 0x004C */\r
+ unsigned : 32U; /* 0x0050 */\r
+ unsigned : 32U; /* 0x0054 */\r
+ unsigned : 32U; /* 0x0058 */\r
+ unsigned : 32U; /* 0x005C */\r
+ unsigned PCSPWRDWNSET0; /* 0x0060 */\r
+ unsigned PCSPWRDWNSET1; /* 0x0064 */\r
+ unsigned : 32U; /* 0x0068 */\r
+ unsigned : 32U; /* 0x006C */\r
+ unsigned PCSPWRDWNCLR0; /* 0x0070 */\r
+ unsigned PCSPWRDWNCLR1; /* 0x0074 */\r
+ unsigned : 32U; /* 0x0078 */\r
+ unsigned : 32U; /* 0x007C */\r
+ unsigned PSPWRDWNSET0; /* 0x0080 */\r
+ unsigned PSPWRDWNSET1; /* 0x0084 */\r
+ unsigned PSPWRDWNSET2; /* 0x0088 */\r
+ unsigned PSPWRDWNSET3; /* 0x008C */\r
+ unsigned : 32U; /* 0x0090 */\r
+ unsigned : 32U; /* 0x0094 */\r
+ unsigned : 32U; /* 0x0098 */\r
+ unsigned : 32U; /* 0x009C */\r
+ unsigned PSPWRDWNCLR0; /* 0x00A0 */\r
+ unsigned PSPWRDWNCLR1; /* 0x00A4 */\r
+ unsigned PSPWRDWNCLR2; /* 0x00A8 */\r
+ unsigned PSPWRDWNCLR3; /* 0x00AC */\r
+} pcrBASE_t;\r
+\r
+/** @def pcrREG\r
+* @brief Pcr Register Frame Pointer\r
+*\r
+* This pointer is used by the system driver to access the Pcr registers.\r
+*/\r
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* CAN register definition */\r
+\r
+typedef volatile struct\r
+{\r
+ uint32 CTL;\r
+ uint32 SR;\r
+ unsigned : 16;\r
+ unsigned REC : 8;\r
+ unsigned TEC : 8;\r
+ uint32 BTR;\r
+ uint32 IR;\r
+ uint32 TR;\r
+ unsigned : 32;\r
+ uint32 PEC;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 ABOT;\r
+ uint32 TRX;\r
+ uint32 TRx[4];\r
+ uint32 NDX;\r
+ uint32 NDx[4];\r
+ uint32 IPX;\r
+ uint32 IPx[4];\r
+ uint32 MVX;\r
+ uint32 MVx[4];\r
+ unsigned : 32;\r
+ uint32 IPMx[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ struct\r
+ {\r
+ uint32 COM;\r
+ uint32 MASK;\r
+ uint32 ARB;\r
+ uint32 MC;\r
+ uint8 DATx[8];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ } IFx[3];\r
+ uint32 IF3UEy[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 IOTX;\r
+ uint32 IORX;\r
+} Can_RegisterType;\r
+\r
+\r
+#define DCAN1_Base ((Can_RegisterType *)0xFFF7DC00)\r
+#define DCAN2_Base ((Can_RegisterType *)0xFFF7DE00)\r
+#define DCAN3_Base ((Can_RegisterType *)0xFFF7E000)\r
+\r
+\r
+\r
+typedef volatile struct gioBase\r
+{\r
+ unsigned GCR0; /**< 0x0000: Global Control Register */\r
+ unsigned PWDN; /**< 0x0004: Power Down Register */\r
+ unsigned INTDET; /**< 0x0008: Interrupt Detect Regsiter*/\r
+ unsigned POL; /**< 0x000C: Interrupt Polarity Register */\r
+ unsigned INTENASET; /**< 0x0010: Interrupt Enable Set Register */\r
+ unsigned INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */\r
+ unsigned LVLSET; /**< 0x0018: Interrupt Priority Set Register */\r
+ unsigned LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */\r
+ unsigned FLG; /**< 0x0020: Interrupt Flag Register */\r
+ unsigned OFFSET0; /**< 0x0024: Interrupt Offset A Register */\r
+ unsigned OFFSET1; /**< 0x0028: Interrupt Offset B Register */\r
+} gioBASE_t;\r
+\r
+\r
+/** @struct gioPort\r
+* @brief GIO Port Register Definition\r
+*/\r
+/** @typedef gioPORT_t\r
+* @brief GIO Port Register Type Definition\r
+*\r
+* This type is used to access the GIO Port Registers.\r
+*/\r
+typedef volatile struct gioPort\r
+{\r
+ unsigned DIR; /**< 0x0000: Data Direction Register */\r
+ unsigned DIN; /**< 0x0004: Data Input Register */\r
+ unsigned DOUT; /**< 0x0008: Data Output Register */\r
+ unsigned DSET; /**< 0x000C: Data Output Set Register */\r
+ unsigned DCLR; /**< 0x0010: Data Output Clear Register */\r
+ unsigned PDR; /**< 0x0014: Open Drain Regsiter */\r
+ unsigned PULDIS; /**< 0x0018: Pullup Disable Register */\r
+ unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */\r
+} gioPORT_t;\r
+\r
+\r
+/** @def gioREG\r
+* @brief GIO Register Frame Pointer\r
+*\r
+* This pointer is used by the GIO driver to access the gio module registers.\r
+*/\r
+#define gioREG ((gioBASE_t *)0xFFF7BC00U)\r
+\r
+/** @def gioPORTA\r
+* @brief GIO Port (A) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTA\r
+*/\r
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)\r
+\r
+/** @def gioPORTB\r
+* @brief GIO Port (B) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTB\r
+*/\r
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)\r
+\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+\r
+static inline void __disable_irq() {\r
+ __asm volatile("CPSID if");\r
+}\r
+static inline void __enable_irq() {\r
+ __asm volatile("CPSIE if");\r
+}\r
+\r
+static inline unsigned long _Irq_Save(void)\r
+{\r
+ register unsigned long val asm("r0");\r
+ asm("mrs r0, cpsr");\r
+ asm("and r0, r0, #0xC0"); // Mask the I and F bit of CPSR\r
+ __disable_irq();\r
+ return val;\r
+}\r
+\r
+static inline void _Irq_Restore(unsigned mask) {\r
+ if (mask & 0x80) {\r
+ __asm volatile("CPSID i");\r
+ } else {\r
+ __asm volatile("CPSIE i");\r
+ }\r
+ if (mask & 0x40) {\r
+ __asm volatile("CPSID f");\r
+ } else {\r
+ __asm volatile("CPSIE f");\r
+ }\r
+}\r
+\r
+#endif /* CORE_CR4_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include "internal.h"
+#include "task_i.h"
+#include "hooks.h"
+#include "irq.h"
+#include "core_cr4.h"
+
+extern TaskType Os_Arc_CreateIsr( void (*entry)(void ), uint8_t prio, const char *name );
+extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+
+
+static inline void Irq_Setup() {
+ vimREG->FIRQPR0 = 0x0;
+ vimREG->FIRQPR1 = 0x0;
+}
+
+void Irq_Init( void ) {
+ Irq_Setup();
+ Irq_Enable();
+}
+
+
+/**
+ *
+ * @param stack_p Ptr to the current stack.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+#define MAX_WAIT_COUNT 1000
+void *Irq_Entry( void *stack_p )
+{
+ uint32_t *stack;
+
+ // Get the active interrupt channel
+ volatile sint8 channel;
+ volatile uint32 c = 0;
+ do {
+ channel = IrqGetCurrentInterruptSource();
+ c++;
+ } while (channel < 0 && c < MAX_WAIT_COUNT);
+
+ if (c > 1) {
+ uint8 a = c;
+ }
+
+ if (c >= MAX_WAIT_COUNT) {
+ // No interrupt is pending
+ return stack_p;
+ }
+
+ // Special case for software interrupts.
+ if (channel == SSI) {
+ // Get the emulated interrupt channel.
+ channel = systemREG1->SSISR1;
+ }
+
+ stack = (uint32_t *)stack_p;
+ stack = Os_Isr(stack, (void *)Irq_VectorTable[channel]);
+
+ //Irq_Enable();
+ return stack;
+}
+
+/**
+ * Attach an ISR type 1 to the interrupt controller.
+ *
+ * @param entry
+ * @param int_ctrl
+ * @param vector
+ * @param prio
+ */
+void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
+
+ // TODO: Use NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio)); here
+}
+
+/**
+ * NVIC prio have priority 0-15, 0-highest priority.
+ * Autosar does it the other way around, 0-Lowest priority
+ *
+ * Autosar NVIC
+ * 31 0
+ * 30 0
+ * ..
+ * 0 15
+ * 0 15
+ * @param prio
+ * @return
+ */
+static inline int osPrioToCpuPio( uint8_t prio ) {
+ assert(prio<32);
+ prio = 31 - prio;
+ return (prio>>1);
+}
+
+/**
+ * Attach a ISR type 2 to the interrupt controller.
+ *
+ * @param tid
+ * @param int_ctrl
+ * @param vector
+ */
+void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {
+ OsPcbType *pcb;
+
+ pcb = os_find_task(tid);
+ Irq_VectorTable[vector] = (void *)pcb;
+ IrqActivateChannel(vector);
+
+ // TOdo replace NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio));
+}
+
+/**
+ * Generates a soft interrupt, ie sets pending bit.
+ * This could also be implemented using ISPR regs.
+ *
+ * @param vector
+ */
+void Irq_GenerateSoftInt( IrqType vector ) {
+ IrqActivateChannel(SSI);
+ systemREG1->SSISR1 = (0x75 << 8) | vector;
+}
+
+/**
+ * Get the current priority from the interrupt controller.
+ * @param cpu
+ * @return
+ */
+uint8_t Irq_GetCurrentPriority( Cpu_t cpu) {
+
+ uint8_t prio = 0;
+
+ // SCB_ICSR contains the active vector
+ return prio;
+}
+
+typedef struct {
+ uint32_t dummy;
+} exc_stack_t;
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef IRQ_TYPES_H\r
+#define IRQ_TYPES_H\r
+\r
+\r
+#define IrqGetCurrentInterruptSource() \\r
+ (((volatile sint8)vimREG->IRQIVEC) - 1)\r
+\r
+/** IrqActivateChannel turns the selected channel on in the VIM */\r
+#define IrqActivateChannel(_channel) \\r
+ if (_channel > 31) { \\r
+ vimREG->REQMASKSET1 |= (1 << (_channel - 32)); \\r
+ } else { \\r
+ vimREG->REQMASKSET0 |= (1 << _channel); \\r
+ }\r
+\r
+\r
+/** IrqDeactivateChannel turns the selected channel off in the VIM */\r
+#define IrqDeactivateChannel(_channel) \\r
+ if (_channel > 31) { \\r
+ vimREG->REQMASKCLR1 = (1 << (_channel - 32)); \\r
+ } else { \\r
+ vimREG->REQMASKCLR0 = (1 << _channel); \\r
+ }\r
+\r
+\r
+#define Irq_SOI() \\r
+ sint8 channel = IrqGetCurrentInterruptSource(); \\r
+ IrqDeactivateChannel(channel)\r
+\r
+\r
+#define Irq_EOI() \\r
+ IrqActivateChannel(channel)\r
+\r
+\r
+typedef enum {\r
+ ESM_LEVEL_0 = 0,\r
+ RESERVED = 1,\r
+ RTI_COMPARE_0,\r
+ RTI_COMPARE_1,\r
+ RTI_COMPARE_2,\r
+ RTI_COMPARE_3,\r
+ RTI_OVERFLOW_0,\r
+ RTI_OVERFLOW_1,\r
+ RTI_TIMEBASE,\r
+ DIO_LEVEL_0,\r
+ HET_LEVEL_0,\r
+ HET_TU_LEVEL_0,\r
+ MIBSP1_LEVEL_0,\r
+ LIN1_LEVEL_0,\r
+ MIBADC1_EVENT,\r
+ MIBADC1_GROUP_1,\r
+ CAN1_LEVEL_0,\r
+ RESERVED_0,\r
+ FR_LEVEL_0,\r
+ CRC_1,\r
+ ESM_LEVEL_1,\r
+ SSI = 21,\r
+ PMU,\r
+ DIO_LEVEL_1,\r
+ HET_LEVEL_1,\r
+ HET_TU_LEVEL_1,\r
+ MIBSP1_LEVEL_1,\r
+ LIN1_LEVEL_1,\r
+ MIBADC1_GROUP_2,\r
+ CAN1_LEVEL_1,\r
+ RESERVED_1,\r
+ MIBADC1_MAG,\r
+ FR_LEVEL_1,\r
+ DMA_FTCA,\r
+ DMA_LFSA,\r
+ CAN2_LEVEL_0,\r
+ DMM_LEVEL_0,\r
+ MIBSPI3_LEVEL_0,\r
+ MIBSPI3_LEVEL_1,\r
+ DMA_HBDC,\r
+ DMA_BTCA,\r
+ RESERVED_2,\r
+ CAN2_LEVEL_1,\r
+ DMM_LEVEL_1,\r
+ CAN1_IF_3,\r
+ CAN3_LEVEL_0,\r
+ CAN2_IF_3,\r
+ FPU,\r
+ FR_TU_STATUS,\r
+ LIN2_LEVEL_0,\r
+ MIBADC2_EVENT,\r
+ MIBADC2_GROUP_1,\r
+ FR_TOC,\r
+ MIBSPIP5_LEVEL_0,\r
+ LIN2_LEVEL_1,\r
+ CAN3_LEVEL_1,\r
+ MIBSPI5_LEVEL_1,\r
+ MIBADC2_GROUP_2,\r
+ FR_TU_ERROR,\r
+ MIBADC2_MAG,\r
+ CAN3_IF_3,\r
+ FR_TU_MPU,\r
+ FR_T1C,\r
+ NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS,\r
+} IrqType;\r
+\r
+/* Total number of interrupts and exceptions\r
+ */\r
+#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS 65\r
+\r
+typedef enum {\r
+ PERIPHERAL_CLOCK_AHB,\r
+ PERIPHERAL_CLOCK_APB1,\r
+ PERIPHERAL_CLOCK_APB2,\r
+ PERIPHERAL_CLOCK_CAN,\r
+ PERIPHERAL_CLOCK_DCAN1,\r
+ PERIPHERAL_CLOCK_DCAN2,\r
+ PERIPHERAL_CLOCK_DCAN3\r
+} McuE_PeriperalClock_t;\r
+\r
+typedef enum {\r
+ CPU_0=0,\r
+} Cpu_t;\r
+\r
+#endif /* IRQ_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CONTEXT_H_\r
+#define CONTEXT_H_\r
+\r
+\r
+#define SC_PATTERN 0xde\r
+#define LC_PATTERN 0xad\r
+\r
+/* Minimum alignment req */\r
+#define ARCH_ALIGN 4\r
+\r
+/* Small context (task swap==function call) */\r
+#define SAVE_NVGPR(_x,_y)\r
+#define RESTORE_NVGPR(_x,_y)\r
+\r
+/* Save volatile regs, NOT preserved by function calls */\r
+#define SAVE_VGPR(_x,_y)\r
+#define RESTORE_VGPR(_x,_y)\r
+\r
+/* Large context (interrupt) */\r
+#define SAVE_ALL_GPR(_x,_y)\r
+#define RESTORE_ALL_GPR(_x,_y)\r
+\r
+\r
+// NVREGS: r0+r1+r2+r3+r4+r5+r6+r7+r8+r9+r10+r11+r12+lr = 14*4 = 40\r
+#define NVGPR_SIZE 56\r
+// VGPR: 9*4 = 36\r
+//#define VGPR_SIZE 36\r
+// SP + context\r
+#define C_SIZE 8\r
+#define VGPR_LR_OFF (C_SIZE+NVGPR_SIZE-4)\r
+#define C_CONTEXT_OFFS 4\r
+#define C_SP_OFF 0\r
+#define SC_SIZE (NVGPR_SIZE+C_SIZE)\r
+\r
+\r
+\r
+#endif /* CONTEXT_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+ \r
+\r
+ .syntax unified\r
+ .cpu cortex-r4\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global Default_Handler\r
+\r
+/* Addresses used to setup RAM */\r
+.word _sidata\r
+.word _sdata\r
+.word _edata\r
+.word _sbss\r
+.word _ebss\r
+\r
+/* The address of the stack to use in all modes. */\r
+.word _estack\r
+\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+\r
+Reset_Handler:\r
+\r
+/* Set big endian state */\r
+ SETEND BE\r
+\r
+/* Initialize core registers.\r
+ This is done to avoid mismatch between lockstep CPU and ordinary CPU\r
+*/\r
+ mov r0, #0x0000\r
+ mov r1, #0x0000\r
+ mov r2, #0x0000\r
+ mov r3, #0x0000\r
+ mov r4, #0x0000\r
+ mov r5, #0x0000\r
+ mov r6, #0x0000\r
+ mov r7, #0x0000\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ mov r1, #0x03D0\r
+ orr r2, r1, #0x0001\r
+ msr cpsr_cxsf, r2\r
+ msr spsr_cxsf, r2\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ orr r12, r1, #0x0002\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0007\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x000B\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0003\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+\r
+/* System level configuration\r
+ This mainly involves setting instruction mode for exceptions and interrupts.\r
+*/\r
+ mrc p15,0,r11,c1,c0,0 /* Read current system configuration */\r
+ mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */\r
+ orr r12, r12, r11\r
+ mcr p15,0,r12,c1,c0,0 /* Write new configuration */\r
+\r
+\r
+/* Initialize stack pointers.\r
+ This is done for all processor modes. Note that we only use one stack pointer.\r
+ In reality this means that no mode except USER and SYS is allowed to do anythin on the stack.\r
+ IRQ mode handles its own stack in the interrupt routine.\r
+*/\r
+ mov r2, #0xD1\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD2\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD7\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xDB\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD3\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+\r
+/* Initialize RAM.\r
+ First the initialized RAM is copied from flash to RAM.\r
+ Then the zeroed RAM is erased.\r
+*/\r
+ ldr r0, =_sdata /* r0 holds start of data in ram */\r
+ ldr r3, =_edata /* r3 holds end of data in ram */\r
+ ldr r5, =_sidata /* r5 start of data in flash */\r
+ movs r1, #0 /* r1 is the counter */\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r4, [r5, r1] /* read current position in flash */\r
+ str r4, [r0, r1] /* store current position in ram */\r
+ adds r1, r1, #4 /* increment counter */\r
+ \r
+LoopCopyDataInit:\r
+ adds r2, r0, r1 /* are we at the final position? */\r
+ cmp r2, r3 /* ... */\r
+ bcc CopyDataInit /* nope, continue */\r
+\r
+/* Fill zero areas */\r
+ ldr r2, =_sbss /* r2 holds the start address */\r
+ ldr r5, =_ebss /* r5 holds the end address */\r
+ bl LoopFillZero\r
+\r
+ ldr r2, =_sstack /* r2 holds the start address */\r
+ ldr r5, =_estack /* r5 holds the end address */\r
+ bl LoopFillZero\r
+\r
+/* Call the application's entry point.*/\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ bl main\r
+ bx lr\r
+\r
+/* Zero fill the bss segment. */ \r
+FillZero:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZero:\r
+ cmp r2, r5\r
+ bcc FillZero\r
+ bx lr\r
+\r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+\r
+\r
+\r
+/******************************************************************************\r
+* Interrupt and exception vectors. Vectors start at addr 0x0.\r
+******************************************************************************/ \r
+ .section .int_vecs,"ax",%progbits\r
+ .extern Irq_Handler\r
+ .extern Svc_Handler\r
+ .extern Data_Exc_Handler\r
+ .extern Prefetch_Exc_Handler\r
+ .extern Dummy_Irq\r
+\r
+ /* This is the reset handler. Since the CPU is in ARM mode when this instruction is executed\r
+ it has to be hard coded (otherwise it will compile wrong).\r
+ Instruction branches to address 0x22 while changing instruction mode to THUMB. */\r
+ .word 0xfb000006\r
+\r
+ b Dummy_Irq /* Undefined instruction exception */\r
+ b Dummy_Irq /* SVC */\r
+ b Prefetch_Exc_Handler /* Prefetch exception */\r
+ b Data_Exc_Handler /* Data exception */\r
+ b Dummy_Irq /* Reserved */\r
+ b Irq_Handler /* Ordinary interrupts (IRQ) */\r
+ b Dummy_Irq /* Fast interrupts (FIR) */\r
+\r
+ nop\r
+ b Reset_Handler /* Branch to the real reset handler. */\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Os.h"\r
+#include "internal.h"\r
+#include "core_cr4.h"\r
+#include "irq.h"\r
+#include "arc.h"\r
+\r
+#define RTICLK_PRESCALER 10\r
+\r
+void CortexR4OsTick() {\r
+ /** Clear all pending interrupts\r
+ * otherwise this will hit again\r
+ * as soon as interrupts are re-enabled. */\r
+ rtiREG1->INTFLAG = 0x1;\r
+\r
+ // Call regular OsTick.\r
+ OsTick();\r
+}\r
+\r
+/**\r
+ * Init of free running timer.\r
+ */\r
+void Os_SysTickInit( void ) {\r
+ TaskType tid;\r
+ tid = Os_Arc_CreateIsr(CortexR4OsTick,6,"OsTick");\r
+ Irq_AttachIsr2(tid,NULL, RTI_COMPARE_0);\r
+}\r
+\r
+\r
+static inline uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+\r
+ /** - Setup NTU source, debug options and disable both counter blocks */\r
+ rtiREG1->GCTRL = 0x0;\r
+\r
+ /** - Setup timebase for free running counter 0 */\r
+ rtiREG1->TBCTRL = 0x0;\r
+\r
+ /** - Enable/Disable capture event sources for both counter blocks */\r
+ rtiREG1->CAPCTRL = 0x0;\r
+\r
+ /** - Setup input source compare 0-3 */\r
+ rtiREG1->COMPCTRL = 0x0;\r
+\r
+ /** - Reset up counter 0 */\r
+ rtiREG1->CNT[0U].UCx = 0x00000000U;\r
+\r
+ /** - Reset free running counter 0 */\r
+ rtiREG1->CNT[0U].FRCx = 0x00000000U;\r
+\r
+ /** - Setup up counter 0 compare value\r
+ * The RTI module is driven by RTICLK. With the Arctic Core\r
+ * MCU driver for cortex R4 RTICLK = VCLK = PLLCLK / 2\r
+ * ticks = number of PLLCLK cycles per os tick = number of RTICLK cycles * 2 per os tick\r
+ *\r
+ * - 0x00000000: Divide by 2^32\r
+ * - 0x00000001-0xFFFFFFFF: Divide by (CPUCx + 1)\r
+ */\r
+ rtiREG1->CNT[0U].CPUCx = RTICLK_PRESCALER - 1;\r
+\r
+ uint8 vclkDiv = systemREG1->VCLKR + 1;\r
+\r
+ /** - Setup compare 0 value. This value is compared with selected free running counter. */\r
+ rtiREG1->CMP[0U].COMPx = ticks / (RTICLK_PRESCALER * vclkDiv);\r
+\r
+ /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */\r
+ rtiREG1->CMP[0U].UDCPx = ticks / (RTICLK_PRESCALER * vclkDiv);\r
+\r
+ /** - Clear all pending interrupts */\r
+ rtiREG1->INTFLAG = 0x0;\r
+\r
+ /** - Disable all interrupts */\r
+ rtiREG1->CLEARINT = 0x0;\r
+\r
+ return (0);\r
+}\r
+\r
+/**\r
+ * Start the Sys Tick timer\r
+ *\r
+ * @param period_ticks How long the period in timer ticks should be.\r
+ *\r
+ */\r
+void Os_SysTickStart(uint32_t period_ticks) {\r
+\r
+ /* Cortex-M3 have a 24-bit system timer that counts down\r
+ * from the reload value to zero.\r
+ */\r
+\r
+ SysTick_Config(period_ticks);\r
+ rtiREG1->GCTRL = 0x1;\r
+ rtiREG1->SETINT = 0x1;\r
+\r
+}\r
+\r
+/**\r
+ * @return\r
+ */\r
+\r
+uint32_t Os_SysTickGetValue( void )\r
+{\r
+ //return (SysTick->LOAD) - (SysTick->VAL);\r
+ return 0;\r
+}\r
+\r
+\r
+TickType Os_SysTickGetElapsedValue( uint32_t preValue ) {\r
+ uint32_t curr;\r
+ uint32_t max;\r
+\r
+ /*\r
+ curr = (SysTick->VAL);\r
+ max = (SysTick->LOAD);\r
+ */\r
+ curr = 0;\r
+ max = 0;\r
+ return Os_CounterDiff((max - curr),preValue,max);\r
+}\r
+\r
--- /dev/null
+\r
+# prefered version\r
+CC_VERSION=4.4.5\r
+# ARMv7, Thumb-2, little endian, soft-float. \r
+cflags-y += -mthumb -mcpu=cortex-r4 -mbig-endian\r
+cflags-y += -ggdb\r
+\r
+lib-y += -lgcc -lc\r
+ASFLAGS += -mthumb -mcpu=cortex-r4 -mbig-endian\r
+\r
+LDFLAGS +=
\ No newline at end of file
--- /dev/null
+/* \r
+ * Copyright (C) ArcCore AB <contact@arccore.com>\r
+ *\r
+ * ST startup variables: \r
+ * _sidata - Start of .data in flash \r
+ * _sdata - start address of .data in RAM\r
+ * _edata - end address of .data in RAM\r
+ * _sbss - start address of .bss\r
+ * _ebss - end address of .bss\r
+ * _etext - ?\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-bigarm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(Reset_Handler)\r
+\r
+#include "Calibration_Settings.h"\r
+\r
+MEMORY\r
+{\r
+#include "memory.ldf"\r
+}\r
+\r
+SECTIONS\r
+{\r
+\r
+ .int_vecs :\r
+ {\r
+ KEEP(*(.int_vecs))\r
+ } > intvecs\r
+\r
+ .text :\r
+ {\r
+ *(.text .text.* );\r
+ *(.glue_7) /* TODO */\r
+ *(.glue_7t) /* TODO */\r
+ \r
+ PROVIDE( btask_sup_matrix = .);\r
+ SORT(*)(.test_btask);\r
+ PROVIDE( etask_sup_matrix = .);\r
+ SORT(*)(.test_etask);\r
+ \r
+ /* ST/ARM special variable to initialize .data */\r
+ _etext = .;\r
+ } > flash\r
+\r
+ /* Relocatable Flash Driver */\r
+ .fls_rom : {\r
+ __FLS_ERASE_ROM__ = .;\r
+ *(.fls_erase);\r
+ __FLS_WRITE_ROM__ = .;\r
+ *(.fls_write);\r
+ __FLS_END_ROM__ = .;\r
+ } > flash\r
+\r
+ /* ARM exception section */\r
+ .ARM.exidx : { \r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > flash\r
+ __exidx_start = .;\r
+\r
+ /* Read-only data section. */\r
+ .rodata : { \r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
+ _sidata = ALIGN(.,4);\r
+ } > flash\r
+ \r
+ .cio ALIGN(0x10) : {\r
+ \r
+ } > ram\r
+#ifdef CALIBRATION_ACTIVE\r
+ .calibration : AT(ORIGIN(flash_calibration_area_0)) {\r
+ __CALIB_RAM_START = .;\r
+ *(.calibration)\r
+ __CALIB_RAM_END = .;\r
+ } > ram\r
+ __CALIB_ROM_START = ORIGIN(flash_calibration_area_0);\r
+#endif\r
+ .data : AT(ALIGN(LOADADDR(.rodata)+SIZEOF(.rodata),4)) {\r
+ _sdata = ALIGN(.,4); \r
+ *(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ _edata = ALIGN(.,4); \r
+ } > ram\r
+\r
+ .t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
+ .bss : {\r
+ _sbss = ., \r
+ *(.bss .bss.* COMMON .gnu.linkonce.b.*);\r
+ _ebss = .; \r
+ } > ram\r
+ \r
+ .init_stack ALIGN(16) (NOLOAD) : \r
+ { \r
+ _sstack = .;\r
+ . = . + 8000; \r
+ _estack = .; \r
+ . = . + 1;\r
+ . = ALIGN(4);\r
+ } > ram\r
+ \r
+ /* Fls RAM section */\r
+ .fls_ram ALIGN(16) (NOLOAD) : {\r
+ __FLS_ERASE_RAM__ = .;\r
+ . = . + SIZEOF(.fls_rom);\r
+ } > ram\r
+\r
+ .ctors :\r
+ {\r
+ KEEP (*(SORT(.ctors.*)))\r
+ }\r
+\r
+ .uninit ALIGN(0x10) (NOLOAD) : { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
+\r
+\r
+ __FLS_SIZE__ = SIZEOF(.fls_rom);\r
+ __FLS_WRITE_RAM__ = __FLS_ERASE_RAM__ + (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
+__EXCEPT_START__ = 0x0;\r
+__EXCEPT_END__ = 0x0;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
\r
}\r
\r
-void Irq_EOI( void ) {\r
-\r
-}\r
\r
// IRQ debug information\r
// Stores irq nr on erroneous interrupt\r
#ifndef IRQ_TYPES_H\r
#define IRQ_TYPES_H\r
\r
+#define Irq_SOI()\r
+#define Irq_EOI()\r
+\r
#include "irq_defines.h"\r
\r
#define DECLARE_IRQ_PROTOTYPE(x) \\r
\r
}\r
\r
-\r
void Irq_EOI( void ) {\r
#if defined(CFG_MPC5516)\r
struct INTC_tag *intc = &INTC;\r
#define IRQ_TYPES_H\r
\r
\r
+#define Irq_SOI()\r
+\r
+/**\r
+ * End-Of-Interrupt. Called by the OS it wants to clear the interrupt.\r
+ */\r
+void Irq_EOI( void );\r
+\r
+\r
typedef enum\r
{\r
/* Software interrupts. */\r
obj-$(CFG_ARM_CM3)-$(USE_PWM) += stm32f10x_tim.o\r
obj-$(CFG_ARM_CM3)-$(USE_LWIP) += stm32_eth.o\r
\r
+obj-$(USE_TTY_TMS570_KEIL) += GLCD.o\r
+obj-$(USE_TTY_TMS570_KEIL) += emif.o\r
\r
+# Cortex R4\r
+obj-$(CFG_ARM_CR4) += startup_cr4.o\r
\r
# OS object files. \r
# (checking if already included for compatability)\r
--- /dev/null
+\r
+\r
+The Texas Instruments TMS570LS is an ARM 32-bit Cortes-R4 microcontroller.\r
+\r
+ \r
+Datasheets: \r
+ http://focus.ti.com/lit/ug/spnu489a/spnu489a.pdf \r
+
\ No newline at end of file
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cr4\r
+ARCH_FAM=arm\r
+ARCH_MCU=tms570ls\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CR4\r
+# Add our board \r
+CFG+= \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_CL\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+MOD_AVAIL+=MCU\r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE CAN\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
--- /dev/null
+#undef CALIBRATION_ACTIVE\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Oct 25 12:52:40 CEST 2010\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 4, // REFCLKDIV\r
+ .Pll2 = 100, // PLLMULT\r
+ .Pll3 = 2, // ODPLL\r
+ .Pll4 = 2, // PLLDIV\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+#endif
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
+typedef struct {
+ uint32 AHBClocksEnable;
+ uint32 APB1ClocksEnable;
+ uint32 APB2ClocksEnable;
+} Mcu_PerClockConfigType;
+
+extern const Mcu_PerClockConfigType McuPerClockConfigData;
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_25MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+\r
+intvecs(R) : ORIGIN = 0x0000000, LENGTH = 0x60\r
+flash(R) : ORIGIN = 0x00000060, LENGTH = 2M\r
+ram(RW) : ORIGIN = 0x08000000, LENGTH = 160K\r
+flash_calibration_area_0(R) : ORIGIN = 0x00004000, LENGTH = 48K
\ No newline at end of file
\r
#endif\r
\r
+#ifdef USE_TTY_CODE_COMPOSER\r
+\r
+#define _DTOPEN (0xF0)\r
+#define _DTCLOSE (0xF1)\r
+#define _DTREAD (0xF2)\r
+#define _DTWRITE (0xF3)\r
+#define _DTLSEEK (0xF4)\r
+#define _DTUNLINK (0xF5)\r
+#define _DTGETENV (0xF6)\r
+#define _DTRENAME (0xF7)\r
+#define _DTGETTIME (0xF8)\r
+#define _DTGETCLK (0xF9)\r
+#define _DTSYNC (0xFF)\r
+\r
+#define LOADSHORT(x,y,z) { x[(z)] = (unsigned short) (y); \\r
+ x[(z)+1] = (unsigned short) (y) >> 8; }\r
+\r
+#define UNLOADSHORT(x,z) ((short) ( (short) x[(z)] + \\r
+ ((short) x[(z)+1] << 8)))\r
+\r
+#define PACKCHAR(val, base, byte) ( (base)[(byte)] = (val) )\r
+\r
+#define UNPACKCHAR(base, byte) ( (base)[byte] )\r
+\r
+\r
+static unsigned char parmbuf[8];\r
+#define BUFSIZ 512\r
+#define CC_BUFFER_SIZE ((BUFSIZ)+32)\r
+volatile unsigned int _CIOBUF_[CC_BUFFER_SIZE] __attribute__ ((section (".cio")));\r
+\r
+/***************************************************************************/\r
+/* */\r
+/* WRITEMSG() - Sends the passed data and parameters on to the host. */\r
+/* */\r
+/***************************************************************************/\r
+void writemsg(unsigned char command,\r
+ register const unsigned char *parm,\r
+ register const char *data,\r
+ unsigned int length)\r
+{\r
+ volatile unsigned char *p = (volatile unsigned char *)(_CIOBUF_+1);\r
+ unsigned int i;\r
+\r
+ /***********************************************************************/\r
+ /* THE LENGTH IS WRITTEN AS A TARGET INT */\r
+ /***********************************************************************/\r
+ _CIOBUF_[0] = length;\r
+\r
+ /***********************************************************************/\r
+ /* THE COMMAND IS WRITTEN AS A TARGET BYTE */\r
+ /***********************************************************************/\r
+ *p++ = command;\r
+\r
+ /***********************************************************************/\r
+ /* PACK THE PARAMETERS AND DATA SO THE HOST READS IT AS BYTE STREAM */\r
+ /***********************************************************************/\r
+ for (i = 0; i < 8; i++) PACKCHAR(*parm++, p, i);\r
+ for (i = 0; i < length; i++) PACKCHAR(*data++, p, i+8);\r
+\r
+ /***********************************************************************/\r
+ /* THE BREAKPOINT THAT SIGNALS THE HOST TO DO DATA TRANSFER */\r
+ /***********************************************************************/\r
+ __asm(" .global C$$IO$$");\r
+ __asm("C$$IO$$: nop");\r
+}\r
+\r
+/***************************************************************************/\r
+/* */\r
+/* READMSG() - Reads the data and parameters passed from the host. */\r
+/* */\r
+/***************************************************************************/\r
+void readmsg(register unsigned char *parm,\r
+ register char *data)\r
+{\r
+ volatile unsigned char *p = (volatile unsigned char *)(_CIOBUF_+1);\r
+ unsigned int i;\r
+ unsigned int length;\r
+\r
+ /***********************************************************************/\r
+ /* THE LENGTH IS READ AS A TARGET INT */\r
+ /***********************************************************************/\r
+ length = _CIOBUF_[0];\r
+\r
+ /***********************************************************************/\r
+ /* UNPACK THE PARAMETERS AND DATA */\r
+ /***********************************************************************/\r
+ for (i = 0; i < 8; i++) *parm++ = UNPACKCHAR(p, i);\r
+ if (data != NULL)\r
+ for (i = 0; i < length; i++) *data++ = UNPACKCHAR(p, i+8);\r
+}\r
+\r
+/****************************************************************************/\r
+/* HOSTWRITE() - Pass the write command and its arguments to the host. */\r
+/****************************************************************************/\r
+int HOSTwrite(int dev_fd, const char *buf, unsigned count)\r
+{\r
+ int result;\r
+\r
+ if (count > BUFSIZ) count = BUFSIZ;\r
+\r
+ LOADSHORT(parmbuf,dev_fd,0);\r
+ LOADSHORT(parmbuf,count,2);\r
+ writemsg(_DTWRITE,parmbuf,(char *)buf,count);\r
+ readmsg(parmbuf,NULL);\r
+\r
+ result = UNLOADSHORT(parmbuf,0);\r
+\r
+ return result;\r
+}\r
+\r
+#endif\r
+\r
+#ifdef USE_TTY_TMS570_KEIL\r
+#include "GLCD.h"\r
+#endif\r
+\r
#define FILE_RAMLOG 3\r
\r
/* Location MUST match NoICE configuration */\r
}\r
#endif\r
\r
+#ifdef USE_TTY_CODE_COMPOSER\r
+ HOSTwrite(fd, _buf, nbytes);\r
+#endif\r
+\r
+#ifdef USE_TTY_TMS570_KEIL\r
+ for (int i = 0; i < nbytes; i++) {\r
+ GLCD_PrintChar((_buf + i));\r
+ }\r
+#endif\r
+\r
#if defined(USE_RAMLOG)\r
{\r
char *buf = (char *)_buf;\r
}\r
#if defined(CFG_ARM)\r
void _exit( int status ) {\r
+#ifdef USE_TTY_CODE_COMPOSER\r
+ __asm(" .global C$$EXIT");\r
+ __asm("C$$EXIT: nop");\r
+#endif\r
while(1);\r
}\r
#endif\r
putc(c, stdout);\r
fflush(stdout);\r
#else\r
- arc_putchar(file->_cookie, c);\r
+ arc_putchar((int)file, c);\r
#endif\r
} else {\r
**buf = c;\r
\r
\r
#ifndef CFG_RAMLOG_SIZE\r
-#define CFG_RAMLOG_SIZE 2000\r
+#define CFG_RAMLOG_SIZE 20000\r
#endif\r
\r
#define RAMLOG_MAGIC 1\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>tiny_arm_cr4</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="7c3c165c-c7e6-458b-a18c-d0e7b89c6a2d">\r
+ <SHORT-NAME>tiny_arm_cr4</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/tiny_arm_cr4/SwComposition_tiny_arm_cr4</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tiny_arm_cr4/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="8e93c90b-a011-4edc-9f6b-a4927f5b499a">\r
+ <SHORT-NAME>SwComposition_tiny_arm_cr4</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="d9b75d00-e6eb-4671-a7cf-0abd1e1ed6a7">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="5ceca27a-71ff-4c71-bcb8-69a1f31f5d79">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="185f3281-13f7-459b-9ccd-66eb1aff52ca">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4c1d9bd6-69e7-48c8-8036-35c6279f2240">\r
+ <SHORT-NAME>etask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fbcd933e-5944-44dd-ac92-f9eace6bb55c">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="41f28680-c88e-4083-bacc-40cf82ec3122">\r
+ <SHORT-NAME>etask_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="53d449ae-bdbe-49cb-bb22-141480e62565">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b5120b2f-2b4e-4e0f-8a7f-c7466b489644">\r
+ <SHORT-NAME>btask_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="759524bb-836c-4d61-b59a-cf8edfb6e162">\r
+ <SHORT-NAME>Alarm_4ms</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cr4/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="45cda08c-e07f-4670-8f14-b85acb209a6f">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5801fbe7-6b9b-4390-9341-2dd9ab4412f5">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cr4/Os/EVENT_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cr4/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f289efa7-5957-47a1-9c32-2248195ca090">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6dde7c3-6596-4a33-96ab-3a43d4ab1429">\r
+ <SHORT-NAME>EVENT_0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d93f5687-240e-465d-afb4-da563598d37a">\r
+ <SHORT-NAME>EVENT_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="94eef554-c26c-44d5-9b8f-501597b53d51">\r
+ <SHORT-NAME>EVENT_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
#include "Mcu.h"\r
#endif\r
\r
+\r
typedef struct {\r
uint32 txSuccessCnt;\r
uint32 rxSuccessCnt;\r
MCU_POWER_ON_RESET,\r
MCU_WATCHDOG_RESET,\r
MCU_SW_RESET,\r
- MCU_RESET_UNDEFINED\r
+ MCU_RESET_UNDEFINED,\r
+ MCU_OSC_FAILURE_RESET,\r
+ MCU_CPU_RESET,\r
+ MCU_EXT_RESET,\r
+ MCU_VSW_RESET\r
} Mcu_ResetType;\r
\r
typedef struct {\r
uint8 Pll1; // PLL setting 1\r
uint8 Pll2; // PLL setting 2\r
uint8 Pll3; // PLL setting 3\r
+ uint8 Pll4; // PLL setting 4\r
\r
} Mcu_ClockSettingConfigType;\r
\r
void Irq_GenerateSoftInt( IrqType vector );\r
uint8_t Irq_GetCurrentPriority( Cpu_t cpu);\r
uint32_t McuE_GetSystemClock( void );\r
-#if defined(CFG_MPC55XX)\r
+#if defined(CFG_MPC55XX) || defined(CFG_ARM_CR4)\r
uint32_t McuE_GetPeripheralClock( McuE_PeriperalClock_t type );\r
#endif\r
#include "McuExtensions.h"\r
/* Contain the current state of the PDU router. The router is uninitialized\r
* until PduR_Init has been run.\r
*/\r
-PduR_StateType PduRState;\r
+//PduR_StateType PduRState;\r
\r
extern const PduR_PBConfigType *PduRConfig;\r
\r
#define CPU_BIT_ORDER MSB_FIRST \r
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST\r
\r
+#if !defined(FALSE)\r
#define FALSE 0\r
#define TRUE 1\r
+#endif\r
\r
typedef unsigned long boolean; \r
typedef signed char sint8; \r
#define CPU_H_
#include <stdint.h>
-#include "stm32f10x.h"
+
+#if defined(CFG_ARM_CM3)
#include "core_cm3.h"
+#elif defined(CFG_ARM_CR4)
+#include "core_cr4.h"
+#endif
-/* Call intrinsic functions directly */
-#define Irq_Disable() __disable_irq()
-#define Irq_Enable() __enable_irq()
+/* Call architecture specific code */
+#define Irq_Disable() __disable_irq()
+#define Irq_Enable() __enable_irq()
-#define Irq_Save(_flags) _flags = _Irq_Save();
+#define Irq_Save(_flags) _flags = _Irq_Save();
#define Irq_Restore(_flags) _Irq_Restore(_flags);
#define Irq_SuspendAll() Irq_Disable()
#define Irq_ResumeAll() Irq_Enable()
#define Irq_SuspendOs() Irq_Disable()
-#define Irq_ResumeOs() Irq_Enable()
-
-static inline unsigned long _Irq_Save(void)
-{
- unsigned long val = __get_PRIMASK();
- Irq_Disable();
- return val;
-}
-
-/*-----------------------------------------------------------------*/
+#define Irq_ResumeOs() Irq_Enable()
-static inline void _Irq_Restore(unsigned mask) {
- __set_PRIMASK(mask);
-}
#define CallService(index,param)
*/\r
void Irq_Init( void );\r
\r
-/**\r
- * End-Of-Interrupt. Called by the OS it wants to clear the interrupt.\r
- */\r
-void Irq_EOI( void );\r
+\r
+\r
\r
#if defined(CFG_HC1X)\r
/**\r
* @param type\r
*/\r
static inline void Irq_SetIsrType( IrqType vector, IsrType type ) {\r
- Irq_IsrTypeTable[vector + IRQ_INTERRUPT_OFFSET ] = type;\r
+ Irq_IsrTypeTable[vector] = type;\r
}\r
\r
/**\r
* 1 - Isr2\r
*/\r
static inline IsrType Irq_GetIsrType( IrqType vector ) {\r
- return Irq_IsrTypeTable[vector + IRQ_INTERRUPT_OFFSET ];\r
+ return Irq_IsrTypeTable[vector];\r
}\r
\r
\r
\r
if( alarm_id >= Os_CfgGetAlarmCnt() ) {\r
rv = E_OS_ID;\r
- }\r
+ } else {\r
#if (OS_ALARM_CNT!=0)\r
- *info = alarm_list[alarm_id].counter->alarm_base;\r
+ *info = alarm_list[alarm_id].counter->alarm_base;\r
#endif\r
+ }\r
return rv;\r
}\r
\r
// Enable interrupts\r
Irq_Init();\r
\r
-\r
// Determine PostBuild configuration\r
internal_data.config = EcuM_DeterminePbConfiguration();\r
\r
assert(0);
}
-#ifndef CFG_HCS12D
+ Irq_SOI();
+
+#if !defined(CFG_HCS12D)
Irq_Enable();
isrPtr->entry();
Irq_Disable();
pos 1. 1. 14.\r
text "CPU:"\r
pos 1. 2. 10.\r
-CPU: PULLDOWN "mpc5516,mpc5554,mpc5633M,CortexM3,HC12DG128A"\r
+CPU: PULLDOWN "mpc5516,mpc5554,mpc5633M,CortexM3,CortexR4F,HC12DG128A"\r
(\r
)\r
HEADER "Project config"\r
postload_HC12DG128A:\r
RETURN\r
\r
+postload_CortexR4F:\r
+ RETURN\r
+\r
//-------------------------------------------------------------\r
\r
path_fast:\r
projects / arc.git / commitdiff