--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#include "Dma.h"\r
+\r
+const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_A_SR_TFFF\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_A_SR_RFRD\r
+ },\r
+ {\r
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_B_SR_TFFF\r
+ },\r
+ {
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_DSPI_B_SR_RFRD
+ },
+ {
+ .DMA_CHANNEL_ENABLE = 1, .DMA_CHANNEL_TRIG_ENABLE = 0, .DMA_CHANNEL_SOURCE = DMA_ADC_A
+ }
+};\r
+\r
+const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_A_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {\r
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1\r
+ },\r
+ {
+ .DMA_CHANNEL_PRIORITY = DMA_DSPI_B_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
+ },
+ {
+ .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1
+ }
+};\r
+\r
+\r
+const Dma_ConfigType DmaConfig []=\r
+{
+ {
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5606S)\r
+ DmaMuxConfig,
+#endif
+ DmaChannelConfig,
+ DMA_FIXED_PRIORITY_ARBITRATION
+ }
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DMA_CFG_H_\r
+#define DMA_CFG_H_\r
+\r
+typedef enum\r
+{
+ DMA_DSPI_A_COMMAND_CHANNEL,\r
+ DMA_DSPI_A_RESULT_CHANNEL,\r
+ DMA_DSPI_B_COMMAND_CHANNEL,\r
+ DMA_DSPI_B_RESULT_CHANNEL,\r
+
+ DMA_ADC_GROUP0_RESULT_CHANNEL,
+
+ DMA_NUMBER_OF_CHANNELS\r
+} Dma_ChannelType;\r
+\r
+#endif /* DMA_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Fls.h"\r
+#include "flash.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#if defined(CFG_MPC5668)\r
+ /* RWW between partitions*\r
+ *\r
+ * LOW 8*16KB + 2*64KB = 256KB\r
+ * MID 2*128KB = 256KB\r
+ * HIGH 6*256KB = 1.5MB\r
+ */\r
+\r
+const FlashType flashInfo[] = {\r
+ [0].sectCnt = 18,\r
+ [0].bankSize = 0x200000,\r
+ [0].regBase = 0xffff8000UL,\r
+\r
+ /* LOW */\r
+ [0].sectAddr[0] = 0,\r
+ [0].addrSpace[0] = ADDR_SPACE(0, ADDR_SPACE_LOW, 1 ),\r
+ [0].sectAddr[1] = 0x00004000,\r
+ [0].addrSpace[1] = ADDR_SPACE(1, ADDR_SPACE_LOW, 1 ),\r
+ [0].sectAddr[2] = 0x00008000,\r
+ [0].addrSpace[2] = ADDR_SPACE(2, ADDR_SPACE_LOW, 1 ),\r
+ [0].sectAddr[3] = 0x0000c000,\r
+ [0].addrSpace[3] = ADDR_SPACE(3, ADDR_SPACE_LOW, 1 ),\r
+ [0].sectAddr[4] = 0x00010000,\r
+ [0].addrSpace[4] = ADDR_SPACE(4, ADDR_SPACE_LOW, 2 ),\r
+ [0].sectAddr[5] = 0x00014000,\r
+ [0].addrSpace[5] = ADDR_SPACE(5, ADDR_SPACE_LOW, 2 ),\r
+ [0].sectAddr[6] = 0x00018000,\r
+ [0].addrSpace[6] = ADDR_SPACE(6, ADDR_SPACE_LOW, 2 ),\r
+ [0].sectAddr[7] = 0x0001c000,\r
+ [0].addrSpace[7] = ADDR_SPACE(7, ADDR_SPACE_LOW, 2 ),\r
+ [0].sectAddr[8] = 0x00020000,\r
+ [0].addrSpace[8] = ADDR_SPACE(8, ADDR_SPACE_LOW, 3 ),\r
+ [0].sectAddr[9] = 0x00030000,\r
+ [0].addrSpace[9] = ADDR_SPACE(9, ADDR_SPACE_LOW, 3 ),\r
+\r
+ /* MID */\r
+ [0].sectAddr[10] = 0x00040000,\r
+ [0].addrSpace[10] = ADDR_SPACE(0, ADDR_SPACE_MID, 4 ),\r
+ [0].sectAddr[11] = 0x00060000,\r
+ [0].addrSpace[11] = ADDR_SPACE(1, ADDR_SPACE_MID, 4 ),\r
+\r
+ /* HIGH */\r
+ [0].sectAddr[12] = 0x00080000,\r
+ [0].addrSpace[12] = ADDR_SPACE(0, ADDR_SPACE_HIGH, 5 ),\r
+ [0].sectAddr[13] = 0x000c0000,\r
+ [0].addrSpace[13] = ADDR_SPACE(1, ADDR_SPACE_HIGH, 5 ),\r
+ [0].sectAddr[14] = 0x00100000,\r
+ [0].addrSpace[14] = ADDR_SPACE(2, ADDR_SPACE_HIGH, 6 ),\r
+ [0].sectAddr[15] = 0x00140000,\r
+ [0].addrSpace[15] = ADDR_SPACE(3, ADDR_SPACE_HIGH, 6 ),\r
+ [0].sectAddr[16] = 0x00180000,\r
+ [0].addrSpace[16] = ADDR_SPACE(4, ADDR_SPACE_HIGH, 7 ),\r
+ [0].sectAddr[17] = 0x001c0000,\r
+ [0].addrSpace[17] = ADDR_SPACE(5, ADDR_SPACE_HIGH, 7 ),\r
+ [0].sectAddr[18] = 0x00200000, /* End, NOT a sector */\r
+};\r
+#else\r
+#error CPU NOT supported\r
+#endif\r
+\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+#if ( FLS_AC_LOAD_ON_JOB_START == STD_ON)\r
+ .FlsAcWrite = __FLS_ERASE_RAM__,\r
+ .FlsAcErase = __FLS_WRITE_RAM__,\r
+#else\r
+ .FlsAcWrite = NULL,\r
+ .FlsAcErase = NULL,\r
+#endif\r
+ .FlsJobEndNotification = NULL,\r
+ .FlsJobErrorNotification = NULL,\r
+ .FlsInfo = flashInfo,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Fls Flash Driver\r
+ * @{ */\r
+\r
+/** @file Fls_Cfg.h\r
+ * Definitions of configuration parameters for Flash Driver.\r
+ */\r
+\r
+\r
+\r
+#ifndef FLS_CFG_H_\r
+#define FLS_CFG_H_\r
+\r
+#define USE_FLS_INFO STD_ON\r
+\r
+\r
+/* STD container : Fls\r
+ * FlsConfigSet 1..*\r
+ * FlsGeneral 1\r
+ * FlsPublishedInformation 1\r
+ */\r
+\r
+#include "MemIf_Types.h"\r
+\r
+/* FlsGeneral, 3.0 OK */\r
+#define FLS_VARIANT_PB STD_OFF\r
+#define FLS_AC_LOAD_ON_JOB_START STD_OFF /* NO SUPPORT */\r
+#define FLS_BASE_ADDRESS 0x00000000\r
+#define FLS_CANCEL_API STD_OFF /* NO SUPPORT */\r
+#define FLS_COMPARE_API STD_ON\r
+#define FLS_DEV_ERROR_DETECT STD_ON\r
+#define FLS_DRIVER_INDEX 0 /* NO SUPPORT */\r
+#define FLS_GET_JOB_RESULT_API STD_ON\r
+#define FLS_GET_STATUS_API STD_ON\r
+#define FLS_SET_MODE_API STD_OFF /* NO SUPPORT */\r
+//#define FLS_TOTAL_SIZE\r
+#define FLS_USE_INTERRUPTS STD_OFF /* NO SUPPORT */\r
+#define FLS_VERSION_INFO_API STD_ON\r
+\r
+/* FlsPublishedInformation, 3.0 OK */\r
+#define FLS_AC_LOCATION_ERASE 0 /* NO SUPPORT */\r
+#define FLS_AC_LOCATION_WRITE 0 /* NO SUPPORT */\r
+#define FLS_AC_SIZE_ERASE 0 /* NO SUPPORT */\r
+#define FLS_AC_SIZE_WRITE 0 /* NO SUPPORT */\r
+#define FLS_ERASE_TIME 0 /* NO SUPPORT */\r
+#define FLS_ERASED_VALUE 0xff /* NO SUPPORT */\r
+#define FLS_EXPECTED_HW_ID 0 /* NO SUPPORT */\r
+#define FLS_SPECIFIED_ERASE_CYCLES 0 /* NO SUPPORT */\r
+#define FLS_WRITE_TIME 0 /* NO SUPPORT */\r
+\r
+/* MCU Specific */\r
+#if defined(CFG_MPC5668)\r
+\r
+#define FLASH_BANK_CNT 1\r
+#define FLASH_PAGE_SIZE 8\r
+#define FLASH_MAX_SECTORS 18\r
+#define FLS_TOTAL_SIZE ((64*2+128*2+256*6)*1024)\r
+\r
+#else\r
+#error CPU not supported\r
+#endif\r
+\r
+#if (USE_FLS_INFO==STD_ON)\r
+\r
+typedef struct Flash {\r
+ uint32_t size;\r
+ uint32_t sectCnt;\r
+ uint32_t bankSize;\r
+ uint32_t regBase;\r
+ uint32_t sectAddr[FLASH_MAX_SECTORS+1];\r
+ uint16_t addrSpace[FLASH_MAX_SECTORS+1];\r
+} FlashType;\r
+\r
+\r
+#else\r
+typedef struct {\r
+ Fls_LengthType FlsNumberOfSectors;\r
+ Fls_LengthType FlsPageSize;\r
+ Fls_LengthType FlsSectorSize;\r
+ Fls_AddressType FlsSectorStartaddress;\r
+} Fls_SectorType;\r
+#endif\r
+\r
+\r
+struct Flash;\r
+\r
+typedef struct {\r
+ void (*FlsAcErase)(); /* NO SUPPORT */\r
+ void (*FlsAcWrite)(); /* NO SUPPORT */\r
+ // FlsCallCycle N/A in core.\r
+ void (*FlsJobEndNotification)();\r
+ void (*FlsJobErrorNotification)();\r
+ uint32_t FlsMaxReadFastMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxReadNormalMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxWriteFastMode; /* NO SUPPORT */\r
+ uint32_t FlsMaxWriteNormalMode; /* NO SUPPORT */\r
+ uint32_t FlsProtection; /* NO SUPPORT */\r
+#if (USE_FLS_INFO==STD_ON)\r
+ const struct Flash *FlsInfo;\r
+#else\r
+ const Fls_SectorType *FlsSectorList;\r
+#endif\r
+// const uint32 FlsSectorListSize; /* NO SUPPORT */\r
+} Fls_ConfigSetType;\r
+\r
+typedef Fls_ConfigSetType Fls_ConfigType;\r
+\r
+extern const Fls_ConfigSetType FlsConfigSet[];\r
+\r
+#endif /*FLS_CFG_H_*/\r
+/** @} */\r
projects / arc.git / commitdiff