Moved clock setup into Mcu.c

diff --git a/arch/arm/arm_cm3/drivers/Mcu.c b/arch/arm/arm_cm3/drivers/Mcu.c
index 12980ebbc7079d3ad70da0cd85e320c80f6ca208..4003aedb5920d10c0a541c6c6d1a15f3d0c36dff 100644 (file)
--- a/arch/arm/arm_cm3/drivers/Mcu.c
+++ b/arch/arm/arm_cm3/drivers/Mcu.c
@@ -24,7 +24,6 @@
 #include "cpu.h"\r
 #include <string.h>\r
 #include "Ramlog.h"\r
-#include "system_stm32f10x.h"
 \r
 //#define USE_TRACE 1\r
 //#define USE_LDEBUG_PRINTF 1\r
@@ -178,7 +177,151 @@ static uint32 Mcu_CheckCpu( void ) {
 \r
   return 0;\r
 }\r
-\r
+
+/**
+  * Set bus clocks.
+  * SysClk  = 72MHz
+  * AHBClk  = 72MHz
+  * APB1Clk = 72MHz/2
+  * APB2Clk = 72MHz
+  */
+static void SetClocks(void)
+{
+  volatile uint32 StartUpCounter = 0, HSEStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+#ifdef STM32F10X_CL
+    /* Configure PLLs ------------------------------------------------------*/
+    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
+    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
+
+    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
+                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
+    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
+                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
+
+    /* Enable PLL2 */
+    RCC->CR |= RCC_CR_PLL2ON;
+    /* Wait till PLL2 is ready */
+    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
+    {
+    }
+
+    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
+                            RCC_CFGR_PLLMULL9);
+#else
+    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
+#endif /* STM32F10X_CL */
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* HSE fails to start-up, the application will have wrong clock */
+         NVIC_SystemReset();
+  }
+}
+
+/**
+  * Initialize Flash, PLL and clocks.
+  */
+static void InitMcu(void)
+{
+  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
+#ifndef STM32F10X_CL
+  RCC->CFGR &= (uint32_t)0xF8FF0000;
+#else
+  RCC->CFGR &= (uint32_t)0xF0FF0000;
+#endif /* STM32F10X_CL */
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
+  RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+#ifndef STM32F10X_CL
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x009F0000;
+#else
+  /* Reset PLL2ON and PLL3ON bits */
+  RCC->CR &= (uint32_t)0xEBFFFFFF;
+
+  /* Disable all interrupts and clear pending bits  */
+  RCC->CIR = 0x00FF0000;
+
+  /* Reset CFGR2 register */
+  RCC->CFGR2 = 0x00000000;
+#endif /* STM32F10X_CL */
+
+  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
+  /* Configure the Flash Latency cycles and enable prefetch buffer */
+  SetClocks();
+}\r
 \r
 //-------------------------------------------------------------------\r
 \r
@@ -192,8 +335,7 @@ void Mcu_Init(const Mcu_ConfigType *configPtr)
 \r
   memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
 
-
-  SystemInit();\r
+  InitMcu();
 
   Irq_Enable();\r
 \r

diff --git a/arch/arm/arm_cm3/kernel/system_stm32f10x.c b/arch/arm/arm_cm3/kernel/system_stm32f10x.c
deleted file mode 100644 (file)
index 053a66a..0000000
--- a/arch/arm/arm_cm3/kernel/system_stm32f10x.c
+++ /dev/null
@@ -1,933 +0,0 @@
-/**\r
-  ******************************************************************************\r
-  * @file    system_stm32f10x.c\r
-  * @author  MCD Application Team\r
-  * @version V3.1.0\r
-  * @date    06/19/2009\r
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
-  ******************************************************************************  \r
-  *\r
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
-  *\r
-  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>\r
-  ******************************************************************************\r
-  */\r
-\r
-/** @addtogroup CMSIS\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup stm32f10x_system\r
-  * @{\r
-  */  \r
-  \r
-/** @addtogroup STM32F10x_System_Private_Includes\r
-  * @{\r
-  */\r
-\r
-#include "stm32f10x.h"\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Defines\r
-  * @{\r
-  */\r
-\r
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
-   frequency (after reset the HSI is used as SYSCLK source)\r
-   \r
-   IMPORTANT NOTE:\r
-   ============== \r
-   1. After each device reset the HSI is used as System clock source.\r
-\r
-   2. Please make sure that the selected System clock doesn't exceed your device's\r
-      maximum frequency.\r
-      \r
-   3. If none of the define below is enabled, the HSI is used as System clock\r
-    source.\r
-\r
-   4. The System clock configuration functions provided within this file assume that:\r
-        - For Low, Medium and High density devices an external 8MHz crystal is\r
-          used to drive the System clock.\r
-        - For Connectivity line devices an external 25MHz crystal is used to drive\r
-          the System clock.\r
-     If you are using different crystal you have to adapt those functions accordingly.\r
-    */\r
-    \r
-/* #define SYSCLK_FREQ_HSE    HSE_Value */\r
-/* #define SYSCLK_FREQ_24MHz  24000000 */\r
-/* #define SYSCLK_FREQ_36MHz  36000000 */\r
-/* #define SYSCLK_FREQ_48MHz  48000000 */\r
-/* #define SYSCLK_FREQ_56MHz  56000000 */\r
-#define SYSCLK_FREQ_72MHz  72000000\r
-\r
-/*!< Uncomment the following line if you need to use external SRAM mounted\r
-     on STM3210E-EVAL board (STM32 High density devices) as data memory  */ \r
-#ifdef STM32F10X_HD\r
-/* #define DATA_IN_ExtSRAM */\r
-#endif /* STM32F10X_HD */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Variables\r
-  * @{\r
-  */\r
-\r
-/*******************************************************************************\r
-*  Clock Definitions\r
-*******************************************************************************/\r
-#ifdef SYSCLK_FREQ_HSE\r
-  const uint32_t SystemFrequency         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */\r
-  const uint32_t SystemFrequency_SysClk  = SYSCLK_FREQ_HSE;        /*!< System clock                        */\r
-  const uint32_t SystemFrequency_AHBClk  = SYSCLK_FREQ_HSE;        /*!< AHB System bus speed                */\r
-  const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE;        /*!< APB Peripheral bus 1 (low)  speed   */\r
-  const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE;        /*!< APB Peripheral bus 2 (high) speed   */\r
-#elif defined SYSCLK_FREQ_24MHz\r
-  const uint32_t SystemFrequency         = SYSCLK_FREQ_24MHz;      /*!< System Clock Frequency (Core Clock) */\r
-  const uint32_t SystemFrequency_SysClk  = SYSCLK_FREQ_24MHz;      /*!< System clock                        */\r
-  const uint32_t SystemFrequency_AHBClk  = SYSCLK_FREQ_24MHz;      /*!< AHB System bus speed                */\r
-  const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz;      /*!< APB Peripheral bus 1 (low)  speed   */\r
-  const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz;      /*!< APB Peripheral bus 2 (high) speed   */\r
-#elif defined SYSCLK_FREQ_36MHz\r
-  const uint32_t SystemFrequency         = SYSCLK_FREQ_36MHz;      /*!< System Clock Frequency (Core Clock) */\r
-  const uint32_t SystemFrequency_SysClk  = SYSCLK_FREQ_36MHz;      /*!< System clock                        */\r
-  const uint32_t SystemFrequency_AHBClk  = SYSCLK_FREQ_36MHz;      /*!< AHB System bus speed                */\r
-  const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz;      /*!< APB Peripheral bus 1 (low)  speed   */\r
-  const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz;      /*!< APB Peripheral bus 2 (high) speed   */\r
-#elif defined SYSCLK_FREQ_48MHz\r
-  const uint32_t SystemFrequency         = SYSCLK_FREQ_48MHz;      /*!< System Clock Frequency (Core Clock) */\r
-  const uint32_t SystemFrequency_SysClk  = SYSCLK_FREQ_48MHz;      /*!< System clock                        */\r
-  const uint32_t SystemFrequency_AHBClk  = SYSCLK_FREQ_48MHz;      /*!< AHB System bus speed                */\r
-  const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2);  /*!< APB Peripheral bus 1 (low)  speed   */\r
-  const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz;      /*!< APB Peripheral bus 2 (high) speed   */\r
-#elif defined SYSCLK_FREQ_56MHz\r
-  const uint32_t SystemFrequency         = SYSCLK_FREQ_56MHz;      /*!< System Clock Frequency (Core Clock) */\r
-  const uint32_t SystemFrequency_SysClk  = SYSCLK_FREQ_56MHz;      /*!< System clock                        */\r
-  const uint32_t SystemFrequency_AHBClk  = SYSCLK_FREQ_56MHz;      /*!< AHB System bus speed                */\r
-  const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2);  /*!< APB Peripheral bus 1 (low)  speed   */\r
-  const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz;      /*!< APB Peripheral bus 2 (high) speed   */  \r
-#elif defined SYSCLK_FREQ_72MHz\r
-  const uint32_t SystemFrequency         = SYSCLK_FREQ_72MHz;      /*!< System Clock Frequency (Core Clock) */\r
-  const uint32_t SystemFrequency_SysClk  = SYSCLK_FREQ_72MHz;      /*!< System clock                        */\r
-  const uint32_t SystemFrequency_AHBClk  = SYSCLK_FREQ_72MHz;      /*!< AHB System bus speed                */\r
-  const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2);  /*!< APB Peripheral bus 1 (low)  speed   */\r
-  const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz;      /*!< APB Peripheral bus 2 (high) speed   */\r
-#else /*!< HSI Selected as System Clock source */\r
-  const uint32_t SystemFrequency         = HSI_Value;              /*!< System Clock Frequency (Core Clock) */\r
-  const uint32_t SystemFrequency_SysClk  = HSI_Value;              /*!< System clock                        */\r
-  const uint32_t SystemFrequency_AHBClk  = HSI_Value;              /*!< AHB System bus speed                */\r
-  const uint32_t SystemFrequency_APB1Clk = HSI_Value;              /*!< APB Peripheral bus 1 (low)  speed   */\r
-  const uint32_t SystemFrequency_APB2Clk = HSI_Value;              /*!< APB Peripheral bus 2 (high) speed   */\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes\r
-  * @{\r
-  */\r
-\r
-static void SetSysClock(void);\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
-  static void SetSysClockToHSE(void);\r
-#elif defined SYSCLK_FREQ_24MHz\r
-  static void SetSysClockTo24(void);\r
-#elif defined SYSCLK_FREQ_36MHz\r
-  static void SetSysClockTo36(void);\r
-#elif defined SYSCLK_FREQ_48MHz\r
-  static void SetSysClockTo48(void);\r
-#elif defined SYSCLK_FREQ_56MHz\r
-  static void SetSysClockTo56(void);  \r
-#elif defined SYSCLK_FREQ_72MHz\r
-  static void SetSysClockTo72(void);\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Functions\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @brief  Setup the microcontroller system\r
-  *         Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.\r
-  * @note   This function should be used only after reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-void SystemInit (void)\r
-{\r
-  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
-  /* Set HSION bit */\r
-  RCC->CR |= (uint32_t)0x00000001;\r
-\r
-  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
-#ifndef STM32F10X_CL\r
-  RCC->CFGR &= (uint32_t)0xF8FF0000;\r
-#else\r
-  RCC->CFGR &= (uint32_t)0xF0FF0000;\r
-#endif /* STM32F10X_CL */   \r
-  \r
-  /* Reset HSEON, CSSON and PLLON bits */\r
-  RCC->CR &= (uint32_t)0xFEF6FFFF;\r
-\r
-  /* Reset HSEBYP bit */\r
-  RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
-  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
-  RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
-\r
-#ifndef STM32F10X_CL\r
-  /* Disable all interrupts and clear pending bits  */\r
-  RCC->CIR = 0x009F0000;\r
-#else\r
-  /* Reset PLL2ON and PLL3ON bits */\r
-  RCC->CR &= (uint32_t)0xEBFFFFFF;\r
-\r
-  /* Disable all interrupts and clear pending bits  */\r
-  RCC->CIR = 0x00FF0000;\r
-\r
-  /* Reset CFGR2 register */\r
-  RCC->CFGR2 = 0x00000000;\r
-#endif /* STM32F10X_CL */\r
-    \r
-  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
-  /* Configure the Flash Latency cycles and enable prefetch buffer */\r
-  SetSysClock();\r
-\r
-}\r
-\r
-/**\r
-  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-static void SetSysClock(void)\r
-{
-#if !defined(CFG_SIMULATOR)\r
-#ifdef SYSCLK_FREQ_HSE\r
-  SetSysClockToHSE();\r
-#elif defined SYSCLK_FREQ_24MHz\r
-  SetSysClockTo24();\r
-#elif defined SYSCLK_FREQ_36MHz\r
-  SetSysClockTo36();\r
-#elif defined SYSCLK_FREQ_48MHz\r
-  SetSysClockTo48();\r
-#elif defined SYSCLK_FREQ_56MHz\r
-  SetSysClockTo56();  \r
-#elif defined SYSCLK_FREQ_72MHz\r
-  SetSysClockTo72();\r
-#endif
-#endif\r
- \r
- /* If none of the define above is enabled, the HSI is used as System clock\r
-    source (default after reset) */ \r
-}\r
-\r
-/**\r
-  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s \r
-  *          before jump to __main\r
-  * @param  None\r
-  * @retval None\r
-  */ \r
-#ifdef DATA_IN_ExtSRAM\r
-/**\r
-  * @brief  Setup the external memory controller. \r
-  *         Called in startup_stm32f10x_xx.s/.c before jump to main.\r
-  *          This function configures the external SRAM mounted on STM3210E-EVAL\r
-  *         board (STM32 High density devices). This SRAM will be used as program\r
-  *         data memory (including heap and stack).\r
-  * @param  None\r
-  * @retval None\r
-  */ \r
-void SystemInit_ExtMemCtl(void) \r
-{\r
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
-  required, then adjust the Register Addresses */\r
-\r
-  /* Enable FSMC clock */\r
-  RCC->AHBENR = 0x00000114;\r
-  \r
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  \r
-  RCC->APB2ENR = 0x000001E0;\r
-  \r
-/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/\r
-/*----------------  SRAM Address lines configuration -------------------------*/\r
-/*----------------  NOE and NWE configuration --------------------------------*/  \r
-/*----------------  NE3 configuration ----------------------------------------*/\r
-/*----------------  NBL0, NBL1 configuration ---------------------------------*/\r
-  \r
-  GPIOD->CRL = 0x44BB44BB;  \r
-  GPIOD->CRH = 0xBBBBBBBB;\r
-\r
-  GPIOE->CRL = 0xB44444BB;  \r
-  GPIOE->CRH = 0xBBBBBBBB;\r
-\r
-  GPIOF->CRL = 0x44BBBBBB;  \r
-  GPIOF->CRH = 0xBBBB4444;\r
-\r
-  GPIOG->CRL = 0x44BBBBBB;  \r
-  GPIOG->CRH = 0x44444B44;\r
-   \r
-/*----------------  FSMC Configuration ---------------------------------------*/  \r
-/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
-  \r
-  FSMC_Bank1->BTCR[4] = 0x00001011;\r
-  FSMC_Bank1->BTCR[5] = 0x00000200;\r
-}\r
-#endif /* DATA_IN_ExtSRAM */\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
-/**\r
-  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2\r
-  *          and PCLK1 prescalers.\r
-  * @note   This function should be used only after reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-static void SetSysClockToHSE(void)\r
-{\r
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
-  \r
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
-  /* Enable HSE */    \r
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
-  /* Wait till HSE is ready and if Time out is reached exit */\r
-  do\r
-  {\r
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
-    StartUpCounter++;  \r
-  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
-  {\r
-    HSEStatus = (uint32_t)0x01;\r
-  }\r
-  else\r
-  {\r
-    HSEStatus = (uint32_t)0x00;\r
-  }  \r
-\r
-  if (HSEStatus == (uint32_t)0x01)\r
-  {\r
-    /* Enable Prefetch Buffer */\r
-    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
-    /* Flash 0 wait state */\r
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-\r
-#ifndef STM32F10X_CL\r
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
-#else\r
-    if (HSE_Value <= 24000000)\r
-       {\r
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
-       }\r
-       else\r
-       {\r
-      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;\r
-       }\r
-#endif /* STM32F10X_CL */\r
- \r
-    /* HCLK = SYSCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
-      \r
-    /* PCLK2 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
-    \r
-    /* PCLK1 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
-    \r
-    /* Select HSE as system clock source */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    \r
-\r
-    /* Wait till HSE is used as system clock source */\r
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
-    {\r
-    }\r
-  }\r
-  else\r
-  { /* If HSE fails to start-up, the application will have wrong clock \r
-         configuration. User can add here some code to deal with this error */    \r
-\r
-    /* Go to infinite loop */\r
-    while (1)\r
-    {\r
-    }\r
-  }  \r
-}\r
-#elif defined SYSCLK_FREQ_24MHz\r
-/**\r
-  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 \r
-  *          and PCLK1 prescalers.\r
-  * @note   This function should be used only after reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-static void SetSysClockTo24(void)\r
-{\r
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
-  \r
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
-  /* Enable HSE */    \r
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
-  /* Wait till HSE is ready and if Time out is reached exit */\r
-  do\r
-  {\r
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
-    StartUpCounter++;  \r
-  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
-  {\r
-    HSEStatus = (uint32_t)0x01;\r
-  }\r
-  else\r
-  {\r
-    HSEStatus = (uint32_t)0x00;\r
-  }  \r
-\r
-  if (HSEStatus == (uint32_t)0x01)\r
-  {\r
-    /* Enable Prefetch Buffer */\r
-    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
-    /* Flash 0 wait state */\r
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    \r
- \r
-    /* HCLK = SYSCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
-      \r
-    /* PCLK2 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
-    \r
-    /* PCLK1 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
-    \r
-#ifdef STM32F10X_CL\r
-    /* Configure PLLs ------------------------------------------------------*/\r
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ \r
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
-                            RCC_CFGR_PLLMULL6); \r
-\r
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       \r
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
-  \r
-    /* Enable PLL2 */\r
-    RCC->CR |= RCC_CR_PLL2ON;\r
-    /* Wait till PLL2 is ready */\r
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
-    {\r
-    }   \r
-#else    \r
-    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
-    /* Enable PLL */\r
-    RCC->CR |= RCC_CR_PLLON;\r
-\r
-    /* Wait till PLL is ready */\r
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
-    {\r
-    }\r
-\r
-    /* Select PLL as system clock source */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
-\r
-    /* Wait till PLL is used as system clock source */\r
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
-    {\r
-    }\r
-  }\r
-  else\r
-  { /* If HSE fails to start-up, the application will have wrong clock \r
-         configuration. User can add here some code to deal with this error */    \r
-\r
-    /* Go to infinite loop */\r
-    while (1)\r
-    {\r
-    }\r
-  } \r
-}\r
-#elif defined SYSCLK_FREQ_36MHz\r
-/**\r
-  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 \r
-  *          and PCLK1 prescalers. \r
-  * @note   This function should be used only after reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-static void SetSysClockTo36(void)\r
-{\r
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
-  \r
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
-  /* Enable HSE */    \r
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
-  /* Wait till HSE is ready and if Time out is reached exit */\r
-  do\r
-  {\r
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
-    StartUpCounter++;  \r
-  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
-  {\r
-    HSEStatus = (uint32_t)0x01;\r
-  }\r
-  else\r
-  {\r
-    HSEStatus = (uint32_t)0x00;\r
-  }  \r
-\r
-  if (HSEStatus == (uint32_t)0x01)\r
-  {\r
-    /* Enable Prefetch Buffer */\r
-    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
-    /* Flash 1 wait state */\r
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    \r
- \r
-    /* HCLK = SYSCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
-      \r
-    /* PCLK2 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
-    \r
-    /* PCLK1 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
-    \r
-#ifdef STM32F10X_CL\r
-    /* Configure PLLs ------------------------------------------------------*/\r
-    \r
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ \r
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
-                            RCC_CFGR_PLLMULL9); \r
-\r
-       /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */\r
-        \r
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
-  \r
-    /* Enable PLL2 */\r
-    RCC->CR |= RCC_CR_PLL2ON;\r
-    /* Wait till PLL2 is ready */\r
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
-    {\r
-    }\r
-    \r
-#else    \r
-    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
-    /* Enable PLL */\r
-    RCC->CR |= RCC_CR_PLLON;\r
-\r
-    /* Wait till PLL is ready */\r
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
-    {\r
-    }\r
-\r
-    /* Select PLL as system clock source */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
-\r
-    /* Wait till PLL is used as system clock source */\r
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
-    {\r
-    }\r
-  }\r
-  else\r
-  { /* If HSE fails to start-up, the application will have wrong clock \r
-         configuration. User can add here some code to deal with this error */    \r
-\r
-    /* Go to infinite loop */\r
-    while (1)\r
-    {\r
-    }\r
-  } \r
-}\r
-#elif defined SYSCLK_FREQ_48MHz\r
-/**\r
-  * @brief  Sets System clock frequency to 48MHz and configure HCLK, PCLK2 \r
-  *          and PCLK1 prescalers. \r
-  * @note   This function should be used only after reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-static void SetSysClockTo48(void)\r
-{\r
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
-  \r
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
-  /* Enable HSE */    \r
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
-  /* Wait till HSE is ready and if Time out is reached exit */\r
-  do\r
-  {\r
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
-    StartUpCounter++;  \r
-  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
-  {\r
-    HSEStatus = (uint32_t)0x01;\r
-  }\r
-  else\r
-  {\r
-    HSEStatus = (uint32_t)0x00;\r
-  }  \r
-\r
-  if (HSEStatus == (uint32_t)0x01)\r
-  {\r
-    /* Enable Prefetch Buffer */\r
-    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
-    /* Flash 1 wait state */\r
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    \r
- \r
-    /* HCLK = SYSCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
-      \r
-    /* PCLK2 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
-    \r
-    /* PCLK1 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-    \r
-#ifdef STM32F10X_CL\r
-    /* Configure PLLs ------------------------------------------------------*/\r
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
-        \r
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
-  \r
-    /* Enable PLL2 */\r
-    RCC->CR |= RCC_CR_PLL2ON;\r
-    /* Wait till PLL2 is ready */\r
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
-    {\r
-    }\r
-    \r
-   \r
-    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ \r
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
-                            RCC_CFGR_PLLMULL6); \r
-#else    \r
-    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
-    /* Enable PLL */\r
-    RCC->CR |= RCC_CR_PLLON;\r
-\r
-    /* Wait till PLL is ready */\r
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
-    {\r
-    }\r
-\r
-    /* Select PLL as system clock source */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
-\r
-    /* Wait till PLL is used as system clock source */\r
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
-    {\r
-    }\r
-  }\r
-  else\r
-  { /* If HSE fails to start-up, the application will have wrong clock \r
-         configuration. User can add here some code to deal with this error */    \r
-\r
-    /* Go to infinite loop */\r
-    while (1)\r
-    {\r
-    }\r
-  } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_56MHz\r
-/**\r
-  * @brief  Sets System clock frequency to 56MHz and configure HCLK, PCLK2 \r
-  *          and PCLK1 prescalers. \r
-  * @note   This function should be used only after reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-static void SetSysClockTo56(void)\r
-{\r
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
-  \r
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   \r
-  /* Enable HSE */    \r
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
-  /* Wait till HSE is ready and if Time out is reached exit */\r
-  do\r
-  {\r
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
-    StartUpCounter++;  \r
-  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
-  {\r
-    HSEStatus = (uint32_t)0x01;\r
-  }\r
-  else\r
-  {\r
-    HSEStatus = (uint32_t)0x00;\r
-  }  \r
-\r
-  if (HSEStatus == (uint32_t)0x01)\r
-  {\r
-    /* Enable Prefetch Buffer */\r
-    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
-    /* Flash 1 wait state */\r
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    \r
- \r
-    /* HCLK = SYSCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
-      \r
-    /* PCLK2 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
-    \r
-    /* PCLK1 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
-    /* Configure PLLs ------------------------------------------------------*/\r
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
-        \r
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
-  \r
-    /* Enable PLL2 */\r
-    RCC->CR |= RCC_CR_PLL2ON;\r
-    /* Wait till PLL2 is ready */\r
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
-    {\r
-    }\r
-    \r
-   \r
-    /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ \r
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
-                            RCC_CFGR_PLLMULL7); \r
-#else     \r
-    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);\r
-\r
-#endif /* STM32F10X_CL */\r
-\r
-    /* Enable PLL */\r
-    RCC->CR |= RCC_CR_PLLON;\r
-\r
-    /* Wait till PLL is ready */\r
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
-    {\r
-    }\r
-\r
-    /* Select PLL as system clock source */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
-\r
-    /* Wait till PLL is used as system clock source */\r
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
-    {\r
-    }\r
-  }\r
-  else\r
-  { /* If HSE fails to start-up, the application will have wrong clock \r
-         configuration. User can add here some code to deal with this error */    \r
-\r
-    /* Go to infinite loop */\r
-    while (1)\r
-    {\r
-    }\r
-  } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_72MHz\r
-/**\r
-  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2 \r
-  *          and PCLK1 prescalers. \r
-  * @note   This function should be used only after reset.\r
-  * @param  None\r
-  * @retval None\r
-  */\r
-static void SetSysClockTo72(void)\r
-{\r
-  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
-  \r
-  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    \r
-  /* Enable HSE */    \r
-  RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
-  /* Wait till HSE is ready and if Time out is reached exit */\r
-  do\r
-  {\r
-    HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
-    StartUpCounter++;  \r
-  } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
-  if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
-  {\r
-    HSEStatus = (uint32_t)0x01;\r
-  }\r
-  else\r
-  {\r
-    HSEStatus = (uint32_t)0x00;\r
-  }  \r
-\r
-  if (HSEStatus == (uint32_t)0x01)\r
-  {\r
-    /* Enable Prefetch Buffer */\r
-    FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
-    /* Flash 2 wait state */\r
-    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;    \r
-\r
- \r
-    /* HCLK = SYSCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
-      \r
-    /* PCLK2 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
-    \r
-    /* PCLK1 = HCLK */\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
-    /* Configure PLLs ------------------------------------------------------*/\r
-    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
-    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
-        \r
-    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
-                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
-    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
-                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
-  \r
-    /* Enable PLL2 */\r
-    RCC->CR |= RCC_CR_PLL2ON;\r
-    /* Wait till PLL2 is ready */\r
-    while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
-    {\r
-    }\r
-    \r
-   \r
-    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ \r
-    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
-                            RCC_CFGR_PLLMULL9); \r
-#else    \r
-    /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
-                                        RCC_CFGR_PLLMULL));\r
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
-    /* Enable PLL */\r
-    RCC->CR |= RCC_CR_PLLON;
-
-
-    /* Wait till PLL is ready */\r
-    while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
-    {\r
-    }\r
-    \r
-    /* Select PLL as system clock source */\r
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
-    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    \r
-
-    /* Wait till PLL is used as system clock source */\r
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
-    {\r
-    }\r
-  }\r
-  else\r
-  { /* If HSE fails to start-up, the application will have wrong clock \r
-         configuration. User can add here some code to deal with this error */    \r
-\r
-    /* Go to infinite loop */\r
-    while (1)\r
-    {\r
-    }\r
-  }\r
-}\r
-#endif\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-  \r
-/**\r
-  * @}\r
-  */    \r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r

diff --git a/arch/arm/arm_cm3/kernel/system_stm32f10x.h b/arch/arm/arm_cm3/kernel/system_stm32f10x.h
deleted file mode 100644 (file)
index 113c9cc..0000000
--- a/arch/arm/arm_cm3/kernel/system_stm32f10x.h
+++ /dev/null
@@ -1,101 +0,0 @@
-
-/**\r
-  ******************************************************************************\r
-  * @file    system_stm32f10x.h\r
-  * @author  MCD Application Team\r
-  * @version V3.1.0\r
-  * @date    06/19/2009\r
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
-  ******************************************************************************  \r
-  *\r
-  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
-  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
-  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
-  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
-  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
-  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
-  *\r
-  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>\r
-  ******************************************************************************\r
-  */\r
-\r
-/** @addtogroup CMSIS\r
-  * @{\r
-  */\r
-\r
-/** @addtogroup stm32f10x_system\r
-  * @{\r
-  */  \r
-  \r
-/**\r
-  * @brief Define to prevent recursive inclusion\r
-  */\r
-#ifndef __SYSTEM_STM32F10X_H\r
-#define __SYSTEM_STM32F10X_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/** @addtogroup STM32F10x_System_Includes\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-\r
-/** @addtogroup STM32F10x_System_Exported_types\r
-  * @{\r
-  */\r
-\r
-extern const uint32_t SystemFrequency;          /*!< System Clock Frequency (Core Clock) */\r
-extern const uint32_t SystemFrequency_SysClk;   /*!< System clock                        */\r
-extern const uint32_t SystemFrequency_AHBClk;   /*!< AHB System bus speed                */\r
-extern const uint32_t SystemFrequency_APB1Clk;  /*!< APB Peripheral Bus 1 (low)  speed   */\r
-extern const uint32_t SystemFrequency_APB2Clk;  /*!< APB Peripheral Bus 2 (high) speed   */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Constants\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Macros\r
-  * @{\r
-  */\r
-\r
-/**\r
-  * @}\r
-  */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Functions\r
-  * @{\r
-  */\r
-  \r
-extern void SystemInit(void);\r
-/**\r
-  * @}\r
-  */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__SYSTEM_STM32F10X_H */\r
-\r
-/**\r
-  * @}\r
-  */\r
-  \r
-/**\r
-  * @}\r
-  */  \r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r

diff --git a/boards/board_common.mk b/boards/board_common.mk
index 13f5c058bdeeca3b6758143955983c2dc178e80a..62f6d87747e580efce9ed0df3d994aeda80f49c6 100644 (file)
--- a/boards/board_common.mk
+++ b/boards/board_common.mk
@@ -1,7 +1,6 @@
 obj-$(CFG_PPC) += crt0.o\r
 obj-$(CFG_HCS12D) += crt0.o\r
 vpath-$(CFG_ARM_CM3) += $(ARCH_PATH-y)kernel\r
-obj-$(CFG_ARM_CM3) += system_stm32f10x.o\r
 obj-$(CFG_ARM_CM3) += core_cm3.o\r
 obj-$(CFG_ARM_CM3) += startup_stm32f10x.o\r
 \r

diff --git a/include/arm/stm32f10x.h b/include/arm/stm32f10x.h
index e2221e81176255d61fe41aacd800ed2f6a435bf4..67015a7a976b159086fcd195d57ea11f4d29b41d 100644 (file)
--- a/include/arm/stm32f10x.h
+++ b/include/arm/stm32f10x.h
@@ -304,7 +304,7 @@ typedef enum IRQn
   */\r
 \r
 #include "core_cm3.h"\r
-#include "system_stm32f10x.h"\r
+//#include "system_stm32f10x.h"\r
 #include <stdint.h>\r
 \r
 /** @addtogroup Exported_types\r