# switch to regexp syntax.\r
syntax: regexp\r
^.*obj_.*\.[h|c|s]\r
-\r
-\r
+^\.lib.*\.arxml\r
+
+syntax: regexp
+^.project$
\ No newline at end of file
\r
if (E_OK == Adc_CheckReadGroup (group))\r
{\r
- if ((ADC_CONV_MODE_CONTINOUS == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
+ if ((ADC_CONV_MODE_CONTINUOUS == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
((ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
(ADC_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
{\r
#endif\r
}\r
\r
-\r
-#if 0\r
-void Adc_ConfigureEQADCInterrupts (void)\r
-{\r
- Adc_GroupType group;\r
-\r
-#if defined(USE_KERNEL)\r
- TaskType tid;\r
- tid = Os_Arc_CreateIsr(Adc_EQADCError,EQADC_FISR_OVER_PRIORITY,"Adc_Err");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR_OVER);\r
-\r
- tid = Os_Arc_CreateIsr(Adc_Group0ConversionComplete,EQADC_FIFO0_END_OF_QUEUE_PRIORITY,"Adc_Grp0");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR0_EOQF0);\r
-\r
- tid = Os_Arc_CreateIsr(Adc_Group1ConversionComplete,EQADC_FIFO1_END_OF_QUEUE_PRIORITY,"Adc_Grp1");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR1_EOQF1);\r
-\r
-#else\r
- Irq_InstallVector (Adc_EQADCError,\r
- EQADC_FISR_OVER,\r
- EQADC_FISR_OVER_PRIORITY, CPU_Z1);\r
-\r
- Irq_InstallVector (Adc_Group0ConversionComplete,\r
- EQADC_FISR0_EOQF0,\r
- EQADC_FIFO0_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
-\r
- Irq_InstallVector (Adc_Group1ConversionComplete,\r
- EQADC_FISR1_EOQF1,\r
- EQADC_FIFO1_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
-\r
-#endif\r
- for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
- {\r
- /* Enable end of queue, queue overflow/underflow interrupts. Clear corresponding flags. */\r
- EQADC.FISR[group].B.RFOF = 1;\r
- EQADC.IDCR[group].B.RFOIE = 1;\r
-\r
- EQADC.FISR[group].B.CFUF = 1;\r
- EQADC.IDCR[group].B.CFUIE = 1;\r
-\r
- EQADC.FISR[group].B.TORF = 1;\r
- EQADC.IDCR[group].B.TORIE = 1;\r
-\r
- EQADC.FISR[group].B.EOQF = 1;\r
- EQADC.IDCR[group].B.EOQIE = 1;\r
- }\r
-}\r
-#endif\r
-\r
#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
void Adc_StartGroupConversion (Adc_GroupType group)\r
{\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include "Can.h"\r
+\r
+#ifndef USE_CAN_STUB
+#include "stm32f10x.h"\r
+#include "stm32f10x_can.h"
+#include "Cpu.h"\r
+#include "Mcu.h"\r
+#include "CanIf_Cbk.h"\r
+#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"\r
+#endif
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "Os.h"
+#include "irq.h"\r
+#include "arc.h"
+\r
+
+/* CONFIGURATION NOTES\r
+ * ------------------------------------------------------------------\r
+ * - CanHandleType must be CAN_ARC_HANDLE_TYPE_BASIC\r
+ * i.e. CanHandleType=CAN_ARC_HANDLE_TYPE_FULL NOT supported\r
+ * i.e CanIdValue is NOT supported\r
+ * - All CanXXXProcessing must be CAN_ARC_PROCESS_TYPE_INTERRUPT\r
+ * ie CAN_ARC_PROCESS_TYPE_POLLED not supported\r
+ * - HOH's for Tx are global and Rx are for each controller\r
+ */\r
+\r
+/* IMPLEMENTATION NOTES\r
+ * -----------------------------------------------\r
+ * - A HOH us unique for a controller( not a config-set )\r
+ * - Hrh's are numbered for each controller from 0\r
+ * - loopback in HW NOT supported
+ * - Only one transmit mailbox is used because otherwise
+ * we cannot use tx_confirmation since there is no way to know
+ * which mailbox caused the tx interrupt. TP will need this feature.
+ * - Sleep,wakeup not fully implemented since other modules lack functionality\r
+ */\r
+\r
+/* ABBREVATIONS\r
+ * -----------------------------------------------\r
+ * - Can Hardware unit - One or multiple Can controllers of the same type.\r
+ * - Hrh - HOH with receive definitions\r
+ * - Hth - HOH with transmit definitions\r
+ *\r
+ */\r
+
+typedef CAN_TypeDef CAN_HW_t;\r
+//-------------------------------------------------------------------\r
+\r
+#define GET_CONTROLLER_CONFIG(_controller) \\r
+ &Can_Global.config->CanConfigSet->CanController[(_controller)]\r
+\r
+#define GET_CALLBACKS() \\r
+ (Can_Global.config->CanConfigSet->CanCallbacks)\r
+\r
+#define GET_PRIVATE_DATA(_controller) \\r
+ &CanUnit[_controller]\r
+\r
+#define GET_CONTROLLER_CNT() (CAN_CONTROLLER_CNT)\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( CAN_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return CAN_NOT_OK; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#endif\r
+
+#if defined(USE_DEM)
+#define VALIDATE_DEM_NO_RV(_exp,_err ) \
+ if( !(_exp) ) { \
+ Dem_ReportErrorStatus(_err, DEM_EVENT_STATUS_FAILED); \
+ return; \
+ }
+#else
+#define VALIDATE_DEM_NO_RV(_exp,_err )
+#endif\r
+
+//-------------------------------------------------------------------\r
+
+typedef enum\r
+{\r
+ CAN_UNINIT = 0,\r
+ CAN_READY\r
+} Can_DriverStateType;\r
+\r
+// Mapping between HRH and Controller//HOH\r
+typedef struct Can_Arc_ObjectHOHMapStruct\r
+{\r
+ CanControllerIdType CanControllerRef; // Reference to controller\r
+ const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.\r
+} Can_Arc_ObjectHOHMapType;\r
+\r
+/* Type for holding global information used by the driver */\r
+typedef struct {\r
+ Can_DriverStateType initRun;\r
+\r
+ // Our config\r
+ const Can_ConfigType *config;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[CAN_CONTROLLER_CNT];\r
+\r
+ // This is a map that maps the HTH:s with the controller and Hoh. It is built\r
+ // during Can_Init and is used to make things faster during a transmit.\r
+ Can_Arc_ObjectHOHMapType CanHTHMap[NUM_OF_HTHS];\r
+} Can_GlobalType;\r
+\r
+// Global config\r
+Can_GlobalType Can_Global =\r
+{\r
+ .initRun = CAN_UNINIT,\r
+};\r
+\r
+/* Type for holding information about each controller */\r
+typedef struct {\r
+ CanIf_ControllerModeType state;\r
+ uint32 lock_cnt;\r
+\r
+ // Statistics\r
+ Can_Arc_StatisticsType stats;\r
+\r
+ // Data stored for Txconfirmation callbacks to CanIf\r
+ PduIdType swPduHandle; //\r
+} Can_UnitType;\r
+\r
+Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =\r
+{\r
+ {\r
+ .state = CANIF_CS_UNINIT,\r
+ },
+ {\r
+ .state = CANIF_CS_UNINIT,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+static CAN_HW_t * GetController(int unit)
+{
+ return ((CAN_HW_t *)(CAN1_BASE + unit*0x400));
+}\r
+
+//-------------------------------------------------------------------\r
+/**\r
+ * Function that finds the Hoh( HardwareObjectHandle ) from a Hth\r
+ * A HTH may connect to one or several HOH's. Just find the first one.\r
+ *\r
+ * @param hth The transmit handle\r
+ * @returns Ptr to the Hoh\r
+ */\r
+static const Can_HardwareObjectType * Can_FindHoh( Can_Arc_HTHType hth , uint32* controller)\r
+{\r
+ const Can_HardwareObjectType *hohObj;\r
+ const Can_Arc_ObjectHOHMapType *map;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+\r
+ map = &Can_Global.CanHTHMap[hth];\r
+\r
+ // Verify that this is the correct map\r
+ if (map->CanHOHRef->CanObjectId != hth)\r
+ {\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+ }\r
+\r
+ canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[map->CanControllerRef]);\r
+\r
+ hohObj = map->CanHOHRef;\r
+\r
+ // Verify that this is the correct Hoh type\r
+ if ( hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ *controller = map->CanControllerRef;\r
+ return hohObj;\r
+ }\r
+\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+\r
+ return NULL;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+static void Can_RxIsr( int unit );
+static void Can_TxIsr( int unit );
+static void Can_ErrIsr( int unit );\r
+
+void Can_1_RxIsr( void ) { Can_RxIsr(CAN_CTRL_1); }
+void Can_2_RxIsr( void ) { Can_RxIsr(CAN_CTRL_2); }
+
+void Can_1_TxIsr( void ) { Can_TxIsr(CAN_CTRL_1); }
+void Can_2_TxIsr( void ) { Can_TxIsr(CAN_CTRL_2); }
+
+void Can_1_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_1); }
+void Can_2_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_2); }
+\r
+
+//-------------------------------------------------------------------\r
+
+// Uses 25.4.5.1 Transmission Abort Mechanism
+static void Can_AbortTx( CAN_HW_t *canHw, Can_UnitType *canUnit ) {
+ // Disable Transmit irq
+
+ // check if mb's empty
+
+ // Abort all pending mb's
+
+ // Wait for mb's being emptied
+}
+
+/**
+ * Hardware wake ISR for CAN
+ *
+ * @param unit CAN controller number( from 0 )
+ */
+static void Can_WakeIsr( int unit ) {
+ if (GET_CALLBACKS()->ControllerWakeup != NULL)
+ {
+ GET_CALLBACKS()->ControllerWakeup(unit);
+ }
+ // 269,270,271
+ Can_SetControllerMode(unit, CAN_T_STOP);
+
+ // TODO EcuM_CheckWakeup();
+}\r
+
+/**\r
+ * Hardware error ISR for CAN\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_ErrIsr( int unit ) {\r
+ CAN_HW_t *canHw = GetController(unit);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
+ Can_Arc_ErrorType err;\r
+ err.R = 0;
+
+ // Check wake up
+ if(SET == CAN_GetITStatus(canHw, CAN_IT_WKU)){\r
+ Can_WakeIsr(unit);\r
+ CAN_ClearITPendingBit(canHw, CAN_IT_WKU);
+ }
+
+ if(SET == CAN_GetITStatus(canHw, CAN_IT_BOF)){
+ canUnit->stats.boffCnt++;
+ if (GET_CALLBACKS()->ControllerBusOff != NULL)
+ {
+ GET_CALLBACKS()->ControllerBusOff(unit);
+ }
+ Can_SetControllerMode(unit, CAN_T_STOP); // CANIF272
+
+ Can_AbortTx( canHw, canUnit ); // CANIF273
+
+ // Clear int
+ CAN_ClearITPendingBit(canHw, CAN_IT_BOF);
+ }
+
+ if (err.R != 0)
+ {
+ if (GET_CALLBACKS()->Arc_Error != NULL)
+ {
+ GET_CALLBACKS()->Arc_Error( unit, err );
+ }
+ }
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * ISR for CAN. Normal Rx/operation\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_RxIsr(int unit) {\r
+\r
+ CAN_HW_t *canHw= GetController(unit);\r
+ const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
+ const Can_HardwareObjectType *hohObj;
+
+ CanRxMsg RxMessage;
+
+ RxMessage.StdId=0x00;
+ RxMessage.ExtId=0x00;
+ RxMessage.IDE=0;
+ RxMessage.DLC=0;
+ RxMessage.FMI=0;
+ RxMessage.Data[0]=0x00;
+ RxMessage.Data[1]=0x00;
+ CAN_Receive(canHw,CAN_FIFO0, &RxMessage);\r
+
+ // Loop over all the Hoh's\r
+ hohObj= canHwConfig->Can_Arc_Hoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
+ {\r
+ Can_IdType id=0;
+
+ // According to autosar MSB shuould be set if extended\r
+ if (RxMessage.IDE != CAN_ID_STD) {
+ id = RxMessage.ExtId;
+ id |= 0x80000000;\r
+ } else {
+ id = RxMessage.StdId;
+ }\r
+\r
+ if (GET_CALLBACKS()->RxIndication != NULL)\r
+ {\r
+ GET_CALLBACKS()->RxIndication(hohObj->CanObjectId,\r
+ id,\r
+ RxMessage.DLC,\r
+ (uint8 *)&RxMessage.Data[0] ); // Next layer will copy\r
+ }\r
+ // Increment statistics\r
+ canUnit->stats.rxSuccessCnt++;\r
+ }\r
+ } while ( !hohObj->Can_Arc_EOL);\r
+}\r
+
+/**
+ * ISR for CAN. Normal Tx operation
+ *
+ * @param unit CAN controller number( from 0 )
+ */
+static void Can_TxIsr(int unit) {
+ CAN_HW_t *canHw= GetController(unit);
+ const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
+ const Can_HardwareObjectType *hohObj;
+
+ // Loop over all the Hoh's
+ hohObj= canHwConfig->Can_Arc_Hoh;
+ --hohObj;
+ do {
+ ++hohObj;
+
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
+ {
+ if (GET_CALLBACKS()->TxConfirmation != NULL)
+ {
+ GET_CALLBACKS()->TxConfirmation(canUnit->swPduHandle);
+ }
+ canUnit->swPduHandle = 0; // Is this really necessary ??
+
+ // Clear Tx interrupt
+ CAN_ClearITPendingBit(canHw,CAN_IT_RQCP0);
+ CAN_ClearITPendingBit(canHw,CAN_IT_RQCP1);
+ CAN_ClearITPendingBit(canHw,CAN_IT_RQCP2);
+ }
+ } while ( !hohObj->Can_Arc_EOL);
+}\r
+
+//-------------------------------------------------------------------\r
+\r
+#define INSTALL_HANDLERS(_can_name,_sce,_rx,_tx) \\r
+ do { \\r
+ TaskType tid; \\r
+ tid = Os_Arc_CreateIsr(_can_name ## _ErrIsr,2/*prio*/,"Can"); \
+ Irq_AttachIsr2(tid,NULL,_sce); \
+ tid = Os_Arc_CreateIsr(_can_name ## _RxIsr,2/*prio*/,"Can"); \
+ Irq_AttachIsr2(tid,NULL,_rx); \
+ tid = Os_Arc_CreateIsr(_can_name ## _TxIsr,2/*prio*/,"Can"); \
+ Irq_AttachIsr2(tid,NULL,_tx); \
+ } while(0);\r
+\r
+// This initiates ALL can controllers\r
+void Can_Init( const Can_ConfigType *config ) {\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint32 ctlrId;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_UNINIT), 0x0, CAN_E_TRANSITION );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x0, CAN_E_PARAM_POINTER );\r
+\r
+ // Save config\r
+ Can_Global.config = config;\r
+ Can_Global.initRun = CAN_READY;\r
+\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Can_Global.channelMap[canHwConfig->CanControllerId] = configId;\r
+ Can_Global.configured |= (1<<ctlrId);\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
+
+ // Note!
+ // Could install handlers depending on HW objects to trap more errors
+ // in configuration
+ switch( canHwConfig->CanControllerId ) {
+#ifndef STM32F10X_CL
+ case CAN_CTRL_1:
+ INSTALL_HANDLERS(Can_1, CAN1_SCE_IRQn, USB_LP_CAN1_RX0_IRQn, USB_HP_CAN1_TX_IRQn); break;
+#else
+ case CAN_CTRL_1:
+ INSTALL_HANDLERS(Can_1, CAN1_SCE_IRQn, CAN1_RX0_IRQn, CAN1_TX_IRQn); break;
+ case CAN_CTRL_2:
+ INSTALL_HANDLERS(Can_2, CAN2_SCE_IRQn, CAN2_RX0_IRQn, CAN2_TX_IRQn); break;
+#endif
+ default:
+ assert(0);
+ }\r
+\r
+ Can_InitController(ctlrId, canHwConfig);\r
+\r
+ // Loop through all Hoh:s and map them into the HTHMap\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = canHwConfig->Can_Arc_Hoh;\r
+ hoh--;\r
+ do\r
+ {\r
+ hoh++;\r
+\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanControllerRef = canHwConfig->CanControllerId;\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return;\r
+}\r
+\r
+// Unitialize the module\r
+void Can_DeInit()\r
+{\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint32 ctlrId;\r
+\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_UNINIT;\r
+\r
+ Can_DisableControllerInterrupts(ctlrId);\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));\r
+ }\r
+\r
+ Can_Global.config = NULL;\r
+ Can_Global.initRun = CAN_UNINIT;\r
+\r
+ return;\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)
+{\r
+ CAN_HW_t *canHw;\r
+ uint8_t tq;\r
+ uint8_t tqSync;
+ uint8_t tq1;
+ uint8_t tq2;\r
+ uint32_t clock;\r
+ Can_UnitType *canUnit;\r
+ uint8 cId = controller;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ const Can_HardwareObjectType *hohObj;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_READY), 0x2, CAN_E_UNINIT );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x2,CAN_E_PARAM_POINTER);\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x2, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state==CANIF_CS_STOPPED), 0x2, CAN_E_TRANSITION );\r
+\r
+ canHw = GetController(cId);\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[cId]);\r
+\r
+ // Start this baby up
+ CAN_DeInit(canHw);\r
+
+ /* CAN filter init. We set up two filters - one for the master (CAN1) and
+ * one for the slave (CAN2)
+ *
+ * CAN_SlaveStartBank(n) denotes which filter is the first of the slave.
+ *
+ * The filter registers reside in CAN1 and is shared to CAN2, so we only need
+ * to set up this once.
+ */
+
+ // We let all frames in and do the filtering in software.
+ CAN_FilterInitTypeDef CAN_FilterInitStructure;
+ CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
+ CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
+ CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
+ CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
+ CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
+ CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
+ CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_FIFO0;
+ CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
+
+ // Init filter 0 (CAN1/master)
+ CAN_FilterInitStructure.CAN_FilterNumber=0;
+ CAN_FilterInit(&CAN_FilterInitStructure);
+
+ // Init filter 1 (CAN2/slave)
+ CAN_FilterInitStructure.CAN_FilterNumber=1;
+ CAN_FilterInit(&CAN_FilterInitStructure);
+
+ // Set which filter to use for CAN2.
+ CAN_SlaveStartBank(1);
+
+ // acceptance filters
+ hohObj = canHwConfig->Can_Arc_Hoh;
+ --hohObj;
+ do {
+ ++hohObj;
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
+ {
+ // TODO Hw filtering
+ }
+ }while( !hohObj->Can_Arc_EOL );\r
+
+ // Clock calucation\r
+ // -------------------------------------------------------------------\r
+ //\r
+ // * 1 TQ = Sclk period( also called SCK )\r
+ // * Ftq = Fcanclk / ( PRESDIV + 1 ) = Sclk\r
+ // ( Fcanclk can come from crystal or from the peripheral dividers )\r
+ //\r
+ // -->\r
+ // TQ = 1/Ftq = (PRESDIV+1)/Fcanclk --> PRESDIV = (TQ * Fcanclk - 1 )\r
+ // TQ is between 8 and 25\r
+ clock = McuE_GetSystemClock()/2;
+
+ tqSync = config->CanControllerPropSeg + 1;
+ tq1 = config->CanControllerSeg1 + 1;\r
+ tq2 = config->CanControllerSeg2 + 1;\r
+ tq = tqSync + tq1 + tq2;\r
+\r
+ // Check TQ limitations..
+ VALIDATE_DEM_NO_RV(( (tq1>=1) && (tq1<=16)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq2>=1) && (tq2<=8)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq>=1) && (tq<5 )), CAN_E_TIMEOUT );
+
+ CAN_InitTypeDef CAN_InitStructure;
+ CAN_StructInit(&CAN_InitStructure);
+
+ /* CAN cell init */
+ CAN_InitStructure.CAN_TTCM=DISABLE;
+ CAN_InitStructure.CAN_ABOM=ENABLE;
+ CAN_InitStructure.CAN_AWUM=ENABLE;
+ CAN_InitStructure.CAN_NART=DISABLE;
+ CAN_InitStructure.CAN_RFLM=DISABLE;
+ CAN_InitStructure.CAN_TXFP=DISABLE;
+ if(config->Can_Arc_Loopback){
+ CAN_InitStructure.CAN_Mode=CAN_Mode_LoopBack;
+ }else{
+ CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;
+ }
+
+ CAN_InitStructure.CAN_SJW=config->CanControllerPropSeg;
+ CAN_InitStructure.CAN_BS1=config->CanControllerSeg1;
+ CAN_InitStructure.CAN_BS2=config->CanControllerSeg2;
+ CAN_InitStructure.CAN_Prescaler= clock/(config->CanControllerBaudRate*1000*tq);
+
+ if(CANINITOK != CAN_Init(canHw,&CAN_InitStructure))
+ {
+ return;
+ }\r
+
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_EnableControllerInterrupts(cId);\r
+\r
+ return;\r
+}\r
+\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 controller, Can_StateTransitionType transition ) {\r
+ CAN_HW_t *canHw;\r
+ Can_ReturnType rv = CAN_OK;\r
+ VALIDATE( (controller < GET_CONTROLLER_CNT()), 0x3, CAN_E_PARAM_CONTROLLER );\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE( (canUnit->state!=CANIF_CS_UNINIT), 0x3, CAN_E_UNINIT );\r
+ canHw = GetController(controller);\r
+\r
+ switch(transition )\r
+ {\r
+ case CAN_T_START:\r
+ canUnit->state = CANIF_CS_STARTED;\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if (canUnit->lock_cnt == 0){ // REQ CAN196\r
+ Can_EnableControllerInterrupts(controller);
+ }\r
+ McuE_ExitCriticalSection(state);\r
+ break;\r
+ case CAN_T_WAKEUP:
+ VALIDATE(canUnit->state == CANIF_CS_SLEEP, 0x3, CAN_E_TRANSITION);
+ CAN_WakeUp(canHw);
+ canUnit->state = CANIF_CS_STOPPED;
+ break;\r
+ case CAN_T_SLEEP: //CAN258, CAN290\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ CAN_Sleep(canHw);
+ canUnit->state = CANIF_CS_SLEEP;
+ break;
+ case CAN_T_STOP:\r
+ // Stop\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_AbortTx( canHw, canUnit ); // CANIF282\r
+ break;\r
+ default:\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ break;\r
+ }\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+ Can_UnitType *canUnit;\r
+ CAN_HW_t *canHw;\r
+\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x4, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x4, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if(canUnit->lock_cnt > 0 )\r
+ {\r
+ // Interrupts already disabled\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ }\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ /* Don't try to be intelligent, turn everything off */\r
+ canHw = GetController(controller);\r
+\r
+ /* Turn off the tx interrupt mailboxes */\r
+ CAN_ITConfig(canHw, CAN_IT_TME, DISABLE);\r
+
+ /* Turn off the bus off/tx warning/rx warning and error and rx */\r
+ CAN_ITConfig(canHw, CAN_IT_FMP0 | CAN_IT_BOF | CAN_IT_ERR | CAN_IT_WKU, DISABLE);
+}\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller ) {\r
+ Can_UnitType *canUnit;\r
+ CAN_HW_t *canHw;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x5, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x5, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if( canUnit->lock_cnt > 1 )\r
+ {\r
+ // IRQ should still be disabled so just decrement counter\r
+ canUnit->lock_cnt--;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ } else if (canUnit->lock_cnt == 1)\r
+ {\r
+ canUnit->lock_cnt = 0;\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ canHw = GetController(controller);\r
+\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);\r
+\r
+ if( canHwConfig->CanRxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the rx interrupt */\r
+ CAN_ITConfig(canHw, CAN_IT_FMP0, ENABLE);
+ }
+ if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
+ /* Turn on the tx interrupt mailboxes */
+ CAN_ITConfig(canHw, CAN_IT_TME, ENABLE);
+ }\r
+\r
+ // BusOff here represents all errors and warnings\r
+ if( canHwConfig->CanBusOffProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the bus off/tx warning/rx warning and error and rx */
+ CAN_ITConfig(canHw, CAN_IT_BOF | CAN_IT_ERR | CAN_IT_WKU, ENABLE);
+ }\r
+\r
+ return;\r
+}\r
+
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo ) {\r
+ Can_ReturnType rv = CAN_OK;\r
+ CAN_HW_t *canHw;\r
+ const Can_HardwareObjectType *hohObj;\r
+ const Can_ControllerConfigType *canHwConfig;
+ uint32 controller;\r
+ uint32 oldMsr;\r
+
+ VALIDATE( (Can_Global.initRun == CAN_READY), 0x6, CAN_E_UNINIT );\r
+ VALIDATE( (pduInfo != NULL), 0x6, CAN_E_PARAM_POINTER );\r
+ VALIDATE( (pduInfo->length <= 8), 0x6, CAN_E_PARAM_DLC );\r
+ VALIDATE( (hth < NUM_OF_HTHS ), 0x6, CAN_E_PARAM_HANDLE );\r
+\r
+ hohObj = Can_FindHoh(hth, &controller);\r
+ if (hohObj == NULL)\r
+ return CAN_NOT_OK;\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ canHw = GetController(controller);\r
+ oldMsr = McuE_EnterCriticalSection();\r
+
+ CanTxMsg TxMessage;
+
+ TxMessage.RTR=CAN_RTR_DATA;
+ TxMessage.DLC=pduInfo->length;
+
+ memcpy(TxMessage.Data, pduInfo->sdu, pduInfo->length);
+
+ if (hohObj->CanIdType == CAN_ID_TYPE_EXTENDED) {
+ TxMessage.IDE=CAN_ID_EXT;
+ TxMessage.ExtId=pduInfo->id;
+ } else {
+ TxMessage.IDE=CAN_ID_STD;
+ TxMessage.StdId=pduInfo->id;
+ }\r
+
+ // check for any free box\r
+ if(CAN_Transmit(canHw,&TxMessage) != CAN_NO_MB) {
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);
+
+ if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
+ /* Turn on the tx interrupt mailboxes */
+ CAN_ITConfig(canHw,CAN_IT_TME, ENABLE);
+ }
+
+ // Increment statistics
+ canUnit->stats.txSuccessCnt++;\r
+
+ // Store pdu handle in unit to be used by TxConfirmation\r
+ canUnit->swPduHandle = pduInfo->swPduHandle;\r
+ } else {\r
+ rv = CAN_BUSY;\r
+ }\r
+ McuE_ExitCriticalSection(oldMsr);\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_MainFunction_Read( void ) {\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_BusOff( void ) {\r
+ /* Bus-off polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_Wakeup( void ) {\r
+ /* Wakeup polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+\r
+/**\r
+ * Get send/receive/error statistics for a controller\r
+ *\r
+ * @param controller The controller\r
+ * @param stats Pointer to data to copy statistics to\r
+ */\r
+\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType *stats)\r
+{\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+ *stats = canUnit->stats;\r
+}\r
+\r
+#else // Stub all functions for use in simulator environment\r
+\r
+#include "debug.h"\r
+\r
+void Can_Init( const Can_ConfigType *Config )\r
+{\r
+ // Do initial configuration of layer here\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)\r
+{\r
+ // Do initialisation of controller here.\r
+}\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 Controller, Can_StateTransitionType transition )\r
+{\r
+ // Turn on off controller here depending on transition\r
+ return E_OK;\r
+}\r
+\r
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo )\r
+{\r
+ // Write to mailbox on controller here.\r
+ DEBUG(DEBUG_MEDIUM, "Can_Write(stub): Received data ");\r
+ for (int i = 0; i < pduInfo->length; i++) {\r
+ DEBUG(DEBUG_MEDIUM, "%d ", pduInfo->sdu[i]);\r
+ }\r
+ DEBUG(DEBUG_MEDIUM, "\n");\r
+\r
+ return E_OK;\r
+}\r
+\r
+extern void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc, const uint8 *CanSduPtr);\r
+Can_ReturnType Can_ReceiveAFrame()\r
+{\r
+ // This function is not part of autosar but needed to feed the stack with data\r
+ // from the mailboxes. Normally this is an interrup but probably not in the PCAN case.\r
+ uint8 CanSduData[] = {1,2,1,0,0,0,0,0};\r
+ CanIf_RxIndication(CAN_HRH_0_1, 3, 8, CanSduData);\r
+\r
+ return E_OK;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+\r
+// Hth - for Flexcan, the hardware message box number... .We don't care\r
+void Can_Cbk_CheckWakeup( uint8 controller ){}\r
+\r
+void Can_MainFunction_Write( void ){}\r
+void Can_MainFunction_Read( void ){}\r
+void Can_MainFunction_BusOff( void ){}\r
+void Can_MainFunction_Wakeup( void ){}\r
+\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType * stat){}\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Dio.h"\r
+#include "Det.h"\r
+#include <string.h>\r
+#include "stm32f10x_gpio.h"\r
+\r
+typedef GPIO_TypeDef* GPIO_TypeDefPtr;\r
+const GPIO_TypeDefPtr GPIO_ports[] = { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF };\r
+\r
+#define DIO_GET_PORT_FROM_CHANNEL_ID(_channelId) (_channelId / 16)\r
+#define DIO_GET_BIT_FROM_CHANNEL_ID(_channelId) (1 << (_channelId % 16))\r
+\r
+#define CHANNEL_PTR (&DioChannelConfigData)\r
+#define PORT_PTR (&DioPortConfigData)\r
+#define CHANNEL_GRP_PTR (&DioConfigData)\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+static int Channel_Config_Contains(Dio_ChannelType channelId)\r
+{\r
+ Dio_ChannelType* ch_ptr=(Dio_ChannelType*)CHANNEL_PTR;\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*ch_ptr)\r
+ {\r
+ if (*ch_ptr==channelId)\r
+ {\r
+ rv=1;\r
+ break;\r
+ }\r
+ ch_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Port_Config_Contains(Dio_PortType portId)\r
+{\r
+ Dio_PortType* port_ptr=(Dio_PortType*)PORT_PTR;\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*port_ptr)\r
+ {\r
+ if (*port_ptr==portId)\r
+ { rv=1; break;}\r
+ port_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Channel_Group_Config_Contains(const Dio_ChannelGroupType* _channelGroupIdPtr)\r
+{\r
+ Dio_ChannelGroupType* chGrp_ptr=(Dio_ChannelGroupType*)CHANNEL_GRP_PTR;\r
+ int rv=0;\r
+\r
+ while (DIO_END_OF_LIST!=chGrp_ptr->port)\r
+ {\r
+ if (chGrp_ptr->port==_channelGroupIdPtr->port&&\r
+ chGrp_ptr->offset==_channelGroupIdPtr->offset&&\r
+ chGrp_ptr->mask==_channelGroupIdPtr->mask)\r
+ { rv=1; break;}\r
+ chGrp_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+#define VALIDATE_CHANNEL(_channelId, _api) \\r
+ if(0==Channel_Config_Contains(channelId)) { \\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_CHANNEL_ID ); \\r
+ level = 0; \\r
+ goto cleanup; \\r
+ }\r
+#define VALIDATE_PORT(_portId, _api)\\r
+ if(0==Port_Config_Contains(_portId)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_PORT_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\\r
+ if(0==Channel_Group_Config_Contains(_channelGroupIdPtr)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_GROUP_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#else\r
+#define VALIDATE_CHANNEL(_channelId, _api)\r
+#define VALIDATE_PORT(_portId, _api)\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\r
+#endif\r
+\r
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId)\r
+{\r
+ Dio_LevelType level = 0;\r
+ VALIDATE_PORT(portId, DIO_READPORT_ID);\r
+\r
+ level = GPIO_ReadInputData(GPIO_ports[portId]);\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
+}\r
+\r
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level)\r
+{\r
+ VALIDATE_PORT(portId, DIO_WRITEPORT_ID);\r
+\r
+ GPIO_Write(GPIO_ports[portId], level);\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
+\r
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNEL(channelId, DIO_READCHANNEL_ID);\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId));\r
+ Dio_PortLevelType bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if ((portVal & bit) != STD_LOW){\r
+ level = STD_HIGH;\r
+ } else{\r
+ level = STD_LOW;\r
+ }\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return (level);\r
+}\r
+\r
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level)\r
+{\r
+ VALIDATE_CHANNEL(channelId, DIO_WRITECHANNEL_ID);\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId));\r
+ Dio_PortLevelType bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if(level == STD_HIGH){\r
+ portVal |= bit;\r
+ }else{\r
+ portVal &= ~bit;\r
+ }\r
+\r
+ Dio_WritePort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId), portVal);\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
+\r
+\r
+Dio_PortLevelType Dio_ReadChannelGroup(\r
+ const Dio_ChannelGroupType *channelGroupIdPtr)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_READCHANNELGROUP_ID);\r
+\r
+ // Get masked values\r
+ level = Dio_ReadPort(channelGroupIdPtr->port) & channelGroupIdPtr->mask;\r
+\r
+ // Shift down\r
+ level = level >> channelGroupIdPtr->offset;\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
+}\r
+\r
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr,\r
+ Dio_PortLevelType level)\r
+{\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_WRITECHANNELGROUP_ID);\r
+\r
+ // Shift up and apply mask so that no unwanted bits are affected\r
+ level = (level << channelGroupIdPtr->offset) & channelGroupIdPtr->mask;\r
+\r
+ // Read port and clear out masked bits\r
+ Dio_PortLevelType portVal = Dio_ReadPort(channelGroupIdPtr->port) & (~channelGroupIdPtr->mask);\r
+\r
+ // Or in the upshifted masked level\r
+ portVal |= level;\r
+\r
+ Dio_WritePort(channelGroupIdPtr->port, portVal);\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "stm32f10x_flash.h"\r
+#include "Fls.h"\r
+\r
+static Fls_ConfigType const *flsConfigPtr;\r
+\r
+void Fls_Init(const Fls_ConfigType *ConfigPtr)\r
+{\r
+ flsConfigPtr = ConfigPtr;\r
+}\r
+\r
+Std_ReturnType Fls_Erase(Fls_AddressType TargetAddress, Fls_LengthType Length)\r
+{\r
+ Fls_AddressType pageStart = 0;\r
+ Fls_AddressType erased = 0;\r
+ u32 page = 0;\r
+ u32 pageIndex;\r
+\r
+ /* Unlock the Flash Program Erase controller */\r
+ FLASH_Unlock();\r
+ /* Clear All pending flags */\r
+ FLASH_ClearFlag(FLASH_FLAG_BSY | FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR);\r
+\r
+ /* Find first sector. */\r
+ page = (TargetAddress - flsConfigPtr->FlsSectorList[0].FlsSectorStartaddress) / flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ pageStart = flsConfigPtr->FlsSectorList[0].FlsSectorStartaddress + page * flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ //page = Length / flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+\r
+ /* Erase the pages... */\r
+ for (pageIndex = page; erased < Length; pageIndex++)\r
+ {\r
+ volatile FLASH_Status status = FLASH_BUSY;\r
+ while(status != FLASH_COMPLETE){\r
+ status = FLASH_ErasePage((uint32_t)pageStart);\r
+ }\r
+ erased += flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ pageStart += flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ }\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Fls_Write(Fls_AddressType TargetAddress, const uint8 *SourceAddressPtr, Fls_LengthType Length)\r
+{\r
+ FLASH_Status stResult;\r
+ Fls_LengthType len = Length;\r
+ Fls_AddressType addr = TargetAddress;\r
+ const uint8 *srcPtr = SourceAddressPtr;\r
+\r
+ while (len >= sizeof(uint32_t))\r
+ {\r
+ stResult = FLASH_ProgramWord((uint32_t)addr, (uint32_t)*(uint32_t *)srcPtr);\r
+ srcPtr += sizeof(uint32_t);\r
+ addr += sizeof(uint32_t);\r
+ len -= sizeof(uint32_t);\r
+ }\r
+\r
+ if (len == sizeof(uint16_t))\r
+ {\r
+ FLASH_ProgramHalfWord((uint32_t)addr, (uint16_t)*(uint16_t *)srcPtr);\r
+ srcPtr += sizeof(uint16_t);\r
+ addr += sizeof(uint16_t);\r
+ len -= sizeof(uint16_t);\r
+ }\r
+\r
+ return E_OK;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#include "Std_Types.h"\r
+//#include "Det.h"\r
+#include "Gpt.h"\r
+#include <string.h>\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#include "irq.h"\r
+#include "arc.h"\r
+#endif\r
+#include "stm32f10x.h"\r
+\r
+\r
+\r
+//TIM2->DIER =\r
+\r
+\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Gpt.h"\r
+#include "Cpu.h"\r
+#include <assert.h>\r
+#include <string.h>\r
+#include "Mcu.h"\r
+#include "Det.h"\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#include "irq.h"\r
+#endif\r
+\r
+// Implementation specific\r
+/* STM32 helper arrays\r
+ *
+ */\r
+TIM_TypeDef * const TimAddr[] =\r
+{\r
+ ((TIM_TypeDef *)TIM1_BASE),\r
+ ((TIM_TypeDef *)TIM2_BASE),\r
+ ((TIM_TypeDef *)TIM3_BASE),\r
+ ((TIM_TypeDef *)TIM4_BASE),\r
+ ((TIM_TypeDef *)TIM5_BASE),\r
+ ((TIM_TypeDef *)TIM6_BASE),\r
+ ((TIM_TypeDef *)TIM7_BASE),\r
+};\r
+\r
+#if ( GPT_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+\r
+#define VALID_CHANNEL(_ch) ( Gpt_Global.configured & (1<<(_ch)) )\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+const uint32 IrqVector[] =\r
+{\r
+ TIM1_UP_IRQn,\r
+ TIM2_IRQn,\r
+ TIM3_IRQn,\r
+ TIM4_IRQn,\r
+};\r
+\r
+typedef enum\r
+{\r
+ GPT_STATE_STOPPED = 0,\r
+ GPT_STATE_STARTED,\r
+} Gpt_StateType;\r
+\r
+/**\r
+ * Type that holds all global data for Gpt\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Gpt_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Gpt_ConfigType *config;\r
+\r
+ uint8 wakeupEnabled;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[GPT_CHANNEL_CNT];\r
+\r
+} Gpt_GlobalType;\r
+\r
+/**\r
+ * Type that holds data that are specific for a channel\r
+ */\r
+typedef struct\r
+{\r
+ Gpt_StateType state;\r
+} Gpt_UnitType;\r
+\r
+Gpt_UnitType Gpt_Unit[GPT_CHANNEL_CNT];\r
+\r
+// Global config\r
+Gpt_GlobalType Gpt_Global;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+/**\r
+ * ISR helper-function that handles the HW channels( 0 to 8 )\r
+ *\r
+ * @param channel - Channel that the raised the interrupt\r
+ */\r
+static void Gpt_IsrCh(Gpt_ChannelType channel)\r
+{\r
+ const Gpt_ConfigType *config;\r
+ int confCh;\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+ assert(confCh != GPT_CHANNEL_ILL);\r
+\r
+ config = &Gpt_Global.config[confCh];\r
+\r
+ if (config->GptChannelMode == GPT_MODE_ONESHOT)\r
+ {\r
+ // Disable the channel\r
+ TimAddr[channel]->CR1 &= ~TIM_CR1_CEN;\r
+\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+ }\r
+ config->GptNotification();\r
+\r
+ // Clear interrupt\r
+ TimAddr[channel]->SR &= ~TIM_SR_UIF;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+// Macro that counts leading zeroes.\r
+#define CNTLZW_INV(x) (31-cntlzw(x))\r
+\r
+/**\r
+ * ISR that handles all interrupts\r
+ */\r
+static void Gpt_Isr(void)\r
+{\r
+ static int i;\r
+ int found = 0;\r
+ /* Find channel for this interrupt. */\r
+ for (i = 0; ((i < GPT_CHANNEL_CNT) && !found);i++)\r
+ {\r
+ found = (((TimAddr[i]->SR & TIM_SR_UIF) == TIM_SR_UIF) &&\r
+ ((TimAddr[i]->CR1 & TIM_CR1_CEN) == TIM_CR1_CEN));\r
+ }\r
+ if (found)\r
+ {\r
+ Gpt_IsrCh(i - 1);\r
+ }\r
+}\r
+//-------------------------------------------------------------------\r
+\r
+void Gpt_Init(const Gpt_ConfigType *config)\r
+{\r
+ uint32_t i=0;\r
+ const Gpt_ConfigType *cfg;\r
+ VALIDATE( (Gpt_Global.initRun == STD_OFF), GPT_INIT_SERVICE_ID, GPT_E_ALREADY_INITIALIZED );\r
+#if defined(GPT_VARIANT_PB)\r
+ VALIDATE( (config != NULL ), GPT_INIT_SERVICE_ID, GPT_E_PARAM_CONFIG );\r
+#elif defined(GPT_VARIANT_PC)\r
+ // We don't support GPT_VARIANT_PC\r
+ assert(0);\r
+#endif\r
+ Gpt_ChannelType ch;\r
+\r
+ for (i=0; i<GPT_CHANNEL_CNT; i++)\r
+ {\r
+ Gpt_Global.channelMap[i] = GPT_CHANNEL_ILL;\r
+ }\r
+\r
+ i = 0;\r
+ cfg = config;\r
+ while (cfg->GptChannelId != GPT_CHANNEL_ILL)\r
+ {\r
+ ch = cfg->GptChannelId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Gpt_Global.channelMap[cfg->GptChannelId] = i;\r
+ Gpt_Global.configured |= (1<<ch);\r
+\r
+ if (ch <= GPT_CHANNEL_CNT)\r
+ {\r
+ if (cfg->GptNotification != NULL)\r
+ {\r
+\r
+#if defined(USE_KERNEL)\r
+ TaskType tid;\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr, 6, "Gpt_Isr");\r
+ Irq_AttachIsr2(tid, NULL, IrqVector[ch]);\r
+#else\r
+ //IntCtrl_InstallVector(Gpt_Isr, PIT_PITFLG_RTIF + ch, 1, CPU_Z1); TODO\r
+#endif\r
+ }\r
+ }\r
+#if defined(USE_KERNEL)\r
+ // Don't install if we use kernel.. it handles that.\r
+#else\r
+\r
+#endif\r
+\r
+ cfg++;\r
+ i++;\r
+ }\r
+\r
+ Gpt_Global.config = config;\r
+\r
+ Gpt_Global.initRun = STD_ON;\r
+ //PIT.CTRL.B.MDIS = 0;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if GPT_DEINIT_API == STD_ON\r
+void Gpt_DeInit(void)\r
+{\r
+ Gpt_ChannelType channel;\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DEINIT_SERVICE_ID, GPT_E_UNINIT );\r
+ for (channel=0; channel<GPT_CHANNEL_CNT; channel++) // Validate that all channels have been stopped\r
+ {\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_DEINIT_SERVICE_ID, GPT_E_BUSY );\r
+ Gpt_StopTimer(channel); // Should this be done here?\r
+ }\r
+ Gpt_Global.initRun = STD_OFF;\r
+ Gpt_Global.configured = 0;\r
+ //_config.config = NULL;\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+// period is in "ticks" !!\r
+void Gpt_StartTimer(Gpt_ChannelType channel, Gpt_ValueType period_ticks)\r
+{\r
+ int confCh;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STARTTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STARTTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ VALIDATE( (Gpt_Unit[channel].state == GPT_STATE_STOPPED), GPT_STARTTIMER_SERVICE_ID, GPT_E_BUSY );\r
+ // GPT_E_PARAM_VALUE, all have 32-bit so no need to check\r
+\r
+ //DEBUG(DEBUG_HIGH, "Gpt_StartTimer ch=%d, period=%d [ticks]\n", channel, period_ticks);\r
+\r
+ confCh = Gpt_Global.channelMap[channel];\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ uint32 *tlval = (uint32 *)&(TimAddr[channel]->ARR);\r
+ uint32 *tval = (uint32 *)&(TimAddr[channel]->CNT);\r
+\r
+ *tlval = period_ticks;\r
+ *tval = period_ticks;\r
+\r
+ // always select interrupt\r
+ //TimAddr[channel]->DIER |= TIM_DIER_UIE;\r
+\r
+ // Make sure that no interrupt is pending.\r
+ TimAddr[channel]->SR &= ~TIM_SR_UIF;\r
+\r
+ // Set prescaler.\r
+ TimAddr[channel]->PSC = Gpt_Global.config[confCh].GptChannelPrescale;\r
+\r
+ // Enable timer\r
+ TimAddr[channel]->CR1 |= (TIM_CR1_CEN | TIM_CR1_URS | TIM_CR1_DIR);\r
+ TimAddr[channel]->CR1 &= ~TIM_CR1_UDIS;\r
+ }\r
+ #if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
+ if( Gpt_Global.config[confCh].GptNotification != NULL )\r
+ {\r
+ // GPT275\r
+ Gpt_EnableNotification(channel);\r
+ }\r
+ #endif\r
+ Gpt_Unit[channel].state = GPT_STATE_STARTED;\r
+}\r
+\r
+void Gpt_StopTimer(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STOPTIMER_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_STOPTIMER_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ // Disable timer\r
+ TimAddr[channel]->CR1 &= ~TIM_CR1_CEN;\r
+ }\r
+ #if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
+ Gpt_DisableNotification(channel);\r
+ #endif\r
+ Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+}\r
+\r
+#if ( GPT_TIME_REMAINING_API == STD_ON )\r
+\r
+Gpt_ValueType Gpt_GetTimeRemaining(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_UNINIT, 0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED), GPT_GETTIMEREMAINING_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+ Gpt_ValueType remaining;\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ uint32 *tval = (uint32 *)&(TimAddr[channel]->CNT);\r
+ // Time remaining is the time until it hits 0, so just return the current timer value\r
+ remaining = *tval;\r
+ }\r
+\r
+ return remaining;\r
+}\r
+#endif\r
+\r
+#if ( GPT_TIME_ELAPSED_API == STD_ON )\r
+Gpt_ValueType Gpt_GetTimeElapsed(Gpt_ChannelType channel)\r
+{\r
+ Gpt_ValueType timer;\r
+\r
+ VALIDATE_W_RV( (Gpt_Global.initRun == STD_ON), GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_UNINIT ,0 );\r
+ VALIDATE_W_RV( VALID_CHANNEL(channel),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_PARAM_CHANNEL, 0 );\r
+ VALIDATE_W_RV( (Gpt_Unit[channel].state == GPT_STATE_STARTED),GPT_GETTIMEELAPSED_SERVICE_ID, GPT_E_NOT_STARTED, 0 );\r
+\r
+ // NOTE!\r
+ // These little creatures count down\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ uint32 *tlval = (uint32 *)&(TimAddr[channel]->ARR);\r
+ uint32 *tval = (uint32 *)&(TimAddr[channel]->CNT);\r
+ timer = *tlval - *tval;\r
+ }\r
+\r
+ return (timer);\r
+}\r
+#endif\r
+\r
+#if ( GPT_ENABLE_DISABLE_NOTIFICATION_API == STD_ON )\r
+void Gpt_EnableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x7, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x7, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ // enable interrupts\r
+ TimAddr[channel]->DIER |= TIM_DIER_UIE;\r
+ }\r
+}\r
+\r
+void Gpt_DisableNotification(Gpt_ChannelType channel)\r
+{\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), 0x8, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),0x8, GPT_E_PARAM_CHANNEL );\r
+\r
+ if (channel <= GPT_CHANNEL_CNT)\r
+ {\r
+ TimAddr[channel]->DIER &= ~TIM_DIER_UIE;\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+#endif\r
+\r
+#if ( GPT_WAKEUP_FUNCTIONALITY_API == STD_ON )\r
+\r
+void Gpt_SetMode(Gpt_ModeType mode)\r
+{\r
+ int i;\r
+\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_SETMODE_SERVIVCE_ID, GPT_E_UNINIT );\r
+ VALIDATE( ( mode <= GPT_MODE_SLEEP ), GPT_SETMODE_SERVIVCE_ID, GPT_E_PARAM_MODE );\r
+\r
+ if (mode == GPT_MODE_NORMAL)\r
+ {\r
+ //PIT.CTRL.B.MDIS = 0; TODO\r
+ // Do NOT restart channels\r
+ }\r
+ else if (mode == GPT_MODE_SLEEP)\r
+ {\r
+\r
+ //PIT.CTRL.B.MDIS = 1; TODO\r
+ // Disable all\r
+ for (i= 0; i <= GPT_CHANNEL_CNT; i++)\r
+ {\r
+ Gpt_StopTimer(i);\r
+ }\r
+ }\r
+}\r
+\r
+void Gpt_DisableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel), GPT_DISABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ // Only RTI have system wakeup\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_OFF;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_EnableWakeup(Gpt_ChannelType channel)\r
+{\r
+ VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_UNINIT );\r
+ VALIDATE( VALID_CHANNEL(channel),GPT_ENABLEWAKEUP_SERVICE_ID, GPT_E_PARAM_CHANNEL );\r
+ if (channel == GPT_CHANNEL_RTI)\r
+ {\r
+ Gpt_Global.wakeupEnabled = STD_ON;\r
+ }\r
+ else\r
+ {\r
+ // TODO:\r
+ //assert(0);\r
+ }\r
+}\r
+\r
+void Gpt_Cbk_CheckWakeup(EcuM_WakeupSourceType wakeupSource)\r
+{\r
+\r
+}\r
+\r
+#endif\r
+\r
#include "Dem.h"\r
#endif\r
#include <assert.h>\r
-#include "cpu.h"\r
+#include "Cpu.h"\r
#include <string.h>\r
#include "Ramlog.h"\r
-#include "system_stm32f10x.h"\r
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#include "debug.h"\r
\r
return NULL;\r
}\r
\r
-\r
-\r
/**\r
* Identify the core, just to check that we have support for it.\r
*\r
*/\r
static uint32 Mcu_CheckCpu( void ) {\r
\r
- uint32 pvr;\r
+ uint32 pvr = SCB->CPUID;\r
//uint32 pir;\r
//cpu_info_t *cpuType;\r
core_info_t *coreType;\r
return 0;\r
}\r
\r
+static uint32_t GetPllValueFromMult(uint8_t pll)\r
+{\r
+ return (((uint32_t)pll - 2) << 18);\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+static uint32_t GetPll2ValueFromMult(uint8_t pll)\r
+{\r
+ return (((uint32_t)pll - 2) << 8);\r
+}\r
+#endif\r
+\r
+/**\r
+ * Set bus clocks. SysClk,AHBClk,APB1Clk,APB2Clk\r
+ */\r
+static void SetClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+ volatile uint32 StartUpCounter = 0, HSEStatus = 0;\r
+\r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+ /* Enable HSE */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++;\r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ }\r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 2 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;\r
+\r
+\r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+\r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | GetPll2ValueFromMult(clockSettingsPtr->Pll2) |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+\r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |\r
+ GetPllValueFromMult(clockSettingsPtr->Pll1));\r
+#else\r
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
+ RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | GetPllValueFromMult(clockSettingsPtr->Pll1));\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* HSE fails to start-up, the application will have wrong clock */\r
+ NVIC_SystemReset();\r
+ }\r
+}\r
+\r
+/**\r
+ * Initialize Peripherals clocks\r
+ */\r
+static void InitPerClocks()\r
+{\r
+ RCC->AHBENR |= McuPerClockConfigData.AHBClocksEnable;\r
+ RCC->APB1ENR |= McuPerClockConfigData.APB1ClocksEnable;\r
+ RCC->APB2ENR |= McuPerClockConfigData.APB2ClocksEnable;\r
+}\r
+\r
+/**\r
+ * Initialize Flash, PLL and clocks.\r
+ */\r
+static void InitMcuClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifndef STM32F10X_CL\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#else\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+ /* Configure the Flash Latency cycles and enable prefetch buffer */\r
+ SetClocks(clockSettingsPtr);\r
+}\r
\r
//-------------------------------------------------------------------\r
\r
{\r
VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
\r
- if( !SIMULATOR() ) {\r
- Mcu_CheckCpu();\r
- }\r
+#if !defined(USE_SIMULATOR)\r
+ Mcu_CheckCpu();\r
+#endif\r
\r
memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
\r
-\r
- SystemInit();\r
-\r
Irq_Enable();\r
\r
Mcu_Global.config = configPtr;\r
Mcu_Global.clockSetting = ClockSetting;\r
clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
\r
+ InitMcuClocks(clockSettingsPtr);\r
+\r
+ InitPerClocks(clockSettingsPtr);\r
\r
return E_OK;\r
}\r
VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );\r
Mcu_PllStatusType rv;\r
\r
- if (!SIMULATOR()) {\r
- if (RCC->CR & RCC_CR_PLLRDY) {\r
- rv = MCU_PLL_LOCKED;\r
- } else {\r
- rv = MCU_PLL_UNLOCKED;\r
- }\r
- } else {\r
- /* We are running on instruction set simulator. PLL is then always in sync... */\r
+#if !defined(USE_SIMULATOR)\r
+ if (RCC->CR & RCC_CR_PLLRDY) {\r
rv = MCU_PLL_LOCKED;\r
+ } else {\r
+ rv = MCU_PLL_UNLOCKED;\r
}\r
-\r
+#else\r
+ /* We are running on instruction set simulator. PLL is then always in sync... */\r
+ rv = MCU_PLL_LOCKED;\r
+#endif\r
return rv;\r
}\r
\r
*/\r
uint32_t McuE_GetSystemClock(void)\r
{\r
- /*\r
- * System clock calculation\r
- *\r
- */\r
+ uint32_t f_sys;\r
\r
- // TODO: This of course wrong....\r
- uint32_t f_sys = 72000000UL;\r
-#if 0\r
uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;\r
-\r
- f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);\r
+ uint32 pll1 = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].Pll1;\r
+\r
+#ifdef STM32F10X_CL\r
+ uint32 pll2 = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].Pll2;\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * PLL2 */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 */\r
+ /* PLL configuration: PLLCLK = PREDIV1 * PLL1 */\r
+ f_sys = (extal / 5 * pll2) / 5 * pll1;\r
+#else\r
+ /* PLL configuration: PLLCLK = HSE * PLL1 */\r
+ f_sys = extal * pll1;\r
#endif\r
\r
-// f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));\r
return f_sys;\r
}\r
\r
imask_t McuE_EnterCriticalSection()\r
{\r
-#if 0\r
- uint32_t msr = get_msr();\r
- Irq_Disable();\r
- return msr;\r
-#endif\r
- return 0;\r
+ uint32_t val;\r
+ Irq_Save(val);\r
+ return val;\r
}\r
\r
void McuE_ExitCriticalSection(uint32_t old_state)\r
{\r
-#if 0\r
- set_msr(old_state);\r
-#endif\r
+ Irq_Restore(old_state);\r
}\r
\r
/**\r
* Get the peripheral clock in Hz for a specific device\r
*/\r
-\r
-#if 0\r
uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
{\r
+ uint32_t res = 0;\r
+\r
+ switch(type)\r
+ {\r
+ case PERIPHERAL_CLOCK_AHB:\r
+ res = McuE_GetSystemClock();\r
+ break;\r
+ case PERIPHERAL_CLOCK_APB1:\r
+ res = McuE_GetSystemClock() / 2;\r
+ break;\r
+ case PERIPHERAL_CLOCK_APB2:\r
+ res = McuE_GetSystemClock();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
\r
- return 0;\r
+ return res;\r
}\r
-#endif\r
\r
\r
/**\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Port.h" /** @req PORT131 */\r
+#include "stm32f10x.h"\r
+#include "Det.h"\r
+#include "string.h"\r
+#include "stm32f10x_gpio.h"\r
+\r
+const uint32 *GpioBaseAddr[] =\r
+{\r
+ (uint32 *)GPIOA_BASE,\r
+ (uint32 *)GPIOB_BASE,\r
+ (uint32 *)GPIOC_BASE,\r
+ (uint32 *)GPIOD_BASE,\r
+ (uint32 *)GPIOE_BASE,\r
+ (uint32 *)GPIOF_BASE,\r
+ (uint32 *)GPIOG_BASE\r
+};\r
+\r
+const uint32 *GpioODRAddr[] =\r
+{\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOA_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOB_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOC_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOD_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOE_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOF_BASE)->ODR,\r
+ (uint32 *)&((GPIO_TypeDef *)GPIOG_BASE)->ODR\r
+};\r
+\r
+typedef enum\r
+{\r
+ PORT_UNINITIALIZED = 0, PORT_INITIALIZED,\r
+} Port_StateType;\r
+\r
+static Port_StateType _portState = PORT_UNINITIALIZED;\r
+static Port_ConfigType * _configPtr = NULL;\r
+\r
+/** @req PORT107 */\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api) \\r
+ if( (_ptr)==((void *)0) ) { \\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_CONFIG ); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_STATE_INIT(_api)\\r
+ if(PORT_INITIALIZED!=_portState){\\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_UNINIT ); \\r
+ return; \\r
+ }\r
+\r
+#else\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api)\r
+#define VALIDATE_STATE_INIT(_api)\r
+#define VALIDATE_PARAM_PIN(_api)\r
+#endif\r
+\r
+#if (PORT_VERSION_INFO_API == STD_ON)\r
+static Std_VersionInfoType _Port_VersionInfo =\r
+{ .vendorID = (uint16)1, .moduleID = (uint16) MODULE_ID_PORT,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)PORT_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)PORT_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)PORT_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)PORT_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)PORT_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)PORT_AR_PATCH_VERSION, };\r
+#endif\r
+\r
+/** @req PORT140 */\r
+/** @req PORT041 Comment: To reduce flash usage the configuration tool can disable configuration of some ports */\r
+/** @req PORT078 See environment i.e Ecu State Manager */\r
+/** @req PORT042 */\r
+/** @req PORT113 Number 2 in list is applicable for all pins. */\r
+/** @req PORT043 Comment: Output value is set before direction */\r
+/** @req PORT071 See environment i.e Ecu State Manager */\r
+/** @req PORT002 The _portState varialble is initialised. */\r
+/** @req PORT003 See environment i.e Ecu State Manager */\r
+/** @req PORT055 Comment: Output value is set before direction */\r
+/** @req PORT121 */\r
+void Port_Init(const Port_ConfigType *configType)\r
+{\r
+ VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID); /** @req PORT105 */\r
+ volatile const uint32 *gpioAddr;\r
+\r
+ for (uint8_t i = 0; i < configType->padCnt; i++)\r
+ {\r
+ /* Configure pin. */\r
+ gpioAddr = GpioBaseAddr[i];\r
+ //*((GpioPinCnfMode_Type *)gpioAddr) = configType->padConfig[i];\r
+ *(uint32 *)gpioAddr = *(uint32 *)&configType->padConfig[i];\r
+ *(1+(uint32 *)gpioAddr) = *(1+(uint32 *)&configType->padConfig[i]);\r
+\r
+ /* Set default output level. */\r
+ gpioAddr = GpioODRAddr[i];\r
+ *((GpioPinOutLevel_Type *)gpioAddr) = configType->outConfig[i];\r
+ }\r
+\r
+ // Enable remaps\r
+ for (int portIndex = 0; portIndex < configType->remapCount; portIndex++) {\r
+ GPIO_PinRemapConfig(configType->remaps[portIndex], ENABLE);\r
+ }\r
+\r
+ _portState = PORT_INITIALIZED;\r
+ _configPtr = (Port_ConfigType *)configType;\r
+ return;\r
+}\r
+\r
+/** @req PORT141 */\r
+/** @req PORT063 */\r
+/** @req PORT054 */\r
+/** @req PORT086 */\r
+#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )\r
+void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
+\r
+ uint32 * gpioAddr;\r
+ static uint8 index, bit, reg;\r
+\r
+ index = pin / 16;\r
+ bit = pin % 16;\r
+ reg = bit / 8;\r
+ bit = (bit % 8) * 4;\r
+ // Ex. DIO_CHANNEL_B8 = 24\r
+ // index = 1 => GPIOB\r
+ // bit = 8\r
+ // reg = 1 => CRH\r
+ // bit = 0 => MODE8, CNF8 => OK\r
+ // 0 1 2\r
+ // 0 4 8\r
+ gpioAddr = (uint32 *)GpioBaseAddr[index];\r
+\r
+ /* Adjust for CRL/CRH */\r
+ gpioAddr += reg;\r
+\r
+ *gpioAddr &= ~(0x000000F << bit);\r
+\r
+ if (direction==PORT_PIN_IN)\r
+ {\r
+ /* Configure pin. */\r
+ //*gpioAddr |= (GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF) << bit; // TODO shall this be added to conf?\r
+ *gpioAddr |= (GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF) << bit; // TODO shall this be added to conf?\r
+ }\r
+ else\r
+ {\r
+ *gpioAddr |= (GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF) << bit; // TODO shall this be added to conf?\r
+ }\r
+\r
+ return;\r
+}\r
+#endif\r
+\r
+/** @req PORT066 */\r
+/** @req PORT142 */\r
+/** @req PORT060 */\r
+/** @req PORT061 */\r
+void Port_RefreshPortDirection(void)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);\r
+\r
+ /* TODO Not implemented yet */\r
+ return;\r
+}\r
+\r
+/** req PORT143 */\r
+/** req PORT102 */\r
+/** req PORT103 */\r
+#if (PORT_VERSION_INFO_API == STD_ON)\r
+void Port_GetVersionInfo(Std_VersionInfoType* versionInfo)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_GET_VERSION_INFO_ID);\r
+ memcpy(versionInfo, &_Port_VersionInfo, sizeof(Std_VersionInfoType));\r
+ return;\r
+}\r
+#endif\r
+\r
+/** req PORT145 */\r
+/** req PORT125 */\r
+/** req PORT128 */\r
+#if (PORT_SET_PIN_MODE_API == STD_ON)\r
+void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
+\r
+ // Mode of pins not changeable on this CPU\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+ Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_MODE_ID, PORT_E_MODE_UNCHANGEABLE );\r
+#endif\r
+\r
+ return;\r
+}\r
+#endif\r
--- /dev/null
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r
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+<div class="Section1">\r
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+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">\r
+<tbody>\r
+ <tr>\r
+ <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../Release_Notes.html">Back to Release page</a></span></td>\r
+ </tr>\r
+<tr style="">\r
+<td style="padding: 1.5pt;">\r
+<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release\r
+Notes for STM32F10x Standard Peripherals Library Drivers\r
+(StdPeriph_Driver)</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2010 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>\r
+<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">\r
+<tbody>\r
+<tr>\r
+<td style="padding: 0cm;" valign="top">\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>\r
+<ol style="margin-top: 0cm;" start="1" type="1">\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32F10x Standard Peripherals Library\r
+Drivers update History</a><o:p></o:p></span></li>\r
+<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>\r
+</ol>\r
+<span style="font-family: "Times New Roman";">\r
+</span>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32F10x Standard\r
+Peripherals Library Drivers update History</span></h2>\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.4.0\r
+- 10/15/2010</span></h3>\r
+\r
+ <ol style="margin-top: 0in;" start="1" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>\r
+ </ol>\r
+\r
+ <ul style="margin-top: 0in;" type="disc">\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x High-density value line </span>devices.</span></li>\r
+ </ul>\r
+\r
+ <ol style="margin-top: 0in;" start="2" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>\r
+ </ol>\r
+\r
+ \r
+ <ul style="margin-top: 0in;" type="disc">\r
+\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_bkp.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete BKP registers definition from stm32f10x_bkp.c and use defines within stm32f10x.h file. </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_can.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CAN registers definition from stm32f10x_can.c and use defines within stm32f10x.h file.<br>\r
+</span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Update the wording of some defines and Asserts macro. <br>\r
+ </span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetFlagStatus()\r
+and CAN_ClearFlag() functions: updated to support new flags (were not\r
+supported in previous version). These flags are: CAN_FLAG_RQCP0,\r
+CAN_FLAG_RQCP1, CAN_FLAG_RQCP2, CAN_FLAG_FMP1, CAN_FLAG_FF1,\r
+CAN_FLAG_FOV1, CAN_FLAG_FMP0, CAN_FLAG_FF0, CAN_FLAG_FOV0,\r
+CAN_FLAG_WKU, CAN_FLAG_SLAK and CAN_FLAG_LEC. <br>\r
+ </span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_GetITStatus()\r
+function: add a check of the interrupt enable bit before getting the\r
+status of corresponding interrupt pending bit. <br>\r
+ </span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">CAN_ClearITPendingBit() function: correct the procedure to clear the interrupt pending bit. <br>\r
+ </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_crc.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete CRC registers definition from stm32f10x_crc.c and use defines within stm32f10x.h file.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dac.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DAC registers definition from stm32f10x_dac.c and use defines within stm32f10x.h file. </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DBGMCU registers definition from stm32f10x_dbgmcu.c and use defines within stm32f10x.h file. </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dma.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete DMA registers definition from stm32f10x_dma.c and use defines within stm32f10x.h file.</span></span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new function "void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);"<br>\r
+ </span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">FLASH functions (Erase and Program) updated to always clear the "PG", "MER" and "PER" bits even in case of TimeOut Error.</span><span style="font-style: italic;"></span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_fsmc.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new member "FSMC_AsynchronousWait" in "FSMC_NORSRAMInitTypeDef" structure.</span><span style="font-style: italic;"></span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for TIM6, TIM7 and DAC DMA requests, TIM12 and DAC Triggers / DMA2_Channel5 Interrupt mapping.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_pwr.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete PWR registers definition from stm32f10x_pwr.c and use defines within stm32f10x.h and core_cm3.h files.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rtc.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Delete RTC registers definition from stm32f10x_rtc.c and use defines within stm32f10x.h file.</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_spi.h/.c</span></li>\r
+ <ul>\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for I2S Audio Clock frequencies "I2S_AudioFreq_192k".</span></span></li>\r
+ </ul>\r
+ <li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c</span></li>\r
+<ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">Add new definition for TIM Input Capture Polarity "TIM_ICPolarity_BothEdge".</span></span></li></ul>\r
+ \r
+ </ul>\r
+\r
+ <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.3.0\r
+- 04/16/2010</span></h3>\r
+\r
+<ol style="margin-top: 0in;" start="1" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li></ol>\r
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support for <span style="font-weight: bold;">STM32F10x XL-density </span>devices.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">I2C driver: events description and management enhancement.</span></li></ul>\r
+<ol style="margin-top: 0in;" start="2" type="1"><li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li></ol>\r
+<ul style="margin-top: 0in;" type="disc"><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_dbgmcu.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">DBGMCU_Config()</span> function: add new values <span style="font-style: italic;">DBGMCU_TIMx_STOP</span> (x: 9..14) for <span style="font-style: italic;">DBGMCU_Periph</span> parameter.</span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_flash.h/.c:\r
+updated to support Bank2 of XL-density devices (up to 1MByte of Flash\r
+memory). For more details, refer to the description provided within\r
+stm32f10x_flash.c file.</span></li><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_gpio.h/.c</span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">GPIO_PinRemapConfig()</span> function: add new values for <span style="font-style: italic;">GPIO_Remap</span> parameter, to support new <span style="font-style: italic;">remap for FSMC_NADV pin and TIM9..11,13,14.</span></span></li></ul><li class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_i2c.h/.c: I2C events description and management enhancement. <br></span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">I2C_CheckEvent()</span>\r
+function: updated to check whether the last event contains the\r
+I2C_EVENT (instead of check whether the last event is equal to\r
+I2C_EVENT)<br></span></li></ul><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add\r
+detailed description of I2C events and how to manage them using the\r
+functions provided by this driver. For more information, refer to\r
+stm32f10x_i2c.h and stm32f10x_i2c.c files.</span></li></ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.</span></li><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">stm32f10x_sdio.h: </span></li><ul><li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter<br>change <br> \r
+#define\r
+SDIO_ReadWaitMode_CLK \r
+ ((uint32_t)0x00000000)<br> #define\r
+SDIO_ReadWaitMode_DATA2 \r
+((uint32_t)0x00000001)<br>by<br> #define\r
+SDIO_ReadWaitMode_CLK \r
+ ((uint32_t)0x00000001)<br> #define\r
+SDIO_ReadWaitMode_DATA2 \r
+((uint32_t)0x00000000)</span></li></ul></ul>\r
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial; margin-right: 558.05pt;"><span style="font-size: 10pt; font-family: Arial; color: white;">3.2.0\r
+- 03/01/2010</span></h3>\r
+<ol style="margin-top: 0in;" start="1" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">General</span></i></b><i><span style="font-size: 10pt; font-family: Verdana;"> </span></i><i><span style="font-size: 10pt;"><o:p></o:p></span></i></li>\r
+</ol>\r
+<ul style="margin-top: 0in;" type="disc">\r
+\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add support\r
+for <b>STM32 Low-density Value line (STM32F100x4/6) and\r
+Medium-density Value line (STM32F100x8/B) devices</b>.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Almost\r
+peripherals drivers were updated to support Value\r
+line devices features</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Drivers limitations fix and enhancements. </span><span style="font-size: 10pt;"><o:p></o:p></span></li>\r
+\r
+</ul>\r
+<ol style="margin-top: 0in;" start="2" type="1">\r
+<li class="MsoNormal" style=""><b><i><span style="font-size: 10pt; font-family: Verdana;">STM32F10x_StdPeriph_Driver</span></i></b><b><i><span style="font-size: 10pt;"><o:p></o:p></span></i></b></li>\r
+</ol>\r
+<ul style="margin-top: 0in;" type="disc">\r
+<li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Add new\r
+firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM1_DMA, </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">USART\r
+driver: add support for Oversampling by 8 mode and onebit method. 2\r
+functions has been added: USART_OverSampling8Cmd() and\r
+USART_OneBitMethodCmd().<br>\r
+ </span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DAC\r
+driver: add new functions handling the DAC under run feature:\r
+DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus()\r
+and DAC_ClearITPendingBit().</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.<br>\r
+ </span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">FLASH\r
+driver: the FLASH_EraseOptionBytes() function updated. This is now just\r
+erasing the option bytes without modifying the RDP status either\r
+enabled or disabled.</span></li>\r
+ <li class="MsoNormal" style=""><span style="font-size: 10pt; font-family: Verdana;">PWR\r
+driver: the PWR_EnterSTOPMode() function updated. When woken up from\r
+STOP mode, this function resets again the SLEEPDEEP bit in the\r
+Cortex-M3 System Control register to allow Sleep mode entering.</span></li>\r
+ \r
+\r
+</ul>\r
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: -moz-initial; -moz-background-origin: -moz-initial; -moz-background-inline-policy: -moz-initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: Verdana; color: black;">The\r
+enclosed firmware and all the related documentation are not covered by\r
+a License Agreement, if you need such License you can contact your\r
+local STMicroelectronics office.<u1:p></u1:p><o:p></o:p></span></p>\r
+<p class="MsoNormal"><b style=""><span style="font-size: 10pt; font-family: Verdana; color: black;">THE\r
+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO\r
+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR\r
+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY\r
+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY\r
+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH\r
+THEIR PRODUCTS. <o:p></o:p></span></b></p>\r
+<p class="MsoNormal"><span style="color: black;"><o:p> </o:p></span></p>\r
+<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">\r
+<hr align="center" size="2" width="100%"></span></div>\r
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For\r
+complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32(<span style="color: black;">CORTEX M3) 32-Bit Microcontrollers\r
+visit </span><u><span style="color: blue;"><a href="http://www.st.com/stm32" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>\r
+</td>\r
+</tr>\r
+</tbody>\r
+</table>\r
+</div>\r
+<p class="MsoNormal"><o:p> </o:p></p>\r
+</div>\r
+</body></html>
\ No newline at end of file
-\r
/**\r
******************************************************************************\r
* @file misc.h\r
* @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
* @brief This file contains all the functions prototypes for the miscellaneous\r
* firmware library functions (add-on to CMSIS functions).\r
******************************************************************************\r
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
*\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
*/ \r
\r
/* Define to prevent recursive inclusion -------------------------------------*/\r
\r
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
\r
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)\r
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)\r
\r
/**\r
* @}\r
* @}\r
*/\r
\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_adc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the ADC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_ADC_H\r
+#define __STM32F10x_ADC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup ADC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief ADC Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or\r
+ dual mode. \r
+ This parameter can be a value of @ref ADC_mode */\r
+\r
+ FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in\r
+ Scan (multichannels) or Single (one channel) mode.\r
+ This parameter can be set to ENABLE or DISABLE */\r
+\r
+ FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in\r
+ Continuous or Single mode.\r
+ This parameter can be set to ENABLE or DISABLE. */\r
+\r
+ uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog\r
+ to digital conversion of regular channels. This parameter\r
+ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */\r
+\r
+ uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.\r
+ This parameter can be a value of @ref ADC_data_align */\r
+\r
+ uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted\r
+ using the sequencer for regular channel group.\r
+ This parameter must range from 1 to 16. */\r
+}ADC_InitTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
+ ((PERIPH) == ADC2) || \\r
+ ((PERIPH) == ADC3))\r
+\r
+#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \\r
+ ((PERIPH) == ADC3))\r
+\r
+/** @defgroup ADC_mode \r
+ * @{\r
+ */\r
+\r
+#define ADC_Mode_Independent ((uint32_t)0x00000000)\r
+#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)\r
+#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)\r
+#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)\r
+#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)\r
+#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)\r
+#define ADC_Mode_RegSimult ((uint32_t)0x00060000)\r
+#define ADC_Mode_FastInterl ((uint32_t)0x00070000)\r
+#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)\r
+#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)\r
+\r
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \\r
+ ((MODE) == ADC_Mode_RegInjecSimult) || \\r
+ ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \\r
+ ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \\r
+ ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \\r
+ ((MODE) == ADC_Mode_InjecSimult) || \\r
+ ((MODE) == ADC_Mode_RegSimult) || \\r
+ ((MODE) == ADC_Mode_FastInterl) || \\r
+ ((MODE) == ADC_Mode_SlowInterl) || \\r
+ ((MODE) == ADC_Mode_AlterTrig))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion \r
+ * @{\r
+ */\r
+\r
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */\r
+\r
+#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */\r
+\r
+#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */\r
+\r
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_None) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \\r
+ ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_data_align \r
+ * @{\r
+ */\r
+\r
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)\r
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)\r
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \\r
+ ((ALIGN) == ADC_DataAlign_Left))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_channels \r
+ * @{\r
+ */\r
+\r
+#define ADC_Channel_0 ((uint8_t)0x00)\r
+#define ADC_Channel_1 ((uint8_t)0x01)\r
+#define ADC_Channel_2 ((uint8_t)0x02)\r
+#define ADC_Channel_3 ((uint8_t)0x03)\r
+#define ADC_Channel_4 ((uint8_t)0x04)\r
+#define ADC_Channel_5 ((uint8_t)0x05)\r
+#define ADC_Channel_6 ((uint8_t)0x06)\r
+#define ADC_Channel_7 ((uint8_t)0x07)\r
+#define ADC_Channel_8 ((uint8_t)0x08)\r
+#define ADC_Channel_9 ((uint8_t)0x09)\r
+#define ADC_Channel_10 ((uint8_t)0x0A)\r
+#define ADC_Channel_11 ((uint8_t)0x0B)\r
+#define ADC_Channel_12 ((uint8_t)0x0C)\r
+#define ADC_Channel_13 ((uint8_t)0x0D)\r
+#define ADC_Channel_14 ((uint8_t)0x0E)\r
+#define ADC_Channel_15 ((uint8_t)0x0F)\r
+#define ADC_Channel_16 ((uint8_t)0x10)\r
+#define ADC_Channel_17 ((uint8_t)0x11)\r
+\r
+#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)\r
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)\r
+\r
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \\r
+ ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \\r
+ ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \\r
+ ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \\r
+ ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \\r
+ ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \\r
+ ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \\r
+ ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \\r
+ ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_sampling_time \r
+ * @{\r
+ */\r
+\r
+#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)\r
+#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)\r
+#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)\r
+#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)\r
+#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)\r
+#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)\r
+#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)\r
+#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)\r
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_7Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_13Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_28Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_41Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_55Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_71Cycles5) || \\r
+ ((TIME) == ADC_SampleTime_239Cycles5))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion \r
+ * @{\r
+ */\r
+\r
+#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */\r
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */\r
+\r
+#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */\r
+#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */\r
+\r
+#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */\r
+#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */\r
+\r
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \\r
+ ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_channel_selection \r
+ * @{\r
+ */\r
+\r
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)\r
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)\r
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)\r
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)\r
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_2) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_3) || \\r
+ ((CHANNEL) == ADC_InjectedChannel_4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_analog_watchdog_selection \r
+ * @{\r
+ */\r
+\r
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)\r
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)\r
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)\r
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)\r
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)\r
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)\r
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)\r
+\r
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \\r
+ ((WATCHDOG) == ADC_AnalogWatchdog_None))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define ADC_IT_EOC ((uint16_t)0x0220)\r
+#define ADC_IT_AWD ((uint16_t)0x0140)\r
+#define ADC_IT_JEOC ((uint16_t)0x0480)\r
+\r
+#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))\r
+\r
+#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \\r
+ ((IT) == ADC_IT_JEOC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define ADC_FLAG_AWD ((uint8_t)0x01)\r
+#define ADC_FLAG_EOC ((uint8_t)0x02)\r
+#define ADC_FLAG_JEOC ((uint8_t)0x04)\r
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)\r
+#define ADC_FLAG_STRT ((uint8_t)0x10)\r
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \\r
+ ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \\r
+ ((FLAG) == ADC_FLAG_STRT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_thresholds \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_offset \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_length \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_injected_rank \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ADC_regular_length \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_regular_rank \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_regular_discontinuous_mode_number \r
+ * @{\r
+ */\r
+\r
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void ADC_DeInit(ADC_TypeDef* ADCx);\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);\r
+void ADC_ResetCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_StartCalibration(ADC_TypeDef* ADCx);\r
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);\r
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);\r
+uint32_t ADC_GetDualModeConversionValue(void);\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);\r
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_ADC_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_bkp.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the BKP firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_BKP_H\r
+#define __STM32F10x_BKP_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup BKP\r
+ * @{\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Tamper_Pin_active_level \r
+ * @{\r
+ */\r
+\r
+#define BKP_TamperPinLevel_High ((uint16_t)0x0000)\r
+#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)\r
+#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \\r
+ ((LEVEL) == BKP_TamperPinLevel_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin \r
+ * @{\r
+ */\r
+\r
+#define BKP_RTCOutputSource_None ((uint16_t)0x0000)\r
+#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)\r
+#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)\r
+#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)\r
+#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_Alarm) || \\r
+ ((SOURCE) == BKP_RTCOutputSource_Second))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Data_Backup_Register \r
+ * @{\r
+ */\r
+\r
+#define BKP_DR1 ((uint16_t)0x0004)\r
+#define BKP_DR2 ((uint16_t)0x0008)\r
+#define BKP_DR3 ((uint16_t)0x000C)\r
+#define BKP_DR4 ((uint16_t)0x0010)\r
+#define BKP_DR5 ((uint16_t)0x0014)\r
+#define BKP_DR6 ((uint16_t)0x0018)\r
+#define BKP_DR7 ((uint16_t)0x001C)\r
+#define BKP_DR8 ((uint16_t)0x0020)\r
+#define BKP_DR9 ((uint16_t)0x0024)\r
+#define BKP_DR10 ((uint16_t)0x0028)\r
+#define BKP_DR11 ((uint16_t)0x0040)\r
+#define BKP_DR12 ((uint16_t)0x0044)\r
+#define BKP_DR13 ((uint16_t)0x0048)\r
+#define BKP_DR14 ((uint16_t)0x004C)\r
+#define BKP_DR15 ((uint16_t)0x0050)\r
+#define BKP_DR16 ((uint16_t)0x0054)\r
+#define BKP_DR17 ((uint16_t)0x0058)\r
+#define BKP_DR18 ((uint16_t)0x005C)\r
+#define BKP_DR19 ((uint16_t)0x0060)\r
+#define BKP_DR20 ((uint16_t)0x0064)\r
+#define BKP_DR21 ((uint16_t)0x0068)\r
+#define BKP_DR22 ((uint16_t)0x006C)\r
+#define BKP_DR23 ((uint16_t)0x0070)\r
+#define BKP_DR24 ((uint16_t)0x0074)\r
+#define BKP_DR25 ((uint16_t)0x0078)\r
+#define BKP_DR26 ((uint16_t)0x007C)\r
+#define BKP_DR27 ((uint16_t)0x0080)\r
+#define BKP_DR28 ((uint16_t)0x0084)\r
+#define BKP_DR29 ((uint16_t)0x0088)\r
+#define BKP_DR30 ((uint16_t)0x008C)\r
+#define BKP_DR31 ((uint16_t)0x0090)\r
+#define BKP_DR32 ((uint16_t)0x0094)\r
+#define BKP_DR33 ((uint16_t)0x0098)\r
+#define BKP_DR34 ((uint16_t)0x009C)\r
+#define BKP_DR35 ((uint16_t)0x00A0)\r
+#define BKP_DR36 ((uint16_t)0x00A4)\r
+#define BKP_DR37 ((uint16_t)0x00A8)\r
+#define BKP_DR38 ((uint16_t)0x00AC)\r
+#define BKP_DR39 ((uint16_t)0x00B0)\r
+#define BKP_DR40 ((uint16_t)0x00B4)\r
+#define BKP_DR41 ((uint16_t)0x00B8)\r
+#define BKP_DR42 ((uint16_t)0x00BC)\r
+\r
+#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \\r
+ ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \\r
+ ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \\r
+ ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \\r
+ ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \\r
+ ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \\r
+ ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \\r
+ ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \\r
+ ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \\r
+ ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \\r
+ ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \\r
+ ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \\r
+ ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \\r
+ ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42))\r
+\r
+#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void BKP_DeInit(void);\r
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);\r
+void BKP_TamperPinCmd(FunctionalState NewState);\r
+void BKP_ITConfig(FunctionalState NewState);\r
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);\r
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);\r
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);\r
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);\r
+FlagStatus BKP_GetFlagStatus(void);\r
+void BKP_ClearFlag(void);\r
+ITStatus BKP_GetITStatus(void);\r
+void BKP_ClearITPendingBit(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_BKP_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_can.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the CAN firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CAN_H\r
+#define __STM32F10x_CAN_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CAN\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Types\r
+ * @{\r
+ */\r
+\r
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \\r
+ ((PERIPH) == CAN2))\r
+\r
+/** \r
+ * @brief CAN init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */\r
+ \r
+ uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.\r
+ This parameter can be a value of @ref CAN_operating_mode */\r
+\r
+ uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware\r
+ is allowed to lengthen or shorten a bit to perform resynchronization.\r
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */\r
+\r
+ uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1.\r
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\r
+\r
+ uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.\r
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\r
+ \r
+ FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+ \r
+ FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. \r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+\r
+ FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+} CAN_InitTypeDef;\r
+\r
+/** \r
+ * @brief CAN filter init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit\r
+ configuration, first one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit\r
+ configuration, second one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (MSBs for a 32-bit configuration,\r
+ first one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,\r
+ according to the mode (LSBs for a 32-bit configuration,\r
+ second one for a 16-bit configuration).\r
+ This parameter can be a value between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.\r
+ This parameter can be a value of @ref CAN_filter_FIFO */\r
+ \r
+ uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */\r
+\r
+ uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.\r
+ This parameter can be a value of @ref CAN_filter_mode */\r
+\r
+ uint8_t CAN_FilterScale; /*!< Specifies the filter scale.\r
+ This parameter can be a value of @ref CAN_filter_scale */\r
+\r
+ FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.\r
+ This parameter can be set either to ENABLE or DISABLE. */\r
+} CAN_FilterInitTypeDef;\r
+\r
+/** \r
+ * @brief CAN Tx message structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter can be a value between 0 to 0x7FF. */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter can be a value between 0 to 0x1FFFFFFF. */\r
+\r
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.\r
+ This parameter can be a value of @ref CAN_identifier_type */\r
+\r
+ uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.\r
+ This parameter can be a value of @ref CAN_remote_transmission_request */\r
+\r
+ uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted.\r
+ This parameter can be a value between 0 to 8 */\r
+\r
+ uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */\r
+} CanTxMsg;\r
+\r
+/** \r
+ * @brief CAN Rx message structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t StdId; /*!< Specifies the standard identifier.\r
+ This parameter can be a value between 0 to 0x7FF. */\r
+\r
+ uint32_t ExtId; /*!< Specifies the extended identifier.\r
+ This parameter can be a value between 0 to 0x1FFFFFFF. */\r
+\r
+ uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received.\r
+ This parameter can be a value of @ref CAN_identifier_type */\r
+\r
+ uint8_t RTR; /*!< Specifies the type of frame for the received message.\r
+ This parameter can be a value of @ref CAN_remote_transmission_request */\r
+\r
+ uint8_t DLC; /*!< Specifies the length of the frame that will be received.\r
+ This parameter can be a value between 0 to 8 */\r
+\r
+ uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */\r
+\r
+ uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.\r
+ This parameter can be a value between 0 to 0xFF */\r
+} CanRxMsg;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN_sleep_constants \r
+ * @{\r
+ */\r
+\r
+#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */\r
+#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_operating_mode \r
+ * @{\r
+ */\r
+\r
+#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */\r
+#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */\r
+#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */\r
+#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */\r
+\r
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \\r
+ ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_synchronisation_jump_width \r
+ * @{\r
+ */\r
+\r
+#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+\r
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \\r
+ ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_1 \r
+ * @{\r
+ */\r
+\r
+#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
+#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
+#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
+#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
+#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */\r
+#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */\r
+#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */\r
+#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */\r
+#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */\r
+#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */\r
+#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */\r
+#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */\r
+\r
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_time_quantum_in_bit_segment_2 \r
+ * @{\r
+ */\r
+\r
+#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */\r
+#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */\r
+#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */\r
+#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */\r
+#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */\r
+#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */\r
+#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */\r
+#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */\r
+\r
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_clock_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_number \r
+ * @{\r
+ */\r
+#ifndef STM32F10X_CL\r
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13)\r
+#else\r
+ #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)\r
+#endif /* STM32F10X_CL */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_mode \r
+ * @{\r
+ */\r
+\r
+#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */\r
+#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */\r
+\r
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \\r
+ ((MODE) == CAN_FilterMode_IdList))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_scale \r
+ * @{\r
+ */\r
+\r
+#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */\r
+#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */\r
+\r
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \\r
+ ((SCALE) == CAN_FilterScale_32bit))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_filter_FIFO\r
+ * @{\r
+ */\r
+\r
+#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */\r
+#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */\r
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \\r
+ ((FIFO) == CAN_FilterFIFO1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Start_bank_filter_for_slave_CAN \r
+ * @{\r
+ */\r
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Tx \r
+ * @{\r
+ */\r
+\r
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))\r
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))\r
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))\r
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_identifier_type \r
+ * @{\r
+ */\r
+\r
+#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */\r
+#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */\r
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_remote_transmission_request \r
+ * @{\r
+ */\r
+\r
+#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */\r
+#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */\r
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_transmit_constants \r
+ * @{\r
+ */\r
+\r
+#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */\r
+#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */\r
+#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */\r
+#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_receive_FIFO_number_constants \r
+ * @{\r
+ */\r
+\r
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */\r
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */\r
+\r
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_sleep_constants \r
+ * @{\r
+ */\r
+\r
+#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */\r
+#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_wake_up_constants \r
+ * @{\r
+ */\r
+\r
+#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */\r
+#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_flags \r
+ * @{\r
+ */\r
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()\r
+ and CAN_ClearFlag() functions. */\r
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. */\r
+\r
+/* Transmit Flags */\r
+#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */\r
+#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */\r
+#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */\r
+\r
+/* Receive Flags */\r
+#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */\r
+#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */\r
+#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */\r
+#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */\r
+#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */\r
+#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */\r
+\r
+/* Operating Mode Flags */\r
+#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */\r
+#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */\r
+/* Note: When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. \r
+ In this case the SLAK bit can be polled.*/\r
+\r
+/* Error Flags */\r
+#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */\r
+#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */\r
+#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */\r
+#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */\r
+\r
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \\r
+ ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \\r
+ ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \\r
+ ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \\r
+ ((FLAG) == CAN_FLAG_SLAK ))\r
+\r
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \\r
+ ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \\r
+ ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\\r
+ ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \\r
+ ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+ \r
+/** @defgroup CAN_interrupts \r
+ * @{\r
+ */\r
+\r
+\r
+ \r
+#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/\r
+\r
+/* Receive Interrupts */\r
+#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/\r
+#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/\r
+#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/\r
+#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/\r
+#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/\r
+#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/\r
+\r
+/* Operating Mode Interrupts */\r
+#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/\r
+#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/\r
+\r
+/* Error Interrupts */\r
+#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/\r
+#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/\r
+#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/\r
+#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/\r
+#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/\r
+\r
+/* Flags named as Interrupts : kept only for FW compatibility */\r
+#define CAN_IT_RQCP0 CAN_IT_TME\r
+#define CAN_IT_RQCP1 CAN_IT_TME\r
+#define CAN_IT_RQCP2 CAN_IT_TME\r
+\r
+\r
+#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\\r
+ ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\\r
+ ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\\r
+ ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\\r
+ ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\\r
+ ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\\r
+ ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\\r
+ ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void CAN_DeInit(CAN_TypeDef* CANx);\r
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);\r
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); \r
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);\r
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);\r
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);\r
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);\r
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);\r
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);\r
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);\r
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);\r
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);\r
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);\r
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_CAN_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_cec.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the CEC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CEC_H\r
+#define __STM32F10x_CEC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CEC\r
+ * @{\r
+ */\r
+ \r
+\r
+/** @defgroup CEC_Exported_Types\r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief CEC Init structure definition \r
+ */ \r
+typedef struct\r
+{\r
+ uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. \r
+ This parameter can be a value of @ref CEC_BitTiming_Mode */\r
+ uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. \r
+ This parameter can be a value of @ref CEC_BitPeriod_Mode */\r
+}CEC_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup CEC_BitTiming_Mode \r
+ * @{\r
+ */ \r
+#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */\r
+#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */\r
+\r
+#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \\r
+ ((MODE) == CEC_BitTimingErrFreeMode))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_BitPeriod_Mode \r
+ * @{\r
+ */ \r
+#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */\r
+#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */\r
+\r
+#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \\r
+ ((MODE) == CEC_BitPeriodFlexibleMode))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_interrupts_definition \r
+ * @{\r
+ */ \r
+#define CEC_IT_TERR CEC_CSR_TERR\r
+#define CEC_IT_TBTRF CEC_CSR_TBTRF\r
+#define CEC_IT_RERR CEC_CSR_RERR\r
+#define CEC_IT_RBTF CEC_CSR_RBTF\r
+#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \\r
+ ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Own_Addres \r
+ * @{\r
+ */ \r
+#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CEC_Prescaler \r
+ * @{\r
+ */ \r
+#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_flags_definition \r
+ * @{\r
+ */\r
+ \r
+/** \r
+ * @brief ESR register flags \r
+ */ \r
+#define CEC_FLAG_BTE ((uint32_t)0x10010000)\r
+#define CEC_FLAG_BPE ((uint32_t)0x10020000)\r
+#define CEC_FLAG_RBTFE ((uint32_t)0x10040000)\r
+#define CEC_FLAG_SBE ((uint32_t)0x10080000)\r
+#define CEC_FLAG_ACKE ((uint32_t)0x10100000)\r
+#define CEC_FLAG_LINE ((uint32_t)0x10200000)\r
+#define CEC_FLAG_TBTFE ((uint32_t)0x10400000)\r
+\r
+/** \r
+ * @brief CSR register flags \r
+ */ \r
+#define CEC_FLAG_TEOM ((uint32_t)0x00000002) \r
+#define CEC_FLAG_TERR ((uint32_t)0x00000004)\r
+#define CEC_FLAG_TBTRF ((uint32_t)0x00000008)\r
+#define CEC_FLAG_RSOM ((uint32_t)0x00000010)\r
+#define CEC_FLAG_REOM ((uint32_t)0x00000020)\r
+#define CEC_FLAG_RERR ((uint32_t)0x00000040)\r
+#define CEC_FLAG_RBTF ((uint32_t)0x00000080)\r
+\r
+#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00))\r
+ \r
+#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \\r
+ ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \\r
+ ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \\r
+ ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \\r
+ ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \\r
+ ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \\r
+ ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup CEC_Exported_Macros\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CEC_Exported_Functions\r
+ * @{\r
+ */ \r
+void CEC_DeInit(void);\r
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);\r
+void CEC_Cmd(FunctionalState NewState);\r
+void CEC_ITConfig(FunctionalState NewState);\r
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);\r
+void CEC_SetPrescaler(uint16_t CEC_Prescaler);\r
+void CEC_SendDataByte(uint8_t Data);\r
+uint8_t CEC_ReceiveDataByte(void);\r
+void CEC_StartOfMessage(void);\r
+void CEC_EndOfMessageCmd(FunctionalState NewState);\r
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG);\r
+void CEC_ClearFlag(uint32_t CEC_FLAG);\r
+ITStatus CEC_GetITStatus(uint8_t CEC_IT);\r
+void CEC_ClearITPendingBit(uint16_t CEC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_CEC_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_crc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the CRC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_CRC_H\r
+#define __STM32F10x_CRC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup CRC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void CRC_ResetDR(void);\r
+uint32_t CRC_CalcCRC(uint32_t Data);\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);\r
+uint32_t CRC_GetCRC(void);\r
+void CRC_SetIDRegister(uint8_t IDValue);\r
+uint8_t CRC_GetIDRegister(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_CRC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dac.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the DAC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DAC_H\r
+#define __STM32F10x_DAC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DAC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief DAC Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.\r
+ This parameter can be a value of @ref DAC_trigger_selection */\r
+\r
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves\r
+ are generated, or whether no wave is generated.\r
+ This parameter can be a value of @ref DAC_wave_generation */\r
+\r
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or\r
+ the maximum amplitude triangle generation for the DAC channel. \r
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */\r
+\r
+ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.\r
+ This parameter can be a value of @ref DAC_output_buffer */\r
+}DAC_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC_trigger_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \r
+ has been loaded, and not by external trigger */\r
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
+ only in High-density devices*/\r
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel\r
+ only in Connectivity line, Medium-density and Low-density Value Line devices */\r
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel \r
+ only in Medium-density and Low-density Value Line devices*/\r
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */\r
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */\r
+\r
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \\r
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T5_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \\r
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \\r
+ ((TRIGGER) == DAC_Trigger_Software))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)\r
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)\r
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \\r
+ ((WAVE) == DAC_WaveGeneration_Noise) || \\r
+ ((WAVE) == DAC_WaveGeneration_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_lfsrunmask_triangleamplitude\r
+ * @{\r
+ */\r
+\r
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */\r
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */\r
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */\r
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */\r
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */\r
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */\r
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */\r
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */\r
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */\r
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */\r
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */\r
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */\r
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */\r
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */\r
+\r
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \\r
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_3) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_7) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_15) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_31) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_63) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_127) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_255) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_511) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \\r
+ ((VALUE) == DAC_TriangleAmplitude_4095))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_output_buffer \r
+ * @{\r
+ */\r
+\r
+#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)\r
+#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)\r
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \\r
+ ((STATE) == DAC_OutputBuffer_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Channel_selection \r
+ * @{\r
+ */\r
+\r
+#define DAC_Channel_1 ((uint32_t)0x00000000)\r
+#define DAC_Channel_2 ((uint32_t)0x00000010)\r
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \\r
+ ((CHANNEL) == DAC_Channel_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data_alignement \r
+ * @{\r
+ */\r
+\r
+#define DAC_Align_12b_R ((uint32_t)0x00000000)\r
+#define DAC_Align_12b_L ((uint32_t)0x00000004)\r
+#define DAC_Align_8b_R ((uint32_t)0x00000008)\r
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \\r
+ ((ALIGN) == DAC_Align_12b_L) || \\r
+ ((ALIGN) == DAC_Align_8b_R))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_wave_generation \r
+ * @{\r
+ */\r
+\r
+#define DAC_Wave_Noise ((uint32_t)0x00000040)\r
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)\r
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \\r
+ ((WAVE) == DAC_Wave_Triangle))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_data \r
+ * @{\r
+ */\r
+\r
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) \r
+/**\r
+ * @}\r
+ */\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/** @defgroup DAC_interrupts_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DAC_flags_definition \r
+ * @{\r
+ */ \r
+ \r
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) \r
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void DAC_DeInit(void);\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);\r
+#endif\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) \r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_DAC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dbgmcu.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the DBGMCU \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DBGMCU_H\r
+#define __STM32F10x_DBGMCU_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DBGMCU\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)\r
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)\r
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000)\r
+#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000)\r
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000)\r
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000)\r
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000)\r
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000)\r
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000)\r
+#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)\r
+#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000)\r
+#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000)\r
+#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000)\r
+#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000)\r
+#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000)\r
+#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000)\r
+#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000)\r
+#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000)\r
+#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000)\r
+ \r
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup DBGMCU_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+uint32_t DBGMCU_GetREVID(void);\r
+uint32_t DBGMCU_GetDEVID(void);\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_DBGMCU_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dma.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the DMA firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_DMA_H\r
+#define __STM32F10x_DMA_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup DMA\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief DMA Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */\r
+\r
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.\r
+ This parameter can be a value of @ref DMA_data_transfer_direction */\r
+\r
+ uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. \r
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize\r
+ or DMA_MemoryDataSize members depending in the transfer direction. */\r
+\r
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */\r
+\r
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.\r
+ This parameter can be a value of @ref DMA_memory_incremented_mode */\r
+\r
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.\r
+ This parameter can be a value of @ref DMA_peripheral_data_size */\r
+\r
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.\r
+ This parameter can be a value of @ref DMA_memory_data_size */\r
+\r
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_circular_normal_mode.\r
+ @note: The circular buffer mode cannot be used if the memory-to-memory\r
+ data transfer is configured on the selected Channel */\r
+\r
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.\r
+ This parameter can be a value of @ref DMA_priority_level */\r
+\r
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.\r
+ This parameter can be a value of @ref DMA_memory_to_memory */\r
+}DMA_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \\r
+ ((PERIPH) == DMA1_Channel2) || \\r
+ ((PERIPH) == DMA1_Channel3) || \\r
+ ((PERIPH) == DMA1_Channel4) || \\r
+ ((PERIPH) == DMA1_Channel5) || \\r
+ ((PERIPH) == DMA1_Channel6) || \\r
+ ((PERIPH) == DMA1_Channel7) || \\r
+ ((PERIPH) == DMA2_Channel1) || \\r
+ ((PERIPH) == DMA2_Channel2) || \\r
+ ((PERIPH) == DMA2_Channel3) || \\r
+ ((PERIPH) == DMA2_Channel4) || \\r
+ ((PERIPH) == DMA2_Channel5))\r
+\r
+/** @defgroup DMA_data_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)\r
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)\r
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \\r
+ ((DIR) == DMA_DIR_PeripheralSRC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)\r
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \\r
+ ((STATE) == DMA_PeripheralInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_incremented_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)\r
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \\r
+ ((STATE) == DMA_MemoryInc_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_peripheral_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)\r
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)\r
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_PeripheralDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_data_size \r
+ * @{\r
+ */\r
+\r
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)\r
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)\r
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)\r
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \\r
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \\r
+ ((SIZE) == DMA_MemoryDataSize_Word))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_circular_normal_mode \r
+ * @{\r
+ */\r
+\r
+#define DMA_Mode_Circular ((uint32_t)0x00000020)\r
+#define DMA_Mode_Normal ((uint32_t)0x00000000)\r
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_priority_level \r
+ * @{\r
+ */\r
+\r
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)\r
+#define DMA_Priority_High ((uint32_t)0x00002000)\r
+#define DMA_Priority_Medium ((uint32_t)0x00001000)\r
+#define DMA_Priority_Low ((uint32_t)0x00000000)\r
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \\r
+ ((PRIORITY) == DMA_Priority_High) || \\r
+ ((PRIORITY) == DMA_Priority_Medium) || \\r
+ ((PRIORITY) == DMA_Priority_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_memory_to_memory \r
+ * @{\r
+ */\r
+\r
+#define DMA_M2M_Enable ((uint32_t)0x00004000)\r
+#define DMA_M2M_Disable ((uint32_t)0x00000000)\r
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define DMA_IT_TC ((uint32_t)0x00000002)\r
+#define DMA_IT_HT ((uint32_t)0x00000004)\r
+#define DMA_IT_TE ((uint32_t)0x00000008)\r
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))\r
+\r
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)\r
+\r
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)\r
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)\r
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)\r
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)\r
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)\r
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)\r
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)\r
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)\r
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)\r
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)\r
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)\r
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)\r
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)\r
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)\r
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)\r
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)\r
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)\r
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)\r
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)\r
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))\r
+\r
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \\r
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \\r
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \\r
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \\r
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \\r
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \\r
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \\r
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \\r
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \\r
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \\r
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \\r
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \\r
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \\r
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \\r
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \\r
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \\r
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \\r
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \\r
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \\r
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \\r
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \\r
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \\r
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \\r
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_flags_definition \r
+ * @{\r
+ */\r
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)\r
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)\r
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)\r
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)\r
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)\r
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)\r
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)\r
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)\r
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)\r
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)\r
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)\r
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)\r
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)\r
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)\r
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)\r
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)\r
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)\r
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)\r
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)\r
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)\r
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)\r
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)\r
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)\r
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)\r
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)\r
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)\r
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)\r
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)\r
+\r
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)\r
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)\r
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)\r
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)\r
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)\r
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)\r
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)\r
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)\r
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)\r
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)\r
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)\r
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)\r
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)\r
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)\r
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)\r
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)\r
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)\r
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)\r
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)\r
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)\r
+\r
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))\r
+\r
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \\r
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \\r
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \\r
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \\r
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \\r
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \\r
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \\r
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \\r
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \\r
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \\r
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \\r
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \\r
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \\r
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \\r
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \\r
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \\r
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \\r
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \\r
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \\r
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \\r
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \\r
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \\r
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \\r
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Buffer_Size \r
+ * @{\r
+ */\r
+\r
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); \r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);\r
+void DMA_ClearFlag(uint32_t DMA_FLAG);\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT);\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_DMA_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_exti.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the EXTI firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_EXTI_H\r
+#define __STM32F10x_EXTI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup EXTI\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief EXTI mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Mode_Interrupt = 0x00,\r
+ EXTI_Mode_Event = 0x04\r
+}EXTIMode_TypeDef;\r
+\r
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))\r
+\r
+/** \r
+ * @brief EXTI Trigger enumeration \r
+ */\r
+\r
+typedef enum\r
+{\r
+ EXTI_Trigger_Rising = 0x08,\r
+ EXTI_Trigger_Falling = 0x0C, \r
+ EXTI_Trigger_Rising_Falling = 0x10\r
+}EXTITrigger_TypeDef;\r
+\r
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \\r
+ ((TRIGGER) == EXTI_Trigger_Falling) || \\r
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))\r
+/** \r
+ * @brief EXTI Init Structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.\r
+ This parameter can be any combination of @ref EXTI_Lines */\r
+ \r
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.\r
+ This parameter can be a value of @ref EXTIMode_TypeDef */\r
+\r
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.\r
+ This parameter can be set either to ENABLE or DISABLE */ \r
+}EXTI_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Lines \r
+ * @{\r
+ */\r
+\r
+#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */\r
+#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */\r
+#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */\r
+#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */\r
+#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */\r
+#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */\r
+#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */\r
+#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */\r
+#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */\r
+#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */\r
+#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */\r
+#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */\r
+#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */\r
+#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */\r
+#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */\r
+#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */\r
+#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */\r
+#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */\r
+#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS\r
+ Wakeup from suspend event */ \r
+#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */\r
+ \r
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00))\r
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \\r
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \\r
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \\r
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \\r
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \\r
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \\r
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \\r
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \\r
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \\r
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19))\r
+\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void EXTI_DeInit(void);\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearFlag(uint32_t EXTI_Line);\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_EXTI_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_flash.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the FLASH \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FLASH_H\r
+#define __STM32F10x_FLASH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FLASH\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief FLASH Status \r
+ */\r
+\r
+typedef enum\r
+{ \r
+ FLASH_BUSY = 1,\r
+ FLASH_ERROR_PG,\r
+ FLASH_ERROR_WRP,\r
+ FLASH_COMPLETE,\r
+ FLASH_TIMEOUT\r
+}FLASH_Status;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup Flash_Latency \r
+ * @{\r
+ */\r
+\r
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */\r
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */\r
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */\r
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \\r
+ ((LATENCY) == FLASH_Latency_1) || \\r
+ ((LATENCY) == FLASH_Latency_2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Half_Cycle_Enable_Disable \r
+ * @{\r
+ */\r
+\r
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */\r
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */\r
+#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \\r
+ ((STATE) == FLASH_HalfCycleAccess_Disable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Prefetch_Buffer_Enable_Disable \r
+ * @{\r
+ */\r
+\r
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */\r
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */\r
+#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \\r
+ ((STATE) == FLASH_PrefetchBuffer_Disable)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_Write_Protection \r
+ * @{\r
+ */\r
+\r
+/* Values to be used with STM32 Low and Medium density devices */\r
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */\r
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */\r
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */\r
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */\r
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */\r
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */\r
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */\r
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */\r
+\r
+/* Values to be used with STM32 Medium-density devices */\r
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */\r
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */\r
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */\r
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */\r
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */\r
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */\r
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */\r
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */\r
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */\r
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */\r
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */\r
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */\r
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */\r
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */\r
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */\r
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */\r
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */\r
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */\r
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */\r
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */\r
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */\r
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */\r
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */\r
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */\r
+\r
+/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */\r
+#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 0 to 1 */\r
+#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 2 to 3 */\r
+#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 4 to 5 */\r
+#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 6 to 7 */\r
+#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 8 to 9 */\r
+#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 10 to 11 */\r
+#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 12 to 13 */\r
+#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 14 to 15 */\r
+#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 16 to 17 */\r
+#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 18 to 19 */\r
+#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 20 to 21 */\r
+#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 22 to 23 */\r
+#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 24 to 25 */\r
+#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 26 to 27 */\r
+#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 28 to 29 */\r
+#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 30 to 31 */\r
+#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 32 to 33 */\r
+#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 34 to 35 */\r
+#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 36 to 37 */\r
+#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 38 to 39 */\r
+#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 40 to 41 */\r
+#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 42 to 43 */\r
+#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 44 to 45 */\r
+#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 46 to 47 */\r
+#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 48 to 49 */\r
+#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 50 to 51 */\r
+#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 52 to 53 */\r
+#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 54 to 55 */\r
+#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 56 to 57 */\r
+#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 58 to 59 */\r
+#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices:\r
+ Write protection of page 60 to 61 */\r
+#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */\r
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */\r
+#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */\r
+\r
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */\r
+\r
+#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000))\r
+\r
+#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF))\r
+\r
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_IWatchdog \r
+ * @{\r
+ */\r
+\r
+#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */\r
+#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */\r
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STOP \r
+ * @{\r
+ */\r
+\r
+#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */\r
+#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */\r
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Option_Bytes_nRST_STDBY \r
+ * @{\r
+ */\r
+\r
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */\r
+#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */\r
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup FLASH_Boot\r
+ * @{\r
+ */\r
+#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank1(Default) */\r
+#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position\r
+ and this parameter is selected the device will boot from Bank 2 or Bank 1,\r
+ depending on the activation of the bank */\r
+#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2))\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+/** @defgroup FLASH_Interrupts \r
+ * @{\r
+ */\r
+#ifdef STM32F10X_XL\r
+#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */\r
+#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */\r
+\r
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
+\r
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */\r
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+#else\r
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */\r
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */\r
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */\r
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */\r
+\r
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Flags \r
+ * @{\r
+ */\r
+#ifdef STM32F10X_XL\r
+#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */\r
+#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */\r
+#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */\r
+#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */\r
+\r
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
+\r
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_OPTERR)|| \\r
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR))\r
+#else\r
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */\r
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */\r
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */\r
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */\r
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */\r
+\r
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/\r
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */\r
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */\r
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */\r
+ \r
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000))\r
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \\r
+ ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \\r
+ ((FLAG) == FLASH_FLAG_OPTERR))\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+/*------------ Functions used for all STM32F10x devices -----*/\r
+void FLASH_SetLatency(uint32_t FLASH_Latency);\r
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);\r
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);\r
+void FLASH_Unlock(void);\r
+void FLASH_Lock(void);\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);\r
+FLASH_Status FLASH_EraseAllPages(void);\r
+FLASH_Status FLASH_EraseOptionBytes(void);\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);\r
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);\r
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);\r
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);\r
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);\r
+uint32_t FLASH_GetUserOptionByte(void);\r
+uint32_t FLASH_GetWriteProtectionOptionByte(void);\r
+FlagStatus FLASH_GetReadOutProtectionStatus(void);\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void);\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);\r
+FLASH_Status FLASH_GetStatus(void);\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);\r
+\r
+/*------------ New function used for all STM32F10x devices -----*/\r
+void FLASH_UnlockBank1(void);\r
+void FLASH_LockBank1(void);\r
+FLASH_Status FLASH_EraseAllBank1Pages(void);\r
+FLASH_Status FLASH_GetBank1Status(void);\r
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);\r
+\r
+#ifdef STM32F10X_XL\r
+/*---- New Functions used only with STM32F10x_XL density devices -----*/\r
+void FLASH_UnlockBank2(void);\r
+void FLASH_LockBank2(void);\r
+FLASH_Status FLASH_EraseAllBank2Pages(void);\r
+FLASH_Status FLASH_GetBank2Status(void);\r
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout);\r
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT);\r
+#endif\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_FLASH_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_fsmc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the FSMC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_FSMC_H\r
+#define __STM32F10x_FSMC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup FSMC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief Timing parameters For NOR/SRAM Banks \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address setup time. \r
+ This parameter can be a value between 0 and 0xF.\r
+ @note: It is not used with synchronous NOR Flash memories. */\r
+\r
+ uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the address hold time.\r
+ This parameter can be a value between 0 and 0xF. \r
+ @note: It is not used with synchronous NOR Flash memories.*/\r
+\r
+ uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the data setup time.\r
+ This parameter can be a value between 0 and 0xFF.\r
+ @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure\r
+ the duration of the bus turnaround.\r
+ This parameter can be a value between 0 and 0xF.\r
+ @note: It is only used for multiplexed NOR Flash memories. */\r
+\r
+ uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.\r
+ This parameter can be a value between 1 and 0xF.\r
+ @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */\r
+\r
+ uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue\r
+ to the memory before getting the first data.\r
+ The value of this parameter depends on the memory type as shown below:\r
+ - It must be set to 0 in case of a CRAM\r
+ - It is don\92t care in asynchronous NOR, SRAM or ROM accesses\r
+ - It may assume a value between 0 and 0xF in NOR Flash memories\r
+ with synchronous burst mode enable */\r
+\r
+ uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. \r
+ This parameter can be a value of @ref FSMC_Access_Mode */\r
+}FSMC_NORSRAMTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NOR/SRAM Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.\r
+ This parameter can be a value of @ref FSMC_NORSRAM_Bank */\r
+\r
+ uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are\r
+ multiplexed on the databus or not. \r
+ This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */\r
+\r
+ uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to\r
+ the corresponding memory bank.\r
+ This parameter can be a value of @ref FSMC_Memory_Type */\r
+\r
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be a value of @ref FSMC_Data_Width */\r
+\r
+ uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,\r
+ valid only with synchronous burst Flash memories.\r
+ This parameter can be a value of @ref FSMC_Burst_Access_Mode */\r
+ \r
+ uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,\r
+ valid only with asynchronous Flash memories.\r
+ This parameter can be a value of @ref FSMC_AsynchronousWait */\r
+\r
+ uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing\r
+ the Flash memory in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */\r
+\r
+ uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash\r
+ memory, valid only when accessing Flash memories in burst mode.\r
+ This parameter can be a value of @ref FSMC_Wrap_Mode */\r
+\r
+ uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one\r
+ clock cycle before the wait state or during the wait state,\r
+ valid only when accessing memories in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Timing */\r
+\r
+ uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. \r
+ This parameter can be a value of @ref FSMC_Write_Operation */\r
+\r
+ uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait\r
+ signal, valid for Flash memory access in burst mode. \r
+ This parameter can be a value of @ref FSMC_Wait_Signal */\r
+\r
+ uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.\r
+ This parameter can be a value of @ref FSMC_Extended_Mode */\r
+\r
+ uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.\r
+ This parameter can be a value of @ref FSMC_Write_Burst */ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ \r
+\r
+ FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ \r
+}FSMC_NORSRAMInitTypeDef;\r
+\r
+/** \r
+ * @brief Timing parameters For FSMC NAND and PCCARD Banks\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before\r
+ the command assertion for NAND-Flash read or write access\r
+ to common/Attribute or I/O memory space (depending on\r
+ the memory space timing to be configured).\r
+ This parameter can be a value between 0 and 0xFF.*/\r
+\r
+ uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the\r
+ command for NAND-Flash read or write access to\r
+ common/Attribute or I/O memory space (depending on the\r
+ memory space timing to be configured). \r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address\r
+ (and data for write access) after the command deassertion\r
+ for NAND-Flash read or write access to common/Attribute\r
+ or I/O memory space (depending on the memory space timing\r
+ to be configured).\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the\r
+ databus is kept in HiZ after the start of a NAND-Flash\r
+ write access to common/Attribute or I/O memory space (depending\r
+ on the memory space timing to be configured).\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+}FSMC_NAND_PCCARDTimingInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC NAND Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.\r
+ This parameter can be a value of @ref FSMC_NAND_Bank */\r
+\r
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.\r
+ This parameter can be any value of @ref FSMC_Wait_feature */\r
+\r
+ uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.\r
+ This parameter can be any value of @ref FSMC_Data_Width */\r
+\r
+ uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.\r
+ This parameter can be any value of @ref FSMC_ECC */\r
+\r
+ uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.\r
+ This parameter can be any value of @ref FSMC_ECC_Page_Size */\r
+\r
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between CLE low and RE low.\r
+ This parameter can be a value between 0 and 0xFF. */\r
+\r
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between ALE low and RE low.\r
+ This parameter can be a number between 0x0 and 0xFF */ \r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ \r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */\r
+}FSMC_NANDInitTypeDef;\r
+\r
+/** \r
+ * @brief FSMC PCCARD Init structure definition\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.\r
+ This parameter can be any value of @ref FSMC_Wait_feature */\r
+\r
+ uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between CLE low and RE low.\r
+ This parameter can be a value between 0 and 0xFF. */\r
+\r
+ uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the\r
+ delay between ALE low and RE low.\r
+ This parameter can be a number between 0x0 and 0xFF */ \r
+\r
+ \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */\r
+\r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ \r
+ \r
+ FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ \r
+}FSMC_PCCARDInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_NORSRAM_Bank \r
+ * @{\r
+ */\r
+#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)\r
+#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)\r
+#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)\r
+#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_NAND_Bank \r
+ * @{\r
+ */ \r
+#define FSMC_Bank2_NAND ((uint32_t)0x00000010)\r
+#define FSMC_Bank3_NAND ((uint32_t)0x00000100)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_PCCARD_Bank \r
+ * @{\r
+ */ \r
+#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM2) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM3) || \\r
+ ((BANK) == FSMC_Bank1_NORSRAM4))\r
+\r
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND))\r
+\r
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+\r
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \\r
+ ((BANK) == FSMC_Bank3_NAND) || \\r
+ ((BANK) == FSMC_Bank4_PCCARD))\r
+\r
+/** @defgroup NOR_SRAM_Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)\r
+#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \\r
+ ((MUX) == FSMC_DataAddressMux_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Memory_Type \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)\r
+#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)\r
+#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)\r
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \\r
+ ((MEMORY) == FSMC_MemoryType_PSRAM)|| \\r
+ ((MEMORY) == FSMC_MemoryType_NOR))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Width \r
+ * @{\r
+ */\r
+\r
+#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)\r
+#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)\r
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \\r
+ ((WIDTH) == FSMC_MemoryDataWidth_16b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Burst_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) \r
+#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)\r
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \\r
+ ((STATE) == FSMC_BurstAccessMode_Enable))\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_AsynchronousWait \r
+ * @{\r
+ */\r
+#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)\r
+#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)\r
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \\r
+ ((STATE) == FSMC_AsynchronousWait_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup FSMC_Wait_Signal_Polarity \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)\r
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \\r
+ ((POLARITY) == FSMC_WaitSignalPolarity_High)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wrap_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) \r
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \\r
+ ((MODE) == FSMC_WrapMode_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Timing \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) \r
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \\r
+ ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Operation \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)\r
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \\r
+ ((OPERATION) == FSMC_WriteOperation_Enable))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Signal \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) \r
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \\r
+ ((SIGNAL) == FSMC_WaitSignal_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Extended_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)\r
+\r
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \\r
+ ((MODE) == FSMC_ExtendedMode_Enable)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Write_Burst \r
+ * @{\r
+ */\r
+\r
+#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)\r
+#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) \r
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \\r
+ ((BURST) == FSMC_WriteBurst_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Address_Hold_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Bus_Turn_around_Duration \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_CLK_Division \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Data_Latency \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Access_Mode \r
+ * @{\r
+ */\r
+\r
+#define FSMC_AccessMode_A ((uint32_t)0x00000000)\r
+#define FSMC_AccessMode_B ((uint32_t)0x10000000) \r
+#define FSMC_AccessMode_C ((uint32_t)0x20000000)\r
+#define FSMC_AccessMode_D ((uint32_t)0x30000000)\r
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \\r
+ ((MODE) == FSMC_AccessMode_B) || \\r
+ ((MODE) == FSMC_AccessMode_C) || \\r
+ ((MODE) == FSMC_AccessMode_D)) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @defgroup NAND_PCCARD_Controller \r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_feature \r
+ * @{\r
+ */\r
+\r
+#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)\r
+#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)\r
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \\r
+ ((FEATURE) == FSMC_Waitfeature_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup FSMC_ECC \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ECC_Disable ((uint32_t)0x00000000)\r
+#define FSMC_ECC_Enable ((uint32_t)0x00000040)\r
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \\r
+ ((STATE) == FSMC_ECC_Enable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_ECC_Page_Size \r
+ * @{\r
+ */\r
+\r
+#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)\r
+#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)\r
+#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)\r
+#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)\r
+#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)\r
+#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)\r
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_512Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \\r
+ ((SIZE) == FSMC_ECCPageSize_8192Bytes))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TCLR_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_TAR_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Wait_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Hold_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_HiZ_Setup_Time \r
+ * @{\r
+ */\r
+\r
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define FSMC_IT_RisingEdge ((uint32_t)0x00000008)\r
+#define FSMC_IT_Level ((uint32_t)0x00000010)\r
+#define FSMC_IT_FallingEdge ((uint32_t)0x00000020)\r
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))\r
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \\r
+ ((IT) == FSMC_IT_Level) || \\r
+ ((IT) == FSMC_IT_FallingEdge)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Flags \r
+ * @{\r
+ */\r
+\r
+#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001)\r
+#define FSMC_FLAG_Level ((uint32_t)0x00000002)\r
+#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004)\r
+#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)\r
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_Level) || \\r
+ ((FLAG) == FSMC_FLAG_FallingEdge) || \\r
+ ((FLAG) == FSMC_FLAG_FEMPT))\r
+\r
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);\r
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);\r
+void FSMC_PCCARDDeInit(void);\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+void FSMC_PCCARDCmd(FunctionalState NewState);\r
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);\r
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);\r
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);\r
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);\r
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_FSMC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_gpio.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the GPIO \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_GPIO_H\r
+#define __STM32F10x_GPIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup GPIO\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Types\r
+ * @{\r
+ */\r
+\r
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \\r
+ ((PERIPH) == GPIOB) || \\r
+ ((PERIPH) == GPIOC) || \\r
+ ((PERIPH) == GPIOD) || \\r
+ ((PERIPH) == GPIOE) || \\r
+ ((PERIPH) == GPIOF) || \\r
+ ((PERIPH) == GPIOG))\r
+ \r
+/** \r
+ * @brief Output Maximum frequency selection \r
+ */\r
+\r
+typedef enum\r
+{ \r
+ GPIO_Speed_10MHz = 1,\r
+ GPIO_Speed_2MHz, \r
+ GPIO_Speed_50MHz\r
+}GPIOSpeed_TypeDef;\r
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \\r
+ ((SPEED) == GPIO_Speed_50MHz))\r
+\r
+/** \r
+ * @brief Configuration Mode enumeration \r
+ */\r
+\r
+typedef enum\r
+{ GPIO_Mode_AIN = 0x0,\r
+ GPIO_Mode_IN_FLOATING = 0x04,\r
+ GPIO_Mode_IPD = 0x28,\r
+ GPIO_Mode_IPU = 0x48,\r
+ GPIO_Mode_Out_OD = 0x14,\r
+ GPIO_Mode_Out_PP = 0x10,\r
+ GPIO_Mode_AF_OD = 0x1C,\r
+ GPIO_Mode_AF_PP = 0x18\r
+}GPIOMode_TypeDef;\r
+\r
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \\r
+ ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \\r
+ ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \\r
+ ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP))\r
+\r
+/** \r
+ * @brief GPIO Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.\r
+ This parameter can be any value of @ref GPIO_pins_define */\r
+\r
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.\r
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */\r
+\r
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.\r
+ This parameter can be a value of @ref GPIOMode_TypeDef */\r
+}GPIO_InitTypeDef;\r
+\r
+\r
+/** \r
+ * @brief Bit_SET and Bit_RESET enumeration \r
+ */\r
+\r
+typedef enum\r
+{ Bit_RESET = 0,\r
+ Bit_SET\r
+}BitAction;\r
+\r
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO_pins_define \r
+ * @{\r
+ */\r
+\r
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */\r
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */\r
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */\r
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */\r
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */\r
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */\r
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */\r
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */\r
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */\r
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */\r
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */\r
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */\r
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */\r
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */\r
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */\r
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */\r
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */\r
+\r
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))\r
+\r
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \\r
+ ((PIN) == GPIO_Pin_1) || \\r
+ ((PIN) == GPIO_Pin_2) || \\r
+ ((PIN) == GPIO_Pin_3) || \\r
+ ((PIN) == GPIO_Pin_4) || \\r
+ ((PIN) == GPIO_Pin_5) || \\r
+ ((PIN) == GPIO_Pin_6) || \\r
+ ((PIN) == GPIO_Pin_7) || \\r
+ ((PIN) == GPIO_Pin_8) || \\r
+ ((PIN) == GPIO_Pin_9) || \\r
+ ((PIN) == GPIO_Pin_10) || \\r
+ ((PIN) == GPIO_Pin_11) || \\r
+ ((PIN) == GPIO_Pin_12) || \\r
+ ((PIN) == GPIO_Pin_13) || \\r
+ ((PIN) == GPIO_Pin_14) || \\r
+ ((PIN) == GPIO_Pin_15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Remap_define \r
+ * @{\r
+ */\r
+\r
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */\r
+#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */\r
+#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */\r
+#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */\r
+#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */\r
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */\r
+#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */\r
+#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */\r
+#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */\r
+#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */\r
+#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */\r
+#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */\r
+#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */\r
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */\r
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */\r
+#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */\r
+#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */\r
+#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */\r
+#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */\r
+#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */\r
+#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */\r
+#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */\r
+#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */\r
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected\r
+ to TIM2 Internal Trigger 1 for calibration\r
+ (only for Connectivity line devices) */\r
+#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */\r
+\r
+#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */\r
+#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */\r
+\r
+#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */\r
+#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */\r
+#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */\r
+#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for High density Value line and XL-density devices) */\r
+#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for High density Value line and XL-density devices) */\r
+#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices) */\r
+\r
+#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /*!< TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */\r
+#define GPIO_Remap_TIM12 ((uint32_t)0x80001000) /*!< TIM12 Alternate Function mapping (only for High density Value line devices) */\r
+#define GPIO_Remap_MISC ((uint32_t)0x80002000) /*!< Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \r
+ only for High density Value line devices) */ \r
+\r
+#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \\r
+ ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \\r
+ ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \\r
+ ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \\r
+ ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \\r
+ ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \\r
+ ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \\r
+ ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \\r
+ ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \\r
+ ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \\r
+ ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \\r
+ ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \\r
+ ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \\r
+ ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \\r
+ ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \\r
+ ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \\r
+ ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \\r
+ ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \\r
+ ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \\r
+ ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \\r
+ ((REMAP) == GPIO_Remap_FSMC_NADV) || ((REMAP) == GPIO_Remap_TIM67_DAC_DMA) || \\r
+ ((REMAP) == GPIO_Remap_TIM12) || ((REMAP) == GPIO_Remap_MISC))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup GPIO_Port_Sources \r
+ * @{\r
+ */\r
+\r
+#define GPIO_PortSourceGPIOA ((uint8_t)0x00)\r
+#define GPIO_PortSourceGPIOB ((uint8_t)0x01)\r
+#define GPIO_PortSourceGPIOC ((uint8_t)0x02)\r
+#define GPIO_PortSourceGPIOD ((uint8_t)0x03)\r
+#define GPIO_PortSourceGPIOE ((uint8_t)0x04)\r
+#define GPIO_PortSourceGPIOF ((uint8_t)0x05)\r
+#define GPIO_PortSourceGPIOG ((uint8_t)0x06)\r
+#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE))\r
+\r
+#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \\r
+ ((PORTSOURCE) == GPIO_PortSourceGPIOG))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Pin_sources \r
+ * @{\r
+ */\r
+\r
+#define GPIO_PinSource0 ((uint8_t)0x00)\r
+#define GPIO_PinSource1 ((uint8_t)0x01)\r
+#define GPIO_PinSource2 ((uint8_t)0x02)\r
+#define GPIO_PinSource3 ((uint8_t)0x03)\r
+#define GPIO_PinSource4 ((uint8_t)0x04)\r
+#define GPIO_PinSource5 ((uint8_t)0x05)\r
+#define GPIO_PinSource6 ((uint8_t)0x06)\r
+#define GPIO_PinSource7 ((uint8_t)0x07)\r
+#define GPIO_PinSource8 ((uint8_t)0x08)\r
+#define GPIO_PinSource9 ((uint8_t)0x09)\r
+#define GPIO_PinSource10 ((uint8_t)0x0A)\r
+#define GPIO_PinSource11 ((uint8_t)0x0B)\r
+#define GPIO_PinSource12 ((uint8_t)0x0C)\r
+#define GPIO_PinSource13 ((uint8_t)0x0D)\r
+#define GPIO_PinSource14 ((uint8_t)0x0E)\r
+#define GPIO_PinSource15 ((uint8_t)0x0F)\r
+\r
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \\r
+ ((PINSOURCE) == GPIO_PinSource1) || \\r
+ ((PINSOURCE) == GPIO_PinSource2) || \\r
+ ((PINSOURCE) == GPIO_PinSource3) || \\r
+ ((PINSOURCE) == GPIO_PinSource4) || \\r
+ ((PINSOURCE) == GPIO_PinSource5) || \\r
+ ((PINSOURCE) == GPIO_PinSource6) || \\r
+ ((PINSOURCE) == GPIO_PinSource7) || \\r
+ ((PINSOURCE) == GPIO_PinSource8) || \\r
+ ((PINSOURCE) == GPIO_PinSource9) || \\r
+ ((PINSOURCE) == GPIO_PinSource10) || \\r
+ ((PINSOURCE) == GPIO_PinSource11) || \\r
+ ((PINSOURCE) == GPIO_PinSource12) || \\r
+ ((PINSOURCE) == GPIO_PinSource13) || \\r
+ ((PINSOURCE) == GPIO_PinSource14) || \\r
+ ((PINSOURCE) == GPIO_PinSource15))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Ethernet_Media_Interface \r
+ * @{\r
+ */ \r
+#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) \r
+#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) \r
+\r
+#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \\r
+ ((INTERFACE) == GPIO_ETH_MediaInterface_RMII))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);\r
+void GPIO_AFIODeInit(void);\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\r
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);\r
+void GPIO_EventOutputCmd(FunctionalState NewState);\r
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);\r
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);\r
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_GPIO_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_i2c.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the I2C firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_I2C_H\r
+#define __STM32F10x_I2C_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup I2C\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief I2C Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.\r
+ This parameter must be set to a value lower than 400kHz */\r
+\r
+ uint16_t I2C_Mode; /*!< Specifies the I2C mode.\r
+ This parameter can be a value of @ref I2C_mode */\r
+\r
+ uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.\r
+ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\r
+\r
+ uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.\r
+ This parameter can be a 7-bit or 10-bit address. */\r
+\r
+ uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.\r
+ This parameter can be a value of @ref I2C_acknowledgement */\r
+\r
+ uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.\r
+ This parameter can be a value of @ref I2C_acknowledged_address */\r
+}I2C_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup I2C_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \\r
+ ((PERIPH) == I2C2))\r
+/** @defgroup I2C_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_Mode_I2C ((uint16_t)0x0000)\r
+#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) \r
+#define I2C_Mode_SMBusHost ((uint16_t)0x000A)\r
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \\r
+ ((MODE) == I2C_Mode_SMBusDevice) || \\r
+ ((MODE) == I2C_Mode_SMBusHost))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_duty_cycle_in_fast_mode \r
+ * @{\r
+ */\r
+\r
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */\r
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */\r
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \\r
+ ((CYCLE) == I2C_DutyCycle_2))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_acknowledgement\r
+ * @{\r
+ */\r
+\r
+#define I2C_Ack_Enable ((uint16_t)0x0400)\r
+#define I2C_Ack_Disable ((uint16_t)0x0000)\r
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \\r
+ ((STATE) == I2C_Ack_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_transfer_direction \r
+ * @{\r
+ */\r
+\r
+#define I2C_Direction_Transmitter ((uint8_t)0x00)\r
+#define I2C_Direction_Receiver ((uint8_t)0x01)\r
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \\r
+ ((DIRECTION) == I2C_Direction_Receiver))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_acknowledged_address \r
+ * @{\r
+ */\r
+\r
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)\r
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)\r
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \\r
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_registers \r
+ * @{\r
+ */\r
+\r
+#define I2C_Register_CR1 ((uint8_t)0x00)\r
+#define I2C_Register_CR2 ((uint8_t)0x04)\r
+#define I2C_Register_OAR1 ((uint8_t)0x08)\r
+#define I2C_Register_OAR2 ((uint8_t)0x0C)\r
+#define I2C_Register_DR ((uint8_t)0x10)\r
+#define I2C_Register_SR1 ((uint8_t)0x14)\r
+#define I2C_Register_SR2 ((uint8_t)0x18)\r
+#define I2C_Register_CCR ((uint8_t)0x1C)\r
+#define I2C_Register_TRISE ((uint8_t)0x20)\r
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \\r
+ ((REGISTER) == I2C_Register_CR2) || \\r
+ ((REGISTER) == I2C_Register_OAR1) || \\r
+ ((REGISTER) == I2C_Register_OAR2) || \\r
+ ((REGISTER) == I2C_Register_DR) || \\r
+ ((REGISTER) == I2C_Register_SR1) || \\r
+ ((REGISTER) == I2C_Register_SR2) || \\r
+ ((REGISTER) == I2C_Register_CCR) || \\r
+ ((REGISTER) == I2C_Register_TRISE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_SMBus_alert_pin_level \r
+ * @{\r
+ */\r
+\r
+#define I2C_SMBusAlert_Low ((uint16_t)0x2000)\r
+#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)\r
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \\r
+ ((ALERT) == I2C_SMBusAlert_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_PEC_position \r
+ * @{\r
+ */\r
+\r
+#define I2C_PECPosition_Next ((uint16_t)0x0800)\r
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)\r
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \\r
+ ((POSITION) == I2C_PECPosition_Current))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_BUF ((uint16_t)0x0400)\r
+#define I2C_IT_EVT ((uint16_t)0x0200)\r
+#define I2C_IT_ERR ((uint16_t)0x0100)\r
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2C_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define I2C_IT_SMBALERT ((uint32_t)0x01008000)\r
+#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)\r
+#define I2C_IT_PECERR ((uint32_t)0x01001000)\r
+#define I2C_IT_OVR ((uint32_t)0x01000800)\r
+#define I2C_IT_AF ((uint32_t)0x01000400)\r
+#define I2C_IT_ARLO ((uint32_t)0x01000200)\r
+#define I2C_IT_BERR ((uint32_t)0x01000100)\r
+#define I2C_IT_TXE ((uint32_t)0x06000080)\r
+#define I2C_IT_RXNE ((uint32_t)0x06000040)\r
+#define I2C_IT_STOPF ((uint32_t)0x02000010)\r
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)\r
+#define I2C_IT_BTF ((uint32_t)0x02000004)\r
+#define I2C_IT_ADDR ((uint32_t)0x02000002)\r
+#define I2C_IT_SB ((uint32_t)0x02000001)\r
+\r
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \\r
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \\r
+ ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \\r
+ ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \\r
+ ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \\r
+ ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \\r
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_flags_definition \r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SR2 register flags \r
+ */\r
+\r
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)\r
+#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)\r
+#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)\r
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)\r
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)\r
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)\r
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)\r
+\r
+/** \r
+ * @brief SR1 register flags \r
+ */\r
+\r
+#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)\r
+#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)\r
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)\r
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)\r
+#define I2C_FLAG_AF ((uint32_t)0x10000400)\r
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)\r
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)\r
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)\r
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)\r
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)\r
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)\r
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)\r
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)\r
+#define I2C_FLAG_SB ((uint32_t)0x10000001)\r
+\r
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+\r
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \\r
+ ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \\r
+ ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \\r
+ ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \\r
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \\r
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \\r
+ ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \\r
+ ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \\r
+ ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \\r
+ ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \\r
+ ((FLAG) == I2C_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Events \r
+ * @{\r
+ */\r
+\r
+/*========================================\r
+ \r
+ I2C Master Events (Events grouped in order of communication)\r
+ ==========================================*/\r
+/** \r
+ * @brief Communication start\r
+ * \r
+ * After sending the START condition (I2C_GenerateSTART() function) the master \r
+ * has to wait for this event. It means that the Start condition has been correctly \r
+ * released on the I2C bus (the bus is free, no other devices is communicating).\r
+ * \r
+ */\r
+/* --EV5 */\r
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */\r
+\r
+/** \r
+ * @brief Address Acknowledge\r
+ * \r
+ * After checking on EV5 (start condition correctly released on the bus), the \r
+ * master sends the address of the slave(s) with which it will communicate \r
+ * (I2C_Send7bitAddress() function, it also determines the direction of the communication: \r
+ * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges \r
+ * his address. If an acknowledge is sent on the bus, one of the following events will \r
+ * be set:\r
+ * \r
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED \r
+ * event is set.\r
+ * \r
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED \r
+ * is set\r
+ * \r
+ * 3) In case of 10-Bit addressing mode, the master (just after generating the START \r
+ * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() \r
+ * function). Then master should wait on EV9. It means that the 10-bit addressing \r
+ * header has been correctly sent on the bus. Then master should send the second part of \r
+ * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master \r
+ * should wait for event EV6. \r
+ * \r
+ */\r
+\r
+/* --EV6 */\r
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */\r
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */\r
+/* --EV9 */\r
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * If a communication is established (START condition generated and slave address \r
+ * acknowledged) then the master has to check on one of the following events for \r
+ * communication procedures:\r
+ * \r
+ * 1) Master Receiver mode: The master has to wait on the event EV7 then to read \r
+ * the data received from the slave (I2C_ReceiveData() function).\r
+ * \r
+ * 2) Master Transmitter mode: The master has to send data (I2C_SendData() \r
+ * function) then to wait on event EV8 or EV8_2.\r
+ * These two events are similar: \r
+ * - EV8 means that the data has been written in the data register and is \r
+ * being shifted out.\r
+ * - EV8_2 means that the data has been physically shifted out and output \r
+ * on the bus.\r
+ * In most cases, using EV8 is sufficient for the application.\r
+ * Using EV8_2 leads to a slower communication but ensure more reliable test.\r
+ * EV8_2 is also more suitable than EV8 for testing on the last data transmission \r
+ * (before Stop condition generation).\r
+ * \r
+ * @note In case the user software does not guarantee that this event EV7 is \r
+ * managed before the current byte end of transfer, then user may check on EV7 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ * \r
+ */\r
+\r
+/* Master RECEIVER mode -----------------------------*/ \r
+/* --EV7 */\r
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */\r
+\r
+/* Master TRANSMITTER mode --------------------------*/\r
+/* --EV8 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */\r
+/* --EV8_2 */\r
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */\r
+\r
+\r
+/*========================================\r
+ \r
+ I2C Slave Events (Events grouped in order of communication)\r
+ ==========================================*/\r
+\r
+/** \r
+ * @brief Communication start events\r
+ * \r
+ * Wait on one of these events at the start of the communication. It means that \r
+ * the I2C peripheral detected a Start condition on the bus (generated by master \r
+ * device) followed by the peripheral address. The peripheral generates an ACK \r
+ * condition on the bus (if the acknowledge feature is enabled through function \r
+ * I2C_AcknowledgeConfig()) and the events listed above are set :\r
+ * \r
+ * 1) In normal case (only one address managed by the slave), when the address \r
+ * sent by the master matches the own address of the peripheral (configured by \r
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set \r
+ * (where XXX could be TRANSMITTER or RECEIVER).\r
+ * \r
+ * 2) In case the address sent by the master matches the second address of the \r
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled \r
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED \r
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.\r
+ * \r
+ * 3) In case the address sent by the master is General Call (address 0x00) and \r
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) \r
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. \r
+ * \r
+ */\r
+\r
+/* --EV1 (all the events below are variants of EV1) */ \r
+/* 1) Case of One Single Address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */\r
+\r
+/* 2) Case of Dual address managed by the slave */\r
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */\r
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */\r
+\r
+/* 3) Case of General Call enabled for the slave */\r
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */\r
+\r
+/** \r
+ * @brief Communication events\r
+ * \r
+ * Wait on one of these events when EV1 has already been checked and: \r
+ * \r
+ * - Slave RECEIVER mode:\r
+ * - EV2: When the application is expecting a data byte to be received. \r
+ * - EV4: When the application is expecting the end of the communication: master \r
+ * sends a stop condition and data transmission is stopped.\r
+ * \r
+ * - Slave Transmitter mode:\r
+ * - EV3: When a byte has been transmitted by the slave and the application is expecting \r
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and\r
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be \r
+ * used when the user software doesn't guarantee the EV3 is managed before the\r
+ * current byte end of tranfer.\r
+ * - EV3_2: When the master sends a NACK in order to tell slave that data transmission \r
+ * shall end (before sending the STOP condition). In this case slave has to stop sending \r
+ * data bytes and expect a Stop condition on the bus.\r
+ * \r
+ * @note In case the user software does not guarantee that the event EV2 is \r
+ * managed before the current byte end of transfer, then user may check on EV2 \r
+ * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).\r
+ * In this case the communication may be slower.\r
+ *\r
+ */\r
+\r
+/* Slave RECEIVER mode --------------------------*/ \r
+/* --EV2 */\r
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */\r
+/* --EV4 */\r
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */\r
+\r
+/* Slave TRANSMITTER mode -----------------------*/\r
+/* --EV3 */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */\r
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */\r
+/* --EV3_2 */\r
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */\r
+\r
+/*=========================== End of Events Description ==========================================*/\r
+\r
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \\r
+ ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \\r
+ ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \\r
+ ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_own_address1 \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_clock_speed \r
+ * @{\r
+ */\r
+\r
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void I2C_DeInit(I2C_TypeDef* I2Cx);\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);\r
+\r
+/**\r
+ * @brief\r
+ ****************************************************************************************\r
+ *\r
+ * I2C State Monitoring Functions\r
+ * \r
+ **************************************************************************************** \r
+ * This I2C driver provides three different ways for I2C state monitoring\r
+ * depending on the application requirements and constraints:\r
+ * \r
+ * \r
+ * 1) Basic state monitoring:\r
+ * Using I2C_CheckEvent() function:\r
+ * It compares the status registers (SR1 and SR2) content to a given event\r
+ * (can be the combination of one or more flags).\r
+ * It returns SUCCESS if the current status includes the given flags \r
+ * and returns ERROR if one or more flags are missing in the current status.\r
+ * - When to use:\r
+ * - This function is suitable for most applications as well as for startup \r
+ * activity since the events are fully described in the product reference manual \r
+ * (RM0008).\r
+ * - It is also suitable for users who need to define their own events.\r
+ * - Limitations:\r
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
+ * hold or corrupted real state. \r
+ * In this case, it is advised to use error interrupts to monitor the error\r
+ * events and handle them in the interrupt IRQ handler.\r
+ * \r
+ * @note \r
+ * For error management, it is advised to use the following functions:\r
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
+ * Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler()\r
+ * in order to determine which error occured.\r
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
+ * and return to correct communication status.\r
+ * \r
+ *\r
+ * 2) Advanced state monitoring:\r
+ * Using the function I2C_GetLastEvent() which returns the image of both status \r
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ * by 16 bits and concatenated to Status Register 1).\r
+ * - When to use:\r
+ * - This function is suitable for the same applications above but it allows to\r
+ * overcome the limitations of I2C_GetFlagStatus() function (see below).\r
+ * The returned value could be compared to events already defined in the \r
+ * library (stm32f10x_i2c.h) or to custom values defined by user.\r
+ * - This function is suitable when multiple flags are monitored at the same time.\r
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
+ * choose when an event is accepted (when all events flags are set and no \r
+ * other flags are set or just when the needed flags are set like \r
+ * I2C_CheckEvent() function).\r
+ * - Limitations:\r
+ * - User may need to define his own events.\r
+ * - Same remark concerning the error management is applicable for this \r
+ * function if user decides to check only regular communication flags (and \r
+ * ignores error flags).\r
+ * \r
+ *\r
+ * 3) Flag-based state monitoring:\r
+ * Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ * one single flag (ie. I2C_FLAG_RXNE ...). \r
+ * - When to use:\r
+ * - This function could be used for specific applications or in debug phase.\r
+ * - It is suitable when only one flag checking is needed (most I2C events \r
+ * are monitored through multiple flags).\r
+ * - Limitations: \r
+ * - When calling this function, the Status register is accessed. Some flags are\r
+ * cleared when the status register is accessed. So checking the status\r
+ * of one Flag, may clear other ones.\r
+ * - Function may need to be called twice or more in order to monitor one \r
+ * single event.\r
+ * \r
+ */\r
+\r
+/**\r
+ * \r
+ * 1) Basic state monitoring\r
+ *******************************************************************************\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);\r
+/**\r
+ * \r
+ * 2) Advanced state monitoring\r
+ *******************************************************************************\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);\r
+/**\r
+ * \r
+ * 3) Flag-based state monitoring\r
+ *******************************************************************************\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+/**\r
+ *\r
+ *******************************************************************************\r
+ */\r
+\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_I2C_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_iwdg.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the IWDG \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_IWDG_H\r
+#define __STM32F10x_IWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup IWDG\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG_WriteAccess\r
+ * @{\r
+ */\r
+\r
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)\r
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)\r
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \\r
+ ((ACCESS) == IWDG_WriteAccess_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_prescaler \r
+ * @{\r
+ */\r
+\r
+#define IWDG_Prescaler_4 ((uint8_t)0x00)\r
+#define IWDG_Prescaler_8 ((uint8_t)0x01)\r
+#define IWDG_Prescaler_16 ((uint8_t)0x02)\r
+#define IWDG_Prescaler_32 ((uint8_t)0x03)\r
+#define IWDG_Prescaler_64 ((uint8_t)0x04)\r
+#define IWDG_Prescaler_128 ((uint8_t)0x05)\r
+#define IWDG_Prescaler_256 ((uint8_t)0x06)\r
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \\r
+ ((PRESCALER) == IWDG_Prescaler_8) || \\r
+ ((PRESCALER) == IWDG_Prescaler_16) || \\r
+ ((PRESCALER) == IWDG_Prescaler_32) || \\r
+ ((PRESCALER) == IWDG_Prescaler_64) || \\r
+ ((PRESCALER) == IWDG_Prescaler_128)|| \\r
+ ((PRESCALER) == IWDG_Prescaler_256))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Flag \r
+ * @{\r
+ */\r
+\r
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)\r
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)\r
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))\r
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);\r
+void IWDG_SetReload(uint16_t Reload);\r
+void IWDG_ReloadCounter(void);\r
+void IWDG_Enable(void);\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_IWDG_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_pwr.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the PWR firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_PWR_H\r
+#define __STM32F10x_PWR_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup PWR\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PWR_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PVD_detection_level \r
+ * @{\r
+ */ \r
+\r
+#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)\r
+#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)\r
+#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040)\r
+#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060)\r
+#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080)\r
+#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0)\r
+#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0)\r
+#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0)\r
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \\r
+ ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Regulator_state_is_STOP_mode \r
+ * @{\r
+ */\r
+\r
+#define PWR_Regulator_ON ((uint32_t)0x00000000)\r
+#define PWR_Regulator_LowPower ((uint32_t)0x00000001)\r
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \\r
+ ((REGULATOR) == PWR_Regulator_LowPower))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup STOP_mode_entry \r
+ * @{\r
+ */\r
+\r
+#define PWR_STOPEntry_WFI ((uint8_t)0x01)\r
+#define PWR_STOPEntry_WFE ((uint8_t)0x02)\r
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Flag \r
+ * @{\r
+ */\r
+\r
+#define PWR_FLAG_WU ((uint32_t)0x00000001)\r
+#define PWR_FLAG_SB ((uint32_t)0x00000002)\r
+#define PWR_FLAG_PVDO ((uint32_t)0x00000004)\r
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \\r
+ ((FLAG) == PWR_FLAG_PVDO))\r
+\r
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void PWR_DeInit(void);\r
+void PWR_BackupAccessCmd(FunctionalState NewState);\r
+void PWR_PVDCmd(FunctionalState NewState);\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);\r
+void PWR_WakeUpPinCmd(FunctionalState NewState);\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);\r
+void PWR_EnterSTANDBYMode(void);\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);\r
+void PWR_ClearFlag(uint32_t PWR_FLAG);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_PWR_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rcc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the RCC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RCC_H\r
+#define __STM32F10x_RCC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RCC\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Types\r
+ * @{\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */\r
+ uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */\r
+ uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */\r
+ uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */\r
+ uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */\r
+}RCC_ClocksTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup HSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_HSE_OFF ((uint32_t)0x00000000)\r
+#define RCC_HSE_ON ((uint32_t)0x00010000)\r
+#define RCC_HSE_Bypass ((uint32_t)0x00040000)\r
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\r
+ ((HSE) == RCC_HSE_Bypass))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PLL_entry_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)\r
+ #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)\r
+ #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)\r
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE_Div1) || \\r
+ ((SOURCE) == RCC_PLLSource_HSE_Div2))\r
+#else\r
+ #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)\r
+ #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \\r
+ ((SOURCE) == RCC_PLLSource_PREDIV1))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup PLL_multiplication_factor \r
+ * @{\r
+ */\r
+#ifndef STM32F10X_CL\r
+ #define RCC_PLLMul_2 ((uint32_t)0x00000000)\r
+ #define RCC_PLLMul_3 ((uint32_t)0x00040000)\r
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)\r
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)\r
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)\r
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)\r
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)\r
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)\r
+ #define RCC_PLLMul_10 ((uint32_t)0x00200000)\r
+ #define RCC_PLLMul_11 ((uint32_t)0x00240000)\r
+ #define RCC_PLLMul_12 ((uint32_t)0x00280000)\r
+ #define RCC_PLLMul_13 ((uint32_t)0x002C0000)\r
+ #define RCC_PLLMul_14 ((uint32_t)0x00300000)\r
+ #define RCC_PLLMul_15 ((uint32_t)0x00340000)\r
+ #define RCC_PLLMul_16 ((uint32_t)0x00380000)\r
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \\r
+ ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
+ ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \\r
+ ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \\r
+ ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \\r
+ ((MUL) == RCC_PLLMul_16))\r
+\r
+#else\r
+ #define RCC_PLLMul_4 ((uint32_t)0x00080000)\r
+ #define RCC_PLLMul_5 ((uint32_t)0x000C0000)\r
+ #define RCC_PLLMul_6 ((uint32_t)0x00100000)\r
+ #define RCC_PLLMul_7 ((uint32_t)0x00140000)\r
+ #define RCC_PLLMul_8 ((uint32_t)0x00180000)\r
+ #define RCC_PLLMul_9 ((uint32_t)0x001C0000)\r
+ #define RCC_PLLMul_6_5 ((uint32_t)0x00340000)\r
+\r
+ #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \\r
+ ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \\r
+ ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \\r
+ ((MUL) == RCC_PLLMul_6_5))\r
+#endif /* STM32F10X_CL */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PREDIV1_division_factor\r
+ * @{\r
+ */\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)\r
+ #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)\r
+ #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)\r
+ #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)\r
+ #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)\r
+ #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)\r
+ #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)\r
+ #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)\r
+ #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)\r
+ #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)\r
+ #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)\r
+ #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)\r
+ #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)\r
+ #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)\r
+ #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)\r
+ #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)\r
+ #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)\r
+\r
+ #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \\r
+ ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))\r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PREDIV1_clock_source\r
+ * @{\r
+ */\r
+#ifdef STM32F10X_CL\r
+/* PREDIV1 clock source (for STM32 connectivity line devices) */\r
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) \r
+ #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) \r
+\r
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \\r
+ ((SOURCE) == RCC_PREDIV1_Source_PLL2)) \r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/* PREDIV1 clock source (for STM32 Value line devices) */\r
+ #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) \r
+\r
+ #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) \r
+#endif\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef STM32F10X_CL\r
+/** @defgroup PREDIV2_division_factor\r
+ * @{\r
+ */\r
+ \r
+ #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)\r
+ #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)\r
+ #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)\r
+ #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)\r
+ #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)\r
+ #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)\r
+ #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)\r
+ #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)\r
+ #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)\r
+ #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)\r
+ #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)\r
+ #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)\r
+ #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)\r
+ #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)\r
+ #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)\r
+ #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)\r
+\r
+ #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \\r
+ ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PLL2_multiplication_factor\r
+ * @{\r
+ */\r
+ \r
+ #define RCC_PLL2Mul_8 ((uint32_t)0x00000600)\r
+ #define RCC_PLL2Mul_9 ((uint32_t)0x00000700)\r
+ #define RCC_PLL2Mul_10 ((uint32_t)0x00000800)\r
+ #define RCC_PLL2Mul_11 ((uint32_t)0x00000900)\r
+ #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)\r
+ #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)\r
+ #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)\r
+ #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)\r
+ #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)\r
+\r
+ #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \\r
+ ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \\r
+ ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \\r
+ ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \\r
+ ((MUL) == RCC_PLL2Mul_20))\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup PLL3_multiplication_factor\r
+ * @{\r
+ */\r
+\r
+ #define RCC_PLL3Mul_8 ((uint32_t)0x00006000)\r
+ #define RCC_PLL3Mul_9 ((uint32_t)0x00007000)\r
+ #define RCC_PLL3Mul_10 ((uint32_t)0x00008000)\r
+ #define RCC_PLL3Mul_11 ((uint32_t)0x00009000)\r
+ #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)\r
+ #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)\r
+ #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)\r
+ #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)\r
+ #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)\r
+\r
+ #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \\r
+ ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \\r
+ ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \\r
+ ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \\r
+ ((MUL) == RCC_PLL3Mul_20))\r
+/**\r
+ * @}\r
+ */\r
+\r
+#endif /* STM32F10X_CL */\r
+\r
+\r
+/** @defgroup System_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)\r
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)\r
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)\r
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \\r
+ ((SOURCE) == RCC_SYSCLKSource_PLLCLK))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)\r
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)\r
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)\r
+#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)\r
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)\r
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)\r
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)\r
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)\r
+#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)\r
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \\r
+ ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \\r
+ ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \\r
+ ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \\r
+ ((HCLK) == RCC_SYSCLK_Div512))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_APB2_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_HCLK_Div1 ((uint32_t)0x00000000)\r
+#define RCC_HCLK_Div2 ((uint32_t)0x00000400)\r
+#define RCC_HCLK_Div4 ((uint32_t)0x00000500)\r
+#define RCC_HCLK_Div8 ((uint32_t)0x00000600)\r
+#define RCC_HCLK_Div16 ((uint32_t)0x00000700)\r
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \\r
+ ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \\r
+ ((PCLK) == RCC_HCLK_Div16))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Interrupt_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_IT_LSIRDY ((uint8_t)0x01)\r
+#define RCC_IT_LSERDY ((uint8_t)0x02)\r
+#define RCC_IT_HSIRDY ((uint8_t)0x04)\r
+#define RCC_IT_HSERDY ((uint8_t)0x08)\r
+#define RCC_IT_PLLRDY ((uint8_t)0x10)\r
+#define RCC_IT_CSS ((uint8_t)0x80)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00))\r
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))\r
+ #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00))\r
+#else\r
+ #define RCC_IT_PLL2RDY ((uint8_t)0x20)\r
+ #define RCC_IT_PLL3RDY ((uint8_t)0x40)\r
+ #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))\r
+ #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \\r
+ ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \\r
+ ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \\r
+ ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY))\r
+ #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)\r
+#endif /* STM32F10X_CL */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifndef STM32F10X_CL\r
+/** @defgroup USB_Device_clock_source \r
+ * @{\r
+ */\r
+\r
+ #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)\r
+ #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \\r
+ ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))\r
+/**\r
+ * @}\r
+ */\r
+#else\r
+/** @defgroup USB_OTG_FS_clock_source \r
+ * @{\r
+ */\r
+ #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00)\r
+ #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \\r
+ ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2))\r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F10X_CL */ \r
+\r
+\r
+#ifdef STM32F10X_CL\r
+/** @defgroup I2S2_clock_source \r
+ * @{\r
+ */\r
+ #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)\r
+ #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S3_clock_source \r
+ * @{\r
+ */\r
+ #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)\r
+ #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)\r
+\r
+ #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \\r
+ ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) \r
+/**\r
+ * @}\r
+ */\r
+#endif /* STM32F10X_CL */ \r
+ \r
+\r
+/** @defgroup ADC_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)\r
+#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)\r
+#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)\r
+#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)\r
+#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \\r
+ ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup LSE_configuration \r
+ * @{\r
+ */\r
+\r
+#define RCC_LSE_OFF ((uint8_t)0x00)\r
+#define RCC_LSE_ON ((uint8_t)0x01)\r
+#define RCC_LSE_Bypass ((uint8_t)0x04)\r
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\r
+ ((LSE) == RCC_LSE_Bypass))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_clock_source \r
+ * @{\r
+ */\r
+\r
+#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)\r
+#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)\r
+#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)\r
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_LSI) || \\r
+ ((SOURCE) == RCC_RTCCLKSource_HSE_Div128))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup AHB_peripheral \r
+ * @{\r
+ */\r
+\r
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)\r
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)\r
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)\r
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)\r
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)\r
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)\r
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00))\r
+#else\r
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)\r
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)\r
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)\r
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)\r
+\r
+ #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00))\r
+ #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00))\r
+#endif /* STM32F10X_CL */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup APB2_peripheral \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)\r
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)\r
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)\r
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)\r
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)\r
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)\r
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)\r
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)\r
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)\r
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)\r
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)\r
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)\r
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)\r
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)\r
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)\r
+#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)\r
+#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)\r
+#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)\r
+#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)\r
+#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)\r
+#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)\r
+\r
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup APB1_peripheral \r
+ * @{\r
+ */\r
+\r
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)\r
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)\r
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)\r
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)\r
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)\r
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)\r
+#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)\r
+#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)\r
+#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)\r
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)\r
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)\r
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)\r
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)\r
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)\r
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)\r
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)\r
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)\r
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)\r
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)\r
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)\r
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)\r
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)\r
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)\r
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)\r
+#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)\r
+ \r
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup Clock_source_to_output_on_MCO_pin \r
+ * @{\r
+ */\r
+\r
+#define RCC_MCO_NoClock ((uint8_t)0x00)\r
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)\r
+#define RCC_MCO_HSI ((uint8_t)0x05)\r
+#define RCC_MCO_HSE ((uint8_t)0x06)\r
+#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \\r
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \\r
+ ((MCO) == RCC_MCO_PLLCLK_Div2))\r
+#else\r
+ #define RCC_MCO_PLL2CLK ((uint8_t)0x08)\r
+ #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)\r
+ #define RCC_MCO_XT1 ((uint8_t)0x0A)\r
+ #define RCC_MCO_PLL3CLK ((uint8_t)0x0B)\r
+\r
+ #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \\r
+ ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \\r
+ ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \\r
+ ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \\r
+ ((MCO) == RCC_MCO_PLL3CLK))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Flag \r
+ * @{\r
+ */\r
+\r
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)\r
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)\r
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)\r
+#define RCC_FLAG_LSERDY ((uint8_t)0x41)\r
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)\r
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)\r
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)\r
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)\r
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)\r
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)\r
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \\r
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \\r
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_LPWRRST))\r
+#else\r
+ #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) \r
+ #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) \r
+ #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \\r
+ ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \\r
+ ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \\r
+ ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \\r
+ ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \\r
+ ((FLAG) == RCC_FLAG_LPWRRST))\r
+#endif /* STM32F10X_CL */ \r
+\r
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void RCC_DeInit(void);\r
+void RCC_HSEConfig(uint32_t RCC_HSE);\r
+ErrorStatus RCC_WaitForHSEStartUp(void);\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);\r
+void RCC_HSICmd(FunctionalState NewState);\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);\r
+void RCC_PLLCmd(FunctionalState NewState);\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)\r
+ void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);\r
+#endif\r
+\r
+#ifdef STM32F10X_CL\r
+ void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);\r
+ void RCC_PLL2Config(uint32_t RCC_PLL2Mul);\r
+ void RCC_PLL2Cmd(FunctionalState NewState);\r
+ void RCC_PLL3Config(uint32_t RCC_PLL3Mul);\r
+ void RCC_PLL3Cmd(FunctionalState NewState);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);\r
+uint8_t RCC_GetSYSCLKSource(void);\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK);\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK);\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);\r
+\r
+#ifndef STM32F10X_CL\r
+ void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);\r
+#else\r
+ void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);\r
+\r
+#ifdef STM32F10X_CL\r
+ void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); \r
+ void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_LSEConfig(uint8_t RCC_LSE);\r
+void RCC_LSICmd(FunctionalState NewState);\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);\r
+void RCC_RTCCLKCmd(FunctionalState NewState);\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+\r
+#ifdef STM32F10X_CL\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);\r
+#endif /* STM32F10X_CL */ \r
+\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);\r
+void RCC_BackupResetCmd(FunctionalState NewState);\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);\r
+void RCC_MCOConfig(uint8_t RCC_MCO);\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);\r
+void RCC_ClearFlag(void);\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_RCC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rtc.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the RTC firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_RTC_H\r
+#define __STM32F10x_RTC_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup RTC\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RTC_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC_interrupts_define \r
+ * @{\r
+ */\r
+\r
+#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */\r
+#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */\r
+#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */\r
+#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00))\r
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \\r
+ ((IT) == RTC_IT_SEC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RTC_interrupts_flags \r
+ * @{\r
+ */\r
+\r
+#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */\r
+#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */\r
+#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */\r
+#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */\r
+#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */\r
+#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00))\r
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \\r
+ ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \\r
+ ((FLAG) == RTC_FLAG_SEC))\r
+#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);\r
+void RTC_EnterConfigMode(void);\r
+void RTC_ExitConfigMode(void);\r
+uint32_t RTC_GetCounter(void);\r
+void RTC_SetCounter(uint32_t CounterValue);\r
+void RTC_SetPrescaler(uint32_t PrescalerValue);\r
+void RTC_SetAlarm(uint32_t AlarmValue);\r
+uint32_t RTC_GetDivider(void);\r
+void RTC_WaitForLastTask(void);\r
+void RTC_WaitForSynchro(void);\r
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);\r
+void RTC_ClearFlag(uint16_t RTC_FLAG);\r
+ITStatus RTC_GetITStatus(uint16_t RTC_IT);\r
+void RTC_ClearITPendingBit(uint16_t RTC_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_RTC_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_sdio.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the SDIO firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SDIO_H\r
+#define __STM32F10x_SDIO_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SDIO\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Types\r
+ * @{\r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref SDIO_Clock_Edge */\r
+\r
+ uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is\r
+ enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Clock_Bypass */\r
+\r
+ uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or\r
+ disabled when the bus is idle.\r
+ This parameter can be a value of @ref SDIO_Clock_Power_Save */\r
+\r
+ uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.\r
+ This parameter can be a value of @ref SDIO_Bus_Wide */\r
+\r
+ uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Hardware_Flow_Control */\r
+\r
+ uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.\r
+ This parameter can be a value between 0x00 and 0xFF. */\r
+ \r
+} SDIO_InitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent\r
+ to a card as part of a command message. If a command\r
+ contains an argument, it must be loaded into this register\r
+ before writing the command to the command register */\r
+\r
+ uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */\r
+\r
+ uint32_t SDIO_Response; /*!< Specifies the SDIO response type.\r
+ This parameter can be a value of @ref SDIO_Response_Type */\r
+\r
+ uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_Wait_Interrupt_State */\r
+\r
+ uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_CPSM_State */\r
+} SDIO_CmdInitTypeDef;\r
+\r
+typedef struct\r
+{\r
+ uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */\r
+\r
+ uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */\r
+ \r
+ uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.\r
+ This parameter can be a value of @ref SDIO_Data_Block_Size */\r
+ \r
+ uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer\r
+ is a read or write.\r
+ This parameter can be a value of @ref SDIO_Transfer_Direction */\r
+ \r
+ uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.\r
+ This parameter can be a value of @ref SDIO_Transfer_Type */\r
+ \r
+ uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)\r
+ is enabled or disabled.\r
+ This parameter can be a value of @ref SDIO_DPSM_State */\r
+} SDIO_DataInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Edge \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)\r
+#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)\r
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \\r
+ ((EDGE) == SDIO_ClockEdge_Falling))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Clock_Bypass \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) \r
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \\r
+ ((BYPASS) == SDIO_ClockBypass_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Clock_Power_Save \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)\r
+#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) \r
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \\r
+ ((SAVE) == SDIO_ClockPowerSave_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Bus_Wide \r
+ * @{\r
+ */\r
+\r
+#define SDIO_BusWide_1b ((uint32_t)0x00000000)\r
+#define SDIO_BusWide_4b ((uint32_t)0x00000800)\r
+#define SDIO_BusWide_8b ((uint32_t)0x00001000)\r
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \\r
+ ((WIDE) == SDIO_BusWide_8b))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Hardware_Flow_Control \r
+ * @{\r
+ */\r
+\r
+#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)\r
+#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)\r
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \\r
+ ((CONTROL) == SDIO_HardwareFlowControl_Enable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Power_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_PowerState_OFF ((uint32_t)0x00000000)\r
+#define SDIO_PowerState_ON ((uint32_t)0x00000003)\r
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SDIO_Interrupt_soucres \r
+ * @{\r
+ */\r
+\r
+#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_IT_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_IT_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_IT_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_IT_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_IT_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_IT_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Command_Index\r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Response_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Response_No ((uint32_t)0x00000000)\r
+#define SDIO_Response_Short ((uint32_t)0x00000040)\r
+#define SDIO_Response_Long ((uint32_t)0x000000C0)\r
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \\r
+ ((RESPONSE) == SDIO_Response_Short) || \\r
+ ((RESPONSE) == SDIO_Response_Long))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Wait_Interrupt_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */\r
+#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */\r
+#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */\r
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \\r
+ ((WAIT) == SDIO_Wait_Pend))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_CPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_CPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_CPSM_Enable ((uint32_t)0x00000400)\r
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SDIO_Response_Registers \r
+ * @{\r
+ */\r
+\r
+#define SDIO_RESP1 ((uint32_t)0x00000000)\r
+#define SDIO_RESP2 ((uint32_t)0x00000004)\r
+#define SDIO_RESP3 ((uint32_t)0x00000008)\r
+#define SDIO_RESP4 ((uint32_t)0x0000000C)\r
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \\r
+ ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Length \r
+ * @{\r
+ */\r
+\r
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Data_Block_Size \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)\r
+#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)\r
+#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)\r
+#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)\r
+#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)\r
+#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)\r
+#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)\r
+#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)\r
+#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)\r
+#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)\r
+#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)\r
+#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)\r
+#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)\r
+#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)\r
+#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)\r
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_32b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_64b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_128b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_256b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_512b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_1024b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_2048b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_4096b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_8192b) || \\r
+ ((SIZE) == SDIO_DataBlockSize_16384b)) \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Direction \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)\r
+#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)\r
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \\r
+ ((DIR) == SDIO_TransferDir_ToSDIO))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Transfer_Type \r
+ * @{\r
+ */\r
+\r
+#define SDIO_TransferMode_Block ((uint32_t)0x00000000)\r
+#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)\r
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \\r
+ ((MODE) == SDIO_TransferMode_Block))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_DPSM_State \r
+ * @{\r
+ */\r
+\r
+#define SDIO_DPSM_Disable ((uint32_t)0x00000000)\r
+#define SDIO_DPSM_Enable ((uint32_t)0x00000001)\r
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Flags \r
+ * @{\r
+ */\r
+\r
+#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)\r
+#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)\r
+#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)\r
+#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)\r
+#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)\r
+#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)\r
+#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)\r
+#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)\r
+#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)\r
+#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)\r
+#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)\r
+#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)\r
+#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)\r
+#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)\r
+#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)\r
+#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)\r
+#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)\r
+#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)\r
+#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)\r
+#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)\r
+#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)\r
+#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)\r
+#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)\r
+#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)\r
+#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_DCRCFAIL) || \\r
+ ((FLAG) == SDIO_FLAG_CTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_DTIMEOUT) || \\r
+ ((FLAG) == SDIO_FLAG_TXUNDERR) || \\r
+ ((FLAG) == SDIO_FLAG_RXOVERR) || \\r
+ ((FLAG) == SDIO_FLAG_CMDREND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDSENT) || \\r
+ ((FLAG) == SDIO_FLAG_DATAEND) || \\r
+ ((FLAG) == SDIO_FLAG_STBITERR) || \\r
+ ((FLAG) == SDIO_FLAG_DBCKEND) || \\r
+ ((FLAG) == SDIO_FLAG_CMDACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXACT) || \\r
+ ((FLAG) == SDIO_FLAG_RXACT) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOHE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOHF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOF) || \\r
+ ((FLAG) == SDIO_FLAG_TXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_RXFIFOE) || \\r
+ ((FLAG) == SDIO_FLAG_TXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_RXDAVL) || \\r
+ ((FLAG) == SDIO_FLAG_SDIOIT) || \\r
+ ((FLAG) == SDIO_FLAG_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))\r
+\r
+#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \\r
+ ((IT) == SDIO_IT_DCRCFAIL) || \\r
+ ((IT) == SDIO_IT_CTIMEOUT) || \\r
+ ((IT) == SDIO_IT_DTIMEOUT) || \\r
+ ((IT) == SDIO_IT_TXUNDERR) || \\r
+ ((IT) == SDIO_IT_RXOVERR) || \\r
+ ((IT) == SDIO_IT_CMDREND) || \\r
+ ((IT) == SDIO_IT_CMDSENT) || \\r
+ ((IT) == SDIO_IT_DATAEND) || \\r
+ ((IT) == SDIO_IT_STBITERR) || \\r
+ ((IT) == SDIO_IT_DBCKEND) || \\r
+ ((IT) == SDIO_IT_CMDACT) || \\r
+ ((IT) == SDIO_IT_TXACT) || \\r
+ ((IT) == SDIO_IT_RXACT) || \\r
+ ((IT) == SDIO_IT_TXFIFOHE) || \\r
+ ((IT) == SDIO_IT_RXFIFOHF) || \\r
+ ((IT) == SDIO_IT_TXFIFOF) || \\r
+ ((IT) == SDIO_IT_RXFIFOF) || \\r
+ ((IT) == SDIO_IT_TXFIFOE) || \\r
+ ((IT) == SDIO_IT_RXFIFOE) || \\r
+ ((IT) == SDIO_IT_TXDAVL) || \\r
+ ((IT) == SDIO_IT_RXDAVL) || \\r
+ ((IT) == SDIO_IT_SDIOIT) || \\r
+ ((IT) == SDIO_IT_CEATAEND))\r
+\r
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Read_Wait_Mode \r
+ * @{\r
+ */\r
+\r
+#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)\r
+#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)\r
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \\r
+ ((MODE) == SDIO_ReadWaitMode_DATA2))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void SDIO_DeInit(void);\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);\r
+void SDIO_ClockCmd(FunctionalState NewState);\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);\r
+uint32_t SDIO_GetPowerState(void);\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);\r
+void SDIO_DMACmd(FunctionalState NewState);\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);\r
+uint8_t SDIO_GetCommandResponse(void);\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);\r
+uint32_t SDIO_GetDataCounter(void);\r
+uint32_t SDIO_ReadData(void);\r
+void SDIO_WriteData(uint32_t Data);\r
+uint32_t SDIO_GetFIFOCount(void);\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState);\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState);\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);\r
+void SDIO_SetSDIOOperation(FunctionalState NewState);\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState);\r
+void SDIO_CEATAITCmd(FunctionalState NewState);\r
+void SDIO_SendCEATACmd(FunctionalState NewState);\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_SDIO_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_spi.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the SPI firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_SPI_H\r
+#define __STM32F10x_SPI_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup SPI\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SPI_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief SPI Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.\r
+ This parameter can be a value of @ref SPI_data_direction */\r
+\r
+ uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.\r
+ This parameter can be a value of @ref SPI_mode */\r
+\r
+ uint16_t SPI_DataSize; /*!< Specifies the SPI data size.\r
+ This parameter can be a value of @ref SPI_data_size */\r
+\r
+ uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.\r
+ This parameter can be a value of @ref SPI_Clock_Polarity */\r
+\r
+ uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.\r
+ This parameter can be a value of @ref SPI_Clock_Phase */\r
+\r
+ uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by\r
+ hardware (NSS pin) or by software using the SSI bit.\r
+ This parameter can be a value of @ref SPI_Slave_Select_management */\r
+ \r
+ uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be\r
+ used to configure the transmit and receive SCK clock.\r
+ This parameter can be a value of @ref SPI_BaudRate_Prescaler.\r
+ @note The communication clock is derived from the master\r
+ clock. The slave clock does not need to be set. */\r
+\r
+ uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.\r
+ This parameter can be a value of @ref SPI_MSB_LSB_transmission */\r
+\r
+ uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */\r
+}SPI_InitTypeDef;\r
+\r
+/** \r
+ * @brief I2S Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.\r
+ This parameter can be a value of @ref I2S_Mode */\r
+\r
+ uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Standard */\r
+\r
+ uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Data_Format */\r
+\r
+ uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.\r
+ This parameter can be a value of @ref I2S_MCLK_Output */\r
+\r
+ uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.\r
+ This parameter can be a value of @ref I2S_Audio_Frequency */\r
+\r
+ uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.\r
+ This parameter can be a value of @ref I2S_Clock_Polarity */\r
+}I2S_InitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \\r
+ ((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+\r
+#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \\r
+ ((PERIPH) == SPI3))\r
+\r
+/** @defgroup SPI_data_direction \r
+ * @{\r
+ */\r
+ \r
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)\r
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)\r
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)\r
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)\r
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \\r
+ ((MODE) == SPI_Direction_2Lines_RxOnly) || \\r
+ ((MODE) == SPI_Direction_1Line_Rx) || \\r
+ ((MODE) == SPI_Direction_1Line_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_mode \r
+ * @{\r
+ */\r
+\r
+#define SPI_Mode_Master ((uint16_t)0x0104)\r
+#define SPI_Mode_Slave ((uint16_t)0x0000)\r
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \\r
+ ((MODE) == SPI_Mode_Slave))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_data_size \r
+ * @{\r
+ */\r
+\r
+#define SPI_DataSize_16b ((uint16_t)0x0800)\r
+#define SPI_DataSize_8b ((uint16_t)0x0000)\r
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \\r
+ ((DATASIZE) == SPI_DataSize_8b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPOL_Low ((uint16_t)0x0000)\r
+#define SPI_CPOL_High ((uint16_t)0x0002)\r
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \\r
+ ((CPOL) == SPI_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Clock_Phase \r
+ * @{\r
+ */\r
+\r
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)\r
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)\r
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \\r
+ ((CPHA) == SPI_CPHA_2Edge))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Slave_Select_management \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSS_Soft ((uint16_t)0x0200)\r
+#define SPI_NSS_Hard ((uint16_t)0x0000)\r
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \\r
+ ((NSS) == SPI_NSS_Hard))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_BaudRate_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)\r
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)\r
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)\r
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)\r
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)\r
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)\r
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)\r
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)\r
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_4) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_8) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_16) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_32) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_64) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_128) || \\r
+ ((PRESCALER) == SPI_BaudRatePrescaler_256))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup SPI_MSB_LSB_transmission \r
+ * @{\r
+ */\r
+\r
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)\r
+#define SPI_FirstBit_LSB ((uint16_t)0x0080)\r
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \\r
+ ((BIT) == SPI_FirstBit_LSB))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Mode \r
+ * @{\r
+ */\r
+\r
+#define I2S_Mode_SlaveTx ((uint16_t)0x0000)\r
+#define I2S_Mode_SlaveRx ((uint16_t)0x0100)\r
+#define I2S_Mode_MasterTx ((uint16_t)0x0200)\r
+#define I2S_Mode_MasterRx ((uint16_t)0x0300)\r
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \\r
+ ((MODE) == I2S_Mode_SlaveRx) || \\r
+ ((MODE) == I2S_Mode_MasterTx) || \\r
+ ((MODE) == I2S_Mode_MasterRx) )\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Standard \r
+ * @{\r
+ */\r
+\r
+#define I2S_Standard_Phillips ((uint16_t)0x0000)\r
+#define I2S_Standard_MSB ((uint16_t)0x0010)\r
+#define I2S_Standard_LSB ((uint16_t)0x0020)\r
+#define I2S_Standard_PCMShort ((uint16_t)0x0030)\r
+#define I2S_Standard_PCMLong ((uint16_t)0x00B0)\r
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \\r
+ ((STANDARD) == I2S_Standard_MSB) || \\r
+ ((STANDARD) == I2S_Standard_LSB) || \\r
+ ((STANDARD) == I2S_Standard_PCMShort) || \\r
+ ((STANDARD) == I2S_Standard_PCMLong))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Data_Format \r
+ * @{\r
+ */\r
+\r
+#define I2S_DataFormat_16b ((uint16_t)0x0000)\r
+#define I2S_DataFormat_16bextended ((uint16_t)0x0001)\r
+#define I2S_DataFormat_24b ((uint16_t)0x0003)\r
+#define I2S_DataFormat_32b ((uint16_t)0x0005)\r
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \\r
+ ((FORMAT) == I2S_DataFormat_16bextended) || \\r
+ ((FORMAT) == I2S_DataFormat_24b) || \\r
+ ((FORMAT) == I2S_DataFormat_32b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2S_MCLK_Output \r
+ * @{\r
+ */\r
+\r
+#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)\r
+#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)\r
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \\r
+ ((OUTPUT) == I2S_MCLKOutput_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2S_Audio_Frequency \r
+ * @{\r
+ */\r
+\r
+#define I2S_AudioFreq_192k ((uint32_t)192000)\r
+#define I2S_AudioFreq_96k ((uint32_t)96000)\r
+#define I2S_AudioFreq_48k ((uint32_t)48000)\r
+#define I2S_AudioFreq_44k ((uint32_t)44100)\r
+#define I2S_AudioFreq_32k ((uint32_t)32000)\r
+#define I2S_AudioFreq_22k ((uint32_t)22050)\r
+#define I2S_AudioFreq_16k ((uint32_t)16000)\r
+#define I2S_AudioFreq_11k ((uint32_t)11025)\r
+#define I2S_AudioFreq_8k ((uint32_t)8000)\r
+#define I2S_AudioFreq_Default ((uint32_t)2)\r
+\r
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \\r
+ ((FREQ) <= I2S_AudioFreq_192k)) || \\r
+ ((FREQ) == I2S_AudioFreq_Default))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup I2S_Clock_Polarity \r
+ * @{\r
+ */\r
+\r
+#define I2S_CPOL_Low ((uint16_t)0x0000)\r
+#define I2S_CPOL_High ((uint16_t)0x0008)\r
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \\r
+ ((CPOL) == I2S_CPOL_High))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_DMA_transfer_requests \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)\r
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)\r
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_NSS_internal_software_mangement \r
+ * @{\r
+ */\r
+\r
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)\r
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)\r
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \\r
+ ((INTERNAL) == SPI_NSSInternalSoft_Reset))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_Transmit_Receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_CRC_Tx ((uint8_t)0x00)\r
+#define SPI_CRC_Rx ((uint8_t)0x01)\r
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_direction_transmit_receive \r
+ * @{\r
+ */\r
+\r
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)\r
+#define SPI_Direction_Tx ((uint16_t)0x4000)\r
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \\r
+ ((DIRECTION) == SPI_Direction_Tx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_interrupts_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)\r
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)\r
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)\r
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == SPI_I2S_IT_RXNE) || \\r
+ ((IT) == SPI_I2S_IT_ERR))\r
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)\r
+#define SPI_IT_MODF ((uint8_t)0x55)\r
+#define SPI_IT_CRCERR ((uint8_t)0x54)\r
+#define I2S_IT_UDR ((uint8_t)0x53)\r
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))\r
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \\r
+ ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \\r
+ ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_I2S_flags_definition \r
+ * @{\r
+ */\r
+\r
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)\r
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)\r
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)\r
+#define I2S_FLAG_UDR ((uint16_t)0x0008)\r
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)\r
+#define SPI_FLAG_MODF ((uint16_t)0x0020)\r
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)\r
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)\r
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))\r
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \\r
+ ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \\r
+ ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \\r
+ ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_CRC_polynomial \r
+ * @{\r
+ */\r
+\r
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_SPI_H */\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_tim.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the TIM firmware \r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_TIM_H\r
+#define __STM32F10x_TIM_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup TIM\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup TIM_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief TIM Time Base Init structure definition\r
+ * @note This sturcture is used with all TIMx except for TIM6 and TIM7. \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.\r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_CounterMode; /*!< Specifies the counter mode.\r
+ This parameter can be a value of @ref TIM_Counter_Mode */\r
+\r
+ uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active\r
+ Auto-Reload Register at the next update event.\r
+ This parameter must be a number between 0x0000 and 0xFFFF. */ \r
+\r
+ uint16_t TIM_ClockDivision; /*!< Specifies the clock division.\r
+ This parameter can be a value of @ref TIM_Clock_Division_CKD */\r
+\r
+ uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter\r
+ reaches zero, an update event is generated and counting restarts\r
+ from the RCR value (N).\r
+ This means in PWM mode that (N+1) corresponds to:\r
+ - the number of PWM periods in edge-aligned mode\r
+ - the number of half PWM period in center-aligned mode\r
+ This parameter must be a number between 0x00 and 0xFF. \r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_TimeBaseInitTypeDef; \r
+\r
+/** \r
+ * @brief TIM Output Compare Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+ uint16_t TIM_OCMode; /*!< Specifies the TIM mode.\r
+ This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\r
+\r
+ uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_state */\r
+\r
+ uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_state\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. \r
+ This parameter can be a number between 0x0000 and 0xFFFF */\r
+\r
+ uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Polarity */\r
+\r
+ uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+\r
+ uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.\r
+ This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\r
+ @note This parameter is valid only for TIM1 and TIM8. */\r
+} TIM_OCInitTypeDef;\r
+\r
+/** \r
+ * @brief TIM Input Capture Init structure definition \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_Channel; /*!< Specifies the TIM channel.\r
+ This parameter can be a value of @ref TIM_Channel */\r
+\r
+ uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Polarity */\r
+\r
+ uint16_t TIM_ICSelection; /*!< Specifies the input.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Selection */\r
+\r
+ uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.\r
+ This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\r
+\r
+ uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.\r
+ This parameter can be a number between 0x0 and 0xF */\r
+} TIM_ICInitTypeDef;\r
+\r
+/** \r
+ * @brief BDTR structure definition \r
+ * @note This sturcture is used only with TIM1 and TIM8. \r
+ */\r
+\r
+typedef struct\r
+{\r
+\r
+ uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.\r
+ This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */\r
+\r
+ uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.\r
+ This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */\r
+\r
+ uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.\r
+ This parameter can be a value of @ref Lock_level */ \r
+\r
+ uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the\r
+ switching-on of the outputs.\r
+ This parameter can be a number between 0x00 and 0xFF */\r
+\r
+ uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. \r
+ This parameter can be a value of @ref Break_Input_enable_disable */\r
+\r
+ uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.\r
+ This parameter can be a value of @ref Break_Polarity */\r
+\r
+ uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. \r
+ This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\r
+} TIM_BDTRInitTypeDef;\r
+\r
+/** @defgroup TIM_Exported_constants \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10)|| \\r
+ ((PERIPH) == TIM11)|| \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM13)|| \\r
+ ((PERIPH) == TIM14)|| \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST1: TIM 1 and 8 */\r
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM8))\r
+\r
+/* LIST2: TIM 1, 8, 15 16 and 17 */\r
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17)) \r
+\r
+/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */\r
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8)) \r
+ \r
+/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */\r
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ \r
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)) \r
+\r
+/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */\r
+#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM15))\r
+\r
+/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */\r
+#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM15)) \r
+\r
+/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ \r
+#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM9) || \\r
+ ((PERIPH) == TIM10)|| \\r
+ ((PERIPH) == TIM11)|| \\r
+ ((PERIPH) == TIM12)|| \\r
+ ((PERIPH) == TIM13)|| \\r
+ ((PERIPH) == TIM14)|| \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17))\r
+\r
+/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */\r
+#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \\r
+ ((PERIPH) == TIM2) || \\r
+ ((PERIPH) == TIM3) || \\r
+ ((PERIPH) == TIM4) || \\r
+ ((PERIPH) == TIM5) || \\r
+ ((PERIPH) == TIM6) || \\r
+ ((PERIPH) == TIM7) || \\r
+ ((PERIPH) == TIM8) || \\r
+ ((PERIPH) == TIM15)|| \\r
+ ((PERIPH) == TIM16)|| \\r
+ ((PERIPH) == TIM17)) \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_and_PWM_modes \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCMode_Timing ((uint16_t)0x0000)\r
+#define TIM_OCMode_Active ((uint16_t)0x0010)\r
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)\r
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)\r
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)\r
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)\r
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2))\r
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \\r
+ ((MODE) == TIM_OCMode_Active) || \\r
+ ((MODE) == TIM_OCMode_Inactive) || \\r
+ ((MODE) == TIM_OCMode_Toggle)|| \\r
+ ((MODE) == TIM_OCMode_PWM1) || \\r
+ ((MODE) == TIM_OCMode_PWM2) || \\r
+ ((MODE) == TIM_ForcedAction_Active) || \\r
+ ((MODE) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_One_Pulse_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_OPMode_Single ((uint16_t)0x0008)\r
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)\r
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \\r
+ ((MODE) == TIM_OPMode_Repetitive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Channel \r
+ * @{\r
+ */\r
+\r
+#define TIM_Channel_1 ((uint16_t)0x0000)\r
+#define TIM_Channel_2 ((uint16_t)0x0004)\r
+#define TIM_Channel_3 ((uint16_t)0x0008)\r
+#define TIM_Channel_4 ((uint16_t)0x000C)\r
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3) || \\r
+ ((CHANNEL) == TIM_Channel_4))\r
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2))\r
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \\r
+ ((CHANNEL) == TIM_Channel_2) || \\r
+ ((CHANNEL) == TIM_Channel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Clock_Division_CKD \r
+ * @{\r
+ */\r
+\r
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)\r
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)\r
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)\r
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \\r
+ ((DIV) == TIM_CKD_DIV2) || \\r
+ ((DIV) == TIM_CKD_DIV4))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Counter_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_CounterMode_Up ((uint16_t)0x0000)\r
+#define TIM_CounterMode_Down ((uint16_t)0x0010)\r
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)\r
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)\r
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)\r
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \\r
+ ((MODE) == TIM_CounterMode_Down) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned1) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned2) || \\r
+ ((MODE) == TIM_CounterMode_CenterAligned3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)\r
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \\r
+ ((POLARITY) == TIM_OCPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_N_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)\r
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)\r
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \\r
+ ((POLARITY) == TIM_OCNPolarity_Low))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Output_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputState_Enable ((uint16_t)0x0001)\r
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \\r
+ ((STATE) == TIM_OutputState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)\r
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)\r
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \\r
+ ((STATE) == TIM_OutputNState_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCx_Enable ((uint16_t)0x0001)\r
+#define TIM_CCx_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \\r
+ ((CCX) == TIM_CCx_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Capture_Compare_N_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_CCxN_Enable ((uint16_t)0x0004)\r
+#define TIM_CCxN_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \\r
+ ((CCXN) == TIM_CCxN_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Break_Input_enable_disable \r
+ * @{\r
+ */\r
+\r
+#define TIM_Break_Enable ((uint16_t)0x1000)\r
+#define TIM_Break_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \\r
+ ((STATE) == TIM_Break_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Break_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)\r
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)\r
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \\r
+ ((POLARITY) == TIM_BreakPolarity_High))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_AOE_Bit_Set_Reset \r
+ * @{\r
+ */\r
+\r
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)\r
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \\r
+ ((STATE) == TIM_AutomaticOutput_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup Lock_level \r
+ * @{\r
+ */\r
+\r
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)\r
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)\r
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)\r
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)\r
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \\r
+ ((LEVEL) == TIM_LOCKLevel_1) || \\r
+ ((LEVEL) == TIM_LOCKLevel_2) || \\r
+ ((LEVEL) == TIM_LOCKLevel_3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)\r
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \\r
+ ((STATE) == TIM_OSSIState_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state \r
+ * @{\r
+ */\r
+\r
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)\r
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \\r
+ ((STATE) == TIM_OSSRState_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)\r
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \\r
+ ((STATE) == TIM_OCIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Output_Compare_N_Idle_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)\r
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)\r
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \\r
+ ((STATE) == TIM_OCNIdleState_Reset))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Polarity \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)\r
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)\r
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)\r
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling))\r
+#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \\r
+ ((POLARITY) == TIM_ICPolarity_Falling)|| \\r
+ ((POLARITY) == TIM_ICPolarity_BothEdge)) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be \r
+ connected to IC1, IC2, IC3 or IC4, respectively */\r
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be\r
+ connected to IC2, IC1, IC4 or IC3, respectively. */\r
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */\r
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_IndirectTI) || \\r
+ ((SELECTION) == TIM_ICSelection_TRC))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */\r
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */\r
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */\r
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */\r
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ICPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_interrupt_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_IT_Update ((uint16_t)0x0001)\r
+#define TIM_IT_CC1 ((uint16_t)0x0002)\r
+#define TIM_IT_CC2 ((uint16_t)0x0004)\r
+#define TIM_IT_CC3 ((uint16_t)0x0008)\r
+#define TIM_IT_CC4 ((uint16_t)0x0010)\r
+#define TIM_IT_COM ((uint16_t)0x0020)\r
+#define TIM_IT_Trigger ((uint16_t)0x0040)\r
+#define TIM_IT_Break ((uint16_t)0x0080)\r
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))\r
+\r
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \\r
+ ((IT) == TIM_IT_CC1) || \\r
+ ((IT) == TIM_IT_CC2) || \\r
+ ((IT) == TIM_IT_CC3) || \\r
+ ((IT) == TIM_IT_CC4) || \\r
+ ((IT) == TIM_IT_COM) || \\r
+ ((IT) == TIM_IT_Trigger) || \\r
+ ((IT) == TIM_IT_Break))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Base_address \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)\r
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)\r
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)\r
+#define TIM_DMABase_DIER ((uint16_t)0x0003)\r
+#define TIM_DMABase_SR ((uint16_t)0x0004)\r
+#define TIM_DMABase_EGR ((uint16_t)0x0005)\r
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)\r
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)\r
+#define TIM_DMABase_CCER ((uint16_t)0x0008)\r
+#define TIM_DMABase_CNT ((uint16_t)0x0009)\r
+#define TIM_DMABase_PSC ((uint16_t)0x000A)\r
+#define TIM_DMABase_ARR ((uint16_t)0x000B)\r
+#define TIM_DMABase_RCR ((uint16_t)0x000C)\r
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)\r
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)\r
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)\r
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)\r
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)\r
+#define TIM_DMABase_DCR ((uint16_t)0x0012)\r
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \\r
+ ((BASE) == TIM_DMABase_CR2) || \\r
+ ((BASE) == TIM_DMABase_SMCR) || \\r
+ ((BASE) == TIM_DMABase_DIER) || \\r
+ ((BASE) == TIM_DMABase_SR) || \\r
+ ((BASE) == TIM_DMABase_EGR) || \\r
+ ((BASE) == TIM_DMABase_CCMR1) || \\r
+ ((BASE) == TIM_DMABase_CCMR2) || \\r
+ ((BASE) == TIM_DMABase_CCER) || \\r
+ ((BASE) == TIM_DMABase_CNT) || \\r
+ ((BASE) == TIM_DMABase_PSC) || \\r
+ ((BASE) == TIM_DMABase_ARR) || \\r
+ ((BASE) == TIM_DMABase_RCR) || \\r
+ ((BASE) == TIM_DMABase_CCR1) || \\r
+ ((BASE) == TIM_DMABase_CCR2) || \\r
+ ((BASE) == TIM_DMABase_CCR3) || \\r
+ ((BASE) == TIM_DMABase_CCR4) || \\r
+ ((BASE) == TIM_DMABase_BDTR) || \\r
+ ((BASE) == TIM_DMABase_DCR))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_Burst_Length \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)\r
+#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)\r
+#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)\r
+#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)\r
+#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)\r
+#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)\r
+#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)\r
+#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)\r
+#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)\r
+#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)\r
+#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)\r
+#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)\r
+#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)\r
+#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)\r
+#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)\r
+#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)\r
+#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)\r
+#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)\r
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \\r
+ ((LENGTH) == TIM_DMABurstLength_2Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_3Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_4Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_5Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_6Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_7Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_8Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_9Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_10Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_11Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_12Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_13Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_14Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_15Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_16Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_17Bytes) || \\r
+ ((LENGTH) == TIM_DMABurstLength_18Bytes))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_DMA_sources \r
+ * @{\r
+ */\r
+\r
+#define TIM_DMA_Update ((uint16_t)0x0100)\r
+#define TIM_DMA_CC1 ((uint16_t)0x0200)\r
+#define TIM_DMA_CC2 ((uint16_t)0x0400)\r
+#define TIM_DMA_CC3 ((uint16_t)0x0800)\r
+#define TIM_DMA_CC4 ((uint16_t)0x1000)\r
+#define TIM_DMA_COM ((uint16_t)0x2000)\r
+#define TIM_DMA_Trigger ((uint16_t)0x4000)\r
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Prescaler \r
+ * @{\r
+ */\r
+\r
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)\r
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)\r
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)\r
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)\r
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \\r
+ ((PRESCALER) == TIM_ExtTRGPSC_DIV8))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Internal_Trigger_Selection \r
+ * @{\r
+ */\r
+\r
+#define TIM_TS_ITR0 ((uint16_t)0x0000)\r
+#define TIM_TS_ITR1 ((uint16_t)0x0010)\r
+#define TIM_TS_ITR2 ((uint16_t)0x0020)\r
+#define TIM_TS_ITR3 ((uint16_t)0x0030)\r
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)\r
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)\r
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)\r
+#define TIM_TS_ETRF ((uint16_t)0x0070)\r
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3) || \\r
+ ((SELECTION) == TIM_TS_TI1F_ED) || \\r
+ ((SELECTION) == TIM_TS_TI1FP1) || \\r
+ ((SELECTION) == TIM_TS_TI2FP2) || \\r
+ ((SELECTION) == TIM_TS_ETRF))\r
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \\r
+ ((SELECTION) == TIM_TS_ITR1) || \\r
+ ((SELECTION) == TIM_TS_ITR2) || \\r
+ ((SELECTION) == TIM_TS_ITR3))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_TIx_External_Clock_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)\r
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)\r
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)\r
+#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \\r
+ ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Polarity \r
+ * @{\r
+ */ \r
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)\r
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)\r
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \\r
+ ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Prescaler_Reload_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)\r
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)\r
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \\r
+ ((RELOAD) == TIM_PSCReloadMode_Immediate))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Forced_Action \r
+ * @{\r
+ */\r
+\r
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)\r
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)\r
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \\r
+ ((ACTION) == TIM_ForcedAction_InActive))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Encoder_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)\r
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)\r
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)\r
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \\r
+ ((MODE) == TIM_EncoderMode_TI2) || \\r
+ ((MODE) == TIM_EncoderMode_TI12))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup TIM_Event_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_EventSource_Update ((uint16_t)0x0001)\r
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)\r
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)\r
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)\r
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)\r
+#define TIM_EventSource_COM ((uint16_t)0x0020)\r
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)\r
+#define TIM_EventSource_Break ((uint16_t)0x0080)\r
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Update_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller. */\r
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */\r
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \\r
+ ((SOURCE) == TIM_UpdateSource_Regular))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Preload_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)\r
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \\r
+ ((STATE) == TIM_OCPreload_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Fast_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCFast_Enable ((uint16_t)0x0004)\r
+#define TIM_OCFast_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \\r
+ ((STATE) == TIM_OCFast_Disable))\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Ouput_Compare_Clear_State \r
+ * @{\r
+ */\r
+\r
+#define TIM_OCClear_Enable ((uint16_t)0x0080)\r
+#define TIM_OCClear_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \\r
+ ((STATE) == TIM_OCClear_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Trigger_Output_Source \r
+ * @{\r
+ */\r
+\r
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)\r
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)\r
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)\r
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)\r
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)\r
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)\r
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)\r
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)\r
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \\r
+ ((SOURCE) == TIM_TRGOSource_Enable) || \\r
+ ((SOURCE) == TIM_TRGOSource_Update) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC1Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC2Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC3Ref) || \\r
+ ((SOURCE) == TIM_TRGOSource_OC4Ref))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)\r
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)\r
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)\r
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)\r
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \\r
+ ((MODE) == TIM_SlaveMode_Gated) || \\r
+ ((MODE) == TIM_SlaveMode_Trigger) || \\r
+ ((MODE) == TIM_SlaveMode_External1))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Master_Slave_Mode \r
+ * @{\r
+ */\r
+\r
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)\r
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)\r
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \\r
+ ((STATE) == TIM_MasterSlaveMode_Disable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Flags \r
+ * @{\r
+ */\r
+\r
+#define TIM_FLAG_Update ((uint16_t)0x0001)\r
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)\r
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)\r
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)\r
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)\r
+#define TIM_FLAG_COM ((uint16_t)0x0020)\r
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)\r
+#define TIM_FLAG_Break ((uint16_t)0x0080)\r
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)\r
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)\r
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)\r
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)\r
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \\r
+ ((FLAG) == TIM_FLAG_CC1) || \\r
+ ((FLAG) == TIM_FLAG_CC2) || \\r
+ ((FLAG) == TIM_FLAG_CC3) || \\r
+ ((FLAG) == TIM_FLAG_CC4) || \\r
+ ((FLAG) == TIM_FLAG_COM) || \\r
+ ((FLAG) == TIM_FLAG_Trigger) || \\r
+ ((FLAG) == TIM_FLAG_Break) || \\r
+ ((FLAG) == TIM_FLAG_CC1OF) || \\r
+ ((FLAG) == TIM_FLAG_CC2OF) || \\r
+ ((FLAG) == TIM_FLAG_CC3OF) || \\r
+ ((FLAG) == TIM_FLAG_CC4OF))\r
+ \r
+ \r
+#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Input_Capture_Filer_Value \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_External_Trigger_Filter \r
+ * @{\r
+ */\r
+\r
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup TIM_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void TIM_DeInit(TIM_TypeDef* TIMx);\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter);\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter);\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);\r
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__STM32F10x_TIM_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_usart.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the USART \r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_USART_H\r
+#define __STM32F10x_USART_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup USART\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Types\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief USART Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+ uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.\r
+ The baud rate is computed using the following formula:\r
+ - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))\r
+ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */\r
+\r
+ uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.\r
+ This parameter can be a value of @ref USART_Word_Length */\r
+\r
+ uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.\r
+ This parameter can be a value of @ref USART_Stop_Bits */\r
+\r
+ uint16_t USART_Parity; /*!< Specifies the parity mode.\r
+ This parameter can be a value of @ref USART_Parity\r
+ @note When parity is enabled, the computed parity is inserted\r
+ at the MSB position of the transmitted data (9th bit when\r
+ the word length is set to 9 data bits; 8th bit when the\r
+ word length is set to 8 data bits). */\r
+ \r
+ uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Mode */\r
+\r
+ uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled\r
+ or disabled.\r
+ This parameter can be a value of @ref USART_Hardware_Flow_Control */\r
+} USART_InitTypeDef;\r
+\r
+/** \r
+ * @brief USART Clock Init Structure definition \r
+ */ \r
+ \r
+typedef struct\r
+{\r
+\r
+ uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.\r
+ This parameter can be a value of @ref USART_Clock */\r
+\r
+ uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock.\r
+ This parameter can be a value of @ref USART_Clock_Polarity */\r
+\r
+ uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.\r
+ This parameter can be a value of @ref USART_Clock_Phase */\r
+\r
+ uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted\r
+ data bit (MSB) has to be output on the SCLK pin in synchronous mode.\r
+ This parameter can be a value of @ref USART_Last_Bit */\r
+} USART_ClockInitTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3) || \\r
+ ((PERIPH) == UART4) || \\r
+ ((PERIPH) == UART5))\r
+\r
+#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3))\r
+\r
+#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \\r
+ ((PERIPH) == USART2) || \\r
+ ((PERIPH) == USART3) || \\r
+ ((PERIPH) == UART4))\r
+/** @defgroup USART_Word_Length \r
+ * @{\r
+ */ \r
+ \r
+#define USART_WordLength_8b ((uint16_t)0x0000)\r
+#define USART_WordLength_9b ((uint16_t)0x1000)\r
+ \r
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \\r
+ ((LENGTH) == USART_WordLength_9b))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Stop_Bits \r
+ * @{\r
+ */ \r
+ \r
+#define USART_StopBits_1 ((uint16_t)0x0000)\r
+#define USART_StopBits_0_5 ((uint16_t)0x1000)\r
+#define USART_StopBits_2 ((uint16_t)0x2000)\r
+#define USART_StopBits_1_5 ((uint16_t)0x3000)\r
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \\r
+ ((STOPBITS) == USART_StopBits_0_5) || \\r
+ ((STOPBITS) == USART_StopBits_2) || \\r
+ ((STOPBITS) == USART_StopBits_1_5))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Parity \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Parity_No ((uint16_t)0x0000)\r
+#define USART_Parity_Even ((uint16_t)0x0400)\r
+#define USART_Parity_Odd ((uint16_t)0x0600) \r
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \\r
+ ((PARITY) == USART_Parity_Even) || \\r
+ ((PARITY) == USART_Parity_Odd))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Mode \r
+ * @{\r
+ */ \r
+ \r
+#define USART_Mode_Rx ((uint16_t)0x0004)\r
+#define USART_Mode_Tx ((uint16_t)0x0008)\r
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Hardware_Flow_Control \r
+ * @{\r
+ */ \r
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)\r
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)\r
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)\r
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)\r
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\\r
+ (((CONTROL) == USART_HardwareFlowControl_None) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_CTS) || \\r
+ ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock \r
+ * @{\r
+ */ \r
+#define USART_Clock_Disable ((uint16_t)0x0000)\r
+#define USART_Clock_Enable ((uint16_t)0x0800)\r
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \\r
+ ((CLOCK) == USART_Clock_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Polarity \r
+ * @{\r
+ */\r
+ \r
+#define USART_CPOL_Low ((uint16_t)0x0000)\r
+#define USART_CPOL_High ((uint16_t)0x0400)\r
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Clock_Phase\r
+ * @{\r
+ */\r
+\r
+#define USART_CPHA_1Edge ((uint16_t)0x0000)\r
+#define USART_CPHA_2Edge ((uint16_t)0x0200)\r
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Last_Bit\r
+ * @{\r
+ */\r
+\r
+#define USART_LastBit_Disable ((uint16_t)0x0000)\r
+#define USART_LastBit_Enable ((uint16_t)0x0100)\r
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \\r
+ ((LASTBIT) == USART_LastBit_Enable))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Interrupt_definition \r
+ * @{\r
+ */\r
+ \r
+#define USART_IT_PE ((uint16_t)0x0028)\r
+#define USART_IT_TXE ((uint16_t)0x0727)\r
+#define USART_IT_TC ((uint16_t)0x0626)\r
+#define USART_IT_RXNE ((uint16_t)0x0525)\r
+#define USART_IT_IDLE ((uint16_t)0x0424)\r
+#define USART_IT_LBD ((uint16_t)0x0846)\r
+#define USART_IT_CTS ((uint16_t)0x096A)\r
+#define USART_IT_ERR ((uint16_t)0x0060)\r
+#define USART_IT_ORE ((uint16_t)0x0360)\r
+#define USART_IT_NE ((uint16_t)0x0260)\r
+#define USART_IT_FE ((uint16_t)0x0160)\r
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))\r
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \\r
+ ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \\r
+ ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \\r
+ ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))\r
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \\r
+ ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_DMA_Requests \r
+ * @{\r
+ */\r
+\r
+#define USART_DMAReq_Tx ((uint16_t)0x0080)\r
+#define USART_DMAReq_Rx ((uint16_t)0x0040)\r
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_WakeUp_methods\r
+ * @{\r
+ */\r
+\r
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)\r
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)\r
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \\r
+ ((WAKEUP) == USART_WakeUp_AddressMark))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_LIN_Break_Detection_Length \r
+ * @{\r
+ */\r
+ \r
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)\r
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)\r
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \\r
+ (((LENGTH) == USART_LINBreakDetectLength_10b) || \\r
+ ((LENGTH) == USART_LINBreakDetectLength_11b))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_IrDA_Low_Power \r
+ * @{\r
+ */\r
+\r
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)\r
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)\r
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \\r
+ ((MODE) == USART_IrDAMode_Normal))\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Flags \r
+ * @{\r
+ */\r
+\r
+#define USART_FLAG_CTS ((uint16_t)0x0200)\r
+#define USART_FLAG_LBD ((uint16_t)0x0100)\r
+#define USART_FLAG_TXE ((uint16_t)0x0080)\r
+#define USART_FLAG_TC ((uint16_t)0x0040)\r
+#define USART_FLAG_RXNE ((uint16_t)0x0020)\r
+#define USART_FLAG_IDLE ((uint16_t)0x0010)\r
+#define USART_FLAG_ORE ((uint16_t)0x0008)\r
+#define USART_FLAG_NE ((uint16_t)0x0004)\r
+#define USART_FLAG_FE ((uint16_t)0x0002)\r
+#define USART_FLAG_PE ((uint16_t)0x0001)\r
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \\r
+ ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \\r
+ ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \\r
+ ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \\r
+ ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))\r
+ \r
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))\r
+#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\\r
+ ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \\r
+ || ((USART_FLAG) != USART_FLAG_CTS)) \r
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21))\r
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)\r
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup USART_Exported_Functions\r
+ * @{\r
+ */\r
+\r
+void USART_DeInit(USART_TypeDef* USARTx);\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);\r
+void USART_SendBreak(USART_TypeDef* USARTx);\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_USART_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_wwdg.h\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file contains all the functions prototypes for the WWDG firmware\r
+ * library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32F10x_WWDG_H\r
+#define __STM32F10x_WWDG_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup WWDG\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Types\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Constants\r
+ * @{\r
+ */ \r
+ \r
+/** @defgroup WWDG_Prescaler \r
+ * @{\r
+ */ \r
+ \r
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)\r
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)\r
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)\r
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)\r
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \\r
+ ((PRESCALER) == WWDG_Prescaler_2) || \\r
+ ((PRESCALER) == WWDG_Prescaler_4) || \\r
+ ((PRESCALER) == WWDG_Prescaler_8))\r
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)\r
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup WWDG_Exported_Functions\r
+ * @{\r
+ */ \r
+ \r
+void WWDG_DeInit(void);\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);\r
+void WWDG_SetWindowValue(uint8_t WindowValue);\r
+void WWDG_EnableIT(void);\r
+void WWDG_SetCounter(uint8_t Counter);\r
+void WWDG_Enable(uint8_t Counter);\r
+FlagStatus WWDG_GetFlagStatus(void);\r
+void WWDG_ClearFlag(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32F10x_WWDG_H */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
******************************************************************************\r
* @file misc.c\r
* @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
* @brief This file provides all the miscellaneous firmware functions (add-on\r
* to CMSIS functions).\r
******************************************************************************\r
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
*\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
*/ \r
\r
/* Includes ------------------------------------------------------------------*/\r
#include "misc.h"\r
\r
-#define assert_param(expr) ((void)0)\r
-\r
/** @addtogroup STM32F10x_StdPeriph_Driver\r
* @{\r
*/\r
* @}\r
*/\r
\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_adc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the ADC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_adc.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC \r
+ * @brief ADC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ADC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ADC DISCNUM mask */\r
+#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)\r
+\r
+/* ADC DISCEN mask */\r
+#define CR1_DISCEN_Set ((uint32_t)0x00000800)\r
+#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)\r
+\r
+/* ADC JAUTO mask */\r
+#define CR1_JAUTO_Set ((uint32_t)0x00000400)\r
+#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)\r
+\r
+/* ADC JDISCEN mask */\r
+#define CR1_JDISCEN_Set ((uint32_t)0x00001000)\r
+#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)\r
+\r
+/* ADC AWDCH mask */\r
+#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)\r
+\r
+/* ADC Analog watchdog enable mode mask */\r
+#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)\r
+\r
+/* CR1 register Mask */\r
+#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)\r
+\r
+/* ADC ADON mask */\r
+#define CR2_ADON_Set ((uint32_t)0x00000001)\r
+#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE)\r
+\r
+/* ADC DMA mask */\r
+#define CR2_DMA_Set ((uint32_t)0x00000100)\r
+#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF)\r
+\r
+/* ADC RSTCAL mask */\r
+#define CR2_RSTCAL_Set ((uint32_t)0x00000008)\r
+\r
+/* ADC CAL mask */\r
+#define CR2_CAL_Set ((uint32_t)0x00000004)\r
+\r
+/* ADC SWSTART mask */\r
+#define CR2_SWSTART_Set ((uint32_t)0x00400000)\r
+\r
+/* ADC EXTTRIG mask */\r
+#define CR2_EXTTRIG_Set ((uint32_t)0x00100000)\r
+#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)\r
+\r
+/* ADC Software start mask */\r
+#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)\r
+#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)\r
+\r
+/* ADC JEXTSEL mask */\r
+#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)\r
+\r
+/* ADC JEXTTRIG mask */\r
+#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000)\r
+#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)\r
+\r
+/* ADC JSWSTART mask */\r
+#define CR2_JSWSTART_Set ((uint32_t)0x00200000)\r
+\r
+/* ADC injected software start mask */\r
+#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)\r
+#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)\r
+\r
+/* ADC TSPD mask */\r
+#define CR2_TSVREFE_Set ((uint32_t)0x00800000)\r
+#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)\r
+\r
+/* CR2 register Mask */\r
+#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)\r
+\r
+/* ADC SQx mask */\r
+#define SQR3_SQ_Set ((uint32_t)0x0000001F)\r
+#define SQR2_SQ_Set ((uint32_t)0x0000001F)\r
+#define SQR1_SQ_Set ((uint32_t)0x0000001F)\r
+\r
+/* SQR1 register Mask */\r
+#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)\r
+\r
+/* ADC JSQx mask */\r
+#define JSQR_JSQ_Set ((uint32_t)0x0000001F)\r
+\r
+/* ADC JL mask */\r
+#define JSQR_JL_Set ((uint32_t)0x00300000)\r
+#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF)\r
+\r
+/* ADC SMPx mask */\r
+#define SMPR1_SMP_Set ((uint32_t)0x00000007)\r
+#define SMPR2_SMP_Set ((uint32_t)0x00000007)\r
+\r
+/* ADC JDRx registers offset */\r
+#define JDR_Offset ((uint8_t)0x28)\r
+\r
+/* ADC1 DR register base address */\r
+#define DR_ADDRESS ((uint32_t)0x4001244C)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ADC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the ADCx peripheral registers to their default reset values.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_DeInit(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ \r
+ if (ADCx == ADC1)\r
+ {\r
+ /* Enable ADC1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);\r
+ /* Release ADC1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);\r
+ }\r
+ else if (ADCx == ADC2)\r
+ {\r
+ /* Enable ADC2 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE);\r
+ /* Release ADC2 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (ADCx == ADC3)\r
+ {\r
+ /* Enable ADC3 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE);\r
+ /* Release ADC3 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ADCx peripheral according to the specified parameters\r
+ * in the ADC_InitStruct.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains\r
+ * the configuration information for the specified ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint8_t tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));\r
+ assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));\r
+ assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); \r
+ assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); \r
+ assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));\r
+\r
+ /*---------------------------- ADCx CR1 Configuration -----------------*/\r
+ /* Get the ADCx CR1 value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear DUALMOD and SCAN bits */\r
+ tmpreg1 &= CR1_CLEAR_Mask;\r
+ /* Configure ADCx: Dual mode and scan conversion mode */\r
+ /* Set DUALMOD bits according to ADC_Mode value */\r
+ /* Set SCAN bit according to ADC_ScanConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));\r
+ /* Write to ADCx CR1 */\r
+ ADCx->CR1 = tmpreg1;\r
+\r
+ /*---------------------------- ADCx CR2 Configuration -----------------*/\r
+ /* Get the ADCx CR2 value */\r
+ tmpreg1 = ADCx->CR2;\r
+ /* Clear CONT, ALIGN and EXTSEL bits */\r
+ tmpreg1 &= CR2_CLEAR_Mask;\r
+ /* Configure ADCx: external trigger event and continuous conversion mode */\r
+ /* Set ALIGN bit according to ADC_DataAlign value */\r
+ /* Set EXTSEL bits according to ADC_ExternalTrigConv value */\r
+ /* Set CONT bit according to ADC_ContinuousConvMode value */\r
+ tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |\r
+ ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));\r
+ /* Write to ADCx CR2 */\r
+ ADCx->CR2 = tmpreg1;\r
+\r
+ /*---------------------------- ADCx SQR1 Configuration -----------------*/\r
+ /* Get the ADCx SQR1 value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Clear L bits */\r
+ tmpreg1 &= SQR1_CLEAR_Mask;\r
+ /* Configure ADCx: regular channel sequence length */\r
+ /* Set L bits according to ADC_NbrOfChannel value */\r
+ tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);\r
+ tmpreg1 |= (uint32_t)tmpreg2 << 20;\r
+ /* Write to ADCx SQR1 */\r
+ ADCx->SQR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ADC_InitStruct member with its default value.\r
+ * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)\r
+{\r
+ /* Reset ADC init structure parameters values */\r
+ /* Initialize the ADC_Mode member */\r
+ ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;\r
+ /* initialize the ADC_ScanConvMode member */\r
+ ADC_InitStruct->ADC_ScanConvMode = DISABLE;\r
+ /* Initialize the ADC_ContinuousConvMode member */\r
+ ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;\r
+ /* Initialize the ADC_ExternalTrigConv member */\r
+ ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;\r
+ /* Initialize the ADC_DataAlign member */\r
+ ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;\r
+ /* Initialize the ADC_NbrOfChannel member */\r
+ ADC_InitStruct->ADC_NbrOfChannel = 1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC peripheral.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the ADCx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ADON bit to wake up the ADC from power down mode */\r
+ ADCx->CR2 |= CR2_ADON_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC peripheral */\r
+ ADCx->CR2 &= CR2_ADON_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC DMA request.\r
+ * @param ADCx: where x can be 1 or 3 to select the ADC peripheral.\r
+ * Note: ADC2 hasn't a DMA capability.\r
+ * @param NewState: new state of the selected ADC DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_DMA_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC DMA request */\r
+ ADCx->CR2 |= CR2_DMA_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC DMA request */\r
+ ADCx->CR2 &= CR2_DMA_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ADC interrupts.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt mask\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
+ * @param NewState: new state of the specified ADC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)\r
+{\r
+ uint8_t itmask = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)ADC_IT;\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC interrupts */\r
+ ADCx->CR1 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC interrupts */\r
+ ADCx->CR1 &= (~(uint32_t)itmask);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Resets the selected ADC calibration registers.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_ResetCalibration(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Resets the selected ADC calibartion registers */ \r
+ ADCx->CR2 |= CR2_RSTCAL_Set;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC reset calibration registers status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC reset calibration registers (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of RSTCAL bit */\r
+ if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET)\r
+ {\r
+ /* RSTCAL bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* RSTCAL bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the RSTCAL bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Starts the selected ADC calibration process.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval None\r
+ */\r
+void ADC_StartCalibration(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Enable the selected ADC calibration process */ \r
+ ADCx->CR2 |= CR2_CAL_Set;\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC calibration status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC calibration (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of CAL bit */\r
+ if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET)\r
+ {\r
+ /* CAL bit is set: calibration on going */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAL bit is reset: end of calibration */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CAL bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC software start conversion .\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC software start conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion on external event and start the selected\r
+ ADC conversion */\r
+ ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC conversion on external event and stop the selected\r
+ ADC conversion */\r
+ ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start conversion Status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC software start conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of SWSTART bit */\r
+ if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET)\r
+ {\r
+ /* SWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Configures the discontinuous mode for the selected ADC regular\r
+ * group channel.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param Number: specifies the discontinuous mode regular channel\r
+ * count value. This number must be between 1 and 8.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->CR1;\r
+ /* Clear the old discontinuous mode channel count */\r
+ tmpreg1 &= CR1_DISCNUM_Reset;\r
+ /* Set the discontinuous mode channel count */\r
+ tmpreg2 = Number - 1;\r
+ tmpreg1 |= tmpreg2 << 13;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode on regular group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on regular group channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 |= CR1_DISCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC regular discontinuous mode */\r
+ ADCx->CR1 &= CR1_DISCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures for the selected ADC regular channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
+ * @retval None\r
+ */\r
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_REGULAR_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
+ if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10));\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ /* For Rank 1 to 6 */\r
+ if (Rank < 7)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR3;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR3 = tmpreg1;\r
+ }\r
+ /* For Rank 7 to 12 */\r
+ else if (Rank < 13)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR2 = tmpreg1;\r
+ }\r
+ /* For Rank 13 to 16 */\r
+ else\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SQR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13));\r
+ /* Clear the old SQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));\r
+ /* Set the SQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SQR1 = tmpreg1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADCx conversion through external trigger.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC external trigger start of conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion on external event */\r
+ ADCx->CR2 |= CR2_EXTTRIG_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC conversion on external event */\r
+ ADCx->CR2 &= CR2_EXTTRIG_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADCx conversion result data for regular channel.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Return the selected ADC conversion value */\r
+ return (uint16_t) ADCx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode.\r
+ * @retval The Data conversion value.\r
+ */\r
+uint32_t ADC_GetDualModeConversionValue(void)\r
+{\r
+ /* Return the dual mode conversion value */\r
+ return (*(__IO uint32_t *) DR_ADDRESS);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC automatic injected group\r
+ * conversion after regular one.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC auto injected conversion\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 |= CR1_JAUTO_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC automatic injected group conversion */\r
+ ADCx->CR1 &= CR1_JAUTO_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the discontinuous mode for injected group\r
+ * channel for the specified ADC\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC discontinuous mode\r
+ * on injected group channel.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 |= CR1_JDISCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC injected discontinuous mode */\r
+ ADCx->CR1 &= CR1_JDISCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the ADCx external trigger for injected channels conversion.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3)\r
+ * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3)\r
+ * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2)\r
+ * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8\r
+ * capture compare4 event selected (for ADC1 and ADC2) \r
+ * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only)\r
+ * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) \r
+ * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only)\r
+ * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) \r
+ * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) \r
+ * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not\r
+ * by external trigger (for ADC1, ADC2 and ADC3)\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR2;\r
+ /* Clear the old external event selection for injected group */\r
+ tmpreg &= CR2_JEXTSEL_Reset;\r
+ /* Set the external event selection for injected group */\r
+ tmpreg |= ADC_ExternalTrigInjecConv;\r
+ /* Store the new register value */\r
+ ADCx->CR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the ADCx injected channels conversion through\r
+ * external trigger\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC external trigger start of\r
+ * injected conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC external event selection for injected group */\r
+ ADCx->CR2 |= CR2_JEXTTRIG_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC external event selection for injected group */\r
+ ADCx->CR2 &= CR2_JEXTTRIG_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected ADC start of the injected \r
+ * channels conversion.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param NewState: new state of the selected ADC software start injected conversion.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ADC conversion for injected group on external event and start the selected\r
+ ADC injected conversion */\r
+ ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ADC conversion on external event for injected group and stop the selected\r
+ ADC injected conversion */\r
+ ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Gets the selected ADC Software start injected conversion Status.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @retval The new state of ADC software start injected conversion (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ /* Check the status of JSWSTART bit */\r
+ if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET)\r
+ {\r
+ /* JSWSTART bit is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* JSWSTART bit is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the JSWSTART bit status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Configures for the selected ADC injected channel its corresponding\r
+ * rank in the sequencer and its sample time.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4.\r
+ * @param ADC_SampleTime: The sample time value to be set for the selected channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles\r
+ * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles\r
+ * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles\r
+ * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles \r
+ * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles \r
+ * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles \r
+ * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles \r
+ * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles \r
+ * @retval None\r
+ */\r
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ assert_param(IS_ADC_INJECTED_RANK(Rank));\r
+ assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));\r
+ /* if ADC_Channel_10 ... ADC_Channel_17 is selected */\r
+ if (ADC_Channel > ADC_Channel_9)\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR1;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR1 = tmpreg1;\r
+ }\r
+ else /* ADC_Channel include in ADC_Channel_[0..9] */\r
+ {\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->SMPR2;\r
+ /* Calculate the mask to clear */\r
+ tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);\r
+ /* Clear the old channel sample time */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set */\r
+ tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);\r
+ /* Set the new channel sample time */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->SMPR2 = tmpreg1;\r
+ }\r
+ /* Rank configuration */\r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Get JL value: Number = JL+1 */\r
+ tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20;\r
+ /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */\r
+ tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Clear the old JSQx bits for the selected rank */\r
+ tmpreg1 &= ~tmpreg2;\r
+ /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */\r
+ tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));\r
+ /* Set the JSQx bits for the selected rank */\r
+ tmpreg1 |= tmpreg2;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the sequencer length for injected channels\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param Length: The sequencer length. \r
+ * This parameter must be a number between 1 to 4.\r
+ * @retval None\r
+ */\r
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)\r
+{\r
+ uint32_t tmpreg1 = 0;\r
+ uint32_t tmpreg2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_LENGTH(Length));\r
+ \r
+ /* Get the old register value */\r
+ tmpreg1 = ADCx->JSQR;\r
+ /* Clear the old injected sequnence lenght JL bits */\r
+ tmpreg1 &= JSQR_JL_Reset;\r
+ /* Set the injected sequnence lenght JL bits */\r
+ tmpreg2 = Length - 1; \r
+ tmpreg1 |= tmpreg2 << 20;\r
+ /* Store the new register value */\r
+ ADCx->JSQR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Set the injected channels conversion value offset\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_InjectedChannel: the ADC injected channel to set its offset. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @param Offset: the offset value for the selected ADC injected channel\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+ assert_param(IS_ADC_OFFSET(Offset)); \r
+ \r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel;\r
+ \r
+ /* Set the selected injected channel data offset */\r
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;\r
+}\r
+\r
+/**\r
+ * @brief Returns the ADC injected channel conversion result\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_InjectedChannel: the converted ADC injected channel.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_InjectedChannel_1: Injected Channel1 selected\r
+ * @arg ADC_InjectedChannel_2: Injected Channel2 selected\r
+ * @arg ADC_InjectedChannel_3: Injected Channel3 selected\r
+ * @arg ADC_InjectedChannel_4: Injected Channel4 selected\r
+ * @retval The Data conversion value.\r
+ */\r
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));\r
+\r
+ tmp = (uint32_t)ADCx;\r
+ tmp += ADC_InjectedChannel + JDR_Offset;\r
+ \r
+ /* Returns the selected injected channel conversion data value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp); \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the analog watchdog on single/all regular\r
+ * or injected channels\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration.\r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel\r
+ * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel\r
+ * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel\r
+ * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel\r
+ * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel\r
+ * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels\r
+ * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog\r
+ * @retval None \r
+ */\r
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear AWDEN, AWDENJ and AWDSGL bits */\r
+ tmpreg &= CR1_AWDMode_Reset;\r
+ /* Set the analog watchdog enable mode */\r
+ tmpreg |= ADC_AnalogWatchdog;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the high and low thresholds of the analog watchdog.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param HighThreshold: the ADC analog watchdog High threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @param LowThreshold: the ADC analog watchdog Low threshold value.\r
+ * This parameter must be a 12bit value.\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,\r
+ uint16_t LowThreshold)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_THRESHOLD(HighThreshold));\r
+ assert_param(IS_ADC_THRESHOLD(LowThreshold));\r
+ /* Set the ADCx high threshold */\r
+ ADCx->HTR = HighThreshold;\r
+ /* Set the ADCx low threshold */\r
+ ADCx->LTR = LowThreshold;\r
+}\r
+\r
+/**\r
+ * @brief Configures the analog watchdog guarded single channel\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_Channel: the ADC channel to configure for the analog watchdog. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_Channel_0: ADC Channel0 selected\r
+ * @arg ADC_Channel_1: ADC Channel1 selected\r
+ * @arg ADC_Channel_2: ADC Channel2 selected\r
+ * @arg ADC_Channel_3: ADC Channel3 selected\r
+ * @arg ADC_Channel_4: ADC Channel4 selected\r
+ * @arg ADC_Channel_5: ADC Channel5 selected\r
+ * @arg ADC_Channel_6: ADC Channel6 selected\r
+ * @arg ADC_Channel_7: ADC Channel7 selected\r
+ * @arg ADC_Channel_8: ADC Channel8 selected\r
+ * @arg ADC_Channel_9: ADC Channel9 selected\r
+ * @arg ADC_Channel_10: ADC Channel10 selected\r
+ * @arg ADC_Channel_11: ADC Channel11 selected\r
+ * @arg ADC_Channel_12: ADC Channel12 selected\r
+ * @arg ADC_Channel_13: ADC Channel13 selected\r
+ * @arg ADC_Channel_14: ADC Channel14 selected\r
+ * @arg ADC_Channel_15: ADC Channel15 selected\r
+ * @arg ADC_Channel_16: ADC Channel16 selected\r
+ * @arg ADC_Channel_17: ADC Channel17 selected\r
+ * @retval None\r
+ */\r
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CHANNEL(ADC_Channel));\r
+ /* Get the old register value */\r
+ tmpreg = ADCx->CR1;\r
+ /* Clear the Analog watchdog channel select bits */\r
+ tmpreg &= CR1_AWDCH_Reset;\r
+ /* Set the Analog watchdog channel */\r
+ tmpreg |= ADC_Channel;\r
+ /* Store the new register value */\r
+ ADCx->CR1 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the temperature sensor and Vrefint channel.\r
+ * @param NewState: new state of the temperature sensor.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the temperature sensor and Vrefint channel*/\r
+ ADC1->CR2 |= CR2_TSVREFE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the temperature sensor and Vrefint channel*/\r
+ ADC1->CR2 &= CR2_TSVREFE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC flag is set or not.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @retval The new state of ADC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_FLAG(ADC_FLAG));\r
+ /* Check the status of the specified ADC flag */\r
+ if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)\r
+ {\r
+ /* ADC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx's pending flags.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_FLAG_AWD: Analog watchdog flag\r
+ * @arg ADC_FLAG_EOC: End of conversion flag\r
+ * @arg ADC_FLAG_JEOC: End of injected group conversion flag\r
+ * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag\r
+ * @arg ADC_FLAG_STRT: Start of regular group conversion flag\r
+ * @retval None\r
+ */\r
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));\r
+ /* Clear the selected ADC flags */\r
+ ADCx->SR = ~(uint32_t)ADC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ADC interrupt has occurred or not.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt mask\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
+ * @retval The new state of ADC_IT (SET or RESET).\r
+ */\r
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t itmask = 0, enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_GET_IT(ADC_IT));\r
+ /* Get the ADC IT index */\r
+ itmask = ADC_IT >> 8;\r
+ /* Get the ADC_IT enable bit status */\r
+ enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ;\r
+ /* Check the status of the specified ADC interrupt */\r
+ if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* ADC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* ADC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the ADC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ADCx\92s interrupt pending bits.\r
+ * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.\r
+ * @param ADC_IT: specifies the ADC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ADC_IT_EOC: End of conversion interrupt mask\r
+ * @arg ADC_IT_AWD: Analog watchdog interrupt mask\r
+ * @arg ADC_IT_JEOC: End of injected conversion interrupt mask\r
+ * @retval None\r
+ */\r
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)\r
+{\r
+ uint8_t itmask = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ADC_ALL_PERIPH(ADCx));\r
+ assert_param(IS_ADC_IT(ADC_IT));\r
+ /* Get the ADC IT index */\r
+ itmask = (uint8_t)(ADC_IT >> 8);\r
+ /* Clear the selected ADC interrupt pending bits */\r
+ ADCx->SR = ~(uint32_t)itmask;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_bkp.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the BKP firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_bkp.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup BKP \r
+ * @brief BKP driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup BKP_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ BKP registers bit address in the alias region --------------- */\r
+#define BKP_OFFSET (BKP_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ----*/\r
+\r
+/* Alias word address of TPAL bit */\r
+#define CR_OFFSET (BKP_OFFSET + 0x30)\r
+#define TPAL_BitNumber 0x01\r
+#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4))\r
+\r
+/* Alias word address of TPE bit */\r
+#define TPE_BitNumber 0x00\r
+#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of TPIE bit */\r
+#define CSR_OFFSET (BKP_OFFSET + 0x34)\r
+#define TPIE_BitNumber 0x02\r
+#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4))\r
+\r
+/* Alias word address of TIF bit */\r
+#define TIF_BitNumber 0x09\r
+#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4))\r
+\r
+/* Alias word address of TEF bit */\r
+#define TEF_BitNumber 0x08\r
+#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4))\r
+\r
+/* ---------------------- BKP registers bit mask ------------------------ */\r
+\r
+/* RTCCR register bit mask */\r
+#define RTCCR_CAL_MASK ((uint16_t)0xFF80)\r
+#define RTCCR_MASK ((uint16_t)0xFC7F)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup BKP_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup BKP_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the BKP peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BKP_DeInit(void)\r
+{\r
+ RCC_BackupResetCmd(ENABLE);\r
+ RCC_BackupResetCmd(DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Configures the Tamper Pin active level.\r
+ * @param BKP_TamperPinLevel: specifies the Tamper Pin active level.\r
+ * This parameter can be one of the following values:\r
+ * @arg BKP_TamperPinLevel_High: Tamper pin active on high level\r
+ * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level\r
+ * @retval None\r
+ */\r
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel));\r
+ *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Tamper Pin activation.\r
+ * @param NewState: new state of the Tamper Pin activation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void BKP_TamperPinCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Tamper Pin Interrupt.\r
+ * @param NewState: new state of the Tamper Pin Interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void BKP_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Select the RTC output source to output on the Tamper pin.\r
+ * @param BKP_RTCOutputSource: specifies the RTC output source.\r
+ * This parameter can be one of the following values:\r
+ * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin.\r
+ * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency\r
+ * divided by 64 on the Tamper pin.\r
+ * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on\r
+ * the Tamper pin.\r
+ * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on\r
+ * the Tamper pin. \r
+ * @retval None\r
+ */\r
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource));\r
+ tmpreg = BKP->RTCCR;\r
+ /* Clear CCO, ASOE and ASOS bits */\r
+ tmpreg &= RTCCR_MASK;\r
+ \r
+ /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */\r
+ tmpreg |= BKP_RTCOutputSource;\r
+ /* Store the new value */\r
+ BKP->RTCCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets RTC Clock Calibration value.\r
+ * @param CalibrationValue: specifies the RTC Clock Calibration value.\r
+ * This parameter must be a number between 0 and 0x7F.\r
+ * @retval None\r
+ */\r
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue));\r
+ tmpreg = BKP->RTCCR;\r
+ /* Clear CAL[6:0] bits */\r
+ tmpreg &= RTCCR_CAL_MASK;\r
+ /* Set CAL[6:0] bits according to CalibrationValue value */\r
+ tmpreg |= CalibrationValue;\r
+ /* Store the new value */\r
+ BKP->RTCCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Writes user data to the specified Data Backup Register.\r
+ * @param BKP_DR: specifies the Data Backup Register.\r
+ * This parameter can be BKP_DRx where x:[1, 42]\r
+ * @param Data: data to write\r
+ * @retval None\r
+ */\r
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_DR(BKP_DR));\r
+\r
+ tmp = (uint32_t)BKP_BASE; \r
+ tmp += BKP_DR;\r
+\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Reads data from the specified Data Backup Register.\r
+ * @param BKP_DR: specifies the Data Backup Register.\r
+ * This parameter can be BKP_DRx where x:[1, 42]\r
+ * @retval The content of the specified Data Backup Register\r
+ */\r
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_BKP_DR(BKP_DR));\r
+\r
+ tmp = (uint32_t)BKP_BASE; \r
+ tmp += BKP_DR;\r
+\r
+ return (*(__IO uint16_t *) tmp);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the Tamper Pin Event flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Tamper Pin Event flag (SET or RESET).\r
+ */\r
+FlagStatus BKP_GetFlagStatus(void)\r
+{\r
+ return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB);\r
+}\r
+\r
+/**\r
+ * @brief Clears Tamper Pin Event pending flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BKP_ClearFlag(void)\r
+{\r
+ /* Set CTE bit to clear Tamper Pin Event flag */\r
+ BKP->CSR |= BKP_CSR_CTE;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the Tamper Pin Interrupt has occurred or not.\r
+ * @param None\r
+ * @retval The new state of the Tamper Pin Interrupt (SET or RESET).\r
+ */\r
+ITStatus BKP_GetITStatus(void)\r
+{\r
+ return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB);\r
+}\r
+\r
+/**\r
+ * @brief Clears Tamper Pin Interrupt pending bit.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void BKP_ClearITPendingBit(void)\r
+{\r
+ /* Set CTI bit to clear Tamper Pin Interrupt pending bit */\r
+ BKP->CSR |= BKP_CSR_CTI;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_can.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the CAN firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_can.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CAN \r
+ * @brief CAN driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup CAN_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* CAN Master Control Register bits */\r
+\r
+#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */\r
+\r
+/* CAN Mailbox Transmit Request */\r
+#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */\r
+\r
+/* CAN Filter Master Register bits */\r
+#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */\r
+\r
+/* Time out for INAK bit */\r
+#define INAK_TIMEOUT ((uint32_t)0x0000FFFF)\r
+/* Time out for SLAK bit */\r
+#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)\r
+\r
+\r
+\r
+/* Flags in TSR register */\r
+#define CAN_FLAGS_TSR ((uint32_t)0x08000000) \r
+/* Flags in RF1R register */\r
+#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) \r
+/* Flags in RF0R register */\r
+#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) \r
+/* Flags in MSR register */\r
+#define CAN_FLAGS_MSR ((uint32_t)0x01000000) \r
+/* Flags in ESR register */\r
+#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CAN_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the CAN peripheral registers to their default reset values.\r
+ * @param CANx: where x can be 1 or 2 to select the CAN peripheral.\r
+ * @retval None.\r
+ */\r
+void CAN_DeInit(CAN_TypeDef* CANx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ if (CANx == CAN1)\r
+ {\r
+ /* Enable CAN1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);\r
+ /* Release CAN1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);\r
+ }\r
+ else\r
+ { \r
+ /* Enable CAN2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);\r
+ /* Release CAN2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_InitStruct.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that\r
+ * contains the configuration information for the CAN peripheral.\r
+ * @retval Constant indicates initialization succeed which will be \r
+ * CANINITFAILED or CANINITOK.\r
+ */\r
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ uint8_t InitStatus = CANINITFAILED;\r
+ uint32_t wait_ack = 0x00000000;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));\r
+ assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));\r
+ assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));\r
+ assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));\r
+ assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));\r
+ assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));\r
+\r
+ /* exit from sleep mode */\r
+ CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);\r
+\r
+ /* Request initialisation */\r
+ CANx->MCR |= CAN_MCR_INRQ ;\r
+\r
+ /* Wait the acknowledge */\r
+ while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r
+ {\r
+ wait_ack++;\r
+ }\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else \r
+ {\r
+ /* Set the time triggered communication mode */\r
+ if (CAN_InitStruct->CAN_TTCM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_TTCM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;\r
+ }\r
+\r
+ /* Set the automatic bus-off management */\r
+ if (CAN_InitStruct->CAN_ABOM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_ABOM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;\r
+ }\r
+\r
+ /* Set the automatic wake-up mode */\r
+ if (CAN_InitStruct->CAN_AWUM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_AWUM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;\r
+ }\r
+\r
+ /* Set the no automatic retransmission */\r
+ if (CAN_InitStruct->CAN_NART == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_NART;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_NART;\r
+ }\r
+\r
+ /* Set the receive FIFO locked mode */\r
+ if (CAN_InitStruct->CAN_RFLM == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_RFLM;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;\r
+ }\r
+\r
+ /* Set the transmit FIFO priority */\r
+ if (CAN_InitStruct->CAN_TXFP == ENABLE)\r
+ {\r
+ CANx->MCR |= CAN_MCR_TXFP;\r
+ }\r
+ else\r
+ {\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;\r
+ }\r
+\r
+ /* Set the bit timing register */\r
+ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) |\r
+ ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) |\r
+ ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);\r
+\r
+ /* Request leave initialisation */\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;\r
+\r
+ /* Wait the acknowledge */\r
+ wait_ack = 0x00;\r
+\r
+ while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))\r
+ {\r
+ wait_ack++;\r
+ }\r
+\r
+ /* ...and check acknowledged */\r
+ if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)\r
+ {\r
+ InitStatus = CANINITFAILED;\r
+ }\r
+ else\r
+ {\r
+ InitStatus = CANINITOK ;\r
+ }\r
+ }\r
+\r
+ /* At this step, return the status of initialization */\r
+ return InitStatus;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the CAN peripheral according to the specified\r
+ * parameters in the CAN_FilterInitStruct.\r
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef\r
+ * structure that contains the configuration information.\r
+ * @retval None.\r
+ */\r
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)\r
+{\r
+ uint32_t filter_number_bit_pos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));\r
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));\r
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));\r
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));\r
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));\r
+\r
+ filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber;\r
+\r
+ /* Initialisation mode for the filter */\r
+ CAN1->FMR |= FMR_FINIT;\r
+\r
+ /* Filter Deactivation */\r
+ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;\r
+\r
+ /* Filter Scale */\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)\r
+ {\r
+ /* 16-bit scale for the filter */\r
+ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;\r
+\r
+ /* First 16-bit identifier and First 16-bit mask */\r
+ /* Or First 16-bit identifier and Second 16-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
+\r
+ /* Second 16-bit identifier and Second 16-bit mask */\r
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);\r
+ }\r
+\r
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)\r
+ {\r
+ /* 32-bit scale for the filter */\r
+ CAN1->FS1R |= filter_number_bit_pos;\r
+ /* 32-bit identifier or First 32-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);\r
+ /* 32-bit mask or Second 32-bit identifier */\r
+ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = \r
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |\r
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);\r
+ }\r
+\r
+ /* Filter Mode */\r
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)\r
+ {\r
+ /*Id/Mask mode for the filter*/\r
+ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;\r
+ }\r
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\r
+ {\r
+ /*Identifier list mode for the filter*/\r
+ CAN1->FM1R |= (uint32_t)filter_number_bit_pos;\r
+ }\r
+\r
+ /* Filter FIFO assignment */\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0)\r
+ {\r
+ /* FIFO 0 assignation for the filter */\r
+ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;\r
+ }\r
+\r
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1)\r
+ {\r
+ /* FIFO 1 assignation for the filter */\r
+ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;\r
+ }\r
+ \r
+ /* Filter activation */\r
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)\r
+ {\r
+ CAN1->FA1R |= filter_number_bit_pos;\r
+ }\r
+\r
+ /* Leave the initialisation mode for the filter */\r
+ CAN1->FMR &= ~FMR_FINIT;\r
+}\r
+\r
+/**\r
+ * @brief Fills each CAN_InitStruct member with its default value.\r
+ * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None.\r
+ */\r
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)\r
+{\r
+ /* Reset CAN init structure parameters values */\r
+ /* Initialize the time triggered communication mode */\r
+ CAN_InitStruct->CAN_TTCM = DISABLE;\r
+ /* Initialize the automatic bus-off management */\r
+ CAN_InitStruct->CAN_ABOM = DISABLE;\r
+ /* Initialize the automatic wake-up mode */\r
+ CAN_InitStruct->CAN_AWUM = DISABLE;\r
+ /* Initialize the no automatic retransmission */\r
+ CAN_InitStruct->CAN_NART = DISABLE;\r
+ /* Initialize the receive FIFO locked mode */\r
+ CAN_InitStruct->CAN_RFLM = DISABLE;\r
+ /* Initialize the transmit FIFO priority */\r
+ CAN_InitStruct->CAN_TXFP = DISABLE;\r
+ /* Initialize the CAN_Mode member */\r
+ CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;\r
+ /* Initialize the CAN_SJW member */\r
+ CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;\r
+ /* Initialize the CAN_BS1 member */\r
+ CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;\r
+ /* Initialize the CAN_BS2 member */\r
+ CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;\r
+ /* Initialize the CAN_Prescaler member */\r
+ CAN_InitStruct->CAN_Prescaler = 1;\r
+}\r
+\r
+/**\r
+ * @brief Select the start bank filter for slave CAN.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.\r
+ * @retval None.\r
+ */\r
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));\r
+ /* enter Initialisation mode for the filter */\r
+ CAN1->FMR |= FMR_FINIT;\r
+ /* Select the start slave bank */\r
+ CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;\r
+ CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;\r
+ /* Leave Initialisation mode for the filter */\r
+ CAN1->FMR &= ~FMR_FINIT;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CANx interrupts.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.\r
+ * This parameter can be: \r
+ * -CAN_IT_TME, \r
+ * -CAN_IT_FMP0, \r
+ * -CAN_IT_FF0,\r
+ * -CAN_IT_FOV0, \r
+ * -CAN_IT_FMP1, \r
+ * -CAN_IT_FF1,\r
+ * -CAN_IT_FOV1, \r
+ * -CAN_IT_EWG, \r
+ * -CAN_IT_EPV,\r
+ * -CAN_IT_LEC, \r
+ * -CAN_IT_ERR, \r
+ * -CAN_IT_WKU or \r
+ * -CAN_IT_SLK.\r
+ * @param NewState: new state of the CAN interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_IT(CAN_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected CANx interrupt */\r
+ CANx->IER |= CAN_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected CANx interrupt */\r
+ CANx->IER &= ~CAN_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initiates the transmission of a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param TxMessage: pointer to a structure which contains CAN Id, CAN\r
+ * DLC and CAN datas.\r
+ * @retval The number of the mailbox that is used for transmission\r
+ * or CAN_NO_MB if there is no empty mailbox.\r
+ */\r
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)\r
+{\r
+ uint8_t transmit_mailbox = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_IDTYPE(TxMessage->IDE));\r
+ assert_param(IS_CAN_RTR(TxMessage->RTR));\r
+ assert_param(IS_CAN_DLC(TxMessage->DLC));\r
+\r
+ /* Select one empty transmit mailbox */\r
+ if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)\r
+ {\r
+ transmit_mailbox = 0;\r
+ }\r
+ else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)\r
+ {\r
+ transmit_mailbox = 1;\r
+ }\r
+ else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)\r
+ {\r
+ transmit_mailbox = 2;\r
+ }\r
+ else\r
+ {\r
+ transmit_mailbox = CAN_NO_MB;\r
+ }\r
+\r
+ if (transmit_mailbox != CAN_NO_MB)\r
+ {\r
+ /* Set up the Id */\r
+ CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;\r
+ if (TxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ assert_param(IS_CAN_STDID(TxMessage->StdId)); \r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_CAN_EXTID(TxMessage->ExtId));\r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | \r
+ TxMessage->RTR);\r
+ }\r
+ \r
+\r
+ /* Set up the DLC */\r
+ TxMessage->DLC &= (uint8_t)0x0000000F;\r
+ CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;\r
+ CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;\r
+\r
+ /* Set up the data field */\r
+ CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | \r
+ ((uint32_t)TxMessage->Data[2] << 16) |\r
+ ((uint32_t)TxMessage->Data[1] << 8) | \r
+ ((uint32_t)TxMessage->Data[0]));\r
+ CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | \r
+ ((uint32_t)TxMessage->Data[6] << 16) |\r
+ ((uint32_t)TxMessage->Data[5] << 8) |\r
+ ((uint32_t)TxMessage->Data[4]));\r
+ /* Request transmission */\r
+ CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;\r
+ }\r
+ return transmit_mailbox;\r
+}\r
+\r
+/**\r
+ * @brief Checks the transmission of a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param TransmitMailbox: the number of the mailbox that is used for transmission.\r
+ * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case.\r
+ */\r
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)\r
+{\r
+ /* RQCP, TXOK and TME bits */\r
+ uint8_t state = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));\r
+ switch (TransmitMailbox)\r
+ {\r
+ case (0): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP0) << 2);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK0) >> 0);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TME0) >> 26);\r
+ break;\r
+ case (1): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP1) >> 6);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK1) >> 8);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TME1) >> 27);\r
+ break;\r
+ case (2): state |= (uint8_t)((CANx->TSR & CAN_TSR_RQCP2) >> 14);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TXOK2) >> 16);\r
+ state |= (uint8_t)((CANx->TSR & CAN_TSR_TME2) >> 28);\r
+ break;\r
+ default:\r
+ state = CANTXFAILED;\r
+ break;\r
+ }\r
+ switch (state)\r
+ {\r
+ /* transmit pending */\r
+ case (0x0): state = CANTXPENDING;\r
+ break;\r
+ /* transmit failed */\r
+ case (0x5): state = CANTXFAILED;\r
+ break;\r
+ /* transmit succedeed */\r
+ case (0x7): state = CANTXOK;\r
+ break;\r
+ default:\r
+ state = CANTXFAILED;\r
+ break;\r
+ }\r
+ return state;\r
+}\r
+\r
+/**\r
+ * @brief Cancels a transmit request.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
+ * @param Mailbox: Mailbox number.\r
+ * @retval None.\r
+ */\r
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));\r
+ /* abort transmission */\r
+ switch (Mailbox)\r
+ {\r
+ case (0): CANx->TSR |= CAN_TSR_ABRQ0;\r
+ break;\r
+ case (1): CANx->TSR |= CAN_TSR_ABRQ1;\r
+ break;\r
+ case (2): CANx->TSR |= CAN_TSR_ABRQ2;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Releases a FIFO.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. \r
+ * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval None.\r
+ */\r
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ /* Release FIFO0 */\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ CANx->RF0R |= CAN_RF0R_RFOM0;\r
+ }\r
+ /* Release FIFO1 */\r
+ else /* FIFONumber == CAN_FIFO1 */\r
+ {\r
+ CANx->RF1R |= CAN_RF1R_RFOM1;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of pending messages.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @retval NbMessage which is the number of pending message.\r
+ */\r
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)\r
+{\r
+ uint8_t message_pending=0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ if (FIFONumber == CAN_FIFO0)\r
+ {\r
+ message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);\r
+ }\r
+ else if (FIFONumber == CAN_FIFO1)\r
+ {\r
+ message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);\r
+ }\r
+ else\r
+ {\r
+ message_pending = 0;\r
+ }\r
+ return message_pending;\r
+}\r
+\r
+/**\r
+ * @brief Receives a message.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.\r
+ * @param RxMessage: pointer to a structure receive message which \r
+ * contains CAN Id, CAN DLC, CAN datas and FMI number.\r
+ * @retval None.\r
+ */\r
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_FIFO(FIFONumber));\r
+ /* Get the Id */\r
+ RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
+ if (RxMessage->IDE == CAN_ID_STD)\r
+ {\r
+ RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);\r
+ }\r
+ else\r
+ {\r
+ RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);\r
+ }\r
+ \r
+ RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;\r
+ /* Get the DLC */\r
+ RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;\r
+ /* Get the FMI */\r
+ RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);\r
+ /* Get the data field */\r
+ RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;\r
+ RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);\r
+ RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);\r
+ RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);\r
+ RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;\r
+ RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);\r
+ RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);\r
+ RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);\r
+ /* Release the FIFO */\r
+ CAN_FIFORelease(CANx, FIFONumber);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DBG Freeze for CAN.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param NewState: new state of the CAN peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable Debug Freeze */\r
+ CANx->MCR |= MCR_DBF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable Debug Freeze */\r
+ CANx->MCR &= ~MCR_DBF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the low power mode.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case.\r
+ */\r
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)\r
+{\r
+ uint8_t sleepstatus = CANSLEEPFAILED;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ /* Request Sleep mode */\r
+ CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);\r
+ \r
+ /* Sleep mode status */\r
+ if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode not entered */\r
+ sleepstatus = CANSLEEPOK;\r
+ }\r
+ /* At this step, sleep mode status */\r
+ return (uint8_t)sleepstatus;\r
+}\r
+\r
+/**\r
+ * @brief Wakes the CAN up.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case.\r
+ */\r
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)\r
+{\r
+ uint32_t wait_slak = SLAK_TIMEOUT;\r
+ uint8_t wakeupstatus = CANWAKEUPFAILED;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ \r
+ /* Wake up request */\r
+ CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;\r
+ \r
+ /* Sleep mode status */\r
+ while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))\r
+ {\r
+ wait_slak--;\r
+ }\r
+ if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)\r
+ {\r
+ /* Sleep mode exited */\r
+ wakeupstatus = CANWAKEUPOK;\r
+ }\r
+ /* At this step, sleep mode status */\r
+ return (uint8_t)wakeupstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CAN flag is set or not.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following flags: \r
+ * - CAN_FLAG_EWG\r
+ * - CAN_FLAG_EPV \r
+ * - CAN_FLAG_BOF\r
+ * - CAN_FLAG_RQCP0\r
+ * - CAN_FLAG_RQCP1\r
+ * - CAN_FLAG_RQCP2\r
+ * - CAN_FLAG_FMP1 \r
+ * - CAN_FLAG_FF1 \r
+ * - CAN_FLAG_FOV1 \r
+ * - CAN_FLAG_FMP0 \r
+ * - CAN_FLAG_FF0 \r
+ * - CAN_FLAG_FOV0 \r
+ * - CAN_FLAG_WKU \r
+ * - CAN_FLAG_SLAK \r
+ * - CAN_FLAG_LEC \r
+ * @retval The new state of CAN_FLAG (SET or RESET).\r
+ */\r
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_GET_FLAG(CAN_FLAG));\r
+ \r
+\r
+ if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */\r
+ { \r
+ /* Check the status of the specified CAN flag */\r
+ if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)\r
+ { \r
+ /* CAN_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ { \r
+ /* CAN_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ /* Return the CAN_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CAN's pending flags.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following flags: \r
+ * - CAN_FLAG_RQCP0\r
+ * - CAN_FLAG_RQCP1\r
+ * - CAN_FLAG_RQCP2\r
+ * - CAN_FLAG_FF1 \r
+ * - CAN_FLAG_FOV1 \r
+ * - CAN_FLAG_FF0 \r
+ * - CAN_FLAG_FOV0 \r
+ * - CAN_FLAG_WKU \r
+ * - CAN_FLAG_SLAK \r
+ * - CAN_FLAG_LEC \r
+ * @retval None.\r
+ */\r
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)\r
+{\r
+ uint32_t flagtmp=0;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));\r
+ \r
+ if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */\r
+ {\r
+ /* Clear the selected CAN flags */\r
+ CANx->ESR = (uint32_t)RESET;\r
+ }\r
+ else /* MSR or TSR or RF0R or RF1R */\r
+ {\r
+ flagtmp = CAN_FLAG & 0x000FFFFF;\r
+\r
+ if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)\r
+ {\r
+ /* Receive Flags */\r
+ CANx->RF0R = (uint32_t)(flagtmp);\r
+ }\r
+ else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)\r
+ {\r
+ /* Receive Flags */\r
+ CANx->RF1R = (uint32_t)(flagtmp);\r
+ }\r
+ else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)\r
+ {\r
+ /* Transmit Flags */\r
+ CANx->TSR = (uint32_t)(flagtmp);\r
+ }\r
+ else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */\r
+ {\r
+ /* Operating mode Flags */\r
+ CANx->MSR = (uint32_t)(flagtmp);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CANx interrupt has occurred or not.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the CAN interrupt source to check.\r
+ * This parameter can be one of the following flags: \r
+ * - CAN_IT_TME \r
+ * - CAN_IT_FMP0 \r
+ * - CAN_IT_FF0 \r
+ * - CAN_IT_FOV0 \r
+ * - CAN_IT_FMP1 \r
+ * - CAN_IT_FF1 \r
+ * - CAN_IT_FOV1 \r
+ * - CAN_IT_WKU \r
+ * - CAN_IT_SLK \r
+ * - CAN_IT_EWG \r
+ * - CAN_IT_EPV \r
+ * - CAN_IT_BOF \r
+ * - CAN_IT_LEC \r
+ * - CAN_IT_ERR \r
+ * @retval The current state of CAN_IT (SET or RESET).\r
+ */\r
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
+{\r
+ ITStatus itstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_IT(CAN_IT));\r
+ \r
+ /* check the enable interrupt bit */\r
+ if((CANx->IER & CAN_IT) != RESET)\r
+ {\r
+ /* in case the Interrupt is enabled, .... */\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_TME:\r
+ /* Check CAN_TSR_RQCPx bits */\r
+ itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); \r
+ break;\r
+ case CAN_IT_FMP0:\r
+ /* Check CAN_RF0R_FMP0 bit */\r
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); \r
+ break;\r
+ case CAN_IT_FF0:\r
+ /* Check CAN_RF0R_FULL0 bit */\r
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); \r
+ break;\r
+ case CAN_IT_FOV0:\r
+ /* Check CAN_RF0R_FOVR0 bit */\r
+ itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); \r
+ break;\r
+ case CAN_IT_FMP1:\r
+ /* Check CAN_RF1R_FMP1 bit */\r
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); \r
+ break;\r
+ case CAN_IT_FF1:\r
+ /* Check CAN_RF1R_FULL1 bit */\r
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); \r
+ break;\r
+ case CAN_IT_FOV1:\r
+ /* Check CAN_RF1R_FOVR1 bit */\r
+ itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); \r
+ break;\r
+ case CAN_IT_WKU:\r
+ /* Check CAN_MSR_WKUI bit */\r
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); \r
+ break;\r
+ case CAN_IT_SLK:\r
+ /* Check CAN_MSR_SLAKI bit */\r
+ itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); \r
+ break;\r
+ case CAN_IT_EWG:\r
+ /* Check CAN_ESR_EWGF bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); \r
+ break;\r
+ case CAN_IT_EPV:\r
+ /* Check CAN_ESR_EPVF bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); \r
+ break;\r
+ case CAN_IT_BOF:\r
+ /* Check CAN_ESR_BOFF bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); \r
+ break;\r
+ case CAN_IT_LEC:\r
+ /* Check CAN_ESR_LEC bit */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); \r
+ break;\r
+ case CAN_IT_ERR:\r
+ /* Check CAN_MSR_ERRI, CAN_ESR_EWGF, CAN_ESR_EPVF, CAN_ESR_BOFF and CAN_ESR_LEC bits */\r
+ itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF|CAN_ESR_EPVF|CAN_ESR_BOFF|CAN_ESR_LEC); \r
+ itstatus |= CheckITStatus(CANx->MSR, CAN_MSR_ERRI); \r
+ break;\r
+ default :\r
+ /* in case of error, return RESET */\r
+ itstatus = RESET;\r
+ break;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* in case the Interrupt is not enabled, return RESET */\r
+ itstatus = RESET;\r
+ }\r
+ \r
+ /* Return the CAN_IT status */\r
+ return itstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CANx\92s interrupt pending bits.\r
+ * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.\r
+ * @param CAN_IT: specifies the interrupt pending bit to clear.\r
+ * - CAN_IT_TME \r
+ * - CAN_IT_FF0 \r
+ * - CAN_IT_FOV0 \r
+ * - CAN_IT_FF1 \r
+ * - CAN_IT_FOV1 \r
+ * - CAN_IT_WKU \r
+ * - CAN_IT_SLK \r
+ * - CAN_IT_EWG \r
+ * - CAN_IT_EPV \r
+ * - CAN_IT_BOF \r
+ * - CAN_IT_LEC \r
+ * - CAN_IT_ERR \r
+ * @retval None.\r
+ */\r
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CAN_ALL_PERIPH(CANx));\r
+ assert_param(IS_CAN_CLEAR_IT(CAN_IT));\r
+\r
+ switch (CAN_IT)\r
+ {\r
+ case CAN_IT_TME:\r
+ /* Clear CAN_TSR_RQCPx (rc_w1)*/\r
+ CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; \r
+ break;\r
+ case CAN_IT_FF0:\r
+ /* Clear CAN_RF0R_FULL0 (rc_w1)*/\r
+ CANx->RF0R = CAN_RF0R_FULL0; \r
+ break;\r
+ case CAN_IT_FOV0:\r
+ /* Clear CAN_RF0R_FOVR0 (rc_w1)*/\r
+ CANx->RF0R = CAN_RF0R_FOVR0; \r
+ break;\r
+ case CAN_IT_FF1:\r
+ /* Clear CAN_RF1R_FULL1 (rc_w1)*/\r
+ CANx->RF1R = CAN_RF1R_FULL1; \r
+ break;\r
+ case CAN_IT_FOV1:\r
+ /* Clear CAN_RF1R_FOVR1 (rc_w1)*/\r
+ CANx->RF1R = CAN_RF1R_FOVR1; \r
+ break;\r
+ case CAN_IT_WKU:\r
+ /* Clear CAN_MSR_WKUI (rc_w1)*/\r
+ CANx->MSR = CAN_MSR_WKUI; \r
+ break;\r
+ case CAN_IT_SLK:\r
+ /* Clear CAN_MSR_SLAKI (rc_w1)*/ \r
+ CANx->MSR = CAN_MSR_SLAKI; \r
+ break;\r
+ case CAN_IT_EWG:\r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI;\r
+ /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/ \r
+ break;\r
+ case CAN_IT_EPV:\r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/\r
+ break;\r
+ case CAN_IT_BOF:\r
+ /* Clear CAN_MSR_ERRI (rc_w1) */ \r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ /* Note : the corresponding Flag is cleared by hardware depending of the CAN Bus status*/\r
+ break;\r
+ case CAN_IT_LEC:\r
+ /* Clear LEC bits */\r
+ CANx->ESR = RESET; \r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ break;\r
+ case CAN_IT_ERR:\r
+ /*Clear LEC bits */\r
+ CANx->ESR = RESET; \r
+ /* Clear CAN_MSR_ERRI (rc_w1) */\r
+ CANx->MSR = CAN_MSR_ERRI; \r
+ /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending of the CAN Bus status*/\r
+ break;\r
+ default :\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the CAN interrupt has occurred or not.\r
+ * @param CAN_Reg: specifies the CAN interrupt register to check.\r
+ * @param It_Bit: specifies the interrupt source bit to check.\r
+ * @retval The new state of the CAN Interrupt (SET or RESET).\r
+ */\r
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)\r
+{\r
+ ITStatus pendingbitstatus = RESET;\r
+ \r
+ if ((CAN_Reg & It_Bit) != (uint32_t)RESET)\r
+ {\r
+ /* CAN_IT is set */\r
+ pendingbitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CAN_IT is reset */\r
+ pendingbitstatus = RESET;\r
+ }\r
+ return pendingbitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_cec.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the CEC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_cec.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC \r
+ * @brief CEC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CEC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @defgroup CEC_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* ------------ CEC registers bit address in the alias region ----------- */\r
+#define CEC_OFFSET (CEC_BASE - PERIPH_BASE)\r
+\r
+/* --- CFGR Register ---*/\r
+\r
+/* Alias word address of PE bit */\r
+#define CFGR_OFFSET (CEC_OFFSET + 0x00)\r
+#define PE_BitNumber 0x00\r
+#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4))\r
+\r
+/* Alias word address of IE bit */\r
+#define IE_BitNumber 0x01\r
+#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of TSOM bit */\r
+#define CSR_OFFSET (CEC_OFFSET + 0x10)\r
+#define TSOM_BitNumber 0x00\r
+#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4))\r
+\r
+/* Alias word address of TEOM bit */\r
+#define TEOM_BitNumber 0x01\r
+#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4))\r
+ \r
+#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */\r
+#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Variables\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup CEC_Private_Functions\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Deinitializes the CEC peripheral registers to their default reset \r
+ * values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_DeInit(void)\r
+{\r
+ /* Enable CEC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); \r
+ /* Release CEC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Initializes the CEC peripheral according to the specified \r
+ * parameters in the CEC_InitStruct.\r
+ * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that\r
+ * contains the configuration information for the specified\r
+ * CEC peripheral.\r
+ * @retval None\r
+ */\r
+void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); \r
+ assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode));\r
+ \r
+ /*---------------------------- CEC CFGR Configuration -----------------*/\r
+ /* Get the CEC CFGR value */\r
+ tmpreg = CEC->CFGR;\r
+ \r
+ /* Clear BTEM and BPEM bits */\r
+ tmpreg &= CFGR_CLEAR_Mask;\r
+ \r
+ /* Configure CEC: Bit Timing Error and Bit Period Error */\r
+ tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode);\r
+\r
+ /* Write to CEC CFGR register*/\r
+ CEC->CFGR = tmpreg;\r
+ \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified CEC peripheral.\r
+ * @param NewState: new state of the CEC peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState;\r
+\r
+ if(NewState == DISABLE)\r
+ {\r
+ /* Wait until the PE bit is cleared by hardware (Idle Line detected) */\r
+ while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET)\r
+ {\r
+ } \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CEC interrupt.\r
+ * @param NewState: new state of the CEC interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_ITConfig(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Defines the Own Address of the CEC device.\r
+ * @param CEC_OwnAddress: The CEC own address\r
+ * @retval None\r
+ */\r
+void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));\r
+\r
+ /* Set the CEC own address */\r
+ CEC->OAR = CEC_OwnAddress;\r
+}\r
+\r
+/**\r
+ * @brief Sets the CEC prescaler value.\r
+ * @param CEC_Prescaler: CEC prescaler new value\r
+ * @retval None\r
+ */\r
+void CEC_SetPrescaler(uint16_t CEC_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_PRESCALER(CEC_Prescaler));\r
+\r
+ /* Set the Prescaler value*/\r
+ CEC->PRES = CEC_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Transmits single data through the CEC peripheral.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void CEC_SendDataByte(uint8_t Data)\r
+{ \r
+ /* Transmit Data */\r
+ CEC->TXD = Data ;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the CEC peripheral.\r
+ * @param None\r
+ * @retval The received data.\r
+ */\r
+uint8_t CEC_ReceiveDataByte(void)\r
+{\r
+ /* Receive Data */\r
+ return (uint8_t)(CEC->RXD);\r
+}\r
+\r
+/**\r
+ * @brief Starts a new message.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CEC_StartOfMessage(void)\r
+{ \r
+ /* Starts of new message */\r
+ *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1;\r
+}\r
+\r
+/**\r
+ * @brief Transmits message with or without an EOM bit.\r
+ * @param NewState: new state of the CEC Tx End Of Message. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void CEC_EndOfMessageCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* The data byte will be transmitted with or without an EOM bit*/\r
+ *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Gets the CEC flag status\r
+ * @param CEC_FLAG: specifies the CEC flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_FLAG_BTE: Bit Timing Error\r
+ * @arg CEC_FLAG_BPE: Bit Period Error\r
+ * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error\r
+ * @arg CEC_FLAG_SBE: Start Bit Error\r
+ * @arg CEC_FLAG_ACKE: Block Acknowledge Error\r
+ * @arg CEC_FLAG_LINE: Line Error\r
+ * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error\r
+ * @arg CEC_FLAG_TEOM: Tx End Of Message \r
+ * @arg CEC_FLAG_TERR: Tx Error\r
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
+ * @arg CEC_FLAG_REOM: Rx End Of Message\r
+ * @arg CEC_FLAG_RERR: Rx Error\r
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
+ * @retval The new state of CEC_FLAG (SET or RESET)\r
+ */\r
+FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) \r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t cecreg = 0, cecbase = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_FLAG(CEC_FLAG));\r
+ \r
+ /* Get the CEC peripheral base address */\r
+ cecbase = (uint32_t)(CEC_BASE);\r
+ \r
+ /* Read flag register index */\r
+ cecreg = CEC_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ CEC_FLAG &= FLAG_Mask;\r
+ \r
+ if(cecreg != 0)\r
+ {\r
+ /* Flag in CEC ESR Register */\r
+ CEC_FLAG = (uint32_t)(CEC_FLAG >> 16);\r
+ \r
+ /* Get the CEC ESR register address */\r
+ cecbase += 0xC;\r
+ }\r
+ else\r
+ {\r
+ /* Get the CEC CSR register address */\r
+ cecbase += 0x10;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* CEC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the CEC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's pending flags.\r
+ * @param CEC_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_FLAG_TERR: Tx Error\r
+ * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished\r
+ * @arg CEC_FLAG_RSOM: Rx Start Of Message\r
+ * @arg CEC_FLAG_REOM: Rx End Of Message\r
+ * @arg CEC_FLAG_RERR: Rx Error\r
+ * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished\r
+ * @retval None\r
+ */\r
+void CEC_ClearFlag(uint32_t CEC_FLAG)\r
+{ \r
+ uint32_t tmp = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));\r
+\r
+ tmp = CEC->CSR & 0x2;\r
+ \r
+ /* Clear the selected CEC flags */\r
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified CEC interrupt has occurred or not.\r
+ * @param CEC_IT: specifies the CEC interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg CEC_IT_TERR: Tx Error\r
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
+ * @arg CEC_IT_RERR: Rx Error\r
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
+ * @retval The new state of CEC_IT (SET or RESET).\r
+ */\r
+ITStatus CEC_GetITStatus(uint8_t CEC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_IT(CEC_IT));\r
+ \r
+ /* Get the CEC IT enable bit status */\r
+ enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ;\r
+ \r
+ /* Check the status of the specified CEC interrupt */\r
+ if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* CEC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* CEC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the CEC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the CEC's interrupt pending bits.\r
+ * @param CEC_IT: specifies the CEC interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg CEC_IT_TERR: Tx Error\r
+ * @arg CEC_IT_TBTF: Tx Block Transfer Finished\r
+ * @arg CEC_IT_RERR: Rx Error\r
+ * @arg CEC_IT_RBTF: Rx Block Transfer Finished\r
+ * @retval None\r
+ */\r
+void CEC_ClearITPendingBit(uint16_t CEC_IT)\r
+{\r
+ uint32_t tmp = 0x0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_CEC_GET_IT(CEC_IT));\r
+ \r
+ tmp = CEC->CSR & 0x2;\r
+ \r
+ /* Clear the selected CEC interrupt pending bits */\r
+ CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_crc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the CRC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_crc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC \r
+ * @brief CRC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup CRC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup CRC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the CRC Data register (DR).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void CRC_ResetDR(void)\r
+{\r
+ /* Reset CRC generator */\r
+ CRC->CR = CRC_CR_RESET;\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given data word(32-bit).\r
+ * @param Data: data word(32-bit) to compute its CRC\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcCRC(uint32_t Data)\r
+{\r
+ CRC->DR = Data;\r
+ \r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).\r
+ * @param pBuffer: pointer to the buffer containing the data to be computed\r
+ * @param BufferLength: length of the buffer to be computed \r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)\r
+{\r
+ uint32_t index = 0;\r
+ \r
+ for(index = 0; index < BufferLength; index++)\r
+ {\r
+ CRC->DR = pBuffer[index];\r
+ }\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Returns the current CRC value.\r
+ * @param None\r
+ * @retval 32-bit CRC\r
+ */\r
+uint32_t CRC_GetCRC(void)\r
+{\r
+ return (CRC->DR);\r
+}\r
+\r
+/**\r
+ * @brief Stores a 8-bit data in the Independent Data(ID) register.\r
+ * @param IDValue: 8-bit value to be stored in the ID register \r
+ * @retval None\r
+ */\r
+void CRC_SetIDRegister(uint8_t IDValue)\r
+{\r
+ CRC->IDR = IDValue;\r
+}\r
+\r
+/**\r
+ * @brief Returns the 8-bit data stored in the Independent Data(ID) register\r
+ * @param None\r
+ * @retval 8-bit value of the ID register \r
+ */\r
+uint8_t CRC_GetIDRegister(void)\r
+{\r
+ return (CRC->IDR);\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dac.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the DAC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dac.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DAC \r
+ * @brief DAC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DAC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* CR register Mask */\r
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)\r
+\r
+/* DAC Dual Channels SWTRIG masks */\r
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)\r
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)\r
+\r
+/* DHR registers offsets */\r
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)\r
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)\r
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)\r
+\r
+/* DOR register offset */\r
+#define DOR_OFFSET ((uint32_t)0x0000002C)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DAC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void DAC_DeInit(void)\r
+{\r
+ /* Enable DAC reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);\r
+ /* Release DAC from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DAC peripheral according to the specified \r
+ * parameters in the DAC_InitStruct.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that\r
+ * contains the configuration information for the specified DAC channel.\r
+ * @retval None\r
+ */\r
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;\r
+ /* Check the DAC parameters */\r
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));\r
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));\r
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));\r
+ assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));\r
+/*---------------------------- DAC CR Configuration --------------------------*/\r
+ /* Get the DAC CR value */\r
+ tmpreg1 = DAC->CR;\r
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */\r
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);\r
+ /* Configure for the selected DAC channel: buffer output, trigger, wave genration,\r
+ mask/amplitude for wave genration */\r
+ /* Set TSELx and TENx bits according to DAC_Trigger value */\r
+ /* Set WAVEx bits according to DAC_WaveGeneration value */\r
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ \r
+ /* Set BOFFx bit according to DAC_OutputBuffer value */ \r
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);\r
+ /* Calculate CR register value depending on DAC_Channel */\r
+ tmpreg1 |= tmpreg2 << DAC_Channel;\r
+ /* Write to DAC CR */\r
+ DAC->CR = tmpreg1;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DAC_InitStruct member with its default value.\r
+ * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)\r
+{\r
+/*--------------- Reset DAC init structure parameters values -----------------*/\r
+ /* Initialize the DAC_Trigger member */\r
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;\r
+ /* Initialize the DAC_WaveGeneration member */\r
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;\r
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */\r
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;\r
+ /* Initialize the DAC_OutputBuffer member */\r
+ DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the DAC channel. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel */\r
+ DAC->CR |= (DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel */\r
+ DAC->CR &= ~(DAC_CR_EN1 << DAC_Channel);\r
+ }\r
+}\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/**\r
+ * @brief Enables or disables the specified DAC interrupts.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @param NewState: new state of the specified DAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */ \r
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) \r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC interrupts */\r
+ DAC->CR |= (DAC_IT << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC interrupts */\r
+ DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));\r
+ }\r
+}\r
+#endif\r
+\r
+/**\r
+ * @brief Enables or disables the specified DAC channel DMA request.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DAC channel DMA request */\r
+ DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DAC channel DMA request */\r
+ DAC->CR &= ~(DAC_CR_DMAEN1 << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel software trigger.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param NewState: new state of the selected DAC channel software trigger.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for the selected DAC channel */\r
+ DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables simultaneously the two DAC channels software\r
+ * triggers.\r
+ * @param NewState: new state of the DAC channels software triggers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable software trigger for both DAC channels */\r
+ DAC->SWTRIGR |= DUAL_SWTRIG_SET ;\r
+ }\r
+ else\r
+ {\r
+ /* Disable software trigger for both DAC channels */\r
+ DAC->SWTRIGR &= DUAL_SWTRIG_RESET;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the selected DAC channel wave generation.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_Wave: Specifies the wave type to enable or disable.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Wave_Noise: noise wave generation\r
+ * @arg DAC_Wave_Triangle: triangle wave generation\r
+ * @param NewState: new state of the selected DAC channel wave generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_WAVE(DAC_Wave)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected wave generation for the selected DAC channel */\r
+ DAC->CR |= DAC_Wave << DAC_Channel;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected wave generation for the selected DAC channel */\r
+ DAC->CR &= ~(DAC_Wave << DAC_Channel);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel1.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel1.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)\r
+{ \r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE; \r
+ tmp += DHR12R1_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel1 selected data holding register */\r
+ *(__IO uint32_t *) tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for DAC channel2.\r
+ * @param DAC_Align: Specifies the data alignement for DAC channel2.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data : Data to be loaded in the selected data holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data));\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12R2_OFFSET + DAC_Align;\r
+\r
+ /* Set the DAC channel2 selected data holding register */\r
+ *(__IO uint32_t *)tmp = Data;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified data holding register value for dual channel\r
+ * DAC.\r
+ * @param DAC_Align: Specifies the data alignement for dual channel DAC.\r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Align_8b_R: 8bit right data alignement selected\r
+ * @arg DAC_Align_12b_L: 12bit left data alignement selected\r
+ * @arg DAC_Align_12b_R: 12bit right data alignement selected\r
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data \r
+ * holding register.\r
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data \r
+ * holding register.\r
+ * @retval None\r
+ */\r
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)\r
+{\r
+ uint32_t data = 0, tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_ALIGN(DAC_Align));\r
+ assert_param(IS_DAC_DATA(Data1));\r
+ assert_param(IS_DAC_DATA(Data2));\r
+ \r
+ /* Calculate and set dual DAC data holding register value */\r
+ if (DAC_Align == DAC_Align_8b_R)\r
+ {\r
+ data = ((uint32_t)Data2 << 8) | Data1; \r
+ }\r
+ else\r
+ {\r
+ data = ((uint32_t)Data2 << 16) | Data1;\r
+ }\r
+ \r
+ tmp = (uint32_t)DAC_BASE;\r
+ tmp += DHR12RD_OFFSET + DAC_Align;\r
+\r
+ /* Set the dual DAC selected data holding register */\r
+ *(__IO uint32_t *)tmp = data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the last data output value of the selected DAC cahnnel.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @retval The selected DAC channel data output value.\r
+ */\r
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ \r
+ tmp = (uint32_t) DAC_BASE ;\r
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);\r
+ \r
+ /* Returns the DAC channel data output register value */\r
+ return (uint16_t) (*(__IO uint32_t*) tmp);\r
+}\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/**\r
+ * @brief Checks whether the specified DAC flag is set or not.\r
+ * @param DAC_Channel: thee selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to check. \r
+ * This parameter can be only of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval The new state of DAC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Check the status of the specified DAC flag */\r
+ if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)\r
+ {\r
+ /* DAC_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channelx's pending flags.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_FLAG: specifies the flag to clear. \r
+ * This parameter can be of the following value:\r
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag \r
+ * @retval None\r
+ */\r
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_FLAG(DAC_FLAG));\r
+\r
+ /* Clear the selected DAC flags */\r
+ DAC->SR = (DAC_FLAG << DAC_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DAC interrupt has occurred or not.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt source to check. \r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval The new state of DAC_IT (SET or RESET).\r
+ */\r
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT));\r
+\r
+ /* Get the DAC_IT enable bit status */\r
+ enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;\r
+ \r
+ /* Check the status of the specified DAC interrupt */\r
+ if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* DAC_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DAC_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DAC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DAC channelx\92s interrupt pending bits.\r
+ * @param DAC_Channel: the selected DAC channel. \r
+ * This parameter can be one of the following values:\r
+ * @arg DAC_Channel_1: DAC Channel1 selected\r
+ * @arg DAC_Channel_2: DAC Channel2 selected\r
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.\r
+ * This parameter can be the following values:\r
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask \r
+ * @retval None\r
+ */\r
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));\r
+ assert_param(IS_DAC_IT(DAC_IT)); \r
+\r
+ /* Clear the selected DAC interrupt pending bits */\r
+ DAC->SR = (DAC_IT << DAC_Channel);\r
+}\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dbgmcu.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the DBGMCU firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dbgmcu.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DBGMCU \r
+ * @brief DBGMCU driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DBGMCU_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DBGMCU_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Returns the device revision identifier.\r
+ * @param None\r
+ * @retval Device revision identifier\r
+ */\r
+uint32_t DBGMCU_GetREVID(void)\r
+{\r
+ return(DBGMCU->IDCODE >> 16);\r
+}\r
+\r
+/**\r
+ * @brief Returns the device identifier.\r
+ * @param None\r
+ * @retval Device identifier\r
+ */\r
+uint32_t DBGMCU_GetDEVID(void)\r
+{\r
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified peripheral and low power mode behavior\r
+ * when the MCU under Debug mode.\r
+ * @param DBGMCU_Periph: specifies the peripheral and low power mode.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode \r
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode \r
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode \r
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted \r
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted \r
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted \r
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted \r
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted\r
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted\r
+ * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted\r
+ * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted \r
+ * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted \r
+ * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted\r
+ * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted\r
+ * @param NewState: new state of the specified peripheral in Debug mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ DBGMCU->CR |= DBGMCU_Periph;\r
+ }\r
+ else\r
+ {\r
+ DBGMCU->CR &= ~DBGMCU_Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_dma.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the DMA firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_dma.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup DMA \r
+ * @brief DMA driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup DMA_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Defines\r
+ * @{\r
+ */\r
+\r
+\r
+/* DMA1 Channelx interrupt pending bit masks */\r
+#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))\r
+#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))\r
+\r
+/* DMA2 Channelx interrupt pending bit masks */\r
+#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))\r
+#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))\r
+#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))\r
+#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))\r
+#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))\r
+\r
+/* DMA2 FLAG mask */\r
+#define FLAG_Mask ((uint32_t)0x10000000)\r
+\r
+/* DMA registers Masks */\r
+#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup DMA_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the DMAy Channelx registers to their default reset\r
+ * values.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and\r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ \r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+ \r
+ /* Reset DMAy Channelx control register */\r
+ DMAy_Channelx->CCR = 0;\r
+ \r
+ /* Reset DMAy Channelx remaining bytes register */\r
+ DMAy_Channelx->CNDTR = 0;\r
+ \r
+ /* Reset DMAy Channelx peripheral address register */\r
+ DMAy_Channelx->CPAR = 0;\r
+ \r
+ /* Reset DMAy Channelx memory address register */\r
+ DMAy_Channelx->CMAR = 0;\r
+ \r
+ if (DMAy_Channelx == DMA1_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel1 */\r
+ DMA1->IFCR |= DMA1_Channel1_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel2 */\r
+ DMA1->IFCR |= DMA1_Channel2_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel3 */\r
+ DMA1->IFCR |= DMA1_Channel3_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel4 */\r
+ DMA1->IFCR |= DMA1_Channel4_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel5 */\r
+ DMA1->IFCR |= DMA1_Channel5_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel6)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel6 */\r
+ DMA1->IFCR |= DMA1_Channel6_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA1_Channel7)\r
+ {\r
+ /* Reset interrupt pending bits for DMA1 Channel7 */\r
+ DMA1->IFCR |= DMA1_Channel7_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel1)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel1 */\r
+ DMA2->IFCR |= DMA2_Channel1_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel2)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel2 */\r
+ DMA2->IFCR |= DMA2_Channel2_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel3)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel3 */\r
+ DMA2->IFCR |= DMA2_Channel3_IT_Mask;\r
+ }\r
+ else if (DMAy_Channelx == DMA2_Channel4)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel4 */\r
+ DMA2->IFCR |= DMA2_Channel4_IT_Mask;\r
+ }\r
+ else\r
+ { \r
+ if (DMAy_Channelx == DMA2_Channel5)\r
+ {\r
+ /* Reset interrupt pending bits for DMA2 Channel5 */\r
+ DMA2->IFCR |= DMA2_Channel5_IT_Mask;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMAy Channelx according to the specified\r
+ * parameters in the DMA_InitStruct.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that\r
+ * contains the configuration information for the specified DMA Channel.\r
+ * @retval None\r
+ */\r
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));\r
+ assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));\r
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));\r
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); \r
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));\r
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));\r
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));\r
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));\r
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));\r
+\r
+/*--------------------------- DMAy Channelx CCR Configuration -----------------*/\r
+ /* Get the DMAy_Channelx CCR value */\r
+ tmpreg = DMAy_Channelx->CCR;\r
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */\r
+ tmpreg &= CCR_CLEAR_Mask;\r
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */\r
+ /* Set DIR bit according to DMA_DIR value */\r
+ /* Set CIRC bit according to DMA_Mode value */\r
+ /* Set PINC bit according to DMA_PeripheralInc value */\r
+ /* Set MINC bit according to DMA_MemoryInc value */\r
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */\r
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */\r
+ /* Set PL bits according to DMA_Priority value */\r
+ /* Set the MEM2MEM bit according to DMA_M2M value */\r
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |\r
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |\r
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |\r
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;\r
+\r
+ /* Write to DMAy Channelx CCR */\r
+ DMAy_Channelx->CCR = tmpreg;\r
+\r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;\r
+\r
+/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CPAR */\r
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;\r
+\r
+/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/\r
+ /* Write to DMAy Channelx CMAR */\r
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;\r
+}\r
+\r
+/**\r
+ * @brief Fills each DMA_InitStruct member with its default value.\r
+ * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)\r
+{\r
+/*-------------- Reset DMA init structure parameters values ------------------*/\r
+ /* Initialize the DMA_PeripheralBaseAddr member */\r
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;\r
+ /* Initialize the DMA_MemoryBaseAddr member */\r
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;\r
+ /* Initialize the DMA_DIR member */\r
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;\r
+ /* Initialize the DMA_BufferSize member */\r
+ DMA_InitStruct->DMA_BufferSize = 0;\r
+ /* Initialize the DMA_PeripheralInc member */\r
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;\r
+ /* Initialize the DMA_MemoryInc member */\r
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;\r
+ /* Initialize the DMA_PeripheralDataSize member */\r
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;\r
+ /* Initialize the DMA_MemoryDataSize member */\r
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;\r
+ /* Initialize the DMA_Mode member */\r
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;\r
+ /* Initialize the DMA_Priority member */\r
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;\r
+ /* Initialize the DMA_M2M member */\r
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param NewState: new state of the DMAy Channelx. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR |= DMA_CCR1_EN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMAy Channelx */\r
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMAy Channelx interrupts.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled\r
+ * or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg DMA_IT_TC: Transfer complete interrupt mask\r
+ * @arg DMA_IT_HT: Half transfer interrupt mask\r
+ * @arg DMA_IT_TE: Transfer error interrupt mask\r
+ * @param NewState: new state of the specified DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR |= DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA interrupts */\r
+ DMAy_Channelx->CCR &= ~DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @param DataNumber: The number of data units in the current DMAy Channelx\r
+ * transfer. \r
+ * @note This function can only be used when the DMAy_Channelx is disabled. \r
+ * @retval None.\r
+ */\r
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ \r
+/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/\r
+ /* Write to DMAy Channelx CNDTR */\r
+ DMAy_Channelx->CNDTR = DataNumber; \r
+}\r
+\r
+/**\r
+ * @brief Returns the number of remaining data units in the current\r
+ * DMAy Channelx transfer.\r
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and \r
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.\r
+ * @retval The number of remaining data units in the current DMAy Channelx\r
+ * transfer.\r
+ */\r
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));\r
+ /* Return the number of remaining data units for DMAy Channelx */\r
+ return ((uint16_t)(DMAy_Channelx->CNDTR));\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.\r
+ * @param DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
+ * @retval The new state of DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_FLAG(DMA_FLAG));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR ;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA flag */\r
+ if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the DMA_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx's pending flags.\r
+ * @param DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.\r
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.\r
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.\r
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.\r
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.\r
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.\r
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.\r
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.\r
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.\r
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.\r
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.\r
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.\r
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.\r
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.\r
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.\r
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.\r
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.\r
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.\r
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.\r
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.\r
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.\r
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.\r
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.\r
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.\r
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.\r
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.\r
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.\r
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.\r
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.\r
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.\r
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.\r
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.\r
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.\r
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.\r
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.\r
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.\r
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.\r
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.\r
+ * @retval None\r
+ */\r
+void DMA_ClearFlag(uint32_t DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));\r
+ /* Calculate the used DMA */\r
+\r
+ if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA2->IFCR = DMA_FLAG;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMA flags */\r
+ DMA1->IFCR = DMA_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.\r
+ * @param DMA_IT: specifies the DMA interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
+ * @retval The new state of DMA_IT (SET or RESET).\r
+ */\r
+ITStatus DMA_GetITStatus(uint32_t DMA_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_GET_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Get DMA2 ISR register value */\r
+ tmpreg = DMA2->ISR ;\r
+ }\r
+ else\r
+ {\r
+ /* Get DMA1 ISR register value */\r
+ tmpreg = DMA1->ISR ;\r
+ }\r
+\r
+ /* Check the status of the specified DMA interrupt */\r
+ if ((tmpreg & DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ /* DMA_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* DMA_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the DMA_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the DMAy Channelx\92s interrupt pending bits.\r
+ * @param DMA_IT: specifies the DMA interrupt pending bit to clear.\r
+ * This parameter can be any combination (for the same DMA) of the following values:\r
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.\r
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.\r
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.\r
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.\r
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.\r
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.\r
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.\r
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.\r
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.\r
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.\r
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.\r
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.\r
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.\r
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.\r
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.\r
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.\r
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.\r
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.\r
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.\r
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.\r
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.\r
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.\r
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.\r
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.\r
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.\r
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.\r
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.\r
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.\r
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.\r
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.\r
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.\r
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.\r
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.\r
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.\r
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.\r
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.\r
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.\r
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.\r
+ * @retval None\r
+ */\r
+void DMA_ClearITPendingBit(uint32_t DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_DMA_CLEAR_IT(DMA_IT));\r
+\r
+ /* Calculate the used DMA */\r
+ if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET)\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA2->IFCR = DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the selected DMA interrupt pending bits */\r
+ DMA1->IFCR = DMA_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_exti.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the EXTI firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_exti.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI \r
+ * @brief EXTI driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup EXTI_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup EXTI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the EXTI peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void EXTI_DeInit(void)\r
+{\r
+ EXTI->IMR = 0x00000000;\r
+ EXTI->EMR = 0x00000000;\r
+ EXTI->RTSR = 0x00000000; \r
+ EXTI->FTSR = 0x00000000; \r
+ EXTI->PR = 0x000FFFFF;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the EXTI peripheral according to the specified\r
+ * parameters in the EXTI_InitStruct.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure\r
+ * that contains the configuration information for the EXTI peripheral.\r
+ * @retval None\r
+ */\r
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));\r
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));\r
+ assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); \r
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));\r
+\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ \r
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)\r
+ {\r
+ /* Clear EXTI line configuration */\r
+ EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+\r
+ /* Clear Rising Falling edge configuration */\r
+ EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;\r
+ \r
+ /* Select the trigger for the selected external interrupts */\r
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)\r
+ {\r
+ /* Rising Falling edge */\r
+ EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;\r
+ EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ else\r
+ {\r
+ tmp = (uint32_t)EXTI_BASE;\r
+ tmp += EXTI_InitStruct->EXTI_Trigger;\r
+\r
+ *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ tmp += EXTI_InitStruct->EXTI_Mode;\r
+\r
+ /* Disable the selected external lines */\r
+ *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each EXTI_InitStruct member with its reset value.\r
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)\r
+{\r
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;\r
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;\r
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;\r
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;\r
+}\r
+\r
+/**\r
+ * @brief Generates a Software interrupt.\r
+ * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
+ * @retval None\r
+ */\r
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->SWIER |= EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line flag is set or not.\r
+ * @param EXTI_Line: specifies the EXTI line flag to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending flags.\r
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearFlag(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified EXTI line is asserted or not.\r
+ * @param EXTI_Line: specifies the EXTI line to check.\r
+ * This parameter can be:\r
+ * @arg EXTI_Linex: External interrupt line x where x(0..19)\r
+ * @retval The new state of EXTI_Line (SET or RESET).\r
+ */\r
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));\r
+ \r
+ enablestatus = EXTI->IMR & EXTI_Line;\r
+ if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the EXTI\92s line pending bits.\r
+ * @param EXTI_Line: specifies the EXTI lines to clear.\r
+ * This parameter can be any combination of EXTI_Linex where x can be (0..19).\r
+ * @retval None\r
+ */\r
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_EXTI_LINE(EXTI_Line));\r
+ \r
+ EXTI->PR = EXTI_Line;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_flash.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the FLASH firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_flash.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FLASH \r
+ * @brief FLASH driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* Flash Access Control Register bits */\r
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)\r
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)\r
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)\r
+\r
+/* Flash Access Control Register bits */\r
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) \r
+\r
+/* Flash Control Register bits */\r
+#define CR_PG_Set ((uint32_t)0x00000001)\r
+#define CR_PG_Reset ((uint32_t)0x00001FFE) \r
+#define CR_PER_Set ((uint32_t)0x00000002)\r
+#define CR_PER_Reset ((uint32_t)0x00001FFD)\r
+#define CR_MER_Set ((uint32_t)0x00000004)\r
+#define CR_MER_Reset ((uint32_t)0x00001FFB)\r
+#define CR_OPTPG_Set ((uint32_t)0x00000010)\r
+#define CR_OPTPG_Reset ((uint32_t)0x00001FEF)\r
+#define CR_OPTER_Set ((uint32_t)0x00000020)\r
+#define CR_OPTER_Reset ((uint32_t)0x00001FDF)\r
+#define CR_STRT_Set ((uint32_t)0x00000040)\r
+#define CR_LOCK_Set ((uint32_t)0x00000080)\r
+\r
+/* FLASH Mask */\r
+#define RDPRT_Mask ((uint32_t)0x00000002)\r
+#define WRP0_Mask ((uint32_t)0x000000FF)\r
+#define WRP1_Mask ((uint32_t)0x0000FF00)\r
+#define WRP2_Mask ((uint32_t)0x00FF0000)\r
+#define WRP3_Mask ((uint32_t)0xFF000000)\r
+#define OB_USER_BFB2 ((uint16_t)0x0008)\r
+\r
+/* FLASH Keys */\r
+#define RDP_Key ((uint16_t)0x00A5)\r
+#define FLASH_KEY1 ((uint32_t)0x45670123)\r
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)\r
+\r
+/* FLASH BANK address */\r
+#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)\r
+\r
+/* Delay definition */ \r
+#define EraseTimeout ((uint32_t)0x000B0000)\r
+#define ProgramTimeout ((uint32_t)0x00002000)\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup FLASH_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FLASH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+@code \r
+ \r
+ This driver provides functions to configure and program the Flash memory of all STM32F10x devices,\r
+ including the latest STM32F10x_XL density devices. \r
+\r
+ STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:\r
+ - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each)\r
+ - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each)\r
+ While other STM32F10x devices features only one bank with memory up to 512 Kbytes.\r
+\r
+ In version V3.3.0, some functions were updated and new ones were added to support\r
+ STM32F10x_XL devices. Thus some functions manages all devices, while other are \r
+ dedicated for XL devices only.\r
+ \r
+ The table below presents the list of available functions depending on the used STM32F10x devices. \r
+ \r
+ ***************************************************\r
+ * Legacy functions used for all STM32F10x devices *\r
+ ***************************************************\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
+ | | devices | devices | |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_SetLatency | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_HalfCycleAccessCmd | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_PrefetchBufferCmd | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. |\r
+ | | | | - For other devices: unlock Bank1 and it is equivalent |\r
+ | | | | to FLASH_UnlockBank1 function. |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. |\r
+ | | | | - For other devices: lock Bank1 and it is equivalent |\r
+ | | | | to FLASH_LockBank1 function. |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 |\r
+ | | | | - For other devices: erase a page in Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 |\r
+ | | | | - For other devices: erase all pages in Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_EraseOptionBytes | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ProgramOptionByteData | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_EnableWriteProtection | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ReadOutProtection | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_UserOptionByteConfig | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetUserOptionByte | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts|\r
+ | | | | - For other devices: enable Bank1's interrupts |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status|\r
+ | | | | - For other devices: return Bank1's flag status |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag |\r
+ | | | | - For other devices: clear Bank1's flag |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) |\r
+ | | | | equivalent to FLASH_GetBank1Status function |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) |\r
+ | | | | equivalent to: FLASH_WaitForLastBank1Operation function |\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+\r
+ ************************************************************************************************************************\r
+ * New functions used for all STM32F10x devices to manage Bank1: *\r
+ * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 *\r
+ * - For other devices, these functions are optional (covered by functions listed above) *\r
+ ************************************************************************************************************************\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
+ | | devices | devices | |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation |\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+\r
+ *****************************************************************************\r
+ * New Functions used only with STM32F10x_XL density devices to manage Bank2 *\r
+ *****************************************************************************\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+ | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments |\r
+ | | devices | devices | |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ |FLASH_LockBank2 | Yes | No | - Lock Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation |\r
+ |----------------------------------------------------------------------------------------------------------------------------------|\r
+ | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 |\r
+ +----------------------------------------------------------------------------------------------------------------------------------+\r
+@endcode\r
+*/\r
+\r
+\r
+/**\r
+ * @brief Sets the code latency value.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_Latency: specifies the FLASH Latency value.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle\r
+ * @arg FLASH_Latency_1: FLASH One Latency cycle\r
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles\r
+ * @retval None\r
+ */\r
+void FLASH_SetLatency(uint32_t FLASH_Latency)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));\r
+ \r
+ /* Read the ACR register */\r
+ tmpreg = FLASH->ACR; \r
+ \r
+ /* Sets the Latency value */\r
+ tmpreg &= ACR_LATENCY_Mask;\r
+ tmpreg |= FLASH_Latency;\r
+ \r
+ /* Write the ACR register */\r
+ FLASH->ACR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Half cycle flash access.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable\r
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable\r
+ * @retval None\r
+ */\r
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess));\r
+ \r
+ /* Enable or disable the Half cycle access */\r
+ FLASH->ACR &= ACR_HLFCYA_Mask;\r
+ FLASH->ACR |= FLASH_HalfCycleAccess;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Prefetch Buffer.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable\r
+ * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable\r
+ * @retval None\r
+ */\r
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer));\r
+ \r
+ /* Enable or disable the Prefetch Buffer */\r
+ FLASH->ACR &= ACR_PRFTBE_Mask;\r
+ FLASH->ACR |= FLASH_PrefetchBuffer;\r
+}\r
+\r
+/**\r
+ * @brief Unlocks the FLASH Program Erase Controller.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2.\r
+ * - For all other devices it unlocks Bank1 and it is equivalent \r
+ * to FLASH_UnlockBank1 function.. \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Unlock(void)\r
+{\r
+ /* Authorize the FPEC of Bank1 Access */\r
+ FLASH->KEYR = FLASH_KEY1;\r
+ FLASH->KEYR = FLASH_KEY2;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Authorize the FPEC of Bank2 Access */\r
+ FLASH->KEYR2 = FLASH_KEY1;\r
+ FLASH->KEYR2 = FLASH_KEY2;\r
+#endif /* STM32F10X_XL */\r
+}\r
+/**\r
+ * @brief Unlocks the FLASH Bank1 Program Erase Controller.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function unlocks Bank1.\r
+ * - For all other devices it unlocks Bank1 and it is \r
+ * equivalent to FLASH_Unlock function.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_UnlockBank1(void)\r
+{\r
+ /* Authorize the FPEC of Bank1 Access */\r
+ FLASH->KEYR = FLASH_KEY1;\r
+ FLASH->KEYR = FLASH_KEY2;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Unlocks the FLASH Bank2 Program Erase Controller.\r
+ * @note This function can be used only for STM32F10X_XL density devices.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_UnlockBank2(void)\r
+{\r
+ /* Authorize the FPEC of Bank2 Access */\r
+ FLASH->KEYR2 = FLASH_KEY1;\r
+ FLASH->KEYR2 = FLASH_KEY2;\r
+\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Locks the FLASH Program Erase Controller.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function Locks Bank1 and Bank2.\r
+ * - For all other devices it Locks Bank1 and it is equivalent \r
+ * to FLASH_LockBank1 function.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_Lock(void)\r
+{\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
+ FLASH->CR |= CR_LOCK_Set;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
+ FLASH->CR2 |= CR_LOCK_Set;\r
+#endif /* STM32F10X_XL */\r
+}\r
+\r
+/**\r
+ * @brief Locks the FLASH Bank1 Program Erase Controller.\r
+ * @note this function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function Locks Bank1.\r
+ * - For all other devices it Locks Bank1 and it is equivalent \r
+ * to FLASH_Lock function.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_LockBank1(void)\r
+{\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */\r
+ FLASH->CR |= CR_LOCK_Set;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Locks the FLASH Bank2 Program Erase Controller.\r
+ * @note This function can be used only for STM32F10X_XL density devices.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void FLASH_LockBank2(void)\r
+{\r
+ /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */\r
+ FLASH->CR2 |= CR_LOCK_Set;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Erases a specified FLASH page.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Page_Address: The page address to be erased.\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Page_Address));\r
+\r
+#ifdef STM32F10X_XL\r
+ if(Page_Address < FLASH_BANK1_END_ADDRESS) \r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* if the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR|= CR_PER_Set;\r
+ FLASH->AR = Page_Address; \r
+ FLASH->CR|= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+\r
+ /* Disable the PER Bit */\r
+ FLASH->CR &= CR_PER_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* if the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR2|= CR_PER_Set;\r
+ FLASH->AR2 = Page_Address; \r
+ FLASH->CR2|= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ \r
+ /* Disable the PER Bit */\r
+ FLASH->CR2 &= CR_PER_Reset;\r
+ }\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* if the previous operation is completed, proceed to erase the page */\r
+ FLASH->CR|= CR_PER_Set;\r
+ FLASH->AR = Page_Address; \r
+ FLASH->CR|= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ /* Disable the PER Bit */\r
+ FLASH->CR &= CR_PER_Reset;\r
+ }\r
+#endif /* STM32F10X_XL */\r
+\r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erases all FLASH pages.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllPages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= CR_MER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ /* Disable the MER Bit */\r
+ FLASH->CR &= CR_MER_Reset;\r
+ } \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR2 |= CR_MER_Set;\r
+ FLASH->CR2 |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ \r
+ /* Disable the MER Bit */\r
+ FLASH->CR2 &= CR_MER_Reset;\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= CR_MER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+\r
+ /* Disable the MER Bit */\r
+ FLASH->CR &= CR_MER_Reset;\r
+ }\r
+#endif /* STM32F10X_XL */\r
+\r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Erases all Bank1 FLASH pages.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices this function erases all Bank1 pages.\r
+ * - For all other devices it erases all Bank1 pages and it is equivalent \r
+ * to FLASH_EraseAllPages function.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllBank1Pages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR |= CR_MER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(EraseTimeout);\r
+ \r
+ /* Disable the MER Bit */\r
+ FLASH->CR &= CR_MER_Reset;\r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Erases all Bank2 FLASH pages.\r
+ * @note This function can be used only for STM32F10x_XL density devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseAllBank2Pages(void)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to erase all pages */\r
+ FLASH->CR2 |= CR_MER_Set;\r
+ FLASH->CR2 |= CR_STRT_Set;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(EraseTimeout);\r
+\r
+ /* Disable the MER Bit */\r
+ FLASH->CR2 &= CR_MER_Reset;\r
+ } \r
+ /* Return the Erase Status */\r
+ return status;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Erases the FLASH option bytes.\r
+ * @note This functions erases all option bytes except the Read protection (RDP). \r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EraseOptionBytes(void)\r
+{\r
+ uint16_t rdptmp = RDP_Key;\r
+\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+\r
+ /* Get the actual read protection Option Byte value */ \r
+ if(FLASH_GetReadOutProtectionStatus() != RESET)\r
+ {\r
+ rdptmp = 0x00; \r
+ }\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* if the previous operation is completed, proceed to erase the option bytes */\r
+ FLASH->CR |= CR_OPTER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set;\r
+ /* Restore the last read protection Option Byte value */\r
+ OB->RDP = (uint16_t)rdptmp; \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (status != FLASH_TIMEOUT)\r
+ {\r
+ /* Disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ }\r
+ /* Return the erase status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a word at a specified address.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+\r
+#ifdef STM32F10X_XL\r
+ if(Address < FLASH_BANK1_END_ADDRESS - 2)\r
+ { \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout); \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ }\r
+ }\r
+ else if(Address == (FLASH_BANK1_END_ADDRESS - 1))\r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ FLASH->CR2 |= CR_PG_Set;\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR2 |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ }\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new first \r
+ half word */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = (uint16_t)Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new second \r
+ half word */\r
+ tmp = Address + 2;\r
+\r
+ *(__IO uint16_t*) tmp = Data >> 16;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ } \r
+#endif /* STM32F10X_XL */\r
+ \r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half word at a specified address.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Address: specifies the address to be programmed.\r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_ADDRESS(Address));\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(Address < FLASH_BANK1_END_ADDRESS)\r
+ {\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank1Operation(ProgramTimeout);\r
+\r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR2 |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastBank2Operation(ProgramTimeout);\r
+\r
+ /* Disable the PG Bit */\r
+ FLASH->CR2 &= CR_PG_Reset;\r
+ }\r
+ }\r
+#else\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the previous operation is completed, proceed to program the new data */\r
+ FLASH->CR |= CR_PG_Set;\r
+ \r
+ *(__IO uint16_t*)Address = Data;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ /* Disable the PG Bit */\r
+ FLASH->CR &= CR_PG_Reset;\r
+ } \r
+#endif /* STM32F10X_XL */\r
+ \r
+ /* Return the Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Programs a half word at a specified Option Byte Data address.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Address: specifies the address to be programmed.\r
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806. \r
+ * @param Data: specifies the data to be programmed.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. \r
+ */\r
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_DATA_ADDRESS(Address));\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ /* Enables the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ *(__IO uint16_t*)Address = Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ /* Return the Option Byte Data Program Status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Write protects the desired pages\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param FLASH_Pages: specifies the address of the pages to be write protected.\r
+ * This parameter can be:\r
+ * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 \r
+ * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3\r
+ * and FLASH_WRProt_Pages124to127\r
+ * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and\r
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255\r
+ * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and\r
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 \r
+ * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and\r
+ * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511\r
+ * @arg FLASH_WRProt_AllPages\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)\r
+{\r
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;\r
+ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages));\r
+ \r
+ FLASH_Pages = (uint32_t)(~FLASH_Pages);\r
+ WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);\r
+ WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);\r
+ WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);\r
+ WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorizes the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ FLASH->CR |= CR_OPTPG_Set;\r
+ if(WRP0_Data != 0xFF)\r
+ {\r
+ OB->WRP0 = WRP0_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))\r
+ {\r
+ OB->WRP1 = WRP1_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))\r
+ {\r
+ OB->WRP2 = WRP2_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ \r
+ if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF))\r
+ {\r
+ OB->WRP3 = WRP3_Data;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ }\r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the write protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the read out protection.\r
+ * @note If the user has already programmed the other option bytes before calling \r
+ * this function, he must re-program them since this function erases all option bytes.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param Newstate: new state of the ReadOut Protection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* Authorizes the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ FLASH->CR |= CR_OPTER_Set;\r
+ FLASH->CR |= CR_STRT_Set;\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout);\r
+ if(status == FLASH_COMPLETE)\r
+ {\r
+ /* if the erase operation is completed, disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ if(NewState != DISABLE)\r
+ {\r
+ OB->RDP = 0x00;\r
+ }\r
+ else\r
+ {\r
+ OB->RDP = RDP_Key; \r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(EraseTimeout); \r
+ \r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ }\r
+ else \r
+ {\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* Disable the OPTER Bit */\r
+ FLASH->CR &= CR_OPTER_Reset;\r
+ }\r
+ }\r
+ }\r
+ /* Return the protection operation Status */\r
+ return status; \r
+}\r
+\r
+/**\r
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param OB_IWDG: Selects the IWDG mode\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_IWDG_SW: Software IWDG selected\r
+ * @arg OB_IWDG_HW: Hardware IWDG selected\r
+ * @param OB_STOP: Reset event when entering STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP\r
+ * @arg OB_STOP_RST: Reset generated when entering in STOP\r
+ * @param OB_STDBY: Reset event when entering Standby mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY\r
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)\r
+{\r
+ FLASH_Status status = FLASH_COMPLETE; \r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));\r
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));\r
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));\r
+\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+ \r
+ OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); \r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Configures to boot from Bank1 or Bank2. \r
+ * @note This function can be used only for STM32F10x_XL density devices.\r
+ * @param FLASH_BOOT: select the FLASH Bank to boot from.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank1(Default).\r
+ * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash\r
+ * position and this parameter is selected the device will boot from Bank2 or Bank1,\r
+ * depending on the activation of the bank. The active banks are checked in\r
+ * the following order: Bank2, followed by Bank1.\r
+ * The active bank is recognized by the value programmed at the base address\r
+ * of the respective bank (corresponding to the initial stack pointer value\r
+ * in the interrupt vector table).\r
+ * For more information, please refer to AN2606 from www.st.com. \r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, \r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE; \r
+ assert_param(IS_FLASH_BOOT(FLASH_BOOT));\r
+ /* Authorize the small information block programming */\r
+ FLASH->OPTKEYR = FLASH_KEY1;\r
+ FLASH->OPTKEYR = FLASH_KEY2;\r
+ \r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ \r
+ if(status == FLASH_COMPLETE)\r
+ { \r
+ /* Enable the Option Bytes Programming operation */\r
+ FLASH->CR |= CR_OPTPG_Set; \r
+\r
+ if(FLASH_BOOT == FLASH_BOOT_Bank1)\r
+ {\r
+ OB->USER |= OB_USER_BFB2;\r
+ }\r
+ else\r
+ {\r
+ OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2));\r
+ }\r
+ /* Wait for last operation to be completed */\r
+ status = FLASH_WaitForLastOperation(ProgramTimeout);\r
+ if(status != FLASH_TIMEOUT)\r
+ {\r
+ /* if the program operation is completed, disable the OPTPG Bit */\r
+ FLASH->CR &= CR_OPTPG_Reset;\r
+ }\r
+ } \r
+ /* Return the Option Byte program Status */\r
+ return status;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @brief Returns the FLASH User Option Bytes values.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)\r
+ * and RST_STDBY(Bit2).\r
+ */\r
+uint32_t FLASH_GetUserOptionByte(void)\r
+{\r
+ /* Return the User Option Byte */\r
+ return (uint32_t)(FLASH->OBR >> 2);\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Write Protection Option Bytes Register value.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval The FLASH Write Protection Option Bytes Register value\r
+ */\r
+uint32_t FLASH_GetWriteProtectionOptionByte(void)\r
+{\r
+ /* Return the Falsh write protection Register value */\r
+ return (uint32_t)(FLASH->WRPR);\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Read Out Protection Status is set or not.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH ReadOut Protection Status(SET or RESET)\r
+ */\r
+FlagStatus FLASH_GetReadOutProtectionStatus(void)\r
+{\r
+ FlagStatus readoutstatus = RESET;\r
+ if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)\r
+ {\r
+ readoutstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ readoutstatus = RESET;\r
+ }\r
+ return readoutstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the FLASH Prefetch Buffer status is set or not.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * @param None\r
+ * @retval FLASH Prefetch Buffer Status (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetPrefetchBufferStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified FLASH interrupts.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts\r
+ for Bank1 and Bank2.\r
+ * - For other devices it enables or disables the specified FLASH interrupts for Bank1.\r
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FLASH_IT_ERROR: FLASH Error Interrupt\r
+ * @arg FLASH_IT_EOP: FLASH end of operation Interrupt\r
+ * @param NewState: new state of the specified Flash interrupts.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None \r
+ */\r
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)\r
+{\r
+#ifdef STM32F10X_XL\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if((FLASH_IT & 0x80000000) != 0x0)\r
+ {\r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+ }\r
+#else\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_IT(FLASH_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if(NewState != DISABLE)\r
+ {\r
+ /* Enable the interrupt sources */\r
+ FLASH->CR |= FLASH_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the interrupt sources */\r
+ FLASH->CR &= ~(uint32_t)FLASH_IT;\r
+ }\r
+#endif /* STM32F10X_XL */\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FLASH flag is set or not.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices, this function checks whether the specified \r
+ * Bank1 or Bank2 flag is set or not.\r
+ * - For other devices, it checks whether the specified Bank1 flag is \r
+ * set or not.\r
+ * @param FLASH_FLAG: specifies the FLASH flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FLASH_FLAG_BSY: FLASH Busy flag \r
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
+ * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag \r
+ * @retval The new state of FLASH_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+\r
+#ifdef STM32F10X_XL\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
+ {\r
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((FLASH_FLAG & 0x80000000) != 0x0)\r
+ {\r
+ if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ }\r
+#else\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ;\r
+ if(FLASH_FLAG == FLASH_FLAG_OPTERR) \r
+ {\r
+ if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+#endif /* STM32F10X_XL */\r
+\r
+ /* Return the new state of FLASH_FLAG (SET or RESET) */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the FLASH\92s pending flags.\r
+ * @note This function can be used for all STM32F10x devices.\r
+ * - For STM32F10X_XL devices, this function clears Bank1 or Bank2\92s pending flags\r
+ * - For other devices, it clears Bank1\92s pending flags.\r
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.\r
+ * This parameter can be any combination of the following values: \r
+ * @arg FLASH_FLAG_PGERR: FLASH Program error flag \r
+ * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag \r
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag \r
+ * @retval None\r
+ */\r
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)\r
+{\r
+#ifdef STM32F10X_XL\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
+\r
+ if((FLASH_FLAG & 0x80000000) != 0x0)\r
+ {\r
+ /* Clear the flags */\r
+ FLASH->SR2 = FLASH_FLAG;\r
+ }\r
+ else\r
+ {\r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+ } \r
+\r
+#else\r
+ /* Check the parameters */\r
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ;\r
+ \r
+ /* Clear the flags */\r
+ FLASH->SR = FLASH_FLAG;\r
+#endif /* STM32F10X_XL */\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Status.\r
+ * @note This function can be used for all STM32F10x devices, it is equivalent\r
+ * to FLASH_GetBank1Status function.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+FLASH_Status FLASH_GetStatus(void)\r
+{\r
+ FLASH_Status flashstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ flashstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & FLASH_FLAG_PGERR) != 0)\r
+ { \r
+ flashstatus = FLASH_ERROR_PG;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 )\r
+ {\r
+ flashstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else\r
+ {\r
+ flashstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Flash Status */\r
+ return flashstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the FLASH Bank1 Status.\r
+ * @note This function can be used for all STM32F10x devices, it is equivalent\r
+ * to FLASH_GetStatus function.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+FLASH_Status FLASH_GetBank1Status(void)\r
+{\r
+ FLASH_Status flashstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) \r
+ {\r
+ flashstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0)\r
+ { \r
+ flashstatus = FLASH_ERROR_PG;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 )\r
+ {\r
+ flashstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else\r
+ {\r
+ flashstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Flash Status */\r
+ return flashstatus;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Returns the FLASH Bank2 Status.\r
+ * @note This function can be used for STM32F10x_XL density devices.\r
+ * @param None\r
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP or FLASH_COMPLETE\r
+ */\r
+FLASH_Status FLASH_GetBank2Status(void)\r
+{\r
+ FLASH_Status flashstatus = FLASH_COMPLETE;\r
+ \r
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) \r
+ {\r
+ flashstatus = FLASH_BUSY;\r
+ }\r
+ else \r
+ { \r
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)\r
+ { \r
+ flashstatus = FLASH_ERROR_PG;\r
+ }\r
+ else \r
+ {\r
+ if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )\r
+ {\r
+ flashstatus = FLASH_ERROR_WRP;\r
+ }\r
+ else\r
+ {\r
+ flashstatus = FLASH_COMPLETE;\r
+ }\r
+ }\r
+ }\r
+ /* Return the Flash Status */\r
+ return flashstatus;\r
+}\r
+#endif /* STM32F10X_XL */\r
+/**\r
+ * @brief Waits for a Flash operation to complete or a TIMEOUT to occur.\r
+ * @note This function can be used for all STM32F10x devices, \r
+ * it is equivalent to FLASH_WaitForLastBank1Operation.\r
+ * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation\r
+ * to complete or a TIMEOUT to occur.\r
+ * - For all other devices it waits for a Flash operation to complete \r
+ * or a TIMEOUT to occur.\r
+ * @param Timeout: FLASH progamming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the Flash Status */\r
+ status = FLASH_GetBank1Status();\r
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_BUSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetBank1Status();\r
+ Timeout--;\r
+ }\r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.\r
+ * @note This function can be used for all STM32F10x devices, \r
+ * it is equivalent to FLASH_WaitForLastOperation.\r
+ * @param Timeout: FLASH progamming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the Flash Status */\r
+ status = FLASH_GetBank1Status();\r
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
+ while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetBank1Status();\r
+ Timeout--;\r
+ }\r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+\r
+#ifdef STM32F10X_XL\r
+/**\r
+ * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur.\r
+ * @note This function can be used only for STM32F10x_XL density devices.\r
+ * @param Timeout: FLASH progamming Timeout\r
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,\r
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.\r
+ */\r
+FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)\r
+{ \r
+ FLASH_Status status = FLASH_COMPLETE;\r
+ \r
+ /* Check for the Flash Status */\r
+ status = FLASH_GetBank2Status();\r
+ /* Wait for a Flash operation to complete or a TIMEOUT to occur */\r
+ while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))\r
+ {\r
+ status = FLASH_GetBank2Status();\r
+ Timeout--;\r
+ }\r
+ if(Timeout == 0x00 )\r
+ {\r
+ status = FLASH_TIMEOUT;\r
+ }\r
+ /* Return the operation status */\r
+ return status;\r
+}\r
+#endif /* STM32F10X_XL */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_fsmc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the FSMC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_fsmc.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup FSMC \r
+ * @brief FSMC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup FSMC_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* --------------------- FSMC registers bit mask ---------------------------- */\r
+\r
+/* FSMC BCRx Mask */\r
+#define BCR_MBKEN_Set ((uint32_t)0x00000001)\r
+#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)\r
+#define BCR_FACCEN_Set ((uint32_t)0x00000040)\r
+\r
+/* FSMC PCRx Mask */\r
+#define PCR_PBKEN_Set ((uint32_t)0x00000004)\r
+#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)\r
+#define PCR_ECCEN_Set ((uint32_t)0x00000040)\r
+#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)\r
+#define PCR_MemoryType_NAND ((uint32_t)0x00000008)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup FSMC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default \r
+ * reset values.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ \r
+ /* FSMC_Bank1_NORSRAM1 */\r
+ if(FSMC_Bank == FSMC_Bank1_NORSRAM1)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; \r
+ }\r
+ /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */\r
+ else\r
+ { \r
+ FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; \r
+ }\r
+ FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;\r
+ FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; \r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND \r
+ * @retval None\r
+ */\r
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)\r
+{\r
+ /* Check the parameter */\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* Set the FSMC_Bank2 registers to their reset values */\r
+ FSMC_Bank2->PCR2 = 0x00000018;\r
+ FSMC_Bank2->SR2 = 0x00000040;\r
+ FSMC_Bank2->PMEM2 = 0xFCFCFCFC;\r
+ FSMC_Bank2->PATT2 = 0xFCFCFCFC; \r
+ }\r
+ /* FSMC_Bank3_NAND */ \r
+ else\r
+ {\r
+ /* Set the FSMC_Bank3 registers to their reset values */\r
+ FSMC_Bank3->PCR3 = 0x00000018;\r
+ FSMC_Bank3->SR3 = 0x00000040;\r
+ FSMC_Bank3->PMEM3 = 0xFCFCFCFC;\r
+ FSMC_Bank3->PATT3 = 0xFCFCFCFC; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDDeInit(void)\r
+{\r
+ /* Set the FSMC_Bank4 registers to their reset values */\r
+ FSMC_Bank4->PCR4 = 0x00000018; \r
+ FSMC_Bank4->SR4 = 0x00000000; \r
+ FSMC_Bank4->PMEM4 = 0xFCFCFCFC;\r
+ FSMC_Bank4->PATT4 = 0xFCFCFCFC;\r
+ FSMC_Bank4->PIO4 = 0xFCFCFCFC;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC NOR/SRAM Banks according to the specified\r
+ * parameters in the FSMC_NORSRAMInitStruct.\r
+ * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef\r
+ * structure that contains the configuration information for \r
+ * the FSMC NOR/SRAM specified Banks. \r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));\r
+ assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));\r
+ assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));\r
+ assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));\r
+ assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));\r
+ assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));\r
+ assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));\r
+ assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));\r
+ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));\r
+ assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));\r
+ assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));\r
+ assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));\r
+ assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); \r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); \r
+ \r
+ /* Bank1 NOR/SRAM control register configuration */ \r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType |\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation |\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal |\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst;\r
+\r
+ if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)\r
+ {\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;\r
+ }\r
+ \r
+ /* Bank1 NOR/SRAM timing register configuration */\r
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;\r
+ \r
+ \r
+ /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */\r
+ if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)\r
+ {\r
+ assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));\r
+ assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));\r
+ assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));\r
+ assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));\r
+ assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));\r
+ assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = \r
+ (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |\r
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC NAND Banks according to the specified \r
+ * parameters in the FSMC_NANDInitStruct.\r
+ * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef \r
+ * structure that contains the configuration information for the FSMC NAND specified Banks. \r
+ * @retval None\r
+ */\r
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
+{\r
+ uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; \r
+ \r
+ /* Check the parameters */\r
+ assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));\r
+ assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));\r
+ assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));\r
+ assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));\r
+ assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));\r
+ assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));\r
+ assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */\r
+ tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |\r
+ PCR_MemoryType_NAND |\r
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |\r
+ FSMC_NANDInitStruct->FSMC_ECC |\r
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |\r
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|\r
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);\r
+ \r
+ /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */\r
+ tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */\r
+ tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);\r
+ \r
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* FSMC_Bank2_NAND registers configuration */\r
+ FSMC_Bank2->PCR2 = tmppcr;\r
+ FSMC_Bank2->PMEM2 = tmppmem;\r
+ FSMC_Bank2->PATT2 = tmppatt;\r
+ }\r
+ else\r
+ {\r
+ /* FSMC_Bank3_NAND registers configuration */\r
+ FSMC_Bank3->PCR3 = tmppcr;\r
+ FSMC_Bank3->PMEM3 = tmppmem;\r
+ FSMC_Bank3->PATT3 = tmppatt;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the FSMC PCCARD Bank according to the specified \r
+ * parameters in the FSMC_PCCARDInitStruct.\r
+ * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef\r
+ * structure that contains the configuration information for the FSMC PCCARD Bank. \r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));\r
+ assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));\r
+ assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));\r
+ \r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));\r
+ assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));\r
+ assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));\r
+ assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));\r
+ \r
+ /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */\r
+ FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |\r
+ FSMC_MemoryDataWidth_16b | \r
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |\r
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);\r
+ \r
+ /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+ \r
+ /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */\r
+ FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|\r
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); \r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.\r
+ * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)\r
+{ \r
+ /* Reset NOR/SRAM Init structure parameters values */\r
+ FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;\r
+ FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;\r
+ FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
+ FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;\r
+ FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; \r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;\r
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;\r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_NANDInitStruct member with its default value.\r
+ * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)\r
+{ \r
+ /* Reset NAND Init structure parameters values */\r
+ FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;\r
+ FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;\r
+ FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;\r
+ FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;\r
+ FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
+ FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
+}\r
+\r
+/**\r
+ * @brief Fills each FSMC_PCCARDInitStruct member with its default value.\r
+ * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)\r
+{\r
+ /* Reset PCCARD Init structure parameters values */\r
+ FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;\r
+ FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;\r
+ FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; \r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;\r
+ FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified NOR/SRAM Memory Bank.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 \r
+ * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 \r
+ * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 \r
+ * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 \r
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */\r
+ FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified NAND Memory Bank.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PCCARD Memory Bank.\r
+ * @param NewState: new state of the PCCARD Memory Bank. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_PCCARDCmd(FunctionalState NewState)\r
+{\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */\r
+ FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */\r
+ FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the FSMC NAND ECC feature.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @param NewState: new state of the FSMC NAND ECC feature. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;\r
+ }\r
+ else\r
+ {\r
+ FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the error correction code register value.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @retval The Error Correction Code (ECC) value.\r
+ */\r
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)\r
+{\r
+ uint32_t eccval = 0x00000000;\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ /* Get the ECCR2 register value */\r
+ eccval = FSMC_Bank2->ECCR2;\r
+ }\r
+ else\r
+ {\r
+ /* Get the ECCR3 register value */\r
+ eccval = FSMC_Bank3->ECCR3;\r
+ }\r
+ /* Return the error correction code value */\r
+ return(eccval);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified FSMC interrupts.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
+ * @param NewState: new state of the specified FSMC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)\r
+{\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_IT(FSMC_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected FSMC_Bank2 interrupts */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 |= FSMC_IT;\r
+ }\r
+ /* Enable the selected FSMC_Bank3 interrupts */\r
+ else if (FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 |= FSMC_IT;\r
+ }\r
+ /* Enable the selected FSMC_Bank4 interrupts */\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 |= FSMC_IT; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected FSMC_Bank2 interrupts */\r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ \r
+ FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;\r
+ }\r
+ /* Disable the selected FSMC_Bank3 interrupts */\r
+ else if (FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;\r
+ }\r
+ /* Disable the selected FSMC_Bank4 interrupts */\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; \r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FSMC flag is set or not.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
+ * @arg FSMC_FLAG_Level: Level detection Flag.\r
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
+ * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. \r
+ * @retval The new state of FSMC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ uint32_t tmpsr = 0x00000000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank2->SR2;\r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank3->SR3;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ tmpsr = FSMC_Bank4->SR4;\r
+ } \r
+ \r
+ /* Get the flag status */\r
+ if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the FSMC\92s pending flags.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.\r
+ * @arg FSMC_FLAG_Level: Level detection Flag.\r
+ * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.\r
+ * @retval None\r
+ */\r
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 &= ~FSMC_FLAG; \r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= ~FSMC_FLAG;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= ~FSMC_FLAG;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified FSMC interrupt has occurred or not.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the FSMC interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. \r
+ * @retval The new state of FSMC_IT (SET or RESET).\r
+ */\r
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; \r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_GET_IT(FSMC_IT));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank2->SR2;\r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ tmpsr = FSMC_Bank3->SR3;\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ tmpsr = FSMC_Bank4->SR4;\r
+ } \r
+ \r
+ itstatus = tmpsr & FSMC_IT;\r
+ \r
+ itenable = tmpsr & (FSMC_IT >> 3);\r
+ if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the FSMC\92s interrupt pending bits.\r
+ * @param FSMC_Bank: specifies the FSMC Bank to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND \r
+ * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND\r
+ * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD\r
+ * @param FSMC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. \r
+ * @arg FSMC_IT_Level: Level edge detection interrupt.\r
+ * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.\r
+ * @retval None\r
+ */\r
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FSMC_IT_BANK(FSMC_Bank));\r
+ assert_param(IS_FSMC_IT(FSMC_IT));\r
+ \r
+ if(FSMC_Bank == FSMC_Bank2_NAND)\r
+ {\r
+ FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); \r
+ } \r
+ else if(FSMC_Bank == FSMC_Bank3_NAND)\r
+ {\r
+ FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);\r
+ }\r
+ /* FSMC_Bank4_PCCARD*/\r
+ else\r
+ {\r
+ FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);\r
+ }\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_gpio.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the GPIO firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_gpio.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup GPIO \r
+ * @brief GPIO driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup GPIO_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------------*/\r
+#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)\r
+\r
+/* --- EVENTCR Register -----*/\r
+\r
+/* Alias word address of EVOE bit */\r
+#define EVCR_OFFSET (AFIO_OFFSET + 0x00)\r
+#define EVOE_BitNumber ((uint8_t)0x07)\r
+#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4))\r
+\r
+\r
+/* --- MAPR Register ---*/ \r
+/* Alias word address of MII_RMII_SEL bit */ \r
+#define MAPR_OFFSET (AFIO_OFFSET + 0x04) \r
+#define MII_RMII_SEL_BitNumber ((u8)0x17) \r
+#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))\r
+\r
+\r
+#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)\r
+#define LSB_MASK ((uint16_t)0xFFFF)\r
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)\r
+#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)\r
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)\r
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup GPIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset values.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ if (GPIOx == GPIOA)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOB)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOC)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);\r
+ }\r
+ else if (GPIOx == GPIOD)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);\r
+ } \r
+ else if (GPIOx == GPIOE)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);\r
+ } \r
+ else if (GPIOx == GPIOF)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (GPIOx == GPIOG)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Deinitializes the Alternate Functions (remap, event control\r
+ * and EXTI configuration) registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void GPIO_AFIODeInit(void)\r
+{\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the GPIOx peripheral according to the specified\r
+ * parameters in the GPIO_InitStruct.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that\r
+ * contains the configuration information for the specified GPIO peripheral.\r
+ * @retval None\r
+ */\r
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;\r
+ uint32_t tmpreg = 0x00, pinmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));\r
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); \r
+ \r
+/*---------------------------- GPIO Mode Configuration -----------------------*/\r
+ currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);\r
+ if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)\r
+ { \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));\r
+ /* Output mode */\r
+ currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;\r
+ }\r
+/*---------------------------- GPIO CRL Configuration ------------------------*/\r
+ /* Configure the eight low port pins */\r
+ if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)\r
+ {\r
+ tmpreg = GPIOx->CRL;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = ((uint32_t)0x01) << pinpos;\r
+ /* Get the port pins position */\r
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding low control register bits */\r
+ pinmask = ((uint32_t)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((uint32_t)0x01) << pinpos);\r
+ }\r
+ else\r
+ {\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((uint32_t)0x01) << pinpos);\r
+ }\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRL = tmpreg;\r
+ }\r
+/*---------------------------- GPIO CRH Configuration ------------------------*/\r
+ /* Configure the eight high port pins */\r
+ if (GPIO_InitStruct->GPIO_Pin > 0x00FF)\r
+ {\r
+ tmpreg = GPIOx->CRH;\r
+ for (pinpos = 0x00; pinpos < 0x08; pinpos++)\r
+ {\r
+ pos = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ /* Get the port pins position */\r
+ currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);\r
+ if (currentpin == pos)\r
+ {\r
+ pos = pinpos << 2;\r
+ /* Clear the corresponding high control register bits */\r
+ pinmask = ((uint32_t)0x0F) << pos;\r
+ tmpreg &= ~pinmask;\r
+ /* Write the mode configuration in the corresponding bits */\r
+ tmpreg |= (currentmode << pos);\r
+ /* Reset the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)\r
+ {\r
+ GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ }\r
+ /* Set the corresponding ODR bit */\r
+ if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)\r
+ {\r
+ GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08));\r
+ }\r
+ }\r
+ }\r
+ GPIOx->CRH = tmpreg;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Fills each GPIO_InitStruct member with its default value.\r
+ * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)\r
+{\r
+ /* Reset GPIO init structure parameters values */\r
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;\r
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;\r
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified input port pin.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The input port pin value.\r
+ */\r
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO input data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval GPIO input data port value.\r
+ */\r
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->IDR);\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified output data port bit.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to read.\r
+ * This parameter can be GPIO_Pin_x where x can be (0..15).\r
+ * @retval The output port pin value.\r
+ */\r
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint8_t bitstatus = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); \r
+ \r
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)\r
+ {\r
+ bitstatus = (uint8_t)Bit_SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = (uint8_t)Bit_RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified GPIO output data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @retval GPIO output data port value.\r
+ */\r
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ return ((uint16_t)GPIOx->ODR);\r
+}\r
+\r
+/**\r
+ * @brief Sets the selected data port bits.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BSRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Clears the selected data port bits.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bits to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ GPIOx->BRR = GPIO_Pin;\r
+}\r
+\r
+/**\r
+ * @brief Sets or clears the selected data port bit.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be one of GPIO_Pin_x where x can be (0..15).\r
+ * @param BitVal: specifies the value to be written to the selected bit.\r
+ * This parameter can be one of the BitAction enum values:\r
+ * @arg Bit_RESET: to clear the port pin\r
+ * @arg Bit_SET: to set the port pin\r
+ * @retval None\r
+ */\r
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));\r
+ assert_param(IS_GPIO_BIT_ACTION(BitVal)); \r
+ \r
+ if (BitVal != Bit_RESET)\r
+ {\r
+ GPIOx->BSRR = GPIO_Pin;\r
+ }\r
+ else\r
+ {\r
+ GPIOx->BRR = GPIO_Pin;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Writes data to the specified GPIO data port.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param PortVal: specifies the value to be written to the port output data register.\r
+ * @retval None\r
+ */\r
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ \r
+ GPIOx->ODR = PortVal;\r
+}\r
+\r
+/**\r
+ * @brief Locks GPIO Pins configuration registers.\r
+ * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.\r
+ * @param GPIO_Pin: specifies the port bit to be written.\r
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\r
+{\r
+ uint32_t tmp = 0x00010000;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));\r
+ assert_param(IS_GPIO_PIN(GPIO_Pin));\r
+ \r
+ tmp |= GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Reset LCKK bit */\r
+ GPIOx->LCKR = GPIO_Pin;\r
+ /* Set LCKK bit */\r
+ GPIOx->LCKR = tmp;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+ /* Read LCKK bit*/\r
+ tmp = GPIOx->LCKR;\r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as Event output.\r
+ * @param GPIO_PortSource: selects the GPIO port to be used as source\r
+ * for Event output.\r
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).\r
+ * @param GPIO_PinSource: specifies the pin for the Event output.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmpreg = AFIO->EVCR;\r
+ /* Clear the PORT[6:4] and PIN[3:0] bits */\r
+ tmpreg &= EVCR_PORTPINCONFIG_MASK;\r
+ tmpreg |= (uint32_t)GPIO_PortSource << 0x04;\r
+ tmpreg |= GPIO_PinSource;\r
+ AFIO->EVCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Event Output.\r
+ * @param NewState: new state of the Event output.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void GPIO_EventOutputCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Changes the mapping of the specified pin.\r
+ * @param GPIO_Remap: selects the pin to remap.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping\r
+ * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping\r
+ * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping\r
+ * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping\r
+ * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping\r
+ * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping\r
+ * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping\r
+ * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping\r
+ * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping\r
+ * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping\r
+ * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping\r
+ * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping\r
+ * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping\r
+ * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping\r
+ * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping\r
+ * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping\r
+ * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping\r
+ * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration\r
+ * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping\r
+ * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping\r
+ * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping\r
+ * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping\r
+ * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST\r
+ * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled\r
+ * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)\r
+ * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected\r
+ * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)\r
+ * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to \r
+ * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. \r
+ * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)\r
+ * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)\r
+ * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)\r
+ * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)\r
+ * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)\r
+ * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)\r
+ * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)\r
+ * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)\r
+ * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)\r
+ * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)\r
+ * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \r
+ * only for High density Value line devices) \r
+ * @param NewState: new state of the port pin remapping.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)\r
+{\r
+ uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_REMAP(GPIO_Remap));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if((GPIO_Remap & 0x80000000) == 0x80000000)\r
+ {\r
+ tmpreg = AFIO->MAPR2;\r
+ }\r
+ else\r
+ {\r
+ tmpreg = AFIO->MAPR;\r
+ }\r
+\r
+ tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;\r
+ tmp = GPIO_Remap & LSB_MASK;\r
+\r
+ if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))\r
+ {\r
+ tmpreg &= DBGAFR_SWJCFG_MASK;\r
+ AFIO->MAPR &= DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)\r
+ {\r
+ tmp1 = ((uint32_t)0x03) << tmpmask;\r
+ tmpreg &= ~tmp1;\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+ else\r
+ {\r
+ tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ tmpreg |= ~DBGAFR_SWJCFG_MASK;\r
+ }\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));\r
+ }\r
+\r
+ if((GPIO_Remap & 0x80000000) == 0x80000000)\r
+ {\r
+ AFIO->MAPR2 = tmpreg;\r
+ }\r
+ else\r
+ {\r
+ AFIO->MAPR = tmpreg;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Selects the GPIO pin used as EXTI Line.\r
+ * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.\r
+ * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).\r
+ * @param GPIO_PinSource: specifies the EXTI line to be configured.\r
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).\r
+ * @retval None\r
+ */\r
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)\r
+{\r
+ uint32_t tmp = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource));\r
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));\r
+ \r
+ tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;\r
+ AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));\r
+}\r
+\r
+/**\r
+ * @brief Selects the Ethernet media interface.\r
+ * @note This function applies only to STM32 Connectivity line devices. \r
+ * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg GPIO_ETH_MediaInterface_MII: MII mode\r
+ * @arg GPIO_ETH_MediaInterface_RMII: RMII mode \r
+ * @retval None\r
+ */\r
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) \r
+{ \r
+ assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); \r
+\r
+ /* Configure MII_RMII selection bit */ \r
+ *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; \r
+}\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_i2c.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the I2C firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_i2c.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup I2C \r
+ * @brief I2C driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup I2C_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* I2C SPE mask */\r
+#define CR1_PE_Set ((uint16_t)0x0001)\r
+#define CR1_PE_Reset ((uint16_t)0xFFFE)\r
+\r
+/* I2C START mask */\r
+#define CR1_START_Set ((uint16_t)0x0100)\r
+#define CR1_START_Reset ((uint16_t)0xFEFF)\r
+\r
+/* I2C STOP mask */\r
+#define CR1_STOP_Set ((uint16_t)0x0200)\r
+#define CR1_STOP_Reset ((uint16_t)0xFDFF)\r
+\r
+/* I2C ACK mask */\r
+#define CR1_ACK_Set ((uint16_t)0x0400)\r
+#define CR1_ACK_Reset ((uint16_t)0xFBFF)\r
+\r
+/* I2C ENGC mask */\r
+#define CR1_ENGC_Set ((uint16_t)0x0040)\r
+#define CR1_ENGC_Reset ((uint16_t)0xFFBF)\r
+\r
+/* I2C SWRST mask */\r
+#define CR1_SWRST_Set ((uint16_t)0x8000)\r
+#define CR1_SWRST_Reset ((uint16_t)0x7FFF)\r
+\r
+/* I2C PEC mask */\r
+#define CR1_PEC_Set ((uint16_t)0x1000)\r
+#define CR1_PEC_Reset ((uint16_t)0xEFFF)\r
+\r
+/* I2C ENPEC mask */\r
+#define CR1_ENPEC_Set ((uint16_t)0x0020)\r
+#define CR1_ENPEC_Reset ((uint16_t)0xFFDF)\r
+\r
+/* I2C ENARP mask */\r
+#define CR1_ENARP_Set ((uint16_t)0x0010)\r
+#define CR1_ENARP_Reset ((uint16_t)0xFFEF)\r
+\r
+/* I2C NOSTRETCH mask */\r
+#define CR1_NOSTRETCH_Set ((uint16_t)0x0080)\r
+#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)\r
+\r
+/* I2C registers Masks */\r
+#define CR1_CLEAR_Mask ((uint16_t)0xFBF5)\r
+\r
+/* I2C DMAEN mask */\r
+#define CR2_DMAEN_Set ((uint16_t)0x0800)\r
+#define CR2_DMAEN_Reset ((uint16_t)0xF7FF)\r
+\r
+/* I2C LAST mask */\r
+#define CR2_LAST_Set ((uint16_t)0x1000)\r
+#define CR2_LAST_Reset ((uint16_t)0xEFFF)\r
+\r
+/* I2C FREQ mask */\r
+#define CR2_FREQ_Reset ((uint16_t)0xFFC0)\r
+\r
+/* I2C ADD0 mask */\r
+#define OAR1_ADD0_Set ((uint16_t)0x0001)\r
+#define OAR1_ADD0_Reset ((uint16_t)0xFFFE)\r
+\r
+/* I2C ENDUAL mask */\r
+#define OAR2_ENDUAL_Set ((uint16_t)0x0001)\r
+#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE)\r
+\r
+/* I2C ADD2 mask */\r
+#define OAR2_ADD2_Reset ((uint16_t)0xFF01)\r
+\r
+/* I2C F/S mask */\r
+#define CCR_FS_Set ((uint16_t)0x8000)\r
+\r
+/* I2C CCR mask */\r
+#define CCR_CCR_Set ((uint16_t)0x0FFF)\r
+\r
+/* I2C FLAG mask */\r
+#define FLAG_Mask ((uint32_t)0x00FFFFFF)\r
+\r
+/* I2C Interrupt Enable mask */\r
+#define ITEN_Mask ((uint32_t)0x07000000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup I2C_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the I2Cx peripheral registers to their default reset values.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_DeInit(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ if (I2Cx == I2C1)\r
+ {\r
+ /* Enable I2C1 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);\r
+ /* Release I2C1 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ /* Enable I2C2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);\r
+ /* Release I2C2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the I2Cx peripheral according to the specified \r
+ * parameters in the I2C_InitStruct.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that\r
+ * contains the configuration information for the specified I2C peripheral.\r
+ * @retval None\r
+ */\r
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, freqrange = 0;\r
+ uint16_t result = 0x04;\r
+ uint32_t pclk1 = 8000000;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed));\r
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));\r
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));\r
+ assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));\r
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));\r
+\r
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/\r
+ /* Get the I2Cx CR2 value */\r
+ tmpreg = I2Cx->CR2;\r
+ /* Clear frequency FREQ[5:0] bits */\r
+ tmpreg &= CR2_FREQ_Reset;\r
+ /* Get pclk1 frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ pclk1 = rcc_clocks.PCLK1_Frequency;\r
+ /* Set frequency bits depending on pclk1 value */\r
+ freqrange = (uint16_t)(pclk1 / 1000000);\r
+ tmpreg |= freqrange;\r
+ /* Write to I2Cx CR2 */\r
+ I2Cx->CR2 = tmpreg;\r
+\r
+/*---------------------------- I2Cx CCR Configuration ------------------------*/\r
+ /* Disable the selected I2C peripheral to configure TRISE */\r
+ I2Cx->CR1 &= CR1_PE_Reset;\r
+ /* Reset tmpreg value */\r
+ /* Clear F/S, DUTY and CCR[11:0] bits */\r
+ tmpreg = 0;\r
+\r
+ /* Configure speed in standard mode */\r
+ if (I2C_InitStruct->I2C_ClockSpeed <= 100000)\r
+ {\r
+ /* Standard mode speed calculate */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));\r
+ /* Test if CCR value is under 0x4*/\r
+ if (result < 0x04)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result = 0x04; \r
+ }\r
+ /* Set speed value for standard mode */\r
+ tmpreg |= result; \r
+ /* Set Maximum Rise Time for standard mode */\r
+ I2Cx->TRISE = freqrange + 1; \r
+ }\r
+ /* Configure speed in fast mode */\r
+ else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/\r
+ {\r
+ if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 2 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));\r
+ }\r
+ else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/\r
+ {\r
+ /* Fast mode speed calculate: Tlow/Thigh = 16/9 */\r
+ result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));\r
+ /* Set DUTY bit */\r
+ result |= I2C_DutyCycle_16_9;\r
+ }\r
+\r
+ /* Test if CCR value is under 0x1*/\r
+ if ((result & CCR_CCR_Set) == 0)\r
+ {\r
+ /* Set minimum allowed value */\r
+ result |= (uint16_t)0x0001; \r
+ }\r
+ /* Set speed value and set F/S bit for fast mode */\r
+ tmpreg |= (uint16_t)(result | CCR_FS_Set);\r
+ /* Set Maximum Rise Time for fast mode */\r
+ I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); \r
+ }\r
+\r
+ /* Write to I2Cx CCR */\r
+ I2Cx->CCR = tmpreg;\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+\r
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/\r
+ /* Get the I2Cx CR1 value */\r
+ tmpreg = I2Cx->CR1;\r
+ /* Clear ACK, SMBTYPE and SMBUS bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure I2Cx: mode and acknowledgement */\r
+ /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */\r
+ /* Set ACK bit according to I2C_Ack value */\r
+ tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);\r
+ /* Write to I2Cx CR1 */\r
+ I2Cx->CR1 = tmpreg;\r
+\r
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/\r
+ /* Set I2Cx Own Address1 and acknowledged address */\r
+ I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2C_InitStruct member with its default value.\r
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)\r
+{\r
+/*---------------- Reset I2C init structure parameters values ----------------*/\r
+ /* initialize the I2C_ClockSpeed member */\r
+ I2C_InitStruct->I2C_ClockSpeed = 5000;\r
+ /* Initialize the I2C_Mode member */\r
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;\r
+ /* Initialize the I2C_DutyCycle member */\r
+ I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;\r
+ /* Initialize the I2C_OwnAddress1 member */\r
+ I2C_InitStruct->I2C_OwnAddress1 = 0;\r
+ /* Initialize the I2C_Ack member */\r
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;\r
+ /* Initialize the I2C_AcknowledgedAddress member */\r
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C peripheral */\r
+ I2Cx->CR1 |= CR1_PE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C peripheral */\r
+ I2Cx->CR1 &= CR1_PE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C DMA requests.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C DMA requests */\r
+ I2Cx->CR2 |= CR2_DMAEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C DMA requests */\r
+ I2Cx->CR2 &= CR2_DMAEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Specifies if the next DMA transfer will be the last one.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C DMA last transfer.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Next DMA transfer is the last transfer */\r
+ I2Cx->CR2 |= CR2_LAST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Next DMA transfer is not the last transfer */\r
+ I2Cx->CR2 &= CR2_LAST_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication START condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C START condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a START condition */\r
+ I2Cx->CR1 |= CR1_START_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the START condition generation */\r
+ I2Cx->CR1 &= CR1_START_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Generates I2Cx communication STOP condition.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C STOP condition generation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Generate a STOP condition */\r
+ I2Cx->CR1 |= CR1_STOP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the STOP condition generation */\r
+ I2Cx->CR1 &= CR1_STOP_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C acknowledge feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C Acknowledgement.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None.\r
+ */\r
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the acknowledgement */\r
+ I2Cx->CR1 |= CR1_ACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the acknowledgement */\r
+ I2Cx->CR1 &= CR1_ACK_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified I2C own address2.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the 7bit I2C own address2.\r
+ * @retval None.\r
+ */\r
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)\r
+{\r
+ uint16_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Get the old register value */\r
+ tmpreg = I2Cx->OAR2;\r
+\r
+ /* Reset I2Cx Own address2 bit [7:1] */\r
+ tmpreg &= OAR2_ADD2_Reset;\r
+\r
+ /* Set I2Cx Own address2 */\r
+ tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);\r
+\r
+ /* Store the new register value */\r
+ I2Cx->OAR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C dual addressing mode.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C dual addressing mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable dual addressing mode */\r
+ I2Cx->OAR2 |= OAR2_ENDUAL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable dual addressing mode */\r
+ I2Cx->OAR2 &= OAR2_ENDUAL_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C general call feature.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C General call.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable generall call */\r
+ I2Cx->CR1 |= CR1_ENGC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable generall call */\r
+ I2Cx->CR1 &= CR1_ENGC_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C interrupts.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_BUF: Buffer interrupt mask\r
+ * @arg I2C_IT_EVT: Event interrupt mask\r
+ * @arg I2C_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified I2C interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C interrupts */\r
+ I2Cx->CR2 |= I2C_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C interrupts */\r
+ I2Cx->CR2 &= (uint16_t)~I2C_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sends a data byte through the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Data: Byte to be transmitted..\r
+ * @retval None\r
+ */\r
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Write in the DR register the data to be sent */\r
+ I2Cx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the I2Cx peripheral.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The value of the received data.\r
+ */\r
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the data in the DR register */\r
+ return (uint8_t)I2Cx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Transmits the address byte to select the slave device.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param Address: specifies the slave address which will be transmitted\r
+ * @param I2C_Direction: specifies whether the I2C device will be a\r
+ * Transmitter or a Receiver. This parameter can be one of the following values\r
+ * @arg I2C_Direction_Transmitter: Transmitter mode\r
+ * @arg I2C_Direction_Receiver: Receiver mode\r
+ * @retval None.\r
+ */\r
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));\r
+ /* Test on the direction to set/reset the read/write bit */\r
+ if (I2C_Direction != I2C_Direction_Transmitter)\r
+ {\r
+ /* Set the address bit0 for read */\r
+ Address |= OAR1_ADD0_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the address bit0 for write */\r
+ Address &= OAR1_ADD0_Reset;\r
+ }\r
+ /* Send the address */\r
+ I2Cx->DR = Address;\r
+}\r
+\r
+/**\r
+ * @brief Reads the specified I2C register and returns its value.\r
+ * @param I2C_Register: specifies the register to read.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_Register_CR1: CR1 register.\r
+ * @arg I2C_Register_CR2: CR2 register.\r
+ * @arg I2C_Register_OAR1: OAR1 register.\r
+ * @arg I2C_Register_OAR2: OAR2 register.\r
+ * @arg I2C_Register_DR: DR register.\r
+ * @arg I2C_Register_SR1: SR1 register.\r
+ * @arg I2C_Register_SR2: SR2 register.\r
+ * @arg I2C_Register_CCR: CCR register.\r
+ * @arg I2C_Register_TRISE: TRISE register.\r
+ * @retval The value of the read register.\r
+ */\r
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_REGISTER(I2C_Register));\r
+\r
+ tmp = (uint32_t) I2Cx;\r
+ tmp += I2C_Register;\r
+\r
+ /* Return the selected register value */\r
+ return (*(__IO uint16_t *) tmp);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C software reset.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C software reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Peripheral under reset */\r
+ I2Cx->CR1 |= CR1_SWRST_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Peripheral not under reset */\r
+ I2Cx->CR1 &= CR1_SWRST_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Drives the SMBusAlert pin high or low for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_SMBusAlert: specifies SMBAlert pin level. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low\r
+ * @arg I2C_SMBusAlert_High: SMBAlert pin driven high\r
+ * @retval None\r
+ */\r
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));\r
+ if (I2C_SMBusAlert == I2C_SMBusAlert_Low)\r
+ {\r
+ /* Drive the SMBusAlert pin Low */\r
+ I2Cx->CR1 |= I2C_SMBusAlert_Low;\r
+ }\r
+ else\r
+ {\r
+ /* Drive the SMBusAlert pin High */\r
+ I2Cx->CR1 &= I2C_SMBusAlert_High;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C PEC transfer.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2C PEC transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC transmission */\r
+ I2Cx->CR1 |= CR1_PEC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC transmission */\r
+ I2Cx->CR1 &= CR1_PEC_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C PEC position.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_PECPosition: specifies the PEC position. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_PECPosition_Next: indicates that the next byte is PEC\r
+ * @arg I2C_PECPosition_Current: indicates that current byte is PEC\r
+ * @retval None\r
+ */\r
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));\r
+ if (I2C_PECPosition == I2C_PECPosition_Next)\r
+ {\r
+ /* Next byte in shift register is PEC */\r
+ I2Cx->CR1 |= I2C_PECPosition_Next;\r
+ }\r
+ else\r
+ {\r
+ /* Current byte in shift register is PEC */\r
+ I2Cx->CR1 &= I2C_PECPosition_Current;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PEC value calculation of the transfered bytes.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx PEC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C PEC calculation */\r
+ I2Cx->CR1 |= CR1_ENPEC_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C PEC calculation */\r
+ I2Cx->CR1 &= CR1_ENPEC_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the PEC value for the specified I2C.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @retval The PEC value.\r
+ */\r
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ /* Return the selected I2C PEC value */\r
+ return ((I2Cx->SR2) >> 8);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C ARP.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx ARP. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected I2C ARP */\r
+ I2Cx->CR1 |= CR1_ENARP_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C ARP */\r
+ I2Cx->CR1 &= CR1_ENARP_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified I2C Clock stretching.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param NewState: new state of the I2Cx Clock stretching.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState == DISABLE)\r
+ {\r
+ /* Enable the selected I2C Clock stretching */\r
+ I2Cx->CR1 |= CR1_NOSTRETCH_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected I2C Clock stretching */\r
+ I2Cx->CR1 &= CR1_NOSTRETCH_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified I2C fast mode duty cycle.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_DutyCycle: specifies the fast mode duty cycle.\r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2\r
+ * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9\r
+ * @retval None\r
+ */\r
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));\r
+ if (I2C_DutyCycle != I2C_DutyCycle_16_9)\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=2 */\r
+ I2Cx->CCR &= I2C_DutyCycle_2;\r
+ }\r
+ else\r
+ {\r
+ /* I2C fast mode Tlow/Thigh=16/9 */\r
+ I2Cx->CCR |= I2C_DutyCycle_16_9;\r
+ }\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief\r
+ ****************************************************************************************\r
+ *\r
+ * I2C State Monitoring Functions\r
+ * \r
+ **************************************************************************************** \r
+ * This I2C driver provides three different ways for I2C state monitoring\r
+ * depending on the application requirements and constraints:\r
+ * \r
+ * \r
+ * 1) Basic state monitoring:\r
+ * Using I2C_CheckEvent() function:\r
+ * It compares the status registers (SR1 and SR2) content to a given event\r
+ * (can be the combination of one or more flags).\r
+ * It returns SUCCESS if the current status includes the given flags \r
+ * and returns ERROR if one or more flags are missing in the current status.\r
+ * - When to use:\r
+ * - This function is suitable for most applciations as well as for startup \r
+ * activity since the events are fully described in the product reference manual \r
+ * (RM0008).\r
+ * - It is also suitable for users who need to define their own events.\r
+ * - Limitations:\r
+ * - If an error occurs (ie. error flags are set besides to the monitored flags),\r
+ * the I2C_CheckEvent() function may return SUCCESS despite the communication\r
+ * hold or corrupted real state. \r
+ * In this case, it is advised to use error interrupts to monitor the error\r
+ * events and handle them in the interrupt IRQ handler.\r
+ * \r
+ * @note \r
+ * For error management, it is advised to use the following functions:\r
+ * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).\r
+ * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs.\r
+ * Where x is the peripheral instance (I2C1, I2C2 ...)\r
+ * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() \r
+ * in order to determine which error occured.\r
+ * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()\r
+ * and/or I2C_GenerateStop() in order to clear the error flag and source,\r
+ * and return to correct communication status.\r
+ * \r
+ *\r
+ * 2) Advanced state monitoring:\r
+ * Using the function I2C_GetLastEvent() which returns the image of both status \r
+ * registers in a single word (uint32_t) (Status Register 2 value is shifted left \r
+ * by 16 bits and concatenated to Status Register 1).\r
+ * - When to use:\r
+ * - This function is suitable for the same applications above but it allows to\r
+ * overcome the mentionned limitation of I2C_GetFlagStatus() function.\r
+ * The returned value could be compared to events already defined in the \r
+ * library (stm32f10x_i2c.h) or to custom values defiend by user.\r
+ * - This function is suitable when multiple flags are monitored at the same time.\r
+ * - At the opposite of I2C_CheckEvent() function, this function allows user to\r
+ * choose when an event is accepted (when all events flags are set and no \r
+ * other flags are set or just when the needed flags are set like \r
+ * I2C_CheckEvent() function).\r
+ * - Limitations:\r
+ * - User may need to define his own events.\r
+ * - Same remark concerning the error management is applicable for this \r
+ * function if user decides to check only regular communication flags (and \r
+ * ignores error flags).\r
+ * \r
+ *\r
+ * 3) Flag-based state monitoring:\r
+ * Using the function I2C_GetFlagStatus() which simply returns the status of \r
+ * one single flag (ie. I2C_FLAG_RXNE ...). \r
+ * - When to use:\r
+ * - This function could be used for specific applications or in debug phase.\r
+ * - It is suitable when only one flag checking is needed (most I2C events \r
+ * are monitored through multiple flags).\r
+ * - Limitations: \r
+ * - When calling this function, the Status register is accessed. Some flags are\r
+ * cleared when the status register is accessed. So checking the status\r
+ * of one Flag, may clear other ones.\r
+ * - Function may need to be called twice or more in order to monitor one \r
+ * single event.\r
+ *\r
+ * For detailed description of Events, please refer to section I2C_Events in \r
+ * stm32f10x_i2c.h file.\r
+ * \r
+ */\r
+\r
+/**\r
+ * \r
+ * 1) Basic state monitoring\r
+ *******************************************************************************\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the last I2Cx Event is equal to the one passed\r
+ * as parameter.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_EVENT: specifies the event to be checked. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1\r
+ * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2\r
+ * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3\r
+ * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3\r
+ * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2\r
+ * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4\r
+ * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5\r
+ * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 \r
+ * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6\r
+ * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8\r
+ * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2\r
+ * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32f10x_i2c.h file.\r
+ * \r
+ * @retval An ErrorStatus enumuration value:\r
+ * - SUCCESS: Last event is equal to the I2C_EVENT\r
+ * - ERROR: Last event is different from the I2C_EVENT\r
+ */\r
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+ ErrorStatus status = ERROR;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_EVENT(I2C_EVENT));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_Mask;\r
+\r
+ /* Check whether the last event contains the I2C_EVENT */\r
+ if ((lastevent & I2C_EVENT) == I2C_EVENT)\r
+ {\r
+ /* SUCCESS: last event is equal to I2C_EVENT */\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: last event is different from I2C_EVENT */\r
+ status = ERROR;\r
+ }\r
+ /* Return status */\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \r
+ * 2) Advanced state monitoring\r
+ *******************************************************************************\r
+ */\r
+\r
+/**\r
+ * @brief Returns the last I2Cx Event.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * \r
+ * @note: For detailed description of Events, please refer to section \r
+ * I2C_Events in stm32f10x_i2c.h file.\r
+ * \r
+ * @retval The last event\r
+ */\r
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)\r
+{\r
+ uint32_t lastevent = 0;\r
+ uint32_t flag1 = 0, flag2 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+\r
+ /* Read the I2Cx status register */\r
+ flag1 = I2Cx->SR1;\r
+ flag2 = I2Cx->SR2;\r
+ flag2 = flag2 << 16;\r
+\r
+ /* Get the last event value from I2C status register */\r
+ lastevent = (flag1 | flag2) & FLAG_Mask;\r
+\r
+ /* Return status */\r
+ return lastevent;\r
+}\r
+\r
+/**\r
+ * \r
+ * 3) Flag-based state monitoring\r
+ *******************************************************************************\r
+ */\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C flag is set or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)\r
+ * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)\r
+ * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)\r
+ * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)\r
+ * @arg I2C_FLAG_TRA: Transmitter/Receiver flag\r
+ * @arg I2C_FLAG_BUSY: Bus busy flag\r
+ * @arg I2C_FLAG_MSL: Master/Slave flag\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_FLAG_BTF: Byte transfer finished flag\r
+ * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_FLAG_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_FLAG (SET or RESET).\r
+ */\r
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ __IO uint32_t i2creg = 0, i2cxbase = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));\r
+\r
+ /* Get the I2Cx peripheral base address */\r
+ i2cxbase = (uint32_t)I2Cx;\r
+ \r
+ /* Read flag register index */\r
+ i2creg = I2C_FLAG >> 28;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_FLAG &= FLAG_Mask;\r
+ \r
+ if(i2creg != 0)\r
+ {\r
+ /* Get the I2Cx SR1 register address */\r
+ i2cxbase += 0x14;\r
+ }\r
+ else\r
+ {\r
+ /* Flag in I2Cx SR2 Register */\r
+ I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);\r
+ /* Get the I2Cx SR2 register address */\r
+ i2cxbase += 0x18;\r
+ }\r
+ \r
+ if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)\r
+ {\r
+ /* I2C_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ /* Return the I2C_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+\r
+\r
+/**\r
+ * @brief Clears the I2Cx's pending flags.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_FLAG: specifies the flag to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_FLAG_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_FLAG_PECERR: PEC error in reception flag\r
+ * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_FLAG_AF: Acknowledge failure flag\r
+ * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_FLAG_BERR: Bus error flag\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation \r
+ * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the \r
+ * second byte of the address in DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1\r
+ * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR\r
+ * register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_FLAG & FLAG_Mask;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified I2C interrupt has occurred or not.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert flag\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag\r
+ * @arg I2C_IT_PECERR: PEC error in reception flag\r
+ * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure flag\r
+ * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error flag\r
+ * @arg I2C_IT_TXE: Data register empty flag (Transmitter)\r
+ * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag\r
+ * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)\r
+ * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)\r
+ * @arg I2C_IT_BTF: Byte transfer finished flag\r
+ * @arg I2C_IT_ADDR: Address sent flag (Master mode) \93ADSL\94\r
+ * Address matched flag (Slave mode)\94ENDAD\94\r
+ * @arg I2C_IT_SB: Start bit flag (Master mode)\r
+ * @retval The new state of I2C_IT (SET or RESET).\r
+ */\r
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint32_t enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_GET_IT(I2C_IT));\r
+\r
+ /* Check if the interrupt source is enabled or not */\r
+ enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ;\r
+ \r
+ /* Get bit[23:0] of the flag */\r
+ I2C_IT &= FLAG_Mask;\r
+\r
+ /* Check the status of the specified I2C flag */\r
+ if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)\r
+ {\r
+ /* I2C_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* I2C_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the I2C_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the I2Cx\92s interrupt pending bits.\r
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.\r
+ * @param I2C_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg I2C_IT_SMBALERT: SMBus Alert interrupt\r
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt\r
+ * @arg I2C_IT_PECERR: PEC error in reception interrupt\r
+ * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)\r
+ * @arg I2C_IT_AF: Acknowledge failure interrupt\r
+ * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)\r
+ * @arg I2C_IT_BERR: Bus error interrupt\r
+ * \r
+ * @note\r
+ * - STOPF (STOP detection) is cleared by software sequence: a read operation \r
+ * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).\r
+ * - ADD10 (10-bit header sent) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second \r
+ * byte of the address in I2C_DR register.\r
+ * - BTF (Byte Transfer Finished) is cleared by software sequence: a read \r
+ * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a \r
+ * read/write to I2C_DR register (I2C_SendData()).\r
+ * - ADDR (Address sent) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to \r
+ * I2C_SR2 register ((void)(I2Cx->SR2)).\r
+ * - SB (Start Bit) is cleared by software sequence: a read operation to \r
+ * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to \r
+ * I2C_DR register (I2C_SendData()).\r
+ * @retval None\r
+ */\r
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)\r
+{\r
+ uint32_t flagpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));\r
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));\r
+ /* Get the I2C flag position */\r
+ flagpos = I2C_IT & FLAG_Mask;\r
+ /* Clear the selected I2C flag */\r
+ I2Cx->SR1 = (uint16_t)~flagpos;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_iwdg.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the IWDG firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_iwdg.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup IWDG \r
+ * @brief IWDG driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup IWDG_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_Defines\r
+ * @{\r
+ */ \r
+\r
+/* ---------------------- IWDG registers bit mask ----------------------------*/\r
+\r
+/* KR register bit mask */\r
+#define KR_KEY_Reload ((uint16_t)0xAAAA)\r
+#define KR_KEY_Enable ((uint16_t)0xCCCC)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup IWDG_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup IWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.\r
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers\r
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers\r
+ * @retval None\r
+ */\r
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));\r
+ IWDG->KR = IWDG_WriteAccess;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Prescaler value.\r
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4\r
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8\r
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16\r
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32\r
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64\r
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128\r
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256\r
+ * @retval None\r
+ */\r
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));\r
+ IWDG->PR = IWDG_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Sets IWDG Reload value.\r
+ * @param Reload: specifies the IWDG Reload value.\r
+ * This parameter must be a number between 0 and 0x0FFF.\r
+ * @retval None\r
+ */\r
+void IWDG_SetReload(uint16_t Reload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_RELOAD(Reload));\r
+ IWDG->RLR = Reload;\r
+}\r
+\r
+/**\r
+ * @brief Reloads IWDG counter with value defined in the reload register\r
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_ReloadCounter(void)\r
+{\r
+ IWDG->KR = KR_KEY_Reload;\r
+}\r
+\r
+/**\r
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void IWDG_Enable(void)\r
+{\r
+ IWDG->KR = KR_KEY_Enable;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified IWDG flag is set or not.\r
+ * @param IWDG_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going\r
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going\r
+ * @retval The new state of IWDG_FLAG (SET or RESET).\r
+ */\r
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));\r
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_pwr.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the PWR firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_pwr.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup PWR \r
+ * @brief PWR driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup PWR_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* --------- PWR registers bit address in the alias region ---------- */\r
+#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of DBP bit */\r
+#define CR_OFFSET (PWR_OFFSET + 0x00)\r
+#define DBP_BitNumber 0x08\r
+#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))\r
+\r
+/* Alias word address of PVDE bit */\r
+#define PVDE_BitNumber 0x04\r
+#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of EWUP bit */\r
+#define CSR_OFFSET (PWR_OFFSET + 0x04)\r
+#define EWUP_BitNumber 0x08\r
+#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))\r
+\r
+/* ------------------ PWR registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)\r
+#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PWR_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the PWR peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables access to the RTC and backup registers.\r
+ * @param NewState: new state of the access to the RTC and backup registers.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_BackupAccessCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Power Voltage Detector(PVD).\r
+ * @param NewState: new state of the PVD.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_PVDCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\r
+ * @param PWR_PVDLevel: specifies the PVD detection level\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V\r
+ * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V\r
+ * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V\r
+ * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V\r
+ * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V\r
+ * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V\r
+ * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V\r
+ * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V\r
+ * @retval None\r
+ */\r
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));\r
+ tmpreg = PWR->CR;\r
+ /* Clear PLS[7:5] bits */\r
+ tmpreg &= CR_PLS_MASK;\r
+ /* Set PLS[7:5] bits according to PWR_PVDLevel value */\r
+ tmpreg |= PWR_PVDLevel;\r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the WakeUp Pin functionality.\r
+ * @param NewState: new state of the WakeUp Pin functionality.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void PWR_WakeUpPinCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enters STOP mode.\r
+ * @param PWR_Regulator: specifies the regulator state in STOP mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_Regulator_ON: STOP mode with regulator ON\r
+ * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode\r
+ * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction\r
+ * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_REGULATOR(PWR_Regulator));\r
+ assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));\r
+ \r
+ /* Select the regulator state in STOP mode ---------------------------------*/\r
+ tmpreg = PWR->CR;\r
+ /* Clear PDDS and LPDS bits */\r
+ tmpreg &= CR_DS_MASK;\r
+ /* Set LPDS bit according to PWR_Regulator value */\r
+ tmpreg |= PWR_Regulator;\r
+ /* Store the new value */\r
+ PWR->CR = tmpreg;\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+ \r
+ /* Select STOP mode entry --------------------------------------------------*/\r
+ if(PWR_STOPEntry == PWR_STOPEntry_WFI)\r
+ { \r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+ }\r
+ else\r
+ {\r
+ /* Request Wait For Event */\r
+ __WFE();\r
+ }\r
+ \r
+ /* Reset SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); \r
+}\r
+\r
+/**\r
+ * @brief Enters STANDBY mode.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void PWR_EnterSTANDBYMode(void)\r
+{\r
+ /* Clear Wake-up flag */\r
+ PWR->CR |= PWR_CR_CWUF;\r
+ /* Select STANDBY mode */\r
+ PWR->CR |= PWR_CR_PDDS;\r
+ /* Set SLEEPDEEP bit of Cortex System Control Register */\r
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;\r
+/* This option is used to ensure that store operations are completed */\r
+#if defined ( __CC_ARM )\r
+ __force_stores();\r
+#endif\r
+ /* Request Wait For Interrupt */\r
+ __WFI();\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified PWR flag is set or not.\r
+ * @param PWR_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @arg PWR_FLAG_PVDO: PVD Output\r
+ * @retval The new state of PWR_FLAG (SET or RESET).\r
+ */\r
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_GET_FLAG(PWR_FLAG));\r
+ \r
+ if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the PWR's pending flags.\r
+ * @param PWR_FLAG: specifies the flag to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg PWR_FLAG_WU: Wake Up flag\r
+ * @arg PWR_FLAG_SB: StandBy flag\r
+ * @retval None\r
+ */\r
+void PWR_ClearFlag(uint32_t PWR_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));\r
+ \r
+ PWR->CR |= PWR_FLAG << 2;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rcc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the RCC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RCC \r
+ * @brief RCC driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup RCC_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ------------ RCC registers bit address in the alias region ----------- */\r
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)\r
+\r
+/* --- CR Register ---*/\r
+\r
+/* Alias word address of HSION bit */\r
+#define CR_OFFSET (RCC_OFFSET + 0x00)\r
+#define HSION_BitNumber 0x00\r
+#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))\r
+\r
+/* Alias word address of PLLON bit */\r
+#define PLLON_BitNumber 0x18\r
+#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Alias word address of PLL2ON bit */\r
+ #define PLL2ON_BitNumber 0x1A\r
+ #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))\r
+\r
+ /* Alias word address of PLL3ON bit */\r
+ #define PLL3ON_BitNumber 0x1C\r
+ #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* Alias word address of CSSON bit */\r
+#define CSSON_BitNumber 0x13\r
+#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))\r
+\r
+/* --- CFGR Register ---*/\r
+\r
+/* Alias word address of USBPRE bit */\r
+#define CFGR_OFFSET (RCC_OFFSET + 0x04)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define USBPRE_BitNumber 0x16\r
+ #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))\r
+#else\r
+ #define OTGFSPRE_BitNumber 0x16\r
+ #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* --- BDCR Register ---*/\r
+\r
+/* Alias word address of RTCEN bit */\r
+#define BDCR_OFFSET (RCC_OFFSET + 0x20)\r
+#define RTCEN_BitNumber 0x0F\r
+#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))\r
+\r
+/* Alias word address of BDRST bit */\r
+#define BDRST_BitNumber 0x10\r
+#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))\r
+\r
+/* --- CSR Register ---*/\r
+\r
+/* Alias word address of LSION bit */\r
+#define CSR_OFFSET (RCC_OFFSET + 0x24)\r
+#define LSION_BitNumber 0x00\r
+#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))\r
+\r
+#ifdef STM32F10X_CL\r
+/* --- CFGR2 Register ---*/\r
+\r
+ /* Alias word address of I2S2SRC bit */\r
+ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)\r
+ #define I2S2SRC_BitNumber 0x11\r
+ #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))\r
+\r
+ /* Alias word address of I2S3SRC bit */\r
+ #define I2S3SRC_BitNumber 0x12\r
+ #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))\r
+#endif /* STM32F10X_CL */\r
+\r
+/* ---------------------- RCC registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)\r
+#define CR_HSEBYP_Set ((uint32_t)0x00040000)\r
+#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)\r
+#define CR_HSEON_Set ((uint32_t)0x00010000)\r
+#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)\r
+\r
+/* CFGR register bit mask */\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) \r
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)\r
+#else\r
+ #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)\r
+#endif /* STM32F10X_CL */ \r
+\r
+#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)\r
+#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)\r
+#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)\r
+#define CFGR_SWS_Mask ((uint32_t)0x0000000C)\r
+#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)\r
+#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)\r
+#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)\r
+#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)\r
+#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)\r
+#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)\r
+#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)\r
+#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)\r
+#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)\r
+\r
+/* CSR register bit mask */\r
+#define CSR_RMVF_Set ((uint32_t)0x01000000)\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) \r
+/* CFGR2 register bit mask */\r
+ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)\r
+ #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)\r
+#endif\r
+#ifdef STM32F10X_CL\r
+ #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)\r
+ #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)\r
+ #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)\r
+#endif /* STM32F10X_CL */ \r
+\r
+/* RCC Flag Mask */\r
+#define FLAG_Mask ((uint8_t)0x1F)\r
+\r
+/* CIR register byte 2 (Bits[15:8]) base address */\r
+#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)\r
+\r
+/* CIR register byte 3 (Bits[23:16]) base address */\r
+#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)\r
+\r
+/* CFGR register byte 4 (Bits[31:24]) base address */\r
+#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)\r
+\r
+/* BDCR register base address */\r
+#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Private_Macros\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup RCC_Private_Variables\r
+ * @{\r
+ */ \r
+\r
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};\r
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RCC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Resets the RCC clock configuration to the default reset state.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_DeInit(void)\r
+{\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */ \r
+ \r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000; \r
+#else\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#endif /* STM32F10X_CL */\r
+\r
+}\r
+\r
+/**\r
+ * @brief Configures the External High Speed oscillator (HSE).\r
+ * @note HSE can not be stopped if it is used directly or through the PLL as system clock.\r
+ * @param RCC_HSE: specifies the new state of the HSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HSE_OFF: HSE oscillator OFF\r
+ * @arg RCC_HSE_ON: HSE oscillator ON\r
+ * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_HSEConfig(uint32_t RCC_HSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HSE(RCC_HSE));\r
+ /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/\r
+ /* Reset HSEON bit */\r
+ RCC->CR &= CR_HSEON_Reset;\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= CR_HSEBYP_Reset;\r
+ /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */\r
+ switch(RCC_HSE)\r
+ {\r
+ case RCC_HSE_ON:\r
+ /* Set HSEON bit */\r
+ RCC->CR |= CR_HSEON_Set;\r
+ break;\r
+ \r
+ case RCC_HSE_Bypass:\r
+ /* Set HSEBYP and HSEON bits */\r
+ RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;\r
+ break;\r
+ \r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Waits for HSE start-up.\r
+ * @param None\r
+ * @retval An ErrorStatus enumuration value:\r
+ * - SUCCESS: HSE oscillator is stable and ready to use\r
+ * - ERROR: HSE oscillator not yet ready\r
+ */\r
+ErrorStatus RCC_WaitForHSEStartUp(void)\r
+{\r
+ __IO uint32_t StartUpCounter = 0;\r
+ ErrorStatus status = ERROR;\r
+ FlagStatus HSEStatus = RESET;\r
+ \r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);\r
+ StartUpCounter++; \r
+ } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));\r
+ \r
+ if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)\r
+ {\r
+ status = SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = ERROR;\r
+ } \r
+ return (status);\r
+}\r
+\r
+/**\r
+ * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.\r
+ * @param HSICalibrationValue: specifies the calibration trimming value.\r
+ * This parameter must be a number between 0 and 0x1F.\r
+ * @retval None\r
+ */\r
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));\r
+ tmpreg = RCC->CR;\r
+ /* Clear HSITRIM[4:0] bits */\r
+ tmpreg &= CR_HSITRIM_Mask;\r
+ /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */\r
+ tmpreg |= (uint32_t)HSICalibrationValue << 3;\r
+ /* Store the new value */\r
+ RCC->CR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal High Speed oscillator (HSI).\r
+ * @note HSI can not be stopped if it is used directly or through the PLL as system clock.\r
+ * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_HSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL clock source and multiplication factor.\r
+ * @note This function must be used only when the PLL is disabled.\r
+ * @param RCC_PLLSource: specifies the PLL entry clock source.\r
+ * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, \r
+ * this parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
+ * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry\r
+ * For @b other_STM32_devices, this parameter can be one of the following values:\r
+ * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry\r
+ * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry\r
+ * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry \r
+ * @param RCC_PLLMul: specifies the PLL multiplication factor.\r
+ * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}\r
+ * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] \r
+ * @retval None\r
+ */\r
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));\r
+ assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));\r
+\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */\r
+ tmpreg &= CFGR_PLL_Mask;\r
+ /* Set the PLL configuration bits */\r
+ tmpreg |= RCC_PLLSource | RCC_PLLMul;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PLL.\r
+ * @note The PLL can not be disabled if it is used as system clock.\r
+ * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLLCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;\r
+}\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)\r
+/**\r
+ * @brief Configures the PREDIV1 division factor.\r
+ * @note \r
+ * - This function must be used only when the PLL is disabled.\r
+ * - This function applies only to STM32 Connectivity line and Value line \r
+ * devices.\r
+ * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock\r
+ * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock\r
+ * @note \r
+ * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE \r
+ * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.\r
+ * This parameter can be RCC_PREDIV1_Divx where x:[1,16]\r
+ * @retval None\r
+ */\r
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));\r
+ assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PREDIV1[3:0] and PREDIV1SRC bits */\r
+ tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);\r
+ /* Set the PREDIV1 clock source and division factor */\r
+ tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+#endif\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Configures the PREDIV2 division factor.\r
+ * @note \r
+ * - This function must be used only when both PLL2 and PLL3 are disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.\r
+ * This parameter can be RCC_PREDIV2_Divx where x:[1,16]\r
+ * @retval None\r
+ */\r
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PREDIV2[3:0] bits */\r
+ tmpreg &= ~CFGR2_PREDIV2;\r
+ /* Set the PREDIV2 division factor */\r
+ tmpreg |= RCC_PREDIV2_Div;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the PLL2 multiplication factor.\r
+ * @note\r
+ * - This function must be used only when the PLL2 is disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.\r
+ * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}\r
+ * @retval None\r
+ */\r
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PLL2Mul[3:0] bits */\r
+ tmpreg &= ~CFGR2_PLL2MUL;\r
+ /* Set the PLL2 configuration bits */\r
+ tmpreg |= RCC_PLL2Mul;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the PLL2.\r
+ * @note \r
+ * - The PLL2 can not be disabled if it is used indirectly as system clock\r
+ * (i.e. it is used as PLL clock entry that is used as System clock).\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLL2Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Configures the PLL3 multiplication factor.\r
+ * @note \r
+ * - This function must be used only when the PLL3 is disabled.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.\r
+ * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}\r
+ * @retval None\r
+ */\r
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)\r
+{\r
+ uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));\r
+\r
+ tmpreg = RCC->CFGR2;\r
+ /* Clear PLL3Mul[3:0] bits */\r
+ tmpreg &= ~CFGR2_PLL3MUL;\r
+ /* Set the PLL3 configuration bits */\r
+ tmpreg |= RCC_PLL3Mul;\r
+ /* Store the new value */\r
+ RCC->CFGR2 = tmpreg;\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the PLL3.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_PLL3Cmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;\r
+}\r
+#endif /* STM32F10X_CL */\r
+\r
+/**\r
+ * @brief Configures the system clock (SYSCLK).\r
+ * @param RCC_SYSCLKSource: specifies the clock source used as system clock.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock\r
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock\r
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock\r
+ * @retval None\r
+ */\r
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear SW[1:0] bits */\r
+ tmpreg &= CFGR_SW_Mask;\r
+ /* Set SW[1:0] bits according to RCC_SYSCLKSource value */\r
+ tmpreg |= RCC_SYSCLKSource;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the clock source used as system clock.\r
+ * @param None\r
+ * @retval The clock source used as system clock. The returned value can\r
+ * be one of the following:\r
+ * - 0x00: HSI used as system clock\r
+ * - 0x04: HSE used as system clock\r
+ * - 0x08: PLL used as system clock\r
+ */\r
+uint8_t RCC_GetSYSCLKSource(void)\r
+{\r
+ return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));\r
+}\r
+\r
+/**\r
+ * @brief Configures the AHB clock (HCLK).\r
+ * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from \r
+ * the system clock (SYSCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK\r
+ * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2\r
+ * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4\r
+ * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8\r
+ * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16\r
+ * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64\r
+ * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128\r
+ * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256\r
+ * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512\r
+ * @retval None\r
+ */\r
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_HCLK(RCC_SYSCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear HPRE[3:0] bits */\r
+ tmpreg &= CFGR_HPRE_Reset_Mask;\r
+ /* Set HPRE[3:0] bits according to RCC_SYSCLK value */\r
+ tmpreg |= RCC_SYSCLK;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the Low Speed APB clock (PCLK1).\r
+ * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB1 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK1Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PPRE1[2:0] bits */\r
+ tmpreg &= CFGR_PPRE1_Reset_Mask;\r
+ /* Set PPRE1[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Configures the High Speed APB clock (PCLK2).\r
+ * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from \r
+ * the AHB clock (HCLK).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_HCLK_Div1: APB2 clock = HCLK\r
+ * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2\r
+ * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4\r
+ * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8\r
+ * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16\r
+ * @retval None\r
+ */\r
+void RCC_PCLK2Config(uint32_t RCC_HCLK)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_PCLK(RCC_HCLK));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear PPRE2[2:0] bits */\r
+ tmpreg &= CFGR_PPRE2_Reset_Mask;\r
+ /* Set PPRE2[2:0] bits according to RCC_HCLK value */\r
+ tmpreg |= RCC_HCLK << 3;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified RCC interrupts.\r
+ * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt\r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the \r
+ * following values \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * \r
+ * @param NewState: new state of the specified RCC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_IT(RCC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */\r
+ *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;\r
+ }\r
+}\r
+\r
+#ifndef STM32F10X_CL\r
+/**\r
+ * @brief Configures the USB clock (USBCLK).\r
+ * @param RCC_USBCLKSource: specifies the USB clock source. This clock is \r
+ * derived from the PLL output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB \r
+ * clock source\r
+ * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source\r
+ * @retval None\r
+ */\r
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;\r
+}\r
+#else\r
+/**\r
+ * @brief Configures the USB OTG FS clock (OTGFSCLK).\r
+ * This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.\r
+ * This clock is derived from the PLL output.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
+ * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source\r
+ * @retval None\r
+ */\r
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;\r
+}\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @brief Configures the ADC clock (ADCCLK).\r
+ * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from \r
+ * the APB2 clock (PCLK2).\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2\r
+ * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4\r
+ * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6\r
+ * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8\r
+ * @retval None\r
+ */\r
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_ADCCLK(RCC_PCLK2));\r
+ tmpreg = RCC->CFGR;\r
+ /* Clear ADCPRE[1:0] bits */\r
+ tmpreg &= CFGR_ADCPRE_Reset_Mask;\r
+ /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */\r
+ tmpreg |= RCC_PCLK2;\r
+ /* Store the new value */\r
+ RCC->CFGR = tmpreg;\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Configures the I2S2 clock source(I2S2CLK).\r
+ * @note\r
+ * - This function must be called before enabling I2S2 APB clock.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry\r
+ * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry\r
+ * @retval None\r
+ */\r
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Configures the I2S3 clock source(I2S2CLK).\r
+ * @note\r
+ * - This function must be called before enabling I2S3 APB clock.\r
+ * - This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry\r
+ * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry\r
+ * @retval None\r
+ */\r
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));\r
+\r
+ *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;\r
+}\r
+#endif /* STM32F10X_CL */\r
+\r
+/**\r
+ * @brief Configures the External Low Speed oscillator (LSE).\r
+ * @param RCC_LSE: specifies the new state of the LSE.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_LSE_OFF: LSE oscillator OFF\r
+ * @arg RCC_LSE_ON: LSE oscillator ON\r
+ * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock\r
+ * @retval None\r
+ */\r
+void RCC_LSEConfig(uint8_t RCC_LSE)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_LSE(RCC_LSE));\r
+ /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/\r
+ /* Reset LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+ /* Reset LSEBYP bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;\r
+ /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */\r
+ switch(RCC_LSE)\r
+ {\r
+ case RCC_LSE_ON:\r
+ /* Set LSEON bit */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;\r
+ break;\r
+ \r
+ case RCC_LSE_Bypass:\r
+ /* Set LSEBYP and LSEON bits */\r
+ *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;\r
+ break; \r
+ \r
+ default:\r
+ break; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Internal Low Speed oscillator (LSI).\r
+ * @note LSI can not be disabled if the IWDG is running.\r
+ * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_LSICmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Configures the RTC clock (RTCCLK).\r
+ * @note Once the RTC clock is selected it can\92t be changed unless the Backup domain is reset.\r
+ * @param RCC_RTCCLKSource: specifies the RTC clock source.\r
+ * This parameter can be one of the following values:\r
+ * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock\r
+ * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));\r
+ /* Select the RTC clock source */\r
+ RCC->BDCR |= RCC_RTCCLKSource;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the RTC clock.\r
+ * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.\r
+ * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_RTCCLKCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Returns the frequencies of different on chip clocks.\r
+ * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold\r
+ * the clocks frequencies.\r
+ * @note The result of this function could be not correct when using \r
+ * fractional value for HSE crystal. \r
+ * @retval None\r
+ */\r
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)\r
+{\r
+ uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;\r
+\r
+#ifdef STM32F10X_CL\r
+ uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;\r
+#endif /* STM32F10X_CL */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ uint32_t prediv1factor = 0;\r
+#endif\r
+ \r
+ /* Get SYSCLK source -------------------------------------------------------*/\r
+ tmp = RCC->CFGR & CFGR_SWS_Mask;\r
+ \r
+ switch (tmp)\r
+ {\r
+ case 0x00: /* HSI used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ case 0x04: /* HSE used as system clock */\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;\r
+ break;\r
+ case 0x08: /* PLL used as system clock */\r
+\r
+ /* Get PLL clock source and multiplication factor ----------------------*/\r
+ pllmull = RCC->CFGR & CFGR_PLLMull_Mask;\r
+ pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;\r
+ \r
+#ifndef STM32F10X_CL \r
+ pllmull = ( pllmull >> 18) + 2;\r
+ \r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
+ /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; \r
+ #else\r
+ /* HSE selected as PLL clock entry */\r
+ if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)\r
+ {/* HSE oscillator clock divided by 2 */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {\r
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;\r
+ }\r
+ #endif\r
+ }\r
+#else\r
+ pllmull = pllmull >> 18;\r
+ \r
+ if (pllmull != 0x0D)\r
+ {\r
+ pllmull += 2;\r
+ }\r
+ else\r
+ { /* PLL multiplication factor = PLL input clock * 6.5 */\r
+ pllmull = 13 / 2; \r
+ }\r
+ \r
+ if (pllsource == 0x00)\r
+ {/* HSI oscillator clock divided by 2 selected as PLL clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;\r
+ }\r
+ else\r
+ {/* PREDIV1 selected as PLL clock entry */\r
+ \r
+ /* Get PREDIV1 clock source and division factor */\r
+ prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;\r
+ prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;\r
+ \r
+ if (prediv1source == 0)\r
+ { /* HSE oscillator clock selected as PREDIV1 clock entry */\r
+ RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; \r
+ }\r
+ else\r
+ {/* PLL2 clock selected as PREDIV1 clock entry */\r
+ \r
+ /* Get PREDIV2 division factor and PLL2 multiplication factor */\r
+ prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;\r
+ pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; \r
+ RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; \r
+ }\r
+ }\r
+#endif /* STM32F10X_CL */ \r
+ break;\r
+\r
+ default:\r
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;\r
+ break;\r
+ }\r
+\r
+ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/\r
+ /* Get HCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;\r
+ tmp = tmp >> 4;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* HCLK clock frequency */\r
+ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;\r
+ /* Get PCLK1 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;\r
+ tmp = tmp >> 8;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK1 clock frequency */\r
+ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+ /* Get PCLK2 prescaler */\r
+ tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;\r
+ tmp = tmp >> 11;\r
+ presc = APBAHBPrescTable[tmp];\r
+ /* PCLK2 clock frequency */\r
+ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;\r
+ /* Get ADCCLK prescaler */\r
+ tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;\r
+ tmp = tmp >> 14;\r
+ presc = ADCPrescTable[tmp];\r
+ /* ADCCLK clock frequency */\r
+ RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the AHB peripheral clock.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values: \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @arg RCC_AHBPeriph_DMA2\r
+ * @arg RCC_AHBPeriph_SRAM\r
+ * @arg RCC_AHBPeriph_FLITF\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_OTG_FS \r
+ * @arg RCC_AHBPeriph_ETH_MAC \r
+ * @arg RCC_AHBPeriph_ETH_MAC_Tx\r
+ * @arg RCC_AHBPeriph_ETH_MAC_Rx\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the \r
+ * following values: \r
+ * @arg RCC_AHBPeriph_DMA1\r
+ * @arg RCC_AHBPeriph_DMA2\r
+ * @arg RCC_AHBPeriph_SRAM\r
+ * @arg RCC_AHBPeriph_FLITF\r
+ * @arg RCC_AHBPeriph_CRC\r
+ * @arg RCC_AHBPeriph_FSMC\r
+ * @arg RCC_AHBPeriph_SDIO\r
+ * \r
+ * @note SRAM and FLITF clock can be disabled only during sleep mode.\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBENR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBENR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the High Speed APB (APB2) peripheral clock.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2ENR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2ENR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14\r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1ENR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1ENR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+#ifdef STM32F10X_CL\r
+/**\r
+ * @brief Forces or releases AHB peripheral reset.\r
+ * @note This function applies only to STM32 Connectivity line devices.\r
+ * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_AHBPeriph_OTG_FS \r
+ * @arg RCC_AHBPeriph_ETH_MAC\r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->AHBRSTR |= RCC_AHBPeriph;\r
+ }\r
+ else\r
+ {\r
+ RCC->AHBRSTR &= ~RCC_AHBPeriph;\r
+ }\r
+}\r
+#endif /* STM32F10X_CL */ \r
+\r
+/**\r
+ * @brief Forces or releases High Speed APB (APB2) peripheral reset.\r
+ * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,\r
+ * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,\r
+ * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,\r
+ * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,\r
+ * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,\r
+ * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,\r
+ * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 \r
+ * @param NewState: new state of the specified peripheral reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB2RSTR |= RCC_APB2Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB2RSTR &= ~RCC_APB2Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases Low Speed APB (APB1) peripheral reset.\r
+ * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,\r
+ * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,\r
+ * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,\r
+ * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, \r
+ * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,\r
+ * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,\r
+ * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,\r
+ * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 \r
+ * @param NewState: new state of the specified peripheral clock.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ RCC->APB1RSTR |= RCC_APB1Periph;\r
+ }\r
+ else\r
+ {\r
+ RCC->APB1RSTR &= ~RCC_APB1Periph;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Forces or releases the Backup domain reset.\r
+ * @param NewState: new state of the Backup domain reset.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_BackupResetCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Clock Security System.\r
+ * @param NewState: new state of the Clock Security System..\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Selects the clock source to output on MCO pin.\r
+ * @param RCC_MCO: specifies the clock source to output.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values: \r
+ * @arg RCC_MCO_NoClock: No clock selected\r
+ * @arg RCC_MCO_SYSCLK: System clock selected\r
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+ * @arg RCC_MCO_PLL2CLK: PLL2 clock selected \r
+ * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected \r
+ * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected \r
+ * @arg RCC_MCO_PLL3CLK: PLL3 clock selected \r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_MCO_NoClock: No clock selected\r
+ * @arg RCC_MCO_SYSCLK: System clock selected\r
+ * @arg RCC_MCO_HSI: HSI oscillator clock selected\r
+ * @arg RCC_MCO_HSE: HSE oscillator clock selected\r
+ * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected\r
+ * \r
+ * @retval None\r
+ */\r
+void RCC_MCOConfig(uint8_t RCC_MCO)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_MCO(RCC_MCO));\r
+\r
+ /* Perform Byte access to MCO bits to select the MCO source */\r
+ *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC flag is set or not.\r
+ * @param RCC_FLAG: specifies the flag to check.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values:\r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready \r
+ * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready \r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready\r
+ * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready\r
+ * @arg RCC_FLAG_PLLRDY: PLL clock ready\r
+ * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready\r
+ * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready\r
+ * @arg RCC_FLAG_PINRST: Pin reset\r
+ * @arg RCC_FLAG_PORRST: POR/PDR reset\r
+ * @arg RCC_FLAG_SFTRST: Software reset\r
+ * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset\r
+ * @arg RCC_FLAG_WWDGRST: Window Watchdog reset\r
+ * @arg RCC_FLAG_LPWRRST: Low Power reset\r
+ * \r
+ * @retval The new state of RCC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint32_t statusreg = 0;\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_FLAG(RCC_FLAG));\r
+\r
+ /* Get the RCC register index */\r
+ tmp = RCC_FLAG >> 5;\r
+ if (tmp == 1) /* The flag to check is in CR register */\r
+ {\r
+ statusreg = RCC->CR;\r
+ }\r
+ else if (tmp == 2) /* The flag to check is in BDCR register */\r
+ {\r
+ statusreg = RCC->BDCR;\r
+ }\r
+ else /* The flag to check is in CSR register */\r
+ {\r
+ statusreg = RCC->CSR;\r
+ }\r
+\r
+ /* Get the flag position */\r
+ tmp = RCC_FLAG & FLAG_Mask;\r
+ if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the flag status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC reset flags.\r
+ * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,\r
+ * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RCC_ClearFlag(void)\r
+{\r
+ /* Set RMVF bit to clear the reset flags */\r
+ RCC->CSR |= CSR_RMVF_Set;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RCC interrupt has occurred or not.\r
+ * @param RCC_IT: specifies the RCC interrupt source to check.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be one of the\r
+ * following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be one of the following values: \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * @retval The new state of RCC_IT (SET or RESET).\r
+ */\r
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_GET_IT(RCC_IT));\r
+\r
+ /* Check the status of the specified RCC interrupt */\r
+ if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+\r
+ /* Return the RCC_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RCC\92s interrupt pending bits.\r
+ * @param RCC_IT: specifies the interrupt pending bit to clear.\r
+ * \r
+ * For @b STM32_Connectivity_line_devices, this parameter can be any combination\r
+ * of the following values:\r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt \r
+ * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * \r
+ * For @b other_STM32_devices, this parameter can be any combination of the\r
+ * following values: \r
+ * @arg RCC_IT_LSIRDY: LSI ready interrupt\r
+ * @arg RCC_IT_LSERDY: LSE ready interrupt\r
+ * @arg RCC_IT_HSIRDY: HSI ready interrupt\r
+ * @arg RCC_IT_HSERDY: HSE ready interrupt\r
+ * @arg RCC_IT_PLLRDY: PLL ready interrupt\r
+ * \r
+ * @arg RCC_IT_CSS: Clock Security System interrupt\r
+ * @retval None\r
+ */\r
+void RCC_ClearITPendingBit(uint8_t RCC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RCC_CLEAR_IT(RCC_IT));\r
+\r
+ /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt\r
+ pending bits */\r
+ *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_rtc.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the RTC firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_rtc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC \r
+ * @brief RTC driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup RTC_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Defines\r
+ * @{\r
+ */\r
+#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */\r
+#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup RTC_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Enables or disables the specified RTC interrupts.\r
+ * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_OW: Overflow interrupt\r
+ * @arg RTC_IT_ALR: Alarm interrupt\r
+ * @arg RTC_IT_SEC: Second interrupt\r
+ * @param NewState: new state of the specified RTC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_IT(RTC_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ RTC->CRH |= RTC_IT;\r
+ }\r
+ else\r
+ {\r
+ RTC->CRH &= (uint16_t)~RTC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enters the RTC configuration mode.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_EnterConfigMode(void)\r
+{\r
+ /* Set the CNF flag to enter in the Configuration Mode */\r
+ RTC->CRL |= RTC_CRL_CNF;\r
+}\r
+\r
+/**\r
+ * @brief Exits from the RTC configuration mode.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_ExitConfigMode(void)\r
+{\r
+ /* Reset the CNF flag to exit from the Configuration Mode */\r
+ RTC->CRL &= (uint16_t)~((uint16_t)RTC_CRL_CNF); \r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC counter value.\r
+ * @param None\r
+ * @retval RTC counter value.\r
+ */\r
+uint32_t RTC_GetCounter(void)\r
+{\r
+ uint16_t tmp = 0;\r
+ tmp = RTC->CNTL;\r
+ return (((uint32_t)RTC->CNTH << 16 ) | tmp) ;\r
+}\r
+\r
+/**\r
+ * @brief Sets the RTC counter value.\r
+ * @param CounterValue: RTC counter new value.\r
+ * @retval None\r
+ */\r
+void RTC_SetCounter(uint32_t CounterValue)\r
+{ \r
+ RTC_EnterConfigMode();\r
+ /* Set RTC COUNTER MSB word */\r
+ RTC->CNTH = CounterValue >> 16;\r
+ /* Set RTC COUNTER LSB word */\r
+ RTC->CNTL = (CounterValue & RTC_LSB_MASK);\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/**\r
+ * @brief Sets the RTC prescaler value.\r
+ * @param PrescalerValue: RTC prescaler new value.\r
+ * @retval None\r
+ */\r
+void RTC_SetPrescaler(uint32_t PrescalerValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_PRESCALER(PrescalerValue));\r
+ \r
+ RTC_EnterConfigMode();\r
+ /* Set RTC PRESCALER MSB word */\r
+ RTC->PRLH = (PrescalerValue & PRLH_MSB_MASK) >> 16;\r
+ /* Set RTC PRESCALER LSB word */\r
+ RTC->PRLL = (PrescalerValue & RTC_LSB_MASK);\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/**\r
+ * @brief Sets the RTC alarm value.\r
+ * @param AlarmValue: RTC alarm new value.\r
+ * @retval None\r
+ */\r
+void RTC_SetAlarm(uint32_t AlarmValue)\r
+{ \r
+ RTC_EnterConfigMode();\r
+ /* Set the ALARM MSB word */\r
+ RTC->ALRH = AlarmValue >> 16;\r
+ /* Set the ALARM LSB word */\r
+ RTC->ALRL = (AlarmValue & RTC_LSB_MASK);\r
+ RTC_ExitConfigMode();\r
+}\r
+\r
+/**\r
+ * @brief Gets the RTC divider value.\r
+ * @param None\r
+ * @retval RTC Divider value.\r
+ */\r
+uint32_t RTC_GetDivider(void)\r
+{\r
+ uint32_t tmp = 0x00;\r
+ tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;\r
+ tmp |= RTC->DIVL;\r
+ return tmp;\r
+}\r
+\r
+/**\r
+ * @brief Waits until last write operation on RTC registers has finished.\r
+ * @note This function must be called before any write to RTC registers.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_WaitForLastTask(void)\r
+{\r
+ /* Loop until RTOFF flag is set */\r
+ while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL)\r
+ * are synchronized with RTC APB clock.\r
+ * @note This function must be called before any read operation after an APB reset\r
+ * or an APB clock stop.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void RTC_WaitForSynchro(void)\r
+{\r
+ /* Clear RSF flag */\r
+ RTC->CRL &= (uint16_t)~RTC_FLAG_RSF;\r
+ /* Loop until RSF flag is set */\r
+ while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET)\r
+ {\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC flag is set or not.\r
+ * @param RTC_FLAG: specifies the flag to check.\r
+ * This parameter can be one the following values:\r
+ * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag\r
+ * @arg RTC_FLAG_OW: Overflow flag\r
+ * @arg RTC_FLAG_ALR: Alarm flag\r
+ * @arg RTC_FLAG_SEC: Second flag\r
+ * @retval The new state of RTC_FLAG (SET or RESET).\r
+ */\r
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); \r
+ \r
+ if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC\92s pending flags.\r
+ * @param RTC_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after\r
+ * an APB reset or an APB Clock stop.\r
+ * @arg RTC_FLAG_OW: Overflow flag\r
+ * @arg RTC_FLAG_ALR: Alarm flag\r
+ * @arg RTC_FLAG_SEC: Second flag\r
+ * @retval None\r
+ */\r
+void RTC_ClearFlag(uint16_t RTC_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); \r
+ \r
+ /* Clear the coressponding RTC flag */\r
+ RTC->CRL &= (uint16_t)~RTC_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified RTC interrupt has occured or not.\r
+ * @param RTC_IT: specifies the RTC interrupts sources to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg RTC_IT_OW: Overflow interrupt\r
+ * @arg RTC_IT_ALR: Alarm interrupt\r
+ * @arg RTC_IT_SEC: Second interrupt\r
+ * @retval The new state of the RTC_IT (SET or RESET).\r
+ */\r
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_GET_IT(RTC_IT)); \r
+ \r
+ bitstatus = (ITStatus)(RTC->CRL & RTC_IT);\r
+ if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the RTC\92s interrupt pending bits.\r
+ * @param RTC_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg RTC_IT_OW: Overflow interrupt\r
+ * @arg RTC_IT_ALR: Alarm interrupt\r
+ * @arg RTC_IT_SEC: Second interrupt\r
+ * @retval None\r
+ */\r
+void RTC_ClearITPendingBit(uint16_t RTC_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_RTC_IT(RTC_IT)); \r
+ \r
+ /* Clear the coressponding RTC pending bit */\r
+ RTC->CRL &= (uint16_t)~RTC_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_sdio.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the SDIO firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_sdio.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SDIO \r
+ * @brief SDIO driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SDIO_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+\r
+/* ------------ SDIO registers bit address in the alias region ----------- */\r
+#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)\r
+\r
+/* --- CLKCR Register ---*/\r
+\r
+/* Alias word address of CLKEN bit */\r
+#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)\r
+#define CLKEN_BitNumber 0x08\r
+#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))\r
+\r
+/* --- CMD Register ---*/\r
+\r
+/* Alias word address of SDIOSUSPEND bit */\r
+#define CMD_OFFSET (SDIO_OFFSET + 0x0C)\r
+#define SDIOSUSPEND_BitNumber 0x0B\r
+#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))\r
+\r
+/* Alias word address of ENCMDCOMPL bit */\r
+#define ENCMDCOMPL_BitNumber 0x0C\r
+#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))\r
+\r
+/* Alias word address of NIEN bit */\r
+#define NIEN_BitNumber 0x0D\r
+#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))\r
+\r
+/* Alias word address of ATACMD bit */\r
+#define ATACMD_BitNumber 0x0E\r
+#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))\r
+\r
+/* --- DCTRL Register ---*/\r
+\r
+/* Alias word address of DMAEN bit */\r
+#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)\r
+#define DMAEN_BitNumber 0x03\r
+#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))\r
+\r
+/* Alias word address of RWSTART bit */\r
+#define RWSTART_BitNumber 0x08\r
+#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))\r
+\r
+/* Alias word address of RWSTOP bit */\r
+#define RWSTOP_BitNumber 0x09\r
+#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))\r
+\r
+/* Alias word address of RWMOD bit */\r
+#define RWMOD_BitNumber 0x0A\r
+#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))\r
+\r
+/* Alias word address of SDIOEN bit */\r
+#define SDIOEN_BitNumber 0x0B\r
+#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))\r
+\r
+/* ---------------------- SDIO registers bit mask ------------------------ */\r
+\r
+/* --- CLKCR Register ---*/\r
+\r
+/* CLKCR register clear mask */\r
+#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) \r
+\r
+/* --- PWRCTRL Register ---*/\r
+\r
+/* SDIO PWRCTRL Mask */\r
+#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)\r
+\r
+/* --- DCTRL Register ---*/\r
+\r
+/* SDIO DCTRL Clear Mask */\r
+#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)\r
+\r
+/* --- CMD Register ---*/\r
+\r
+/* CMD Register clear mask */\r
+#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)\r
+\r
+/* SDIO RESP Registers Address */\r
+#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SDIO_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SDIO peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void SDIO_DeInit(void)\r
+{\r
+ SDIO->POWER = 0x00000000;\r
+ SDIO->CLKCR = 0x00000000;\r
+ SDIO->ARG = 0x00000000;\r
+ SDIO->CMD = 0x00000000;\r
+ SDIO->DTIMER = 0x00000000;\r
+ SDIO->DLEN = 0x00000000;\r
+ SDIO->DCTRL = 0x00000000;\r
+ SDIO->ICR = 0x00C007FF;\r
+ SDIO->MASK = 0x00000000;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SDIO peripheral according to the specified \r
+ * parameters in the SDIO_InitStruct.\r
+ * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure \r
+ * that contains the configuration information for the SDIO peripheral.\r
+ * @retval None\r
+ */\r
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));\r
+ assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));\r
+ assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));\r
+ assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));\r
+ assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); \r
+ \r
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/ \r
+ /* Get the SDIO CLKCR value */\r
+ tmpreg = SDIO->CLKCR;\r
+ \r
+ /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */\r
+ tmpreg &= CLKCR_CLEAR_MASK;\r
+ \r
+ /* Set CLKDIV bits according to SDIO_ClockDiv value */\r
+ /* Set PWRSAV bit according to SDIO_ClockPowerSave value */\r
+ /* Set BYPASS bit according to SDIO_ClockBypass value */\r
+ /* Set WIDBUS bits according to SDIO_BusWide value */\r
+ /* Set NEGEDGE bits according to SDIO_ClockEdge value */\r
+ /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */\r
+ tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |\r
+ SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |\r
+ SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); \r
+ \r
+ /* Write to SDIO CLKCR */\r
+ SDIO->CLKCR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_InitStruct member with its default value.\r
+ * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which \r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)\r
+{\r
+ /* SDIO_InitStruct members default value */\r
+ SDIO_InitStruct->SDIO_ClockDiv = 0x00;\r
+ SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;\r
+ SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;\r
+ SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;\r
+ SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;\r
+ SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO Clock.\r
+ * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_ClockCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Sets the power status of the controller.\r
+ * @param SDIO_PowerState: new state of the Power state. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_PowerState_OFF\r
+ * @arg SDIO_PowerState_ON\r
+ * @retval None\r
+ */\r
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));\r
+ \r
+ SDIO->POWER &= PWR_PWRCTRL_MASK;\r
+ SDIO->POWER |= SDIO_PowerState;\r
+}\r
+\r
+/**\r
+ * @brief Gets the power status of the controller.\r
+ * @param None\r
+ * @retval Power status of the controller. The returned value can\r
+ * be one of the following:\r
+ * - 0x00: Power OFF\r
+ * - 0x02: Power UP\r
+ * - 0x03: Power ON \r
+ */\r
+uint32_t SDIO_GetPowerState(void)\r
+{\r
+ return (SDIO->POWER & (~PWR_PWRCTRL_MASK));\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO interrupts.\r
+ * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.\r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
+ * @param NewState: new state of the specified SDIO interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None \r
+ */\r
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_IT(SDIO_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SDIO interrupts */\r
+ SDIO->MASK |= SDIO_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SDIO interrupts */\r
+ SDIO->MASK &= ~SDIO_IT;\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SDIO DMA request.\r
+ * @param NewState: new state of the selected SDIO DMA request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_DMACmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SDIO Command according to the specified \r
+ * parameters in the SDIO_CmdInitStruct and send the command.\r
+ * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef \r
+ * structure that contains the configuration information for the SDIO command.\r
+ * @retval None\r
+ */\r
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));\r
+ assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));\r
+ assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));\r
+ assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));\r
+ \r
+/*---------------------------- SDIO ARG Configuration ------------------------*/\r
+ /* Set the SDIO Argument value */\r
+ SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;\r
+ \r
+/*---------------------------- SDIO CMD Configuration ------------------------*/ \r
+ /* Get the SDIO CMD value */\r
+ tmpreg = SDIO->CMD;\r
+ /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */\r
+ tmpreg &= CMD_CLEAR_MASK;\r
+ /* Set CMDINDEX bits according to SDIO_CmdIndex value */\r
+ /* Set WAITRESP bits according to SDIO_Response value */\r
+ /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */\r
+ /* Set CPSMEN bits according to SDIO_CPSM value */\r
+ tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response\r
+ | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;\r
+ \r
+ /* Write to SDIO CMD */\r
+ SDIO->CMD = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_CmdInitStruct member with its default value.\r
+ * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef \r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)\r
+{\r
+ /* SDIO_CmdInitStruct members default value */\r
+ SDIO_CmdInitStruct->SDIO_Argument = 0x00;\r
+ SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;\r
+ SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;\r
+ SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;\r
+ SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Returns command index of last command for which response received.\r
+ * @param None\r
+ * @retval Returns the command index of the last command response received.\r
+ */\r
+uint8_t SDIO_GetCommandResponse(void)\r
+{\r
+ return (uint8_t)(SDIO->RESPCMD);\r
+}\r
+\r
+/**\r
+ * @brief Returns response received from the card for the last command.\r
+ * @param SDIO_RESP: Specifies the SDIO response register. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_RESP1: Response Register 1\r
+ * @arg SDIO_RESP2: Response Register 2\r
+ * @arg SDIO_RESP3: Response Register 3\r
+ * @arg SDIO_RESP4: Response Register 4\r
+ * @retval The Corresponding response register value.\r
+ */\r
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)\r
+{\r
+ __IO uint32_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_RESP(SDIO_RESP));\r
+\r
+ tmp = SDIO_RESP_ADDR + SDIO_RESP;\r
+ \r
+ return (*(__IO uint32_t *) tmp); \r
+}\r
+\r
+/**\r
+ * @brief Initializes the SDIO data path according to the specified \r
+ * parameters in the SDIO_DataInitStruct.\r
+ * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that\r
+ * contains the configuration information for the SDIO command.\r
+ * @retval None\r
+ */\r
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));\r
+ assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));\r
+ assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));\r
+ assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));\r
+ assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));\r
+\r
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/\r
+ /* Set the SDIO Data TimeOut value */\r
+ SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;\r
+\r
+/*---------------------------- SDIO DLEN Configuration -----------------------*/\r
+ /* Set the SDIO DataLength value */\r
+ SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;\r
+\r
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/ \r
+ /* Get the SDIO DCTRL value */\r
+ tmpreg = SDIO->DCTRL;\r
+ /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */\r
+ tmpreg &= DCTRL_CLEAR_MASK;\r
+ /* Set DEN bit according to SDIO_DPSM value */\r
+ /* Set DTMODE bit according to SDIO_TransferMode value */\r
+ /* Set DTDIR bit according to SDIO_TransferDir value */\r
+ /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */\r
+ tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir\r
+ | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;\r
+\r
+ /* Write to SDIO DCTRL */\r
+ SDIO->DCTRL = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each SDIO_DataInitStruct member with its default value.\r
+ * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)\r
+{\r
+ /* SDIO_DataInitStruct members default value */\r
+ SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;\r
+ SDIO_DataInitStruct->SDIO_DataLength = 0x00;\r
+ SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;\r
+ SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;\r
+ SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; \r
+ SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Returns number of remaining data bytes to be transferred.\r
+ * @param None\r
+ * @retval Number of remaining data bytes to be transferred\r
+ */\r
+uint32_t SDIO_GetDataCounter(void)\r
+{ \r
+ return SDIO->DCOUNT;\r
+}\r
+\r
+/**\r
+ * @brief Read one data word from Rx FIFO.\r
+ * @param None\r
+ * @retval Data received\r
+ */\r
+uint32_t SDIO_ReadData(void)\r
+{ \r
+ return SDIO->FIFO;\r
+}\r
+\r
+/**\r
+ * @brief Write one data word to Tx FIFO.\r
+ * @param Data: 32-bit data word to write.\r
+ * @retval None\r
+ */\r
+void SDIO_WriteData(uint32_t Data)\r
+{ \r
+ SDIO->FIFO = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the number of words left to be written to or read from FIFO. \r
+ * @param None\r
+ * @retval Remaining number of words.\r
+ */\r
+uint32_t SDIO_GetFIFOCount(void)\r
+{ \r
+ return SDIO->FIFOCNT;\r
+}\r
+\r
+/**\r
+ * @brief Starts the SD I/O Read Wait operation. \r
+ * @param NewState: new state of the Start SDIO Read Wait operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_StartSDIOReadWait(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;\r
+}\r
+\r
+/**\r
+ * @brief Stops the SD I/O Read Wait operation. \r
+ * @param NewState: new state of the Stop SDIO Read Wait operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_StopSDIOReadWait(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;\r
+}\r
+\r
+/**\r
+ * @brief Sets one of the two options of inserting read wait interval.\r
+ * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.\r
+ * This parametre can be:\r
+ * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK\r
+ * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2\r
+ * @retval None\r
+ */\r
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));\r
+ \r
+ *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SD I/O Mode Operation.\r
+ * @param NewState: new state of SDIO specific operation. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SetSDIOOperation(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SD I/O Mode suspend command sending.\r
+ * @param NewState: new state of the SD I/O Mode suspend command.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the command completion signal.\r
+ * @param NewState: new state of command completion signal. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_CommandCompletionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CE-ATA interrupt.\r
+ * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_CEATAITCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));\r
+}\r
+\r
+/**\r
+ * @brief Sends CE-ATA command (CMD61).\r
+ * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SDIO_SendCEATACmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SDIO flag is set or not.\r
+ * @param SDIO_FLAG: specifies the flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode.\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDACT: Command transfer in progress\r
+ * @arg SDIO_FLAG_TXACT: Data transmit in progress\r
+ * @arg SDIO_FLAG_RXACT: Data receive in progress\r
+ * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty\r
+ * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full\r
+ * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full\r
+ * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full\r
+ * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty\r
+ * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty\r
+ * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO\r
+ * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval The new state of SDIO_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)\r
+{ \r
+ FlagStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_FLAG(SDIO_FLAG));\r
+ \r
+ if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SDIO's pending flags.\r
+ * @param SDIO_FLAG: specifies the flag to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)\r
+ * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)\r
+ * @arg SDIO_FLAG_CTIMEOUT: Command response timeout\r
+ * @arg SDIO_FLAG_DTIMEOUT: Data timeout\r
+ * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error\r
+ * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error\r
+ * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)\r
+ * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)\r
+ * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)\r
+ * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode\r
+ * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)\r
+ * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received\r
+ * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval None\r
+ */\r
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));\r
+ \r
+ SDIO->ICR = SDIO_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SDIO interrupt has occurred or not.\r
+ * @param SDIO_IT: specifies the SDIO interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt\r
+ * @arg SDIO_IT_TXACT: Data transmit in progress interrupt\r
+ * @arg SDIO_IT_RXACT: Data receive in progress interrupt\r
+ * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt\r
+ * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt\r
+ * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt\r
+ * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt\r
+ * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt\r
+ * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt\r
+ * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt\r
+ * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt\r
+ * @retval The new state of SDIO_IT (SET or RESET).\r
+ */\r
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)\r
+{ \r
+ ITStatus bitstatus = RESET;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_GET_IT(SDIO_IT));\r
+ if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) \r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SDIO\92s interrupt pending bits.\r
+ * @param SDIO_IT: specifies the interrupt pending bit to clear. \r
+ * This parameter can be one or a combination of the following values:\r
+ * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt\r
+ * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt\r
+ * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt\r
+ * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt\r
+ * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt\r
+ * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt\r
+ * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt\r
+ * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt\r
+ * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide \r
+ * bus mode interrupt\r
+ * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt\r
+ * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61\r
+ * @retval None\r
+ */\r
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));\r
+ \r
+ SDIO->ICR = SDIO_IT;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_spi.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the SPI firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_spi.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup SPI \r
+ * @brief SPI driver modules\r
+ * @{\r
+ */ \r
+\r
+/** @defgroup SPI_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup SPI_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* SPI SPE mask */\r
+#define CR1_SPE_Set ((uint16_t)0x0040)\r
+#define CR1_SPE_Reset ((uint16_t)0xFFBF)\r
+\r
+/* I2S I2SE mask */\r
+#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)\r
+#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)\r
+\r
+/* SPI CRCNext mask */\r
+#define CR1_CRCNext_Set ((uint16_t)0x1000)\r
+\r
+/* SPI CRCEN mask */\r
+#define CR1_CRCEN_Set ((uint16_t)0x2000)\r
+#define CR1_CRCEN_Reset ((uint16_t)0xDFFF)\r
+\r
+/* SPI SSOE mask */\r
+#define CR2_SSOE_Set ((uint16_t)0x0004)\r
+#define CR2_SSOE_Reset ((uint16_t)0xFFFB)\r
+\r
+/* SPI registers Masks */\r
+#define CR1_CLEAR_Mask ((uint16_t)0x3040)\r
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)\r
+\r
+/* SPI or I2S mode selection masks */\r
+#define SPI_Mode_Select ((uint16_t)0xF7FF)\r
+#define I2S_Mode_Select ((uint16_t)0x0800) \r
+\r
+/* I2S clock source selection masks */\r
+#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))\r
+#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))\r
+#define I2S_MUL_MASK ((uint32_t)(0x0000F000))\r
+#define I2S_DIV_MASK ((uint32_t)(0x000000F0))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup SPI_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the SPIx peripheral registers to their default\r
+ * reset values (Affects also the I2Ss).\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+\r
+ if (SPIx == SPI1)\r
+ {\r
+ /* Enable SPI1 reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);\r
+ /* Release SPI1 from reset state */\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);\r
+ }\r
+ else if (SPIx == SPI2)\r
+ {\r
+ /* Enable SPI2 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);\r
+ /* Release SPI2 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);\r
+ }\r
+ else\r
+ {\r
+ if (SPIx == SPI3)\r
+ {\r
+ /* Enable SPI3 reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);\r
+ /* Release SPI3 from reset state */\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the SPI_InitStruct.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ \r
+ /* check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx)); \r
+ \r
+ /* Check the SPI parameters */\r
+ assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));\r
+ assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));\r
+ assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));\r
+ assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));\r
+ assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));\r
+ assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));\r
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));\r
+ assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));\r
+ assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));\r
+\r
+/*---------------------------- SPIx CR1 Configuration ------------------------*/\r
+ /* Get the SPIx CR1 value */\r
+ tmpreg = SPIx->CR1;\r
+ /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler\r
+ master/salve mode, CPOL and CPHA */\r
+ /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */\r
+ /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */\r
+ /* Set LSBFirst bit according to SPI_FirstBit value */\r
+ /* Set BR bits according to SPI_BaudRatePrescaler value */\r
+ /* Set CPOL bit according to SPI_CPOL value */\r
+ /* Set CPHA bit according to SPI_CPHA value */\r
+ tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |\r
+ SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | \r
+ SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | \r
+ SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);\r
+ /* Write to SPIx CR1 */\r
+ SPIx->CR1 = tmpreg;\r
+ \r
+ /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */\r
+ SPIx->I2SCFGR &= SPI_Mode_Select; \r
+\r
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/\r
+ /* Write to SPIx CRCPOLY */\r
+ SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the SPIx peripheral according to the specified \r
+ * parameters in the I2S_InitStruct.\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral\r
+ * (configured in I2S mode).\r
+ * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that\r
+ * contains the configuration information for the specified SPI peripheral\r
+ * configured in I2S mode.\r
+ * @note\r
+ * The function calculates the optimal prescaler needed to obtain the most \r
+ * accurate audio frequency (depending on the I2S clock source, the PLL values \r
+ * and the product configuration). But in case the prescaler value is greater \r
+ * than 511, the default value (0x02) will be configured instead. * \r
+ * @retval None\r
+ */\r
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+ uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;\r
+ uint32_t tmp = 0;\r
+ RCC_ClocksTypeDef RCC_Clocks;\r
+ uint32_t sourceclock = 0;\r
+ \r
+ /* Check the I2S parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));\r
+ assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));\r
+ assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));\r
+ assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));\r
+ assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));\r
+ assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); \r
+\r
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/\r
+ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */\r
+ SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; \r
+ SPIx->I2SPR = 0x0002;\r
+ \r
+ /* Get the I2SCFGR register value */\r
+ tmpreg = SPIx->I2SCFGR;\r
+ \r
+ /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/\r
+ if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)\r
+ {\r
+ i2sodd = (uint16_t)0;\r
+ i2sdiv = (uint16_t)2; \r
+ }\r
+ /* If the requested audio frequency is not the default, compute the prescaler */\r
+ else\r
+ {\r
+ /* Check the frame length (For the Prescaler computing) */\r
+ if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)\r
+ {\r
+ /* Packet length is 16 bits */\r
+ packetlength = 1;\r
+ }\r
+ else\r
+ {\r
+ /* Packet length is 32 bits */\r
+ packetlength = 2;\r
+ }\r
+\r
+ /* Get the I2S clock source mask depending on the peripheral number */\r
+ if(((uint32_t)SPIx) == SPI2_BASE)\r
+ {\r
+ /* The mask is relative to I2S2 */\r
+ tmp = I2S2_CLOCK_SRC;\r
+ }\r
+ else \r
+ {\r
+ /* The mask is relative to I2S3 */ \r
+ tmp = I2S3_CLOCK_SRC;\r
+ }\r
+\r
+ /* Check the I2S clock source configuration depending on the Device:\r
+ Only Connectivity line devices have the PLL3 VCO clock */\r
+#ifdef STM32F10X_CL\r
+ if((RCC->CFGR2 & tmp) != 0)\r
+ {\r
+ /* Get the configuration bits of RCC PLL3 multiplier */\r
+ tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);\r
+\r
+ /* Get the value of the PLL3 multiplier */ \r
+ if((tmp > 5) && (tmp < 15))\r
+ {\r
+ /* Multplier is between 8 and 14 (value 15 is forbidden) */\r
+ tmp += 2;\r
+ }\r
+ else\r
+ {\r
+ if (tmp == 15)\r
+ {\r
+ /* Multiplier is 20 */\r
+ tmp = 20;\r
+ }\r
+ } \r
+ /* Get the PREDIV2 value */\r
+ sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1);\r
+ \r
+ /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */\r
+ sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); \r
+ }\r
+ else\r
+ {\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+ \r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency;\r
+ } \r
+#else /* STM32F10X_HD */\r
+ /* I2S Clock source is System clock: Get System Clock frequency */\r
+ RCC_GetClocksFreq(&RCC_Clocks); \r
+ \r
+ /* Get the source clock value: based on System Clock value */\r
+ sourceclock = RCC_Clocks.SYSCLK_Frequency; \r
+#endif /* STM32F10X_CL */ \r
+\r
+ /* Compute the Real divider depending on the MCLK output state with a flaoting point */\r
+ if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)\r
+ {\r
+ /* MCLK output is enabled */\r
+ tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ else\r
+ {\r
+ /* MCLK output is disabled */\r
+ tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);\r
+ }\r
+ \r
+ /* Remove the flaoting point */\r
+ tmp = tmp / 10; \r
+ \r
+ /* Check the parity of the divider */\r
+ i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);\r
+ \r
+ /* Compute the i2sdiv prescaler */\r
+ i2sdiv = (uint16_t)((tmp - i2sodd) / 2);\r
+ \r
+ /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */\r
+ i2sodd = (uint16_t) (i2sodd << 8);\r
+ }\r
+ \r
+ /* Test if the divider is 1 or 0 or greater than 0xFF */\r
+ if ((i2sdiv < 2) || (i2sdiv > 0xFF))\r
+ {\r
+ /* Set the default values */\r
+ i2sdiv = 2;\r
+ i2sodd = 0;\r
+ }\r
+\r
+ /* Write to SPIx I2SPR register the computed value */\r
+ SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); \r
+ \r
+ /* Configure the I2S with the SPI_InitStruct values */\r
+ tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \\r
+ (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \\r
+ (uint16_t)I2S_InitStruct->I2S_CPOL))));\r
+ \r
+ /* Write to SPIx I2SCFGR */ \r
+ SPIx->I2SCFGR = tmpreg; \r
+}\r
+\r
+/**\r
+ * @brief Fills each SPI_InitStruct member with its default value.\r
+ * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)\r
+{\r
+/*--------------- Reset SPI init structure parameters values -----------------*/\r
+ /* Initialize the SPI_Direction member */\r
+ SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;\r
+ /* initialize the SPI_Mode member */\r
+ SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;\r
+ /* initialize the SPI_DataSize member */\r
+ SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;\r
+ /* Initialize the SPI_CPOL member */\r
+ SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;\r
+ /* Initialize the SPI_CPHA member */\r
+ SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;\r
+ /* Initialize the SPI_NSS member */\r
+ SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;\r
+ /* Initialize the SPI_BaudRatePrescaler member */\r
+ SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;\r
+ /* Initialize the SPI_FirstBit member */\r
+ SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;\r
+ /* Initialize the SPI_CRCPolynomial member */\r
+ SPI_InitStruct->SPI_CRCPolynomial = 7;\r
+}\r
+\r
+/**\r
+ * @brief Fills each I2S_InitStruct member with its default value.\r
+ * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)\r
+{\r
+/*--------------- Reset I2S init structure parameters values -----------------*/\r
+ /* Initialize the I2S_Mode member */\r
+ I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;\r
+ \r
+ /* Initialize the I2S_Standard member */\r
+ I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;\r
+ \r
+ /* Initialize the I2S_DataFormat member */\r
+ I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;\r
+ \r
+ /* Initialize the I2S_MCLKOutput member */\r
+ I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;\r
+ \r
+ /* Initialize the I2S_AudioFreq member */\r
+ I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;\r
+ \r
+ /* Initialize the I2S_CPOL member */\r
+ I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral */\r
+ SPIx->CR1 |= CR1_SPE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral */\r
+ SPIx->CR1 &= CR1_SPE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI peripheral (in I2S mode).\r
+ * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx peripheral. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_23_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI peripheral (in I2S mode) */\r
+ SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified SPI/I2S interrupts.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask\r
+ * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask\r
+ * @arg SPI_I2S_IT_ERR: Error interrupt mask\r
+ * @param NewState: new state of the specified SPI/I2S interrupt.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)\r
+{\r
+ uint16_t itpos = 0, itmask = 0 ;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = (uint16_t)1 << (uint16_t)itpos;\r
+\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 |= itmask;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S interrupt */\r
+ SPIx->CR2 &= (uint16_t)~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SPIx/I2Sx DMA interface.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. \r
+ * This parameter can be any combination of the following values:\r
+ * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request\r
+ * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request\r
+ * @param NewState: new state of the selected SPI/I2S DMA transfer request.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 |= SPI_I2S_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI/I2S DMA requests */\r
+ SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits a Data through the SPIx/I2Sx peripheral.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param Data : Data to be transmitted.\r
+ * @retval None\r
+ */\r
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Write in the DR register the data to be sent */\r
+ SPIx->DR = Data;\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. \r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @retval The value of the received data.\r
+ */\r
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the data in the DR register */\r
+ return SPIx->DR;\r
+}\r
+\r
+/**\r
+ * @brief Configures internally by software the NSS pin for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally\r
+ * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally\r
+ * @retval None\r
+ */\r
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));\r
+ if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)\r
+ {\r
+ /* Set NSS pin internally by software */\r
+ SPIx->CR1 |= SPI_NSSInternalSoft_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Reset NSS pin internally by software */\r
+ SPIx->CR1 &= SPI_NSSInternalSoft_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the SS output for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx SS output. \r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI SS output */\r
+ SPIx->CR2 |= CR2_SSOE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI SS output */\r
+ SPIx->CR2 &= CR2_SSOE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the data size for the selected SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_DataSize: specifies the SPI data size.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_DataSize_16b: Set data frame format to 16bit\r
+ * @arg SPI_DataSize_8b: Set data frame format to 8bit\r
+ * @retval None\r
+ */\r
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DATASIZE(SPI_DataSize));\r
+ /* Clear DFF bit */\r
+ SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;\r
+ /* Set new DFF bit value */\r
+ SPIx->CR1 |= SPI_DataSize;\r
+}\r
+\r
+/**\r
+ * @brief Transmit the SPIx CRC value.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval None\r
+ */\r
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Enable the selected SPI CRC transmission */\r
+ SPIx->CR1 |= CR1_CRCNext_Set;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the CRC value calculation of the transfered bytes.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param NewState: new state of the SPIx CRC value calculation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected SPI CRC calculation */\r
+ SPIx->CR1 |= CR1_CRCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected SPI CRC calculation */\r
+ SPIx->CR1 &= CR1_CRCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the transmit or the receive CRC register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_CRC: specifies the CRC register to be read.\r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_CRC_Tx: Selects Tx CRC register\r
+ * @arg SPI_CRC_Rx: Selects Rx CRC register\r
+ * @retval The selected CRC register value..\r
+ */\r
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)\r
+{\r
+ uint16_t crcreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_CRC(SPI_CRC));\r
+ if (SPI_CRC != SPI_CRC_Rx)\r
+ {\r
+ /* Get the Tx CRC register */\r
+ crcreg = SPIx->TXCRCR;\r
+ }\r
+ else\r
+ {\r
+ /* Get the Rx CRC register */\r
+ crcreg = SPIx->RXCRCR;\r
+ }\r
+ /* Return the selected CRC register */\r
+ return crcreg;\r
+}\r
+\r
+/**\r
+ * @brief Returns the CRC Polynomial register value for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @retval The CRC Polynomial register value.\r
+ */\r
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ \r
+ /* Return the CRC polynomial register */\r
+ return SPIx->CRCPR;\r
+}\r
+\r
+/**\r
+ * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.\r
+ * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.\r
+ * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_Direction_Tx: Selects Tx transmission direction\r
+ * @arg SPI_Direction_Rx: Selects Rx receive direction\r
+ * @retval None\r
+ */\r
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_DIRECTION(SPI_Direction));\r
+ if (SPI_Direction == SPI_Direction_Tx)\r
+ {\r
+ /* Set the Tx only mode */\r
+ SPIx->CR1 |= SPI_Direction_Tx;\r
+ }\r
+ else\r
+ {\r
+ /* Set the Rx only mode */\r
+ SPIx->CR1 &= SPI_Direction_Rx;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI/I2S flag is set or not.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.\r
+ * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.\r
+ * @arg SPI_I2S_FLAG_BSY: Busy flag.\r
+ * @arg SPI_I2S_FLAG_OVR: Overrun flag.\r
+ * @arg SPI_FLAG_MODF: Mode Fault flag.\r
+ * @arg SPI_FLAG_CRCERR: CRC Error flag.\r
+ * @arg I2S_FLAG_UDR: Underrun Error flag.\r
+ * @arg I2S_FLAG_CHSIDE: Channel Side flag.\r
+ * @retval The new state of SPI_I2S_FLAG (SET or RESET).\r
+ */\r
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));\r
+ /* Check the status of the specified SPI/I2S flag */\r
+ if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)\r
+ {\r
+ /* SPI_I2S_FLAG is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_FLAG is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_FLAG status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) flag.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * @param SPI_I2S_FLAG: specifies the SPI flag to clear. \r
+ * This function clears only CRCERR flag.\r
+ * @note\r
+ * - OVR (OverRun error) flag is cleared by software sequence: a read \r
+ * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - UDR (UnderRun error) flag is cleared by a read operation to \r
+ * SPI_SR register (SPI_I2S_GetFlagStatus()).\r
+ * - MODF (Mode Fault) flag is cleared by software sequence: a read/write \r
+ * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a \r
+ * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));\r
+ \r
+ /* Clear the selected SPI CRC Error (CRCERR) flag */\r
+ SPIx->SR = (uint16_t)~SPI_I2S_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * - 2 or 3 in I2S mode\r
+ * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. \r
+ * This parameter can be one of the following values:\r
+ * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.\r
+ * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.\r
+ * @arg SPI_I2S_IT_OVR: Overrun interrupt.\r
+ * @arg SPI_IT_MODF: Mode Fault interrupt.\r
+ * @arg SPI_IT_CRCERR: CRC Error interrupt.\r
+ * @arg I2S_IT_UDR: Underrun Error interrupt.\r
+ * @retval The new state of SPI_I2S_IT (SET or RESET).\r
+ */\r
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ uint16_t itpos = 0, itmask = 0, enablestatus = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI/I2S IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Get the SPI/I2S IT mask */\r
+ itmask = SPI_I2S_IT >> 4;\r
+\r
+ /* Set the IT mask */\r
+ itmask = 0x01 << itmask;\r
+\r
+ /* Get the SPI_I2S_IT enable bit status */\r
+ enablestatus = (SPIx->CR2 & itmask) ;\r
+\r
+ /* Check the status of the specified SPI/I2S interrupt */\r
+ if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)\r
+ {\r
+ /* SPI_I2S_IT is set */\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ /* SPI_I2S_IT is reset */\r
+ bitstatus = RESET;\r
+ }\r
+ /* Return the SPI_I2S_IT status */\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.\r
+ * @param SPIx: where x can be\r
+ * - 1, 2 or 3 in SPI mode \r
+ * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.\r
+ * This function clears only CRCERR intetrrupt pending bit. \r
+ * @note\r
+ * - OVR (OverRun Error) interrupt pending bit is cleared by software \r
+ * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) \r
+ * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - UDR (UnderRun Error) interrupt pending bit is cleared by a read \r
+ * operation to SPI_SR register (SPI_I2S_GetITStatus()).\r
+ * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:\r
+ * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) \r
+ * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable \r
+ * the SPI).\r
+ * @retval None\r
+ */\r
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)\r
+{\r
+ uint16_t itpos = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_SPI_ALL_PERIPH(SPIx));\r
+ assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));\r
+\r
+ /* Get the SPI IT index */\r
+ itpos = 0x01 << (SPI_I2S_IT & 0x0F);\r
+\r
+ /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */\r
+ SPIx->SR = (uint16_t)~itpos;\r
+}\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_tim.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the TIM firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_tim.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM \r
+ * @brief TIM driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup TIM_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ---------------------- TIM registers bit mask ------------------------ */\r
+#define SMCR_ETR_Mask ((uint16_t)0x00FF) \r
+#define CCMR_Offset ((uint16_t)0x0018)\r
+#define CCER_CCE_Set ((uint16_t)0x0001) \r
+#define CCER_CCNE_Set ((uint16_t)0x0004) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter);\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup TIM_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the TIMx peripheral registers to their default reset values.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_DeInit(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ \r
+ if (TIMx == TIM1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); \r
+ } \r
+ else if (TIMx == TIM2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);\r
+ }\r
+ else if (TIMx == TIM3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);\r
+ }\r
+ else if (TIMx == TIM4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);\r
+ } \r
+ else if (TIMx == TIM5)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);\r
+ } \r
+ else if (TIMx == TIM6)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);\r
+ } \r
+ else if (TIMx == TIM7)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);\r
+ } \r
+ else if (TIMx == TIM8)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);\r
+ }\r
+ else if (TIMx == TIM9)\r
+ { \r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); \r
+ } \r
+ else if (TIMx == TIM10)\r
+ { \r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); \r
+ } \r
+ else if (TIMx == TIM11) \r
+ { \r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); \r
+ } \r
+ else if (TIMx == TIM12)\r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); \r
+ } \r
+ else if (TIMx == TIM13) \r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); \r
+ }\r
+ else if (TIMx == TIM14) \r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); \r
+ } \r
+ else if (TIMx == TIM15)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);\r
+ } \r
+ else if (TIMx == TIM16)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (TIMx == TIM17)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);\r
+ } \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Time Base Unit peripheral according to \r
+ * the specified parameters in the TIM_TimeBaseInitStruct.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));\r
+\r
+ tmpcr1 = TIMx->CR1; \r
+\r
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||\r
+ (TIMx == TIM4) || (TIMx == TIM5)) \r
+ {\r
+ /* Select the Counter Mode */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;\r
+ }\r
+ \r
+ if((TIMx != TIM6) && (TIMx != TIM7))\r
+ {\r
+ /* Set the clock division */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));\r
+ tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;\r
+ }\r
+\r
+ TIMx->CR1 = tmpcr1;\r
+\r
+ /* Set the Autoreload value */\r
+ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;\r
+ \r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;\r
+ \r
+ if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) \r
+ {\r
+ /* Set the Repetition Counter value */\r
+ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;\r
+ }\r
+\r
+ /* Generate an update event to reload the Prescaler and the Repetition counter\r
+ values immediately */\r
+ TIMx->EGR = TIM_PSCReloadMode_Immediate; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel1 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);\r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare Mode Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));\r
+\r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputState;\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||\r
+ (TIMx == TIM16)|| (TIMx == TIM17))\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;\r
+ \r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); \r
+ /* Set the Output N State */\r
+ tmpccer |= TIM_OCInitStruct->TIM_OutputNState;\r
+ \r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));\r
+ \r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; \r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel2 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));\r
+ \r
+ /* Get the TIMx CCER register value */ \r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmrx = TIMx->CCMR1;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8))\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);\r
+ \r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); \r
+ /* Set the Output N State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);\r
+ \r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));\r
+ \r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel3 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8))\r
+ {\r
+ assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));\r
+ assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ \r
+ /* Reset the Output N Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));\r
+ /* Set the Output N Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);\r
+ /* Reset the Output N State */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));\r
+ \r
+ /* Set the Output N State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);\r
+ /* Reset the Ouput Compare and Output Compare N IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);\r
+ /* Set the Output N Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIMx Channel4 according to the specified\r
+ * parameters in the TIM_OCInitStruct.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));\r
+ assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); \r
+ /* Disable the Channel 2: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ /* Get the TIMx CR2 register value */\r
+ tmpcr2 = TIMx->CR2;\r
+ \r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmrx = TIMx->CCMR2;\r
+ \r
+ /* Reset the Output Compare mode and Capture/Compare selection Bits */\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));\r
+ tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));\r
+ \r
+ /* Select the Output Compare Mode */\r
+ tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);\r
+ \r
+ /* Reset the Output Polarity level */\r
+ tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));\r
+ /* Set the Output Compare Polarity */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);\r
+ \r
+ /* Set the Output State */\r
+ tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8))\r
+ {\r
+ assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));\r
+ /* Reset the Ouput Compare IDLE State */\r
+ tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));\r
+ /* Set the Output Idle state */\r
+ tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);\r
+ }\r
+ /* Write to TIMx CR2 */\r
+ TIMx->CR2 = tmpcr2;\r
+ \r
+ /* Write to TIMx CCMR2 */ \r
+ TIMx->CCMR2 = tmpccmrx;\r
+\r
+ /* Set the Capture Compare Register value */\r
+ TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;\r
+ \r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); \r
+ assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));\r
+ assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)\r
+ {\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)\r
+ {\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* TI3 Configuration */\r
+ TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ {\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* TI4 Configuration */\r
+ TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,\r
+ TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIM peripheral according to the specified\r
+ * parameters in the TIM_ICInitStruct to measure an external PWM signal.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure\r
+ * that contains the configuration information for the specified TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ uint16_t icoppositepolarity = TIM_ICPolarity_Rising;\r
+ uint16_t icoppositeselection = TIM_ICSelection_DirectTI;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Select the Opposite Input Polarity */\r
+ if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Falling;\r
+ }\r
+ else\r
+ {\r
+ icoppositepolarity = TIM_ICPolarity_Rising;\r
+ }\r
+ /* Select the Opposite Input */\r
+ if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)\r
+ {\r
+ icoppositeselection = TIM_ICSelection_IndirectTI;\r
+ }\r
+ else\r
+ {\r
+ icoppositeselection = TIM_ICSelection_DirectTI;\r
+ }\r
+ if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)\r
+ {\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+ else\r
+ { \r
+ /* TI2 Configuration */\r
+ TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,\r
+ TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ /* TI1 Configuration */\r
+ TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);\r
+ /* Set the Input Capture Prescaler value */\r
+ TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the: Break feature, dead time, Lock level, the OSSI,\r
+ * the OSSR State and the AOE(automatic output enable).\r
+ * @param TIMx: where x can be 1 or 8 to select the TIM \r
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that\r
+ * contains the BDTR Register configuration information for the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));\r
+ assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));\r
+ assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));\r
+ assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));\r
+ assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));\r
+ assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));\r
+ /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,\r
+ the OSSI State, the dead time value and the Automatic Output Enable Bit */\r
+ TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |\r
+ TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |\r
+ TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |\r
+ TIM_BDTRInitStruct->TIM_AutomaticOutput;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_TimeBaseInitStruct member with its default value.\r
+ * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;\r
+ TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;\r
+ TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;\r
+ TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;\r
+ TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_OCInitStruct member with its default value.\r
+ * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;\r
+ TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;\r
+ TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;\r
+ TIM_OCInitStruct->TIM_Pulse = 0x0000;\r
+ TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;\r
+ TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;\r
+ TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;\r
+ TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_ICInitStruct member with its default value.\r
+ * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will\r
+ * be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;\r
+ TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;\r
+ TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;\r
+ TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;\r
+ TIM_ICInitStruct->TIM_ICFilter = 0x00;\r
+}\r
+\r
+/**\r
+ * @brief Fills each TIM_BDTRInitStruct member with its default value.\r
+ * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which\r
+ * will be initialized.\r
+ * @retval None\r
+ */\r
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)\r
+{\r
+ /* Set the default configuration */\r
+ TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;\r
+ TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;\r
+ TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;\r
+ TIM_BDTRInitStruct->TIM_DeadTime = 0x00;\r
+ TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;\r
+ TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;\r
+ TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM peripheral.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIMx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Counter */\r
+ TIMx->CR1 |= TIM_CR1_CEN;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Counter */\r
+ TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM peripheral Main Outputs.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.\r
+ * @param NewState: new state of the TIM peripheral Main Outputs.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the TIM Main Output */\r
+ TIMx->BDTR |= TIM_BDTR_MOE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the TIM Main Output */\r
+ TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified TIM interrupts.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update interrupt.\r
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
+ * TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @param NewState: new state of the TIM interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Interrupt sources */\r
+ TIMx->DIER |= TIM_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Interrupt sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx event to be generate by software.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_EventSource: specifies the event source.\r
+ * This parameter can be one or more of the following values: \r
+ * @arg TIM_EventSource_Update: Timer update Event source\r
+ * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source\r
+ * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source\r
+ * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source\r
+ * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source\r
+ * @arg TIM_EventSource_COM: Timer COM event source \r
+ * @arg TIM_EventSource_Trigger: Timer Trigger Event source\r
+ * @arg TIM_EventSource_Break: Timer Break event source\r
+ * @note \r
+ * - TIM6 and TIM7 can only generate an update event. \r
+ * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. \r
+ * @retval None\r
+ */\r
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));\r
+ \r
+ /* Set the event sources */\r
+ TIMx->EGR = TIM_EventSource;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx\92s DMA interface.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_DMABase: DMA Base address.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,\r
+ * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,\r
+ * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,\r
+ * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,\r
+ * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,\r
+ * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,\r
+ * TIM_DMABase_DCR.\r
+ * @param TIM_DMABurstLength: DMA Burst length.\r
+ * This parameter can be one value between:\r
+ * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes.\r
+ * @retval None\r
+ */\r
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_BASE(TIM_DMABase));\r
+ assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));\r
+ /* Set the DMA Base and the DMA Burst Length */\r
+ TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s DMA Requests.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 \r
+ * to select the TIM peripheral. \r
+ * @param TIM_DMASource: specifies the DMA Request sources.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_DMA_Update: TIM update Interrupt source\r
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\r
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\r
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\r
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\r
+ * @arg TIM_DMA_COM: TIM Commutation DMA source\r
+ * @arg TIM_DMA_Trigger: TIM Trigger DMA source\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST9_PERIPH(TIMx));\r
+ assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA sources */\r
+ TIMx->DIER |= TIM_DMASource; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA sources */\r
+ TIMx->DIER &= (uint16_t)~TIM_DMASource;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx interrnal Clock\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15\r
+ * to select the TIM peripheral.\r
+ * @retval None\r
+ */\r
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Disable slave mode to clock the prescaler directly with the internal clock */\r
+ TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Internal Trigger as External Clock\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ITRSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @param TIM_TS_ITR0: Internal Trigger 0\r
+ * @param TIM_TS_ITR1: Internal Trigger 1\r
+ * @param TIM_TS_ITR2: Internal Trigger 2\r
+ * @param TIM_TS_ITR3: Internal Trigger 3\r
+ * @retval None\r
+ */\r
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Select the Internal Trigger */\r
+ TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Trigger as External Clock\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_TIxExternalCLKSource: Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector\r
+ * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1\r
+ * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2\r
+ * @param TIM_ICPolarity: specifies the TIx Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param ICFilter : specifies the filter value.\r
+ * This parameter must be a value between 0x0 and 0xF.\r
+ * @retval None\r
+ */\r
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,\r
+ uint16_t TIM_ICPolarity, uint16_t ICFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));\r
+ assert_param(IS_TIM_IC_FILTER(ICFilter));\r
+ /* Configure the Timer Input Clock Source */\r
+ if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)\r
+ {\r
+ TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ else\r
+ {\r
+ TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);\r
+ }\r
+ /* Select the Trigger source */\r
+ TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);\r
+ /* Select the External clock mode1 */\r
+ TIMx->SMCR |= TIM_SlaveMode_External1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode1\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ \r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the SMS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ /* Select the External clock mode1 */\r
+ tmpsmcr |= TIM_SlaveMode_External1;\r
+ /* Select the Trigger selection : ETRF */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ tmpsmcr |= TIM_TS_ETRF;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the External clock Mode2\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, \r
+ uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ /* Configure the ETR Clock source */\r
+ TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);\r
+ /* Enable the External clock mode2 */\r
+ TIMx->SMCR |= TIM_SMCR_ECE;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx External Trigger (ETR).\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.\r
+ * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.\r
+ * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.\r
+ * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.\r
+ * @param TIM_ExtTRGPolarity: The external Trigger Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.\r
+ * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.\r
+ * @param ExtTRGFilter: External Trigger Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F\r
+ * @retval None\r
+ */\r
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,\r
+ uint16_t ExtTRGFilter)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));\r
+ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));\r
+ assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the ETR Bits */\r
+ tmpsmcr &= SMCR_ETR_Mask;\r
+ /* Set the Prescaler, the Filter value and the Polarity */\r
+ tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Prescaler.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param Prescaler: specifies the Prescaler Register value\r
+ * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.\r
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.\r
+ * @retval None\r
+ */\r
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));\r
+ /* Set the Prescaler value */\r
+ TIMx->PSC = Prescaler;\r
+ /* Set or reset the UG Bit */\r
+ TIMx->EGR = TIM_PSCReloadMode;\r
+}\r
+\r
+/**\r
+ * @brief Specifies the TIMx Counter Mode to be used.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_CounterMode: specifies the Counter Mode to be used\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_CounterMode_Up: TIM Up Counting Mode\r
+ * @arg TIM_CounterMode_Down: TIM Down Counting Mode\r
+ * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1\r
+ * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2\r
+ * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3\r
+ * @retval None\r
+ */\r
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)\r
+{\r
+ uint16_t tmpcr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));\r
+ tmpcr1 = TIMx->CR1;\r
+ /* Reset the CMS and DIR Bits */\r
+ tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));\r
+ /* Set the Counter Mode */\r
+ tmpcr1 |= TIM_CounterMode;\r
+ /* Write to TIMx CR1 register */\r
+ TIMx->CR1 = tmpcr1;\r
+}\r
+\r
+/**\r
+ * @brief Selects the Input Trigger source\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_InputTriggerSource: The Input Trigger source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_TS_ITR0: Internal Trigger 0\r
+ * @arg TIM_TS_ITR1: Internal Trigger 1\r
+ * @arg TIM_TS_ITR2: Internal Trigger 2\r
+ * @arg TIM_TS_ITR3: Internal Trigger 3\r
+ * @arg TIM_TS_TI1F_ED: TI1 Edge Detector\r
+ * @arg TIM_TS_TI1FP1: Filtered Timer Input 1\r
+ * @arg TIM_TS_TI2FP2: Filtered Timer Input 2\r
+ * @arg TIM_TS_ETRF: External Trigger input\r
+ * @retval None\r
+ */\r
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ /* Reset the TS Bits */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));\r
+ /* Set the Input Trigger source */\r
+ tmpsmcr |= TIM_InputTriggerSource;\r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Encoder Interface.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.\r
+ * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.\r
+ * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending\r
+ * on the level of the other input.\r
+ * @param TIM_IC1Polarity: specifies the IC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @param TIM_IC2Polarity: specifies the IC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Falling: IC Falling edge.\r
+ * @arg TIM_ICPolarity_Rising: IC Rising edge.\r
+ * @retval None\r
+ */\r
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,\r
+ uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)\r
+{\r
+ uint16_t tmpsmcr = 0;\r
+ uint16_t tmpccmr1 = 0;\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));\r
+ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));\r
+\r
+ /* Get the TIMx SMCR register value */\r
+ tmpsmcr = TIMx->SMCR;\r
+ \r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ \r
+ /* Get the TIMx CCER register value */\r
+ tmpccer = TIMx->CCER;\r
+ \r
+ /* Set the encoder Mode */\r
+ tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));\r
+ tmpsmcr |= TIM_EncoderMode;\r
+ \r
+ /* Select the Capture Compare 1 and the Capture Compare 2 as input */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));\r
+ tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;\r
+ \r
+ /* Set the TI1 and the TI2 Polarities */\r
+ tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));\r
+ tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));\r
+ \r
+ /* Write to TIMx SMCR */\r
+ TIMx->SMCR = tmpsmcr;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ /* Write to TIMx CCER */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 1 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC1REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 2 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC2REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 3 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC3REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC1M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= TIM_ForcedAction;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Forces the TIMx output 4 waveform to active or inactive level.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ForcedAction_Active: Force active level on OC4REF\r
+ * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.\r
+ * @retval None\r
+ */\r
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC2M Bits */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);\r
+ /* Configure The Forced output Mode */\r
+ tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables TIMx peripheral Preload register on ARR.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx peripheral Preload register\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the ARR Preload Bit */\r
+ TIMx->CR1 |= TIM_CR1_ARPE;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the ARR Preload Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM peripheral Commutation event.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral\r
+ * @param NewState: new state of the Commutation event.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the COM Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCUS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the COM Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx peripheral Capture Compare DMA source.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select \r
+ * the TIM peripheral.\r
+ * @param NewState: new state of the Capture Compare DMA source\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST4_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCDS Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCDS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCDS Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 \r
+ * to select the TIMx peripheral\r
+ * @param NewState: new state of the Capture Compare Preload Control bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST5_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the CCPC Bit */\r
+ TIMx->CR2 |= TIM_CR2_CCPC;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the CCPC Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR1.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR2.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2PE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR3.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= TIM_OCPreload;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx peripheral Preload register on CCR4.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPreload: new state of the TIMx peripheral Preload register\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCPreload_Enable\r
+ * @arg TIM_OCPreload_Disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4PE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);\r
+ /* Enable or Disable the Output Compare Preload feature */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 1 Fast feature.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC1FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 2 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR1 register value */\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2FE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR1 */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 3 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= TIM_OCFast;\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Output Compare 4 Fast feature.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCFast_Enable: TIM output compare fast enable\r
+ * @arg TIM_OCFast_Disable: TIM output compare fast disable\r
+ * @retval None\r
+ */\r
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));\r
+ /* Get the TIMx CCMR2 register value */\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4FE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);\r
+ /* Enable or Disable the Output Compare Fast Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);\r
+ /* Write to TIMx CCMR2 */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF1 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+\r
+ tmpccmr1 = TIMx->CCMR1;\r
+\r
+ /* Reset the OC1CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF2 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr1 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ /* Reset the OC2CE Bit */\r
+ tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR1 register */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF3 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC3CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= TIM_OCClear;\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Clears or safeguards the OCREF4 signal on an external event\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OCClear_Enable: TIM Output clear enable\r
+ * @arg TIM_OCClear_Disable: TIM Output clear disable\r
+ * @retval None\r
+ */\r
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)\r
+{\r
+ uint16_t tmpccmr2 = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ /* Reset the OC4CE Bit */\r
+ tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);\r
+ /* Enable or Disable the Output Compare Clear Bit */\r
+ tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);\r
+ /* Write to TIMx CCMR2 register */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 1 polarity.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC1 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);\r
+ tmpccer |= TIM_OCPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 1N polarity.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC1N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC1NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);\r
+ tmpccer |= TIM_OCNPolarity;\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 2 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC2 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 2N polarity.\r
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC2N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC2NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);\r
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 3 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC3 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Channel 3N polarity.\r
+ * @param TIMx: where x can be 1 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCNPolarity: specifies the OC3N Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCNPolarity_High: Output Compare active high\r
+ * @arg TIM_OCNPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST1_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));\r
+ \r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC3NP Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);\r
+ tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx channel 4 polarity.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_OCPolarity: specifies the OC4 Polarity\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_OCPolarity_High: Output Compare active high\r
+ * @arg TIM_OCPolarity_Low: Output Compare active low\r
+ * @retval None\r
+ */\r
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)\r
+{\r
+ uint16_t tmpccer = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));\r
+ tmpccer = TIMx->CCER;\r
+ /* Set or Reset the CC4P Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);\r
+ tmpccer |= (uint16_t)(TIM_OCPolarity << 12);\r
+ /* Write to TIMx CCER register */\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel x.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.\r
+ * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
+ assert_param(IS_TIM_CCX(TIM_CCx));\r
+\r
+ tmp = CCER_CCE_Set << TIM_Channel;\r
+\r
+ /* Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t)~ tmp;\r
+\r
+ /* Set or reset the CCxE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIM Capture Compare Channel xN.\r
+ * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.\r
+ * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. \r
+ * @retval None\r
+ */\r
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)\r
+{\r
+ uint16_t tmp = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST2_PERIPH(TIMx));\r
+ assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));\r
+ assert_param(IS_TIM_CCXN(TIM_CCxN));\r
+\r
+ tmp = CCER_CCNE_Set << TIM_Channel;\r
+\r
+ /* Reset the CCxNE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp;\r
+\r
+ /* Set or reset the CCxNE Bit */ \r
+ TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIM Ouput Compare Mode.\r
+ * @note This function disables the selected channel before changing the Ouput\r
+ * Compare Mode.\r
+ * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_Channel: specifies the TIM Channel\r
+ * This parmeter can be one of the following values:\r
+ * @arg TIM_Channel_1: TIM Channel 1\r
+ * @arg TIM_Channel_2: TIM Channel 2\r
+ * @arg TIM_Channel_3: TIM Channel 3\r
+ * @arg TIM_Channel_4: TIM Channel 4\r
+ * @param TIM_OCMode: specifies the TIM Output Compare Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_OCMode_Timing\r
+ * @arg TIM_OCMode_Active\r
+ * @arg TIM_OCMode_Toggle\r
+ * @arg TIM_OCMode_PWM1\r
+ * @arg TIM_OCMode_PWM2\r
+ * @arg TIM_ForcedAction_Active\r
+ * @arg TIM_ForcedAction_InActive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)\r
+{\r
+ uint32_t tmp = 0;\r
+ uint16_t tmp1 = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CHANNEL(TIM_Channel));\r
+ assert_param(IS_TIM_OCM(TIM_OCMode));\r
+\r
+ tmp = (uint32_t) TIMx;\r
+ tmp += CCMR_Offset;\r
+\r
+ tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;\r
+\r
+ /* Disable the Channel: Reset the CCxE Bit */\r
+ TIMx->CCER &= (uint16_t) ~tmp1;\r
+\r
+ if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))\r
+ {\r
+ tmp += (TIM_Channel>>1);\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= TIM_OCMode;\r
+ }\r
+ else\r
+ {\r
+ tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;\r
+\r
+ /* Reset the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);\r
+ \r
+ /* Configure the OCxM bits in the CCMRx register */\r
+ *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or Disables the TIMx Update event.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx UDIS bit\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the Update Disable Bit */\r
+ TIMx->CR1 |= TIM_CR1_UDIS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the Update Disable Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the TIMx Update Request Interrupt source.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_UpdateSource: specifies the Update source.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow\r
+ or the setting of UG bit, or an update generation\r
+ through the slave mode controller.\r
+ * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.\r
+ * @retval None\r
+ */\r
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));\r
+ if (TIM_UpdateSource != TIM_UpdateSource_Global)\r
+ {\r
+ /* Set the URS Bit */\r
+ TIMx->CR1 |= TIM_CR1_URS;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the URS Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the TIMx\92s Hall sensor interface.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param NewState: new state of the TIMx Hall sensor interface.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Set the TI1S Bit */\r
+ TIMx->CR2 |= TIM_CR2_TI1S;\r
+ }\r
+ else\r
+ {\r
+ /* Reset the TI1S Bit */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx\92s One Pulse Mode.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_OPMode: specifies the OPM Mode to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_OPMode_Single\r
+ * @arg TIM_OPMode_Repetitive\r
+ * @retval None\r
+ */\r
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_OPM_MODE(TIM_OPMode));\r
+ /* Reset the OPM Bit */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);\r
+ /* Configure the OPM Mode */\r
+ TIMx->CR1 |= TIM_OPMode;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Trigger Output Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_TRGOSource: specifies the Trigger Output source.\r
+ * This paramter can be one of the following values:\r
+ *\r
+ * - For all TIMx\r
+ * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).\r
+ *\r
+ * - For all TIMx except TIM6 and TIM7\r
+ * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag\r
+ * is to be set, as soon as a capture or compare match occurs (TRGO).\r
+ * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).\r
+ * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).\r
+ *\r
+ * @retval None\r
+ */\r
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST7_PERIPH(TIMx));\r
+ assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));\r
+ /* Reset the MMS Bits */\r
+ TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);\r
+ /* Select the TRGO source */\r
+ TIMx->CR2 |= TIM_TRGOSource;\r
+}\r
+\r
+/**\r
+ * @brief Selects the TIMx Slave Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_SlaveMode: specifies the Timer Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes\r
+ * the counter and triggers an update of the registers.\r
+ * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.\r
+ * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.\r
+ * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.\r
+ * @retval None\r
+ */\r
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));\r
+ /* Reset the SMS Bits */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);\r
+ /* Select the Slave Mode */\r
+ TIMx->SMCR |= TIM_SlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets or Resets the TIMx Master/Slave Mode.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.\r
+ * This paramter can be one of the following values:\r
+ * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer\r
+ * and its slaves (through TRGO).\r
+ * @arg TIM_MasterSlaveMode_Disable: No action\r
+ * @retval None\r
+ */\r
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));\r
+ /* Reset the MSM Bit */\r
+ TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);\r
+ \r
+ /* Set or Reset the MSM Bit */\r
+ TIMx->SMCR |= TIM_MasterSlaveMode;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Counter Register value\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param Counter: specifies the Counter register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Set the Counter Register value */\r
+ TIMx->CNT = Counter;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Autoreload Register value\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param Autoreload: specifies the Autoreload register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Set the Autoreload Register value */\r
+ TIMx->ARR = Autoreload;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare1 Register value\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param Compare1: specifies the Capture Compare1 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ /* Set the Capture Compare1 Register value */\r
+ TIMx->CCR1 = Compare1;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare2 Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param Compare2: specifies the Capture Compare2 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Set the Capture Compare2 Register value */\r
+ TIMx->CCR2 = Compare2;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare3 Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param Compare3: specifies the Capture Compare3 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* Set the Capture Compare3 Register value */\r
+ TIMx->CCR3 = Compare3;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Capture Compare4 Register value\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param Compare4: specifies the Capture Compare4 register new value.\r
+ * @retval None\r
+ */\r
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* Set the Capture Compare4 Register value */\r
+ TIMx->CCR4 = Compare4;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 1 prescaler.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC1PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);\r
+ /* Set the IC1PSC value */\r
+ TIMx->CCMR1 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 2 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC2PSC Bits */\r
+ TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);\r
+ /* Set the IC2PSC value */\r
+ TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 3 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC3PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);\r
+ /* Set the IC3PSC value */\r
+ TIMx->CCMR2 |= TIM_ICPSC;\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Input Capture 4 prescaler.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPSC_DIV1: no prescaler\r
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events\r
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events\r
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events\r
+ * @retval None\r
+ */\r
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));\r
+ /* Reset the IC4PSC Bits */\r
+ TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);\r
+ /* Set the IC4PSC value */\r
+ TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);\r
+}\r
+\r
+/**\r
+ * @brief Sets the TIMx Clock Division value.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select \r
+ * the TIM peripheral.\r
+ * @param TIM_CKD: specifies the clock division value.\r
+ * This parameter can be one of the following value:\r
+ * @arg TIM_CKD_DIV1: TDTS = Tck_tim\r
+ * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim\r
+ * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim\r
+ * @retval None\r
+ */\r
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CKD_DIV(TIM_CKD));\r
+ /* Reset the CKD Bits */\r
+ TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);\r
+ /* Set the CKD value */\r
+ TIMx->CR1 |= TIM_CKD;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 1 value.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @retval Capture Compare 1 Register value.\r
+ */\r
+uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST8_PERIPH(TIMx));\r
+ /* Get the Capture 1 Register value */\r
+ return TIMx->CCR1;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 2 value.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @retval Capture Compare 2 Register value.\r
+ */\r
+uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST6_PERIPH(TIMx));\r
+ /* Get the Capture 2 Register value */\r
+ return TIMx->CCR2;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 3 value.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @retval Capture Compare 3 Register value.\r
+ */\r
+uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx)); \r
+ /* Get the Capture 3 Register value */\r
+ return TIMx->CCR3;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Input Capture 4 value.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @retval Capture Compare 4 Register value.\r
+ */\r
+uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_LIST3_PERIPH(TIMx));\r
+ /* Get the Capture 4 Register value */\r
+ return TIMx->CCR4;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Counter value.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @retval Counter Register value.\r
+ */\r
+uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Get the Counter Register value */\r
+ return TIMx->CNT;\r
+}\r
+\r
+/**\r
+ * @brief Gets the TIMx Prescaler value.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @retval Prescaler Register value.\r
+ */\r
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ /* Get the Prescaler Register value */\r
+ return TIMx->PSC;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified TIM flag is set or not.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_COM: TIM Commutation Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_Break: TIM Break Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag. \r
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval The new state of TIM_FLAG (SET or RESET).\r
+ */\r
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ ITStatus bitstatus = RESET; \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_FLAG(TIM_FLAG));\r
+ \r
+ if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's pending flags.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_FLAG: specifies the flag bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_FLAG_Update: TIM update Flag\r
+ * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag\r
+ * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag\r
+ * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag\r
+ * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag\r
+ * @arg TIM_FLAG_COM: TIM Commutation Flag\r
+ * @arg TIM_FLAG_Trigger: TIM Trigger Flag\r
+ * @arg TIM_FLAG_Break: TIM Break Flag\r
+ * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag\r
+ * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag\r
+ * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag\r
+ * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag\r
+ * @note\r
+ * - TIM6 and TIM7 can have only one update flag. \r
+ * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,\r
+ * TIM_FLAG_CC2 or TIM_FLAG_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. \r
+ * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval None\r
+ */\r
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));\r
+ \r
+ /* Clear the flags */\r
+ TIMx->SR = (uint16_t)~TIM_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the TIM interrupt has occurred or not.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the TIM interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_IT_Update: TIM update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
+ * TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval The new state of the TIM_IT(SET or RESET).\r
+ */\r
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ ITStatus bitstatus = RESET; \r
+ uint16_t itstatus = 0x0, itenable = 0x0;\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_GET_IT(TIM_IT));\r
+ \r
+ itstatus = TIMx->SR & TIM_IT;\r
+ \r
+ itenable = TIMx->DIER & TIM_IT;\r
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the TIMx's interrupt pending bits.\r
+ * @param TIMx: where x can be 1 to 17 to select the TIM peripheral.\r
+ * @param TIM_IT: specifies the pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg TIM_IT_Update: TIM1 update Interrupt source\r
+ * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source\r
+ * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source\r
+ * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source\r
+ * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source\r
+ * @arg TIM_IT_COM: TIM Commutation Interrupt source\r
+ * @arg TIM_IT_Trigger: TIM Trigger Interrupt source\r
+ * @arg TIM_IT_Break: TIM Break Interrupt source\r
+ * @note\r
+ * - TIM6 and TIM7 can generate only an update interrupt.\r
+ * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,\r
+ * TIM_IT_CC2 or TIM_IT_Trigger. \r
+ * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. \r
+ * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. \r
+ * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. \r
+ * @retval None\r
+ */\r
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_TIM_ALL_PERIPH(TIMx));\r
+ assert_param(IS_TIM_IT(TIM_IT));\r
+ /* Clear the IT pending Bit */\r
+ TIMx->SR = (uint16_t)~TIM_IT;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI1 as Input.\r
+ * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0;\r
+ /* Disable the Channel 1: Reset the CC1E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC1E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);\r
+ }\r
+\r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI2 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;\r
+ /* Disable the Channel 2: Reset the CC2E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);\r
+ tmpccmr1 = TIMx->CCMR1;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 4);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));\r
+ tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);\r
+ tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC2E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);\r
+ }\r
+ \r
+ /* Write to TIMx CCMR1 and CCER registers */\r
+ TIMx->CCMR1 = tmpccmr1 ;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI3 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+ /* Disable the Channel 3: Reset the CC3E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 8);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC3E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);\r
+ }\r
+ \r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @brief Configure the TI4 as Input.\r
+ * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.\r
+ * @param TIM_ICPolarity : The Input Polarity.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICPolarity_Rising\r
+ * @arg TIM_ICPolarity_Falling\r
+ * @param TIM_ICSelection: specifies the input to be used.\r
+ * This parameter can be one of the following values:\r
+ * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.\r
+ * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.\r
+ * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.\r
+ * @param TIM_ICFilter: Specifies the Input Capture Filter.\r
+ * This parameter must be a value between 0x00 and 0x0F.\r
+ * @retval None\r
+ */\r
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,\r
+ uint16_t TIM_ICFilter)\r
+{\r
+ uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;\r
+\r
+ /* Disable the Channel 4: Reset the CC4E Bit */\r
+ TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);\r
+ tmpccmr2 = TIMx->CCMR2;\r
+ tmpccer = TIMx->CCER;\r
+ tmp = (uint16_t)(TIM_ICPolarity << 12);\r
+ /* Select the Input and set the filter */\r
+ tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));\r
+ tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);\r
+ tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);\r
+ \r
+ if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||\r
+ (TIMx == TIM4) ||(TIMx == TIM5))\r
+ {\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));\r
+ tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);\r
+ }\r
+ else\r
+ {\r
+ /* Select the Polarity and set the CC4E Bit */\r
+ tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));\r
+ tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);\r
+ }\r
+ /* Write to TIMx CCMR2 and CCER registers */\r
+ TIMx->CCMR2 = tmpccmr2;\r
+ TIMx->CCER = tmpccer;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_usart.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the USART firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_usart.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART \r
+ * @brief USART driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup USART_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Defines\r
+ * @{\r
+ */\r
+\r
+#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */\r
+#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */\r
+\r
+#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */\r
+\r
+#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */\r
+#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */\r
+#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */\r
+#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */\r
+#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */\r
+\r
+#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */\r
+#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */\r
+\r
+#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */\r
+#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */\r
+#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */\r
+\r
+#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */\r
+#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */\r
+\r
+#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */\r
+#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */\r
+\r
+#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */\r
+#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */\r
+\r
+#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */\r
+#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */\r
+\r
+#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */\r
+#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */\r
+#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */\r
+#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */\r
+#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */\r
+\r
+/* USART OverSampling-8 Mask */\r
+#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */\r
+#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */\r
+\r
+/* USART One Bit Sampling Mask */\r
+#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */\r
+#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup USART_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the USARTx peripheral registers to their default reset values.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval None\r
+ */\r
+void USART_DeInit(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+\r
+ if (USARTx == USART1)\r
+ {\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);\r
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);\r
+ }\r
+ else if (USARTx == USART2)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);\r
+ }\r
+ else if (USARTx == USART3)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);\r
+ } \r
+ else if (USARTx == UART4)\r
+ {\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);\r
+ } \r
+ else\r
+ {\r
+ if (USARTx == UART5)\r
+ { \r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral according to the specified\r
+ * parameters in the USART_InitStruct .\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * that contains the configuration information for the specified USART peripheral.\r
+ * @retval None\r
+ */\r
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00, apbclock = 0x00;\r
+ uint32_t integerdivider = 0x00;\r
+ uint32_t fractionaldivider = 0x00;\r
+ uint32_t usartxbase = 0;\r
+ RCC_ClocksTypeDef RCC_ClocksStatus;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); \r
+ assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));\r
+ assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));\r
+ assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));\r
+ assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));\r
+ assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));\r
+ /* The hardware flow control is available only for USART1, USART2 and USART3 */\r
+ if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ }\r
+\r
+ usartxbase = (uint32_t)USARTx;\r
+\r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear STOP[13:12] bits */\r
+ tmpreg &= CR2_STOP_CLEAR_Mask;\r
+ /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set STOP[13:12] bits according to USART_StopBits value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;\r
+ \r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR1 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR1;\r
+ /* Clear M, PCE, PS, TE and RE bits */\r
+ tmpreg &= CR1_CLEAR_Mask;\r
+ /* Configure the USART Word Length, Parity and mode ----------------------- */\r
+ /* Set the M bits according to USART_WordLength value */\r
+ /* Set PCE and PS bits according to USART_Parity value */\r
+ /* Set TE and RE bits according to USART_Mode value */\r
+ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |\r
+ USART_InitStruct->USART_Mode;\r
+ /* Write to USART CR1 */\r
+ USARTx->CR1 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART CR3 Configuration -----------------------*/ \r
+ tmpreg = USARTx->CR3;\r
+ /* Clear CTSE and RTSE bits */\r
+ tmpreg &= CR3_CLEAR_Mask;\r
+ /* Configure the USART HFC -------------------------------------------------*/\r
+ /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */\r
+ tmpreg |= USART_InitStruct->USART_HardwareFlowControl;\r
+ /* Write to USART CR3 */\r
+ USARTx->CR3 = (uint16_t)tmpreg;\r
+\r
+/*---------------------------- USART BRR Configuration -----------------------*/\r
+ /* Configure the USART Baud Rate -------------------------------------------*/\r
+ RCC_GetClocksFreq(&RCC_ClocksStatus);\r
+ if (usartxbase == USART1_BASE)\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK2_Frequency;\r
+ }\r
+ else\r
+ {\r
+ apbclock = RCC_ClocksStatus.PCLK1_Frequency;\r
+ }\r
+ \r
+ /* Determine the integer part */\r
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 8 Samples */\r
+ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ /* Integer part computing in case Oversampling mode is 16 Samples */\r
+ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); \r
+ }\r
+ tmpreg = (integerdivider / 100) << 4;\r
+\r
+ /* Determine the fractional part */\r
+ fractionaldivider = integerdivider - (100 * (tmpreg >> 4));\r
+\r
+ /* Implement the fractional part in the register */\r
+ if ((USARTx->CR1 & CR1_OVER8_Set) != 0)\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);\r
+ }\r
+ else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */\r
+ {\r
+ tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);\r
+ }\r
+ \r
+ /* Write to USART BRR */\r
+ USARTx->BRR = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_InitStruct member with its default value.\r
+ * @param USART_InitStruct: pointer to a USART_InitTypeDef structure\r
+ * which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)\r
+{\r
+ /* USART_InitStruct members default value */\r
+ USART_InitStruct->USART_BaudRate = 9600;\r
+ USART_InitStruct->USART_WordLength = USART_WordLength_8b;\r
+ USART_InitStruct->USART_StopBits = USART_StopBits_1;\r
+ USART_InitStruct->USART_Parity = USART_Parity_No ;\r
+ USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;\r
+ USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the USARTx peripheral Clock according to the \r
+ * specified parameters in the USART_ClockInitStruct .\r
+ * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure that contains the configuration information for the specified \r
+ * USART peripheral. \r
+ * @note The Smart Card mode is not available for UART4 and UART5.\r
+ * @retval None\r
+ */\r
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ uint32_t tmpreg = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));\r
+ assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));\r
+ assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));\r
+ assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));\r
+ \r
+/*---------------------------- USART CR2 Configuration -----------------------*/\r
+ tmpreg = USARTx->CR2;\r
+ /* Clear CLKEN, CPOL, CPHA and LBCL bits */\r
+ tmpreg &= CR2_CLOCK_CLEAR_Mask;\r
+ /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/\r
+ /* Set CLKEN bit according to USART_Clock value */\r
+ /* Set CPOL bit according to USART_CPOL value */\r
+ /* Set CPHA bit according to USART_CPHA value */\r
+ /* Set LBCL bit according to USART_LastBit value */\r
+ tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | \r
+ USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;\r
+ /* Write to USART CR2 */\r
+ USARTx->CR2 = (uint16_t)tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Fills each USART_ClockInitStruct member with its default value.\r
+ * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef\r
+ * structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)\r
+{\r
+ /* USART_ClockInitStruct members default value */\r
+ USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;\r
+ USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;\r
+ USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;\r
+ USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART peripheral.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USARTx peripheral.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected USART by setting the UE bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_UE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected USART by clearing the UE bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_UE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified USART interrupts.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)\r
+ * @param NewState: new state of the specified USARTx interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)\r
+{\r
+ uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;\r
+ uint32_t usartxbase = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CONFIG_IT(USART_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ /* The CTS interrupt is not available for UART4 and UART5 */\r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ usartxbase = (uint32_t)USARTx;\r
+\r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+\r
+ /* Get the interrupt position */\r
+ itpos = USART_IT & IT_Mask;\r
+ itmask = (((uint32_t)0x01) << itpos);\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ usartxbase += 0x0C;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ usartxbase += 0x10;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ usartxbase += 0x14; \r
+ }\r
+ if (NewState != DISABLE)\r
+ {\r
+ *(__IO uint32_t*)usartxbase |= itmask;\r
+ }\r
+ else\r
+ {\r
+ *(__IO uint32_t*)usartxbase &= ~itmask;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s DMA interface.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_DMAReq: specifies the DMA request.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_DMAReq_Tx: USART DMA transmit request\r
+ * @arg USART_DMAReq_Rx: USART DMA receive request\r
+ * @param NewState: new state of the DMA Request sources.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note The DMA mode is not available for UART5 except in the STM32\r
+ * High density value line devices(STM32F10X_HD_VL). \r
+ * @retval None\r
+ */\r
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DMAREQ(USART_DMAReq)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transfer for selected requests by setting the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 |= USART_DMAReq;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transfer for selected requests by clearing the DMAT and/or\r
+ DMAR bits in the USART CR3 register */\r
+ USARTx->CR3 &= (uint16_t)~USART_DMAReq;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the address of the USART node.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_Address: Indicates the address of the USART node.\r
+ * @retval None\r
+ */\r
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_ADDRESS(USART_Address)); \r
+ \r
+ /* Clear the USART address */\r
+ USARTx->CR2 &= CR2_Address_Mask;\r
+ /* Set the USART address node */\r
+ USARTx->CR2 |= USART_Address;\r
+}\r
+\r
+/**\r
+ * @brief Selects the USART WakeUp method.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_WakeUp: specifies the USART wakeup method.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection\r
+ * @arg USART_WakeUp_AddressMark: WakeUp by an address mark\r
+ * @retval None\r
+ */\r
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_WAKEUP(USART_WakeUp));\r
+ \r
+ USARTx->CR1 &= CR1_WAKE_Mask;\r
+ USARTx->CR1 |= USART_WakeUp;\r
+}\r
+\r
+/**\r
+ * @brief Determines if the USART is in mute mode or not.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART mute mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the USART mute mode by setting the RWU bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_RWU_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_RWU_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Sets the USART LIN Break detection length.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_LINBreakDetectLength: specifies the LIN break detection length.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_LINBreakDetectLength_10b: 10-bit break detection\r
+ * @arg USART_LINBreakDetectLength_11b: 11-bit break detection\r
+ * @retval None\r
+ */\r
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));\r
+ \r
+ USARTx->CR2 &= CR2_LBDL_Mask;\r
+ USARTx->CR2 |= USART_LINBreakDetectLength; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s LIN mode.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART LIN mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\r
+ USARTx->CR2 |= CR2_LINEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */\r
+ USARTx->CR2 &= CR2_LINEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Transmits single data through the USARTx peripheral.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param Data: the data to transmit.\r
+ * @retval None\r
+ */\r
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_DATA(Data)); \r
+ \r
+ /* Transmit Data */\r
+ USARTx->DR = (Data & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Returns the most recent received data by the USARTx peripheral.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval The received data.\r
+ */\r
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Receive Data */\r
+ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);\r
+}\r
+\r
+/**\r
+ * @brief Transmits break characters.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @retval None\r
+ */\r
+void USART_SendBreak(USART_TypeDef* USARTx)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Send break characters */\r
+ USARTx->CR1 |= CR1_SBK_Set;\r
+}\r
+\r
+/**\r
+ * @brief Sets the specified USART guard time.\r
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
+ * @param USART_GuardTime: specifies the guard time.\r
+ * @note The guard time bits are not available for UART4 and UART5. \r
+ * @retval None\r
+ */\r
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART Guard time */\r
+ USARTx->GTPR &= GTPR_LSB_Mask;\r
+ /* Set the USART guard time */\r
+ USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);\r
+}\r
+\r
+/**\r
+ * @brief Sets the system clock prescaler.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_Prescaler: specifies the prescaler clock. \r
+ * @note The function is used for IrDA mode with UART4 and UART5.\r
+ * @retval None\r
+ */\r
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ \r
+ /* Clear the USART prescaler */\r
+ USARTx->GTPR &= GTPR_MSB_Mask;\r
+ /* Set the USART prescaler */\r
+ USARTx->GTPR |= USART_Prescaler;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Smart Card mode.\r
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral.\r
+ * @param NewState: new state of the Smart Card mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @note The Smart Card mode is not available for UART4 and UART5. \r
+ * @retval None\r
+ */\r
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the SC mode by setting the SCEN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_SCEN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the SC mode by clearing the SCEN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_SCEN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables NACK transmission.\r
+ * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. \r
+ * @param NewState: new state of the NACK transmission.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @note The Smart Card mode is not available for UART4 and UART5.\r
+ * @retval None\r
+ */\r
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_123_PERIPH(USARTx)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the NACK transmission by setting the NACK bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_NACK_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_NACK_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s Half Duplex communication.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART Communication.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_HDSEL_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_HDSEL_Reset;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * @brief Enables or disables the USART's 8x oversampling mode.\r
+ * @param USARTx: Select the USART or the UART peripheral.\r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART one bit sampling methode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @note\r
+ * This function has to be called before calling USART_Init()\r
+ * function in order to have correct baudrate Divider value. \r
+ * @retval None\r
+ */\r
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 |= CR1_OVER8_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */\r
+ USARTx->CR1 &= CR1_OVER8_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART's one bit sampling methode.\r
+ * @param USARTx: Select the USART or the UART peripheral.\r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the USART one bit sampling methode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_ONEBITE_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_ONEBITE_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IrDAMode: specifies the IrDA mode.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IrDAMode_LowPower\r
+ * @arg USART_IrDAMode_Normal\r
+ * @retval None\r
+ */\r
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));\r
+ \r
+ USARTx->CR3 &= CR3_IRLP_Mask;\r
+ USARTx->CR3 |= USART_IrDAMode;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the USART\92s IrDA interface.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param NewState: new state of the IrDA mode.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the IrDA mode by setting the IREN bit in the CR3 register */\r
+ USARTx->CR3 |= CR3_IREN_Set;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */\r
+ USARTx->CR3 &= CR3_IREN_Reset;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART flag is set or not.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag\r
+ * @arg USART_FLAG_TXE: Transmit data register empty flag\r
+ * @arg USART_FLAG_TC: Transmission Complete flag\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag\r
+ * @arg USART_FLAG_IDLE: Idle Line detection flag\r
+ * @arg USART_FLAG_ORE: OverRun Error flag\r
+ * @arg USART_FLAG_NE: Noise Error flag\r
+ * @arg USART_FLAG_FE: Framing Error flag\r
+ * @arg USART_FLAG_PE: Parity Error flag\r
+ * @retval The new state of USART_FLAG (SET or RESET).\r
+ */\r
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_FLAG(USART_FLAG));\r
+ /* The CTS flag is not available for UART4 and UART5 */\r
+ if (USART_FLAG == USART_FLAG_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx's pending flags.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).\r
+ * @arg USART_FLAG_LBD: LIN Break detection flag.\r
+ * @arg USART_FLAG_TC: Transmission Complete flag.\r
+ * @arg USART_FLAG_RXNE: Receive data register not empty flag.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) flags are cleared by software \r
+ * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) \r
+ * followed by a read operation to USART_DR register (USART_ReceiveData()).\r
+ * - RXNE flag can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC flag can be also cleared by software sequence: a read operation to \r
+ * USART_SR register (USART_GetFlagStatus()) followed by a write operation\r
+ * to USART_DR register (USART_SendData()).\r
+ * - TXE flag is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));\r
+ /* The CTS flag is not available for UART4 and UART5 */\r
+ if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ USARTx->SR = (uint16_t)~USART_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified USART interrupt has occurred or not.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the USART interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TXE: Tansmit Data Register empty interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt\r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt\r
+ * @arg USART_IT_IDLE: Idle line detection interrupt\r
+ * @arg USART_IT_ORE: OverRun Error interrupt\r
+ * @arg USART_IT_NE: Noise Error interrupt\r
+ * @arg USART_IT_FE: Framing Error interrupt\r
+ * @arg USART_IT_PE: Parity Error interrupt\r
+ * @retval The new state of USART_IT (SET or RESET).\r
+ */\r
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_GET_IT(USART_IT));\r
+ /* The CTS interrupt is not available for UART4 and UART5 */ \r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ /* Get the USART register index */\r
+ usartreg = (((uint8_t)USART_IT) >> 0x05);\r
+ /* Get the interrupt position */\r
+ itmask = USART_IT & IT_Mask;\r
+ itmask = (uint32_t)0x01 << itmask;\r
+ \r
+ if (usartreg == 0x01) /* The IT is in CR1 register */\r
+ {\r
+ itmask &= USARTx->CR1;\r
+ }\r
+ else if (usartreg == 0x02) /* The IT is in CR2 register */\r
+ {\r
+ itmask &= USARTx->CR2;\r
+ }\r
+ else /* The IT is in CR3 register */\r
+ {\r
+ itmask &= USARTx->CR3;\r
+ }\r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ bitpos = (uint32_t)0x01 << bitpos;\r
+ bitpos &= USARTx->SR;\r
+ if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ \r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Clears the USARTx\92s interrupt pending bits.\r
+ * @param USARTx: Select the USART or the UART peripheral. \r
+ * This parameter can be one of the following values:\r
+ * USART1, USART2, USART3, UART4 or UART5.\r
+ * @param USART_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be one of the following values:\r
+ * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\r
+ * @arg USART_IT_LBD: LIN Break detection interrupt\r
+ * @arg USART_IT_TC: Transmission complete interrupt. \r
+ * @arg USART_IT_RXNE: Receive Data register not empty interrupt.\r
+ * \r
+ * @note\r
+ * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun \r
+ * error) and IDLE (Idle line detected) pending bits are cleared by \r
+ * software sequence: a read operation to USART_SR register \r
+ * (USART_GetITStatus()) followed by a read operation to USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - RXNE pending bit can be also cleared by a read to the USART_DR register \r
+ * (USART_ReceiveData()).\r
+ * - TC pending bit can be also cleared by software sequence: a read \r
+ * operation to USART_SR register (USART_GetITStatus()) followed by a write \r
+ * operation to USART_DR register (USART_SendData()).\r
+ * - TXE pending bit is cleared only by a write to the USART_DR register \r
+ * (USART_SendData()).\r
+ * @retval None\r
+ */\r
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)\r
+{\r
+ uint16_t bitpos = 0x00, itmask = 0x00;\r
+ /* Check the parameters */\r
+ assert_param(IS_USART_ALL_PERIPH(USARTx));\r
+ assert_param(IS_USART_CLEAR_IT(USART_IT));\r
+ /* The CTS interrupt is not available for UART4 and UART5 */\r
+ if (USART_IT == USART_IT_CTS)\r
+ {\r
+ assert_param(IS_USART_123_PERIPH(USARTx));\r
+ } \r
+ \r
+ bitpos = USART_IT >> 0x08;\r
+ itmask = ((uint16_t)0x01 << (uint16_t)bitpos);\r
+ USARTx->SR = (uint16_t)~itmask;\r
+}\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f10x_wwdg.c\r
+ * @author MCD Application Team\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
+ * @brief This file provides all the WWDG firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x_wwdg.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32F10x_StdPeriph_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG \r
+ * @brief WWDG driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup WWDG_Private_TypesDefinitions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Defines\r
+ * @{\r
+ */\r
+\r
+/* ----------- WWDG registers bit address in the alias region ----------- */\r
+#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)\r
+\r
+/* Alias word address of EWI bit */\r
+#define CFR_OFFSET (WWDG_OFFSET + 0x04)\r
+#define EWI_BitNumber 0x09\r
+#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))\r
+\r
+/* --------------------- WWDG registers bit mask ------------------------ */\r
+\r
+/* CR register bit mask */\r
+#define CR_WDGA_Set ((uint32_t)0x00000080)\r
+\r
+/* CFR register bit mask */\r
+#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)\r
+#define CFR_W_Mask ((uint32_t)0xFFFFFF80)\r
+#define BIT_Mask ((uint8_t)0x7F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Variables\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_FunctionPrototypes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup WWDG_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the WWDG peripheral registers to their default reset values.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_DeInit(void)\r
+{\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);\r
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG Prescaler.\r
+ * @param WWDG_Prescaler: specifies the WWDG Prescaler.\r
+ * This parameter can be one of the following values:\r
+ * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1\r
+ * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2\r
+ * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4\r
+ * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8\r
+ * @retval None\r
+ */\r
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)\r
+{\r
+ uint32_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));\r
+ /* Clear WDGTB[1:0] bits */\r
+ tmpreg = WWDG->CFR & CFR_WDGTB_Mask;\r
+ /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */\r
+ tmpreg |= WWDG_Prescaler;\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG window value.\r
+ * @param WindowValue: specifies the window value to be compared to the downcounter.\r
+ * This parameter value must be lower than 0x80.\r
+ * @retval None\r
+ */\r
+void WWDG_SetWindowValue(uint8_t WindowValue)\r
+{\r
+ __IO uint32_t tmpreg = 0;\r
+\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));\r
+ /* Clear W[6:0] bits */\r
+\r
+ tmpreg = WWDG->CFR & CFR_W_Mask;\r
+\r
+ /* Set W[6:0] bits according to WindowValue value */\r
+ tmpreg |= WindowValue & (uint32_t) BIT_Mask;\r
+\r
+ /* Store the new value */\r
+ WWDG->CFR = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Enables the WWDG Early Wakeup interrupt(EWI).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_EnableIT(void)\r
+{\r
+ *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;\r
+}\r
+\r
+/**\r
+ * @brief Sets the WWDG counter value.\r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F.\r
+ * @retval None\r
+ */\r
+void WWDG_SetCounter(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ /* Write to T[6:0] bits to configure the counter value, no need to do\r
+ a read-modify-write; writing a 0 to WDGA bit does nothing */\r
+ WWDG->CR = Counter & BIT_Mask;\r
+}\r
+\r
+/**\r
+ * @brief Enables WWDG and load the counter value. \r
+ * @param Counter: specifies the watchdog counter value.\r
+ * This parameter must be a number between 0x40 and 0x7F.\r
+ * @retval None\r
+ */\r
+void WWDG_Enable(uint8_t Counter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_WWDG_COUNTER(Counter));\r
+ WWDG->CR = CR_WDGA_Set | Counter;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the Early Wakeup interrupt flag is set or not.\r
+ * @param None\r
+ * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)\r
+ */\r
+FlagStatus WWDG_GetFlagStatus(void)\r
+{\r
+ return (FlagStatus)(WWDG->SR);\r
+}\r
+\r
+/**\r
+ * @brief Clears Early Wakeup interrupt flag.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void WWDG_ClearFlag(void)\r
+{\r
+ WWDG->SR = (uint32_t)RESET;\r
+}\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_eth.h\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 11/20/2009\r
+ * @brief This file contains all the functions prototypes for the Ethernet\r
+ * firmware library.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Define to prevent recursive inclusion -------------------------------------*/\r
+#ifndef __STM32_ETH_H\r
+#define __STM32_ETH_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32f10x.h"\r
+\r
+/** @addtogroup STM32_ETH_Driver\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Types\r
+ * @{\r
+ */\r
+\r
+/** \r
+ * @brief ETH MAC Init structure definition\r
+ * @note The user should not configure all the ETH_InitTypeDef structure's fields. \r
+ * By calling the ETH_StructInit function the structure\92s fields are set to their default values.\r
+ * Only the parameters that will be set to a non-default value should be configured. \r
+ */ \r
+typedef struct {\r
+/** \r
+ * @brief / * MAC \r
+ */ \r
+ uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY\r
+ The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)\r
+ and the mode (half/full-duplex).\r
+ This parameter can be a value of @ref ETH_AutoNegotiation */\r
+\r
+ uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be received.\r
+ When disabled, the MAC can receive up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_watchdog */ \r
+\r
+ uint32_t ETH_Jabber; /*!< Selects or not Jabber timer\r
+ When enabled, the MAC allows no more then 2048 bytes to be sent.\r
+ When disabled, the MAC can send up to 16384 bytes.\r
+ This parameter can be a value of @ref ETH_Jabber */\r
+\r
+ uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission\r
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */ \r
+\r
+ uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense\r
+ This parameter can be a value of @ref ETH_Carrier_Sense */\r
+\r
+ uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps\r
+ This parameter can be a value of @ref ETH_Speed */\r
+\r
+ uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn\r
+ ReceiveOwn allows the reception of frames when the TX_EN signal is asserted\r
+ in Half-Duplex mode\r
+ This parameter can be a value of @ref ETH_Receive_Own */ \r
+\r
+ uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode\r
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */ \r
+\r
+ uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode\r
+ This parameter can be a value of @ref ETH_Duplex_Mode */ \r
+\r
+ uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.\r
+ This parameter can be a value of @ref ETH_Checksum_Offload */ \r
+\r
+ uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,\r
+ when a colision occurs (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Retry_Transmission */\r
+\r
+ uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping\r
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ \r
+\r
+ uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value\r
+ This parameter can be a value of @ref ETH_Back_Off_Limit */\r
+\r
+ uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Deferral_Check */ \r
+\r
+ uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No fitering)\r
+ This parameter can be a value of @ref ETH_Receive_All */ \r
+\r
+ uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode \r
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */ \r
+\r
+ uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) \r
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */ \r
+\r
+ uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames\r
+ This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */\r
+\r
+ uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames\r
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */ \r
+\r
+ uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode\r
+ This parameter can be a value of @ref ETH_Promiscuous_Mode */\r
+\r
+ uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter\r
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ \r
+\r
+ uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter\r
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ \r
+\r
+ uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ \r
+\r
+ uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ \r
+\r
+ uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the\r
+ transmit control frame */\r
+\r
+ uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames\r
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ \r
+\r
+ uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for\r
+ automatic retransmission of PAUSE Frame\r
+ This parameter can be a value of @ref ETH_Pause_Low_Threshold */\r
+ \r
+ uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0\r
+ unicast address and unique multicast address)\r
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ \r
+\r
+ uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and\r
+ disable its transmitter for a specified time (Pause Time)\r
+ This parameter can be a value of @ref ETH_Receive_Flow_Control */\r
+\r
+ uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)\r
+ or the MAC back-pressure operation (Half-Duplex mode)\r
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */ \r
+\r
+ uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for\r
+ comparison and filtering\r
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ \r
+\r
+ uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */\r
+\r
+/** \r
+ * @brief / * DMA \r
+ */ \r
+\r
+ uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames\r
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ \r
+\r
+ uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode\r
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */ \r
+\r
+ uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames\r
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */ \r
+\r
+ uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode\r
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */ \r
+\r
+ uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control\r
+ This parameter can be a value of @ref ETH_Transmit_Threshold_Control */\r
+\r
+ uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames\r
+ This parameter can be a value of @ref ETH_Forward_Error_Frames */\r
+\r
+ uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error\r
+ and length less than 64 bytes) including pad-bytes and CRC)\r
+ This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */\r
+\r
+ uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO\r
+ This parameter can be a value of @ref ETH_Receive_Threshold_Control */\r
+\r
+ uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second\r
+ frame of Transmit data even before obtaining the status for the first frame.\r
+ This parameter can be a value of @ref ETH_Second_Frame_Operate */\r
+\r
+ uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats\r
+ This parameter can be a value of @ref ETH_Address_Aligned_Beats */\r
+\r
+ uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers\r
+ This parameter can be a value of @ref ETH_Fixed_Burst */\r
+ \r
+ uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction\r
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ \r
+\r
+ uint32_t ETH_TxDMABurstLength; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction\r
+ This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ \r
+\r
+ uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ \r
+\r
+ uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration\r
+ This parameter can be a value of @ref ETH_DMA_Arbitration */ \r
+}ETH_InitTypeDef;\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief DMA descriptors types\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/** \r
+ * @brief ETH DMA Desciptors data structure definition\r
+ */ \r
+typedef struct {\r
+ uint32_t Status; /*!< Status */\r
+ uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */\r
+ uint32_t Buffer1Addr; /*!< Buffer1 address pointer */\r
+ uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */\r
+} ETH_DMADESCTypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Constants\r
+ * @{\r
+ */ \r
+\r
+/**\r
+ * @brief Uncomment the line below if you want to use user defined Delay function\r
+ * (for precise timing), otherwise default _eth_delay_ function defined within\r
+ * this driver is used (less precise timing). \r
+ */\r
+/* #define USE_Delay */\r
+\r
+#ifdef USE_Delay\r
+#include "main.h" \r
+ #define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */\r
+#else\r
+ #define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */\r
+#endif \r
+ \r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief ETH Frames defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/** @defgroup ENET_Buffers_setting \r
+ * @{\r
+ */ \r
+#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */\r
+#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */\r
+#define ETH_CRC 4 /*!< Ethernet CRC */\r
+#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ \r
+#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */\r
+#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */\r
+#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */\r
+#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ \r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet DMA descriptors registers bits definition\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/**\r
+@code \r
+ DMA Tx Desciptor\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES2 | Buffer1 Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+ TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |\r
+ -----------------------------------------------------------------------------------------------\r
+@endcode\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of TDES0 register: DMA Tx descriptor status register\r
+ */ \r
+#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */\r
+#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */\r
+#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */\r
+#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */\r
+#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */\r
+#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */\r
+#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */\r
+#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ \r
+#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ \r
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ \r
+#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ \r
+#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */\r
+#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */\r
+#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */\r
+#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */\r
+#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */\r
+#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */\r
+#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */\r
+#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */\r
+#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */\r
+#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */\r
+#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */\r
+#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */\r
+#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */\r
+#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */\r
+#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */\r
+#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */\r
+#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */\r
+\r
+/** \r
+ * @brief Bit definition of TDES1 register\r
+ */ \r
+#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */\r
+#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of TDES2 register\r
+ */ \r
+#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of TDES3 register\r
+ */ \r
+#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup DMA_Rx_descriptor \r
+ * @{\r
+ */\r
+\r
+/**\r
+@code \r
+ DMA Rx Desciptor\r
+ --------------------------------------------------------------------------------------------------------------------\r
+ RDES0 | OWN(31) | Status [30:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES2 | Buffer1 Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+ RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |\r
+ ---------------------------------------------------------------------------------------------------------------------\r
+@endcode\r
+*/\r
+\r
+/** \r
+ * @brief Bit definition of RDES0 register: DMA Rx descriptor status register\r
+ */ \r
+#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */\r
+#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */\r
+#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */\r
+#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */\r
+#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */\r
+#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */\r
+#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */\r
+#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */\r
+#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */\r
+#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */\r
+#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ \r
+#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ \r
+#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */\r
+#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */\r
+#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */\r
+#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */\r
+#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */\r
+#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */\r
+#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */\r
+\r
+/** \r
+ * @brief Bit definition of RDES1 register\r
+ */ \r
+#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */\r
+#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */\r
+#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */\r
+#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */\r
+#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */\r
+\r
+/** \r
+ * @brief Bit definition of RDES2 register \r
+ */ \r
+#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */\r
+\r
+/** \r
+ * @brief Bit definition of RDES3 register \r
+ */ \r
+#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Desciption of common PHY registers\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Read_write_Timeouts \r
+ * @{\r
+ */ \r
+#define PHY_READ_TO ((uint32_t)0x0004FFFF)\r
+#define PHY_WRITE_TO ((uint32_t)0x0004FFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Reset_Delay \r
+ * @{\r
+ */ \r
+#define PHY_ResetDelay ((uint32_t)0x000FFFFF) \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Config_Delay \r
+ * @{\r
+ */ \r
+#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_Register_address \r
+ * @{\r
+ */ \r
+#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */\r
+#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_basic_Control_register \r
+ * @{\r
+ */ \r
+#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */\r
+#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */\r
+#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */\r
+#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */\r
+#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */\r
+#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */\r
+#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */\r
+#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */\r
+#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */\r
+#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_basic_status_register \r
+ * @{\r
+ */ \r
+#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */\r
+#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */\r
+#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup PHY_status_register \r
+ * @{\r
+ */ \r
+/* The PHY status register value change from a PHY to another so the user have \r
+ to update this value depending on the used external PHY */\r
+/** \r
+ * @brief For LAN8700 \r
+ */ \r
+//#define PHY_SR 31 /*!< Tranceiver Status Register */\r
+/** \r
+ * @brief For DP83848 \r
+ */ \r
+#define PHY_SR 16 /*!< Tranceiver Status Register */\r
+\r
+/* The Speed and Duplex mask values change from a PHY to another so the user have to update\r
+ this value depending on the used external PHY */\r
+/** \r
+ * @brief For LAN8700 \r
+ */ \r
+//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */\r
+//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */\r
+\r
+/** \r
+ * @brief For DP83848 \r
+ */ \r
+#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */\r
+#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */\r
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)\r
+#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \\r
+ ((REG) == PHY_BSR) || \\r
+ ((REG) == PHY_SR))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief MAC defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/** @defgroup ETH_AutoNegotiation \r
+ * @{\r
+ */ \r
+#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001)\r
+#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \\r
+ ((CMD) == ETH_AutoNegotiation_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_watchdog \r
+ * @{\r
+ */ \r
+#define ETH_Watchdog_Enable ((uint32_t)0x00000000)\r
+#define ETH_Watchdog_Disable ((uint32_t)0x00800000)\r
+#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \\r
+ ((CMD) == ETH_Watchdog_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Jabber \r
+ * @{\r
+ */ \r
+#define ETH_Jabber_Enable ((uint32_t)0x00000000)\r
+#define ETH_Jabber_Disable ((uint32_t)0x00400000)\r
+#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \\r
+ ((CMD) == ETH_Jabber_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Inter_Frame_Gap \r
+ * @{\r
+ */ \r
+#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */\r
+#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */\r
+#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */\r
+#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */\r
+#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */\r
+#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */\r
+#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */\r
+#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */\r
+#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_88Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_80Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_72Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_64Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_56Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_48Bit) || \\r
+ ((GAP) == ETH_InterFrameGap_40Bit))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Carrier_Sense \r
+ * @{\r
+ */ \r
+#define ETH_CarrierSense_Enable ((uint32_t)0x00000000)\r
+#define ETH_CarrierSense_Disable ((uint32_t)0x00010000)\r
+#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \\r
+ ((CMD) == ETH_CarrierSense_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Speed \r
+ * @{\r
+ */ \r
+#define ETH_Speed_10M ((uint32_t)0x00000000)\r
+#define ETH_Speed_100M ((uint32_t)0x00004000)\r
+#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \\r
+ ((SPEED) == ETH_Speed_100M))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Own \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000)\r
+#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000)\r
+#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \\r
+ ((CMD) == ETH_ReceiveOwn_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Loop_Back_Mode \r
+ * @{\r
+ */ \r
+#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000)\r
+#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \\r
+ ((CMD) == ETH_LoopbackMode_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Duplex_Mode \r
+ * @{\r
+ */ \r
+#define ETH_Mode_FullDuplex ((uint32_t)0x00000800)\r
+#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000)\r
+#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \\r
+ ((MODE) == ETH_Mode_HalfDuplex))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Checksum_Offload \r
+ * @{\r
+ */ \r
+#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400)\r
+#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \\r
+ ((CMD) == ETH_ChecksumOffload_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Retry_Transmission \r
+ * @{\r
+ */ \r
+#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000)\r
+#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200)\r
+#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \\r
+ ((CMD) == ETH_RetryTransmission_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Automatic_Pad_CRC_Strip \r
+ * @{\r
+ */ \r
+#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080)\r
+#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \\r
+ ((CMD) == ETH_AutomaticPadCRCStrip_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Back_Off_Limit \r
+ * @{\r
+ */ \r
+#define ETH_BackOffLimit_10 ((uint32_t)0x00000000)\r
+#define ETH_BackOffLimit_8 ((uint32_t)0x00000020)\r
+#define ETH_BackOffLimit_4 ((uint32_t)0x00000040)\r
+#define ETH_BackOffLimit_1 ((uint32_t)0x00000060)\r
+#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \\r
+ ((LIMIT) == ETH_BackOffLimit_8) || \\r
+ ((LIMIT) == ETH_BackOffLimit_4) || \\r
+ ((LIMIT) == ETH_BackOffLimit_1))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Deferral_Check \r
+ * @{\r
+ */\r
+#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010)\r
+#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \\r
+ ((CMD) == ETH_DeferralCheck_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_All \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000)\r
+#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \\r
+ ((CMD) == ETH_ReceiveAll_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Source_Addr_Filter \r
+ * @{\r
+ */ \r
+#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200)\r
+#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300)\r
+#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \\r
+ ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \\r
+ ((CMD) == ETH_SourceAddrFilter_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pass_Control_Frames \r
+ * @{\r
+ */ \r
+#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */\r
+#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */\r
+#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ \r
+#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \\r
+ ((PASS) == ETH_PassControlFrames_ForwardAll) || \\r
+ ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Broadcast_Frames_Reception \r
+ * @{\r
+ */ \r
+#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000)\r
+#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020)\r
+#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \\r
+ ((CMD) == ETH_BroadcastFramesReception_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Destination_Addr_Filter \r
+ * @{\r
+ */ \r
+#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000)\r
+#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008)\r
+#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \\r
+ ((FILTER) == ETH_DestinationAddrFilter_Inverse))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Promiscuous_Mode \r
+ * @{\r
+ */ \r
+#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001)\r
+#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \\r
+ ((CMD) == ETH_PromiscuousMode_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Multicast_Frames_Filter \r
+ * @{\r
+ */ \r
+#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404)\r
+#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004)\r
+#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000)\r
+#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010)\r
+#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \\r
+ ((FILTER) == ETH_MulticastFramesFilter_None))\r
+ \r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Frames_Filter \r
+ * @{\r
+ */ \r
+#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402)\r
+#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002)\r
+#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000)\r
+#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \\r
+ ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \\r
+ ((FILTER) == ETH_UnicastFramesFilter_Perfect))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Time \r
+ * @{\r
+ */ \r
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Zero_Quanta_Pause \r
+ * @{\r
+ */ \r
+#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000)\r
+#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080)\r
+#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \\r
+ ((CMD) == ETH_ZeroQuantaPause_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Pause_Low_Threshold \r
+ * @{\r
+ */ \r
+#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */\r
+#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */\r
+#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */\r
+#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */\r
+#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \\r
+ ((THRESHOLD) == ETH_PauseLowThreshold_Minus256))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Unicast_Pause_Frame_Detect \r
+ * @{\r
+ */ \r
+#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008)\r
+#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \\r
+ ((CMD) == ETH_UnicastPauseFrameDetect_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Flow_Control \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004)\r
+#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \\r
+ ((CMD) == ETH_ReceiveFlowControl_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Flow_Control \r
+ * @{\r
+ */ \r
+#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002)\r
+#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \\r
+ ((CMD) == ETH_TransmitFlowControl_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_VLAN_Tag_Comparison \r
+ * @{\r
+ */ \r
+#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000)\r
+#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000)\r
+#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \\r
+ ((COMPARISON) == ETH_VLANTagComparison_16Bit))\r
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Flags \r
+ * @{\r
+ */ \r
+#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */\r
+#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */\r
+#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */\r
+#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */\r
+#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */\r
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \\r
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \\r
+ ((FLAG) == ETH_MAC_FLAG_PMT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */\r
+#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */\r
+#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */\r
+#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */\r
+#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */\r
+#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \\r
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \\r
+ ((IT) == ETH_MAC_IT_PMT))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses \r
+ * @{\r
+ */ \r
+#define ETH_MAC_Address0 ((uint32_t)0x00000000)\r
+#define ETH_MAC_Address1 ((uint32_t)0x00000008)\r
+#define ETH_MAC_Address2 ((uint32_t)0x00000010)\r
+#define ETH_MAC_Address3 ((uint32_t)0x00000018)\r
+#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \\r
+ ((ADDRESS) == ETH_MAC_Address1) || \\r
+ ((ADDRESS) == ETH_MAC_Address2) || \\r
+ ((ADDRESS) == ETH_MAC_Address3))\r
+#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \\r
+ ((ADDRESS) == ETH_MAC_Address2) || \\r
+ ((ADDRESS) == ETH_MAC_Address3))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames \r
+ * @{\r
+ */ \r
+#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000)\r
+#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008)\r
+#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \\r
+ ((FILTER) == ETH_MAC_AddressFilter_DA))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes \r
+ * @{\r
+ */ \r
+#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */\r
+#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */\r
+#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */\r
+#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */\r
+#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */\r
+#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */\r
+#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte5) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte4) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte3) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte2) || \\r
+ ((MASK) == ETH_MAC_AddressMask_Byte1))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet DMA Desciptors defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_flags\r
+ * @{\r
+ */ \r
+#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \\r
+ ((FLAG) == ETH_DMATxDesc_IC) || \\r
+ ((FLAG) == ETH_DMATxDesc_LS) || \\r
+ ((FLAG) == ETH_DMATxDesc_FS) || \\r
+ ((FLAG) == ETH_DMATxDesc_DC) || \\r
+ ((FLAG) == ETH_DMATxDesc_DP) || \\r
+ ((FLAG) == ETH_DMATxDesc_TTSE) || \\r
+ ((FLAG) == ETH_DMATxDesc_TER) || \\r
+ ((FLAG) == ETH_DMATxDesc_TCH) || \\r
+ ((FLAG) == ETH_DMATxDesc_TTSS) || \\r
+ ((FLAG) == ETH_DMATxDesc_IHE) || \\r
+ ((FLAG) == ETH_DMATxDesc_ES) || \\r
+ ((FLAG) == ETH_DMATxDesc_JT) || \\r
+ ((FLAG) == ETH_DMATxDesc_FF) || \\r
+ ((FLAG) == ETH_DMATxDesc_PCE) || \\r
+ ((FLAG) == ETH_DMATxDesc_LCA) || \\r
+ ((FLAG) == ETH_DMATxDesc_NC) || \\r
+ ((FLAG) == ETH_DMATxDesc_LCO) || \\r
+ ((FLAG) == ETH_DMATxDesc_EC) || \\r
+ ((FLAG) == ETH_DMATxDesc_VF) || \\r
+ ((FLAG) == ETH_DMATxDesc_CC) || \\r
+ ((FLAG) == ETH_DMATxDesc_ED) || \\r
+ ((FLAG) == ETH_DMATxDesc_UF) || \\r
+ ((FLAG) == ETH_DMATxDesc_DB))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_segment \r
+ * @{\r
+ */ \r
+#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */\r
+#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */\r
+#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \\r
+ ((SEGMENT) == ETH_DMATxDesc_FirstSegment))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control\r
+ * @{\r
+ */ \r
+#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */\r
+#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */\r
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */\r
+#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */\r
+#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \\r
+ ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull))\r
+/** \r
+ * @brief ETH DMA Tx Desciptor buffer size\r
+ */ \r
+#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_flags\r
+ * @{\r
+ */ \r
+#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \\r
+ ((FLAG) == ETH_DMARxDesc_AFM) || \\r
+ ((FLAG) == ETH_DMARxDesc_ES) || \\r
+ ((FLAG) == ETH_DMARxDesc_DE) || \\r
+ ((FLAG) == ETH_DMARxDesc_SAF) || \\r
+ ((FLAG) == ETH_DMARxDesc_LE) || \\r
+ ((FLAG) == ETH_DMARxDesc_OE) || \\r
+ ((FLAG) == ETH_DMARxDesc_VLAN) || \\r
+ ((FLAG) == ETH_DMARxDesc_FS) || \\r
+ ((FLAG) == ETH_DMARxDesc_LS) || \\r
+ ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \\r
+ ((FLAG) == ETH_DMARxDesc_LC) || \\r
+ ((FLAG) == ETH_DMARxDesc_FT) || \\r
+ ((FLAG) == ETH_DMARxDesc_RWT) || \\r
+ ((FLAG) == ETH_DMARxDesc_RE) || \\r
+ ((FLAG) == ETH_DMARxDesc_DBE) || \\r
+ ((FLAG) == ETH_DMARxDesc_CE) || \\r
+ ((FLAG) == ETH_DMARxDesc_MAMPCE))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Rx_descriptor_buffers_ \r
+ * @{\r
+ */ \r
+#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */\r
+#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */\r
+#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \\r
+ ((BUFFER) == ETH_DMARxDesc_Buffer2))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet DMA defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame \r
+ * @{\r
+ */ \r
+#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000)\r
+#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000)\r
+#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \\r
+ ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Store_Forward \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000)\r
+#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \\r
+ ((CMD) == ETH_ReceiveStoreForward_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Flush_Received_Frame \r
+ * @{\r
+ */ \r
+#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000)\r
+#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000)\r
+#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \\r
+ ((CMD) == ETH_FlushReceivedFrame_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Store_Forward \r
+ * @{\r
+ */ \r
+#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000)\r
+#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \\r
+ ((CMD) == ETH_TransmitStoreForward_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Transmit_Threshold_Control \r
+ * @{\r
+ */ \r
+#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \\r
+ ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Error_Frames \r
+ * @{\r
+ */ \r
+#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080)\r
+#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000)\r
+#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \\r
+ ((CMD) == ETH_ForwardErrorFrames_Disable))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Forward_Undersized_Good_Frames \r
+ * @{\r
+ */ \r
+#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040)\r
+#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \\r
+ ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Receive_Threshold_Control \r
+ * @{\r
+ */ \r
+#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */\r
+#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */\r
+#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */\r
+#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \\r
+ ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Second_Frame_Operate \r
+ * @{\r
+ */ \r
+#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004)\r
+#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \\r
+ ((CMD) == ETH_SecondFrameOperate_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Address_Aligned_Beats \r
+ * @{\r
+ */ \r
+#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000)\r
+#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \\r
+ ((CMD) == ETH_AddressAlignedBeats_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Fixed_Burst \r
+ * @{\r
+ */ \r
+#define ETH_FixedBurst_Enable ((uint32_t)0x00010000)\r
+#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) \r
+#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \\r
+ ((CMD) == ETH_FixedBurst_Disable))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Rx_DMA_Burst_Length \r
+ * @{\r
+ */ \r
+#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */\r
+#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \\r
+ ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Tx_DMA_Burst_Length \r
+ * @{\r
+ */ \r
+#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \\r
+ ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat))\r
+/** \r
+ * @brief ETH DMA Desciptor SkipLength \r
+ */ \r
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Arbitration \r
+ * @{\r
+ */ \r
+#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000)\r
+#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000)\r
+#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002)\r
+#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \\r
+ ((RATIO) == ETH_DMAArbitration_RxPriorTx))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Flags \r
+ * @{\r
+ */ \r
+#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */\r
+#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */\r
+#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */\r
+#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */\r
+#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */\r
+#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */\r
+#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */\r
+#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */\r
+#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */\r
+#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */\r
+#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */\r
+#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */\r
+#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */\r
+#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */\r
+#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */\r
+#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */\r
+#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */\r
+\r
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) \r
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \\r
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \\r
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \\r
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \\r
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \\r
+ ((FLAG) == ETH_DMA_FLAG_T))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */\r
+#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */\r
+#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */\r
+#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */\r
+#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */\r
+#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */\r
+#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */\r
+#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */\r
+#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */\r
+#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */\r
+#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */\r
+#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */\r
+#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */\r
+#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */\r
+#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */\r
+#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */\r
+#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */\r
+#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */\r
+\r
+#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00))\r
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \\r
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \\r
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \\r
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \\r
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \\r
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \\r
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \\r
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \\r
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_transmit_process_state_ \r
+ * @{\r
+ */ \r
+#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */\r
+#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */\r
+#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */\r
+#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */\r
+#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */\r
+#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_DMA_receive_process_state_ \r
+ * @{\r
+ */ \r
+#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */\r
+#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */\r
+#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */\r
+#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */\r
+#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */\r
+#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_DMA_overflow_ \r
+ * @{\r
+ */ \r
+#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */\r
+#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */\r
+#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \\r
+ ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet PMT defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PMT_Flags \r
+ * @{\r
+ */ \r
+#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */\r
+#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */\r
+#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */\r
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \\r
+ ((FLAG) == ETH_PMT_FLAG_MPR))\r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet MMC defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Tx_Interrupts \r
+ * @{\r
+ */ \r
+#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Rx_Interrupts \r
+ * @{\r
+ */\r
+#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */\r
+#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \\r
+ ((IT) != 0x00))\r
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \\r
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \\r
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_MMC_Registers \r
+ * @{\r
+ */ \r
+#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */\r
+#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */\r
+#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */\r
+#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */\r
+#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ \r
+#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */\r
+#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ \r
+#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */\r
+#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */\r
+#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */\r
+#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */\r
+\r
+/** \r
+ * @brief ETH MMC registers \r
+ */ \r
+#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \\r
+ ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \\r
+ ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \\r
+ ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \\r
+ ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \\r
+ ((REG) == ETH_MMCRGUFCR)) \r
+\r
+/**--------------------------------------------------------------------------**/\r
+/** \r
+ * @brief Ethernet PTP defines\r
+ */ \r
+/**--------------------------------------------------------------------------**/\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_PTP_time_update_method \r
+ * @{\r
+ */ \r
+#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */\r
+#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */\r
+#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \\r
+ ((UPDATE) == ETH_PTP_CoarseUpdate))\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_PTP_Flags \r
+ * @{\r
+ */ \r
+#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */\r
+#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */\r
+#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */\r
+#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */\r
+#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSITE) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSSTU) || \\r
+ ((FLAG) == ETH_PTP_FLAG_TSSTI))\r
+/** \r
+ * @brief ETH PTP subsecond increment \r
+ */ \r
+#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF)\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_PTP_time_sign \r
+ * @{\r
+ */ \r
+#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */\r
+#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */\r
+#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \\r
+ ((SIGN) == ETH_PTP_NegativeTime))\r
+\r
+/** \r
+ * @brief ETH PTP time stamp low update \r
+ */ \r
+#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF)\r
+\r
+/** \r
+ * @brief ETH PTP registers \r
+ */ \r
+#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */\r
+#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */\r
+#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */\r
+#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */\r
+#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */\r
+#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */\r
+#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */\r
+#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */\r
+#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */\r
+#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \\r
+ ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \\r
+ ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \\r
+ ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \\r
+ ((REG) == ETH_PTPTTLR)) \r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Exported_Functions\r
+ * @{\r
+ */ \r
+void ETH_DeInit(void);\r
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress);\r
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);\r
+void ETH_SoftwareReset(void);\r
+FlagStatus ETH_GetSoftwareResetStatus(void);\r
+void ETH_Start(void);\r
+uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength);\r
+uint32_t ETH_HandleRxPkt(u8 *ppkt);\r
+uint32_t ETH_GetRxPktSize(void);\r
+void ETH_DropRxPkt(void);\r
+\r
+/** \r
+ * @brief PHY \r
+ */ \r
+u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg);\r
+uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue);\r
+uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState);\r
+\r
+/** \r
+ * @brief MAC \r
+ */ \r
+void ETH_MACTransmissionCmd(FunctionalState NewState);\r
+void ETH_MACReceptionCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetFlowControlBusyStatus(void);\r
+void ETH_InitiatePauseControlFrame(void); \r
+void ETH_BackPressureActivationCmd(FunctionalState NewState); \r
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); \r
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT);\r
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);\r
+void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr);\r
+void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr);\r
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);\r
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);\r
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);\r
+\r
+/** \r
+ * @brief DMA Tx/Rx descriptors \r
+ */ \r
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount);\r
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount);\r
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag);\r
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc);\r
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);\r
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);\r
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);\r
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);\r
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);\r
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount);\r
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount);\r
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag);\r
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);\r
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc);\r
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);\r
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer);\r
+\r
+/** \r
+ * @brief DMA\r
+ */ \r
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG);\r
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);\r
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT);\r
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);\r
+uint32_t ETH_GetTransmitProcessState(void);\r
+uint32_t ETH_GetReceiveProcessState(void);\r
+void ETH_FlushTransmitFIFO(void);\r
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void);\r
+void ETH_DMATransmissionCmd(FunctionalState NewState);\r
+void ETH_DMAReceptionCmd(FunctionalState NewState);\r
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);\r
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow);\r
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void);\r
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);\r
+uint32_t ETH_GetCurrentTxDescStartAddress(void);\r
+uint32_t ETH_GetCurrentRxDescStartAddress(void);\r
+uint32_t ETH_GetCurrentTxBufferAddress(void);\r
+uint32_t ETH_GetCurrentRxBufferAddress(void);\r
+void ETH_ResumeDMATransmission(void);\r
+void ETH_ResumeDMAReception(void);\r
+\r
+/** \r
+ * @brief PMT \r
+ */ \r
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void);\r
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);\r
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG);\r
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);\r
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState);\r
+void ETH_PowerDownCmd(FunctionalState NewState);\r
+\r
+/** \r
+ * @brief MMC \r
+ */ \r
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState);\r
+void ETH_MMCResetOnReadCmd(FunctionalState NewState);\r
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState);\r
+void ETH_MMCCountersReset(void);\r
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);\r
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT);\r
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg);\r
+\r
+/** \r
+ * @brief PTP \r
+ */ \r
+uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab);\r
+uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab);\r
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount);\r
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount);\r
+void ETH_EnablePTPTimeStampAddend(void);\r
+void ETH_EnablePTPTimeStampInterruptTrigger(void);\r
+void ETH_EnablePTPTimeStampUpdate(void);\r
+void ETH_InitializePTPTimeStamp(void);\r
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);\r
+void ETH_PTPTimeStampCmd(FunctionalState NewState);\r
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG);\r
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);\r
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);\r
+void ETH_SetPTPTimeStampAddend(uint32_t Value);\r
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);\r
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __STM32_ETH_H */\r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/**\r
+ * @}\r
+ */ \r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32_eth.c\r
+ * @author MCD Application Team\r
+ * @version V1.1.0\r
+ * @date 11/20/2009\r
+ * @brief This file provides all the ETH firmware functions.\r
+ ******************************************************************************\r
+ * @copy\r
+ *\r
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
+ *\r
+ * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ */ \r
+\r
+/* Includes ------------------------------------------------------------------*/\r
+#include "stm32_eth.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+/** @addtogroup STM32_ETH_Driver\r
+ * @brief ETH driver modules\r
+ * @{\r
+ */\r
+\r
+/** @defgroup ETH_Private_TypesDefinitions\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */ \r
+\r
+\r
+/** @defgroup ETH_Private_Defines\r
+ * @{\r
+ */ \r
+/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */\r
+ETH_DMADESCTypeDef *DMATxDescToSet;\r
+ETH_DMADESCTypeDef *DMARxDescToGet;\r
+ETH_DMADESCTypeDef *DMAPTPTxDescToSet;\r
+ETH_DMADESCTypeDef *DMAPTPRxDescToGet;\r
+\r
+/* ETHERNET MAC address offsets */\r
+#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */\r
+#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */\r
+\r
+/* ETHERNET MACMIIAR register Mask */\r
+#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) \r
+\r
+/* ETHERNET MACCR register Mask */\r
+#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) \r
+\r
+/* ETHERNET MACFCR register Mask */\r
+#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)\r
+\r
+/* ETHERNET DMAOMR register Mask */\r
+#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)\r
+\r
+/* ETHERNET Remote Wake-up frame register length */\r
+#define ETH_WAKEUP_REGISTER_LENGTH 8\r
+\r
+/* ETHERNET Missed frames counter Shift */\r
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17\r
+\r
+/* ETHERNET DMA Tx descriptors Collision Count Shift */\r
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3\r
+\r
+/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */\r
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16\r
+\r
+/* ETHERNET DMA Rx descriptors Frame Length Shift */\r
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16\r
+\r
+/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */\r
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16\r
+\r
+/* ETHERNET errors */\r
+#define ETH_ERROR ((uint32_t)0)\r
+#define ETH_SUCCESS ((uint32_t)1)\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_Macros\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_Variables\r
+ * @{\r
+ */ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_FunctionPrototypes\r
+ * @{\r
+ */ \r
+ \r
+#ifndef USE_Delay\r
+static void ETH_Delay(__IO uint32_t nCount);\r
+#endif /* USE_Delay*/\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @defgroup ETH_Private_Functions\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Deinitializes the ETHERNET peripheral registers to their default reset values.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void ETH_DeInit(void)\r
+{\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);\r
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);\r
+}\r
+\r
+/**\r
+ * @brief Initializes the ETHERNET peripheral according to the specified\r
+ * parameters in the ETH_InitStruct .\r
+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains\r
+ * the configuration information for the specified ETHERNET peripheral.\r
+ * @param PHYAddress: external PHY address \r
+ * @retval ETH_ERROR: Ethernet initialization failed\r
+ * ETH_SUCCESS: Ethernet successfully initialized \r
+ */\r
+uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)\r
+{\r
+ uint32_t RegValue = 0, tmpreg = 0;\r
+ __IO uint32_t i = 0;\r
+ RCC_ClocksTypeDef rcc_clocks;\r
+ uint32_t hclk = 60000000;\r
+ __IO uint32_t timeout = 0;\r
+ /* Check the parameters */\r
+ /* MAC --------------------------*/ \r
+ assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));\r
+ assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));\r
+ assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));\r
+ assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));\r
+ assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));\r
+ assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));\r
+ assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));\r
+ assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));\r
+ assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));\r
+ assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));\r
+ assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));\r
+ assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));\r
+ assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));\r
+ assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));\r
+ assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));\r
+ assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));\r
+ assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));\r
+ assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));\r
+ assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));\r
+ assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));\r
+ assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); \r
+ assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));\r
+ assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));\r
+ assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));\r
+ assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));\r
+ assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));\r
+ assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));\r
+ assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));\r
+ assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));\r
+ assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));\r
+ /* DMA --------------------------*/\r
+ assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));\r
+ assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));\r
+ assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));\r
+ assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));\r
+ assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));\r
+ assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));\r
+ assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));\r
+ assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));\r
+ assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));\r
+ assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));\r
+ assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));\r
+ assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));\r
+ assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); \r
+ assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); \r
+ assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); \r
+ /*-------------------------------- MAC Config ------------------------------*/ \r
+ /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/\r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH->MACMIIAR;\r
+ /* Clear CSR Clock Range CR[2:0] bits */\r
+ tmpreg &= MACMIIAR_CR_MASK;\r
+ /* Get hclk frequency value */\r
+ RCC_GetClocksFreq(&rcc_clocks);\r
+ hclk = rcc_clocks.HCLK_Frequency;\r
+ /* Set CR bits depending on hclk value */\r
+ if((hclk >= 20000000)&&(hclk < 35000000))\r
+ {\r
+ /* CSR Clock Range between 20-35 MHz */\r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;\r
+ }\r
+ else if((hclk >= 35000000)&&(hclk < 60000000))\r
+ {\r
+ /* CSR Clock Range between 35-60 MHz */ \r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; \r
+ } \r
+ else /* ((hclk >= 60000000)&&(hclk <= 72000000)) */\r
+ {\r
+ /* CSR Clock Range between 60-72 MHz */ \r
+ tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; \r
+ }\r
+ /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */\r
+ ETH->MACMIIAR = (uint32_t)tmpreg; \r
+ /*-------------------- PHY initialization and configuration ----------------*/\r
+ /* Put the PHY in reset mode */\r
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Delay to assure PHY reset */\r
+ _eth_delay_(PHY_ResetDelay);\r
+ \r
+ \r
+ if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)\r
+ { \r
+ /* We wait for linked satus... */\r
+ do\r
+ {\r
+ timeout++;\r
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ /* Reset Timeout counter */\r
+ timeout = 0;\r
+ \r
+ /* Enable Auto-Negotiation */\r
+ if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Wait until the autonegotiation will be completed */\r
+ do\r
+ {\r
+ timeout++;\r
+ } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO)); \r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ /* Reset Timeout counter */\r
+ timeout = 0;\r
+ \r
+ /* Read the result of the autonegotiation */\r
+ RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);\r
+ \r
+ /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */\r
+ if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)\r
+ {\r
+ /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */\r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;\r
+ \r
+ }\r
+ else\r
+ {\r
+ /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */\r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; \r
+ }\r
+ /* Configure the MAC with the speed fixed by the autonegotiation process */\r
+ if(RegValue & PHY_Speed_Status)\r
+ { \r
+ /* Set Ethernet speed to 10M following the autonegotiation */ \r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M; \r
+ }\r
+ else\r
+ { \r
+ /* Set Ethernet speed to 100M following the autonegotiation */ \r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_100M; \r
+ } \r
+ }\r
+ else\r
+ {\r
+ if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |\r
+ (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))\r
+ {\r
+ /* Return ERROR in case of write timeout */\r
+ return ETH_ERROR;\r
+ }\r
+ /* Delay to assure PHY configuration */\r
+ _eth_delay_(PHY_ConfigDelay);\r
+ \r
+ }\r
+ /*------------------------ ETHERNET MACCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACCR value */ \r
+ tmpreg = ETH->MACCR;\r
+ /* Clear WD, PCE, PS, TE and RE bits */\r
+ tmpreg &= MACCR_CLEAR_MASK;\r
+ /* Set the WD bit according to ETH_Watchdog value */\r
+ /* Set the JD: bit according to ETH_Jabber value */\r
+ /* Set the IFG bit according to ETH_InterFrameGap value */ \r
+ /* Set the DCRS bit according to ETH_CarrierSense value */ \r
+ /* Set the FES bit according to ETH_Speed value */ \r
+ /* Set the DO bit according to ETH_ReceiveOwn value */ \r
+ /* Set the LM bit according to ETH_LoopbackMode value */ \r
+ /* Set the DM bit according to ETH_Mode value */ \r
+ /* Set the IPC bit according to ETH_ChecksumOffload value */ \r
+ /* Set the DR bit according to ETH_RetryTransmission value */ \r
+ /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ \r
+ /* Set the BL bit according to ETH_BackOffLimit value */ \r
+ /* Set the DC bit according to ETH_DeferralCheck value */ \r
+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | \r
+ ETH_InitStruct->ETH_Jabber | \r
+ ETH_InitStruct->ETH_InterFrameGap |\r
+ ETH_InitStruct->ETH_CarrierSense |\r
+ ETH_InitStruct->ETH_Speed | \r
+ ETH_InitStruct->ETH_ReceiveOwn |\r
+ ETH_InitStruct->ETH_LoopbackMode |\r
+ ETH_InitStruct->ETH_Mode | \r
+ ETH_InitStruct->ETH_ChecksumOffload | \r
+ ETH_InitStruct->ETH_RetryTransmission | \r
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip | \r
+ ETH_InitStruct->ETH_BackOffLimit | \r
+ ETH_InitStruct->ETH_DeferralCheck);\r
+ /* Write to ETHERNET MACCR */\r
+ ETH->MACCR = (uint32_t)tmpreg;\r
+ \r
+ /*----------------------- ETHERNET MACFFR Configuration --------------------*/ \r
+ /* Set the RA bit according to ETH_ReceiveAll value */\r
+ /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */\r
+ /* Set the PCF bit according to ETH_PassControlFrames value */\r
+ /* Set the DBF bit according to ETH_BroadcastFramesReception value */\r
+ /* Set the DAIF bit according to ETH_DestinationAddrFilter value */\r
+ /* Set the PR bit according to ETH_PromiscuousMode value */\r
+ /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */\r
+ /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */\r
+ /* Write to ETHERNET MACFFR */ \r
+ ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | \r
+ ETH_InitStruct->ETH_SourceAddrFilter |\r
+ ETH_InitStruct->ETH_PassControlFrames |\r
+ ETH_InitStruct->ETH_BroadcastFramesReception | \r
+ ETH_InitStruct->ETH_DestinationAddrFilter |\r
+ ETH_InitStruct->ETH_PromiscuousMode |\r
+ ETH_InitStruct->ETH_MulticastFramesFilter |\r
+ ETH_InitStruct->ETH_UnicastFramesFilter); \r
+ /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/\r
+ /* Write to ETHERNET MACHTHR */\r
+ ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;\r
+ /* Write to ETHERNET MACHTLR */\r
+ ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;\r
+ /*----------------------- ETHERNET MACFCR Configuration --------------------*/\r
+ /* Get the ETHERNET MACFCR value */ \r
+ tmpreg = ETH->MACFCR;\r
+ /* Clear xx bits */\r
+ tmpreg &= MACFCR_CLEAR_MASK;\r
+ \r
+ /* Set the PT bit according to ETH_PauseTime value */\r
+ /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */\r
+ /* Set the PLT bit according to ETH_PauseLowThreshold value */\r
+ /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */\r
+ /* Set the RFE bit according to ETH_ReceiveFlowControl value */\r
+ /* Set the TFE bit according to ETH_TransmitFlowControl value */ \r
+ tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | \r
+ ETH_InitStruct->ETH_ZeroQuantaPause |\r
+ ETH_InitStruct->ETH_PauseLowThreshold |\r
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect | \r
+ ETH_InitStruct->ETH_ReceiveFlowControl |\r
+ ETH_InitStruct->ETH_TransmitFlowControl); \r
+ /* Write to ETHERNET MACFCR */\r
+ ETH->MACFCR = (uint32_t)tmpreg;\r
+ /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/\r
+ /* Set the ETV bit according to ETH_VLANTagComparison value */\r
+ /* Set the VL bit according to ETH_VLANTagIdentifier value */ \r
+ ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | \r
+ ETH_InitStruct->ETH_VLANTagIdentifier); \r
+ \r
+ /*-------------------------------- DMA Config ------------------------------*/\r
+ /*----------------------- ETHERNET DMAOMR Configuration --------------------*/\r
+ /* Get the ETHERNET DMAOMR value */ \r
+ tmpreg = ETH->DMAOMR;\r
+ /* Clear xx bits */\r
+ tmpreg &= DMAOMR_CLEAR_MASK;\r
+ \r
+ /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */\r
+ /* Set the RSF bit according to ETH_ReceiveStoreForward value */\r
+ /* Set the DFF bit according to ETH_FlushReceivedFrame value */\r
+ /* Set the TSF bit according to ETH_TransmitStoreForward value */\r
+ /* Set the TTC bit according to ETH_TransmitThresholdControl value */\r
+ /* Set the FEF bit according to ETH_ForwardErrorFrames value */\r
+ /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */\r
+ /* Set the RTC bit according to ETH_ReceiveThresholdControl value */\r
+ /* Set the OSF bit according to ETH_SecondFrameOperate value */\r
+ tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | \r
+ ETH_InitStruct->ETH_ReceiveStoreForward |\r
+ ETH_InitStruct->ETH_FlushReceivedFrame |\r
+ ETH_InitStruct->ETH_TransmitStoreForward | \r
+ ETH_InitStruct->ETH_TransmitThresholdControl |\r
+ ETH_InitStruct->ETH_ForwardErrorFrames |\r
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |\r
+ ETH_InitStruct->ETH_ReceiveThresholdControl | \r
+ ETH_InitStruct->ETH_SecondFrameOperate); \r
+ /* Write to ETHERNET DMAOMR */\r
+ ETH->DMAOMR = (uint32_t)tmpreg;\r
+ \r
+ /*----------------------- ETHERNET DMABMR Configuration --------------------*/ \r
+ /* Set the AAL bit according to ETH_AddressAlignedBeats value */\r
+ /* Set the FB bit according to ETH_FixedBurst value */\r
+ /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */\r
+ /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */\r
+ /* Set the DSL bit according to ETH_DesciptorSkipLength value */\r
+ /* Set the PR and DA bits according to ETH_DMAArbitration value */ \r
+ ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | \r
+ ETH_InitStruct->ETH_FixedBurst |\r
+ ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */\r
+ ETH_InitStruct->ETH_TxDMABurstLength | \r
+ (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |\r
+ ETH_InitStruct->ETH_DMAArbitration |\r
+ ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ \r
+ /* Return Ethernet configuration success */\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/**\r
+ * @brief Fills each ETH_InitStruct member with its default value.\r
+ * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure which will be initialized.\r
+ * @retval None\r
+ */\r
+void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)\r
+{\r
+ /* ETH_InitStruct members default value */\r
+ /*------------------------ MAC -----------------------------------*/ \r
+ ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; \r
+ ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; \r
+ ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; \r
+ ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; \r
+ ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; \r
+ ETH_InitStruct->ETH_Speed = ETH_Speed_10M; \r
+ ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; \r
+ ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; \r
+ ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; \r
+ ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; \r
+ ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; \r
+ ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; \r
+ ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; \r
+ ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; \r
+ ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; \r
+ ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; \r
+ ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; \r
+ ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;\r
+ ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; \r
+ ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; \r
+ ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; \r
+ ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; \r
+ ETH_InitStruct->ETH_HashTableHigh = 0x0; \r
+ ETH_InitStruct->ETH_HashTableLow = 0x0; \r
+ ETH_InitStruct->ETH_PauseTime = 0x0; \r
+ ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; \r
+ ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; \r
+ ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; \r
+ ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; \r
+ ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; \r
+ ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; \r
+ ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; \r
+ /*------------------------ DMA -----------------------------------*/ \r
+ ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; \r
+ ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; \r
+ ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable; \r
+ ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; \r
+ ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; \r
+ ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; \r
+ ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; \r
+ ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; \r
+ ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;\r
+ ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;\r
+ ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;\r
+ ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;\r
+ ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;\r
+ ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;\r
+ ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;\r
+}\r
+\r
+/**\r
+ * @brief Enables ENET MAC and DMA reception/transmission \r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_Start(void)\r
+{\r
+ /* Enable transmit state machine of the MAC for transmission on the MII */ \r
+ ETH_MACTransmissionCmd(ENABLE);\r
+ /* Flush Transmit FIFO */\r
+ ETH_FlushTransmitFIFO();\r
+ /* Enable receive state machine of the MAC for reception from the MII */ \r
+ ETH_MACReceptionCmd(ENABLE);\r
+ \r
+ /* Start DMA transmission */\r
+ ETH_DMATransmissionCmd(ENABLE); \r
+ /* Start DMA reception */\r
+ ETH_DMAReceptionCmd(ENABLE); \r
+}\r
+\r
+/**\r
+ * @brief Transmits a packet, from application buffer, pointed by ppkt.\r
+ * @param ppkt: pointer to the application's packet buffer to transmit.\r
+ * @param FrameLength: Tx Packet size.\r
+ * @retval ETH_ERROR: in case of Tx desc owned by DMA\r
+ * ETH_SUCCESS: for correct transmission\r
+ */\r
+uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)\r
+{ \r
+ uint32_t offset = 0;\r
+ \r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return ERROR: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ \r
+ for(offset=0; offset<FrameLength; offset++) \r
+ {\r
+ (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));\r
+ }\r
+ \r
+ /* Setting the Frame Length: bits[12:0] */\r
+ DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);\r
+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ \r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ ETH->DMATPDR = 0;\r
+ }\r
+ \r
+ /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ \r
+ /* Chained Mode */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)\r
+ { \r
+ /* Selects the next DMA Tx descriptor list for next buffer to send */ \r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); \r
+ }\r
+ else /* Ring Mode */\r
+ { \r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); \r
+ }\r
+ else\r
+ { \r
+ /* Selects the next DMA Tx descriptor list for next buffer to send */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS; \r
+}\r
+\r
+/**\r
+ * @brief Receives a packet and copies it to memory pointed by ppkt.\r
+ * @param ppkt: pointer to the application packet receive buffer.\r
+ * @retval ETH_ERROR: if there is error in reception\r
+ * framelength: received packet size if packet reception is correct\r
+ */\r
+uint32_t ETH_HandleRxPkt(uint8_t *ppkt)\r
+{ \r
+ uint32_t offset = 0, framelength = 0;\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return error: OWN bit set */\r
+ return ETH_ERROR; \r
+ }\r
+ \r
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && \r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && \r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) \r
+ { \r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;\r
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */\r
+ for(offset=0; offset<framelength; offset++) \r
+ {\r
+ (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return ERROR */\r
+ framelength = ETH_ERROR;\r
+ }\r
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN; \r
+ \r
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */\r
+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) \r
+ {\r
+ /* Clear RBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_RBUS;\r
+ /* Resume DMA reception */\r
+ ETH->DMARPDR = 0;\r
+ }\r
+ \r
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ \r
+ /* Chained Mode */\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)\r
+ { \r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */ \r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); \r
+ }\r
+ else /* Ring Mode */\r
+ { \r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); \r
+ }\r
+ else\r
+ { \r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ \r
+ /* Return Frame Length/ERROR */\r
+ return (framelength); \r
+}\r
+\r
+/**\r
+ * @brief Get the size of received the received packet.\r
+ * @param None\r
+ * @retval framelength: received packet size \r
+ */\r
+uint32_t ETH_GetRxPktSize(void)\r
+{\r
+ uint32_t frameLength = 0;\r
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))\r
+ {\r
+ /* Get the size of the packet: including 4 bytes of the CRC */\r
+ frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);\r
+ }\r
+ \r
+ /* Return Frame Length */ \r
+ return frameLength;\r
+}\r
+\r
+/**\r
+ * @brief Drop a Received packet (too small packet, etc...)\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_DropRxPkt(void)\r
+{\r
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMARxDescToGet->Status = ETH_DMARxDesc_OWN; \r
+ /* Chained Mode */\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);\r
+ }\r
+ else /* Ring Mode */\r
+ {\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read: this will\r
+ be the first Rx descriptor in this case */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));\r
+ }\r
+ }\r
+}\r
+\r
+/*--------------------------------- PHY ------------------------------------*/\r
+/**\r
+ * @brief Read a PHY register\r
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. \r
+ * This parameter can be one of the following values: 0,..,31 \r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * @arg PHY_BCR: Tranceiver Basic Control Register \r
+ * @arg PHY_BSR: Tranceiver Basic Status Register \r
+ * @arg PHY_SR : Tranceiver Status Register \r
+ * @arg More PHY register could be read depending on the used PHY\r
+ * @retval ETH_ERROR: in case of timeout\r
+ * MAC MIIDR register value: Data read from the selected PHY register (correct read )\r
+ */\r
+uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)\r
+{\r
+ uint32_t tmpreg = 0; \r
+__IO uint32_t timeout = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ assert_param(IS_ETH_PHY_REG(PHYReg));\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH->MACMIIAR;\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~MACMIIAR_CR_MASK;\r
+ /* Prepare the MII address register value */\r
+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ /* Write the result value into the MII Address register */\r
+ ETH->MACMIIAR = tmpreg;\r
+ /* Check for the Busy flag */\r
+ do\r
+ {\r
+ timeout++;\r
+ tmpreg = ETH->MACMIIAR;\r
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return (uint16_t)ETH_ERROR;\r
+ }\r
+ \r
+ /* Return data register value */\r
+ return (uint16_t)(ETH->MACMIIDR);\r
+}\r
+\r
+/**\r
+ * @brief Write to a PHY register\r
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. \r
+ * This parameter can be one of the following values: 0,..,31\r
+ * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. \r
+ * This parameter can be one of the following values: \r
+ * @arg PHY_BCR : Tranceiver Control Register \r
+ * @arg More PHY register could be written depending on the used PHY\r
+ * @param PHYValue: the value to write\r
+ * @retval ETH_ERROR: in case of timeout\r
+ * ETH_SUCCESS: for correct write\r
+ */\r
+uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)\r
+{\r
+ uint32_t tmpreg = 0; \r
+ __IO uint32_t timeout = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ assert_param(IS_ETH_PHY_REG(PHYReg));\r
+ \r
+ /* Get the ETHERNET MACMIIAR value */\r
+ tmpreg = ETH->MACMIIAR;\r
+ /* Keep only the CSR Clock Range CR[2:0] bits value */\r
+ tmpreg &= ~MACMIIAR_CR_MASK;\r
+ /* Prepare the MII register address value */\r
+ tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */\r
+ tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */\r
+ tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */\r
+ tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */\r
+ /* Give the value to the MII data register */\r
+ ETH->MACMIIDR = PHYValue;\r
+ /* Write the result value into the MII Address register */\r
+ ETH->MACMIIAR = tmpreg;\r
+ /* Check for the Busy flag */\r
+ do\r
+ {\r
+ timeout++;\r
+ tmpreg = ETH->MACMIIAR;\r
+ } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_WRITE_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ \r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PHY loopBack mode.\r
+ * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal\r
+ * loopback at MII level\r
+ * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. \r
+ * This parameter can be one of the following values: \r
+ * @param NewState: new state of the PHY loopBack mode.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval ETH_ERROR: in case of bad PHY configuration\r
+ * ETH_SUCCESS: for correct PHY configuration\r
+ */\r
+uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)\r
+{\r
+ uint16_t tmpreg = 0;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ /* Get the PHY configuration to update it */\r
+ tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PHY loopback mode */\r
+ tmpreg |= PHY_Loopback; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the PHY loopback mode: normal mode */\r
+ tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);\r
+ }\r
+ /* Update the PHY control register with the new configuration */\r
+ if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)\r
+ {\r
+ return ETH_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ /* Return SUCCESS */\r
+ return ETH_ERROR; \r
+ } \r
+}\r
+\r
+/*--------------------------------- MAC ------------------------------------*/\r
+/**\r
+ * @brief Enables or disables the MAC transmission.\r
+ * @param NewState: new state of the MAC transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACTransmissionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC transmission */\r
+ ETH->MACCR |= ETH_MACCR_TE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC transmission */\r
+ ETH->MACCR &= ~ETH_MACCR_TE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC reception.\r
+ * @param NewState: new state of the MAC reception.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACReceptionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC reception */\r
+ ETH->MACCR |= ETH_MACCR_RE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC reception */\r
+ ETH->MACCR &= ~ETH_MACCR_RE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET flow control busy bit is set or not.\r
+ * @param None\r
+ * @retval The new state of flow control busy status bit (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetFlowControlBusyStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* The Flow Control register should not be written to until this bit is cleared */\r
+ if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Initiate a Pause Control Frame (Full-duplex only).\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_InitiatePauseControlFrame(void) \r
+{ \r
+ /* When Set In full duplex MAC initiates pause control frame */\r
+ ETH->MACFCR |= ETH_MACFCR_FCBBPA; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only).\r
+ * @param NewState: new state of the MAC BackPressure operation activation.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_BackPressureActivationCmd(FunctionalState NewState) \r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Activate the MAC BackPressure operation */\r
+ /* In Half duplex: during backpressure, when the MAC receives a new frame,\r
+ the transmitter starts sending a JAM pattern resulting in a collision */\r
+ ETH->MACFCR |= ETH_MACFCR_FCBBPA; \r
+ }\r
+ else\r
+ {\r
+ /* Desactivate the MAC BackPressure operation */\r
+ ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; \r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MAC flag is set or not.\r
+ * @param ETH_MAC_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag \r
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag \r
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag \r
+ * @arg ETH_MAC_FLAG_MMC : MMC flag \r
+ * @arg ETH_MAC_FLAG_PMT : PMT flag \r
+ * @retval The new state of ETHERNET MAC flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); \r
+ if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not.\r
+ * @param ETH_MAC_IT: specifies the interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt \r
+ * @arg ETH_MAC_IT_MMCR : MMC receive interrupt \r
+ * @arg ETH_MAC_IT_MMC : MMC interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt \r
+ * @retval The new state of ETHERNET MAC interrupt (SET or RESET).\r
+ */\r
+ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); \r
+ if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ETHERNET MAC interrupts.\r
+ * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt \r
+ * @arg ETH_MAC_IT_PMT : PMT interrupt \r
+ * @param NewState: new state of the specified ETHERNET MAC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MAC interrupts */\r
+ ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MAC interrupts */\r
+ ETH->MACIMR |= ETH_MAC_IT;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the selected MAC address.\r
+ * @param MacAddr: The MAC addres to configure.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0 : MAC Address0 \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param Addr: Pointer on MAC address buffer data (6 bytes).\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+ \r
+ /* Calculate the selectecd MAC address high register */\r
+ tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];\r
+ /* Load the selectecd MAC address high register */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg;\r
+ /* Calculate the selectecd MAC address low register */\r
+ tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];\r
+ \r
+ /* Load the selectecd MAC address low register */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg;\r
+}\r
+\r
+/**\r
+ * @brief Get the selected MAC address.\r
+ * @param MacAddr: The MAC addres to return.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MAC_Address0 : MAC Address0 \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param Addr: Pointer on MAC address buffer data (6 bytes).\r
+ * @retval None\r
+ */\r
+void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr)\r
+{\r
+ uint32_t tmpreg;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));\r
+ \r
+ /* Get the selectecd MAC address high register */\r
+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr));\r
+ \r
+ /* Calculate the selectecd MAC address buffer */\r
+ Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF);\r
+ Addr[4] = (tmpreg & (uint8_t)0xFF);\r
+ /* Load the selectecd MAC address low register */\r
+ tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr));\r
+ /* Calculate the selectecd MAC address buffer */\r
+ Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF);\r
+ Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF);\r
+ Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF);\r
+ Addr[0] = (tmpreg & (uint8_t)0xFF);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the Address filter module uses the specified\r
+ * ETHERNET MAC address for perfect filtering \r
+ * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering.\r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param NewState: new state of the specified ETHERNET MAC address use.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MAC address for perfect filtering */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MAC address for perfect filtering */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the filter type for the specified ETHERNET MAC address \r
+ * @param MacAddr: specifies the ETHERNET MAC address \r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param Filter: specifies the used frame received field for comparaison \r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the\r
+ * SA fields of the received frame.\r
+ * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the\r
+ * DA fields of the received frame.\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter));\r
+ \r
+ if (Filter != ETH_MAC_AddressFilter_DA)\r
+ {\r
+ /* The selected ETHERNET MAC address is used to compare with the SA fields of the\r
+ received frame. */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA;\r
+ }\r
+ else\r
+ {\r
+ /* The selected ETHERNET MAC address is used to compare with the DA fields of the\r
+ received frame. */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Set the filter type for the specified ETHERNET MAC address \r
+ * @param MacAddr: specifies the ETHERNET MAC address \r
+ * This parameter can be one of the following values: \r
+ * @arg ETH_MAC_Address1 : MAC Address1 \r
+ * @arg ETH_MAC_Address2 : MAC Address2\r
+ * @arg ETH_MAC_Address3 : MAC Address3\r
+ * @param MaskByte: specifies the used address bytes for comparaison \r
+ * This parameter can be any combination of the following values: \r
+ * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8].\r
+ * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0].\r
+ * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24].\r
+ * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16].\r
+ * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8].\r
+ * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0].\r
+ * @retval None\r
+ */\r
+void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MAC_ADDRESS123(MacAddr));\r
+ assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte));\r
+ \r
+ /* Clear MBC bits in the selected MAC address high register */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC);\r
+ /* Set the selected Filetr mask bytes */\r
+ (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte;\r
+}\r
+/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode.\r
+ * @param DMATxDescTab: Pointer on the first Tx desc list \r
+ * @param TxBuff: Pointer on the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab + i;\r
+ /* Set Second Address Chained bit */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TCH; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; \r
+ }\r
+ }\r
+ \r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in ring mode.\r
+ * @param DMATxDescTab: Pointer on the first Tx desc list \r
+ * @param TxBuff1: Pointer on the first TxBuffer1 list \r
+ * @param TxBuff2: Pointer on the first TxBuffer2 list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct\r
+ * for the number of Words to skip between two unchained descriptors. \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab + i;\r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Set Buffer2 address pointer */\r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base\r
+ address of the list, creating a Desciptor Ring */\r
+ if(i == (TxBuffCount-1))\r
+ {\r
+ /* Set Transmit End of Ring bit */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TER;\r
+ }\r
+ }\r
+ \r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param ETH_DMATxDescFlag: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine\r
+ * @arg ETH_DMATxDesc_IC : Interrupt on completetion\r
+ * @arg ETH_DMATxDesc_LS : Last Segment\r
+ * @arg ETH_DMATxDesc_FS : First Segment\r
+ * @arg ETH_DMATxDesc_DC : Disable CRC\r
+ * @arg ETH_DMATxDesc_DP : Disable Pad\r
+ * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable\r
+ * @arg ETH_DMATxDesc_TER : Transmit End of Ring\r
+ * @arg ETH_DMATxDesc_TCH : Second Address Chained\r
+ * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status\r
+ * @arg ETH_DMATxDesc_IHE : IP Header Error\r
+ * @arg ETH_DMATxDesc_ES : Error summary\r
+ * @arg ETH_DMATxDesc_JT : Jabber Timeout\r
+ * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush\r
+ * @arg ETH_DMATxDesc_PCE : Payload Checksum Error\r
+ * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission\r
+ * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver\r
+ * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision\r
+ * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions\r
+ * @arg ETH_DMATxDesc_VF : VLAN Frame\r
+ * @arg ETH_DMATxDesc_CC : Collision Count \r
+ * @arg ETH_DMATxDesc_ED : Excessive Deferral\r
+ * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory\r
+ * @arg ETH_DMATxDesc_DB : Deferred Bit\r
+ * @retval The new state of ETH_DMATxDescFlag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag));\r
+ \r
+ if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Returns the specified ETHERNET DMA Tx Desc collision count.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor \r
+ * @retval The Transmit descriptor collision counter value.\r
+ */\r
+uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc)\r
+{\r
+ /* Return the Receive descriptor frame length */\r
+ return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT);\r
+}\r
+\r
+/**\r
+ * @brief Set the specified DMA Tx Desc Own bit.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @retval None\r
+ */\r
+void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc)\r
+{\r
+ /* Set the DMA Tx Desc Own bit */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_OWN;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @param NewState: new state of the DMA Tx Desc transmit interrupt.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA Tx Desc Transmit interrupt */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_IC;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA Tx Desc Transmit interrupt */\r
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment \r
+ * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment));\r
+ \r
+ /* Selects the DMA Tx Desc Frame segment */\r
+ DMATxDesc->Status |= DMATxDesc_FrameSegment;\r
+}\r
+\r
+/**\r
+ * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor \r
+ * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass\r
+ * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum\r
+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present\r
+ * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header \r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum));\r
+ \r
+ /* Set the selected DMA Tx desc checksum insertion control */\r
+ DMATxDesc->Status |= DMATxDesc_Checksum;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc CRC.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc CRC.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc CRC */\r
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc CRC */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_DC; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc end of ring.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc end of ring.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc end of ring */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TER; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc end of ring */\r
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc second address chained.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc second address chained.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc second address chained */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TCH; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc second address chained */\r
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */\r
+ DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/\r
+ DMATxDesc->Status |= ETH_DMATxDesc_DP; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Tx Desc time stamp.\r
+ * @param DMATxDesc: pointer on a DMA Tx descriptor\r
+ * @param NewState: new state of the specified DMA Tx Desc time stamp.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Tx Desc time stamp */\r
+ DMATxDesc->Status |= ETH_DMATxDesc_TTSE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Tx Desc time stamp */\r
+ DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes.\r
+ * @param DMATxDesc: Pointer on a Tx desc\r
+ * @param BufferSize1: specifies the Tx desc buffer1 size.\r
+ * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used).\r
+ * @retval None\r
+ */\r
+void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1));\r
+ assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2));\r
+ \r
+ /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */\r
+ DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT));\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param DMARxDescTab: Pointer on the first Rx desc list \r
+ * @param RxBuff: Pointer on the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+ \r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab; \r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); \r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); \r
+ }\r
+ }\r
+ \r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab; \r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in ring mode.\r
+ * @param DMARxDescTab: Pointer on the first Rx desc list \r
+ * @param RxBuff1: Pointer on the first RxBuffer1 list \r
+ * @param RxBuff2: Pointer on the first RxBuffer2 list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * Note: see decriptor skip length defined in ETH_DMA_InitStruct\r
+ * for the number of Words to skip between two unchained descriptors. \r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab; \r
+ /* Fill each DMARxDesc descriptor with the right values */ \r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i; \r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN; \r
+ /* Set Buffer1 size */\r
+ DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); \r
+ \r
+ /* Set Buffer2 address pointer */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); \r
+ \r
+ /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base\r
+ address of the list, creating a Desciptor Ring */\r
+ if(i == (RxBuffCount-1))\r
+ {\r
+ /* Set Receive End of Ring bit */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER;\r
+ }\r
+ }\r
+ \r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor\r
+ * @param ETH_DMARxDescFlag: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine \r
+ * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame\r
+ * @arg ETH_DMARxDesc_ES: Error summary\r
+ * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame\r
+ * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame\r
+ * @arg ETH_DMARxDesc_LE: Frame size not matching with length field\r
+ * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow\r
+ * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame\r
+ * @arg ETH_DMARxDesc_FS: First descriptor of the frame\r
+ * @arg ETH_DMARxDesc_LS: Last descriptor of the frame\r
+ * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error \r
+ * @arg ETH_DMARxDesc_LC: Late collision occurred during reception\r
+ * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3\r
+ * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception\r
+ * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface\r
+ * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits\r
+ * @arg ETH_DMARxDesc_CE: CRC error\r
+ * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error\r
+ * @retval The new state of ETH_DMARxDescFlag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag));\r
+ if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Set the specified DMA Rx Desc Own bit.\r
+ * @param DMARxDesc: Pointer on a Rx desc\r
+ * @retval None\r
+ */\r
+void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc)\r
+{\r
+ /* Set the DMA Rx Desc Own bit */\r
+ DMARxDesc->Status |= ETH_DMARxDesc_OWN;\r
+}\r
+\r
+/**\r
+ * @brief Returns the specified DMA Rx Desc frame length.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor \r
+ * @retval The Rx descriptor received frame length.\r
+ */\r
+uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc)\r
+{\r
+ /* Return the Receive descriptor frame length */\r
+ return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT);\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified DMA Rx Desc receive interrupt.\r
+ * @param DMARxDesc: Pointer on a Rx desc\r
+ * @param NewState: new state of the specified DMA Rx Desc interrupt.\r
+ * This parameter can be: ENABLE or DISABLE. \r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA Rx Desc receive interrupt */\r
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA Rx Desc receive interrupt */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Rx Desc end of ring.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor\r
+ * @param NewState: new state of the specified DMA Rx Desc end of ring.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Rx Desc end of ring */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Rx Desc end of ring */\r
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA Rx Desc second address chained.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor\r
+ * @param NewState: new state of the specified DMA Rx Desc second address chained.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected DMA Rx Desc second address chained */\r
+ DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected DMA Rx Desc second address chained */\r
+ DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Returns the specified ETHERNET DMA Rx Desc buffer size.\r
+ * @param DMARxDesc: pointer on a DMA Rx descriptor \r
+ * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer.\r
+ * This parameter can be any one of the following values:\r
+ * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1\r
+ * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 \r
+ * @retval The Receive descriptor frame length.\r
+ */\r
+uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer));\r
+ \r
+ if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1)\r
+ {\r
+ /* Return the DMA Rx Desc buffer2 size */\r
+ return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); \r
+ }\r
+ else\r
+ {\r
+ /* Return the DMA Rx Desc buffer1 size */\r
+ return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); \r
+ }\r
+}\r
+\r
+/*--------------------------------- DMA ------------------------------------*/\r
+/**\r
+ * @brief Resets all MAC subsystem internal registers and logic.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_SoftwareReset(void)\r
+{\r
+ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */\r
+ /* After reset all the registers holds their respective reset values */\r
+ ETH->DMABMR |= ETH_DMABMR_SR;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET software reset bit is set or not.\r
+ * @param None\r
+ * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetSoftwareResetStatus(void)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA flag is set or not.\r
+ * @param ETH_DMA_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag\r
+ * @arg ETH_DMA_FLAG_PMT : PMT flag \r
+ * @arg ETH_DMA_FLAG_MMC : MMC flag \r
+ * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access\r
+ * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr\r
+ * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA\r
+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag\r
+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag \r
+ * @arg ETH_DMA_FLAG_ER : Early receive flag \r
+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag \r
+ * @arg ETH_DMA_FLAG_ET : Early transmit flag \r
+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag \r
+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag \r
+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_R : Receive flag \r
+ * @arg ETH_DMA_FLAG_TU : Underflow flag \r
+ * @arg ETH_DMA_FLAG_RO : Overflow flag \r
+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag \r
+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag \r
+ * @arg ETH_DMA_FLAG_T : Transmit flag \r
+ * @retval The new state of ETH_DMA_FLAG (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG)\r
+{ \r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG));\r
+ if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET\92s DMA pending flag.\r
+ * @param ETH_DMA_FLAG: specifies the flag to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag\r
+ * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag \r
+ * @arg ETH_DMA_FLAG_ER : Early receive flag \r
+ * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag \r
+ * @arg ETH_DMA_FLAG_ETI : Early transmit flag \r
+ * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag \r
+ * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag \r
+ * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_R : Receive flag \r
+ * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag \r
+ * @arg ETH_DMA_FLAG_RO : Receive Overflow flag \r
+ * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag \r
+ * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag \r
+ * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag \r
+ * @arg ETH_DMA_FLAG_T : Transmit flag\r
+ * @retval None\r
+ */\r
+void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG));\r
+ \r
+ /* Clear the selected ETHERNET DMA FLAG */\r
+ ETH->DMASR = (uint32_t) ETH_DMA_FLAG;\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not.\r
+ * @param ETH_DMA_IT: specifies the interrupt source to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt\r
+ * @arg ETH_DMA_IT_PMT : PMT interrupt \r
+ * @arg ETH_DMA_IT_MMC : MMC interrupt\r
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary \r
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary \r
+ * @arg ETH_DMA_IT_ER : Early receive interrupt \r
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt \r
+ * @arg ETH_DMA_IT_ET : Early transmit interrupt \r
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt \r
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt \r
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_R : Receive interrupt \r
+ * @arg ETH_DMA_IT_TU : Underflow interrupt \r
+ * @arg ETH_DMA_IT_RO : Overflow interrupt \r
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt \r
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt \r
+ * @arg ETH_DMA_IT_T : Transmit interrupt \r
+ * @retval The new state of ETH_DMA_IT (SET or RESET).\r
+ */\r
+ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT)\r
+{ \r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT));\r
+ if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET\92s DMA IT pending bit.\r
+ * @param ETH_DMA_IT: specifies the interrupt pending bit to clear.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary \r
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary \r
+ * @arg ETH_DMA_IT_ER : Early receive interrupt \r
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt \r
+ * @arg ETH_DMA_IT_ETI : Early transmit interrupt \r
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt \r
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt \r
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_R : Receive interrupt \r
+ * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt \r
+ * @arg ETH_DMA_IT_RO : Receive Overflow interrupt \r
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt \r
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt \r
+ * @arg ETH_DMA_IT_T : Transmit interrupt\r
+ * @retval None\r
+ */\r
+void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));\r
+ \r
+ /* Clear the selected ETHERNET DMA IT */\r
+ ETH->DMASR = (uint32_t) ETH_DMA_IT;\r
+}\r
+\r
+/**\r
+ * @brief Returns the ETHERNET DMA Transmit Process State.\r
+ * @param None\r
+ * @retval The new ETHERNET DMA Transmit Process State:\r
+ * This can be one of the following values:\r
+ * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued\r
+ * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor \r
+ * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status\r
+ * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory\r
+ * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe\r
+ * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor \r
+ */\r
+uint32_t ETH_GetTransmitProcessState(void)\r
+{\r
+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); \r
+}\r
+\r
+/**\r
+ * @brief Returns the ETHERNET DMA Receive Process State.\r
+ * @param None\r
+ * @retval The new ETHERNET DMA Receive Process State:\r
+ * This can be one of the following values:\r
+ * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued\r
+ * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor \r
+ * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet\r
+ * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable\r
+ * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor\r
+ * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory \r
+ */\r
+uint32_t ETH_GetReceiveProcessState(void)\r
+{\r
+ return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); \r
+}\r
+\r
+/**\r
+ * @brief Clears the ETHERNET transmit FIFO.\r
+ * @param None \r
+ * @retval None\r
+ */\r
+void ETH_FlushTransmitFIFO(void)\r
+{\r
+ /* Set the Flush Transmit FIFO bit */\r
+ ETH->DMAOMR |= ETH_DMAOMR_FTF; \r
+}\r
+\r
+/**\r
+ * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not.\r
+ * @param None \r
+ * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetFlushTransmitFIFOStatus(void)\r
+{ \r
+ FlagStatus bitstatus = RESET;\r
+ if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA transmission.\r
+ * @param NewState: new state of the DMA transmission.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMATransmissionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA transmission */\r
+ ETH->DMAOMR |= ETH_DMAOMR_ST; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA transmission */\r
+ ETH->DMAOMR &= ~ETH_DMAOMR_ST;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the DMA reception.\r
+ * @param NewState: new state of the DMA reception.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMAReceptionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the DMA reception */\r
+ ETH->DMAOMR |= ETH_DMAOMR_SR; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the DMA reception */\r
+ ETH->DMAOMR &= ~ETH_DMAOMR_SR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ETHERNET DMA interrupts.\r
+ * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be\r
+ * enabled or disabled.\r
+ * This parameter can be any combination of the following values:\r
+ * @arg ETH_DMA_IT_NIS : Normal interrupt summary \r
+ * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary \r
+ * @arg ETH_DMA_IT_ER : Early receive interrupt \r
+ * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt \r
+ * @arg ETH_DMA_IT_ET : Early transmit interrupt \r
+ * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt \r
+ * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt \r
+ * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_R : Receive interrupt \r
+ * @arg ETH_DMA_IT_TU : Underflow interrupt \r
+ * @arg ETH_DMA_IT_RO : Overflow interrupt \r
+ * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt \r
+ * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt \r
+ * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt \r
+ * @arg ETH_DMA_IT_T : Transmit interrupt\r
+ * @param NewState: new state of the specified ETHERNET DMA interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_IT(ETH_DMA_IT));\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET DMA interrupts */\r
+ ETH->DMAIER |= ETH_DMA_IT;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET DMA interrupts */\r
+ ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.\r
+ * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter\r
+ * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter\r
+ * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow));\r
+ \r
+ if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value.\r
+ * @param None\r
+ * @retval The value of Rx overflow Missed Frame Counter.\r
+ */\r
+uint32_t ETH_GetRxOverflowMissedFrameCounter(void)\r
+{\r
+ return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value.\r
+ * @param None\r
+ * @retval The value of Buffer unavailable Missed Frame Counter.\r
+ */\r
+uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void)\r
+{\r
+ return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC);\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHTDR register value.\r
+ * @param None\r
+ * @retval The value of the current Tx desc start address.\r
+ */\r
+uint32_t ETH_GetCurrentTxDescStartAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHTDR));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHRDR register value.\r
+ * @param None\r
+ * @retval The value of the current Rx desc start address.\r
+ */\r
+uint32_t ETH_GetCurrentRxDescStartAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHRDR));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHTBAR register value.\r
+ * @param None\r
+ * @retval The value of the current Tx buffer address.\r
+ */\r
+uint32_t ETH_GetCurrentTxBufferAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHTBAR));\r
+}\r
+\r
+/**\r
+ * @brief Get the ETHERNET DMA DMACHRBAR register value.\r
+ * @param None\r
+ * @retval The value of the current Rx buffer address.\r
+ */\r
+uint32_t ETH_GetCurrentRxBufferAddress(void)\r
+{\r
+ return ((uint32_t)(ETH->DMACHRBAR));\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register\r
+ * (the data written could be anything). This forces the DMA to resume transmission.\r
+ * @param None\r
+ * @retval None.\r
+ */\r
+void ETH_ResumeDMATransmission(void)\r
+{\r
+ ETH->DMATPDR = 0;\r
+}\r
+\r
+/**\r
+ * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register\r
+ * (the data written could be anything). This forces the DMA to resume reception.\r
+ * @param None\r
+ * @retval None.\r
+ */\r
+void ETH_ResumeDMAReception(void)\r
+{\r
+ ETH->DMARPDR = 0;\r
+}\r
+\r
+/*--------------------------------- PMT ------------------------------------*/\r
+/**\r
+ * @brief Reset Wakeup frame filter register pointer.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_ResetWakeUpFrameFilterRegisterPointer(void)\r
+{ \r
+ /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; \r
+}\r
+\r
+/**\r
+ * @brief Populates the remote wakeup frame registers.\r
+ * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words).\r
+ * @retval None\r
+ */\r
+void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer)\r
+{\r
+ uint32_t i = 0;\r
+ \r
+ /* Fill Remote Wake-up Frame Filter register with Buffer data */\r
+ for(i =0; i<ETH_WAKEUP_REGISTER_LENGTH; i++)\r
+ {\r
+ /* Write each time to the same register */ \r
+ ETH->MACRWUFFR = Buffer[i];\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables any unicast packet filtered by the MAC address\r
+ * recognition to be a wake-up frame.\r
+ * @param NewState: new state of the MAC Global Unicast Wake-Up.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Global Unicast Wake-Up */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Global Unicast Wake-Up */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET PMT flag is set or not.\r
+ * @param ETH_PMT_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset \r
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received \r
+ * @arg ETH_PMT_FLAG_MPR : Magic Packet Received\r
+ * @retval The new state of ETHERNET PMT Flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG));\r
+ \r
+ if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC Wake-Up Frame Detection.\r
+ * @param NewState: new state of the MAC Wake-Up Frame Detection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Wake-Up Frame Detection */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Wake-Up Frame Detection */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC Magic Packet Detection.\r
+ * @param NewState: new state of the MAC Magic Packet Detection.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MagicPacketDetectionCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Magic Packet Detection */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Magic Packet Detection */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MAC Power Down.\r
+ * @param NewState: new state of the MAC Power Down.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_PowerDownCmd(FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MAC Power Down */\r
+ /* This puts the MAC in power down mode */\r
+ ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MAC Power Down */ \r
+ ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD;\r
+ }\r
+}\r
+\r
+/*--------------------------------- MMC ------------------------------------*/\r
+/**\r
+ * @brief Enables or disables the MMC Counter Freeze.\r
+ * @param NewState: new state of the MMC Counter Freeze.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCCounterFreezeCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MMC Counter Freeze */\r
+ ETH->MMCCR |= ETH_MMCCR_MCF;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the MMC Counter Freeze */\r
+ ETH->MMCCR &= ~ETH_MMCCR_MCF;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MMC Reset On Read.\r
+ * @param NewState: new state of the MMC Reset On Read.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCResetOnReadCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the MMC Counter reset on read */\r
+ ETH->MMCCR |= ETH_MMCCR_ROR; \r
+ }\r
+ else\r
+ {\r
+ /* Disable the MMC Counter reset on read */\r
+ ETH->MMCCR &= ~ETH_MMCCR_ROR;\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the MMC Counter Stop Rollover.\r
+ * @param NewState: new state of the MMC Counter Stop Rollover.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCCounterRolloverCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Disable the MMC Counter Stop Rollover */\r
+ ETH->MMCCR &= ~ETH_MMCCR_CSR;\r
+ }\r
+ else\r
+ {\r
+ /* Enable the MMC Counter Stop Rollover */\r
+ ETH->MMCCR |= ETH_MMCCR_CSR; \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Resets the MMC Counters.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_MMCCountersReset(void)\r
+{\r
+ /* Resets the MMC Counters */\r
+ ETH->MMCCR |= ETH_MMCCR_CR; \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the specified ETHERNET MMC interrupts.\r
+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.\r
+ * This parameter can be any combination of Tx interrupt or \r
+ * any combination of Rx interrupt (but not both)of the following values: \r
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value\r
+ * @param NewState: new state of the specified ETHERNET MMC interrupts.\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState)\r
+{ \r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); \r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)\r
+ {\r
+ /* Remove egister mak from IT */\r
+ ETH_MMC_IT &= 0xEFFFFFFF;\r
+ \r
+ /* ETHERNET MMC Rx interrupts selected */\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCRIMR |= ETH_MMC_IT; \r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* ETHERNET MMC Tx interrupts selected */\r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT);\r
+ }\r
+ else\r
+ {\r
+ /* Disable the selected ETHERNET MMC interrupts */\r
+ ETH->MMCTIMR |= ETH_MMC_IT; \r
+ } \r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET MMC IT is set or not.\r
+ * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value \r
+ * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value \r
+ * @retval The value of ETHERNET MMC IT (SET or RESET).\r
+ */\r
+ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT)\r
+{\r
+ ITStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); \r
+ \r
+ if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET)\r
+ {\r
+ /* ETHERNET MMC Rx interrupts selected */\r
+ /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ \r
+ if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* ETHERNET MMC Tx interrupts selected */\r
+ /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ \r
+ if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET))\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ } \r
+ } \r
+ \r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Get the specified ETHERNET MMC register value.\r
+ * @param ETH_MMCReg: specifies the ETHERNET MMC register.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_MMCCR : MMC CR register \r
+ * @arg ETH_MMCRIR : MMC RIR register \r
+ * @arg ETH_MMCTIR : MMC TIR register \r
+ * @arg ETH_MMCRIMR : MMC RIMR register \r
+ * @arg ETH_MMCTIMR : MMC TIMR register \r
+ * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register \r
+ * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register \r
+ * @arg ETH_MMCTGFCR : MMC TGFCR register\r
+ * @arg ETH_MMCRFCECR : MMC RFCECR register \r
+ * @arg ETH_MMCRFAECR : MMC RFAECR register \r
+ * @arg ETH_MMCRGUFCR : MMC RGUFCRregister \r
+ * @retval The value of ETHERNET MMC Register value.\r
+ */\r
+uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg));\r
+ \r
+ /* Return the selected register value */\r
+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg));\r
+}\r
+/*--------------------------------- PTP ------------------------------------*/\r
+\r
+/**\r
+ * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_EnablePTPTimeStampAddend(void)\r
+{\r
+ /* Enable the PTP block update with the Time Stamp Addend register value */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; \r
+}\r
+\r
+/**\r
+ * @brief Enable the PTP Time Stamp interrupt trigger\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_EnablePTPTimeStampInterruptTrigger(void)\r
+{\r
+ /* Enable the PTP target time interrupt */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; \r
+}\r
+\r
+/**\r
+ * @brief Updated the PTP system time with the Time Stamp Update register value.\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_EnablePTPTimeStampUpdate(void)\r
+{\r
+ /* Enable the PTP system time update with the Time Stamp Update register value */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; \r
+}\r
+\r
+/**\r
+ * @brief Initialize the PTP Time Stamp\r
+ * @param None\r
+ * @retval None\r
+ */\r
+void ETH_InitializePTPTimeStamp(void)\r
+{\r
+ /* Initialize the PTP Time Stamp */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; \r
+}\r
+\r
+/**\r
+ * @brief Selects the PTP Update method\r
+ * @param UpdateMethod: the PTP Update method\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTP_FineUpdate : Fine Update method \r
+ * @arg ETH_PTP_CoarseUpdate : Coarse Update method \r
+ * @retval None\r
+ */\r
+void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_UPDATE(UpdateMethod));\r
+ \r
+ if (UpdateMethod != ETH_PTP_CoarseUpdate)\r
+ {\r
+ /* Enable the PTP Fine Update method */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PTP Coarse Update method */\r
+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU);\r
+ } \r
+}\r
+\r
+/**\r
+ * @brief Enables or disables the PTP time stamp for transmit and receive frames.\r
+ * @param NewState: new state of the PTP time stamp for transmit and receive frames\r
+ * This parameter can be: ENABLE or DISABLE.\r
+ * @retval None\r
+ */\r
+void ETH_PTPTimeStampCmd(FunctionalState NewState)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_FUNCTIONAL_STATE(NewState));\r
+ \r
+ if (NewState != DISABLE)\r
+ {\r
+ /* Enable the PTP time stamp for transmit and receive frames */\r
+ ETH->PTPTSCR |= ETH_PTPTSCR_TSE;\r
+ }\r
+ else\r
+ {\r
+ /* Disable the PTP time stamp for transmit and receive frames */\r
+ ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE);\r
+ }\r
+}\r
+\r
+/**\r
+ * @brief Checks whether the specified ETHERNET PTP flag is set or not.\r
+ * @param ETH_PTP_FLAG: specifies the flag to check.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTP_FLAG_TSARU : Addend Register Update \r
+ * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable \r
+ * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update \r
+ * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize \r
+ * @retval The new state of ETHERNET PTP Flag (SET or RESET).\r
+ */\r
+FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG)\r
+{\r
+ FlagStatus bitstatus = RESET;\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG));\r
+ \r
+ if ((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET)\r
+ {\r
+ bitstatus = SET;\r
+ }\r
+ else\r
+ {\r
+ bitstatus = RESET;\r
+ }\r
+ return bitstatus;\r
+}\r
+\r
+/**\r
+ * @brief Sets the system time Sub-Second Increment value.\r
+ * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue));\r
+ /* Set the PTP Sub-Second Increment Register */\r
+ ETH->PTPSSIR = SubSecondValue; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Time Stamp update sign and values.\r
+ * @param Sign: specifies the PTP Time update value sign.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTP_PositiveTime : positive time value. \r
+ * @arg ETH_PTP_NegativeTime : negative time value. \r
+ * @param SecondValue: specifies the PTP Time update second value. \r
+ * @param SubSecondValue: specifies the PTP Time update sub-second value.\r
+ * This parameter is a 31 bit value, bit32 correspond to the sign.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); \r
+ assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); \r
+ /* Set the PTP Time Update High Register */\r
+ ETH->PTPTSHUR = SecondValue;\r
+ \r
+ /* Set the PTP Time Update Low Register with sign */\r
+ ETH->PTPTSLUR = Sign | SubSecondValue; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Time Stamp Addend value.\r
+ * @param Value: specifies the PTP Time Stamp Addend Register value.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPTimeStampAddend(uint32_t Value)\r
+{\r
+ /* Set the PTP Time Stamp Addend Register */\r
+ ETH->PTPTSAR = Value; \r
+}\r
+\r
+/**\r
+ * @brief Sets the Target Time registers values.\r
+ * @param HighValue: specifies the PTP Target Time High Register value.\r
+ * @param LowValue: specifies the PTP Target Time Low Register value.\r
+ * @retval None\r
+ */\r
+void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue)\r
+{\r
+ /* Set the PTP Target Time High Register */\r
+ ETH->PTPTTHR = HighValue;\r
+ /* Set the PTP Target Time Low Register */\r
+ ETH->PTPTTLR = LowValue; \r
+}\r
+\r
+/**\r
+ * @brief Get the specified ETHERNET PTP register value.\r
+ * @param ETH_PTPReg: specifies the ETHERNET PTP register.\r
+ * This parameter can be one of the following values:\r
+ * @arg ETH_PTPTSCR : Sub-Second Increment Register \r
+ * @arg ETH_PTPSSIR : Sub-Second Increment Register \r
+ * @arg ETH_PTPTSHR : Time Stamp High Register\r
+ * @arg ETH_PTPTSLR : Time Stamp Low Register \r
+ * @arg ETH_PTPTSHUR : Time Stamp High Update Register \r
+ * @arg ETH_PTPTSLUR : Time Stamp Low Update Register\r
+ * @arg ETH_PTPTSAR : Time Stamp Addend Register\r
+ * @arg ETH_PTPTTHR : Target Time High Register \r
+ * @arg ETH_PTPTTLR : Target Time Low Register \r
+ * @retval The value of ETHERNET PTP Register value.\r
+ */\r
+uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg)\r
+{\r
+ /* Check the parameters */\r
+ assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg));\r
+ \r
+ /* Return the selected register value */\r
+ return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg));\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Tx descriptors in chain mode with PTP.\r
+ * @param DMATxDescTab: Pointer on the first Tx desc list \r
+ * @param DMAPTPTxDescTab: Pointer on the first PTP Tx desc list\r
+ * @param TxBuff: Pointer on the first TxBuffer list\r
+ * @param TxBuffCount: Number of the used Tx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab,\r
+ uint8_t* TxBuff, uint32_t TxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMATxDesc;\r
+ \r
+ /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */\r
+ DMATxDescToSet = DMATxDescTab;\r
+ DMAPTPTxDescToSet = DMAPTPTxDescTab;\r
+ /* Fill each DMATxDesc descriptor with the right values */ \r
+ for(i=0; i < TxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Tx Desc list */\r
+ DMATxDesc = DMATxDescTab+i;\r
+ /* Set Second Address Chained bit and enable PTP */\r
+ DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; \r
+ \r
+ /* Set Buffer1 address pointer */\r
+ DMATxDesc->Buffer1Addr =(uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (TxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);\r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; \r
+ }\r
+ /* make DMAPTPTxDescTab points to the same addresses as DMATxDescTab */\r
+ (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr;\r
+ (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr;\r
+ }\r
+ /* Store on the last DMAPTPTxDescTab desc status record the first list address */\r
+ (&DMAPTPTxDescTab[i-1])->Status = (uint32_t) DMAPTPTxDescTab;\r
+\r
+ /* Set Transmit Desciptor List Address Register */\r
+ ETH->DMATDLAR = (uint32_t) DMATxDescTab;\r
+}\r
+\r
+/**\r
+ * @brief Initializes the DMA Rx descriptors in chain mode.\r
+ * @param DMARxDescTab: Pointer on the first Rx desc list \r
+ * @param DMAPTPRxDescTab: Pointer on the first PTP Rx desc list\r
+ * @param RxBuff: Pointer on the first RxBuffer list\r
+ * @param RxBuffCount: Number of the used Rx desc in the list\r
+ * @retval None\r
+ */\r
+void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab,\r
+ uint8_t *RxBuff, uint32_t RxBuffCount)\r
+{\r
+ uint32_t i = 0;\r
+ ETH_DMADESCTypeDef *DMARxDesc;\r
+ \r
+ /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */\r
+ DMARxDescToGet = DMARxDescTab; \r
+ DMAPTPRxDescToGet = DMAPTPRxDescTab;\r
+ /* Fill each DMARxDesc descriptor with the right values */\r
+ for(i=0; i < RxBuffCount; i++)\r
+ {\r
+ /* Get the pointer on the ith member of the Rx Desc list */\r
+ DMARxDesc = DMARxDescTab+i;\r
+ /* Set Own bit of the Rx descriptor Status */\r
+ DMARxDesc->Status = ETH_DMARxDesc_OWN;\r
+\r
+ /* Set Buffer1 size and Second Address Chained bit */\r
+ DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; \r
+ /* Set Buffer1 address pointer */\r
+ DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]);\r
+ \r
+ /* Initialize the next descriptor with the Next Desciptor Polling Enable */\r
+ if(i < (RxBuffCount-1))\r
+ {\r
+ /* Set next descriptor address register with next descriptor base address */\r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); \r
+ }\r
+ else\r
+ {\r
+ /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ \r
+ DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); \r
+ }\r
+ /* Make DMAPTPRxDescTab points to the same addresses as DMARxDescTab */\r
+ (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr;\r
+ (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr;\r
+ }\r
+ /* Store on the last DMAPTPRxDescTab desc status record the first list address */\r
+ (&DMAPTPRxDescTab[i-1])->Status = (uint32_t) DMAPTPRxDescTab;\r
+\r
+ /* Set Receive Desciptor List Address Register */\r
+ ETH->DMARDLAR = (uint32_t) DMARxDescTab; \r
+}\r
+\r
+/**\r
+ * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values.\r
+ * @param ppkt: pointer to application packet buffer to transmit.\r
+ * @param FrameLength: Tx Packet size.\r
+ * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values.\r
+ * @retval ETH_ERROR: in case of Tx desc owned by DMA\r
+ * ETH_SUCCESS: for correct transmission\r
+ */\r
+uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab)\r
+{\r
+ uint32_t offset = 0, timeout = 0;\r
+ /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return ERROR: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ \r
+ for(offset=0; offset<FrameLength; offset++)\r
+ {\r
+ (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));\r
+ }\r
+ /* Setting the Frame Length: bits[12:0] */\r
+ DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF);\r
+ /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ \r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;\r
+ /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;\r
+ /* When Tx Buffer unavailable flag is set: clear it and resume transmission */\r
+ if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear TBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_TBUS;\r
+ /* Resume DMA transmission*/\r
+ ETH->DMATPDR = 0;\r
+ }\r
+ /* Wait for ETH_DMATxDesc_TTSS flag to be set */\r
+ do\r
+ {\r
+ timeout++;\r
+ } while (!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF));\r
+ /* Return ERROR in case of timeout */\r
+ if(timeout == PHY_READ_TO)\r
+ {\r
+ return ETH_ERROR;\r
+ }\r
+ /* Clear the DMATxDescToSet status register TTSS flag */\r
+ DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS;\r
+ *PTPTxTab++ = DMATxDescToSet->Buffer1Addr;\r
+ *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr;\r
+ /* Update the ENET DMA current descriptor */\r
+ /* Chained Mode */\r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)\r
+ { \r
+ /* Selects the next DMA Tx descriptor list for next buffer read */ \r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr);\r
+ if(DMAPTPTxDescToSet->Status != 0)\r
+ { \r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Status);\r
+ }\r
+ else\r
+ {\r
+ DMAPTPTxDescToSet++;\r
+ }\r
+ }\r
+ else /* Ring Mode */\r
+ { \r
+ if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Tx descriptor list for next buffer read: this will\r
+ be the first Tx descriptor in this case */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); \r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Tx descriptor list for next buffer read */\r
+ DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ /* Return SUCCESS */\r
+ return ETH_SUCCESS;\r
+}\r
+\r
+/**\r
+ * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values.\r
+ * @param ppkt: pointer to application packet receive buffer. \r
+ * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values.\r
+ * @retval ETH_ERROR: if there is error in reception\r
+ * framelength: received packet size if packet reception is correct\r
+ */\r
+uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab)\r
+{\r
+ uint32_t offset = 0, framelength = 0;\r
+ /* Check if the descriptor is owned by the ENET or CPU */\r
+ if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)\r
+ {\r
+ /* Return error: OWN bit set */\r
+ return ETH_ERROR;\r
+ }\r
+ if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&\r
+ ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))\r
+ {\r
+ /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */\r
+ framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4;\r
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ \r
+ for(offset=0; offset<framelength; offset++)\r
+ {\r
+ (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Return ERROR */\r
+ framelength = ETH_ERROR;\r
+ }\r
+ /* When Rx Buffer unavailable flag is set: clear it and resume reception */\r
+ if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)\r
+ {\r
+ /* Clear RBUS ETHERNET DMA flag */\r
+ ETH->DMASR = ETH_DMASR_RBUS;\r
+ /* Resume DMA reception */\r
+ ETH->DMARPDR = 0;\r
+ }\r
+ *PTPRxTab++ = DMARxDescToGet->Buffer1Addr;\r
+ *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr;\r
+ /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */\r
+ DMARxDescToGet->Status |= ETH_DMARxDesc_OWN;\r
+ /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */\r
+ /* Chained Mode */\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr);\r
+ if(DMAPTPRxDescToGet->Status != 0)\r
+ {\r
+ DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Status);\r
+ }\r
+ else\r
+ {\r
+ DMAPTPRxDescToGet++;\r
+ }\r
+ }\r
+ else /* Ring Mode */\r
+ {\r
+ if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)\r
+ {\r
+ /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);\r
+ }\r
+ else\r
+ {\r
+ /* Selects the next DMA Rx descriptor list for next buffer to read */\r
+ DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); \r
+ }\r
+ }\r
+ /* Return Frame Length/ERROR */\r
+ return (framelength);\r
+}\r
+\r
+#ifndef USE_Delay\r
+/**\r
+ * @brief Inserts a delay time.\r
+ * @param nCount: specifies the delay time length.\r
+ * @retval None\r
+ */\r
+static void ETH_Delay(__IO uint32_t nCount)\r
+{\r
+ __IO uint32_t index = 0; \r
+ for(index = nCount; index != 0; index--)\r
+ {\r
+ }\r
+}\r
+#endif /* USE_Delay*/\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
#include "internal.h"\r
#include "stack.h"\r
#include "stm32f10x.h"\r
-#include "core_cm3.h"\r
\r
\r
/**\r
\r
-#\r
-# Copyright ArcCore AB\r
-#\r
+/*\r
+ * Copyright ArcCore AB\r
+ *\r
+ *\r
+ */\r
\r
#define _ASSEMBLER_\r
#include "kernel_offset.h"\r
#include "stack.h"\r
\r
.extern os_sys\r
+.extern TailChaining\r
\r
.syntax unified\r
.cpu cortex-m3\r
\r
.global Irq_Handler\r
.type Irq_Handler, %function\r
+ .global SVC_Handler\r
+ .type SVC_Handler, %function\r
+ .global PendSV_Handler\r
+ .type PendSV_Handler, %function\r
\r
#define IRQ_ENABLE() cpsie i\r
#define IRQ_DISABLE() cpsid i\r
// lr\r
#define REG_SAVE r4-r8,r10,r11\r
\r
+SVC_Handler: \r
+ add sp,sp,#(8*4) /* remove one interrupt frame from the stack */\r
+ bx lr /* return to the preempted task */\r
\r
-Irq_Handler:\r
+PendSV_Handler:\r
+ IRQ_DISABLE()\r
+ push {REG_SAVE,lr}\r
+ sub.w sp,sp,#C_SIZE\r
+ mov.w r4,#LC_PATTERN\r
+ str r4,[sp,#C_CONTEXT_OFFS] \r
+ mov r2,sp // stack as first arg\r
+\r
+ mov r1,#0x01000000 // make up a task xPSR that has only the T bit set \r
+ ldr r0,=TailChaining // load the address of scheduler wrapper (new PC) \r
+ push {r0-r1} // push xPSR,PC \r
+ sub sp,sp,#(5*4) // don't care for lr,r12,r3,r2,r1\r
+ push {r2} // stack as first arg\r
+ bx lr // interrupt return to the scheduler wrapper\r
+ \r
+Irq_Handler: \r
push {REG_SAVE,lr}\r
sub.w sp,sp,#C_SIZE\r
mov.w r4,#LC_PATTERN\r
str r4,[sp,#C_CONTEXT_OFFS] \r
mov r0,sp // stack as first arg\r
+\r
+ // When at interrupt nest count = 0, load interrupt stack \r
+ ldr r4,=os_sys\r
+ ldr r5,[r4,#SYS_INT_NEST_CNT]\r
+ cmp r5, #0\r
+ bgt arggg \r
+ ldr sp,[r4,#SYS_INT_STACK] \r
+arggg: \r
bl Irq_Entry\r
mov sp, r0 // pop from returned stack\r
- b os_lc_restore\r
- \r
+\r
+ /* Do a normal exception return */\r
+ add.w sp,sp,#C_SIZE\r
+ pop {REG_SAVE,lr}\r
+ bx lr \r
\r
/**\r
* Fake an interrupt stack to be able to return to thread mode.\r
*\r
* Don't really know what bits matter on the xPSR here. Not setting\r
* the EPSR[T] is really bad since it will generate a INVSTATE exception.\r
- *\r
- * @param r0 Pointer to PC to set\r
*/\r
.global Irq_EOI2\r
.type Irq_EOI2, %function\r
\r
Irq_EOI2:\r
mov.w r1,0x01000000 /* EPSR[T] bit */\r
+ mov r0,lr\r
push {r0,r1} /* Push PC and xPSR */\r
sub.w sp,sp,#(6*4) /* r0,r1,r2,r3, r12,lr,pc,xPSR */\r
- mov.w lr,#0xfffffff9 /* Return with MSR */\r
- bx lr\r
+ mov.w lr,#0xfffffff9 /* interrupt return with stack=MSR */\r
+ bx lr /* do return */\r
\r
\r
/**\r
*/\r
os_sc_restore:\r
add.w sp,sp,#C_SIZE\r
-\r
pop {REG_SAVE,lr}\r
bx lr\r
\r
\r
- /* Restore the large context. Cases:\r
- * - Directly from Irq_Handler()\r
- * (the preempted task got swapped in directly)\r
- * - The preempted task, got preemted by a task and\r
- * we have already returned from handler mode.\r
- */\r
-\r
+/* Restore the large context. Cases:\r
+ * 1. Directly from Irq_Handler()\r
+ * (the preempted task got swapped in directly)\r
+ * 2. The preempted task, got preemted by a task and\r
+ * we have already returned from handler mode.\r
+ *\r
+ * NOTE ! Only case 2 is covered here, case 1 is handled in Irq_Handler\r
+ * prologue\r
+ */\r
+ \r
os_lc_restore:\r
add.w sp,sp,#C_SIZE\r
+ /* Pop function stack (LR will be 0xffff_fff9 here, just ignore */\r
pop {REG_SAVE,lr}\r
- \r
- /* The usual case is that we are in handler mode (=handling exceptions).\r
- * So, LR(=r14) should be 0xffff_fffx, and x in this case should return \r
- * to threaded mode (=not handling exeptions) 0b1001. (EXC_RETURN)\r
- */\r
- bx lr\r
+ IRQ_ENABLE() /* Enable interrupts to allow svc */\r
+ svc 0 /* cause exception to return to the preempted task */\r
\r
\r
+ \r
\r
#ifndef __CM3_CORE_H__\r
#define __CM3_CORE_H__\r
\r
+\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif \r
*/\r
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
+ uint32_t prio = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);\r
+\r
if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = prio; } /* set Priority for Cortex-M3 System Interrupts */\r
else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ NVIC->IP[(uint32_t)(IRQn)] = prio; } /* set Priority for device specific Interrupts */\r
}\r
\r
/**\r
if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */\r
\r
SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ //NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
SysTick->VAL = (0x00); /* Load the SysTick Counter Value */\r
SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */\r
return (0); /* Function successful */\r
return (ch);\r
}\r
\r
+/* --- Arctic Core --- */\r
+\r
+static inline unsigned long _Irq_Save(void)\r
+{\r
+ unsigned long val = __get_PRIMASK();\r
+ __disable_irq();\r
+ return val;\r
+}\r
+\r
+\r
+static inline void _Irq_Restore(unsigned mask) {\r
+ __set_PRIMASK(mask);\r
+}\r
+\r
+\r
+\r
#ifdef __cplusplus\r
}\r
#endif\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#include "internal.h"\r
-#include "task_i.h"\r
-#include "hooks.h"\r
-#include "stm32f10x.h"\r
-#include "misc.h"\r
-#include "irq.h"\r
-#include "core_cm3.h"\r
-\r
-extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
-\r
-void Irq_Init( void ) {\r
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);\r
-}\r
-\r
-void Irq_EOI( void ) {\r
- /* Note!\r
- * This is not applicable on the Cortex-M3 since we\r
- * can't terminate the interrupt request without popping\r
- * back registers..have to be solved in the context switches\r
- * themselves.\r
- */\r
-}\r
-\r
-#define ICSR_VECTACTIVE 0x1ff\r
-\r
-/**\r
- * Get Active ISR number field.\r
- * You can subtract 16 from the VECTACTIVE field to index into the Interrupt\r
- * Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority\r
- * Registers. INTISR[0] has vector number 16.\r
- *\r
- */\r
-static uint32_t NVIC_GetActiveVector( void) {\r
- return (SCB->ICSR & ICSR_VECTACTIVE);\r
-}\r
-\r
-/**\r
- *\r
- * @param stack_p Ptr to the current stack.\r
- *\r
- * The stack holds C, NVGPR, VGPR and the EXC frame.\r
- *\r
- */\r
-void *Irq_Entry( void *stack_p )\r
-{\r
- uint32_t vector = 0;\r
- uint32_t *stack;\r
-\r
- Irq_Disable();\r
- stack = (uint32_t *)stack_p;\r
-\r
- /* 0. Set the default handler here....\r
- * 1. Grab the vector from the interrupt controller\r
- * INT_CTRL_ST[VECTACTIVE]\r
- * 2. Irq_VectorTable[vector] is odd -> ISR1\r
- * Irq_VectorTable[vector] is even-> ISR2\r
- */\r
-\r
-\r
- vector = NVIC_GetActiveVector();\r
-\r
- stack = Os_Isr(stack, (void *)Irq_VectorTable[vector]);\r
- Irq_Enable();\r
- return stack;\r
-}\r
-\r
-/**\r
- * Attach an ISR type 1 to the interrupt controller.\r
- *\r
- * @param entry\r
- * @param int_ctrl\r
- * @param vector\r
- * @param prio\r
- */\r
-void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {\r
-\r
- // TODO: Use NVIC_Init here\r
- /*\r
- NVIC_InitTypeDef NVIC_InitStructure;\r
-\r
- // Enable and configure RCC global IRQ channel\r
- NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;\r
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
- NVIC_Init(&NVIC_InitStructure);\r
- */\r
-}\r
-\r
-static inline int osPrioToCpuPio( uint8_t prio ) {\r
- assert(prio<32);\r
- return prio>>1;\r
-}\r
-\r
-\r
-/**\r
- * Attach a ISR type 2 to the interrupt controller.\r
- *\r
- * @param tid\r
- * @param int_ctrl\r
- * @param vector\r
- */\r
-void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {\r
- OsPcbType *pcb;\r
- NVIC_InitTypeDef irqInit;\r
-\r
- pcb = os_find_task(tid);\r
- Irq_VectorTable[vector+16] = (void *)pcb;\r
-\r
- irqInit.NVIC_IRQChannel = vector;\r
- irqInit.NVIC_IRQChannelPreemptionPriority = osPrioToCpuPio(pcb->prio);\r
- irqInit.NVIC_IRQChannelSubPriority = 0;\r
- irqInit.NVIC_IRQChannelCmd = ENABLE;\r
-\r
-\r
- // TODO: Same as for AttachIsr1\r
- NVIC_Init(&irqInit);\r
-}\r
-\r
-\r
-/**\r
- * Generates a soft interrupt, ie sets pending bit.\r
- * This could also be implemented using ISPR regs.\r
- *\r
- * @param vector\r
- */\r
-void Irq_GenerateSoftInt( IrqType vector ) {\r
-\r
- NVIC->STIR = (vector + 16);\r
-}\r
-\r
-/**\r
- * Get the current priority from the interrupt controller.\r
- * @param cpu\r
- * @return\r
- */\r
-uint8_t Irq_GetCurrentPriority( Cpu_t cpu) {\r
-\r
- uint8_t prio = 0;\r
-\r
- // SCB_ICSR contains the active vector\r
- return prio;\r
-}\r
-\r
-typedef struct {\r
- uint32_t dummy;\r
-} exc_stack_t;\r
-\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include "internal.h"
+#include "task_i.h"
+#include "hooks.h"
+#include "stm32f10x.h"
+#include "irq.h"
+
+extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+
+/**
+ * Init NVIC vector. We do not use subpriority
+ *
+ * @param vector The IRQ number
+ * @param prio NVIC priority, 0-31, 0-high prio
+ */
+static void NVIC_InitVector(IRQn_Type vector, uint32_t prio)
+{
+ // Set prio
+ NVIC_SetPriority(vector,prio);
+
+ // Enable
+ NVIC->ISER[vector >> 5] = (uint32_t)1 << (vector & (uint8_t)0x1F);
+}
+
+/*
+PRIGROUP
+0 7.1 indicates seven bits of pre-emption priority, one bit of subpriority
+1 6.2 indicates six bits of pre-emption priority, two bits of subpriority
+2 5.3 indicates five bits of pre-emption priority, three bits of subpriority
+3 4.4 indicates four bits of pre-emption priority, four bits of subpriority
+4 3.5 indicates three bits of pre-emption priority, five bits of subpriority
+5 2.6 indicates two bits of pre-emption priority, six bits of subpriority
+6 1.7 indicates one bit of pre-emption priority, seven bits of subpriority
+7 0.8 indicates no pre-emption priority, eight bits of subpriority.
+*/
+void Irq_Init( void ) {
+ NVIC_SetPriorityGrouping(0);
+ NVIC_SetPriority(SVCall_IRQn, 0xff); // Set lowest prio
+ NVIC_SetPriority(PendSV_IRQn, 0xff); // Set lowest prio
+
+ /* Stop counters and watchdogs when halting in debug */
+ DBGMCU->CR |= 0x00ffffff00;
+}
+
+void Irq_EOI( void ) {
+ /* Note!
+ * This is not applicable on the Cortex-M3 since we
+ * can't terminate the interrupt request without popping
+ * back registers..have to be solved in the context switches
+ * themselves.
+ */
+}
+
+#define ICSR_VECTACTIVE 0x1ff
+
+/**
+ * Get Active ISR number field.
+ * You can subtract 16 from the VECTACTIVE field to index into the Interrupt
+ * Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority
+ * Registers. INTISR[0] has vector number 16.
+ *
+ */
+static uint32_t NVIC_GetActiveVector( void) {
+ return (SCB->ICSR & ICSR_VECTACTIVE);
+}
+
+
+/**
+ *
+ * @param stack_p Ptr to the current stack.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+void *Irq_Entry( void *stack_p ){
+ uint32_t vector = 0;
+
+ Irq_Disable();
+
+ /* 0. Set the default handler here....
+ * 1. Grab the vector from the interrupt controller
+ * INT_CTRL_ST[VECTACTIVE]
+ * 2. Irq_VectorTable[vector] is odd -> ISR1
+ * Irq_VectorTable[vector] is even-> ISR2
+ */
+
+
+ vector = NVIC_GetActiveVector();
+
+ Os_Isr_cm3((void *)Irq_VectorTable[vector]);
+ Irq_Enable();
+
+ return stack_p;
+}
+
+/**
+ * Attach an ISR type 1 to the interrupt controller.
+ *
+ * @param entry
+ * @param int_ctrl
+ * @param vector
+ * @param prio
+ */
+void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
+
+ // TODO: Use NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio)); here
+}
+
+/**
+ * NVIC prio have priority 0-31, 0-highest priority.
+ * Autosar does it the other way around, 0-Lowest priority
+ * NOTE: prio 255 is reserved for SVC and PendSV
+ *
+ * Autosar NVIC
+ * 31 0
+ * 30 1
+ * ..
+ * 0 31
+ * @param prio
+ * @return
+ */
+static inline int osPrioToCpuPio( uint8_t prio ) {
+ assert(prio<32);
+ prio = 31 - prio;
+ return prio;
+}
+
+/**
+ * Attach a ISR type 2 to the interrupt controller.
+ *
+ * @param tid
+ * @param int_ctrl
+ * @param vector
+ */
+void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {
+ OsPcbType *pcb;
+
+ pcb = os_find_task(tid);
+ Irq_VectorTable[vector+16] = (void *)pcb;
+
+ NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio));
+}
+
+
+/**
+ * Generates a soft interrupt, ie sets pending bit.
+ * This could also be implemented using ISPR regs.
+ *
+ * @param vector
+ */
+void Irq_GenerateSoftInt( IrqType vector ) {
+
+ NVIC->STIR = (vector);
+}
+
+/**
+ * Get the current priority from the interrupt controller.
+ * @param cpu
+ * @return
+ */
+uint8_t Irq_GetCurrentPriority( Cpu_t cpu) {
+
+ uint8_t prio = 0;
+
+ // SCB_ICSR contains the active vector
+ return prio;
+}
+
+typedef struct {
+ uint32_t dummy;
+} exc_stack_t;
+
+
*/\r
#define IRQ_INTERRUPT_OFFSET 16\r
\r
+#define Irq_SOI()\r
+\r
/* Total number of interrupts and exceptions\r
*/\r
\r
#error No device selected\r
#endif\r
\r
+\r
+typedef enum {\r
+ PERIPHERAL_CLOCK_AHB,\r
+ PERIPHERAL_CLOCK_APB1,\r
+ PERIPHERAL_CLOCK_APB2,\r
+} McuE_PeriperalClock_t;\r
+\r
+\r
typedef enum {\r
CPU_0=0,\r
} Cpu_t;\r
*\r
* Misc\r
* r9 - Platform specific ???\r
- * r12 - IP\r
+ * r12 - IP (Intra Procedure call)\r
* r13 - SP\r
* r14 - LR\r
* r15 - PC\r
*\r
+ * See "Procedure Call Standard for the ARM® Architecture" for more information.\r
+ *\r
* Other:\r
* PSR\r
* PRIMASK[0] 0 - No effect,\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+ \r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+.word _sidata\r
+.word _sdata\r
+.word _edata\r
+.word _sbss\r
+.word _ebss\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+\r
+/* Copy the data segment initializers from flash to SRAM */\r
+ ldr r0, =_sdata /* r0 holds start of data in ram */\r
+ ldr r3, =_edata /* r3 holds end of data in ram */\r
+ ldr r5, =_sidata /* r5 start of data in flash */\r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r4, [r5, r1] /* read current position in flash */\r
+ str r4, [r0, r1] /* store current position in ram */\r
+ adds r1, r1, #4 /* increment counter */\r
+ \r
+LoopCopyDataInit:\r
+ adds r2, r0, r1 /* are we at the final position? */\r
+ cmp r2, r3 /* ... */\r
+ bcc CopyDataInit /* nope, continue */\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+* Vector table for a Cortex M3. Vectors start at addr 0x0.\r
+******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+\r
+ .extern Irq_Handler\r
+ .extern SVC_Handler\r
+ .extern PendSV_Handler\r
+\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word Irq_Handler+1 /* SysTick */\r
+ .rept 83\r
+ .word Irq_Handler+1\r
+ .endr\r
+ \r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+\r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+\r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+\r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_cl.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR \r
- * address.\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF1E0F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
-#if 1\r
-\r
- .extern Irq_Handler\r
-\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word Irq_Handler+1 /* SysTick */\r
- .rept 83\r
- .word Irq_Handler+1\r
- .endr\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-#else\r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word CAN1_TX_IRQHandler\r
- .word CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word OTG_FS_WKUP_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word TIM5_IRQHandler \r
- .word SPI3_IRQHandler \r
- .word UART4_IRQHandler \r
- .word UART5_IRQHandler \r
- .word TIM6_IRQHandler \r
- .word TIM7_IRQHandler \r
- .word DMA2_Channel1_IRQHandler \r
- .word DMA2_Channel2_IRQHandler \r
- .word DMA2_Channel3_IRQHandler \r
- .word DMA2_Channel4_IRQHandler \r
- .word DMA2_Channel5_IRQHandler \r
- .word ETH_IRQHandler \r
- .word ETH_WKUP_IRQHandler \r
- .word CAN2_TX_IRQHandler \r
- .word CAN2_RX0_IRQHandler \r
- .word CAN2_RX1_IRQHandler \r
- .word CAN2_SCE_IRQHandler \r
- .word OTG_FS_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
- STM32F10x Connectivity line Devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_TX_IRQHandler\r
- .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX0_IRQHandler\r
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak OTG_FS_WKUP_IRQHandler\r
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak TIM5_IRQHandler\r
- .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
- .weak SPI3_IRQHandler \r
- .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
- .weak UART4_IRQHandler \r
- .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
- .weak UART5_IRQHandler \r
- .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler \r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler \r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel1_IRQHandler \r
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel2_IRQHandler \r
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel3_IRQHandler \r
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel4_IRQHandler \r
- .thumb_set DMA2_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel5_IRQHandler \r
- .thumb_set DMA2_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak ETH_IRQHandler \r
- .thumb_set ETH_IRQHandler,Default_Handler\r
-\r
- .weak ETH_WKUP_IRQHandler \r
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_TX_IRQHandler \r
- .thumb_set CAN2_TX_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_RX0_IRQHandler \r
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_RX1_IRQHandler \r
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_SCE_IRQHandler \r
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r
-\r
- .weak OTG_FS_IRQHandler \r
- .thumb_set OTG_FS_IRQHandler ,Default_Handler\r
-#endif\r
- \r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_hd.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. \r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address,\r
- * - Configure external SRAM mounted on STM3210E-EVAL board\r
- * to be used as data memory (optional, to be enabled by user)\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r
-\r
-.equ Initial_spTop, 0x20000400 \r
-.equ BootRAM, 0xF1E0F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
- required, then adjust the Register Addresses */\r
- bl SystemInit_ExtMemCtl\r
-/* restore original stack pointer */ \r
- LDR r0, =_estack\r
- MSR msp, r0\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief Dummy SystemInit_ExtMemCtl function \r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits\r
-SystemInit_ExtMemCtl_Dummy:\r
- bx lr\r
- .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word Initial_spTop\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler\r
- .word TIM8_BRK_IRQHandler\r
- .word TIM8_UP_IRQHandler\r
- .word TIM8_TRG_COM_IRQHandler\r
- .word TIM8_CC_IRQHandler\r
- .word ADC3_IRQHandler\r
- .word FSMC_IRQHandler\r
- .word SDIO_IRQHandler\r
- .word TIM5_IRQHandler\r
- .word SPI3_IRQHandler\r
- .word UART4_IRQHandler\r
- .word UART5_IRQHandler\r
- .word TIM6_IRQHandler\r
- .word TIM7_IRQHandler\r
- .word DMA2_Channel1_IRQHandler\r
- .word DMA2_Channel2_IRQHandler\r
- .word DMA2_Channel3_IRQHandler\r
- .word DMA2_Channel4_5_IRQHandler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
- STM32F10x High Density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_BRK_IRQHandler\r
- .thumb_set TIM8_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_UP_IRQHandler\r
- .thumb_set TIM8_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_TRG_COM_IRQHandler\r
- .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_CC_IRQHandler\r
- .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
-\r
- .weak ADC3_IRQHandler\r
- .thumb_set ADC3_IRQHandler,Default_Handler\r
-\r
- .weak FSMC_IRQHandler\r
- .thumb_set FSMC_IRQHandler,Default_Handler\r
-\r
- .weak SDIO_IRQHandler\r
- .thumb_set SDIO_IRQHandler,Default_Handler\r
-\r
- .weak TIM5_IRQHandler\r
- .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
- .weak SPI3_IRQHandler\r
- .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
- .weak UART4_IRQHandler\r
- .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
- .weak UART5_IRQHandler\r
- .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler\r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler\r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel1_IRQHandler\r
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel2_IRQHandler\r
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel3_IRQHandler\r
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel4_5_IRQHandler\r
- .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler\r
-\r
- .weak SystemInit_ExtMemCtl\r
- .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_ld.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address.\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- 0\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- 0\r
- 0\r
- .word SPI1_IRQHandler\r
- 0\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- 0\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32F10x Low Density devices.*/\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler \r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_md.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
-#if 1\r
-\r
- .extern Irq_Handler\r
-\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word Irq_Handler+1 /* SysTick */\r
- .rept 83\r
- .word Irq_Handler+1\r
- .endr\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
-\r
-#else\r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32F10x Medium Density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
-\r
-#endif\r
-\r
/**\r
******************************************************************************\r
* @file stm32f10x.h\r
* @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
+ * @version V3.4.0\r
+ * @date 10/15/2010\r
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \r
* This file contains all the peripheral register's definitions, bits \r
- * definitions and memory mapping for STM32F10x Connectivity line, High\r
- * density, Medium density and Low density devices.\r
+ * definitions and memory mapping for STM32F10x Connectivity line, \r
+ * High density, High density value line, Medium density, \r
+ * Medium density Value line, Low density, Low density Value line \r
+ * and XL-density devices.\r
****************************************************************************** \r
*\r
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
*\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
+ * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>\r
******************************************************************************\r
*/\r
\r
application \r
*/\r
\r
-#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)\r
- /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */\r
- #define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */\r
- /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */\r
- /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) \r
+ /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */\r
+ /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ \r
+ /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */\r
+ /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ \r
+ /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */\r
+ /* #define STM32F10X_HD_VL */ /*!< STM32F10X_HD_VL: STM32 High density value line devices */ \r
+ /* #define STM32F10X_XL */ /*!< STM32F10X_XL: STM32 XL-density devices */\r
+ /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */\r
#endif\r
/* Tip: To avoid modifying this file each time you need to switch between these\r
devices, you can define the device in your toolchain compiler preprocessor.\r
\r
- - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
+ - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
where the Flash memory density ranges between 16 and 32 Kbytes.\r
- - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
+ - Low-density value line devices are STM32F100xx microcontrollers where the Flash\r
+ memory density ranges between 16 and 32 Kbytes.\r
+ - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers\r
where the Flash memory density ranges between 64 and 128 Kbytes.\r
- - High density devices are STM32F101xx and STM32F103xx microcontrollers where\r
+ - Medium-density value line devices are STM32F100xx microcontrollers where the \r
+ Flash memory density ranges between 64 and 128 Kbytes. \r
+ - High-density devices are STM32F101xx and STM32F103xx microcontrollers where\r
the Flash memory density ranges between 256 and 512 Kbytes.\r
+ - High-density value line devices are STM32F100xx microcontrollers where the \r
+ Flash memory density ranges between 256 and 512 Kbytes. \r
+ - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where\r
+ the Flash memory density ranges between 512 and 1024 Kbytes.\r
- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.\r
*/\r
\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)\r
+ #error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"\r
+#endif\r
+\r
#if !defined USE_STDPERIPH_DRIVER\r
/**\r
* @brief Comment the line below if you will not use the peripherals drivers.\r
Tip: To avoid modifying this file each time you need to use different HSE, you\r
can define the HSE value in your toolchain compiler preprocessor.\r
*/ \r
-#if !defined HSE_Value\r
+#if !defined HSE_VALUE\r
#ifdef STM32F10X_CL \r
- #define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
#else \r
- #define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */\r
#endif /* STM32F10X_CL */\r
-#endif /* HSE_Value */\r
+#endif /* HSE_VALUE */\r
\r
\r
/**\r
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
Timeout value \r
*/\r
-#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */\r
\r
-#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\r
+#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/\r
\r
/**\r
* @brief STM32F10x Standard Peripheral Library version number\r
*/\r
#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */\r
-#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */\r
+#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x04) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */\r
#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */\r
#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\\r
| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\\r
/**\r
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals \r
*/\r
-#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */\r
-#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */\r
+#ifdef STM32F10X_XL\r
+ #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */\r
+#else\r
+ #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */\r
+#endif /* STM32F10X_XL */\r
+/* NOTE We use 7 bits preemption since 8 bits premtion isn't configurable */\r
+#define __NVIC_PRIO_BITS 7 /*!< STM32 uses 7 Bits for the Priority Levels */\r
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
\r
/**\r
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */\r
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */\r
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */\r
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
\r
#ifdef STM32F10X_LD\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
#endif /* STM32F10X_LD */ \r
\r
+#ifdef STM32F10X_LD_VL\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */ \r
+#endif /* STM32F10X_LD_VL */\r
+\r
#ifdef STM32F10X_MD\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
+ USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ \r
#endif /* STM32F10X_MD */ \r
\r
+#ifdef STM32F10X_MD_VL\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
+ TIM7_IRQn = 55 /*!< TIM7 Interrupt */ \r
+#endif /* STM32F10X_MD_VL */\r
+\r
#ifdef STM32F10X_HD\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
#endif /* STM32F10X_HD */ \r
\r
+#ifdef STM32F10X_HD_VL\r
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */\r
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */\r
+ TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */\r
+ TIM12_IRQn = 43, /*!< TIM12 global Interrupt */\r
+ TIM13_IRQn = 44, /*!< TIM13 global Interrupt */\r
+ TIM14_IRQn = 45, /*!< TIM14 global Interrupt */\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */ \r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 Interrupt */ \r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_5_IRQn = 59, /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
+ DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is \r
+ mapped at postion 60 only if the MISC_REMAP bit in \r
+ the AFIO_MAPR2 register is set) */ \r
+#endif /* STM32F10X_HD_VL */\r
+\r
+#ifdef STM32F10X_XL\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
+ USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
+ USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */\r
+ USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ ADC3_IRQn = 47, /*!< ADC3 global Interrupt */\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_IRQn = 54, /*!< TIM6 global Interrupt */\r
+ TIM7_IRQn = 55, /*!< TIM7 global Interrupt */\r
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */\r
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */\r
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */\r
+ DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */\r
+#endif /* STM32F10X_XL */ \r
+\r
#ifdef STM32F10X_CL\r
+ ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */\r
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */\r
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */\r
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
*/\r
\r
#include "core_cm3.h"\r
-#include "system_stm32f10x.h"\r
+//#include "system_stm32f10x.h"\r
#include <stdint.h>\r
\r
/** @addtogroup Exported_types\r
typedef __I uint16_t vuc16; /*!< Read Only */\r
typedef __I uint8_t vuc8; /*!< Read Only */\r
\r
-#if !defined(FALSE)\r
-#ifndef __cplusplus\r
-typedef enum {FALSE = 0, TRUE = !FALSE} bool;\r
-#endif\r
-#endif\r
-\r
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
\r
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
\r
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
\r
+/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */\r
+#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT\r
+#define HSE_Value HSE_VALUE\r
+#define HSI_Value HSI_VALUE\r
/**\r
* @}\r
*/\r
__IO uint16_t DR42;\r
uint16_t RESERVED45; \r
} BKP_TypeDef;\r
-\r
+ \r
/** \r
* @brief Controller Area Network TxMailBox \r
*/\r
#endif /* STM32F10X_CL */ \r
} CAN_TypeDef;\r
\r
+/** \r
+ * @brief Consumer Electronics Control (CEC)\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CFGR;\r
+ __IO uint32_t OAR;\r
+ __IO uint32_t PRES;\r
+ __IO uint32_t ESR;\r
+ __IO uint32_t CSR;\r
+ __IO uint32_t TXD;\r
+ __IO uint32_t RXD; \r
+} CEC_TypeDef;\r
+\r
/** \r
* @brief CRC calculation unit \r
*/\r
__IO uint32_t DHR8RD;\r
__IO uint32_t DOR1;\r
__IO uint32_t DOR2;\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ __IO uint32_t SR;\r
+#endif\r
} DAC_TypeDef;\r
\r
/** \r
__IO uint32_t RESERVED;\r
__IO uint32_t OBR;\r
__IO uint32_t WRPR;\r
+#ifdef STM32F10X_XL\r
+ uint32_t RESERVED1[8]; \r
+ __IO uint32_t KEYR2;\r
+ uint32_t RESERVED2; \r
+ __IO uint32_t SR2;\r
+ __IO uint32_t CR2;\r
+ __IO uint32_t AR2; \r
+#endif /* STM32F10X_XL */ \r
} FLASH_TypeDef;\r
\r
/** \r
__IO uint32_t EVCR;\r
__IO uint32_t MAPR;\r
__IO uint32_t EXTICR[4];\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t MAPR2; \r
} AFIO_TypeDef;\r
/** \r
* @brief Inter-integrated Circuit Interface\r
__IO uint32_t APB1ENR;\r
__IO uint32_t BDCR;\r
__IO uint32_t CSR;\r
+\r
#ifdef STM32F10X_CL \r
__IO uint32_t AHBRSTR;\r
__IO uint32_t CFGR2;\r
#endif /* STM32F10X_CL */ \r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) \r
+ uint32_t RESERVED0;\r
+ __IO uint32_t CFGR2;\r
+#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL || STM32F10X_HD_VL */ \r
} RCC_TypeDef;\r
\r
/** \r
* @{\r
*/\r
\r
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */\r
-#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */\r
\r
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */\r
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */\r
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+\r
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
\r
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
\r
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)\r
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define CEC_BASE (APB1PERIPH_BASE + 0x7800)\r
\r
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)\r
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)\r
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)\r
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)\r
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)\r
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)\r
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)\r
+#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)\r
\r
#define SDIO_BASE (PERIPH_BASE + 0x18000)\r
\r
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
#define RTC ((RTC_TypeDef *) RTC_BASE)\r
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
#define BKP ((BKP_TypeDef *) BKP_BASE)\r
#define PWR ((PWR_TypeDef *) PWR_BASE)\r
#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define CEC ((CEC_TypeDef *) CEC_BASE)\r
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)\r
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
#define USART1 ((USART_TypeDef *) USART1_BASE)\r
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\r
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\r
+#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/\r
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */\r
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */\r
+#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
+ #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */\r
+\r
+ #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */\r
+ #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */\r
+\r
+ #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */\r
+ #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */\r
+ #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */\r
+ #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */\r
+ #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */\r
+ #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */\r
+ #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */\r
+ #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */\r
+ #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */\r
+ #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */\r
+ #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */\r
+ #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */\r
+ #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */\r
+ #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */\r
+ #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */\r
+\r
+/*!< MCO configuration */\r
+ #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */\r
+ #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */\r
+ #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */\r
+ #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */\r
+\r
+ #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */\r
+ #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */\r
+ #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */\r
#else\r
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */\r
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */\r
#endif /* STM32F10X_CL */\r
\r
/***************** Bit definition for RCC_APB2RSTR register *****************/\r
-#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */\r
-#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */\r
-#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */\r
-#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */\r
-#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */\r
-#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */\r
-#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */\r
-#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */\r
-#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */\r
-#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */\r
-\r
-#ifndef STM32F10X_LD\r
- #define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */\r
+#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */\r
+#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */\r
+#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */\r
+#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */\r
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
+#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */\r
+#endif\r
\r
-#ifdef STM32F10X_HD\r
- #define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */\r
- #define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */\r
- #define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */\r
- #define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */\r
+#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */\r
+#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */\r
+#endif\r
+\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
+ #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */\r
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */\r
+ #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */\r
+ #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */\r
+ #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */\r
+#endif\r
+\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */\r
+ #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */\r
+ #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */\r
+#endif /* STM32F10X_XL */\r
\r
/***************** Bit definition for RCC_APB1RSTR register *****************/\r
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */\r
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */\r
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */\r
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */\r
+#endif\r
+\r
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */\r
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */\r
\r
-#ifndef STM32F10X_LD\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */\r
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */\r
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */\r
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */\r
-#endif /* STM32F10X_HD */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)\r
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */\r
#endif\r
\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)\r
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */\r
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
#endif\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */\r
+ #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */\r
+ #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */\r
+ #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ \r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */\r
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */\r
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */\r
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */\r
+ #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ \r
+ #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */\r
+ #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ \r
+#endif\r
+\r
#ifdef STM32F10X_CL\r
- #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */\r
+ #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */\r
#endif /* STM32F10X_CL */\r
\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */\r
+ #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */\r
+ #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */\r
+#endif /* STM32F10X_XL */\r
+\r
/****************** Bit definition for RCC_AHBENR register ******************/\r
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */\r
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */\r
#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */\r
#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */\r
\r
-#if defined (STM32F10X_HD) || defined (STM32F10X_CL)\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_HD_VL)\r
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */\r
#endif\r
\r
-#ifdef STM32F10X_HD\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */\r
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */\r
-#endif /* STM32F10X_HD */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */\r
+#endif\r
\r
#ifdef STM32F10X_CL\r
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */\r
#endif /* STM32F10X_CL */\r
\r
/****************** Bit definition for RCC_APB2ENR register *****************/\r
-#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */\r
-#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */\r
-#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */\r
-#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */\r
-#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */\r
-#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */\r
-#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */\r
-#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */\r
-#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */\r
-#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */\r
-\r
-#ifndef STM32F10X_LD\r
- #define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */\r
+#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */\r
+#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */\r
+#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */\r
+#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */\r
+#endif\r
\r
-#ifdef STM32F10X_HD\r
- #define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */\r
- #define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */\r
- #define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */\r
- #define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */\r
-#endif /* STM32F10X_HD */\r
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */\r
+\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */\r
+#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */\r
+#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */\r
+#endif\r
+\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
+ #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
+\r
+#if defined (STM32F10X_HD) || defined (STM32F10X_XL)\r
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */\r
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */\r
+ #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */\r
+ #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */\r
+#endif\r
+\r
+#if defined (STM32F10X_HD_VL)\r
+ #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */\r
+ #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */\r
+#endif\r
+\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */\r
+ #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */\r
+ #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */\r
+#endif\r
\r
/***************** Bit definition for RCC_APB1ENR register ******************/\r
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/\r
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */\r
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */\r
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */\r
+\r
+#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)\r
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */\r
+#endif\r
+\r
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */\r
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */\r
\r
-#ifndef STM32F10X_LD\r
+#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)\r
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */\r
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */\r
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */\r
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */\r
-#endif /* STM32F10X_HD */\r
+#endif /* STM32F10X_LD && STM32F10X_LD_VL */\r
\r
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)\r
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */\r
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
#endif\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+ #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */\r
+ #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */\r
+ #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */\r
+ #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ \r
+#endif\r
+\r
+#ifdef STM32F10X_HD_VL\r
+ #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */\r
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */\r
+ #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */\r
+ #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */\r
+ #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ \r
+#endif /* STM32F10X_HD_VL */\r
+\r
#ifdef STM32F10X_CL\r
- #define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */\r
+ #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */\r
#endif /* STM32F10X_CL */\r
\r
+#ifdef STM32F10X_XL\r
+ #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */\r
+ #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */\r
+#endif /* STM32F10X_XL */\r
+\r
/******************* Bit definition for RCC_BDCR register *******************/\r
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */\r
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */\r
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */\r
#endif /* STM32F10X_CL */\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/******************* Bit definition for RCC_CFGR2 register ******************/\r
+/*!< PREDIV1 configuration */\r
+ #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */\r
+ #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+ #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+ #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */\r
+ #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */\r
+\r
+ #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */\r
+ #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */\r
+ #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */\r
+ #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */\r
+ #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */\r
+ #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */\r
+ #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */\r
+ #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */\r
+ #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */\r
+ #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */\r
+ #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */\r
+ #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */\r
+ #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */\r
+ #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */\r
+ #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */\r
+ #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */\r
+#endif\r
+ \r
/******************************************************************************/\r
/* */\r
/* General Purpose and Alternate Function I/O */\r
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */\r
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */\r
\r
+#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)\r
+/****************** Bit definition for AFIO_MAPR2 register ******************/\r
+#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */\r
+#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */\r
+#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */\r
+#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */\r
+#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */\r
+#endif\r
+\r
+#ifdef STM32F10X_HD_VL\r
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */\r
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */\r
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */\r
+#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /*!< TIM6/TIM7 and DAC DMA remapping */\r
+#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /*!< TIM12 remapping */\r
+#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /*!< Miscellaneous remapping */\r
+#endif\r
+\r
+#ifdef STM32F10X_XL \r
+/****************** Bit definition for AFIO_MAPR2 register ******************/\r
+#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */\r
+#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */\r
+#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */\r
+#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */\r
+#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */\r
+#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */\r
+#endif\r
+\r
/******************************************************************************/\r
/* */\r
/* SystemTick */\r
/******************* Bit definition for DAC_DOR2 register *******************/\r
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CEC */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for CEC_CFGR register ******************/\r
+#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */\r
+#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */\r
+#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */\r
+#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */\r
+\r
+/******************** Bit definition for CEC_OAR register ******************/\r
+#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */\r
+#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */\r
+#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */\r
+#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */\r
+#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */\r
+\r
+/******************** Bit definition for CEC_PRES register ******************/\r
+#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */\r
+\r
+/******************** Bit definition for CEC_ESR register ******************/\r
+#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */\r
+#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */\r
+#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */\r
+#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */\r
+#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */\r
+#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */\r
+#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */\r
+\r
+/******************** Bit definition for CEC_CSR register ******************/\r
+#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */\r
+#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */\r
+#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */\r
+#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */\r
+#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */\r
+#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */\r
+#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */\r
+#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */\r
+\r
+/******************** Bit definition for CEC_TXD register ******************/\r
+#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */\r
+\r
+/******************** Bit definition for CEC_RXD register ******************/\r
+#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */\r
+\r
/******************************************************************************/\r
/* */\r
/* TIM */\r
#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
\r
/******************* Bit definition for TIM_CNT register ********************/\r
#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BCR2 register *******************/\r
#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BCR3 register *******************/\r
#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BCR4 register *******************/\r
#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
\r
/****************** Bit definition for FSMC_BTR1 register ******************/\r
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */\r
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */\r
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */\r
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */\r
\r
/****************** Bit definition for USART_CR2 register *******************/\r
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */\r
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */\r
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */\r
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */\r
\r
/****************** Bit definition for USART_GTPR register ******************/\r
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */\r
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */\r
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */\r
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */\r
+#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */\r
\r
/******************************************************************************/\r
/* */\r
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */\r
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */\r
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */\r
-#define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */\r
+#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */\r
\r
/****************** Bit definition for FLASH_WRPR register ******************/\r
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */\r
* @}\r
*/\r
\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/\r
#include "Os.h"\r
#include "internal.h"\r
#include "stm32f10x.h"\r
-#include "core_cm3.h"\r
#include "irq.h"\r
#include "arc.h"\r
\r
\r
SysTick_Config(period_ticks);\r
\r
- /* Set SysTick Priority to 3 */\r
- NVIC_SetPriority(SysTick_IRQn, 0x0C);\r
-\r
#if 0\r
// SysTick interrupt each 250ms with counter clock equal to 9MHz\r
if (SysTick_Config((SystemFrequency / 8) / 4)) {\r
* @return\r
*/\r
\r
-uint32_t Os_SysTickGetTimeElapsed( void )\r
+uint32_t Os_SysTickGetValue( void )\r
{\r
- return (SysTick->VAL);\r
+ return (SysTick->LOAD) - (SysTick->VAL);\r
+}\r
+\r
+\r
+TickType Os_SysTickGetElapsedValue( uint32_t preValue ) {\r
+ uint32_t curr;\r
+ uint32_t max;\r
+\r
+ curr = (SysTick->VAL);\r
+ max = (SysTick->LOAD);\r
+ return Os_CounterDiff((max - curr),preValue,max);\r
}\r
+\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32f10x.c\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
- ****************************************************************************** \r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x_system\r
- * @{\r
- */ \r
- \r
-/** @addtogroup STM32F10x_System_Private_Includes\r
- * @{\r
- */\r
-\r
-#include "stm32f10x.h"\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Defines\r
- * @{\r
- */\r
-\r
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
- frequency (after reset the HSI is used as SYSCLK source)\r
- \r
- IMPORTANT NOTE:\r
- ============== \r
- 1. After each device reset the HSI is used as System clock source.\r
-\r
- 2. Please make sure that the selected System clock doesn't exceed your device's\r
- maximum frequency.\r
- \r
- 3. If none of the define below is enabled, the HSI is used as System clock\r
- source.\r
-\r
- 4. The System clock configuration functions provided within this file assume that:\r
- - For Low, Medium and High density devices an external 8MHz crystal is\r
- used to drive the System clock.\r
- - For Connectivity line devices an external 25MHz crystal is used to drive\r
- the System clock.\r
- If you are using different crystal you have to adapt those functions accordingly.\r
- */\r
- \r
-/* #define SYSCLK_FREQ_HSE HSE_Value */\r
-/* #define SYSCLK_FREQ_24MHz 24000000 */\r
-/* #define SYSCLK_FREQ_36MHz 36000000 */\r
-/* #define SYSCLK_FREQ_48MHz 48000000 */\r
-/* #define SYSCLK_FREQ_56MHz 56000000 */\r
-#define SYSCLK_FREQ_72MHz 72000000\r
-\r
-/*!< Uncomment the following line if you need to use external SRAM mounted\r
- on STM3210E-EVAL board (STM32 High density devices) as data memory */ \r
-#ifdef STM32F10X_HD\r
-/* #define DATA_IN_ExtSRAM */\r
-#endif /* STM32F10X_HD */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Variables\r
- * @{\r
- */\r
-\r
-/*******************************************************************************\r
-* Clock Definitions\r
-*******************************************************************************/\r
-#ifdef SYSCLK_FREQ_HSE\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_24MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_36MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_48MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_56MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */ \r
-#elif defined SYSCLK_FREQ_72MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#else /*!< HSI Selected as System Clock source */\r
- const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static void SetSysClock(void);\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
- static void SetSysClockToHSE(void);\r
-#elif defined SYSCLK_FREQ_24MHz\r
- static void SetSysClockTo24(void);\r
-#elif defined SYSCLK_FREQ_36MHz\r
- static void SetSysClockTo36(void);\r
-#elif defined SYSCLK_FREQ_48MHz\r
- static void SetSysClockTo48(void);\r
-#elif defined SYSCLK_FREQ_56MHz\r
- static void SetSysClockTo56(void); \r
-#elif defined SYSCLK_FREQ_72MHz\r
- static void SetSysClockTo72(void);\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Setup the microcontroller system\r
- * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit (void)\r
-{\r
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
- /* Set HSION bit */\r
- RCC->CR |= (uint32_t)0x00000001;\r
-\r
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
-#ifndef STM32F10X_CL\r
- RCC->CFGR &= (uint32_t)0xF8FF0000;\r
-#else\r
- RCC->CFGR &= (uint32_t)0xF0FF0000;\r
-#endif /* STM32F10X_CL */ \r
- \r
- /* Reset HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xFEF6FFFF;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
- RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
-\r
-#ifndef STM32F10X_CL\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000;\r
-#else\r
- /* Reset PLL2ON and PLL3ON bits */\r
- RCC->CR &= (uint32_t)0xEBFFFFFF;\r
-\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x00FF0000;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000;\r
-#endif /* STM32F10X_CL */\r
- \r
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
- /* Configure the Flash Latency cycles and enable prefetch buffer */\r
- SetSysClock();\r
-\r
-}\r
-\r
-/**\r
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClock(void)\r
-{\r
-#if !defined(CFG_SIMULATOR)\r
-#ifdef SYSCLK_FREQ_HSE\r
- SetSysClockToHSE();\r
-#elif defined SYSCLK_FREQ_24MHz\r
- SetSysClockTo24();\r
-#elif defined SYSCLK_FREQ_36MHz\r
- SetSysClockTo36();\r
-#elif defined SYSCLK_FREQ_48MHz\r
- SetSysClockTo48();\r
-#elif defined SYSCLK_FREQ_56MHz\r
- SetSysClockTo56(); \r
-#elif defined SYSCLK_FREQ_72MHz\r
- SetSysClockTo72();\r
-#endif\r
-#endif\r
- \r
- /* If none of the define above is enabled, the HSI is used as System clock\r
- source (default after reset) */ \r
-}\r
-\r
-/**\r
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s \r
- * before jump to __main\r
- * @param None\r
- * @retval None\r
- */ \r
-#ifdef DATA_IN_ExtSRAM\r
-/**\r
- * @brief Setup the external memory controller. \r
- * Called in startup_stm32f10x_xx.s/.c before jump to main.\r
- * This function configures the external SRAM mounted on STM3210E-EVAL\r
- * board (STM32 High density devices). This SRAM will be used as program\r
- * data memory (including heap and stack).\r
- * @param None\r
- * @retval None\r
- */ \r
-void SystemInit_ExtMemCtl(void) \r
-{\r
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
- required, then adjust the Register Addresses */\r
-\r
- /* Enable FSMC clock */\r
- RCC->AHBENR = 0x00000114;\r
- \r
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ \r
- RCC->APB2ENR = 0x000001E0;\r
- \r
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/\r
-/*---------------- SRAM Address lines configuration -------------------------*/\r
-/*---------------- NOE and NWE configuration --------------------------------*/ \r
-/*---------------- NE3 configuration ----------------------------------------*/\r
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/\r
- \r
- GPIOD->CRL = 0x44BB44BB; \r
- GPIOD->CRH = 0xBBBBBBBB;\r
-\r
- GPIOE->CRL = 0xB44444BB; \r
- GPIOE->CRH = 0xBBBBBBBB;\r
-\r
- GPIOF->CRL = 0x44BBBBBB; \r
- GPIOF->CRH = 0xBBBB4444;\r
-\r
- GPIOG->CRL = 0x44BBBBBB; \r
- GPIOG->CRH = 0x44444B44;\r
- \r
-/*---------------- FSMC Configuration ---------------------------------------*/ \r
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
- \r
- FSMC_Bank1->BTCR[4] = 0x00001011;\r
- FSMC_Bank1->BTCR[5] = 0x00000200;\r
-}\r
-#endif /* DATA_IN_ExtSRAM */\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
-/**\r
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2\r
- * and PCLK1 prescalers.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockToHSE(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-\r
-#ifndef STM32F10X_CL\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
-#else\r
- if (HSE_Value <= 24000000)\r
- {\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
- }\r
- else\r
- {\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;\r
- }\r
-#endif /* STM32F10X_CL */\r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
- /* Select HSE as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; \r
-\r
- /* Wait till HSE is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_24MHz\r
-/**\r
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo24(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL6); \r
-\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- } \r
-#else \r
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_36MHz\r
-/**\r
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo36(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL9); \r
-\r
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
-#else \r
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_48MHz\r
-/**\r
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo48(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL6); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_56MHz\r
-/**\r
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo56(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL7); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);\r
-\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_72MHz\r
-/**\r
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo72(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 2 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; \r
-\r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL9); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
- RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
- \r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- }\r
-}\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-\r
-/**\r
- ******************************************************************************\r
- * @file system_stm32f10x.h\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
- ****************************************************************************** \r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x_system\r
- * @{\r
- */ \r
- \r
-/**\r
- * @brief Define to prevent recursive inclusion\r
- */\r
-#ifndef __SYSTEM_STM32F10X_H\r
-#define __SYSTEM_STM32F10X_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/** @addtogroup STM32F10x_System_Includes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @addtogroup STM32F10x_System_Exported_types\r
- * @{\r
- */\r
-\r
-extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
-extern const uint32_t SystemFrequency_SysClk; /*!< System clock */\r
-extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */\r
-extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */\r
-extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Functions\r
- * @{\r
- */\r
- \r
-extern void SystemInit(void);\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__SYSTEM_STM32F10X_H */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
\r
MEMORY\r
{\r
- flash(R) : ORIGIN = 0x08000000, LENGTH = 128K\r
- ram(RW) : ORIGIN = 0x20000000, LENGTH = 20K\r
+#include "memory.ldf"\r
}\r
\r
SECTIONS\r
\r
.text :\r
{\r
+ . = ALIGN(4);\r
*(.text .text.* );\r
*(.glue_7) /* TODO */\r
*(.glue_7t) /* TODO */\r
SORT(*)(.test_etask);\r
\r
/* ST/ARM special variable to initialize .data */\r
+ . = ALIGN(4);\r
_etext = .;\r
} > flash\r
\r
\r
/* Read-only data section. */\r
.rodata : { \r
+ . = ALIGN(4);\r
*(.rodata .rodata.* .gnu.linkonce.r.*)\r
- _sidata = .;\r
+ . = ALIGN(4);\r
+ _sidata = ALIGN(.,4);\r
} > flash\r
\r
- .data : AT(ALIGN(LOADADDR(.rodata)+SIZEOF(.rodata),4)) {\r
+ .data : AT ( _sidata )\r
+ {\r
+ . = ALIGN(4);\r
_sdata = .; \r
*(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ . = ALIGN(4);\r
_edata = .; \r
} > ram\r
\r
.t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
.bss : {\r
+ . = ALIGN(4);\r
_sbss = ., \r
*(.bss .bss.* COMMON .gnu.linkonce.b.*);\r
+ . = ALIGN(4);\r
_ebss = .; \r
} > ram\r
\r
--- /dev/null
+/* \r
+ * Copyright (C) ArcCore AB <contact@arccore.com>\r
+ *\r
+ * ST startup variables: \r
+ * _sidata - Start of .data in flash \r
+ * _sdata - start address of .data in RAM\r
+ * _edata - end address of .data in RAM\r
+ * _sbss - start address of .bss\r
+ * _ebss - end address of .bss\r
+ * _etext - ?\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm","elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(Reset_Handler)\r
+\r
+MEMORY\r
+{\r
+ flash(R) : ORIGIN = 0x08008000, LENGTH = 256K-32K\r
+ ram(RW) : ORIGIN = 0x20000000, LENGTH = 64K\r
+}\r
+\r
+SECTIONS\r
+{\r
+\r
+ .isr_vector :\r
+ {\r
+ . = ALIGN(4);\r
+ KEEP(*(.isr_vector))\r
+ . = ALIGN(4);\r
+ } > flash\r
+\r
+ .text :\r
+ {\r
+ *(.text .text.* );\r
+ *(.glue_7) /* TODO */\r
+ *(.glue_7t) /* TODO */\r
+ \r
+ PROVIDE( btask_sup_matrix = .);\r
+ SORT(*)(.test_btask);\r
+ PROVIDE( etask_sup_matrix = .);\r
+ SORT(*)(.test_etask);\r
+ \r
+ /* ST/ARM special variable to initialize .data */\r
+ _etext = .;\r
+ } > flash\r
+\r
+ /* Relocatable Flash Driver */\r
+ .fls_rom : {\r
+ __FLS_ERASE_ROM__ = .;\r
+ *(.fls_erase);\r
+ __FLS_WRITE_ROM__ = .;\r
+ *(.fls_write);\r
+ __FLS_END_ROM__ = .;\r
+ } > flash\r
+\r
+ /* ARM exception section */\r
+ .ARM.exidx : { \r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > flash\r
+ __exidx_start = .;\r
+\r
+ /* Read-only data section. */\r
+ .rodata : { \r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
+ _sidata = .;\r
+ } > flash\r
+\r
+ .data : AT(ALIGN(LOADADDR(.rodata)+SIZEOF(.rodata),4)) {\r
+ _sdata = .; \r
+ *(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ _edata = .; \r
+ } > ram\r
+\r
+ .t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
+ .bss : {\r
+ _sbss = ., \r
+ *(.bss .bss.* COMMON .gnu.linkonce.b.*);\r
+ _ebss = .; \r
+ } > ram\r
+ \r
+ .init_stack ALIGN(16) (NOLOAD) : \r
+ { \r
+ . = . + 200; \r
+ _estack = .; \r
+ } > ram\r
+ \r
+ /* Fls RAM section */\r
+ .fls_ram ALIGN(16) (NOLOAD) : {\r
+ __FLS_ERASE_RAM__ = .;\r
+ . = . + SIZEOF(.fls_rom);\r
+ } > ram\r
+\r
+ .ctors :\r
+ {\r
+ KEEP (*(SORT(.ctors.*)))\r
+ }\r
+\r
+ .uninit ALIGN(0x10) (NOLOAD) : { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
+\r
+ .boot_area 0x2000FE00 (NOLOAD):\r
+ {\r
+ _boot_area_start = .;\r
+ . = . + 256;\r
+ _boot_area_end = .;\r
+ } > ram\r
+ \r
+ PROVIDE (boot_area_start = _boot_area_start);\r
+ PROVIDE (boot_area_end = _boot_area_end);\r
+\r
+ __FLS_SIZE__ = SIZEOF(.fls_rom);\r
+ __FLS_WRITE_RAM__ = __FLS_ERASE_RAM__ + (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
+__EXCEPT_START__ = 0x0;\r
+__EXCEPT_END__ = 0x0;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Can.h"\r
+#include "core_cr4.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#include "Det.h"\r
+#include "CanIf_Cbk.h"\r
+#include "Os.h"\r
+#include "irq.h"\r
+#include "Mcu.h"\r
+#include "arc.h"\r
+\r
+#define DCAN1_MAX_MESSAGEBOXES 64\r
+#define DCAN2_MAX_MESSAGEBOXES 64\r
+#define DCAN3_MAX_MESSAGEBOXES 32\r
+\r
+#define CAN_TIMEOUT_DURATION 0xFFFFFFFF\r
+#define CAN_INSTANCE 0\r
+\r
+#define DCAN_IRQ_MASK 0x00000006\r
+\r
+\r
+#if !defined(USE_DEM)\r
+// If compiled without the DEM, calls to DEM are simply ignored.\r
+#define Dem_ReportErrorStatus(...)\r
+#endif\r
+\r
+/* Macro for waiting until busy flag is 0 */\r
+#define DCAN_WAIT_UNTIL_NOT_BUSY(ControllerId, IfRegId) \\r
+ { \\r
+ uint32 ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ while(CanRegs[ControllerId]->IFx[IfRegId].COM & 0x00008000) { \\r
+ ErrCounter--; \\r
+ if(ErrCounter == 0) { \\r
+ Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED); \\r
+ ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ return CAN_NOT_OK; \\r
+ } \\r
+ } \\r
+ }\r
+\r
+/* Macro for waiting until busy flag is 0 */\r
+#define DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(ControllerId, IfRegId) \\r
+ { \\r
+ uint32 ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ while(CanRegs[ControllerId]->IFx[IfRegId].COM & 0x00008000) { \\r
+ ErrCounter--; \\r
+ if(ErrCounter == 0) { \\r
+ Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED); \\r
+ ErrCounter = CAN_TIMEOUT_DURATION; \\r
+ return; \\r
+ } \\r
+ } \\r
+ }\r
+\r
+\r
+\r
+// Array for easy access to DCAN register definitions.\r
+static Can_RegisterType* CanRegs[]=\r
+{\r
+ DCAN1_Base,\r
+ DCAN2_Base,\r
+ DCAN3_Base\r
+};\r
+\r
+typedef enum\r
+{\r
+ CAN_UNINIT,\r
+ CAN_READY\r
+} Can_StateType;\r
+\r
+\r
+typedef struct\r
+{\r
+ uint16 MaxBoxes;\r
+ uint32 WakeupSrc;\r
+ Can_PduType *PduPtr;\r
+ uint8 *CancelPtr;\r
+ uint8 *TxPtr; \r
+} Controller_PreConfigType;\r
+\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+/* Module is in uninitialized state */\r
+static Can_StateType ModuleState = CAN_UNINIT;\r
+#endif\r
+\r
+static CanIf_ControllerModeType ControllerMode[CAN_ARC_CTRL_CONFIG_CNT];\r
+\r
+/* Used to switch between IF1 and IF2 of DCAN */\r
+static uint8 IfRegId = 0;\r
+\r
+/* Used to order Data Bytes according to hardware registers in DCAN */\r
+static const uint8 ElementIndex[] = {3, 2, 1, 0, 7, 6, 5, 4};\r
+\r
+/* To save pointer to the configuration set */\r
+static const Can_ConfigType *CurConfig;\r
+\r
+/* To save the PduData of transmission objects */\r
+static Can_PduType PduInfoArray_1[DCAN1_MAX_MESSAGEBOXES];\r
+/* To save pending Cancel Requests of transmission objects */\r
+static uint8 CancelRqstArray_1[DCAN1_MAX_MESSAGEBOXES];\r
+/* To save pending Transmit Requests of transmission objects */\r
+static uint8 TxRqstArray_1[DCAN1_MAX_MESSAGEBOXES];\r
+\r
+static Can_PduType PduInfoArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+static uint8 CancelRqstArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+static uint8 TxRqstArray_2[DCAN2_MAX_MESSAGEBOXES];\r
+\r
+static Can_PduType PduInfoArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+static uint8 CancelRqstArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+static uint8 TxRqstArray_3[DCAN3_MAX_MESSAGEBOXES];\r
+\r
+\r
+/* Holds the Controller specific configuration */ \r
+static Controller_PreConfigType ControllerConfig[] =\r
+{\r
+ { // DCAN1\r
+ .MaxBoxes = DCAN1_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 0,\r
+ .PduPtr = PduInfoArray_1,\r
+ .CancelPtr = CancelRqstArray_1,\r
+ .TxPtr = TxRqstArray_1\r
+ },\r
+ { // DCAN2\r
+ .MaxBoxes = DCAN2_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 1,\r
+ .PduPtr = PduInfoArray_2,\r
+ .CancelPtr = CancelRqstArray_2,\r
+ .TxPtr = TxRqstArray_2\r
+ },\r
+ { // DCAN3\r
+ .MaxBoxes = DCAN3_MAX_MESSAGEBOXES,\r
+ .WakeupSrc = 1,\r
+ .PduPtr = PduInfoArray_3,\r
+ .CancelPtr = CancelRqstArray_3,\r
+ .TxPtr = TxRqstArray_3\r
+ }\r
+\r
+};\r
+\r
+/* Shadow Buffer is used for buffering of received data */ \r
+static uint8 RxShadowBuf[CAN_ARC_CTRL_CONFIG_CNT][8];\r
+\r
+/* Driver must know how often Can_DisableControllerInterrupts() has been called */\r
+static uint32 IntDisableCount[CAN_ARC_CTRL_CONFIG_CNT];\r
+\r
+\r
+static inline const Can_HardwareObjectType * Can_FindTxHoh(Can_Arc_HTHType hth) {\r
+ for (int i = 0; i < CAN_ARC_CTRL_CONFIG_CNT; i++) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[i].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT && hoh->CanObjectId == hth) {\r
+ return hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return 0;\r
+}\r
+\r
+static inline uint8 Can_FindControllerId(Can_Arc_HTHType hth) {\r
+ for (int i = 0; i < CAN_ARC_CTRL_CONFIG_CNT; i++) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[i].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT && hoh->CanObjectId == hth) {\r
+ return i;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return 0;\r
+}\r
+\r
+static inline const Can_HardwareObjectType * Can_FindRxHoh(CanControllerIdType Controller, uint8 msgNr) {\r
+ const Can_HardwareObjectType * hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_RECEIVE\r
+ && (hoh->Can_Arc_MbMask & (1 << (msgNr - 1))) ) {\r
+ return hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ return 0;\r
+}\r
+\r
+#define DCAN_MC_NEWDAT 15\r
+#define DCAN_MC_EOB 7\r
+\r
+uint32 usedRxBoxes[64] = {0};\r
+uint32 usedTxBoxes[64] = {0};\r
+\r
+static inline Can_ReturnType handleRxMsgObject(uint8 MsgNr, const Can_HardwareObjectType *hoh, CanControllerIdType controller) {\r
+ uint32 MsgId;\r
+ uint8 MsgDlc;\r
+ uint8 DataByteIndex;\r
+ uint8 *SduPtr;\r
+\r
+ /* Wait until Busy Flag is 0 */\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(controller, IfRegId);\r
+\r
+ // Read message control\r
+ uint32 mc = CanRegs[controller]->IFx[IfRegId].MC;\r
+ uint32 arb = CanRegs[controller]->IFx[IfRegId].ARB;\r
+\r
+ // Is there a new message waiting?\r
+ if (!(mc & (1 << DCAN_MC_NEWDAT))) {\r
+ return CAN_NOT_OK; // Nothing more to be done.\r
+ }\r
+\r
+ // For debug\r
+ if (MsgNr == 0) {\r
+ usedRxBoxes[MsgNr]++;\r
+ } else {\r
+ usedRxBoxes[MsgNr]++;\r
+ }\r
+\r
+\r
+ /* Extended Id */\r
+ if(arb & 0x40000000) {\r
+ /* Bring Id to standardized format (MSB marks extended Id) */\r
+ MsgId = (arb & 0x1FFFFFFF) | 0x80000000;\r
+\r
+ } else { /* Standard Id */\r
+ /* Bring Id to standardized format (MSB marks extended Id) */\r
+ MsgId = (arb & 0x1FFC0000) >> 18;\r
+ }\r
+\r
+ /* DLC (Max 8) */\r
+ MsgDlc = mc & 0x000F;\r
+ if(MsgDlc > 8) {\r
+ MsgDlc = 8;\r
+ }\r
+\r
+ /* Let SduPtr point to Shadow Buffer */\r
+ SduPtr = RxShadowBuf[controller];\r
+\r
+ /* Copy Message Data to Shadow Buffer */\r
+ for(DataByteIndex = 0; DataByteIndex < MsgDlc; DataByteIndex++)\r
+ {\r
+ SduPtr[DataByteIndex] = CanRegs[controller]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]];\r
+ }\r
+\r
+ /* Indicate successful Reception */\r
+ CanIf_RxIndication(hoh->CanObjectId, MsgId, MsgDlc, SduPtr);\r
+\r
+ // Is this the last message object of the FIFO?\r
+ if (mc & (1 << DCAN_MC_EOB)) {\r
+ return CAN_NOT_OK;\r
+ }\r
+\r
+ return CAN_OK;\r
+}\r
+\r
+\r
+void Can_InterruptHandler(CanControllerIdType controller)\r
+{\r
+ uint32 MsgNr;\r
+\r
+ uint32 ir = CanRegs[controller]->IR;\r
+\r
+\r
+ if(ir == 0x8000) { // This is an error interrupt\r
+\r
+ uint32 sr = CanRegs[controller]->SR;\r
+\r
+ if(sr & 0x00000200) { /* WakeUp Pending */\r
+ /* Set Init Bit, so that Controller is in Stop state */\r
+ CanRegs[controller]->CTL |= 0x1;\r
+ // EcuM_CheckWakeUp(ControllerConfig[0].WakeupSrc);\r
+\r
+ }\r
+\r
+ if(sr & 0x00000080) { /* Bus Off */\r
+ Can_SetControllerMode(controller, CAN_T_STOP); // CANIF272\r
+ //CanIf_ControllerBusOff(0); // Not implemented in Arctic Core\r
+\r
+ }\r
+\r
+ } else if (ir > 0 && ir < 0x8000){ // This interrupt is from a message object.\r
+ MsgNr = ir;\r
+\r
+ /* Read Arbitration and control */\r
+ CanRegs[controller]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
+\r
+ /* Wait until Busy Flag is 0 */\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(controller, IfRegId);\r
+\r
+ /* Transmit Object */\r
+ if(CanRegs[controller]->IFx[IfRegId].ARB & 0x20000000)\r
+ {\r
+ // For debug\r
+ if (MsgNr == 0) {\r
+ usedTxBoxes[MsgNr]++;\r
+ } else {\r
+ usedTxBoxes[MsgNr]++;\r
+ }\r
+\r
+ /* Reset TxRqst-Array Element */\r
+ ControllerConfig[controller].TxPtr[MsgNr - 1] = 0;\r
+ /* A Message was successfully transmitted */\r
+ CanIf_TxConfirmation(ControllerConfig[controller].PduPtr[MsgNr - 1].swPduHandle);\r
+\r
+ /* Receive Object */\r
+ } else {\r
+\r
+ // Handle all of the message objects in this FIFO buffer.\r
+ const Can_HardwareObjectType *hoh = Can_FindRxHoh(controller, MsgNr);\r
+ for(; MsgNr < ControllerConfig[controller].MaxBoxes; MsgNr++) {\r
+ if (!(hoh->Can_Arc_MbMask & (1 << (MsgNr - 1)))) {\r
+ continue;\r
+ }\r
+\r
+ /* Read setup hardware to read arbitration, control and data Bits of the message object.\r
+ * Clear IntPnd and Tx */\r
+ if (MsgNr != ir) { // Don't do this the first time.\r
+ CanRegs[controller]->IFx[IfRegId].COM = 0x003F0000 | MsgNr;\r
+ }\r
+\r
+ if (handleRxMsgObject(MsgNr, hoh, controller) == CAN_NOT_OK) {\r
+ break; // We have parsed the last object of this FIFO.\r
+ }\r
+ }\r
+\r
+ }\r
+ }\r
+}\r
+\r
+void Can1_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN1);\r
+}\r
+\r
+void Can2_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN2);\r
+}\r
+\r
+void Can3_InterruptHandler() {\r
+ Can_InterruptHandler(DCAN3);\r
+}\r
+\r
+uint32 Can_CalculateBTR(uint8 Controller) {\r
+\r
+ uint32 clock = McuE_GetPeripheralClock(PERIPHERAL_CLOCK_CAN);\r
+ uint32 tq1 = CanControllerConfigData[Controller].CanControllerPropSeg + CanControllerConfigData[Controller].CanControllerSeg1;\r
+ uint32 tq2 = CanControllerConfigData[Controller].CanControllerSeg2;\r
+ uint32 ntq = tq1 + tq2 + 1 + 1 + 1;\r
+ uint32 brp = clock / (CanControllerConfigData[Controller].CanControllerBaudRate * 1000 * ntq) - 1;\r
+\r
+ uint32 retVal = (brp | (tq1 << 8) | (tq2 << 12));\r
+ return retVal;\r
+}\r
+\r
+\r
+void Can_Init(const Can_ConfigType *Config)\r
+{\r
+ uint32 Controller;\r
+ uint8 MsgNr;\r
+ uint32 ErrCounter;\r
+ uint32 Eob;\r
+\r
+/* DET Error Check */\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(ModuleState != CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0, CAN_E_TRANSITION);\r
+ return;\r
+ }\r
+ if(Config == NULL)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0, CAN_E_PARAM_POINTER);\r
+ return;\r
+ }\r
+#endif \r
+\r
+ imask_t i_state = McuE_EnterCriticalSection();\r
+\r
+ // TODO This should be used instead of other variables in the Can_Lcfg file.\r
+ CurConfig = Config;\r
+\r
+ for(Controller = 0; Controller < CAN_ARC_CTRL_CONFIG_CNT; Controller++)\r
+ {\r
+ ErrCounter = CAN_TIMEOUT_DURATION;\r
+\r
+ /* Init, IE, AutomaticRetransmission, ConfChangeEnable, ABO Off,Parity On, SIE and EIE depending on ControllerConfig, loopback */\r
+#if(CAN_WAKEUP_SUPPORT == STD_ON)\r
+ CanRegs[Controller]->CTL = 0x02001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
+#else\r
+ CanRegs[Controller]->CTL = 0x00001641 | DCAN_IRQ_MASK | (CanControllerConfigData[Controller].Can_Arc_Loopback << 7);// | (CanControllerConfigData[Controller].CanWakeupProcessing >> 8) | (CanControllerConfigData[Controller].CanBusOffProcessing >> 7);\r
+#endif \r
+ /* LEC 7, TxOk, RxOk, PER */\r
+ CanRegs[Controller]->SR = 0x0000011F;\r
+\r
+ /* Test Mode only for Development time: Silent Loopback */\r
+ if (CanControllerConfigData[Controller].Can_Arc_Loopback) {\r
+ CanRegs[Controller]->TR = 0x00000018;\r
+ }\r
+ \r
+\r
+ // Basic message object initialization\r
+ for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MaxBoxes; MsgNr++) {\r
+ /* Initialize the Arrays for Transmit and Cancellation handling */\r
+ *(ControllerConfig[Controller].CancelPtr + MsgNr) = 0;\r
+ *(ControllerConfig[Controller].TxPtr + MsgNr) = 0;\r
+ \r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ // Initialize all message objects for this controller to invalid state.\r
+ /* Valid = 0 */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0x00000000;\r
+ /* Start writing Arbitration Bits */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00A80000 | (MsgNr + 1);\r
+\r
+ /* Use IFx[0] and IFx[1] alternating */\r
+ IfRegId ^= 1;\r
+\r
+ }\r
+\r
+ /* Configure the HOHs for this controller. */\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ hoh--;\r
+ do {\r
+ hoh++;\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ uint32 mbNr = 0;\r
+ uint32 nProcessedMb = 0;\r
+\r
+ // For every message object in this hoh\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ mbNr++;\r
+ if (!(mbMask & 1)) {\r
+ // This message object is not part of this hoh.\r
+ continue;\r
+ }\r
+ nProcessedMb++;\r
+\r
+ // Check if this is the last message box for this hoh.\r
+ if((mbMask != 1) &&\r
+ (hoh->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)) {\r
+ /* EndOfBlock Bit will not be set */\r
+ Eob = 0x00000000;\r
+ }\r
+ else\r
+ {\r
+ /* EndOfBlock Bit will be set */\r
+ Eob = 0x00000080;\r
+ }\r
+\r
+ /* DLC=8, Use Mask only for receive, Set RxIE/TxIE depending on pre-config settings, Eob */\r
+ CanRegs[Controller]->IFx[IfRegId].MC = 0x00000008 // DLC = 8\r
+ | 0x00001000 // umask = ON\r
+ | CanControllerConfigData[Controller].CanRxProcessing // Rx interrupt enabled\r
+ | (CanControllerConfigData[Controller].CanTxProcessing << 1) // Tx confirmation interrupt enabled\r
+ | (Eob & ~(hoh->CanObjectType >> 22)); // Eob, only for Rx.\r
+\r
+ //CanRegs[Controller]->IFx[IfRegId].MC = 0x00001008 | CanControllerConfigData[Controller].CanRxProcessing | (CanControllerConfigData[Controller].CanTxProcessing) | Eob & ~(hoh->CanObjectType >> 17);\r
+\r
+ if(hoh->CanIdType == CAN_ID_TYPE_STANDARD) /* Standard Identifiers */\r
+ {\r
+ /* Only Standard-Ids are accepted, Set Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0x80000000 | ((hoh->CanIdValue & 0x7FF) << 18) | hoh->CanObjectType;\r
+ }\r
+ else if(hoh->CanIdType == CAN_ID_TYPE_EXTENDED) /* Extended Identifiers */\r
+ {\r
+ /* Only Extended-Ids are accepted, Set Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0x80000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFFF) | hoh->CanObjectType;\r
+ }\r
+ else /* Mixed Identifiers */\r
+ {\r
+ /* Standard- and Mixed-Ids are accepted, Set Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK = 0x00000000 | ((*(hoh->CanFilterMaskRef)) & 0x1FFFFFF);\r
+ /* Message valid, Id, Direction */\r
+ CanRegs[Controller]->IFx[IfRegId].ARB = 0xC0000000 | (hoh->CanIdValue & 0x1FFFFFF) | hoh->CanObjectType;\r
+ }\r
+ /* Start writing Mask, Arb, Control and Id bits */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00F80000 | mbNr;\r
+\r
+ /* Use IFx[0] and IFx[1] alternating */\r
+ IfRegId ^= 1;\r
+\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+\r
+\r
+ /* Set Bit Timing Register */\r
+ CanRegs[Controller]->BTR = Can_CalculateBTR(Controller);\r
+\r
+ /* Reset CCE Bit */\r
+ CanRegs[Controller]->CTL &= ~0x00000040;\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ /* Switch Controller State to CANIF_CS_STOPPED */\r
+ ControllerMode[Controller] = CANIF_CS_STOPPED;\r
+#endif\r
+\r
+ // Install interrupt handlers\r
+ TaskType tid;\r
+ if (CanControllerConfigData[Controller].CanControllerId == DCAN1) {\r
+ tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2 ,"DCAN1Level0");\r
+ Irq_AttachIsr2(tid, NULL, 16);\r
+\r
+ tid = Os_Arc_CreateIsr(Can1_InterruptHandler, 2, "DCAN1Level1");\r
+ Irq_AttachIsr2(tid, NULL, 29);\r
+\r
+ } else if (CanControllerConfigData[Controller].CanControllerId == DCAN2) {\r
+ tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2 ,"DCAN2Level0");\r
+ Irq_AttachIsr2(tid, NULL, 35);\r
+\r
+ tid = Os_Arc_CreateIsr(Can2_InterruptHandler, 2, "DCAN2Level1");\r
+ Irq_AttachIsr2(tid, NULL, 42);\r
+\r
+ } else if (CanControllerConfigData[Controller].CanControllerId == DCAN3) {\r
+ tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2 ,"DCAN3Level0");\r
+ Irq_AttachIsr2(tid, NULL, 45);\r
+\r
+ tid = Os_Arc_CreateIsr(Can3_InterruptHandler, 2, "DCAN3Level1");\r
+ Irq_AttachIsr2(tid, NULL, 55);\r
+\r
+ }\r
+\r
+ }\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ /* Switch Module State to CAN_READY */\r
+ ModuleState = CAN_READY;\r
+#endif\r
+\r
+ McuE_ExitCriticalSection(i_state);\r
+\r
+}\r
+\r
+\r
+\r
+void Can_InitController(uint8 Controller, const Can_ControllerConfigType* Config)\r
+{\r
+ uint8 MsgNr;\r
+ uint32 ErrCounter;\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(Config == NULL)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_PARAM_POINTER);\r
+ return;\r
+ }\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_UNINIT);\r
+ return;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_PARAM_CONTROLLER);\r
+ return;\r
+ }\r
+ if(ControllerMode[Controller] != CANIF_CS_STOPPED)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 2, CAN_E_TRANSITION);\r
+ return;\r
+ }\r
+#endif \r
+\r
+ imask_t i_state = McuE_EnterCriticalSection();\r
+\r
+ ErrCounter = CAN_TIMEOUT_DURATION;\r
+ \r
+ //for(MsgNr = 0; MsgNr < ControllerConfig[Controller].MessageBoxCount; MsgNr++)\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = CanControllerConfigData[Controller].Can_Arc_Hoh;\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ uint32 nProcessedMb = 0;\r
+ MsgNr = 0;\r
+\r
+ // For every message object in this hoh\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ MsgNr++;\r
+ if (!(mbMask & 1)) {\r
+ // This message object is not part of this hoh.\r
+ continue;\r
+ }\r
+ nProcessedMb++;\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ /* Read actual MaskRegister value of MessageObject */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x004C0000 | (MsgNr);\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ CanRegs[Controller]->IFx[IfRegId].MASK &= 0xD0000000;\r
+ /* Set new Mask */\r
+ CanRegs[Controller]->IFx[IfRegId].MASK |= (*(hoh->CanFilterMaskRef)) & 0x1FFFFFFF;\r
+ /* Write new Mask to MaskRegister */\r
+ CanRegs[Controller]->IFx[IfRegId].COM = 0x00C80000 | (MsgNr);\r
+\r
+ IfRegId ^= 1;\r
+ }\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY_NO_RV(Controller, IfRegId);\r
+\r
+ /* Set CCE Bit to allow access to BitTiming Register (Init already set, in mode "stopped") */\r
+ CanRegs[Controller]->CTL |= 0x00000040;\r
+ /* Set Bit Timing Register */\r
+ CanRegs[Controller]->BTR = Can_CalculateBTR(Controller);\r
+ /* Clear CCE Bit */\r
+ CanRegs[Controller]->CTL &= ~0x00000040;\r
+\r
+ McuE_ExitCriticalSection(i_state);\r
+}\r
+\r
+\r
+Can_ReturnType Can_SetControllerMode(uint8 Controller, Can_StateTransitionType Transition)\r
+{\r
+ Can_ReturnType Status = CAN_OK;\r
+ uint32 ErrCounter = CAN_TIMEOUT_DURATION;\r
+ uint32 RegBuf;\r
+ \r
+#if(CAN_DEV_ERROR_DETECT == STD_ON) \r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_UNINIT);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_PARAM_CONTROLLER);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(((Transition == CAN_T_START ) && (ControllerMode[Controller] != CANIF_CS_STOPPED)) ||\r
+ ((Transition == CAN_T_STOP ) && (ControllerMode[Controller] != CANIF_CS_STARTED)) ||\r
+ ((Transition == CAN_T_SLEEP ) && (ControllerMode[Controller] != CANIF_CS_STOPPED)) ||\r
+ ((Transition == CAN_T_WAKEUP) && (ControllerMode[Controller] != CANIF_CS_SLEEP )))\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_TRANSITION);\r
+ return CAN_NOT_OK;\r
+ }\r
+#endif \r
+\r
+ switch(Transition)\r
+ {\r
+ case CAN_T_START:\r
+ /* Clear Init Bit */\r
+ CanRegs[Controller]->CTL &= ~0x00000001;\r
+ /* Clear Status Register */\r
+ CanRegs[Controller]->SR = 0x0000011F;\r
+\r
+ ControllerMode[Controller] = CANIF_CS_STARTED;\r
+ Can_EnableControllerInterrupts(Controller);\r
+ break;\r
+\r
+ case CAN_T_STOP:\r
+ /* Set Init Bit */\r
+ CanRegs[Controller]->CTL |= 0x00000001;\r
+ ControllerMode[Controller] = CANIF_CS_STOPPED;\r
+ Can_DisableControllerInterrupts(Controller);\r
+ break;\r
+\r
+ case CAN_T_SLEEP:\r
+ /* Set PDR Bit */\r
+ CanRegs[Controller]->CTL |= 0x01000000;\r
+ /* Save actual Register status */\r
+ RegBuf = CanRegs[Controller]->CTL;\r
+ /* Disable Status Interrupts and WUBA */\r
+ CanRegs[Controller]->CTL &= ~0x02000004;\r
+ /* Wait until Local Power Down Mode acknowledged */\r
+ while(!(CanRegs[Controller]->SR & 0x00000400))\r
+ {\r
+ /* Check if a WakeUp occurs */\r
+ if(CanRegs[Controller]->SR & 0x00000200)\r
+ {\r
+ Status = CAN_NOT_OK;\r
+ break;\r
+ }\r
+ ErrCounter--;\r
+ if(ErrCounter == 0)\r
+ {\r
+ Dem_ReportErrorStatus(CAN_E_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
+ ErrCounter = CAN_TIMEOUT_DURATION;\r
+ Status = CAN_NOT_OK;\r
+ break;\r
+ }\r
+ }\r
+ /* Reset Control Register */\r
+ CanRegs[Controller]->CTL = RegBuf;\r
+ ControllerMode[Controller] = CANIF_CS_SLEEP;\r
+ break;\r
+\r
+ case CAN_T_WAKEUP:\r
+ /* Clear PDR Bit */\r
+ CanRegs[Controller]->CTL &= ~0x01000000;\r
+ ControllerMode[Controller] = CANIF_CS_STOPPED;\r
+ break;\r
+\r
+ default:\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ /* Invalid Transition */\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 3, CAN_E_TRANSITION);\r
+ return CAN_NOT_OK;\r
+#endif\r
+ break;\r
+ }\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+void Can_DisableControllerInterrupts(uint8 Controller)\r
+{\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 4, CAN_E_UNINIT);\r
+ return;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 4, CAN_E_PARAM_CONTROLLER);\r
+ return;\r
+ }\r
+#endif \r
+ /* Clear IE */\r
+ CanRegs[Controller]->CTL &= ~DCAN_IRQ_MASK;\r
+ /* Increment Disable Counter */\r
+ IntDisableCount[Controller]++;\r
+}\r
+\r
+void Can_EnableControllerInterrupts(uint8 Controller)\r
+{\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 5, CAN_E_UNINIT);\r
+ return;\r
+ }\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 5, CAN_E_PARAM_CONTROLLER);\r
+ return;\r
+ }\r
+#endif \r
+ if(IntDisableCount[Controller] > 0)\r
+ {\r
+ if(IntDisableCount[Controller] == 1)\r
+ {\r
+ /* Set IE */\r
+ CanRegs[Controller]->CTL |= DCAN_IRQ_MASK;\r
+ }\r
+ IntDisableCount[Controller]--;\r
+ }\r
+}\r
+\r
+\r
+void Can_Cbk_CheckWakeup(uint8 Controller)\r
+{\r
+ /* TODO not supported yet.\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(Controller >= CAN_ARC_CTRL_CONFIG_CNT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 0x0B, CAN_E_PARAM_CONTROLLER);\r
+ return CAN_NOT_OK;\r
+ }\r
+#endif\r
+ // Check WakeUpPending\r
+ if(CanRegs[Controller]->SR & 0x00000200)\r
+ {\r
+ return E_OK;\r
+ }\r
+ else\r
+ {\r
+ return E_NOT_OK;\r
+ }\r
+ */\r
+}\r
+\r
+\r
+Can_ReturnType Can_Write(Can_Arc_HTHType Hth, Can_PduType *PduInfo)\r
+{\r
+ uint8 ControllerId;\r
+ uint8 MsgNr;\r
+ uint32 ArbRegValue;\r
+ uint8 DataByteIndex;\r
+ uint8 *CurSduPtr;\r
+ Can_PduType *CurPduArrayPtr;\r
+ uint8 *CurCancelRqstPtr;\r
+ uint8 *CurTxRqstPtr;\r
+\r
+ CurSduPtr = PduInfo->sdu;\r
+ \r
+\r
+/* DET Error Check */\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(PduInfo == NULL || PduInfo->sdu == NULL)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_POINTER);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(ModuleState == CAN_UNINIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_UNINIT);\r
+ return CAN_NOT_OK;\r
+ }\r
+ if(PduInfo->length > 8)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_DLC);\r
+ return CAN_NOT_OK; \r
+ }\r
+#endif\r
+\r
+ ControllerId = Can_FindControllerId(Hth);\r
+ \r
+ const Can_HardwareObjectType *hoh = Can_FindTxHoh(Hth);\r
+\r
+#if(CAN_DEV_ERROR_DETECT == STD_ON)\r
+ if(hoh->CanObjectType != CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ Det_ReportError(CAN_MODULE_ID, CAN_INSTANCE, 6, CAN_E_PARAM_HANDLE);\r
+ return CAN_NOT_OK;\r
+ }\r
+#endif\r
+ uint64 mbMask = hoh->Can_Arc_MbMask;\r
+ MsgNr = 0;\r
+ for(; mbMask != 0; mbMask >>= 1) {\r
+ MsgNr++;\r
+ if (!(mbMask & 1)) {\r
+ continue; // This message object is not part of this hoh.\r
+ }\r
+ /* Check if TxRqst Bit of MsgObject is set */\r
+ if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F)))\r
+ {\r
+ continue;\r
+ }\r
+ break;\r
+ }\r
+\r
+ /* Check if TxRqst Bit of MsgObject is set */\r
+ if(CanRegs[ControllerId]->TRx[MsgNr >> 5] & (1 << (MsgNr & 0x1F)))\r
+ {\r
+ return CAN_BUSY;\r
+ }\r
+\r
+ CurPduArrayPtr = ControllerConfig[ControllerId].PduPtr + (MsgNr - 1);\r
+ CurCancelRqstPtr = ControllerConfig[ControllerId].CancelPtr + (MsgNr - 1);\r
+ CurTxRqstPtr = ControllerConfig[ControllerId].TxPtr + (MsgNr - 1);\r
+ \r
+ /* Bring Id Value to appropriate format and set ArbRegValue */\r
+ if( hoh->CanIdType == CAN_ID_TYPE_EXTENDED ) {\r
+ /* MsgVal, Ext, Transmit, Extended Id */ \r
+ ArbRegValue = 0xE0000000 | (PduInfo->id & 0x1FFFFFFF);\r
+ } else {\r
+ /* MsgVal, Std, Transmit, Standard Id */ \r
+ ArbRegValue = 0xA0000000 | ((PduInfo->id & 0x7FF) << 18);\r
+ }\r
+\r
+\r
+ DCAN_WAIT_UNTIL_NOT_BUSY(ControllerId, IfRegId);\r
+\r
+ // We cannot allow an interrupt or other task to play with the COM, MC and ARB registers here.\r
+ imask_t i_state = McuE_EnterCriticalSection();\r
+\r
+\r
+ /* Set NewDat, TxIE (dep on ControllerConfig), TxRqst, EoB and DLC */\r
+ CanRegs[ControllerId]->IFx[IfRegId].MC = 0x00000100 // Tx request\r
+ | 0x00000080 // Eob should be set to one for tx\r
+ | (0x000F & PduInfo->length) // Set DLC\r
+ | (CanControllerConfigData[ControllerId].CanTxProcessing << 1); // Tx confirmation interrupt enabled\r
+\r
+\r
+ /* Set ArbitrationRegister */\r
+ CanRegs[ControllerId]->IFx[IfRegId].ARB = ArbRegValue;\r
+\r
+ /* Set Databytes */\r
+ for(DataByteIndex = 0; DataByteIndex < PduInfo->length; DataByteIndex++)\r
+ {\r
+ CanRegs[ControllerId]->IFx[IfRegId].DATx[ElementIndex[DataByteIndex]] = *CurSduPtr++;\r
+ }\r
+\r
+ /* Start transmission to MessageRAM */\r
+ CanRegs[ControllerId]->IFx[IfRegId].COM = 0x00BF0000 | MsgNr;\r
+ \r
+ /* Save the PduInfo in PduArray, so that messages can be identified later */\r
+ *CurPduArrayPtr = *PduInfo;\r
+ /* TxRqstArray-Elements are used to identifiy transmitted objects in polling mode */\r
+ *CurTxRqstPtr = 1;\r
+ \r
+ IfRegId ^= 1;\r
+ \r
+ McuE_ExitCriticalSection(i_state);\r
+ return CAN_OK;\r
+}\r
+\r
+\r
+void Can_MainFunction_Write()\r
+{\r
+ // Not supported\r
+}\r
+\r
+void Can_MainFunction_Read()\r
+{\r
+ // Not supported\r
+}\r
+\r
+void Can_MainFunction_BusOff()\r
+{\r
+ // Not supported\r
+}\r
+\r
+void Can_MainFunction_Wakeup()\r
+{\r
+ // Not supported\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Dio.h"\r
+#include "Det.h"\r
+#include "Cpu.h"\r
+#include <string.h>\r
+\r
+GIO_RegisterType *GPIO_ports[] = { GIO_PORTA_BASE, GIO_PORTB_BASE };\r
+\r
+#define DIO_GET_PORT_FROM_CHANNEL_ID(_channelId) (_channelId >> 8)\r
+#define DIO_GET_BIT_FROM_CHANNEL_ID(_channelId) (1 << (_channelId & 0x1F))\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+static int Channel_Config_Contains(Dio_ChannelType channelId)\r
+{\r
+ Dio_ChannelType* ch_ptr=(Dio_ChannelType*)(&DioChannelConfigData);\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*ch_ptr)\r
+ {\r
+ if (*ch_ptr==channelId)\r
+ {\r
+ rv=1;\r
+ break;\r
+ }\r
+ ch_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Port_Config_Contains(Dio_PortType portId)\r
+{\r
+ Dio_PortType* port_ptr=(Dio_PortType*)(&DioPortConfigData);\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*port_ptr)\r
+ {\r
+ if (*port_ptr==portId)\r
+ { rv=1; break;}\r
+ port_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Channel_Group_Config_Contains(const Dio_ChannelGroupType* _channelGroupIdPtr)\r
+{\r
+ Dio_ChannelGroupType* chGrp_ptr=(Dio_ChannelGroupType*)(&DioConfigData);\r
+ int rv=0;\r
+\r
+ while (DIO_END_OF_LIST!=chGrp_ptr->port)\r
+ {\r
+ if (chGrp_ptr->port==_channelGroupIdPtr->port&&\r
+ chGrp_ptr->offset==_channelGroupIdPtr->offset&&\r
+ chGrp_ptr->mask==_channelGroupIdPtr->mask)\r
+ { rv=1; break;}\r
+ chGrp_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+#define VALIDATE_CHANNEL(_channelId, _api) \\r
+ if(0==Channel_Config_Contains(channelId)) { \\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_CHANNEL_ID ); \\r
+ level = 0; \\r
+ goto cleanup; \\r
+ }\r
+#define VALIDATE_PORT(_portId, _api)\\r
+ if(0==Port_Config_Contains(_portId)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_PORT_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\\r
+ if(0==Channel_Group_Config_Contains(_channelGroupIdPtr)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_GROUP_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#else\r
+#define VALIDATE_CHANNEL(_channelId, _api)\r
+#define VALIDATE_PORT(_portId, _api)\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\r
+#endif\r
+\r
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId)\r
+{\r
+ Dio_PortLevelType level = 0;\r
+ VALIDATE_PORT(portId, DIO_READPORT_ID);\r
+\r
+ level = (uint8)GPIO_ports[portId]->DIN;\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
+}\r
+\r
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level)\r
+{\r
+ VALIDATE_PORT(portId, DIO_WRITEPORT_ID);\r
+\r
+ GPIO_ports[portId]->DOUT = (uint32)level;\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
+\r
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNEL(channelId, DIO_READCHANNEL_ID);\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId));\r
+ Dio_PortLevelType bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if ((portVal & bit) != STD_LOW){\r
+ level = STD_HIGH;\r
+ } else{\r
+ level = STD_LOW;\r
+ }\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return (level);\r
+}\r
+\r
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level)\r
+{\r
+ VALIDATE_CHANNEL(channelId, DIO_WRITECHANNEL_ID);\r
+\r
+ Dio_PortType port = DIO_GET_PORT_FROM_CHANNEL_ID(channelId);\r
+ uint16 bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if (!( GPIO_ports[port]->DIR & bit)) { // This is an input channel.\r
+ goto cleanup;\r
+ }\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(port);\r
+\r
+ if(level == STD_HIGH){\r
+ portVal |= bit;\r
+ }else{\r
+ portVal &= ~bit;\r
+ }\r
+\r
+ Dio_WritePort(port, portVal);\r
+\r
+ cleanup: return;\r
+}\r
+\r
+\r
+Dio_PortLevelType Dio_ReadChannelGroup(\r
+ const Dio_ChannelGroupType *channelGroupIdPtr)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_READCHANNELGROUP_ID);\r
+\r
+ // Get masked values\r
+ level = Dio_ReadPort(channelGroupIdPtr->port) & channelGroupIdPtr->mask;\r
+\r
+ // Shift down\r
+ level = level >> channelGroupIdPtr->offset;\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
+}\r
+\r
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr,\r
+ Dio_PortLevelType level)\r
+{\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_WRITECHANNELGROUP_ID);\r
+\r
+ // Shift up and apply mask so that no unwanted bits are affected\r
+ level = (level << channelGroupIdPtr->offset) & channelGroupIdPtr->mask;\r
+\r
+ // Read port and clear out masked bits\r
+ Dio_PortLevelType portVal = Dio_ReadPort(channelGroupIdPtr->port) & (~channelGroupIdPtr->mask);\r
+\r
+ // Or in the upshifted masked level\r
+ portVal |= level;\r
+\r
+ Dio_WritePort(channelGroupIdPtr->port, portVal);\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Mcu.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#include <assert.h>\r
+#include "Cpu.h"\r
+#include <string.h>\r
+#include "Ramlog.h"\r
+\r
+#include "core_cr4.h"\r
+\r
+//#define USE_LDEBUG_PRINTF 1\r
+#include "debug.h"\r
+\r
+/* PLLCTL1 register */\r
+#define MCU_RESET_ON_SLIP 0 // Reset on slip is off\r
+#define MCU_RESET_ON_SLIP_OFFSET 31 // Offset in PLLCTL1\r
+\r
+#define MCU_BYPASS_ON_SLIP 2 // Bypass on slip is off\r
+#define MCU_BYPASS_ON_SLIP_OFFSET 29 // Offset in PLLCTL1 (2 bits)\r
+\r
+#define MCU_RESET_ON_OSC_FAIL 0 // Reset on oscillator fail is off\r
+#define MCU_RESET_ON_OSC_FAIL_OFFSET 23 // Offset in PLLCTL1\r
+\r
+#define MCU_PLLDIV_OFFSET 24 // Offset in PLLCTL1 (5 bits)\r
+#define MCU_PLLDIV_MASK (0x1F << MCU_PLLDIV_OFFSET)\r
+#define MCU_REFCLKDIV_OFFSET 16 // Offset in PLLCTL1 (6 bits)\r
+#define MCU_REFCLKDIV_MASK (0x3F << MCU_REFCLKDIV_OFFSET)\r
+#define MCU_PLLMUL_OFFSET 0 // Offset in PLLCTL1 (16 bits)\r
+#define MCU_PLLMUL_MASK (0xFFFF << MCU_PLLMUL_OFFSET)\r
+\r
+/* PLLCTL2 register */\r
+#define MCU_FM_ENABLE 0 // Frequency modulation is off\r
+#define MCU_FM_ENABLE_OFFSET 31 // Offset in PLLCTL2\r
+\r
+#define MCU_SPREADING_RATE 0 // Spreading rate\r
+#define MCU_SPREADING_RATE_OFFSET 22 // Offset in PLLCTL2 (9 bits)\r
+\r
+#define MCU_BWADJ 0 // Bandwidth adjustment\r
+#define MCU_BWADJ_OFFSET 12 // Offset in PLLCTL2 (9 bits)\r
+\r
+#define MCU_ODPLL_OFFSET 9 // Offset in PLLCTL2 (3 bits)\r
+#define MCU_ODPLL_MASK (0x7 << MCU_ODPLL_OFFSET)\r
+\r
+#define MCU_SPREADING_AMOUNT 0 // Spreading amount\r
+#define MCU_SPREADING_AMOUT_OFFSET 0 // Offset in PLLCTL2 (9 bits)\r
+\r
+\r
+/* CSDIS (Clock source disable) register offsets */\r
+#define MCU_CLK_SOURCE_OSC_OFFSET 0\r
+#define MCU_CLK_SOURCE_FMZPLL_OFFSET 1\r
+#define MCU_CLK_SOURCE_LPO_OFFSET 4\r
+#define MCU_CLK_SOURCE_HPO_OFFSET 5\r
+#define MCU_CLK_SOURCE_FPLL_OFFSET 6\r
+\r
+\r
+#ifndef ARRAY_SIZE\r
+#define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))\r
+#endif\r
+\r
+/* Development error macros. */\r
+#if ( MCU_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_MCU,0,_api,_err); \\r
+ return (_rv); \\r
+ }\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_W_RV(_exp,_api,_err,_rv )\r
+#endif\r
+\r
+\r
+#define CORE_CPUID_CORTEX_M3 0x411FC231UL\r
+\r
+typedef struct {\r
+ uint32 lossOfLockCnt;\r
+ uint32 lossOfClockCnt;\r
+} Mcu_Stats;\r
+\r
+\r
+\r
+\r
+\r
+\r
+/**\r
+ * Type that holds all global data for Mcu\r
+ */\r
+typedef struct\r
+{\r
+ // Set if Mcu_Init() have been called\r
+ boolean initRun;\r
+\r
+ // Our config\r
+ const Mcu_ConfigType *config;\r
+\r
+ Mcu_ClockType clockSetting;\r
+\r
+ Mcu_Stats stats;\r
+\r
+} Mcu_GlobalType;\r
+\r
+\r
+// Global config\r
+Mcu_GlobalType Mcu_Global =\r
+{\r
+ .initRun = 0,\r
+ .config = &McuConfigData[0],\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} core_info_t;\r
+\r
+typedef struct {\r
+ char *name;\r
+ uint32 pvr;\r
+} cpu_info_t;\r
+\r
+\r
+void Mcu_ConfigureFlash(void);\r
+\r
+\r
+\r
+/* Haven't found any ID accessable from memory.\r
+ * There is the DBGMCU_IDCODE (0xe0042000) found in RM0041 but it\r
+ * you can't read from that address..\r
+ */\r
+#if 0\r
+cpu_info_t cpu_info_list[] = {\r
+ {\r
+ .name = "????",\r
+ .pvr = 0,\r
+ },\r
+};\r
+#endif\r
+\r
+/* The supported cores\r
+ */\r
+core_info_t core_info_list[] = {\r
+ {\r
+ .name = "CORE_ARM_CORTEX_M3",\r
+ .pvr = CORE_CPUID_CORTEX_M3,\r
+ },\r
+};\r
+\r
+/**\r
+ * Identify the core, just to check that we have support for it.\r
+ *\r
+ * @return\r
+ */\r
+static uint32 Mcu_CheckCpu( void ) {\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * Initialize Peripherals clocks\r
+ */\r
+static void InitPerClocks()\r
+{\r
+\r
+}\r
+\r
+/**\r
+ * Initialize Flash, PLL and clocks.\r
+ */\r
+static void InitMcuClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+\r
+ // INTCLK 1.63MHz - 6.53MHz\r
+ // NR (REFCLKDIV) 1 - 64\r
+ // INTCLK = CLKIN / REFCLKDIV;\r
+\r
+ // Output CLK 120MHz - 500MHz\r
+ // NF (PLLMUL) 92 - 184\r
+ // OutputCLK = INTCLK * PLLMUL;\r
+\r
+ // OD (ODPLL) 1 - 8\r
+ // R (PLLDIV) 1 - 32\r
+ // PLLCLK = OutputCLK / ODPLL / PLLDIV;\r
+\r
+ // Algorithm\r
+ // PLLCLK = (CLKIN * PLLMUL) / (REFCLKDIV * ODPLL * PLLDIV);\r
+\r
+\r
+ /** - Setup pll control register 1:\r
+ * - Setup reset on oscillator slip\r
+ * - Setup bypass on pll slip\r
+ * - Setup reset on oscillator fail\r
+ * - Setup Pll output clock divider\r
+ * - Setup reference clock divider\r
+ * - Setup Pll multiplier*\r
+ */\r
+ systemREG1->PLLCTL1 =\r
+ (MCU_RESET_ON_SLIP << MCU_RESET_ON_SLIP_OFFSET)\r
+ | (MCU_BYPASS_ON_SLIP << MCU_BYPASS_ON_SLIP_OFFSET)\r
+ | (MCU_RESET_ON_OSC_FAIL << MCU_RESET_ON_OSC_FAIL_OFFSET)\r
+ | ((clockSettingsPtr->Pll1 - 1) << MCU_REFCLKDIV_OFFSET)\r
+ | (((clockSettingsPtr->Pll2 - 1) * 256) << MCU_PLLMUL_OFFSET)\r
+ | ((clockSettingsPtr->Pll4 - 1) << MCU_PLLDIV_OFFSET);\r
+\r
+\r
+ /** Setup PLLCTL2\r
+ * - Setup internal Pll output divider\r
+ * - Enable/Disable frequency modulation (NOT USED)\r
+ * - Setup spreading rate (NOT USED)\r
+ * - Setup bandwidth adjustment (NOT USED)\r
+ * - Setup spreading amount (NOT USED)\r
+ */\r
+ systemREG1->PLLCTL2 =\r
+ (MCU_FM_ENABLE << MCU_FM_ENABLE_OFFSET)\r
+ | (MCU_SPREADING_RATE << MCU_SPREADING_RATE_OFFSET)\r
+ | (MCU_BWADJ << MCU_BWADJ_OFFSET)\r
+ | (MCU_SPREADING_AMOUNT << MCU_SPREADING_AMOUT_OFFSET)\r
+ | ((clockSettingsPtr->Pll3 - 1) << MCU_ODPLL_OFFSET);\r
+\r
+ /** - Wait for until clocks are locked */\r
+ while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF));\r
+\r
+\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_Init(const Mcu_ConfigType *configPtr)\r
+{\r
+ VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
+\r
+#if !defined(USE_SIMULATOR)\r
+ Mcu_CheckCpu();\r
+#endif\r
+\r
+ memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
+\r
+ /** Enable/Disable the right clocks\r
+ * 0 = enable, 1 = disable */\r
+ systemREG1->CSDIS =\r
+ (0 << MCU_CLK_SOURCE_OSC_OFFSET)\r
+ | (0 << MCU_CLK_SOURCE_FMZPLL_OFFSET)\r
+ | (1 << MCU_CLK_SOURCE_LPO_OFFSET)\r
+ | (0 << MCU_CLK_SOURCE_HPO_OFFSET)\r
+ | (1 << MCU_CLK_SOURCE_FPLL_OFFSET);\r
+\r
+\r
+ /** - Wait for until clocks are locked */\r
+ while ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF));\r
+\r
+ /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */\r
+ systemREG1->GHVSRC = (SYS_PLL << 24U) // Selectes PLL clock (clock source 1) as wakeup clock source.\r
+ | (SYS_PLL << 16U) // Select PLL clock (clock source 1) as wakeup when GCLK is off as clock source.\r
+ | SYS_PLL; // Select PLL clock (clock source 1) as current clock source.\r
+\r
+ /** - Power-up clocks to all peripharals */\r
+ pcrREG->PSPWRDWNCLR0 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR1 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR2 = 0xFFFFFFFFU;\r
+ pcrREG->PSPWRDWNCLR3 = 0xFFFFFFFFU;\r
+\r
+ /** - Setup synchronous peripheral clock dividers for VCLK1 and VCLK2\r
+ * 1 = divide by 2\r
+ */\r
+ systemREG1->VCLKR = 1U;\r
+ systemREG1->VCLK2R = 1U;\r
+\r
+ /** - Setup RTICLK1 and RTICLK2 clocks */\r
+ systemREG1->RCLKSRC = (0U << 24U) // RTICLK2 divider is 1\r
+ | (SYS_VCLK << 16U) // Select VCLK as source for RTICLK2.\r
+ | (0U << 8U) // RTICLK2 divider is 1\r
+ | SYS_VCLK; // Select VCLK as source for RTICLK1.\r
+\r
+ /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */\r
+ systemREG1->VCLKASRC = (SYS_VCLK << 8U)\r
+ | SYS_VCLK;\r
+\r
+ /** - Enable Peripherals */\r
+ systemREG1->PENA = 1U;\r
+\r
+ Mcu_Global.config = configPtr;\r
+ Mcu_Global.initRun = 1;\r
+}\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DeInit()\r
+{\r
+ Mcu_Global.initRun = FALSE;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)\r
+{\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );\r
+\r
+ /* NOT SUPPORTED, reason: no support for external RAM */\r
+\r
+ return E_NOT_OK;\r
+}\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+\r
+Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)\r
+{\r
+ Mcu_ClockSettingConfigType *clockSettingsPtr;\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );\r
+ VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );\r
+\r
+ Mcu_Global.clockSetting = ClockSetting;\r
+ clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
+\r
+ InitMcuClocks(clockSettingsPtr);\r
+ InitPerClocks(clockSettingsPtr);\r
+\r
+ return E_OK;\r
+\r
+\r
+\r
+\r
+\r
+ return E_OK;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_DistributePllClock(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+\r
+Mcu_PllStatusType Mcu_GetPllStatus(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );\r
+\r
+ if ((systemREG1->CSVSTAT & ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) != ((systemREG1->CSDIS ^ 0xFF) & 0xFF)) {\r
+ return MCU_PLL_UNLOCKED;\r
+ }\r
+\r
+ return MCU_PLL_LOCKED;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ *\r
+ * @return\r
+ */\r
+Mcu_ResetType Mcu_GetResetReason(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );\r
+ Mcu_ResetType reason = MCU_RESET_UNDEFINED;\r
+\r
+ if (systemREG1->SYSESR & 0x00008000) {\r
+ reason = MCU_POWER_ON_RESET;\r
+ systemREG1->SYSESR = 0x00008000;\r
+ } else if (systemREG1->SYSESR & 0x00004000) {\r
+ reason = MCU_OSC_FAILURE_RESET;\r
+ systemREG1->SYSESR = 0x00004000;\r
+ } else if (systemREG1->SYSESR & 0x00002000) {\r
+ reason = MCU_WATCHDOG_RESET;\r
+ systemREG1->SYSESR = 0x00002000;\r
+ } else if (systemREG1->SYSESR & 0x00000020) {\r
+ reason = MCU_CPU_RESET;\r
+ systemREG1->SYSESR = 0x00000020;\r
+ } else if (systemREG1->SYSESR & 0x00000010) {\r
+ reason = MCU_SW_RESET;\r
+ systemREG1->SYSESR = 0x00000010;\r
+ } else if (systemREG1->SYSESR & 0x00000008) {\r
+ reason = MCU_EXT_RESET;\r
+ systemREG1->SYSESR = 0x00000008;\r
+ } else if (systemREG1->SYSESR & 0x00000004) {\r
+ reason = MCU_VSW_RESET;\r
+ systemREG1->SYSESR = 0x00000004;\r
+ } else {\r
+ reason = MCU_RESET_UNDEFINED;\r
+ }\r
+\r
+/* USER CODE BEGIN (23) */\r
+/* USER CODE END */\r
+\r
+ return reason;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * Shall read the raw reset value from hardware register if the hardware\r
+ * supports this.\r
+ *\r
+ * @return\r
+ */\r
+\r
+Mcu_RawResetType Mcu_GetResetRawValue(void) {\r
+ VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );\r
+\r
+ Mcu_RawResetType reason = 0xFFFFFFFF;\r
+ reason = systemREG1->SYSESR & 0x0000E03B;\r
+ systemREG1->SYSESR = 0x0000E03B;\r
+\r
+ return reason;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( MCU_PERFORM_RESET_API == STD_ON )\r
+/**\r
+ * Shell perform a microcontroller reset by using the hardware feature\r
+ * of the micro controller.\r
+ */\r
+void Mcu_PerformReset(void)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );\r
+ systemREG1->SYSECR = 0x00008000;\r
+}\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+void Mcu_SetMode(const Mcu_ModeType McuMode)\r
+{\r
+ VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * Get the system clock in Hz. It calculates the clock from the\r
+ * different register settings in HW.\r
+ */\r
+uint32_t McuE_GetSystemClock(void)\r
+{\r
+ uint32_t f_sys;\r
+\r
+ // PLLCLK = (CLKIN * PLLMUL) / (REFCLKDIV * ODPLL * PLLDIV);\r
+\r
+ uint32 odpll = ((systemREG1->PLLCTL2 & MCU_ODPLL_MASK) >> MCU_ODPLL_OFFSET) + 1;\r
+ uint32 plldiv = ((systemREG1->PLLCTL1 & MCU_PLLDIV_MASK) >> MCU_PLLDIV_OFFSET) + 1;\r
+ uint32 refclkdiv = ((systemREG1->PLLCTL1 & MCU_REFCLKDIV_MASK) >> MCU_REFCLKDIV_OFFSET) + 1;\r
+ uint32 pllmult = (((systemREG1->PLLCTL1 & MCU_PLLMUL_MASK) >> MCU_PLLMUL_OFFSET) / 256) + 1;\r
+\r
+ f_sys = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;\r
+ f_sys = f_sys * pllmult / (refclkdiv * odpll * plldiv);\r
+\r
+ return f_sys;\r
+}\r
+\r
+imask_t McuE_EnterCriticalSection()\r
+{\r
+ imask_t state;\r
+ Irq_Save(state);\r
+ return state;\r
+}\r
+\r
+void McuE_ExitCriticalSection(uint32_t old_state)\r
+{\r
+ Irq_Restore(old_state);\r
+}\r
+\r
+/**\r
+ * Get the peripheral clock in Hz for a specific device\r
+ */\r
+uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
+{\r
+ if (type == PERIPHERAL_CLOCK_CAN) {\r
+ uint8 vclockDiv = systemREG1->VCLKR;\r
+ return McuE_GetSystemClock() / (vclockDiv + 1);\r
+ }\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * Function to setup the internal flash for optimal performance\r
+ */\r
+void Mcu_ConfigureFlash(void)\r
+{\r
+\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Port.h"\r
+#include "Det.h"\r
+#include "Cpu.h"\r
+#include <string.h>\r
+\r
+#define GET_PIN_PORT(_pin) (_pin >> 8)\r
+#define GET_PIN_PIN(_pin) (_pin & 0x1F)\r
+#define GET_PIN_MASK(_pin) (1 << (_pin & 0x1F))\r
+\r
+typedef enum\r
+{\r
+ PORT_UNINITIALIZED = 0, PORT_INITIALIZED,\r
+} Port_StateType;\r
+\r
+\r
+typedef volatile struct\r
+{\r
+ uint32 FUN;\r
+ uint32 DIR;\r
+ uint32 DIN;\r
+ uint32 DOUT;\r
+ uint32 DSET;\r
+ uint32 DCLR;\r
+ uint32 PDR;\r
+ uint32 PULDIS;\r
+ uint32 PSL;\r
+} Port_RegisterType;\r
+\r
+\r
+#define PORT_NOT_CONFIGURED 0x00000000\r
+\r
+#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30)\r
+#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50)\r
+#define PORT_2_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_3_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_4_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_5_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_6_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_7_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
+#define PORT_8_BASE ((Port_RegisterType *)0xFFF7DDE0)\r
+#define PORT_9_BASE ((Port_RegisterType *)0xFFF7DFE0)\r
+#define PORT_10_BASE ((Port_RegisterType *)0xFFF7E1E0)\r
+#define PORT_NUMBER_OF_PORTS 11\r
+\r
+static Port_RegisterType * const Port_Base[] =\r
+{\r
+ PORT_0_BASE,\r
+ PORT_1_BASE,\r
+ PORT_2_BASE,\r
+ PORT_3_BASE,\r
+ PORT_4_BASE,\r
+ PORT_5_BASE,\r
+ PORT_6_BASE,\r
+ PORT_7_BASE,\r
+ PORT_8_BASE,\r
+ PORT_9_BASE,\r
+ PORT_10_BASE,\r
+};\r
+\r
+\r
+\r
+static Port_StateType _portState = PORT_UNINITIALIZED;\r
+static const Port_ConfigType * _configPtr = &PortConfigData;\r
+\r
+#if PORT_DEV_ERROR_DETECT == STD_ON\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api) \\r
+ if( (_ptr)==((void *)0) ) { \\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_CONFIG ); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_STATE_INIT(_api)\\r
+ if(PORT_INITIALIZED!=_portState){\\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_UNINIT ); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_PARAM_PIN(_pin, _api)\\r
+ if(GET_PIN_PORT(_pin) >= PORT_NUMBER_OF_PORTS || Port_Base[GET_PIN_PORT(_pin)] == PORT_NOT_CONFIGURED || GET_PIN_PIN(_pin) > 7 ){\\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_PIN ); \\r
+ return; \\r
+ }\r
+\r
+#else\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api)\r
+#define VALIDATE_STATE_INIT(_api)\r
+#define VALIDATE_PARAM_PIN(_pin, _api)\r
+#endif\r
+\r
+#if PORT_VERSION_INFO_API == STD_ON\r
+static Std_VersionInfoType _Port_VersionInfo =\r
+{\r
+ .vendorID = (uint16)1,\r
+ .moduleID = (uint16) MODULE_ID_PORT,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)PORT_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)PORT_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)PORT_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)PORT_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)PORT_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)PORT_AR_PATCH_VERSION,\r
+};\r
+#endif\r
+\r
+void Port_RefreshPin(uint16 pinNumber) {\r
+ uint8 port = GET_PIN_PORT(_configPtr->pins[pinNumber].pin);\r
+ uint32 mask = GET_PIN_MASK(_configPtr->pins[pinNumber].pin);\r
+ uint16 conf = _configPtr->pins[pinNumber].conf;\r
+\r
+ if (conf & PORT_FUNC) {\r
+ // Don't do anything, let each driver configure???\r
+ return;\r
+ }\r
+\r
+ // Set pin direction\r
+ if (conf & PORT_PIN_OUT) {\r
+ Port_Base[port]->DIR |= mask;\r
+\r
+ // Set open drain\r
+ if (conf & PORT_ODE_ENABLE) {\r
+ Port_Base[port]->PDR |= mask;\r
+ } else {\r
+ Port_Base[port]->PDR &= ~mask;\r
+ }\r
+\r
+ } else {\r
+ Port_Base[port]->DIR &= ~mask;\r
+ }\r
+\r
+ // Set pull up or down or nothing.\r
+ if (conf & PORT_PULL_NONE) {\r
+ Port_Base[port]->PULDIS |= mask;\r
+\r
+ } else {\r
+ Port_Base[port]->PULDIS &= ~mask;\r
+ if (conf & PORT_PULL_UP) {\r
+ Port_Base[port]->PSL |= mask;\r
+\r
+ } else {\r
+ Port_Base[port]->PSL &= ~mask;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+\r
+void Port_Init(const Port_ConfigType *configType) {\r
+ VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);\r
+\r
+ _configPtr = (Port_ConfigType *)configType;\r
+\r
+ // Bring GIO register out of reset.\r
+ gioREG->GCR0 = 1;\r
+\r
+ for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {\r
+ Port_RefreshPin(i);\r
+ }\r
+\r
+ _portState = PORT_INITIALIZED;\r
+\r
+ return;\r
+}\r
+\r
+#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )\r
+void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
+ VALIDATE_PARAM_PIN(pin, PORT_SET_PIN_DIRECTION_ID);\r
+\r
+ uint8 port = GET_PIN_PORT(pin);\r
+ uint32 mask = GET_PIN_MASK(pin);\r
+\r
+ if (direction & PORT_PIN_IN) {\r
+ Port_Base[port]->DIR |= mask;\r
+\r
+ } else {\r
+ Port_Base[port]->DIR &= ~mask;\r
+\r
+ }\r
+\r
+ return;\r
+}\r
+#endif\r
+\r
+void Port_RefreshPortDirection( void )\r
+{\r
+ VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);\r
+ for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {\r
+ if (!(_configPtr->pins[i].conf & PORT_DIRECTION_CHANGEABLE)) {\r
+ Port_RefreshPin(i);\r
+ }\r
+ }\r
+ return;\r
+}\r
+\r
+\r
+#if PORT_VERSION_INFO_API == STD_ON\r
+void Port_GetVersionInfo(Std_VersionInfoType* versionInfo)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_GET_VERSION_INFO_ID);\r
+ memcpy(versionInfo, &_Port_VersionInfo, sizeof(Std_VersionInfoType));\r
+ return;\r
+}\r
+#endif\r
+\r
+#if (PORT_SET_PIN_MODE_API == STD_ON)\r
+void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode) {\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
+ VALIDATE_PARAM_PIN(Pin, PORT_SET_PIN_MODE_ID);\r
+\r
+ uint8 port = GET_PIN_PORT(Pin);\r
+ uint8 pin = GET_PIN_PIN(Pin);\r
+ uint32 mask = GET_PIN_MASK(Pin);\r
+\r
+ Port_Base[port]->FUN &= ~mask;\r
+ Port_Base[port]->FUN |= ((Mode & 1) << pin);\r
+ return;\r
+}\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "internal.h"\r
+#include "stack.h"\r
+#include "core_cr4.h"\r
+\r
+\r
+/**\r
+ * Function make sure that we switch to supervisor mode(rfi) before\r
+ * we call a task for the first time.\r
+ */\r
+\r
+void Os_ArchFirstCall( void )\r
+{\r
+ // TODO: make switch here... for now just call func.\r
+ Irq_Enable();\r
+ os_sys.curr_pcb->entry();\r
+}\r
+\r
+void *Os_ArchGetStackPtr( void ) {\r
+\r
+ return (void *)0;\r
+}\r
+\r
+unsigned int Os_ArchGetScSize( void ) {\r
+ return SC_SIZE;\r
+}\r
+\r
+void Os_ArchSetTaskEntry(OsPcbType *pcbPtr ) {\r
+ // TODO: Add lots of things here, see ppc55xx\r
+ uint32_t *context = (uint32_t *)pcbPtr->stack.curr;\r
+\r
+ context[C_CONTEXT_OFFS/4] = SC_PATTERN;\r
+\r
+ /* Set LR to start function */\r
+ if( pcbPtr->proc_type == PROC_EXTENDED ) {\r
+ context[VGPR_LR_OFF/4] = (uint32_t)Os_TaskStartExtended;\r
+ } else if( pcbPtr->proc_type == PROC_BASIC ) {\r
+ context[VGPR_LR_OFF/4] = (uint32_t)Os_TaskStartBasic;\r
+ }\r
+\r
+}\r
+\r
+void Os_ArchSetupContext( OsPcbType *pcb ) {\r
+ // TODO: Add lots of things here, see ppc55xx\r
+ // uint32_t *context = (uint32_t *)pcb->stack.curr;\r
+\r
+}\r
+\r
+void Os_ArchInit( void ) {\r
+ // nothing to do here, yet :)\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#define _ASSEMBLER_\r
+#include "kernel_offset.h"\r
+#include "stack.h"\r
+\r
+.extern os_sys\r
+\r
+ .syntax unified\r
+ .cpu cortex-r4\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+ .section .text\r
+\r
+ .global Irq_Handler\r
+ .type Irq_Handler, %function\r
+ \r
+ .global Svc_Handler\r
+ .type Svc_Handler, %function \r
+\r
+ .global Data_Exc_Handler\r
+ .type Data_Exc_Handler, %function\r
+ \r
+ .global Prefetch_Exc_Handler\r
+ .type Prefetch_Exc_Handler, %function\r
+ \r
+ .global Dummy_Irq\r
+ .type Dummy_Irq, %function \r
+\r
+\r
+// Registers part of context.\r
+#define REG_SAVE r0-r12\r
+\r
+\r
+// A data exception handler. This let us put a breakpoint and return to the place where the exception was caught.\r
+// If DEBUG_EXCEPTIONS is off then just use the ordinary dummy irq.\r
+Data_Exc_Handler: \r
+#ifdef CFG_ARM_CR4_DEBUG_EXCEPTIONS\r
+ // Setup return address. This requires subtraction from LR.\r
+ sub lr, lr, #8\r
+ \r
+ // Store return stuff on system mode's stack\r
+ srsdb sp!, #31 // 31 = System mode\r
+ \r
+ // Switch to system mode.\r
+ cpsid i, #31 // 31 = system mode\r
+ \r
+ // Return using stuff from stack.\r
+ rfeia sp!\r
+#else\r
+ b Dummy_Irq\r
+#endif\r
+\r
+// A prefetch exception handler. This let us put a breakpoint and return to the place where the exception was caught.\r
+// If DEBUG_EXCEPTIONS is off then just use the ordinary dummy irq.\r
+Prefetch_Exc_Handler: \r
+#ifdef CFG_ARM_CR4_DEBUG_EXCEPTIONS \r
+\r
+ // Switch to system mode.\r
+ cpsid i, #31 // 31 = system mode\r
+ \r
+ // Setup return address. This requires subtraction from LR.\r
+ sub lr, lr, #4\r
+ \r
+ // Return to the place before the instruction that caused the interrupt.\r
+ MOVS PC, LR\r
+ \r
+#else\r
+ b Dummy_Irq\r
+#endif\r
+\r
+\r
+Irq_Handler:\r
+ // Setup return address. This requires subtraction from LR.\r
+ sub lr, lr, #4\r
+\r
+Svc_Handler:\r
+ // Store return stuff on system mode's stack\r
+ srsdb sp!, #31 // 31 = System mode\r
+ \r
+ // Switch to system mode.\r
+ cpsid i, #31 // 31 = system mode \r
+ \r
+ // Push registers on stack\r
+ push {REG_SAVE,lr}\r
+ \r
+ sub.w sp,sp,#C_SIZE\r
+ mov.w r4,#LC_PATTERN\r
+ str r4,[sp,#C_CONTEXT_OFFS]\r
+ \r
+ // Put stack as first arg to Irq_Entry \r
+ mov r0,sp \r
+ \r
+ // When at interrupt nest count = 0, load interrupt stack \r
+ ldr r4,=os_sys\r
+ ldr r5,[r4,#SYS_INT_NEST_CNT]\r
+ cmp r5, #0\r
+ bgt arggg\r
+ ldr sp,[r4,#SYS_INT_STACK] \r
+ \r
+arggg: \r
+ bl Irq_Entry\r
+ mov sp, r0 // pop from returned stack\r
+\r
+ /* Do a normal exception return */\r
+ add.w sp,sp,#C_SIZE\r
+ \r
+ // Restore registers\r
+ pop {REG_SAVE,lr}\r
+ \r
+ // Return using stuff from stack.\r
+ rfeia sp!\r
+ \r
+/**\r
+ * Fake an interrupt stack to be able to return to thread mode.\r
+ *\r
+ * Arm stack look like:\r
+ * xPSR\r
+ * PC\r
+ * LR\r
+ * r12\r
+ * r3\r
+ * r2\r
+ * r1\r
+ * r0\r
+ *\r
+ * Don't really know what bits matter on the xPSR here. Not setting\r
+ * the EPSR[T] is really bad since it will generate a INVSTATE exception.\r
+ */\r
+ .global Irq_EOI2\r
+ .type Irq_EOI2, %function\r
+\r
+Irq_EOI2:\r
+ mov.w r1,0x01000000 /* EPSR[T] bit */\r
+ mov r0,lr\r
+ push {r0,r1} /* Push PC and xPSR */\r
+ sub.w sp,sp,#(6*4) /* r0,r1,r2,r3, r12,lr,pc,xPSR */\r
+ mov.w lr,#0xfffffff9 /* interrupt return with stack=MSR */\r
+ bx lr /* do return */\r
+\r
+\r
+/**\r
+ * Os_ArchSetSpAndCall\r
+ *\r
+ * @param sp Pointer to the stack\r
+ * @param f Pointer to the function to call\r
+ */\r
+\r
+ .global Os_ArchSetSpAndCall\r
+ .type Os_ArchSetSpAndCall, %function\r
+Os_ArchSetSpAndCall:\r
+ mov.w sp,r0\r
+ mov.w lr,r1\r
+ bx lr\r
+\r
+/**\r
+ * Os_ArchSwapContext\r
+ *\r
+ * @param r0 - pcb for old task\r
+ * @param r1 - pcb for new task\r
+ *\r
+ * -------------- higher addr\r
+ * r4-r8,etc\r
+ * -------\r
+ * 4 - Large or Small context indicator\r
+ * 0 - ?\r
+ * ----------\r
+ *\r
+ */\r
+ .global Os_ArchSwapContext\r
+ .type Os_ArchSwapContext, %function\r
+Os_ArchSwapContext:\r
+ // Save function call registers\r
+ push {REG_SAVE,lr}\r
+\r
+ // Store the context frame\r
+ sub.w sp,sp,#C_SIZE\r
+\r
+ // Save small-context indicator\r
+ mov.w r4,#SC_PATTERN\r
+ str r4,[sp,#C_CONTEXT_OFFS]\r
+ // ---> We have saved NVGPR+C\r
+\r
+ // store old stack for old task\r
+ mov.w r4,sp\r
+ str r4,[r0,#PCB_STACK_CURR_P]\r
+\r
+ // Flow down\r
+ // R1 - new PCB\r
+ .global Os_ArchSwapContextTo\r
+ .type Os_ArchSwapContextTo, %function\r
+Os_ArchSwapContextTo:\r
+\r
+ // Get stack for new task\r
+ ldr r2,[r1,#PCB_STACK_CURR_P]\r
+ mov.w sp,r2\r
+ \r
+ // Set new current pcb\r
+ ldr r5,= os_sys\r
+ str r1,[r5,#SYS_CURR_PCB_P]\r
+\r
+ // Restore C context\r
+ ldr r6,[sp,#C_CONTEXT_OFFS]\r
+ cmp r6,#SC_PATTERN\r
+ beq os_sc_restore\r
+ cmp r6,#LC_PATTERN\r
+ beq os_lc_restore\r
+ \r
+os_stack_problem:\r
+// TODO: Jump to error handler\r
+ b os_stack_problem\r
+\r
+\r
+/* Restore the small context. Cases:\r
+ * - "Normal" context switch between processes.\r
+ * - We are in handler mode (this task preemted another task in interrupt\r
+ * context). We need to terminate handler mode ( set to LR=0xffff_fff9 )\r
+ * and\r
+ */\r
+os_sc_restore:\r
+ add.w sp,sp,#C_SIZE\r
+ pop {REG_SAVE,lr}\r
+ bx lr\r
+\r
+\r
+/* Restore the large context. Cases:\r
+ * 1. Directly from Irq_Handler()\r
+ * (the preempted task got swapped in directly)\r
+ * 2. The preempted task, got preemted by a task and\r
+ * we have already returned from handler mode.\r
+ *\r
+ * NOTE ! Only case 2 is covered here, case 1 is handled in Irq_Handler\r
+ * prologue\r
+ */\r
+ \r
+os_lc_restore:\r
+ /* Do a normal exception return */\r
+ add.w sp,sp,#C_SIZE\r
+ \r
+ // Restore registers\r
+ pop {REG_SAVE,lr}\r
+ \r
+ /* Enable interrupts */\r
+ //cpsie i \r
+\r
+ // Return using stuff from stack.\r
+ rfeia sp!\r
+\r
+ \r
+/* Interrupt routine used to catch unused interrupts and exceptions */\r
+Dummy_Irq:\r
+ /* Go back to sys mode for easier debugging.\r
+ Save link register*/\r
+ mov r3, lr\r
+ /* We don't want to use the IRQ mode\r
+ so swich back to sys mode. */\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ /* Restore link register again */\r
+ mov lr, r3\r
+ b Dummy_Irq\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+\r
+#define DECLARE(_sym,_val) \\r
+ __asm("#define " #_sym " %0 ": : "i" (_val))\r
+\r
+\r
+#include "stack.h"\r
+\r
+void arch_foo(void) {\r
+ /* StackNvgprType */\r
+ DECLARE(STACK_NVGPR_R4, offsetof(StackNvgprType, r4));\r
+ DECLARE(STACK_NVGPR_R5, offsetof(StackNvgprType, r5));\r
+ DECLARE(STACK_NVGPR_R6, offsetof(StackNvgprType, r6));\r
+ DECLARE(STACK_NVGPR_R7, offsetof(StackNvgprType, r7));\r
+ DECLARE(STACK_NVGPR_R8, offsetof(StackNvgprType, r8));\r
+ DECLARE(STACK_NVGPR_R10, offsetof(StackNvgprType, r10));\r
+ DECLARE(STACK_NVGPR_R11, offsetof(StackNvgprType, r11));\r
+ DECLARE(STACK_NVGPR_VA, offsetof(StackNvgprType, va));\r
+\r
+ /* StackCallAndContextType */\r
+}\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef CORE_CR4_H_\r
+#define CORE_CR4_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define __I volatile const /*!< defines 'read only' permissions */\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+typedef volatile struct vimBase\r
+{\r
+ unsigned : 24U; /* 0x0000 */\r
+ unsigned IRQIVEC : 8U; /* 0x0000 */\r
+ unsigned : 24U; /* 0x0004 */\r
+ unsigned FIQIVEC : 8U; /* 0x0004 */\r
+ unsigned : 32U; /* 0x0008 */\r
+ unsigned : 32U; /* 0x000C */\r
+ unsigned FIRQPR0; /* 0x0010 */\r
+ unsigned FIRQPR1; /* 0x0014 */\r
+ unsigned FIRQPR2; /* 0x0018 */\r
+ unsigned FIRQPR3; /* 0x001C */\r
+ unsigned INTREQ0; /* 0x0020 */\r
+ unsigned INTREQ1; /* 0x0024 */\r
+ unsigned INTREQ2; /* 0x0028 */\r
+ unsigned INTREQ3; /* 0x002C */\r
+ unsigned REQMASKSET0; /* 0x0030 */\r
+ unsigned REQMASKSET1; /* 0x0034 */\r
+ unsigned REQMASKSET2; /* 0x0038 */\r
+ unsigned REQMASKSET3; /* 0x003C */\r
+ unsigned REQMASKCLR0; /* 0x0040 */\r
+ unsigned REQMASKCLR1; /* 0x0044 */\r
+ unsigned REQMASKCLR2; /* 0x0048 */\r
+ unsigned REQMASKCLR3; /* 0x004C */\r
+ unsigned WAKEMASKSET0; /* 0x0050 */\r
+ unsigned WAKEMASKSET1; /* 0x0054 */\r
+ unsigned WAKEMASKSET2; /* 0x0058 */\r
+ unsigned WAKEMASKSET3; /* 0x005C */\r
+ unsigned WAKEMASKCLR0; /* 0x0060 */\r
+ unsigned WAKEMASKCLR1; /* 0x0064 */\r
+ unsigned WAKEMASKCLR2; /* 0x0068 */\r
+ unsigned WAKEMASKCLR3; /* 0x006C */\r
+ unsigned IRQVECREG; /* 0x0070 */\r
+ unsigned FIQVECREQ; /* 0x0074 */\r
+ unsigned : 9U; /* 0x0078 */\r
+ unsigned CAPEVTSRC1 : 7U; /* 0x0078 */\r
+ unsigned : 9U; /* 0x0078 */\r
+ unsigned CAPEVTSRC0 : 7U; /* 0x0078 */\r
+ unsigned : 32U; /* 0x007C */\r
+ unsigned char CHANMAP[64U]; /* 0x0080-0x017C */\r
+} vimBASE_t;\r
+\r
+#define vimREG ((vimBASE_t *)0xFFFFFE00U)\r
+\r
+\r
+\r
+typedef volatile struct rtiBase\r
+{\r
+ unsigned GCTRL; /**< 0x0000: Global Control Register */\r
+ unsigned TBCTRL; /**< 0x0004: Timebase Control Register */\r
+ unsigned CAPCTRL; /**< 0x0008: Capture Control Register */\r
+ unsigned COMPCTRL; /**< 0x000C: Compare Control Register */\r
+ struct\r
+ {\r
+ unsigned FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */\r
+ unsigned UCx; /**< 0x0014,0x0034: Up Counter x Register */\r
+ unsigned CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */\r
+ unsigned : 32; /**< 0x001C,0x003C: Reserved */\r
+ unsigned CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */\r
+ unsigned CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */\r
+ unsigned : 32; /**< 0x0028,0x0048: Reserved */\r
+ unsigned : 32; /**< 0x002C,0x004C: Reserved */\r
+ } CNT[2U]; /**< Counter x selection:\r
+ - 0: Counter 0\r
+ - 1: Counter 1 */\r
+ struct\r
+ {\r
+ unsigned COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */\r
+ unsigned UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */\r
+ } CMP[4U]; /**< Compare x selection:\r
+ - 0: Compare 0\r
+ - 1: Compare 1\r
+ - 2: Compare 2\r
+ - 3: Compare 3 */\r
+ unsigned TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */\r
+ unsigned TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */\r
+ unsigned : 32; /**< 0x0078: Reserved */\r
+ unsigned : 32; /**< 0x007C: Reserved */\r
+ unsigned SETINT; /**< 0x0080: Set/Status Interrupt Register */\r
+ unsigned CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */\r
+ unsigned INTFLAG; /**< 0x008C: Interrupt Flag Register */\r
+} rtiBASE_t;\r
+\r
+/** @def rtiREG1\r
+* @brief RTI1 Register Frame Pointer\r
+*\r
+* This pointer is used by the RTI driver to access the RTI1 registers.\r
+*/\r
+#define rtiREG1 ((rtiBASE_t *)0xFFFFFC00)\r
+\r
+\r
+enum systemClockSource\r
+{\r
+ SYS_OSC = 0, /**< Alias for oscillator clock Source */\r
+ SYS_PLL = 1, /**< Alias for Pll clock Source */\r
+ SYS_O32 = 2, /**< Alias for 32 kHz oscillator clock Source */\r
+ SYS_EXTERNAL = 3, /**< Alias for external clock Source */\r
+ SYS_LPO_LOW = 4, /**< Alias for low power oscillator low clock Source */\r
+ SYS_LPO_HIGH = 5, /**< Alias for low power oscillator high clock Source */\r
+ SYS_FR_PLL = 6, /**< Alias for flexray pll clock Source */\r
+ SYS_VCLK = 9 /**< Alias for synchronous VCLK1 clock Source */\r
+};\r
+\r
+typedef volatile struct systemBase1\r
+{\r
+ unsigned SYSPC1; /* 0x0000 */\r
+ unsigned SYSPC2; /* 0x0004 */\r
+ unsigned SYSPC3; /* 0x0008 */\r
+ unsigned SYSPC4; /* 0x000C */\r
+ unsigned SYSPC5; /* 0x0010 */\r
+ unsigned SYSPC6; /* 0x0014 */\r
+ unsigned SYSPC7; /* 0x0018 */\r
+ unsigned SYSPC8; /* 0x001C */\r
+ unsigned SYSPC9; /* 0x0020 */\r
+ unsigned SSWPLL1; /* 0x0024 */\r
+ unsigned SSWPLL2; /* 0x0028 */\r
+ unsigned SSWPLL3; /* 0x002C */\r
+ unsigned CSDIS; /* 0x0030 */\r
+ unsigned CSDISSET; /* 0x0034 */\r
+ unsigned CSDISCLR; /* 0x0038 */\r
+ unsigned CSDDIS; /* 0x003C */\r
+ unsigned CSDDISSET; /* 0x0040 */\r
+ unsigned CSDDISCLR; /* 0x0044 */\r
+ unsigned GHVSRC; /* 0x0048 */\r
+ unsigned VCLKASRC; /* 0x004C */\r
+ unsigned RCLKSRC; /* 0x0050 */\r
+ unsigned CSVSTAT; /* 0x0054 */\r
+ unsigned MSTGCR; /* 0x0058 */\r
+ unsigned MINITGCR; /* 0x005C */\r
+ unsigned MSINENA; /* 0x0060 */\r
+ unsigned MSTFAIL; /* 0x0064 */\r
+ unsigned MSTCGSTAT; /* 0x0068 */\r
+ unsigned MINISTAT; /* 0x006C */\r
+ unsigned PLLCTL1; /* 0x0070 */\r
+ unsigned PLLCTL2; /* 0x0074 */\r
+ unsigned UERFLAG; /* 0x0078 */\r
+ unsigned DIEIDL; /* 0x007C */\r
+ unsigned DIEIDH; /* 0x0080 */\r
+ unsigned VRCTL; /* 0x0084 */\r
+ unsigned LPOMONCTL; /* 0x0088 */\r
+ unsigned CLKTEST; /* 0x008C */\r
+ unsigned DFTCTRLREG1; /* 0x0090 */\r
+ unsigned DFTCTRLREG2; /* 0x0094 */\r
+ unsigned : 32U; /* 0x0098 */\r
+ unsigned : 32U; /* 0x009C */\r
+ unsigned GPREG1; /* 0x00A0 */\r
+ unsigned BTRMSEL; /* 0x00A4 */\r
+ unsigned IMPFASTS; /* 0x00A8 */\r
+ unsigned IMPFTADD; /* 0x00AC */\r
+ unsigned SSISR1; /* 0x00B0 */\r
+ unsigned SSISR2; /* 0x00B4 */\r
+ unsigned SSISR3; /* 0x00B8 */\r
+ unsigned SSISR4; /* 0x00BC */\r
+ unsigned RAMGCR; /* 0x00C0 */\r
+ unsigned BMMCR1; /* 0x00C4 */\r
+ unsigned BMMCR2; /* 0x00C8 */\r
+ unsigned MMUGCR; /* 0x00CC */\r
+#ifdef _little_endian__\r
+ unsigned : 8U; /* 0x00D0 */\r
+ unsigned PENA : 1U; /* 0x00D0 */\r
+ unsigned : 7U; /* 0x00D0 */\r
+ unsigned VCLKR : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLK2R : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+#else\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLK2R : 4U; /* 0x00D0 */\r
+ unsigned : 4U; /* 0x00D0 */\r
+ unsigned VCLKR : 4U; /* 0x00D0 */\r
+ unsigned : 7U; /* 0x00D0 */\r
+ unsigned PENA : 1U; /* 0x00D0 */\r
+ unsigned : 8U; /* 0x00D0 */\r
+#endif\r
+ unsigned : 32U; /* 0x00D4 */\r
+ unsigned DSPGCR; /* 0x00D8 */\r
+ unsigned DEVCR1; /* 0x00DC */\r
+ unsigned SYSECR; /* 0x00E0 */\r
+ unsigned SYSESR; /* 0x00E4 */\r
+ unsigned ITIFLAG; /* 0x00E8 */\r
+ unsigned GBLSTAT; /* 0x00EC */\r
+ unsigned DEV; /* 0x00F0 */\r
+ unsigned SSIVEC; /* 0x00F4 */\r
+ unsigned SSIF; /* 0x00F8 */\r
+} systemBASE1_t;\r
+\r
+\r
+/** @def systemREG1\r
+* @brief System Register Frame 1 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 1 registers.\r
+*/\r
+#define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)\r
+\r
+\r
+/** @def PRE1\r
+* @brief Alias name for RTI1CLK PRE clock source\r
+*\r
+* This is an alias name for the RTI1CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define PRE1 SYS_PLL\r
+\r
+/** @def PRE2\r
+* @brief Alias name for RTI2CLK pre clock source\r
+*\r
+* This is an alias name for the RTI2CLK pre clock source.\r
+* This can be either:\r
+* - Oscillator\r
+* - Pll\r
+* - 32 kHz Oscillator\r
+* - External\r
+* - Low Power Oscillator Low\r
+* - Low Power Oscillator High\r
+* - Flexray Pll\r
+*/\r
+#define PRE2 SYS_PLL\r
+\r
+typedef volatile struct systemBase2\r
+{\r
+ unsigned PLLCTL3; /* 0x0000 */\r
+ unsigned : 32U; /* 0x0004 */\r
+ unsigned STCCLKDIV; /* 0x0008 */\r
+ unsigned CLKHB_GLBREG; /* 0x000C */\r
+ unsigned CLKHB_RTIDREG; /* 0x0010 */\r
+ unsigned HBCD_STAT; /* 0x0014 */\r
+ unsigned : 32U; /* 0x0018 */\r
+ unsigned : 32U; /* 0x001C */\r
+ unsigned CLKTRMI1; /* 0x0020 */\r
+ unsigned ECPCNTRL0; /* 0x0024 */\r
+ unsigned ECPCNTRL1; /* 0x0028 */\r
+ unsigned ECPCNTRL2; /* 0x002C */\r
+ unsigned ECPCNTRL3; /* 0x0030 */\r
+} systemBASE2_t;\r
+\r
+\r
+/** @def systemREG2\r
+* @brief System Register Frame 2 Pointer\r
+*\r
+* This pointer is used by the system driver to access the system frame 2 registers.\r
+*/\r
+#define systemREG2 ((systemBASE2_t *)0xFFFFE100U)\r
+\r
+typedef volatile struct pcrBase\r
+{\r
+ unsigned PMPROTSET0; /* 0x0000 */\r
+ unsigned PMPROTSET1; /* 0x0004 */\r
+ unsigned : 32U; /* 0x0008 */\r
+ unsigned : 32U; /* 0x000C */\r
+ unsigned PMPROTCLR0; /* 0x0010 */\r
+ unsigned PMPROTCLR1; /* 0x0014 */\r
+ unsigned : 32U; /* 0x0018 */\r
+ unsigned : 32U; /* 0x001C */\r
+ unsigned PPROTSET0; /* 0x0020 */\r
+ unsigned PPROTSET1; /* 0x0024 */\r
+ unsigned PPROTSET2; /* 0x0028 */\r
+ unsigned PPROTSET3; /* 0x002C */\r
+ unsigned : 32U; /* 0x0030 */\r
+ unsigned : 32U; /* 0x0034 */\r
+ unsigned : 32U; /* 0x0038 */\r
+ unsigned : 32U; /* 0x003C */\r
+ unsigned PPROTCLR0; /* 0x0040 */\r
+ unsigned PPROTCLR1; /* 0x0044 */\r
+ unsigned PPROTCLR2; /* 0x0048 */\r
+ unsigned PPROTCLR3; /* 0x004C */\r
+ unsigned : 32U; /* 0x0050 */\r
+ unsigned : 32U; /* 0x0054 */\r
+ unsigned : 32U; /* 0x0058 */\r
+ unsigned : 32U; /* 0x005C */\r
+ unsigned PCSPWRDWNSET0; /* 0x0060 */\r
+ unsigned PCSPWRDWNSET1; /* 0x0064 */\r
+ unsigned : 32U; /* 0x0068 */\r
+ unsigned : 32U; /* 0x006C */\r
+ unsigned PCSPWRDWNCLR0; /* 0x0070 */\r
+ unsigned PCSPWRDWNCLR1; /* 0x0074 */\r
+ unsigned : 32U; /* 0x0078 */\r
+ unsigned : 32U; /* 0x007C */\r
+ unsigned PSPWRDWNSET0; /* 0x0080 */\r
+ unsigned PSPWRDWNSET1; /* 0x0084 */\r
+ unsigned PSPWRDWNSET2; /* 0x0088 */\r
+ unsigned PSPWRDWNSET3; /* 0x008C */\r
+ unsigned : 32U; /* 0x0090 */\r
+ unsigned : 32U; /* 0x0094 */\r
+ unsigned : 32U; /* 0x0098 */\r
+ unsigned : 32U; /* 0x009C */\r
+ unsigned PSPWRDWNCLR0; /* 0x00A0 */\r
+ unsigned PSPWRDWNCLR1; /* 0x00A4 */\r
+ unsigned PSPWRDWNCLR2; /* 0x00A8 */\r
+ unsigned PSPWRDWNCLR3; /* 0x00AC */\r
+} pcrBASE_t;\r
+\r
+/** @def pcrREG\r
+* @brief Pcr Register Frame Pointer\r
+*\r
+* This pointer is used by the system driver to access the Pcr registers.\r
+*/\r
+#define pcrREG ((pcrBASE_t *)0xFFFFE000U)\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* CAN register definition */\r
+\r
+typedef volatile struct\r
+{\r
+ uint32 CTL;\r
+ uint32 SR;\r
+ unsigned : 16;\r
+ unsigned REC : 8;\r
+ unsigned TEC : 8;\r
+ uint32 BTR;\r
+ uint32 IR;\r
+ uint32 TR;\r
+ unsigned : 32;\r
+ uint32 PEC;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 ABOT;\r
+ uint32 TRX;\r
+ uint32 TRx[4];\r
+ uint32 NDX;\r
+ uint32 NDx[4];\r
+ uint32 IPX;\r
+ uint32 IPx[4];\r
+ uint32 MVX;\r
+ uint32 MVx[4];\r
+ unsigned : 32;\r
+ uint32 IPMx[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ struct\r
+ {\r
+ uint32 COM;\r
+ uint32 MASK;\r
+ uint32 ARB;\r
+ uint32 MC;\r
+ uint8 DATx[8];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ } IFx[3];\r
+ uint32 IF3UEy[4];\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ unsigned : 32;\r
+ uint32 IOTX;\r
+ uint32 IORX;\r
+} Can_RegisterType;\r
+\r
+\r
+#define DCAN1_Base ((Can_RegisterType *)0xFFF7DC00)\r
+#define DCAN2_Base ((Can_RegisterType *)0xFFF7DE00)\r
+#define DCAN3_Base ((Can_RegisterType *)0xFFF7E000)\r
+\r
+\r
+\r
+typedef volatile struct gioBase\r
+{\r
+ unsigned GCR0; /**< 0x0000: Global Control Register */\r
+ unsigned PWDN; /**< 0x0004: Power Down Register */\r
+ unsigned INTDET; /**< 0x0008: Interrupt Detect Regsiter*/\r
+ unsigned POL; /**< 0x000C: Interrupt Polarity Register */\r
+ unsigned INTENASET; /**< 0x0010: Interrupt Enable Set Register */\r
+ unsigned INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */\r
+ unsigned LVLSET; /**< 0x0018: Interrupt Priority Set Register */\r
+ unsigned LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */\r
+ unsigned FLG; /**< 0x0020: Interrupt Flag Register */\r
+ unsigned OFFSET0; /**< 0x0024: Interrupt Offset A Register */\r
+ unsigned OFFSET1; /**< 0x0028: Interrupt Offset B Register */\r
+} GIO_Base_RegisterType;\r
+\r
+\r
+/** @struct gioPort\r
+* @brief GIO Port Register Definition\r
+*/\r
+/** @typedef gioPORT_t\r
+* @brief GIO Port Register Type Definition\r
+*\r
+* This type is used to access the GIO Port Registers.\r
+*/\r
+typedef volatile struct gioPort\r
+{\r
+ unsigned DIR; /**< 0x0000: Data Direction Register */\r
+ unsigned DIN; /**< 0x0004: Data Input Register */\r
+ unsigned DOUT; /**< 0x0008: Data Output Register */\r
+ unsigned DSET; /**< 0x000C: Data Output Set Register */\r
+ unsigned DCLR; /**< 0x0010: Data Output Clear Register */\r
+ unsigned PDR; /**< 0x0014: Open Drain Regsiter */\r
+ unsigned PULDIS; /**< 0x0018: Pullup Disable Register */\r
+ unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */\r
+} GIO_RegisterType;\r
+\r
+#define GIO_PORTA_BASE ((GIO_RegisterType *)0xFFF7BC34)\r
+#define GIO_PORTB_BASE ((GIO_RegisterType *)0xFFF7BC54)\r
+\r
+\r
+/** @def gioREG\r
+* @brief GIO Register Frame Pointer\r
+*\r
+* This pointer is used by the GIO driver to access the gio module registers.\r
+*/\r
+#define gioREG ((GIO_Base_RegisterType *)0xFFF7BC00U)\r
+\r
+/** @def gioPORTA\r
+* @brief GIO Port (A) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTA\r
+*/\r
+#define gioPORTA ((gioPORT_t *)0xFFF7BC34U)\r
+\r
+/** @def gioPORTB\r
+* @brief GIO Port (B) Register Pointer\r
+*\r
+* Pointer used by the GIO driver to access PORTB\r
+*/\r
+#define gioPORTB ((gioPORT_t *)0xFFF7BC54U)\r
+\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+\r
+static inline void __disable_irq() {\r
+ __asm volatile("CPSID if");\r
+}\r
+static inline void __enable_irq() {\r
+ __asm volatile("CPSIE if");\r
+}\r
+\r
+static inline unsigned long _Irq_Save(void)\r
+{\r
+ register unsigned long val asm("r0");\r
+ asm("mrs r0, cpsr");\r
+ asm("and r0, r0, #0xC0"); // Mask the I and F bit of CPSR\r
+ __disable_irq();\r
+ return val;\r
+}\r
+\r
+static inline void _Irq_Restore(unsigned mask) {\r
+ if (mask & 0x80) {\r
+ __asm volatile("CPSID i");\r
+ } else {\r
+ __asm volatile("CPSIE i");\r
+ }\r
+ if (mask & 0x40) {\r
+ __asm volatile("CPSID f");\r
+ } else {\r
+ __asm volatile("CPSIE f");\r
+ }\r
+}\r
+\r
+#endif /* CORE_CR4_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include "internal.h"
+#include "task_i.h"
+#include "hooks.h"
+#include "irq.h"
+#include "core_cr4.h"
+
+extern TaskType Os_Arc_CreateIsr( void (*entry)(void ), uint8_t prio, const char *name );
+extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+
+
+static inline void Irq_Setup() {
+ vimREG->FIRQPR0 = 0x0;
+ vimREG->FIRQPR1 = 0x0;
+}
+
+void Irq_Init( void ) {
+ Irq_Setup();
+ Irq_Enable();
+}
+
+
+/**
+ *
+ * @param stack_p Ptr to the current stack.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+#define MAX_WAIT_COUNT 1000
+void *Irq_Entry( void *stack_p )
+{
+ uint32_t *stack;
+
+ // This is the current hardware interrupt channel that we are processing.
+ volatile sint8 channel;
+
+ // This is the current OS-interrupt vector that we are processing.
+ volatile sint8 virtualChannel;
+
+ // Get the highest pending interrupt.
+ volatile uint32 c = 0;
+ do {
+ channel = IrqGetCurrentInterruptSource();
+ c++;
+ } while (channel < 0 && c < MAX_WAIT_COUNT);
+
+ if (c >= MAX_WAIT_COUNT) {
+ // No interrupt is pending
+ return stack_p;
+ }
+
+ // In most cases the OS-channel is the same as the hardware channel.
+ virtualChannel = channel;
+
+ // Special case for software interrupts.
+ if (channel == SSI) {
+ // Get the emulated interrupt channel.
+ virtualChannel = systemREG1->SSISR1;
+ }
+
+ stack = (uint32_t *)stack_p;
+ struct OsPcb * pcb = (struct OsPcb *)Irq_VectorTable[virtualChannel];
+ // Save the hardware channel in the PCB, so that Os_Isr knows which interrupt channel to deactivate.
+ pcb->vector = channel;
+ stack = Os_Isr(stack, (void *)pcb);
+
+ //Irq_Enable();
+ return stack;
+}
+
+/**
+ * Attach an ISR type 1 to the interrupt controller.
+ *
+ * @param entry
+ * @param int_ctrl
+ * @param vector
+ * @param prio
+ */
+void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
+
+ // TODO: Use NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio)); here
+}
+
+/**
+ * NVIC prio have priority 0-15, 0-highest priority.
+ * Autosar does it the other way around, 0-Lowest priority
+ *
+ * Autosar NVIC
+ * 31 0
+ * 30 0
+ * ..
+ * 0 15
+ * 0 15
+ * @param prio
+ * @return
+ */
+static inline int osPrioToCpuPio( uint8_t prio ) {
+ assert(prio<32);
+ prio = 31 - prio;
+ return (prio>>1);
+}
+
+/**
+ * Attach a ISR type 2 to the interrupt controller.
+ *
+ * @param tid
+ * @param int_ctrl
+ * @param vector
+ */
+void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {
+ OsPcbType *pcb;
+
+ pcb = os_find_task(tid);
+ Irq_VectorTable[vector] = (void *)pcb;
+ IrqActivateChannel(vector);
+
+ // TOdo replace NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio));
+}
+
+/**
+ * Generates a soft interrupt, ie sets pending bit.
+ * This could also be implemented using ISPR regs.
+ *
+ * @param vector
+ */
+void Irq_GenerateSoftInt( IrqType vector ) {
+ IrqActivateChannel(SSI);
+ systemREG1->SSISR1 = (0x75 << 8) | vector;
+}
+
+/**
+ * Get the current priority from the interrupt controller.
+ * @param cpu
+ * @return
+ */
+uint8_t Irq_GetCurrentPriority( Cpu_t cpu) {
+
+ uint8_t prio = 0;
+
+ // SCB_ICSR contains the active vector
+ return prio;
+}
+
+typedef struct {
+ uint32_t dummy;
+} exc_stack_t;
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef IRQ_TYPES_H\r
+#define IRQ_TYPES_H\r
+\r
+\r
+#define IrqGetCurrentInterruptSource() \\r
+ (((volatile sint8)vimREG->IRQIVEC) - 1)\r
+\r
+/** IrqActivateChannel turns the selected channel on in the VIM */\r
+#define IrqActivateChannel(_channel) \\r
+ if (_channel > 31) { \\r
+ vimREG->REQMASKSET1 |= (1 << (_channel - 32)); \\r
+ } else { \\r
+ vimREG->REQMASKSET0 |= (1 << _channel); \\r
+ }\r
+\r
+\r
+/** IrqDeactivateChannel turns the selected channel off in the VIM */\r
+#define IrqDeactivateChannel(_channel) \\r
+ if (_channel > 31) { \\r
+ vimREG->REQMASKCLR1 = (1 << (_channel - 32)); \\r
+ } else { \\r
+ vimREG->REQMASKCLR0 = (1 << _channel); \\r
+ }\r
+\r
+\r
+#define Irq_SOI() \\r
+ IrqDeactivateChannel(isrPtr->vector)\r
+\r
+\r
+#define Irq_EOI() \\r
+ IrqActivateChannel(isrPtr->vector)\r
+\r
+\r
+typedef enum {\r
+ ESM_LEVEL_0 = 0,\r
+ RESERVED = 1,\r
+ RTI_COMPARE_0,\r
+ RTI_COMPARE_1,\r
+ RTI_COMPARE_2,\r
+ RTI_COMPARE_3,\r
+ RTI_OVERFLOW_0,\r
+ RTI_OVERFLOW_1,\r
+ RTI_TIMEBASE,\r
+ DIO_LEVEL_0,\r
+ HET_LEVEL_0,\r
+ HET_TU_LEVEL_0,\r
+ MIBSP1_LEVEL_0,\r
+ LIN1_LEVEL_0,\r
+ MIBADC1_EVENT,\r
+ MIBADC1_GROUP_1,\r
+ CAN1_LEVEL_0,\r
+ RESERVED_0,\r
+ FR_LEVEL_0,\r
+ CRC_1,\r
+ ESM_LEVEL_1,\r
+ SSI = 21,\r
+ PMU,\r
+ DIO_LEVEL_1,\r
+ HET_LEVEL_1,\r
+ HET_TU_LEVEL_1,\r
+ MIBSP1_LEVEL_1,\r
+ LIN1_LEVEL_1,\r
+ MIBADC1_GROUP_2,\r
+ CAN1_LEVEL_1,\r
+ RESERVED_1,\r
+ MIBADC1_MAG,\r
+ FR_LEVEL_1,\r
+ DMA_FTCA,\r
+ DMA_LFSA,\r
+ CAN2_LEVEL_0,\r
+ DMM_LEVEL_0,\r
+ MIBSPI3_LEVEL_0,\r
+ MIBSPI3_LEVEL_1,\r
+ DMA_HBDC,\r
+ DMA_BTCA,\r
+ RESERVED_2,\r
+ CAN2_LEVEL_1,\r
+ DMM_LEVEL_1,\r
+ CAN1_IF_3,\r
+ CAN3_LEVEL_0,\r
+ CAN2_IF_3,\r
+ FPU,\r
+ FR_TU_STATUS,\r
+ LIN2_LEVEL_0,\r
+ MIBADC2_EVENT,\r
+ MIBADC2_GROUP_1,\r
+ FR_TOC,\r
+ MIBSPIP5_LEVEL_0,\r
+ LIN2_LEVEL_1,\r
+ CAN3_LEVEL_1,\r
+ MIBSPI5_LEVEL_1,\r
+ MIBADC2_GROUP_2,\r
+ FR_TU_ERROR,\r
+ MIBADC2_MAG,\r
+ CAN3_IF_3,\r
+ FR_TU_MPU,\r
+ FR_T1C,\r
+ NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS,\r
+} IrqType;\r
+\r
+/* Total number of interrupts and exceptions\r
+ */\r
+#define NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS 65\r
+\r
+typedef enum {\r
+ PERIPHERAL_CLOCK_AHB,\r
+ PERIPHERAL_CLOCK_APB1,\r
+ PERIPHERAL_CLOCK_APB2,\r
+ PERIPHERAL_CLOCK_CAN,\r
+ PERIPHERAL_CLOCK_DCAN1,\r
+ PERIPHERAL_CLOCK_DCAN2,\r
+ PERIPHERAL_CLOCK_DCAN3\r
+} McuE_PeriperalClock_t;\r
+\r
+typedef enum {\r
+ CPU_0=0,\r
+} Cpu_t;\r
+\r
+#endif /* IRQ_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CONTEXT_H_\r
+#define CONTEXT_H_\r
+\r
+\r
+#define SC_PATTERN 0xde\r
+#define LC_PATTERN 0xad\r
+\r
+/* Minimum alignment req */\r
+#define ARCH_ALIGN 4\r
+\r
+/* Small context (task swap==function call) */\r
+#define SAVE_NVGPR(_x,_y)\r
+#define RESTORE_NVGPR(_x,_y)\r
+\r
+/* Save volatile regs, NOT preserved by function calls */\r
+#define SAVE_VGPR(_x,_y)\r
+#define RESTORE_VGPR(_x,_y)\r
+\r
+/* Large context (interrupt) */\r
+#define SAVE_ALL_GPR(_x,_y)\r
+#define RESTORE_ALL_GPR(_x,_y)\r
+\r
+\r
+// NVREGS: r0+r1+r2+r3+r4+r5+r6+r7+r8+r9+r10+r11+r12+lr = 14*4 = 40\r
+#define NVGPR_SIZE 56\r
+// VGPR: 9*4 = 36\r
+//#define VGPR_SIZE 36\r
+// SP + context\r
+#define C_SIZE 8\r
+#define VGPR_LR_OFF (C_SIZE+NVGPR_SIZE-4)\r
+#define C_CONTEXT_OFFS 4\r
+#define C_SP_OFF 0\r
+#define SC_SIZE (NVGPR_SIZE+C_SIZE)\r
+\r
+\r
+\r
+#endif /* CONTEXT_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+ \r
+\r
+ .syntax unified\r
+ .cpu cortex-r4\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global Default_Handler\r
+\r
+/* Addresses used to setup RAM */\r
+.word _sidata\r
+.word _sdata\r
+.word _edata\r
+.word _sbss\r
+.word _ebss\r
+\r
+/* The address of the stack to use in all modes. */\r
+.word _estack\r
+\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+\r
+Reset_Handler:\r
+\r
+/* Set big endian state */\r
+ SETEND BE\r
+\r
+/* Initialize core registers.\r
+ This is done to avoid mismatch between lockstep CPU and ordinary CPU\r
+*/\r
+ mov r0, #0x0000\r
+ mov r1, #0x0000\r
+ mov r2, #0x0000\r
+ mov r3, #0x0000\r
+ mov r4, #0x0000\r
+ mov r5, #0x0000\r
+ mov r6, #0x0000\r
+ mov r7, #0x0000\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ mov r1, #0x03D0\r
+ orr r2, r1, #0x0001\r
+ msr cpsr_cxsf, r2\r
+ msr spsr_cxsf, r2\r
+ mov r8, #0x0000\r
+ mov r9, #0x0000\r
+ mov r10, #0x0000\r
+ mov r11, #0x0000\r
+ mov r12, #0x0000\r
+ orr r12, r1, #0x0002\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0007\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x000B\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+ orr r12, r1, #0x0003\r
+ msr cpsr_c, r12\r
+ msr spsr_cxsf, r12\r
+\r
+/* System level configuration\r
+ This mainly involves setting instruction mode for exceptions and interrupts.\r
+*/\r
+ mrc p15,0,r11,c1,c0,0 /* Read current system configuration */\r
+ mov r12, #0x40000000 /* Set THUMB instruction set mode for interrupts and exceptions */\r
+ orr r12, r12, r11\r
+ mcr p15,0,r12,c1,c0,0 /* Write new configuration */\r
+\r
+\r
+/* Initialize stack pointers.\r
+ This is done for all processor modes. Note that we only use one stack pointer.\r
+ In reality this means that no mode except USER and SYS is allowed to do anythin on the stack.\r
+ IRQ mode handles its own stack in the interrupt routine.\r
+*/\r
+ mov r2, #0xD1\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD2\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD7\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xDB\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+ mov r2, #0xD3\r
+ msr cpsr_c, r2\r
+ ldr sp, =_estack\r
+\r
+\r
+/* Initialize RAM.\r
+ First the initialized RAM is copied from flash to RAM.\r
+ Then the zeroed RAM is erased.\r
+*/\r
+ ldr r0, =_sdata /* r0 holds start of data in ram */\r
+ ldr r3, =_edata /* r3 holds end of data in ram */\r
+ ldr r5, =_sidata /* r5 start of data in flash */\r
+ movs r1, #0 /* r1 is the counter */\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r4, [r5, r1] /* read current position in flash */\r
+ str r4, [r0, r1] /* store current position in ram */\r
+ adds r1, r1, #4 /* increment counter */\r
+ \r
+LoopCopyDataInit:\r
+ adds r2, r0, r1 /* are we at the final position? */\r
+ cmp r2, r3 /* ... */\r
+ bcc CopyDataInit /* nope, continue */\r
+\r
+/* Fill zero areas */\r
+ ldr r2, =_sbss /* r2 holds the start address */\r
+ ldr r5, =_ebss /* r5 holds the end address */\r
+ bl LoopFillZero\r
+\r
+ ldr r2, =_sstack /* r2 holds the start address */\r
+ ldr r5, =_estack /* r5 holds the end address */\r
+ bl LoopFillZero\r
+\r
+/* Call the application's entry point.*/\r
+ mov r2, #0xDF\r
+ msr cpsr_c, r2\r
+ bl main\r
+ bx lr\r
+\r
+/* Zero fill the bss segment. */ \r
+FillZero:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZero:\r
+ cmp r2, r5\r
+ bcc FillZero\r
+ bx lr\r
+\r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+\r
+\r
+\r
+/******************************************************************************\r
+* Interrupt and exception vectors. Vectors start at addr 0x0.\r
+******************************************************************************/ \r
+ .section .int_vecs,"ax",%progbits\r
+ .extern Irq_Handler\r
+ .extern Svc_Handler\r
+ .extern Data_Exc_Handler\r
+ .extern Prefetch_Exc_Handler\r
+ .extern Dummy_Irq\r
+\r
+ /* This is the reset handler. Since the CPU is in ARM mode when this instruction is executed\r
+ it has to be hard coded (otherwise it will compile wrong).\r
+ Instruction branches to address 0x22 while changing instruction mode to THUMB. */\r
+ .word 0xfb000006\r
+\r
+ b Dummy_Irq /* Undefined instruction exception */\r
+ b Dummy_Irq /* SVC */\r
+ b Prefetch_Exc_Handler /* Prefetch exception */\r
+ b Data_Exc_Handler /* Data exception */\r
+ b Dummy_Irq /* Reserved */\r
+ b Irq_Handler /* Ordinary interrupts (IRQ) */\r
+ b Dummy_Irq /* Fast interrupts (FIR) */\r
+\r
+ nop\r
+ b Reset_Handler /* Branch to the real reset handler. */\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Os.h"\r
+#include "internal.h"\r
+#include "core_cr4.h"\r
+#include "irq.h"\r
+#include "arc.h"\r
+\r
+#define RTICLK_PRESCALER 10\r
+\r
+void CortexR4OsTick() {\r
+ /** Clear all pending interrupts\r
+ * otherwise this will hit again\r
+ * as soon as interrupts are re-enabled. */\r
+ rtiREG1->INTFLAG = 0x1;\r
+\r
+ // Call regular OsTick.\r
+ OsTick();\r
+}\r
+\r
+/**\r
+ * Init of free running timer.\r
+ */\r
+void Os_SysTickInit( void ) {\r
+ TaskType tid;\r
+ tid = Os_Arc_CreateIsr(CortexR4OsTick,6,"OsTick");\r
+ Irq_AttachIsr2(tid,NULL, RTI_COMPARE_0);\r
+}\r
+\r
+\r
+static inline uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+\r
+ /** - Setup NTU source, debug options and disable both counter blocks */\r
+ rtiREG1->GCTRL = 0x0;\r
+\r
+ /** - Setup timebase for free running counter 0 */\r
+ rtiREG1->TBCTRL = 0x0;\r
+\r
+ /** - Enable/Disable capture event sources for both counter blocks */\r
+ rtiREG1->CAPCTRL = 0x0;\r
+\r
+ /** - Setup input source compare 0-3 */\r
+ rtiREG1->COMPCTRL = 0x0;\r
+\r
+ /** - Reset up counter 0 */\r
+ rtiREG1->CNT[0U].UCx = 0x00000000U;\r
+\r
+ /** - Reset free running counter 0 */\r
+ rtiREG1->CNT[0U].FRCx = 0x00000000U;\r
+\r
+ /** - Setup up counter 0 compare value\r
+ * The RTI module is driven by RTICLK. With the Arctic Core\r
+ * MCU driver for cortex R4 RTICLK = VCLK = PLLCLK / 2\r
+ * ticks = number of PLLCLK cycles per os tick = number of RTICLK cycles * 2 per os tick\r
+ *\r
+ * - 0x00000000: Divide by 2^32\r
+ * - 0x00000001-0xFFFFFFFF: Divide by (CPUCx + 1)\r
+ */\r
+ rtiREG1->CNT[0U].CPUCx = RTICLK_PRESCALER - 1;\r
+\r
+ uint8 vclkDiv = systemREG1->VCLKR + 1;\r
+\r
+ /** - Setup compare 0 value. This value is compared with selected free running counter. */\r
+ rtiREG1->CMP[0U].COMPx = ticks / (RTICLK_PRESCALER * vclkDiv);\r
+\r
+ /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */\r
+ rtiREG1->CMP[0U].UDCPx = ticks / (RTICLK_PRESCALER * vclkDiv);\r
+\r
+ /** - Clear all pending interrupts */\r
+ rtiREG1->INTFLAG = 0x0;\r
+\r
+ /** - Disable all interrupts */\r
+ rtiREG1->CLEARINT = 0x0;\r
+\r
+ return (0);\r
+}\r
+\r
+/**\r
+ * Start the Sys Tick timer\r
+ *\r
+ * @param period_ticks How long the period in timer ticks should be.\r
+ *\r
+ */\r
+void Os_SysTickStart(uint32_t period_ticks) {\r
+\r
+ /* Cortex-M3 have a 24-bit system timer that counts down\r
+ * from the reload value to zero.\r
+ */\r
+\r
+ SysTick_Config(period_ticks);\r
+ rtiREG1->GCTRL = 0x1;\r
+ rtiREG1->SETINT = 0x1;\r
+\r
+}\r
+\r
+/**\r
+ * @return\r
+ */\r
+\r
+uint32_t Os_SysTickGetValue( void )\r
+{\r
+ //return (SysTick->LOAD) - (SysTick->VAL);\r
+ return 0;\r
+}\r
+\r
+\r
+TickType Os_SysTickGetElapsedValue( uint32_t preValue ) {\r
+ uint32_t curr;\r
+ uint32_t max;\r
+\r
+ /*\r
+ curr = (SysTick->VAL);\r
+ max = (SysTick->LOAD);\r
+ */\r
+ curr = 0;\r
+ max = 0;\r
+ return Os_CounterDiff((max - curr),preValue,max);\r
+}\r
+\r
--- /dev/null
+\r
+# prefered version\r
+CC_VERSION=4.4.5\r
+# ARMv7, Thumb-2, little endian, soft-float. \r
+cflags-y += -mthumb -mcpu=cortex-r4 -mbig-endian\r
+cflags-y += -ggdb\r
+\r
+lib-y += -lgcc -lc\r
+ASFLAGS += -mthumb -mcpu=cortex-r4 -mbig-endian\r
+\r
+LDFLAGS +=
\ No newline at end of file
--- /dev/null
+/* \r
+ * Copyright (C) ArcCore AB <contact@arccore.com>\r
+ *\r
+ * ST startup variables: \r
+ * _sidata - Start of .data in flash \r
+ * _sdata - start address of .data in RAM\r
+ * _edata - end address of .data in RAM\r
+ * _sbss - start address of .bss\r
+ * _ebss - end address of .bss\r
+ * _etext - ?\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-bigarm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(Reset_Handler)\r
+\r
+#include "Calibration_Settings.h"\r
+\r
+MEMORY\r
+{\r
+#include "memory.ldf"\r
+}\r
+\r
+SECTIONS\r
+{\r
+/* __CALIB_RAM_START, __CALIB_RAM_END, __CALIB_ROM_START are needed by the a2l and the rte generator. \r
+ CALIBRATION_ENABLED, CALIBRATION_INITIALIZED_RAM, CALIBRATION_FLS_START are generated by rte \r
+*/\r
+#if defined(CALIBRATION_ENABLED)\r
+#if defined(CALIBRATION_INITIALIZED_RAM)\r
+/* when calibration is active a flash and ram area is needed. the rte will copy the calibration area from flash to ram. */\r
+ .calibration : AT(CALIBRATION_FLS_START) { \r
+ *(.calibration)\r
+ } > ram \r
+#else /* CALIBRATION_INITIALIZED_RAM */\r
+/* when calibration isnt active only a flash area is needed. */ \r
+ .calibration CALIBRATION_FLS_START : {\r
+ *(.calibration)\r
+ } > flash \r
+#endif\r
+\r
+__CALIB_RAM_START = ADDR(.calibration);\r
+__CALIB_RAM_END = ADDR(.calibration) + SIZEOF(.calibration);\r
+__CALIB_ROM_START = LOADADDR(.calibration);\r
+#else\r
+ /* failsafe to avoid trouble with defined calib variables if CALIBRATION_ENABLED is not set */\r
+ .calibration : {\r
+ *(.calibration)\r
+ } > flash\r
+ ASSERT(SIZEOF(.calibration) == 0, ".calibration section used but CALIBRATION_ENABLED is undefined")\r
+#endif /* CALIBRATION_ENABLED */\r
+\r
+ .int_vecs :\r
+ {\r
+ KEEP(*(.int_vecs))\r
+ } > intvecs\r
+\r
+ .text :\r
+ {\r
+ *(.text .text.* );\r
+ *(.glue_7) /* TODO */\r
+ *(.glue_7t) /* TODO */\r
+ \r
+ PROVIDE( btask_sup_matrix = .);\r
+ SORT(*)(.test_btask);\r
+ PROVIDE( etask_sup_matrix = .);\r
+ SORT(*)(.test_etask);\r
+ \r
+ /* ST/ARM special variable to initialize .data */\r
+ _etext = .;\r
+ } > flash\r
+\r
+ /* Relocatable Flash Driver */\r
+ .fls_rom : {\r
+ __FLS_ERASE_ROM__ = .;\r
+ *(.fls_erase);\r
+ __FLS_WRITE_ROM__ = .;\r
+ *(.fls_write);\r
+ __FLS_END_ROM__ = .;\r
+ } > flash\r
+\r
+ /* ARM exception section */\r
+ .ARM.exidx : { \r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > flash\r
+ __exidx_start = .;\r
+\r
+ /* Read-only data section. */\r
+ .rodata : { \r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
+ _sidata = ALIGN(.,4);\r
+ } > flash\r
+ \r
+ .cio ALIGN(0x10) : {\r
+ \r
+ } > ram\r
+\r
+ .data : AT(ALIGN(LOADADDR(.rodata)+SIZEOF(.rodata),4)) {\r
+ _sdata = ALIGN(.,4); \r
+ *(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ _edata = ALIGN(.,4); \r
+ } > ram\r
+\r
+ .t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
+ .bss : {\r
+ _sbss = ., \r
+ *(.bss .bss.* COMMON .gnu.linkonce.b.*);\r
+ _ebss = .; \r
+ } > ram\r
+ \r
+ .init_stack ALIGN(16) (NOLOAD) : \r
+ { \r
+ _sstack = .;\r
+ . = . + 8000; \r
+ _estack = .; \r
+ . = . + 1;\r
+ . = ALIGN(4);\r
+ } > ram\r
+ \r
+ /* Fls RAM section */\r
+ .fls_ram ALIGN(16) (NOLOAD) : {\r
+ __FLS_ERASE_RAM__ = .;\r
+ . = . + SIZEOF(.fls_rom);\r
+ } > ram\r
+\r
+ .ctors :\r
+ {\r
+ KEEP (*(SORT(.ctors.*)))\r
+ }\r
+\r
+ .uninit ALIGN(0x10) (NOLOAD) : { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
+\r
+\r
+ __FLS_SIZE__ = SIZEOF(.fls_rom);\r
+ __FLS_WRITE_RAM__ = __FLS_ERASE_RAM__ + (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
+__EXCEPT_START__ = 0x0;\r
+__EXCEPT_END__ = 0x0;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+\r
+#include "McuExtensions.h"\r
+\r
+imask_t McuE_EnterCriticalSection(void) {\r
+ return 0;\r
+}\r
+\r
+void McuE_ExitCriticalSection(imask_t old_state) {\r
+ (void)old_state; // Nothing to be done. This is just to avoid PC-Lint warning.\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include "Mcu.h"\r
+#include "Adc.h"\r
+#include "Det.h"\r
+#include "Os.h"\r
+#include "irq.h"\r
+#include "regs.h"\r
+#include "arc.h"\r
+\r
+\r
+// ATDCTL2\r
+#define BM_ADPU 0x80\r
+#define BM_AFFC 0x40\r
+#define BM_AWAI 0x20\r
+#define BM_ETRIGLE 0x10\r
+#define BM_ETRIGP 0x08\r
+#define BM_ETRIG_E 0x04\r
+#define BM_ASCIE 0x02\r
+#define BM_ASCIF 0x01\r
+\r
+// ATDCTL3\r
+#define BM_S8C 0x40\r
+#define BM_S4C 0x20\r
+#define BM_S2C 0x10\r
+#define BM_S1C 0x08\r
+#define BM_FIFO 0x04\r
+#define BM_FRZ1 0x02\r
+#define BM_FRZ0 0x01\r
+\r
+// ATDCTL4\r
+#define BM_SRES8 0x80\r
+#define BM_SMP1 0x40\r
+#define BM_SMP0 0x20\r
+#define BM_PRS4 0x10\r
+#define BM_PRS3 0x08\r
+#define BM_PRS2 0x04\r
+#define BM_PRS1 0x02\r
+#define BM_PRS0 0x01\r
+\r
+// ATDCTL5\r
+#define BM_DJM 0x80\r
+#define BM_DSGN 0x40\r
+#define BM_SCAN 0x20\r
+#define BM_MULT 0x10\r
+#define BM_CC 0x04\r
+#define BM_CB 0x02\r
+#define BM_CA 0x01\r
+\r
+typedef enum\r
+{\r
+ ADC_UNINIT,\r
+ ADC_INIT,\r
+}Adc_StateType;\r
+\r
+/* Function prototypes. */\r
+\r
+/* Development error checking. */\r
+static Std_ReturnType Adc_CheckReadGroup (Adc_GroupType group);\r
+static Std_ReturnType Adc_CheckStartGroupConversion (Adc_GroupType group);\r
+static Std_ReturnType Adc_CheckInit (const Adc_ConfigType *ConfigPtr);\r
+static Std_ReturnType Adc_CheckSetupResultBuffer (Adc_GroupType group);\r
+\r
+static void Adc_GroupConversionComplete (void);\r
+\r
+static Adc_StateType adcState = ADC_UNINIT;\r
+\r
+/* Pointer to configuration structure. */\r
+static const Adc_ConfigType *AdcConfigPtr;\r
+\r
+#if (ADC_DEINIT_API == STD_ON)\r
+Std_ReturnType Adc_DeInit (const Adc_ConfigType *ConfigPtr)\r
+{\r
+\r
+ return (E_OK);\r
+}\r
+#endif\r
+\r
+Std_ReturnType Adc_Init (const Adc_ConfigType *ConfigPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+ Adc_GroupType group;\r
+\r
+ if (E_OK == Adc_CheckInit(ConfigPtr))\r
+ {\r
+ /* First of all, store the location of the configuration data. */\r
+ AdcConfigPtr = ConfigPtr;\r
+\r
+ // Connect interrupt to correct isr\r
+ TaskType tid;\r
+ tid = Os_Arc_CreateIsr(Adc_GroupConversionComplete,6/*prio*/,"ADC");\r
+ Irq_AttachIsr2(tid,NULL, IRQ_TYPE_ATD0);\r
+\r
+ ATD0CTL2 = BM_ADPU | BM_AFFC | BM_ASCIE; /* power enable, Fast Flag Clear, irq enable*/\r
+ ATD0CTL3 = 0x00; /* 8 conversions per sequence default */\r
+\r
+ ATD0CTL4 = (ConfigPtr->hwConfigPtr->resolution << 7) |\r
+ (ConfigPtr->hwConfigPtr->convTime << 5) |\r
+ ConfigPtr->hwConfigPtr->adcPrescale;\r
+\r
+ for (group = ADC_GROUP0; group < ADC_NBR_OF_GROUPS; group++)\r
+ {\r
+ /* ADC307. */\r
+ ConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+ }\r
+\r
+ /* Move on to INIT state. */\r
+ adcState = ADC_INIT;\r
+ returnValue = E_OK;\r
+ }\r
+ else\r
+ {\r
+ returnValue = E_NOT_OK;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+Std_ReturnType Adc_SetupResultBuffer (Adc_GroupType group, Adc_ValueGroupType *bufferPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+ /* Check for development errors. */\r
+ if (E_OK == Adc_CheckSetupResultBuffer (group))\r
+ {\r
+ AdcConfigPtr->groupConfigPtr[group].status->resultBufferPtr = bufferPtr;\r
+ returnValue = E_OK;\r
+ }\r
+ else\r
+ {\r
+ /* An error have been raised from Adc_CheckSetupResultBuffer(). */\r
+ returnValue = E_NOT_OK;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+#if (ADC_READ_GROUP_API == STD_ON)\r
+Std_ReturnType Adc_ReadGroup (Adc_GroupType group, Adc_ValueGroupType *dataBufferPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+ Adc_ChannelType channel;\r
+\r
+ if (E_OK == Adc_CheckReadGroup (group))\r
+ {\r
+ if ((ADC_CONV_MODE_CONTINUOUS == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
+ ((ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
+ (ADC_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
+ {\r
+ /* ADC329, ADC331. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_BUSY;\r
+ returnValue = E_OK;\r
+ }\r
+ else if ((ADC_CONV_MODE_ONESHOT == AdcConfigPtr->groupConfigPtr[group].conversionMode) &&\r
+ (ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus))\r
+ {\r
+ /* ADC330. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_IDLE;\r
+\r
+ returnValue = E_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Keep status. */\r
+ returnValue = E_OK;\r
+ }\r
+\r
+ if (E_OK == returnValue)\r
+ {\r
+ /* Copy the result to application buffer. */\r
+ for (channel = 0; channel < AdcConfigPtr->groupConfigPtr[group].numberOfChannels; channel++)\r
+ {\r
+ dataBufferPtr[channel] = AdcConfigPtr->groupConfigPtr[group].resultBuffer[channel];\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* An error have been raised from Adc_CheckReadGroup(). */\r
+ returnValue = E_NOT_OK;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+#endif\r
+\r
+Adc_StatusType Adc_GetGroupStatus (Adc_GroupType group)\r
+{\r
+ Adc_StatusType returnValue;\r
+ if ((ADC_INIT == adcState) && (AdcConfigPtr != NULL))\r
+ {\r
+ /* Adc initilised, OK to move on... */\r
+ returnValue = AdcConfigPtr->groupConfigPtr[group].status->groupStatus;\r
+ }\r
+ else\r
+ {\r
+ returnValue = ADC_IDLE;\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_GETGROUPSTATUS_ID, ADC_E_UNINIT );\r
+#endif\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+static void Adc_GroupConversionComplete (void)\r
+{\r
+ uint8 index;\r
+ Adc_GroupDefType *groupPtr = NULL;\r
+ /* Clear SCF flag. Not needed if AFFC is set but better to always do it */\r
+ ATD0STAT0 = SCF;\r
+\r
+ // Check which group is busy, only one is allowed to be busy at a time in a hw unit\r
+ for (index = ADC_GROUP0; index < ADC_NBR_OF_GROUPS; index++)\r
+ {\r
+ if(AdcConfigPtr->groupConfigPtr[index].status->groupStatus == ADC_BUSY)\r
+ {\r
+ groupPtr = (Adc_GroupDefType *)&AdcConfigPtr->groupConfigPtr[index];\r
+ break;\r
+ }\r
+ }\r
+ if(groupPtr != NULL)\r
+ {\r
+ // Read hw buffer,\r
+ volatile uint16_t *ptr = &ATD0DR0;\r
+ for(index=0; index<groupPtr->numberOfChannels; index++)\r
+ {\r
+ groupPtr->resultBuffer[index] = *(ptr + groupPtr->channelList[index]);\r
+ }\r
+\r
+ /* Sample completed. */\r
+ groupPtr->status->groupStatus = ADC_STREAM_COMPLETED;\r
+\r
+ /* Call notification if enabled. */\r
+ #if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
+ if (groupPtr->status->notifictionEnable && groupPtr->groupCallback != NULL)\r
+ {\r
+ groupPtr->groupCallback();\r
+ }\r
+ #endif\r
+ }\r
+}\r
+\r
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
+void Adc_StartGroupConversion (Adc_GroupType group)\r
+{\r
+ /* Run development error check. */\r
+ if (E_OK == Adc_CheckStartGroupConversion (group))\r
+ {\r
+ /* Set single scan enable bit if this group is one shot. */\r
+ if (AdcConfigPtr->groupConfigPtr[group].conversionMode == ADC_CONV_MODE_ONESHOT)\r
+ {\r
+ /* Start next AD conversion. */\r
+ ATD0CTL5 = BM_DJM | BM_MULT; /* 10010000 Right Justified,unsigned */\r
+ /* No SCAN/MULT/AD0 start select */\r
+ /* Set group state to BUSY. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_BUSY;\r
+ }\r
+ else\r
+ {\r
+ // Continous mode\r
+ /* Start AD conversion. */\r
+ ATD0CTL5 = BM_DJM | BM_MULT | BM_SCAN; /* 10010000 Right Justified,unsigned */\r
+ /* SCAN/MULT/AD0 start select */\r
+ /* Set group state to BUSY. */\r
+ AdcConfigPtr->groupConfigPtr[group].status->groupStatus = ADC_BUSY;\r
+ }\r
+ }\r
+}\r
+#endif\r
+\r
+#if (ADC_GRP_NOTIF_CAPABILITY == STD_ON)\r
+void Adc_EnableGroupNotification (Adc_GroupType group)\r
+{\r
+ AdcConfigPtr->groupConfigPtr[group].status->notifictionEnable = 1;\r
+}\r
+\r
+void Adc_DisableGroupNotification (Adc_GroupType group)\r
+{\r
+ AdcConfigPtr->groupConfigPtr[group].status->notifictionEnable = 0;\r
+}\r
+#endif\r
+\r
+\r
+/* Development error checking functions. */\r
+#if (ADC_READ_GROUP_API == STD_ON)\r
+static Std_ReturnType Adc_CheckReadGroup (Adc_GroupType group)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+\r
+ if (ADC_UNINIT == adcState)\r
+ {\r
+ /* ADC296. */\r
+ returnValue = E_NOT_OK;\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_READGROUP_ID ,ADC_E_UNINIT );\r
+ }\r
+ else if ((group < ADC_GROUP0) || (group >= ADC_NBR_OF_GROUPS))\r
+ {\r
+ /* ADC152. */\r
+ returnValue = E_NOT_OK;\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_READGROUP_ID ,ADC_E_PARAM_GROUP );\r
+ }\r
+ else if (ADC_IDLE == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)\r
+ {\r
+ /* ADC388. */\r
+ returnValue = E_NOT_OK;\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_READGROUP_ID ,ADC_E_IDLE );\r
+ }\r
+ else\r
+ {\r
+ /* Nothing strange. Go on... */\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+#endif\r
+\r
+#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
+static Std_ReturnType Adc_CheckStartGroupConversion (Adc_GroupType group)\r
+{\r
+ Std_ReturnType returnValue;\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ if (!(ADC_INIT == adcState))\r
+ {\r
+ /* ADC not initialised, ADC294. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_UNINIT );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (!((group >= 0) && (group < ADC_NBR_OF_GROUPS)))\r
+ {\r
+ /* Wrong group ID, ADC125 */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_PARAM_GROUP );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (!(ADC_TRIGG_SRC_SW == AdcConfigPtr->groupConfigPtr[group].triggerSrc))\r
+ {\r
+ /* Wrong trig source, ADC133. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_WRONG_TRIGG_SRC);\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (!((ADC_IDLE == AdcConfigPtr->groupConfigPtr[group].status->groupStatus) ||\r
+ (ADC_STREAM_COMPLETED == AdcConfigPtr->groupConfigPtr[group].status->groupStatus)))\r
+ {\r
+ /* Group status not OK, ADC351, ADC428 */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_STARTGROUPCONVERSION_ID, ADC_E_BUSY );\r
+\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else\r
+ {\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+#endif\r
+\r
+static Std_ReturnType Adc_CheckInit (const Adc_ConfigType *ConfigPtr)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ if (!(ADC_UNINIT == adcState))\r
+ {\r
+ /* Oops, already initialised. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_INIT_ID, ADC_E_ALREADY_INITIALIZED );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (ConfigPtr == NULL)\r
+ {\r
+ /* Wrong config! */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_INIT_ID, ADC_E_PARAM_CONFIG );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Looks good!! */\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+\r
+static Std_ReturnType Adc_CheckSetupResultBuffer (Adc_GroupType group)\r
+{\r
+ Std_ReturnType returnValue;\r
+\r
+#if ( ADC_DEV_ERROR_DETECT == STD_ON )\r
+ if (ADC_UNINIT == adcState)\r
+ {\r
+ /* Driver not initialised. */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_SETUPRESULTBUFFER_ID,ADC_E_UNINIT );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else if (group < ADC_NBR_OF_GROUPS)\r
+ {\r
+ /* ADC423 */\r
+ Det_ReportError(MODULE_ID_ADC,0,ADC_SETUPRESULTBUFFER_ID,ADC_E_PARAM_GROUP );\r
+ returnValue = E_NOT_OK;\r
+ }\r
+ else\r
+ {\r
+ /* Looks good!! */\r
+ returnValue = E_OK;\r
+ }\r
+#else\r
+ returnValue = E_OK;\r
+#endif\r
+ return (returnValue);\r
+}\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Can.h"\r
+\r
+#ifndef USE_CAN_STUB\r
+#include "regs.h"\r
+#include "Cpu.h"\r
+#include "Mcu.h"\r
+#include "CanIf_Cbk.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "Os.h"\r
+#include "irq.h"\r
+#include "arc.h"\r
+\r
+// bits in CANxCTL0:\r
+#define BM_INITRQ 0x01\r
+#define BM_SLPRQ 0x02\r
+#define BM_WUPE 0x04\r
+\r
+// bits in CANxCTL1:\r
+#define BM_INITAK 0x01\r
+#define BM_SLPAK 0x02\r
+#define BM_WUPM 0x04\r
+#define BM_LISTEN 0x10\r
+#define BM_LOOPB 0x20\r
+#define BM_CLKSRC 0x40\r
+#define BM_CANE 0x80\r
+\r
+// bits in CANxRFLG:\r
+// bits in CANxRIER:\r
+#define BM_WUPI 0x80\r
+#define BM_CSCI 0x40\r
+#define BM_RSTAT1 0x20\r
+#define BM_RSTAT0 0x10\r
+#define BM_TSTAT1 0x08\r
+#define BM_TSTAT0 0x04\r
+#define BM_OVRI 0x02\r
+#define BM_RXF 0x01\r
+\r
+// bits in CANxTFLG:\r
+// bits in CANxTBSEL:\r
+#define BM_TX2 0x04\r
+#define BM_TX1 0x02\r
+#define BM_TX0 0x01\r
+\r
+typedef struct{\r
+ volatile uint8_t idr0; // Identifier Register 0\r
+ volatile uint8_t idr1;\r
+ volatile uint8_t idr2;\r
+ volatile uint8_t idr3;\r
+ volatile uint8_t ds0; // Data Segment Register 0\r
+ volatile uint8_t ds1;\r
+ volatile uint8_t ds2;\r
+ volatile uint8_t ds3;\r
+ volatile uint8_t ds4;\r
+ volatile uint8_t ds5;\r
+ volatile uint8_t ds6;\r
+ volatile uint8_t ds7;\r
+ volatile uint8_t dlr; // Data Length Register\r
+ volatile uint8_t tbpr; // Transmit Buffer Priority Register\r
+ volatile uint8_t tsr_hb; // Time Stamp Register (High Byte)\r
+ volatile uint8_t tsr_lb; // Time Stamp Register (Low Byte)\r
+} RxTxBuf_t;\r
+\r
+/*\r
+IDR0 : ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21\r
+IDR1 : ID20 ID19 ID18 SRR IDE ID17 ID16 ID15\r
+IDR2 : ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7\r
+IDR3 : ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR\r
+*/\r
+typedef union {\r
+ volatile uint8_t R[4];\r
+ struct {\r
+ volatile uint8_t id28to21;\r
+ volatile uint8_t id20to18:3;\r
+ volatile uint8_t SRR:1;\r
+ volatile uint8_t IDE:1;\r
+ volatile uint8_t id17to15:3;\r
+ volatile uint8_t id14to7;\r
+ volatile uint8_t id6to0:7;\r
+ volatile uint8_t RTR:1;\r
+ } Bit;\r
+} IdrType;\r
+\r
+\r
+typedef struct{\r
+ volatile uint8_t CTL0; /* control register 0 */\r
+ volatile uint8_t CTL1; /* control register 1 */\r
+ volatile uint8_t BTR0; /* bus timing register 0 */\r
+ volatile uint8_t BTR1; /* bus timing register 1 */\r
+ volatile uint8_t RFLG; /* receiver flag register */\r
+ volatile uint8_t RIER; /* receiver interrupt reg */\r
+ volatile uint8_t TFLG; /* transmitter flag reg */\r
+ volatile uint8_t TIER; /* transmitter control reg */\r
+ volatile uint8_t TARQ; /* transmitter abort request */\r
+ volatile uint8_t TAAK; /* transmitter abort acknowledge */\r
+ volatile uint8_t TBSEL; /* transmit buffer selection */\r
+ volatile uint8_t IDAC; /* identifier acceptance */\r
+ volatile uint8_t NOTUSED1;\r
+ volatile uint8_t NOTUSED2;\r
+ volatile uint8_t RXERR; /* receive error counter */\r
+ volatile uint8_t TXERR; /* transmit error counter */\r
+ volatile uint8_t IDAR0; /* id acceptance reg 0 */\r
+ volatile uint8_t IDAR1; /* id acceptance reg 1 */\r
+ volatile uint8_t IDAR2; /* id acceptance reg 2 */\r
+ volatile uint8_t IDAR3; /* id acceptance reg 3 */\r
+ volatile uint8_t IDMR0; /* id mask register 0 */\r
+ volatile uint8_t IDMR1; /* id mask register 1 */\r
+ volatile uint8_t IDMR2; /* id mask register 2 */\r
+ volatile uint8_t IDMR3; /* id mask register 3 */\r
+ volatile uint8_t IDAR4; /* id acceptance reg 4 */\r
+ volatile uint8_t IDAR5; /* id acceptance reg 5 */\r
+ volatile uint8_t IDAR6; /* id acceptance reg 6 */\r
+ volatile uint8_t IDAR7; /* id acceptance reg 7 */\r
+ volatile uint8_t IDMR4; /* id mask register 4 */\r
+ volatile uint8_t IDMR5; /* id mask register 5 */\r
+ volatile uint8_t IDMR6; /* id mask register 6 */\r
+ volatile uint8_t IDMR7; /* id mask register 7 */\r
+ volatile RxTxBuf_t RXFG; /* receive buffer */\r
+ volatile RxTxBuf_t TXFG; /* transmit buffer */\r
+} CAN_HW_t;\r
+\r
+/* CONFIGURATION NOTES\r
+ * ------------------------------------------------------------------\r
+ * - CanHandleType must be CAN_ARC_HANDLE_TYPE_BASIC\r
+ * i.e. CanHandleType=CAN_ARC_HANDLE_TYPE_FULL NOT supported\r
+ * i.e CanIdValue is NOT supported\r
+ * - All CanXXXProcessing must be CAN_ARC_PROCESS_TYPE_INTERRUPT\r
+ * ie CAN_ARC_PROCESS_TYPE_POLLED not supported\r
+ * - HOH's for Tx are global and Rx are for each controller\r
+ */\r
+\r
+/* IMPLEMENTATION NOTES\r
+ * -----------------------------------------------\r
+ * - A HOH us unique for a controller( not a config-set )\r
+ * - Hrh's are numbered for each controller from 0\r
+ * - Only one transmit mailbox is used because otherwise\r
+ * we cannot use tx_confirmation since there is no way to know\r
+ * which mailbox caused the tx interrupt. TP will need this feature.\r
+ * - Sleep,wakeup not fully implemented since other modules lack functionality\r
+ */\r
+\r
+/* ABBREVATIONS\r
+ * -----------------------------------------------\r
+ * - Can Hardware unit - One or multiple Can controllers of the same type.\r
+ * - Hrh - HOH with receive definitions\r
+ * - Hth - HOH with transmit definitions\r
+ *\r
+ */\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#define GET_CONTROLLER_CONFIG(_controller) \\r
+ &Can_Global.config->CanConfigSet->CanController[(_controller)]\r
+\r
+#define GET_CALLBACKS() \\r
+ (Can_Global.config->CanConfigSet->CanCallbacks)\r
+\r
+#define GET_PRIVATE_DATA(_controller) \\r
+ &CanUnit[_controller]\r
+\r
+#define GET_CONTROLLER_CNT() (CAN_CONTROLLER_CNT)\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( CAN_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return CAN_NOT_OK; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+#define VALIDATE_DEM_NO_RV(_exp,_err ) \\r
+ if( !(_exp) ) { \\r
+ Dem_ReportErrorStatus(_err, DEM_EVENT_STATUS_FAILED); \\r
+ return; \\r
+ }\r
+#else\r
+#define VALIDATE_DEM_NO_RV(_exp,_err )\r
+#endif\r
+\r
+//-------------------------------------------------------------------\r
+\r
+typedef enum\r
+{\r
+ CAN_UNINIT = 0,\r
+ CAN_READY\r
+} Can_DriverStateType;\r
+\r
+// Mapping between HRH and Controller//HOH\r
+typedef struct Can_Arc_ObjectHOHMapStruct\r
+{\r
+ CanControllerIdType CanControllerRef; // Reference to controller\r
+ const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.\r
+} Can_Arc_ObjectHOHMapType;\r
+\r
+/* Type for holding global information used by the driver */\r
+typedef struct {\r
+ Can_DriverStateType initRun;\r
+\r
+ // Our config\r
+ const Can_ConfigType *config;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[CAN_CONTROLLER_CNT];\r
+\r
+ // This is a map that maps the HTH:s with the controller and Hoh. It is built\r
+ // during Can_Init and is used to make things faster during a transmit.\r
+ Can_Arc_ObjectHOHMapType CanHTHMap[NUM_OF_HTHS];\r
+} Can_GlobalType;\r
+\r
+// Global config\r
+Can_GlobalType Can_Global =\r
+{\r
+ .initRun = CAN_UNINIT,\r
+};\r
+\r
+/* Type for holding information about each controller */\r
+typedef struct {\r
+ CanIf_ControllerModeType state;\r
+ uint32 lock_cnt;\r
+\r
+ // Statistics\r
+ Can_Arc_StatisticsType stats;\r
+\r
+ // Data stored for Txconfirmation callbacks to CanIf\r
+ PduIdType swPduHandle; //\r
+} Can_UnitType;\r
+\r
+Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =\r
+{\r
+ {\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },{\r
+ .state = CANIF_CS_UNINIT,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+\r
+static CAN_HW_t * GetController(int unit)\r
+{\r
+ CAN_HW_t *res = 0;\r
+\r
+ if(unit == CAN_CTRL_0)\r
+ {\r
+ res = (CAN_HW_t *)CAN0_BASE;\r
+ }\r
+ else if(unit == CAN_CTRL_1)\r
+ {\r
+ res = (CAN_HW_t *)CAN1_BASE;\r
+ }\r
+ else if(unit == CAN_CTRL_2)\r
+ {\r
+ res = (CAN_HW_t *)CAN2_BASE;\r
+ }\r
+ else if(unit == CAN_CTRL_3)\r
+ {\r
+ res = (CAN_HW_t *)CAN3_BASE;\r
+ }\r
+ else if(unit == CAN_CTRL_4)\r
+ {\r
+ res = (CAN_HW_t *)CAN4_BASE;\r
+ }\r
+\r
+ return res;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+/**\r
+ * Function that finds the Hoh( HardwareObjectHandle ) from a Hth\r
+ * A HTH may connect to one or several HOH's. Just find the first one.\r
+ *\r
+ * @param hth The transmit handle\r
+ * @returns Ptr to the Hoh\r
+ */\r
+static const Can_HardwareObjectType * Can_FindHoh( Can_Arc_HTHType hth , uint32* controller)\r
+{\r
+ const Can_HardwareObjectType *hohObj;\r
+ const Can_Arc_ObjectHOHMapType *map;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+\r
+ map = &Can_Global.CanHTHMap[hth];\r
+\r
+ // Verify that this is the correct map\r
+ if (map->CanHOHRef->CanObjectId != hth)\r
+ {\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+ }\r
+\r
+ canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[map->CanControllerRef]);\r
+\r
+ hohObj = map->CanHOHRef;\r
+\r
+ // Verify that this is the correct Hoh type\r
+ if ( hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ *controller = map->CanControllerRef;\r
+ return hohObj;\r
+ }\r
+\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+\r
+ return NULL;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+static void Can_RxIsr( int unit );\r
+static void Can_TxIsr( int unit );\r
+static void Can_ErrIsr( int unit );\r
+static void Can_WakeIsr( int unit );\r
+\r
+void Can_0_RxIsr( void ) { Can_RxIsr(CAN_CTRL_0); }\r
+void Can_1_RxIsr( void ) { Can_RxIsr(CAN_CTRL_1); }\r
+void Can_2_RxIsr( void ) { Can_RxIsr(CAN_CTRL_2); }\r
+void Can_3_RxIsr( void ) { Can_RxIsr(CAN_CTRL_3); }\r
+void Can_4_RxIsr( void ) { Can_RxIsr(CAN_CTRL_4); }\r
+\r
+void Can_0_TxIsr( void ) { Can_TxIsr(CAN_CTRL_0); }\r
+void Can_1_TxIsr( void ) { Can_TxIsr(CAN_CTRL_1); }\r
+void Can_2_TxIsr( void ) { Can_TxIsr(CAN_CTRL_2); }\r
+void Can_3_TxIsr( void ) { Can_TxIsr(CAN_CTRL_3); }\r
+void Can_4_TxIsr( void ) { Can_TxIsr(CAN_CTRL_4); }\r
+\r
+void Can_0_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_0); }\r
+void Can_1_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_1); }\r
+void Can_2_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_2); }\r
+void Can_3_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_3); }\r
+void Can_4_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_4); }\r
+\r
+void Can_0_WakeIsr( void ) { Can_WakeIsr(CAN_CTRL_0); }\r
+void Can_1_WakeIsr( void ) { Can_WakeIsr(CAN_CTRL_1); }\r
+void Can_2_WakeIsr( void ) { Can_WakeIsr(CAN_CTRL_2); }\r
+void Can_3_WakeIsr( void ) { Can_WakeIsr(CAN_CTRL_3); }\r
+void Can_4_WakeIsr( void ) { Can_WakeIsr(CAN_CTRL_4); }\r
+\r
+//-------------------------------------------------------------------\r
+\r
+// Uses 25.4.5.1 Transmission Abort Mechanism\r
+static void Can_AbortTx( CAN_HW_t *canHw, Can_UnitType *canUnit ) {\r
+ uint8_t mask = 0;\r
+\r
+ // Disable Transmit irq\r
+ canHw->TIER = 0;\r
+\r
+ // check if mb's empty\r
+ if((canHw->TFLG & BM_TX0) == 0){mask |= BM_TX0;}\r
+ if((canHw->TFLG & BM_TX1) == 0){mask |= BM_TX1;}\r
+ if((canHw->TFLG & BM_TX2) == 0){mask |= BM_TX2;}\r
+\r
+ canHw->TARQ = mask; // Abort all pending mb's\r
+\r
+ // Wait for mb's being emptied\r
+ int i=0;\r
+ while(canHw->TFLG != (BM_TX0 | BM_TX1 | BM_TX2)){\r
+ i++;\r
+ if(i > 100)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * Hardware wake ISR for CAN\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_WakeIsr( int unit ) {\r
+ if (GET_CALLBACKS()->ControllerWakeup != NULL)\r
+ {\r
+ GET_CALLBACKS()->ControllerWakeup(unit);\r
+ }\r
+ // 269,270,271\r
+ Can_SetControllerMode(unit, CAN_T_STOP);\r
+\r
+ // TODO EcuM_CheckWakeup();\r
+}\r
+\r
+/**\r
+ * Hardware error ISR for CAN\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_ErrIsr( int unit ) {\r
+ CAN_HW_t *canHw = GetController(unit);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
+ Can_Arc_ErrorType err;\r
+ err.R = 0;\r
+ uint8_t rflg = canHw->RFLG;\r
+\r
+ if((rflg & BM_OVRI) == BM_OVRI){\r
+ err.B.FRMERR = 1;\r
+\r
+ // Clear ERRINT\r
+ canHw->RFLG = BM_OVRI;\r
+ }\r
+\r
+ if((rflg & BM_CSCI) == BM_CSCI){\r
+ if( ((rflg & (BM_RSTAT0 | BM_RSTAT0)) == (BM_RSTAT0 | BM_RSTAT1)) ||\r
+ ((rflg & (BM_TSTAT0 | BM_TSTAT0)) == (BM_TSTAT0 | BM_TSTAT1)) )\r
+ {\r
+ canUnit->stats.boffCnt++;\r
+ if (GET_CALLBACKS()->ControllerBusOff != NULL)\r
+ {\r
+ GET_CALLBACKS()->ControllerBusOff(unit);\r
+ }\r
+ Can_SetControllerMode(unit, CAN_T_STOP); // CANIF272\r
+\r
+ Can_AbortTx( canHw, canUnit ); // CANIF273\r
+ }\r
+\r
+ // Clear ERRINT\r
+ canHw->RFLG = BM_CSCI;\r
+ }\r
+\r
+ if (err.R != 0)\r
+ {\r
+ if (GET_CALLBACKS()->Arc_Error != NULL)\r
+ {\r
+ GET_CALLBACKS()->Arc_Error( unit, err );\r
+ }\r
+ }\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * ISR for CAN. Normal Rx/operation\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_RxIsr(int unit) {\r
+\r
+ CAN_HW_t *canHw= GetController(unit);\r
+ const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
+ const Can_HardwareObjectType *hohObj;\r
+\r
+ // Loop over all the Hoh's\r
+ hohObj= canHwConfig->Can_Arc_Hoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
+ {\r
+ Can_IdType id=0;\r
+ IdrType *idr;\r
+ idr = (IdrType *)&canHw->RXFG.idr0;\r
+\r
+ // According to autosar MSB shuould be set if extended\r
+ if (idr->Bit.IDE == 1) {\r
+ id = ((uint32)idr->Bit.id28to21 << 21) | ((uint32)idr->Bit.id20to18 << 18) | ((uint32)idr->Bit.id17to15 << 15) |\r
+ ((uint32)idr->Bit.id14to7 << 7) | idr->Bit.id6to0;\r
+ id |= 0x80000000;\r
+ } else {\r
+ id = ((uint32)idr->Bit.id28to21 << 3) | (uint32)idr->Bit.id20to18;\r
+ }\r
+\r
+ if (GET_CALLBACKS()->RxIndication != NULL)\r
+ {\r
+ GET_CALLBACKS()->RxIndication(hohObj->CanObjectId,\r
+ id,\r
+ canHw->RXFG.dlr,\r
+ (uint8 *)&canHw->RXFG.ds0 ); // Next layer will copy\r
+ }\r
+ // Increment statistics\r
+ canUnit->stats.rxSuccessCnt++;\r
+\r
+ // Clear interrupt\r
+ canHw->RFLG = BM_RXF; // clear RX flag\r
+ }\r
+ } while ( !hohObj->Can_Arc_EOL);\r
+}\r
+\r
+/**\r
+ * ISR for CAN. Normal Tx operation\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_TxIsr(int unit) {\r
+ CAN_HW_t *canHw= GetController(unit);\r
+ const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
+ const Can_HardwareObjectType *hohObj;\r
+\r
+ // Loop over all the Hoh's\r
+ hohObj= canHwConfig->Can_Arc_Hoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ if (GET_CALLBACKS()->TxConfirmation != NULL)\r
+ {\r
+ GET_CALLBACKS()->TxConfirmation(canUnit->swPduHandle);\r
+ }\r
+ canUnit->swPduHandle = 0; // Is this really necessary ??\r
+\r
+ // Disable Tx interrupt\r
+ canHw->TIER = 0;\r
+ }\r
+ } while ( !hohObj->Can_Arc_EOL);\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#define INSTALL_HANDLERS(_can_name,_err,_wake,_rx,_tx) \\r
+ do { \\r
+ TaskType tid; \\r
+ tid = Os_Arc_CreateIsr(_can_name ## _ErrIsr,2/*prio*/,"Can"); \\r
+ Irq_AttachIsr2(tid,NULL,_err); \\r
+ tid = Os_Arc_CreateIsr(_can_name ## _WakeIsr,2/*prio*/,"Can"); \\r
+ Irq_AttachIsr2(tid,NULL,_wake); \\r
+ tid = Os_Arc_CreateIsr(_can_name ## _RxIsr,2/*prio*/,"Can"); \\r
+ Irq_AttachIsr2(tid,NULL,_rx); \\r
+ tid = Os_Arc_CreateIsr(_can_name ## _TxIsr,2/*prio*/,"Can"); \\r
+ Irq_AttachIsr2(tid,NULL,_tx); \\r
+ } while(0);\r
+\r
+// This initiates ALL can controllers\r
+void Can_Init( const Can_ConfigType *config ) {\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint8 ctlrId;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_UNINIT), 0x0, CAN_E_TRANSITION );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x0, CAN_E_PARAM_POINTER );\r
+\r
+ // Save config\r
+ Can_Global.config = config;\r
+ Can_Global.initRun = CAN_READY;\r
+\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Can_Global.channelMap[canHwConfig->CanControllerId] = configId;\r
+ Can_Global.configured |= (1<<ctlrId);\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));\r
+\r
+ // Note!\r
+ // Could install handlers depending on HW objects to trap more errors\r
+ // in configuration\r
+ if( canHwConfig->CanControllerId == CAN_CTRL_0) {\r
+ INSTALL_HANDLERS(Can_0, IRQ_TYPE_CAN0_ERR, IRQ_TYPE_CAN0_WAKE, IRQ_TYPE_CAN0_RX, IRQ_TYPE_CAN0_TX);\r
+ }\r
+ else if( canHwConfig->CanControllerId == CAN_CTRL_1) {\r
+ INSTALL_HANDLERS(Can_1, IRQ_TYPE_CAN1_ERR, IRQ_TYPE_CAN1_WAKE, IRQ_TYPE_CAN1_RX, IRQ_TYPE_CAN1_TX);\r
+ }\r
+ else if( canHwConfig->CanControllerId == CAN_CTRL_2) {\r
+ INSTALL_HANDLERS(Can_2, IRQ_TYPE_CAN2_ERR, IRQ_TYPE_CAN2_WAKE, IRQ_TYPE_CAN2_RX, IRQ_TYPE_CAN2_TX);\r
+ }\r
+ else if( canHwConfig->CanControllerId == CAN_CTRL_3) {\r
+ INSTALL_HANDLERS(Can_3, IRQ_TYPE_CAN3_ERR, IRQ_TYPE_CAN3_WAKE, IRQ_TYPE_CAN3_RX, IRQ_TYPE_CAN3_TX);\r
+ }\r
+ else if( canHwConfig->CanControllerId == CAN_CTRL_4) {\r
+ INSTALL_HANDLERS(Can_4, IRQ_TYPE_CAN4_ERR, IRQ_TYPE_CAN4_WAKE, IRQ_TYPE_CAN4_RX, IRQ_TYPE_CAN4_TX);\r
+ }\r
+\r
+ Can_InitController(ctlrId, canHwConfig);\r
+\r
+ // Loop through all Hoh:s and map them into the HTHMap\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = canHwConfig->Can_Arc_Hoh;\r
+ hoh--;\r
+ do\r
+ {\r
+ hoh++;\r
+\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanControllerRef = canHwConfig->CanControllerId;\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return;\r
+}\r
+\r
+// Unitialize the module\r
+void Can_DeInit()\r
+{\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint32 ctlrId;\r
+\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_UNINIT;\r
+\r
+ Can_DisableControllerInterrupts(ctlrId);\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));\r
+ }\r
+\r
+ Can_Global.config = NULL;\r
+ Can_Global.initRun = CAN_UNINIT;\r
+\r
+ return;\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)\r
+{\r
+ CAN_HW_t *canHw;\r
+ uint8_t tq;\r
+ uint8_t tqSync;\r
+ uint8_t tq1;\r
+ uint8_t tq2;\r
+ uint32_t clock;\r
+ Can_UnitType *canUnit;\r
+ uint8 cId = controller;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ const Can_HardwareObjectType *hohObj;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_READY), 0x2, CAN_E_UNINIT );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x2,CAN_E_PARAM_POINTER);\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x2, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state==CANIF_CS_STOPPED), 0x2, CAN_E_TRANSITION );\r
+\r
+ canHw = GetController(cId);\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[cId]);\r
+\r
+ // Start this baby up\r
+ canHw->CTL0 = BM_INITRQ; // request Init Mode\r
+ while((canHw->CTL1 & BM_INITAK) == 0); // wait until Init Mode is established\r
+\r
+ // set CAN enable bit, deactivate listen-only mode,\r
+ // use Bus Clock as clock source and select loop back mode on/off\r
+ canHw->CTL1 = BM_CANE | BM_CLKSRC | (config->Can_Arc_Loopback ? BM_LOOPB : 0x00);\r
+\r
+ // acceptance filters\r
+ hohObj = canHwConfig->Can_Arc_Hoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
+ {\r
+ canHw->IDAC = hohObj->CanFilterMaskRef->idam;\r
+ canHw->IDAR0 = hohObj->CanFilterMaskRef->idar[0];\r
+ canHw->IDAR1 = hohObj->CanFilterMaskRef->idar[1];\r
+ canHw->IDAR2 = hohObj->CanFilterMaskRef->idar[2];\r
+ canHw->IDAR3 = hohObj->CanFilterMaskRef->idar[3];\r
+ canHw->IDAR4 = hohObj->CanFilterMaskRef->idar[4];\r
+ canHw->IDAR5 = hohObj->CanFilterMaskRef->idar[5];\r
+ canHw->IDAR6 = hohObj->CanFilterMaskRef->idar[6];\r
+ canHw->IDAR7 = hohObj->CanFilterMaskRef->idar[7];\r
+ canHw->IDMR0 = hohObj->CanFilterMaskRef->idmr[0];\r
+ canHw->IDMR1 = hohObj->CanFilterMaskRef->idmr[1];\r
+ canHw->IDMR2 = hohObj->CanFilterMaskRef->idmr[2];\r
+ canHw->IDMR3 = hohObj->CanFilterMaskRef->idmr[3];\r
+ canHw->IDMR4 = hohObj->CanFilterMaskRef->idmr[4];\r
+ canHw->IDMR5 = hohObj->CanFilterMaskRef->idmr[5];\r
+ canHw->IDMR6 = hohObj->CanFilterMaskRef->idmr[6];\r
+ canHw->IDMR7 = hohObj->CanFilterMaskRef->idmr[7];\r
+ }\r
+ }while( !hohObj->Can_Arc_EOL );\r
+\r
+ // Clock calucation\r
+ // -------------------------------------------------------------------\r
+ //\r
+ // * 1 TQ = Sclk period( also called SCK )\r
+ // * Ftq = Fcanclk / ( PRESDIV + 1 ) = Sclk\r
+ // ( Fcanclk can come from crystal or from the peripheral dividers )\r
+ //\r
+ // -->\r
+ // TQ = 1/Ftq = (PRESDIV+1)/Fcanclk --> PRESDIV = (TQ * Fcanclk - 1 )\r
+ // TQ is between 8 and 25\r
+ clock = McuE_GetSystemClock()/2;\r
+\r
+ tqSync = config->CanControllerPropSeg + 1;\r
+ tq1 = config->CanControllerSeg1 + 1;\r
+ tq2 = config->CanControllerSeg2 + 1;\r
+ tq = tqSync + tq1 + tq2;\r
+\r
+ // Check TQ limitations..\r
+ VALIDATE_DEM_NO_RV(( (tq1>=1) && (tq1<=16)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq2>=1) && (tq2<=8)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq>=3) && (tq<25 )), CAN_E_TIMEOUT );\r
+\r
+ canHw->BTR0 = (config->CanControllerPropSeg << 6) | (uint8)(clock/(config->CanControllerBaudRate*1000*tq) - 1); // Prescaler\r
+ canHw->BTR1 = (config->CanControllerSeg2 << 4) | config->CanControllerSeg1;\r
+\r
+ canHw->CTL0 &= ~BM_INITRQ; // exit Init Mode\r
+ while((canHw->CTL1 & BM_INITAK) != 0);// wait until Normal Mode is established\r
+\r
+ canHw->TBSEL = BM_TX0; // use (only) TX buffer 0\r
+\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_EnableControllerInterrupts(cId);\r
+\r
+ return;\r
+}\r
+\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 controller, Can_StateTransitionType transition ) {\r
+ CAN_HW_t *canHw;\r
+ Can_ReturnType rv = CAN_OK;\r
+ VALIDATE( (controller < GET_CONTROLLER_CNT()), 0x3, CAN_E_PARAM_CONTROLLER );\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE( (canUnit->state!=CANIF_CS_UNINIT), 0x3, CAN_E_UNINIT );\r
+ canHw = GetController(controller);\r
+\r
+ switch(transition )\r
+ {\r
+ case CAN_T_START:\r
+ canUnit->state = CANIF_CS_STARTED;\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if (canUnit->lock_cnt == 0){ // REQ CAN196\r
+ Can_EnableControllerInterrupts(controller);\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+ break;\r
+ case CAN_T_WAKEUP:\r
+ VALIDATE(canUnit->state == CANIF_CS_SLEEP, 0x3, CAN_E_TRANSITION);\r
+ canHw->CTL0 &= ~BM_SLPRQ; // Clear Sleep request\r
+ canHw->CTL0 &= ~BM_WUPE; // Clear Wake up enable\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+ break;\r
+ case CAN_T_SLEEP: //CAN258, CAN290\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ canHw->CTL0 |= BM_WUPE; // Set wake up enable\r
+ canHw->CTL0 |= BM_SLPRQ; // Set sleep request\r
+ canHw->RIER |= BM_WUPI; // Enable wake up irq\r
+ canUnit->state = CANIF_CS_SLEEP;\r
+ break;\r
+ case CAN_T_STOP:\r
+ // Stop\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_AbortTx( canHw, canUnit ); // CANIF282\r
+ break;\r
+ default:\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ break;\r
+ }\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+ Can_UnitType *canUnit;\r
+ CAN_HW_t *canHw;\r
+\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x4, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x4, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if(canUnit->lock_cnt > 0 )\r
+ {\r
+ // Interrupts already disabled\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ }\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ /* Don't try to be intelligent, turn everything off */\r
+ canHw = GetController(controller);\r
+\r
+ /* Turn off the tx interrupt mailboxes */\r
+ canHw->TIER = 0;\r
+\r
+ /* Turn off the bus off/tx warning/rx warning and error and rx */\r
+ canHw->RIER = 0;\r
+ }\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller ) {\r
+ Can_UnitType *canUnit;\r
+ CAN_HW_t *canHw;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x5, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x5, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if( canUnit->lock_cnt > 1 )\r
+ {\r
+ // IRQ should still be disabled so just decrement counter\r
+ canUnit->lock_cnt--;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ } else if (canUnit->lock_cnt == 1)\r
+ {\r
+ canUnit->lock_cnt = 0;\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ canHw = GetController(controller);\r
+\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);\r
+\r
+ if( canHwConfig->CanRxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the rx interrupt */\r
+ canHw->RIER |= BM_RXF;\r
+ }\r
+\r
+ // BusOff here represents all errors and warnings\r
+ if( canHwConfig->CanBusOffProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn off the bus off/tx warning/rx warning and error and rx */\r
+ canHw->RIER |= BM_WUPI | BM_CSCI | BM_OVRI | BM_RXF | BM_RSTAT0 | BM_TSTAT0;\r
+ }\r
+\r
+ return;\r
+}\r
+\r
+static IdrType ConstructIdBytes(Can_IdType id, Can_IdTypeType idType)\r
+{\r
+ IdrType idr;\r
+\r
+ idr.R[3] = idr.R[2] = idr.R[1] = idr.R[0] = 0;\r
+\r
+ if(idType == CAN_ID_TYPE_EXTENDED) {\r
+ idr.Bit.SRR = 1;\r
+ idr.Bit.RTR = 0;\r
+ idr.Bit.IDE = 1;\r
+ idr.Bit.id28to21 = id>>21;\r
+ idr.Bit.id20to18 = id>>18 & 0x07;\r
+ idr.Bit.id17to15 = id>>15 & 0x07;\r
+ idr.Bit.id14to7 = id>>7;\r
+ idr.Bit.id6to0 = id & 0x7F;\r
+ } else if (idType == CAN_ID_TYPE_STANDARD) {\r
+ idr.R[0] = id>>3;\r
+ idr.R[1] = id<<5 & 0xE0;\r
+ } else {\r
+ // No support for mixed in this processor\r
+ assert(0);\r
+ }\r
+\r
+ return idr;\r
+}\r
+\r
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo ) {\r
+ Can_ReturnType rv = CAN_OK;\r
+ CAN_HW_t *canHw;\r
+ const Can_HardwareObjectType *hohObj;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint32 controller;\r
+ uint32 oldMsr;\r
+ IdrType idr;\r
+\r
+ VALIDATE( (Can_Global.initRun == CAN_READY), 0x6, CAN_E_UNINIT );\r
+ VALIDATE( (pduInfo != NULL), 0x6, CAN_E_PARAM_POINTER );\r
+ VALIDATE( (pduInfo->length <= 8), 0x6, CAN_E_PARAM_DLC );\r
+ VALIDATE( (hth < NUM_OF_HTHS ), 0x6, CAN_E_PARAM_HANDLE );\r
+\r
+ hohObj = Can_FindHoh(hth, &controller);\r
+ if (hohObj == NULL)\r
+ return CAN_NOT_OK;\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ canHw = GetController(controller);\r
+ oldMsr = McuE_EnterCriticalSection();\r
+\r
+ // check for any free box\r
+ if((canHw->TFLG & BM_TX0) == BM_TX0) {\r
+ canHw->TBSEL = BM_TX0; // Select mb0\r
+\r
+ idr = ConstructIdBytes(pduInfo->id, hohObj->CanIdType);\r
+\r
+ canHw->TXFG.idr0 = idr.R[0];\r
+ canHw->TXFG.idr1 = idr.R[1];\r
+ canHw->TXFG.idr2 = idr.R[2];\r
+ canHw->TXFG.idr3 = idr.R[3];\r
+\r
+ memcpy((uint8 *)&canHw->TXFG.ds0, pduInfo->sdu, pduInfo->length);\r
+ canHw->TXFG.dlr = pduInfo->length;\r
+ canHw->TXFG.tbpr = 0; // Highest prio\r
+\r
+ // Send\r
+ canHw->TFLG = BM_TX0;\r
+\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);\r
+\r
+ if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the tx interrupt mailboxes */\r
+ canHw->TIER |= BM_TX0; // We only use TX0\r
+ }\r
+\r
+ // Increment statistics\r
+ canUnit->stats.txSuccessCnt++;\r
+\r
+ // Store pdu handle in unit to be used by TxConfirmation\r
+ canUnit->swPduHandle = pduInfo->swPduHandle;\r
+ } else {\r
+ rv = CAN_BUSY;\r
+ }\r
+ McuE_ExitCriticalSection(oldMsr);\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_MainFunction_Read( void ) {\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_BusOff( void ) {\r
+ /* Bus-off polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_Wakeup( void ) {\r
+ /* Wakeup polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+\r
+/**\r
+ * Get send/receive/error statistics for a controller\r
+ *\r
+ * @param controller The controller\r
+ * @param stats Pointer to data to copy statistics to\r
+ */\r
+\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType *stats)\r
+{\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+ *stats = canUnit->stats;\r
+}\r
+\r
+#else // Stub all functions for use in simulator environment\r
+\r
+#include "debug.h"\r
+\r
+void Can_Init( const Can_ConfigType *Config )\r
+{\r
+ // Do initial configuration of layer here\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)\r
+{\r
+ // Do initialisation of controller here.\r
+}\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 Controller, Can_StateTransitionType transition )\r
+{\r
+ // Turn on off controller here depending on transition\r
+ return E_OK;\r
+}\r
+\r
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo )\r
+{\r
+ // Write to mailbox on controller here.\r
+ DEBUG(DEBUG_MEDIUM, "Can_Write(stub): Received data ");\r
+ for (int i = 0; i < pduInfo->length; i++) {\r
+ DEBUG(DEBUG_MEDIUM, "%d ", pduInfo->sdu[i]);\r
+ }\r
+ DEBUG(DEBUG_MEDIUM, "\n");\r
+\r
+ return E_OK;\r
+}\r
+\r
+extern void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc, const uint8 *CanSduPtr);\r
+Can_ReturnType Can_ReceiveAFrame()\r
+{\r
+ // This function is not part of autosar but needed to feed the stack with data\r
+ // from the mailboxes. Normally this is an interrup but probably not in the PCAN case.\r
+ uint8 CanSduData[] = {1,2,1,0,0,0,0,0};\r
+ CanIf_RxIndication(CAN_HRH_0_1, 3, 8, CanSduData);\r
+\r
+ return E_OK;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+\r
+// Hth - for Flexcan, the hardware message box number... .We don't care\r
+void Can_Cbk_CheckWakeup( uint8 controller ){}\r
+\r
+void Can_MainFunction_Write( void ){}\r
+void Can_MainFunction_Read( void ){}\r
+void Can_MainFunction_BusOff( void ){}\r
+void Can_MainFunction_Wakeup( void ){}\r
+\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType * stat){}\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Std_Types.h"\r
+#include "Dio.h"\r
+#include "Det.h"\r
+#include <string.h>\r
+#include "regs.h"\r
+\r
+#define DIO_GET_PORT_FROM_CHANNEL_ID(_channelId) (_channelId / 8)\r
+#define DIO_GET_BIT_FROM_CHANNEL_ID(_channelId) (1 << (_channelId % 8))\r
+#define CHANNEL_PTR (&DioChannelConfigData)\r
+#define CHANNEL_GRP_PTR (&DioConfigData)\r
+#define PORT_PTR (&DioPortConfigData)\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+static int Channel_Config_Contains(Dio_ChannelType channelId)\r
+{\r
+ Dio_ChannelType* ch_ptr=(Dio_ChannelType*)CHANNEL_PTR;\r
+ int rv=0;\r
+ while ((Dio_ChannelType)DIO_END_OF_LIST!=*ch_ptr)\r
+ {\r
+ if (*ch_ptr==channelId)\r
+ {\r
+ rv=1;\r
+ break;\r
+ }\r
+ ch_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Port_Config_Contains(Dio_PortType portId)\r
+{\r
+ Dio_PortType* port_ptr=(Dio_PortType*)PORT_PTR;\r
+ int rv=0;\r
+ while ((Dio_PortType)DIO_END_OF_LIST!=*port_ptr)\r
+ {\r
+ if (*port_ptr==portId)\r
+ {\r
+ rv=1;\r
+ break;\r
+ }\r
+ port_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Channel_Group_Config_Contains(const Dio_ChannelGroupType* _channelGroupIdPtr)\r
+{\r
+ Dio_ChannelGroupType* chGrp_ptr=(Dio_ChannelGroupType*)CHANNEL_GRP_PTR;\r
+ int rv=0;\r
+\r
+ while ((Dio_PortType)DIO_END_OF_LIST!=chGrp_ptr->port)\r
+ {\r
+ if (chGrp_ptr->port==_channelGroupIdPtr->port\r
+ && chGrp_ptr->offset==_channelGroupIdPtr->offset\r
+ && chGrp_ptr->mask==_channelGroupIdPtr->mask)\r
+ {\r
+ rv=1;\r
+ break;\r
+ }\r
+ chGrp_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+#define VALIDATE_CHANNEL(_channelId, _api) \\r
+ if(0==Channel_Config_Contains(channelId)) { \\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_CHANNEL_ID ); \\r
+ level = 0; \\r
+ goto cleanup; \\r
+ }\r
+#define VALIDATE_PORT(_portId, _api)\\r
+ if(0==Port_Config_Contains(_portId)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_PORT_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\\r
+ if(0==Channel_Group_Config_Contains(_channelGroupIdPtr)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_GROUP_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#else\r
+#define VALIDATE_CHANNEL(_channelId, _api)\r
+#define VALIDATE_PORT(_portId, _api)\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\r
+#endif\r
+\r
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNEL(channelId, DIO_READCHANNEL_ID);\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId));\r
+ Dio_PortLevelType bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if ((portVal & bit) != STD_LOW){\r
+ level = STD_HIGH;\r
+ } else {\r
+ level = STD_LOW;\r
+ }\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return (level);\r
+}\r
+\r
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level)\r
+{\r
+ VALIDATE_CHANNEL(channelId, DIO_WRITECHANNEL_ID);\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId));\r
+ Dio_PortLevelType bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if(level == STD_HIGH){\r
+ portVal |= bit;\r
+ } else {\r
+ portVal &= ~bit;\r
+ }\r
+\r
+ Dio_WritePort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId), portVal);\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
+\r
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId)\r
+{\r
+ Dio_LevelType level = 0;\r
+ VALIDATE_PORT(portId, DIO_READPORT_ID);\r
+\r
+ if(portId == DIO_PORT_A){level = PORTA;}\r
+ else if(portId == DIO_PORT_B){level = PORTB;}\r
+ else if(portId == DIO_PORT_E){level = PORTE;}\r
+ else if(portId == DIO_PORT_J){level = PTJ;}\r
+ else if(portId == DIO_PORT_K){level = PORTK;}\r
+ else if(portId == DIO_PORT_M){level = PTM;}\r
+ else if(portId == DIO_PORT_P){level = PTP;}\r
+ else if(portId == DIO_PORT_S){level = PTS;}\r
+ else if(portId == DIO_PORT_T){level = PTT;}\r
+ else if(portId == DIO_PORT_H){level = PTH;}\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
+}\r
+\r
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level)\r
+{\r
+ VALIDATE_PORT(portId, DIO_WRITEPORT_ID);\r
+\r
+ if(portId == DIO_PORT_A){PORTA = level;}\r
+ else if(portId == DIO_PORT_B){PORTB = level;}\r
+ else if(portId == DIO_PORT_E){PORTE = level;}\r
+ else if(portId == DIO_PORT_J){PTJ = level;}\r
+ else if(portId == DIO_PORT_K){PORTK = level;}\r
+ else if(portId == DIO_PORT_M){PTM = level;}\r
+ else if(portId == DIO_PORT_P){PTP = level;}\r
+ else if(portId == DIO_PORT_S){PTS = level;}\r
+ else if(portId == DIO_PORT_T){PTT = level;}\r
+ else if(portId == DIO_PORT_H){PTH = level;}\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
+\r
+Dio_PortLevelType Dio_ReadChannelGroup(\r
+ const Dio_ChannelGroupType *channelGroupIdPtr)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_READCHANNELGROUP_ID);\r
+\r
+ // Get masked values\r
+ level = Dio_ReadPort(channelGroupIdPtr->port) & channelGroupIdPtr->mask;\r
+\r
+ // Shift down\r
+ level = level >> channelGroupIdPtr->offset;\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
+}\r
+\r
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr,\r
+ Dio_PortLevelType level)\r
+{\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_WRITECHANNELGROUP_ID);\r
+\r
+ // Shift up and apply mask so that no unwanted bits are affected\r
+ level = (level << channelGroupIdPtr->offset) & channelGroupIdPtr->mask;\r
+\r
+ // Read port and clear out masked bits\r
+ Dio_PortLevelType portVal = Dio_ReadPort(channelGroupIdPtr->port) & (~channelGroupIdPtr->mask);\r
+\r
+ // Or in the upshifted masked level\r
+ portVal |= level;\r
+\r
+ Dio_WritePort(channelGroupIdPtr->port, portVal);\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
+}\r
#include "Mcu.h"\r
#include "debug.h"\r
#include "Det.h"\r
-#include "irq_types.h"\r
#include "Os.h"\r
#include "arc.h"\r
+#include "irq.h"\r
\r
#define FIRST_OC_REG 0x50\r
\r
// period is in "ticks" !!\r
void Gpt_StartTimer(Gpt_ChannelType channel, Gpt_ValueType period_ticks)\r
{\r
- uint32_t tmp;\r
int confCh;\r
\r
VALIDATE( (Gpt_Global.initRun == STD_ON), GPT_STARTTIMER_SERVICE_ID, GPT_E_UNINIT );\r
#include <string.h>\r
#include "Ramlog.h"\r
\r
-#define USE_TRACE 1\r
#define USE_LDEBUG_PRINTF 1\r
#include "debug.h"\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Std_Types.h"\r
+#include "Port.h" /** @req PORT131 */\r
+#include "regs.h"\r
+#include "Det.h"\r
+#include <string.h>\r
+\r
+/* SHORT ON HW\r
+ * Have a bunch of ports:\r
+ * - PA, PB, PE, PK is CPU registers (used as address bus if external RAM is used)\r
+ * - PH, PJ, PM, PP, PS, PT is peripheral registers\r
+ */\r
+\r
+typedef enum\r
+{\r
+ PORT_UNINITIALIZED = 0, PORT_INITIALIZED,\r
+} Port_StateType;\r
+\r
+static Port_StateType _portState = PORT_UNINITIALIZED;\r
+static const Port_ConfigType * _configPtr = NULL;\r
+\r
+/** @req PORT107 */\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api) \\r
+ if( (_ptr)==((void *)0) ) { \\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_CONFIG ); \\r
+ return; \\r
+ }\r
+\r
+#define VALIDATE_STATE_INIT(_api)\\r
+ if(PORT_INITIALIZED!=_portState){\\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_UNINIT ); \\r
+ return; \\r
+ }\r
+\r
+#else\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api)\r
+#define VALIDATE_STATE_INIT(_api)\r
+#define VALIDATE_PARAM_PIN(_api)\r
+#endif\r
+\r
+#if PORT_VERSION_INFO_API == STD_ON\r
+static Std_VersionInfoType _Port_VersionInfo =\r
+{\r
+ .vendorID = (uint16)1,\r
+ .moduleID = (uint16) MODULE_ID_PORT,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)PORT_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)PORT_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)PORT_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)PORT_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)PORT_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)PORT_AR_PATCH_VERSION, };\r
+#endif\r
+\r
+/** @req PORT140 */\r
+/** @req PORT041 Comment: To reduce flash usage the configuration tool can disable configuration of some ports */\r
+/** @req PORT078 See environment i.e Ecu State Manager */\r
+/** @req PORT042 */\r
+/** @req PORT113 Number 2 in list is applicable for all pins. */\r
+/** @req PORT043 Comment: Output value is set before direction */\r
+/** @req PORT071 See environment i.e Ecu State Manager */\r
+/** @req PORT002 The _portState varialble is initialised. */\r
+/** @req PORT003 See environment i.e Ecu State Manager */\r
+/** @req PORT055 Comment: Output value is set before direction */\r
+/** @req PORT121 */\r
+void Port_Init(const Port_ConfigType *configType)\r
+{\r
+ VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID); /** @req PORT105 */\r
+\r
+ // Setup pin drives and pullups\r
+ RDRIV = configType->coreReducedDriveRegister;\r
+ PUCR = configType->corePullUpRegister;\r
+\r
+ // CAN and SPI routing of pins\r
+ MODDR = configType->modeRoutingRegister;\r
+\r
+ // Setup ports\r
+#if ( PORTA_CONFIGURABLE == STD_ON )\r
+ PORTA = configType->portAOutValue;\r
+ DDRA = configType->portADirection;\r
+#endif\r
+\r
+#if ( PORTB_CONFIGURABLE == STD_ON )\r
+ PORTB = configType->portBOutValue;\r
+ DDRB = configType->portBDirection;\r
+#endif\r
+\r
+#if ( PORTE_CONFIGURABLE == STD_ON )\r
+ PORTE = configType->portEOutValue;\r
+ DDRE = configType->portEDirection;\r
+#endif\r
+\r
+#if ( PORTK_CONFIGURABLE == STD_ON )\r
+ PORTK = configType->portKOutValue;\r
+ DDRK = configType->portKDirection;\r
+#endif\r
+\r
+#if ( PORTH_CONFIGURABLE == STD_ON )\r
+ RDRH = configType->portHReducedDriveRegister;\r
+ PERH = configType->portHPullEnableRegister;\r
+ PPSH = configType->portHPullPolarityRegsiter;\r
+ PTH = configType->portHOutValue;\r
+ DDRH = configType->portHDirection;\r
+#endif\r
+\r
+#if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ RDRJ = configType->portJReducedDriveRegister;\r
+ PERJ = configType->portJPullEnableRegister;\r
+ PPSJ = configType->portJPullPolarityRegsiter;\r
+ PTJ = configType->portJOutValue;\r
+ DDRJ = configType->portJDirection;\r
+#endif\r
+\r
+#if ( PORTM_CONFIGURABLE == STD_ON )\r
+ RDRM = configType->portMReducedDriveRegister;\r
+ PERM = configType->portMPullEnableRegister;\r
+ PPSM = configType->portMPullPolarityRegsiter;\r
+ WOMM = configType->portMWiredModeRegsiter;\r
+ PTM = configType->portMOutValue;\r
+ DDRM = configType->portMDirection;\r
+#endif\r
+\r
+#if ( PORTP_CONFIGURABLE == STD_ON )\r
+ RDRP = configType->portPReducedDriveRegister;\r
+ PERP = configType->portPPullEnableRegister;\r
+ PPSP = configType->portPPullPolarityRegsiter;\r
+ PTP = configType->portPOutValue;\r
+ DDRP = configType->portPDirection;\r
+#endif\r
+\r
+#if ( PORTS_CONFIGURABLE == STD_ON )\r
+ RDRS = configType->portSReducedDriveRegister;\r
+ PERS = configType->portSPullEnableRegister;\r
+ PPSS = configType->portSPullPolarityRegsiter;\r
+ WOMS = configType->portSWiredModeRegsiter;\r
+ PTS = configType->portSOutValue;\r
+ DDRS = configType->portSDirection;\r
+#endif\r
+\r
+#if ( PORTT_CONFIGURABLE == STD_ON )\r
+ RDRT = configType->portTReducedDriveRegister;\r
+ PERT = configType->portTPullEnableRegister;\r
+ PPST = configType->portTPullPolarityRegsiter;\r
+ PTT = configType->portTOutValue;\r
+ DDRT = configType->portTDirection;\r
+#endif\r
+\r
+ _portState = PORT_INITIALIZED;\r
+ _configPtr = configType;\r
+\r
+ return;\r
+}\r
+\r
+/** @req PORT141 */\r
+/** @req PORT063 */\r
+/** @req PORT054 */\r
+/** @req PORT086 */\r
+#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )\r
+void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
+ uint16_t base;\r
+ uint8_t bitmask;\r
+ uint8_t curValue;\r
+\r
+ base = pin & PORT_BASEMASK;\r
+ bitmask = 1 << (pin & PORT_BITMASK);\r
+ if (base == PORT_A_BASE)\r
+ {\r
+ curValue = DDRA & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRA = curValue;\r
+ }\r
+ else if (base == PORT_B_BASE)\r
+ {\r
+ curValue = DDRB & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRB = curValue;\r
+ }\r
+ else if (base == PORT_E_BASE)\r
+ {\r
+ curValue = DDRE & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRE = curValue;\r
+ }\r
+ else if (base == PORT_K_BASE)\r
+ {\r
+ curValue = DDRK & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRK = curValue;\r
+ }\r
+ else if (base == PORT_H_BASE)\r
+ {\r
+ curValue = DDRH & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRH = curValue;\r
+ }\r
+ else if (base == PORT_J_BASE)\r
+ {\r
+ curValue = DDRJ & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRJ = curValue;\r
+ }\r
+ else if (base == PORT_M_BASE)\r
+ {\r
+ curValue = DDRM & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRM = curValue;\r
+ }\r
+ else if (base == PORT_P_BASE)\r
+ {\r
+ curValue = DDRP & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRP = curValue;\r
+ }\r
+ else if (base == PORT_S_BASE)\r
+ {\r
+ curValue = DDRS & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRS = curValue;\r
+ }\r
+ else if (base == PORT_T_BASE)\r
+ {\r
+ curValue = DDRT & ~(bitmask);\r
+ if (direction == PORT_PIN_OUT)\r
+ curValue = curValue | bitmask;\r
+ DDRT = curValue;\r
+ }\r
+ else\r
+ {\r
+ Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_DIRECTION_ID, PORT_E_PARAM_PIN );\r
+ }\r
+\r
+ return;\r
+}\r
+#endif\r
+\r
+/** @req PORT066 */\r
+/** @req PORT142 */\r
+/** @req PORT060 */\r
+/** @req PORT061 */\r
+void Port_RefreshPortDirection(void)\r
+{\r
+ uint8_t curValue;\r
+ VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);\r
+\r
+#if ( PORTA_CONFIGURABLE == STD_ON )\r
+ curValue = DDRA & ~(_configPtr->portAMask);\r
+ curValue |= (_configPtr->portADirection & _configPtr->portAMask);\r
+ DDRA = curValue;\r
+#endif\r
+\r
+#if ( PORTB_CONFIGURABLE == STD_ON )\r
+ curValue = DDRB & ~(_configPtr->portBMask);\r
+ curValue |= (_configPtr->portBDirection & _configPtr->portBMask);\r
+ DDRB = curValue;\r
+#endif\r
+\r
+#if ( PORTE_CONFIGURABLE == STD_ON )\r
+ curValue = DDRE & ~(_configPtr->portEMask);\r
+ curValue |= (_configPtr->portEDirection & _configPtr->portEMask);\r
+ DDRE = curValue;\r
+#endif\r
+\r
+#if ( PORTK_CONFIGURABLE == STD_ON )\r
+ curValue = DDRK & ~(_configPtr->portKMask);\r
+ curValue |= (_configPtr->portKDirection & _configPtr->portKMask);\r
+ DDRK = curValue;\r
+#endif\r
+\r
+#if ( PORTH_CONFIGURABLE == STD_ON )\r
+ curValue = DDRH & ~(_configPtr->portHMask);\r
+ curValue |= (_configPtr->portHDirection & _configPtr->portHMask);\r
+ DDRH = curValue;\r
+#endif\r
+\r
+#if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ curValue = DDRJ & ~(_configPtr->portJMask);\r
+ curValue |= (_configPtr->portJDirection & _configPtr->portJMask);\r
+ DDRJ = curValue;\r
+#endif\r
+\r
+#if ( PORTM_CONFIGURABLE == STD_ON )\r
+ curValue = DDRM & ~(_configPtr->portMMask);\r
+ curValue |= (_configPtr->portMDirection & _configPtr->portMMask);\r
+ DDRM = curValue;\r
+#endif\r
+\r
+#if ( PORTP_CONFIGURABLE == STD_ON )\r
+ curValue = DDRP & ~(_configPtr->portPMask);\r
+ curValue |= (_configPtr->portPDirection & _configPtr->portPMask);\r
+ DDRP =\r
+#endif\r
+\r
+#if ( PORTS_CONFIGURABLE == STD_ON )\r
+ curValue = DDRS & ~(_configPtr->portSMask);\r
+ curValue |= (_configPtr->portSDirection & _configPtr->portSMask);\r
+ DDRS = curValue;\r
+#endif\r
+\r
+#if ( PORTT_CONFIGURABLE == STD_ON )\r
+ curValue = DDRT & ~(_configPtr->portTMask);\r
+ curValue |= (_configPtr->portTDirection & _configPtr->portTMask);\r
+ DDRT = curValue;\r
+#endif\r
+\r
+ return;\r
+}\r
+\r
+/** req PORT143 */\r
+/** req PORT102 */\r
+/** req PORT103 */\r
+#if (PORT_VERSION_INFO_API == STD_ON)\r
+void Port_GetVersionInfo(Std_VersionInfoType* versionInfo)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_GET_VERSION_INFO_ID);\r
+ memcpy(versionInfo, &_Port_VersionInfo, sizeof(Std_VersionInfoType));\r
+ return;\r
+}\r
+#endif\r
+\r
+/** req PORT145 */\r
+/** req PORT125 */\r
+/** req PORT128 */\r
+#if (PORT_SET_PIN_MODE_API == STD_ON)\r
+void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
+\r
+ // Mode of pins not changeable on this CPU\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+ Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_MODE_ID, PORT_E_MODE_UNCHANGEABLE );\r
+#endif\r
+\r
+ return;\r
+}\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Pwm.c\r
+ *\r
+ * TODO Only supports 8 8-bit channels. Could also be 4 16-bit.\r
+ * Author: jonte\r
+ */\r
+\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
+#include "Pwm.h"\r
+#include "Det.h"\r
+#include "Os.h"\r
+#include "Mcu.h"\r
+#include "regs.h"\r
+#include "arc.h"\r
+\r
+#if PWM_DEV_ERROR_DETECT==STD_ON\r
+ #define PWM_VALIDATE(_exp, _errid) \\r
+ if (!(_exp)) { \\r
+ Pwm_ReportError(_errid); \\r
+ return; \\r
+ }\r
+ #define Pwm_VALIDATE_CHANNEL(_ch) PWM_VALIDATE(_ch <= 7, PWM_E_PARAM_CHANNEL)\r
+ #define Pwm_VALIDATE_INITIALIZED() PWM_VALIDATE(Pwm_ModuleState == PWM_STATE_INITIALIZED, PWM_E_UNINIT)\r
+ #define Pwm_VALIDATE_UNINITIALIZED() PWM_VALIDATE(Pwm_ModuleState != PWM_STATE_INITIALIZED, PWM_E_ALREADY_INITIALIZED)\r
+#else\r
+ #define PWM_VALIDATE(_exp, _errid)\r
+ #define Pwm_VALIDATE_CHANNEL(ch)\r
+ #define Pwm_VALIDATE_INITIALIZED()\r
+ #define Pwm_VALIDATE_UNINITIALIZED()\r
+#endif\r
+\r
+typedef enum {\r
+ PWM_STATE_UNINITIALIZED,\r
+ PWM_STATE_INITIALIZED\r
+} Pwm_ModuleStateType;\r
+\r
+static void SetRegChannelBit(volatile uint8 *reg, uint8 channel, uint8 value)\r
+{\r
+ if(value==0)\r
+ {\r
+ *reg &= ~(1<<channel);\r
+ }\r
+ else\r
+ {\r
+ *reg |= (1<<channel);\r
+ }\r
+}\r
+\r
+static Pwm_ModuleStateType Pwm_ModuleState = PWM_STATE_UNINITIALIZED;\r
+\r
+// Run-time variables\r
+typedef struct {\r
+ Pwm_ChannelClassType Class;\r
+ Pwm_OutputStateType IdleState;\r
+} Pwm_ChannelStructType;\r
+\r
+// We use Pwm_ChannelType as index here\r
+static Pwm_ChannelStructType ChannelRuntimeStruct[8];\r
+\r
+void Pwm_Init(const Pwm_ConfigType* ConfigPtr) {\r
+ Pwm_ChannelType channel_iterator;\r
+\r
+ Pwm_VALIDATE_UNINITIALIZED();\r
+ #if PWM_DEV_ERROR_DETECT==STD_ON\r
+ /*\r
+ * PWM046: If development error detection is enabled for the Pwm module,\r
+ * the function Pwm_Init shall raise development error PWM_E_PARAM_CONFIG\r
+ * if ConfigPtr is a null pointer.\r
+ *\r
+ * PWM120: For pre-compile and link-time configuration variants, a NULL\r
+ * pointer shall be passed to the initialization routine. In this case the\r
+ * check for this NULL pointer has to be omitted.\r
+ */\r
+ #if PWM_STATICALLY_CONFIGURED==OFF\r
+ if (ConfigPtr == NULL) {\r
+ Pwm_ReportError(PWM_E_PARAM_CONFIG);\r
+ return;\r
+ }\r
+ #endif\r
+ #endif\r
+\r
+ Pwm_ModuleState = PWM_STATE_INITIALIZED;\r
+\r
+ PWMCTL = 0; // We only support 8 8bit channels\r
+ if(PWM_FREEZE_ENABLE == STD_ON){\r
+ PWMCTL |= 0x04;\r
+ }else{\r
+ PWMCTL &= ~0x04;\r
+ }\r
+\r
+ PWMPRCLK = ConfigPtr->busPrescalerA | (ConfigPtr->busPrescalerB << 4);\r
+\r
+ PWMSCLA = ConfigPtr->prescalerA;\r
+ PWMSCLB = ConfigPtr->prescalerB;\r
+\r
+ for (channel_iterator = 0; channel_iterator < PWM_NUMBER_OF_CHANNELS; channel_iterator++) {\r
+ const Pwm_ChannelConfigurationType *chCfgPtr = &ConfigPtr->channels[channel_iterator];\r
+ Pwm_ChannelType channel = ConfigPtr->channels[channel_iterator].channel;\r
+\r
+ ChannelRuntimeStruct[channel].Class = ConfigPtr->channels[channel_iterator].class;\r
+ ChannelRuntimeStruct[channel].IdleState = ConfigPtr->channels[channel_iterator].idleState;\r
+\r
+ // Set up the registers in hw\r
+ SetRegChannelBit(&PWMCAE, channel, chCfgPtr->centerAlign);\r
+ SetRegChannelBit(&PWMCLK, channel, chCfgPtr->scaledClockEnable);\r
+ SetRegChannelBit(&PWMPOL, channel, chCfgPtr->polarity);\r
+\r
+ volatile uint8 *pDuty = &PWMDTY0+channel;\r
+ *pDuty = chCfgPtr->duty;\r
+ volatile uint8 *pPer = &PWMPER0+channel;\r
+ *pPer = chCfgPtr->period;\r
+\r
+ SetRegChannelBit(&PWME, channel, 1); // Enable Channel\r
+ }\r
+}\r
+\r
+#if PWM_DEINIT_API==STD_ON\r
+\r
+void Pwm_DeInit() {\r
+\r
+ Pwm_VALIDATE_INITIALIZED();\r
+\r
+ PWME = 0;\r
+\r
+ Pwm_ModuleState = PWM_STATE_UNINITIALIZED;\r
+}\r
+#endif\r
+\r
+/*\r
+ * PWM083: The function Pwm_SetPeriodAndDuty shall be pre compile time\r
+ * changeable ON/OFF by the configuration parameter PwmSetPeriodAndDuty.\r
+ */\r
+#if PWM_SET_PERIOD_AND_DUTY==STD_ON\r
+void Pwm_SetPeriodAndDuty(Pwm_ChannelType Channel, Pwm_PeriodType Period,\r
+ Pwm_DutyCycleType DutyCycle)\r
+{\r
+ Pwm_VALIDATE_INITIALIZED();\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+ PWM_VALIDATE(ChannelRuntimeStruct[Channel].Class == PWM_VARIABLE_PERIOD, PWM_E_PERIOD_UNCHANGEABLE);\r
+\r
+ volatile uint8 *pDuty = &PWMDTY0+Channel;\r
+ *pDuty = (uint8)((uint32)((uint32)DutyCycle*(uint32)Period)>>15);\r
+ volatile uint8 *pPer = &PWMPER0+Channel;\r
+ *pPer = Period;\r
+\r
+ if(PWM_DUTYCYCLE_UPDATED_ENDPERIOD != STD_ON){\r
+ //Reset Counter to update directly\r
+ volatile uint8 *pCtr = &PWMCNT0+Channel;\r
+ *pCtr = 0;\r
+ }\r
+}\r
+#endif\r
+\r
+\r
+/**\r
+ * PWM013: The function Pwm_SetDutyCycle shall set the duty cycle of the PWM\r
+ * channel.\r
+ *\r
+ * @param Channel PWM channel to use. 0 <= Channel < PWM_NUMBER_OF_CHANNELS <= 7\r
+ * @param DutyCycle 0 <= DutyCycle <= 0x8000\r
+ */\r
+void Pwm_SetDutyCycle(Pwm_ChannelType Channel, Pwm_DutyCycleType DutyCycle) {\r
+ Pwm_VALIDATE_INITIALIZED();\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+\r
+ volatile uint8 *pDuty = &PWMDTY0+Channel;\r
+\r
+ /*\r
+ * PWM017: The function Pwm_SetDutyCycle shall update the duty cycle at\r
+ * the end of the period if supported by the implementation and configured\r
+ * with PwmDutycycleUpdatedEndperiod.\r
+ *\r
+ * PWM014: The function Pwm_SetDutyCycle shall set the output state according\r
+ * to the configured polarity parameter [which is already set from\r
+ * Pwm_InitChannel], when the duty parameter is 0% [=0] or 100% [=0x8000].\r
+ */\r
+ if (DutyCycle == Pwm_100_Procent || DutyCycle == Pwm_0_Procent) {\r
+ *pDuty = 0;\r
+ } else {\r
+ volatile uint8 *pPer = &PWMPER0+Channel;\r
+ *pDuty = (uint8)((uint32)((uint32)DutyCycle*(uint32)*pPer)>>15);\r
+ }\r
+\r
+ if(PWM_DUTYCYCLE_UPDATED_ENDPERIOD != STD_ON){\r
+ //Reset Counter to update directly\r
+ volatile uint8 *pCtr = &PWMCNT0+Channel;\r
+ *pCtr = 0;\r
+ }\r
+}\r
+\r
+void Pwm_SetOutputToIdle(Pwm_ChannelType Channel) {\r
+ Pwm_VALIDATE_CHANNEL(Channel);\r
+ Pwm_VALIDATE_INITIALIZED();\r
+\r
+ volatile uint8 *pDuty = &PWMDTY0+Channel;\r
+ if(ChannelRuntimeStruct[Channel].IdleState == PWM_HIGH)\r
+ {\r
+ // Output shall be high\r
+ if((PWMPOL & (1 << Channel)) == (1 << Channel)){\r
+ *pDuty = 100;//Polarity high at beginning and goes low when duty is reached\r
+ }else{\r
+ *pDuty = 0;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ // Output shall be low\r
+ if((PWMPOL & (1 << Channel)) == (1 << Channel)){\r
+ *pDuty = 0;//Polarity high at beginning and goes low when duty is reached\r
+ }else{\r
+ *pDuty = 100;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * PWM085: The function Pwm_GetOutputState shall be pre compile configurable\r
+ * ON/OFF by the configuration parameter PwmGetOutputState\r
+ */\r
+#if PWM_GET_OUTPUT_STATE==STD_ON\r
+/*\r
+ * PWM022: The function Pwm_GetOutputState shall read the internal state\r
+ * of the PWM output signal and return it.\r
+ */\r
+Pwm_OutputStateType Pwm_GetOutputState(Pwm_ChannelType Channel)\r
+{\r
+ // We need to return something, even in presence of errors\r
+ if (Channel >= 8) {\r
+ Pwm_ReportError(PWM_E_PARAM_CHANNEL);\r
+\r
+ /*\r
+ * Accordingly to PWM025, we should return PWM_LOW on failure.\r
+ */\r
+ return PWM_LOW;\r
+\r
+ } else if (Pwm_ModuleState != PWM_STATE_INITIALIZED) {\r
+ Pwm_ReportError(PWM_E_UNINIT);\r
+ /*\r
+ * Accordingly to PWM025, we should return PWM_LOW on failure.\r
+ */\r
+ return PWM_LOW;\r
+ }\r
+\r
+ // TODO Is there an easy way to read from the port\r
+ return PWM_LOW;\r
+}\r
+#endif\r
+\r
--- /dev/null
+#ifndef _REGS_HCS12D_H_\r
+#define _REGS_HCS12D_H_\r
+\r
+#define IO_BASE 0\r
+\r
+#define ienable() __asm("cli");\r
+#define idisable() __asm("orcc #0x10")\r
+#define xenable() __asm("andcc #0xbf")\r
+#define xdisable()__asm("orcc #0x40")\r
+\r
+/**\r
+ * constant offsets to use where a C expression doesn't work\r
+ * You may use it with GEL\r
+ */\r
+#define M6811_PORTA 0x00\r
+#define M6811_PORTB 0x01\r
+#define M6811_PTT 0x240\r
+#define M6811_PTM 0x250\r
+#define M6811_PTP 0x258\r
+#define M6811_PTH 0x260\r
+\r
+#define PORTIO_8 *(volatile unsigned char *)\r
+#define PORTIO_16 *(volatile unsigned short int *)\r
+\r
+\r
+/* \r
+ * Core HC12 Registers\r
+ */\r
+#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
+#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
+#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
+#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
+#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
+#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
+#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
+#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
+#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
+#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
+#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
+#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
+#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
+#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
+#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
+#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
+#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
+#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
+#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
+#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
+#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
+#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
+#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
+#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
+\r
+// Bitflags - PEAR\r
+#define NOACCE 0x80\r
+#define PIPOE 0x20\r
+#define NECLK 0x10\r
+#define LSTRE 0x08\r
+#define RDWE 0x04\r
+\r
+// INTCR bitflags\r
+#define IRQE 0x80\r
+#define IRQEN 0x40\r
+#define DLY 0x20\r
+\r
+// BKP Module\r
+#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
+#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
+#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
+#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
+#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
+#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
+\r
+// MEBI Module \r
+#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
+#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
+#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
+\r
+// CRG Module \r
+#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
+#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
+#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
+#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
+#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
+#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
+#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
+#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
+#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
+#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
+#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
+#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
+\r
+// CRG bitflags\r
+#define RTIF 0x80\r
+#define RTIE 0x80\r
+#define LOCK 0x08\r
+#define AUTO 0x20\r
+#define PLLSEL 0x80\r
+\r
+// COPCTL bitflags\r
+#define WCOP 0x80\r
+#define RSBCK 0x40\r
+\r
+// ECT Module\r
+#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
+#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
+#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
+#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
+#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
+#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
+#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
+#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
+#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
+#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
+#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
+#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
+#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
+#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
+#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
+#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
+#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
+#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
+#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
+#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
+#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
+#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
+#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
+#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
+#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
+#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
+#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
+#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
+#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
+#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
+#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
+#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
+#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
+#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
+#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
+#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
+#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
+#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
+#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
+#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
+#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
+#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
+#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
+#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
+#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
+#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
+#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
+\r
+#define TEN 0x80\r
+#define TSFRZ 0x20\r
+#define TOI 0x80\r
+#define MCZI 0x80\r
+#define MODMC 0x40\r
+#define MCEN 0x4\r
+#define MCPR1 0x2\r
+#define MCPR0 0x1\r
+\r
+#define MCPRE_VAL_1 0\r
+#define MCPRE_VAL_4 MCPR0\r
+#define MCPRE_VAL_8 MCPR1\r
+#define MCPRE_VAL_16 MCPR0 | MCPR1\r
+\r
+// ATD0 Module \r
+#define ATD0_BASE (IO_BASE + 0x80)\r
+#define ATD0CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D0 control register 0 */\r
+#define ATD0CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D0 control register 1 */\r
+#define ATD0CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D0 control register 2 */\r
+#define ATD0CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D0 control register 3 */\r
+#define ATD0CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D0 control register 4 */\r
+#define ATD0CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D0 control register 5 */\r
+#define ATD0STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D0 status register 0 */\r
+#define ATD0STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D0 status register 1 */\r
+#define ATD0TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D0 test register 0 */\r
+#define ATD0TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D0 test register 1 */\r
+#define ATD0DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D0 interrupt enable */\r
+#define PORTAD0 PORTIO_8(IO_BASE + 0x8f) /* port AD0 data input register */\r
+#define ATD0DR0 PORTIO_16(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR0H PORTIO_8(IO_BASE + 0x90) /* A/D0 result 0 */\r
+#define ATD0DR1 PORTIO_16(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR1H PORTIO_8(IO_BASE + 0x92) /* A/D0 result 1 */\r
+#define ATD0DR2 PORTIO_16(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR2H PORTIO_8(IO_BASE + 0x94) /* A/D0 result 2 */\r
+#define ATD0DR3 PORTIO_16(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR3H PORTIO_8(IO_BASE + 0x96) /* A/D0 result 3 */\r
+#define ATD0DR4 PORTIO_16(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR4H PORTIO_8(IO_BASE + 0x98) /* A/D0 result 4 */\r
+#define ATD0DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D0 result 5 */\r
+#define ATD0DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D0 result 6 */\r
+#define ATD0DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+#define ATD0DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D0 result 7 */\r
+\r
+// ATDnCTL5 bitflags\r
+#define DJM 0x80\r
+#define DSGN 0x40\r
+#define SCAN 0x20\r
+#define MULT 0x10\r
+\r
+// ATDnSTAT0 bitflags\r
+#define SCF 0x80\r
+#define ETORF 0x20\r
+#define FIFOR 0x10\r
+\r
+// PWM Module \r
+#define PWME PORTIO_8(IO_BASE + 0xa0) /* PWM Enable */\r
+#define PWMPOL PORTIO_8(IO_BASE + 0xa1) /* PWM Clock Polarity */\r
+#define PWMCLK PORTIO_8(IO_BASE + 0xa2) /* PWM Clocks */\r
+#define PWMPRCLK PORTIO_8(IO_BASE + 0xa3) /* PWM prescale clock select */\r
+#define PWMCAE PORTIO_8(IO_BASE + 0xa4) /* PWM center align enable */\r
+#define PWMCTL PORTIO_8(IO_BASE + 0xa5) /* PWM Control Register */\r
+#define PWMTST PORTIO_8(IO_BASE + 0xa6) /* PWM Test Register */\r
+#define PWMPRSC PORTIO_8(IO_BASE + 0xa7) /* PWM Test Register */\r
+#define PWMSCLA PORTIO_8(IO_BASE + 0xa8) /* PWM scale A */\r
+#define PWMSCLB PORTIO_8(IO_BASE + 0xa9) /* PWM scale B */\r
+#define PWMSCNTA PORTIO_8(IO_BASE + 0xaa) /* PWM Test Register A */\r
+#define PWMSCNTB PORTIO_8(IO_BASE + 0xab) /* PWM Test Register B */\r
+#define PWMCNT0 PORTIO_8(IO_BASE + 0xac) /* PWM Channel Counter 0 */\r
+#define PWMCNT1 PORTIO_8(IO_BASE + 0xad) /* PWM Channel Counter 1 */\r
+#define PWMCNT2 PORTIO_8(IO_BASE + 0xae) /* PWM Channel Counter 2 */\r
+#define PWMCNT3 PORTIO_8(IO_BASE + 0xaf) /* PWM Channel Counter 3 */\r
+#define PWMCNT4 PORTIO_8(IO_BASE + 0xb0) /* PWM Channel Counter 4 */\r
+#define PWMCNT5 PORTIO_8(IO_BASE + 0xb1) /* PWM Channel Counter 5 */\r
+#define PWMCNT6 PORTIO_8(IO_BASE + 0xb2) /* PWM Channel Counter 6 */\r
+#define PWMCNT7 PORTIO_8(IO_BASE + 0xb3) /* PWM Channel Counter 7 */\r
+#define PWMPER0 PORTIO_8(IO_BASE + 0xb4) /* PWM Channel Period 0 */\r
+#define PWMPER1 PORTIO_8(IO_BASE + 0xb5) /* PWM Channel Period 1 */\r
+#define PWMPER2 PORTIO_8(IO_BASE + 0xb6) /* PWM Channel Period 2 */\r
+#define PWMPER3 PORTIO_8(IO_BASE + 0xb7) /* PWM Channel Period 3 */\r
+#define PWMPER4 PORTIO_8(IO_BASE + 0xb8) /* PWM Channel Period 4 */\r
+#define PWMPER5 PORTIO_8(IO_BASE + 0xb9) /* PWM Channel Period 5 */\r
+#define PWMPER6 PORTIO_8(IO_BASE + 0xba) /* PWM Channel Period 6 */\r
+#define PWMPER7 PORTIO_8(IO_BASE + 0xbb) /* PWM Channel Period 7 */\r
+#define PWMDTY0 PORTIO_8(IO_BASE + 0xbc) /* PWM Channel Duty 0 */\r
+#define PWMDTY1 PORTIO_8(IO_BASE + 0xbd) /* PWM Channel Duty 1 */\r
+#define PWMDTY2 PORTIO_8(IO_BASE + 0xbe) /* PWM Channel Duty 2 */\r
+#define PWMDTY3 PORTIO_8(IO_BASE + 0xbf) /* PWM Channel Duty 3 */\r
+#define PWMDTY4 PORTIO_8(IO_BASE + 0xc0) /* PWM Channel Duty 4 */\r
+#define PWMDTY5 PORTIO_8(IO_BASE + 0xc1) /* PWM Channel Duty 5 */\r
+#define PWMDTY6 PORTIO_8(IO_BASE + 0xc2) /* PWM Channel Duty 6 */\r
+#define PWMDTY7 PORTIO_8(IO_BASE + 0xc3) /* PWM Channel Duty 7 */\r
+#define PWMSDN PORTIO_8(IO_BASE + 0xc4) /* PWM shutdown register */\r
+\r
+#define PWMCNT01_16BIT PORTIO_16(IO_BASE + 0xac) /* pwm channel 0,1 counter, 16bit */\r
+#define PWMCNT23_16BIT PORTIO_16(IO_BASE + 0xae) /* pwm channel 2,3 counter, 16bit */\r
+#define PWMCNT45_16BIT PORTIO_16(IO_BASE + 0xb0) /* pwm channel 4,5 counter, 16bit */\r
+#define PWMCNT67_16BIT PORTIO_16(IO_BASE + 0xb2) /* pwm channel 6,7 counter, 16bit */\r
+#define PWMPER01_16BIT PORTIO_16(IO_BASE + 0xb4) /* pwm channel 0,1 period, 16bit */\r
+#define PWMPER23_16BIT PORTIO_16(IO_BASE + 0xb6) /* pwm channel 2,3 period, 16bit */\r
+#define PWMPER45_16BIT PORTIO_16(IO_BASE + 0xb8) /* pwm channel 4,5 period, 16bit */\r
+#define PWMPER67_16BIT PORTIO_16(IO_BASE + 0xba) /* pwm channel 6,7 period, 16bit */\r
+#define PWMDTY01_16BIT PORTIO_16(IO_BASE + 0xbc) /* pwm channel 0,1 duty cycle, 16bit */\r
+#define PWMDTY23_16BIT PORTIO_16(IO_BASE + 0xbe) /* pwm channel 2,3 duty cycle, 16bit */\r
+#define PWMDTY45_16BIT PORTIO_16(IO_BASE + 0xc0) /* pwm channel 4,5 duty cycle, 16bit */\r
+#define PWMDTY67_16BIT PORTIO_16(IO_BASE + 0xc2) /* pwm channel 6,7 duty cycle, 16bit */\r
+\r
+\r
+\r
+// SCI register offsets\r
+#define _SCIBD 0x0 /* SCI baud rate high */\r
+#define _SCIBDH 0x0 /* SCI baud rate high */\r
+#define _SCIBDL 0x1 /* SCI baud rate low */\r
+#define _SCICR1 0x2 /* SCI control register 1 */\r
+#define _SCICR2 0x3 /* SCI control register 2 */\r
+#define _SCISR1 0x4 /* SCI status register 1 */\r
+#define _SCISR2 0x5 /* SCI status register 2 */\r
+#define _SCIDRH 0x6 /* SCI data register high */\r
+#define _SCIDRL 0x7 /* SCI data register low */\r
+\r
+// SCI0 Module\r
+#define SCI0_BASE (IO_BASE + 0xc8)\r
+#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
+#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
+#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
+#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
+#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
+#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
+#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
+\r
+// SCI1 Module \r
+#define SCI1_BASE (IO_BASE + 0xd0)\r
+#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
+#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
+#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
+#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
+#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
+#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
+#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
+#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
+#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
+\r
+// SCInSR1\r
+#define TDRE 0x80\r
+#define RDRF 0x20\r
+#define IDLE 0x10\r
+\r
+// SPI register offsets\r
+#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
+#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
+#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
+#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
+#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
+\r
+// SPI0 Module \r
+#define SPI0_BASE (IO_BASE + 0xd8)\r
+#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
+#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
+#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
+#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
+#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
+\r
+// SPInCR1\r
+#define SPIE 0x80\r
+#define SPE 0x40\r
+#define SPTIE 0x20\r
+#define MSTR 0x10\r
+#define CPOL 0x08\r
+#define CPHA 0x04\r
+#define SSOE 0x02\r
+#define LSBFE 0x01\r
+\r
+// SPInSR\r
+#define SPIF 0x80\r
+#define SPTEF 0x20\r
+#define MODF 0x10\r
+\r
+// I2C Module \r
+#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
+#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
+#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
+#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
+#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
+\r
+// IBSR\r
+#define TCF 0x80\r
+#define IAAS 0x40\r
+#define IBB 0x20\r
+#define IBAL 0x10\r
+#define SRW 0x04\r
+#define IBIF 0x02\r
+#define RXAK 0x01\r
+\r
+// BDLC Module\r
+#define DLCBCR1 PORTIO_8(IO_BASE + 0xe8) /* BDLC control register 1 */\r
+#define DLCBSVR PORTIO_8(IO_BASE + 0xe9) /* BDLC state vector register */\r
+#define DLCBCR2 PORTIO_8(IO_BASE + 0xea) /* BDLC control register 2 */\r
+#define DLCBDR PORTIO_8(IO_BASE + 0xeb) /* BDLC data register */\r
+#define DLCBARD PORTIO_8(IO_BASE + 0xec) /* BDLC analog round trip delay */\r
+#define DLCBRSR PORTIO_8(IO_BASE + 0xed) /* BDLC rate select register */\r
+#define DLCSCR PORTIO_8(IO_BASE + 0xee) /* BDLC control register */\r
+#define DLCBSTAT PORTIO_8(IO_BASE + 0xef) /* BDLC status register */\r
+\r
+// SPI1 Module\r
+#define SPI1_BASE (IO_BASE + 0xf0)\r
+#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
+#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
+#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
+#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
+#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
+\r
+// SPI2 Module\r
+#define SPI2_BASE (IO_BASE + 0xf8)\r
+#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
+#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
+#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
+#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
+#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
+\r
+// FLC Module\r
+#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
+#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
+#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
+#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
+#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
+#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
+\r
+// EEPROM Module\r
+#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
+#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
+#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
+#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
+#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
+\r
+// ATD1 Module \r
+#define ATD1_BASE (IO_BASE + 0x120)\r
+#define ATD1CTL0 PORTIO_8(IO_BASE + 0x120) /* A/D1 control register 0 */\r
+#define ATD1CTL1 PORTIO_8(IO_BASE + 0x121) /* A/D1 control register 1 */\r
+#define ATD1CTL2 PORTIO_8(IO_BASE + 0x122) /* A/D1 control register 2 */\r
+#define ATD1CTL3 PORTIO_8(IO_BASE + 0x123) /* A/D1 control register 3 */\r
+#define ATD1CTL4 PORTIO_8(IO_BASE + 0x124) /* A/D1 control register 4 */\r
+#define ATD1CTL5 PORTIO_8(IO_BASE + 0x125) /* A/D1 control register 5 */\r
+#define ATD1STAT0 PORTIO_8(IO_BASE + 0x126) /* A/D1 status register 0 */\r
+#define ATD1STAT1 PORTIO_8(IO_BASE + 0x127) /* A/D1 status register 1 */\r
+#define ATD1TEST0 PORTIO_8(IO_BASE + 0x128) /* A/D1 test register 0 */\r
+#define ATD1TEST1 PORTIO_8(IO_BASE + 0x129) /* A/D1 test register 1 */\r
+#define ATD1DIEN PORTIO_8(IO_BASE + 0x12d) /* A/D1 interrupt enable */\r
+#define PORTAD1 PORTIO_8(IO_BASE + 0x12f) /* port AD1 data input register */\r
+#define ATD1DR0 PORTIO_16(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR0H PORTIO_8(IO_BASE + 0x130) /* A/D1 result 0 */\r
+#define ATD1DR1 PORTIO_16(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR1H PORTIO_8(IO_BASE + 0x132) /* A/D1 result 1 */\r
+#define ATD1DR2 PORTIO_16(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR2H PORTIO_8(IO_BASE + 0x134) /* A/D1 result 2 */\r
+#define ATD1DR3 PORTIO_16(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR3H PORTIO_8(IO_BASE + 0x136) /* A/D1 result 3 */\r
+#define ATD1DR4 PORTIO_16(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR4H PORTIO_8(IO_BASE + 0x138) /* A/D1 result 4 */\r
+#define ATD1DR5 PORTIO_16(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR5H PORTIO_8(IO_BASE + 0x13a) /* A/D1 result 5 */\r
+#define ATD1DR6 PORTIO_16(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR6H PORTIO_8(IO_BASE + 0x13c) /* A/D1 result 6 */\r
+#define ATD1DR7 PORTIO_16(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+#define ATD1DR7H PORTIO_8(IO_BASE + 0x13e) /* A/D1 result 7 */\r
+\r
+// CAN0 Module \r
+#define CAN0_BASE (IO_BASE + 0x140)\r
+#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
+#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
+#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
+#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
+#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
+#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
+#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
+#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
+#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
+#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
+#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
+#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
+#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
+#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
+#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
+#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
+#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
+#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
+#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
+#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
+#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
+#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
+#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
+#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
+#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
+#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
+#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
+#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
+#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
+#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
+#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
+#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
+\r
+// CAN1 Module \r
+#define CAN1_BASE (IO_BASE + 0x180)\r
+#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
+#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
+#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
+#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
+#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
+#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
+#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
+#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
+#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
+#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
+#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
+#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
+#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
+#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
+#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
+#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
+#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
+#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
+#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
+#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
+#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
+#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
+#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
+#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
+#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
+#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
+#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
+#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
+#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
+#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
+#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
+#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
+\r
+// CAN2 Module \r
+#define CAN2_BASE (IO_BASE + 0x1c0)\r
+#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
+#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
+#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
+#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
+#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
+#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
+#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
+#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
+#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
+#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
+#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
+#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
+#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
+#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
+#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
+#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
+#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
+#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
+#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
+#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
+#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
+#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
+#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
+#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
+#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
+#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
+#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
+#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
+#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
+#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
+#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
+#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
+\r
+// CAN3 Module \r
+#define CAN3_BASE (IO_BASE + 0x200)\r
+#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
+#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
+#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
+#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
+#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
+#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
+#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
+#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
+#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
+#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
+#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
+#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
+#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
+#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
+#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
+#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
+#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
+#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
+#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
+#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
+#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
+#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
+#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
+#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
+#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
+#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
+#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
+#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
+#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
+#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
+#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
+#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
+\r
+\r
+// Port T register offsets\r
+#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
+#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
+#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
+#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
+#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
+#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
+\r
+// Port S\r
+#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
+#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
+#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
+#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
+#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
+#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
+#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
+\r
+// Port M\r
+#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
+#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
+#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
+#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
+#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
+#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
+#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
+\r
+#define MODDR PORTIO_8(IO_BASE + 0x257) /* Module routing register */\r
+\r
+// Port P\r
+#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
+#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
+#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
+#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
+#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
+#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
+#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
+#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
+\r
+// Port H\r
+#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
+#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
+#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
+#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
+#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
+#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
+#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
+#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
+\r
+// Port J\r
+#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
+#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
+#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
+#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
+#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
+#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
+#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
+#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
+\r
+\r
+\r
+// CAN4 Module \r
+#define CAN4_BASE (IO_BASE + 0x280)\r
+#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
+#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
+#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
+#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
+#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
+#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
+#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
+#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
+#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
+#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
+#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
+#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
+#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
+#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
+#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
+#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
+#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
+#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
+#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
+#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
+#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
+#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
+#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
+#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
+#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
+#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
+#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
+#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
+#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
+#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
+#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
+#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
+\r
+\r
+\r
+# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
+# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
+# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
+# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
+# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
+# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+\r
+#endif /* ifndef _REGS_HCS12D_H_ */\r
--- /dev/null
+#ifndef _REGS_HCS12XD_H_\r
+#define _REGS_HCS12XD_H_\r
+\r
+#define IO_BASE 0\r
+\r
+#define ienable() __asm("cli");\r
+#define idisable() __asm("orcc #0x10")\r
+#define xenable() __asm("andcc #0xbf")\r
+#define xdisable()__asm("orcc #0x40")\r
+\r
+/**\r
+ * constant offsets to use where a C expression doesn't work\r
+ * You may use it with GEL\r
+ */\r
+#define M6811_PORTA 0x00\r
+#define M6811_PORTB 0x01\r
+#define M6811_PTT 0x240\r
+#define M6811_PTM 0x250\r
+#define M6811_PTP 0x258\r
+#define M6811_PTH 0x260\r
+\r
+#define PORTIO_8 *(volatile unsigned char *)\r
+#define PORTIO_16 *(volatile unsigned short int *)\r
+\r
+\r
+/* \r
+ * Core HC12 Registers\r
+ */\r
+#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
+#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
+#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
+#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
+#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
+#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
+#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
+#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
+#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
+#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
+#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
+#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
+#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
+#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
+#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
+#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
+#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
+#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
+#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
+#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
+#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
+#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
+#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
+#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
+\r
+// Bitflags - PEAR\r
+#define NOACCE 0x80\r
+#define PIPOE 0x20\r
+#define NECLK 0x10\r
+#define LSTRE 0x08\r
+#define RDWE 0x04\r
+\r
+// INTCR bitflags\r
+#define IRQE 0x80\r
+#define IRQEN 0x40\r
+#define DLY 0x20\r
+\r
+// BKP Module\r
+#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
+#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
+#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
+#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
+#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
+#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
+\r
+// MEBI Module \r
+#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
+#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
+#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
+\r
+// CRG Module \r
+#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
+#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
+#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
+#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
+#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
+#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
+#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
+#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
+#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
+#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
+#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
+#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
+\r
+// CRG bitflags\r
+#define RTIF 0x80\r
+#define RTIE 0x80\r
+#define LOCK 0x08\r
+#define AUTO 0x20\r
+#define PLLSEL 0x80\r
+\r
+// COPCTL bitflags\r
+#define WCOP 0x80\r
+#define RSBCK 0x40\r
+\r
+// ECT Module\r
+#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
+#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
+#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
+#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
+#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
+#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
+#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
+#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
+#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
+#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
+#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
+#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
+#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
+#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
+#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
+#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
+#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
+#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
+#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
+#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
+#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
+#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
+#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
+#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
+#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
+#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
+#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
+#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
+#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
+#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
+#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
+#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
+#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
+#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
+#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
+#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
+#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
+#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
+#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
+#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
+#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
+#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
+#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
+#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
+#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
+#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
+#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
+\r
+#define TEN 0x80\r
+#define TSFRZ 0x20\r
+#define TOI 0x80\r
+#define MCZI 0x80\r
+#define MODMC 0x40\r
+#define MCEN 0x4\r
+#define MCPR1 0x2\r
+#define MCPR0 0x1\r
+\r
+#define MCPRE_VAL_1 0\r
+#define MCPRE_VAL_4 MCPR0\r
+#define MCPRE_VAL_8 MCPR1\r
+#define MCPRE_VAL_16 MCPR0 | MCPR1\r
+\r
+// ATD1 Module\r
+#define ATD1_BASE (IO_BASE + 0x80)\r
+#define ATD1CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D1 control register 0 */\r
+#define ATD1CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D1 control register 1 */\r
+#define ATD1CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D1 control register 2 */\r
+#define ATD1CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D1 control register 3 */\r
+#define ATD1CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D1 control register 4 */\r
+#define ATD1CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D1 control register 5 */\r
+#define ATD1STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D1 status register 0 */\r
+#define ATD1STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D1 status register 1 */\r
+#define ATD1TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D1 test register 0 */\r
+#define ATD1TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D1 test register 1 */\r
+#define ATD1DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D1 interrupt enable */\r
+#define PORTAD1 PORTIO_8(IO_BASE + 0x8f) /* port AD1 data input register */\r
+#define ATD1DR0 PORTIO_16(IO_BASE + 0x90) /* A/D1 result 0 */\r
+#define ATD1DR0H PORTIO_8(IO_BASE + 0x90) /* A/D1 result 0 */\r
+#define ATD1DR1 PORTIO_16(IO_BASE + 0x92) /* A/D1 result 1 */\r
+#define ATD1DR1H PORTIO_8(IO_BASE + 0x92) /* A/D1 result 1 */\r
+#define ATD1DR2 PORTIO_16(IO_BASE + 0x94) /* A/D1 result 2 */\r
+#define ATD1DR2H PORTIO_8(IO_BASE + 0x94) /* A/D1 result 2 */\r
+#define ATD1DR3 PORTIO_16(IO_BASE + 0x96) /* A/D1 result 3 */\r
+#define ATD1DR3H PORTIO_8(IO_BASE + 0x96) /* A/D1 result 3 */\r
+#define ATD1DR4 PORTIO_16(IO_BASE + 0x98) /* A/D1 result 4 */\r
+#define ATD1DR4H PORTIO_8(IO_BASE + 0x98) /* A/D1 result 4 */\r
+#define ATD1DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D1 result 5 */\r
+#define ATD1DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D1 result 5 */\r
+#define ATD1DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D1 result 6 */\r
+#define ATD1DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D1 result 6 */\r
+#define ATD1DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D1 result 7 */\r
+#define ATD1DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D1 result 7 */\r
+\r
+// ATDnCTL5 bitflags\r
+#define DJM 0x80\r
+#define DSGN 0x40\r
+#define SCAN 0x20\r
+#define MULT 0x10\r
+\r
+// ATDnSTAT0 bitflags\r
+#define SCF 0x80\r
+#define ETORF 0x20\r
+#define FIFOR 0x10\r
+\r
+// PWM Module \r
+#define PWME PORTIO_8(IO_BASE + 0x300) /* PWM Enable */\r
+#define PWMPOL PORTIO_8(IO_BASE + 0x301) /* PWM Clock Polarity */\r
+#define PWMCLK PORTIO_8(IO_BASE + 0x302) /* PWM Clocks */\r
+#define PWMPRCLK PORTIO_8(IO_BASE + 0x303) /* PWM prescale clock select */\r
+#define PWMCAE PORTIO_8(IO_BASE + 0x304) /* PWM center align enable */\r
+#define PWMCTL PORTIO_8(IO_BASE + 0x305) /* PWM Control Register */\r
+#define PWMTST PORTIO_8(IO_BASE + 0x306) /* PWM Test Register */\r
+#define PWMPRSC PORTIO_8(IO_BASE + 0x307) /* PWM Test Register */\r
+#define PWMSCLA PORTIO_8(IO_BASE + 0x308) /* PWM scale A */\r
+#define PWMSCLB PORTIO_8(IO_BASE + 0x309) /* PWM scale B */\r
+#define PWMSCNTA PORTIO_8(IO_BASE + 0x30a) /* PWM Test Register A */\r
+#define PWMSCNTB PORTIO_8(IO_BASE + 0x30b) /* PWM Test Register B */\r
+#define PWMCNT0 PORTIO_8(IO_BASE + 0x30c) /* PWM Channel Counter 0 */\r
+#define PWMCNT1 PORTIO_8(IO_BASE + 0x30d) /* PWM Channel Counter 1 */\r
+#define PWMCNT2 PORTIO_8(IO_BASE + 0x30e) /* PWM Channel Counter 2 */\r
+#define PWMCNT3 PORTIO_8(IO_BASE + 0x30f) /* PWM Channel Counter 3 */\r
+#define PWMCNT4 PORTIO_8(IO_BASE + 0x310) /* PWM Channel Counter 4 */\r
+#define PWMCNT5 PORTIO_8(IO_BASE + 0x311) /* PWM Channel Counter 5 */\r
+#define PWMCNT6 PORTIO_8(IO_BASE + 0x312) /* PWM Channel Counter 6 */\r
+#define PWMCNT7 PORTIO_8(IO_BASE + 0x313) /* PWM Channel Counter 7 */\r
+#define PWMPER0 PORTIO_8(IO_BASE + 0x314) /* PWM Channel Period 0 */\r
+#define PWMPER1 PORTIO_8(IO_BASE + 0x315) /* PWM Channel Period 1 */\r
+#define PWMPER2 PORTIO_8(IO_BASE + 0x316) /* PWM Channel Period 2 */\r
+#define PWMPER3 PORTIO_8(IO_BASE + 0x317) /* PWM Channel Period 3 */\r
+#define PWMPER4 PORTIO_8(IO_BASE + 0x318) /* PWM Channel Period 4 */\r
+#define PWMPER5 PORTIO_8(IO_BASE + 0x319) /* PWM Channel Period 5 */\r
+#define PWMPER6 PORTIO_8(IO_BASE + 0x31a) /* PWM Channel Period 6 */\r
+#define PWMPER7 PORTIO_8(IO_BASE + 0x31b) /* PWM Channel Period 7 */\r
+#define PWMDTY0 PORTIO_8(IO_BASE + 0x31c) /* PWM Channel Duty 0 */\r
+#define PWMDTY1 PORTIO_8(IO_BASE + 0x31d) /* PWM Channel Duty 1 */\r
+#define PWMDTY2 PORTIO_8(IO_BASE + 0x31e) /* PWM Channel Duty 2 */\r
+#define PWMDTY3 PORTIO_8(IO_BASE + 0x31f) /* PWM Channel Duty 3 */\r
+#define PWMDTY4 PORTIO_8(IO_BASE + 0x320) /* PWM Channel Duty 4 */\r
+#define PWMDTY5 PORTIO_8(IO_BASE + 0x321) /* PWM Channel Duty 5 */\r
+#define PWMDTY6 PORTIO_8(IO_BASE + 0x322) /* PWM Channel Duty 6 */\r
+#define PWMDTY7 PORTIO_8(IO_BASE + 0x323) /* PWM Channel Duty 7 */\r
+#define PWMSDN PORTIO_8(IO_BASE + 0x324) /* PWM shutdown register */\r
+\r
+#define PWMCNT01_16BIT PORTIO_16(IO_BASE + 0x30c) /* pwm channel 0,1 counter, 16bit */\r
+#define PWMCNT23_16BIT PORTIO_16(IO_BASE + 0x30e) /* pwm channel 2,3 counter, 16bit */\r
+#define PWMCNT45_16BIT PORTIO_16(IO_BASE + 0x310) /* pwm channel 4,5 counter, 16bit */\r
+#define PWMCNT67_16BIT PORTIO_16(IO_BASE + 0x312) /* pwm channel 6,7 counter, 16bit */\r
+#define PWMPER01_16BIT PORTIO_16(IO_BASE + 0x314) /* pwm channel 0,1 period, 16bit */\r
+#define PWMPER23_16BIT PORTIO_16(IO_BASE + 0x316) /* pwm channel 2,3 period, 16bit */\r
+#define PWMPER45_16BIT PORTIO_16(IO_BASE + 0x318) /* pwm channel 4,5 period, 16bit */\r
+#define PWMPER67_16BIT PORTIO_16(IO_BASE + 0x31a) /* pwm channel 6,7 period, 16bit */\r
+#define PWMDTY01_16BIT PORTIO_16(IO_BASE + 0x31c) /* pwm channel 0,1 duty cycle, 16bit */\r
+#define PWMDTY23_16BIT PORTIO_16(IO_BASE + 0x31e) /* pwm channel 2,3 duty cycle, 16bit */\r
+#define PWMDTY45_16BIT PORTIO_16(IO_BASE + 0x320) /* pwm channel 4,5 duty cycle, 16bit */\r
+#define PWMDTY67_16BIT PORTIO_16(IO_BASE + 0x322) /* pwm channel 6,7 duty cycle, 16bit */\r
+\r
+\r
+\r
+// SCI register offsets\r
+#define _SCIBD 0x0 /* SCI baud rate high */\r
+#define _SCIBDH 0x0 /* SCI baud rate high */\r
+#define _SCIBDL 0x1 /* SCI baud rate low */\r
+#define _SCICR1 0x2 /* SCI control register 1 */\r
+#define _SCICR2 0x3 /* SCI control register 2 */\r
+#define _SCISR1 0x4 /* SCI status register 1 */\r
+#define _SCISR2 0x5 /* SCI status register 2 */\r
+#define _SCIDRH 0x6 /* SCI data register high */\r
+#define _SCIDRL 0x7 /* SCI data register low */\r
+\r
+// SCI0 Module\r
+#define SCI0_BASE (IO_BASE + 0xc8)\r
+#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
+#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
+#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
+#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
+#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
+#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
+#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
+#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
+\r
+// SCI1 Module \r
+#define SCI1_BASE (IO_BASE + 0xd0)\r
+#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
+#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
+#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
+#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
+#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
+#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
+#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
+#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
+#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
+\r
+// SCInSR1\r
+#define TDRE 0x80\r
+#define RDRF 0x20\r
+#define IDLE 0x10\r
+\r
+// SPI register offsets\r
+#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
+#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
+#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
+#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
+#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
+\r
+// SPI0 Module \r
+#define SPI0_BASE (IO_BASE + 0xd8)\r
+#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
+#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
+#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
+#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
+#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
+\r
+// SPInCR1\r
+#define SPIE 0x80\r
+#define SPE 0x40\r
+#define SPTIE 0x20\r
+#define MSTR 0x10\r
+#define CPOL 0x08\r
+#define CPHA 0x04\r
+#define SSOE 0x02\r
+#define LSBFE 0x01\r
+\r
+// SPInSR\r
+#define SPIF 0x80\r
+#define SPTEF 0x20\r
+#define MODF 0x10\r
+\r
+// I2C Module \r
+#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
+#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
+#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
+#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
+#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
+\r
+// IBSR\r
+#define TCF 0x80\r
+#define IAAS 0x40\r
+#define IBB 0x20\r
+#define IBAL 0x10\r
+#define SRW 0x04\r
+#define IBIF 0x02\r
+#define RXAK 0x01\r
+\r
+// SPI1 Module\r
+#define SPI1_BASE (IO_BASE + 0xf0)\r
+#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
+#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
+#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
+#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
+#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
+\r
+// SPI2 Module\r
+#define SPI2_BASE (IO_BASE + 0xf8)\r
+#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
+#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
+#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
+#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
+#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
+\r
+// FLC Module\r
+#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
+#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
+#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
+#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
+#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
+#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
+\r
+// EEPROM Module\r
+#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
+#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
+#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
+#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
+#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
+\r
+// ATD0 Module\r
+#define ATD0_BASE (IO_BASE + 0x2C0)\r
+#define ATD0CTL0 PORTIO_8(IO_BASE + 0x2C0) /* A/D0 control register 0 */\r
+#define ATD0CTL1 PORTIO_8(IO_BASE + 0x2C1) /* A/D0 control register 1 */\r
+#define ATD0CTL2 PORTIO_8(IO_BASE + 0x2C2) /* A/D0 control register 2 */\r
+#define ATD0CTL3 PORTIO_8(IO_BASE + 0x2C3) /* A/D0 control register 3 */\r
+#define ATD0CTL4 PORTIO_8(IO_BASE + 0x2C4) /* A/D0 control register 4 */\r
+#define ATD0CTL5 PORTIO_8(IO_BASE + 0x2C5) /* A/D0 control register 5 */\r
+#define ATD0STAT0 PORTIO_8(IO_BASE + 0x2C6) /* A/D0 status register 0 */\r
+#define ATD0STAT1 PORTIO_8(IO_BASE + 0x2C7) /* A/D0 status register 1 */\r
+#define ATD0TEST0 PORTIO_8(IO_BASE + 0x2C8) /* A/D0 test register 0 */\r
+#define ATD0TEST1 PORTIO_8(IO_BASE + 0x2C9) /* A/D0 test register 1 */\r
+#define ATD0DIEN PORTIO_8(IO_BASE + 0x2Cd) /* A/D0 interrupt enable */\r
+#define PORTAD0 PORTIO_8(IO_BASE + 0x2Cf) /* port AD0 data input register */\r
+#define ATD0DR0 PORTIO_16(IO_BASE + 0x2d0) /* A/D0 result 0 */\r
+#define ATD0DR0H PORTIO_8(IO_BASE + 0x2d0) /* A/D0 result 0 */\r
+#define ATD0DR1 PORTIO_16(IO_BASE + 0x2d2) /* A/D0 result 1 */\r
+#define ATD0DR1H PORTIO_8(IO_BASE + 0x2d2) /* A/D0 result 1 */\r
+#define ATD0DR2 PORTIO_16(IO_BASE + 0x2d4) /* A/D0 result 2 */\r
+#define ATD0DR2H PORTIO_8(IO_BASE + 0x2d4) /* A/D0 result 2 */\r
+#define ATD0DR3 PORTIO_16(IO_BASE + 0x2d6) /* A/D0 result 3 */\r
+#define ATD0DR3H PORTIO_8(IO_BASE + 0x2d6) /* A/D0 result 3 */\r
+#define ATD0DR4 PORTIO_16(IO_BASE + 0x2d8) /* A/D0 result 4 */\r
+#define ATD0DR4H PORTIO_8(IO_BASE + 0x2d8) /* A/D0 result 4 */\r
+#define ATD0DR5 PORTIO_16(IO_BASE + 0x2da) /* A/D0 result 5 */\r
+#define ATD0DR5H PORTIO_8(IO_BASE + 0x2da) /* A/D0 result 5 */\r
+#define ATD0DR6 PORTIO_16(IO_BASE + 0x2dc) /* A/D0 result 6 */\r
+#define ATD0DR6H PORTIO_8(IO_BASE + 0x2dc) /* A/D0 result 6 */\r
+#define ATD0DR7 PORTIO_16(IO_BASE + 0x2de) /* A/D0 result 7 */\r
+#define ATD0DR7H PORTIO_8(IO_BASE + 0x2de) /* A/D0 result 7 */\r
+\r
+// CAN0 Module \r
+#define CAN0_BASE (IO_BASE + 0x140)\r
+#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
+#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
+#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
+#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
+#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
+#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
+#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
+#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
+#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
+#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
+#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
+#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
+#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
+#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
+#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
+#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
+#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
+#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
+#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
+#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
+#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
+#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
+#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
+#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
+#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
+#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
+#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
+#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
+#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
+#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
+#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
+#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
+\r
+// CAN1 Module \r
+#define CAN1_BASE (IO_BASE + 0x180)\r
+#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
+#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
+#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
+#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
+#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
+#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
+#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
+#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
+#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
+#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
+#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
+#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
+#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
+#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
+#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
+#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
+#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
+#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
+#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
+#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
+#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
+#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
+#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
+#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
+#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
+#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
+#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
+#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
+#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
+#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
+#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
+#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
+\r
+// CAN2 Module \r
+#define CAN2_BASE (IO_BASE + 0x1c0)\r
+#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
+#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
+#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
+#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
+#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
+#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
+#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
+#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
+#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
+#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
+#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
+#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
+#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
+#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
+#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
+#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
+#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
+#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
+#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
+#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
+#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
+#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
+#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
+#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
+#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
+#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
+#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
+#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
+#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
+#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
+#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
+#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
+\r
+// CAN3 Module \r
+#define CAN3_BASE (IO_BASE + 0x200)\r
+#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
+#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
+#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
+#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
+#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
+#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
+#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
+#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
+#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
+#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
+#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
+#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
+#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
+#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
+#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
+#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
+#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
+#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
+#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
+#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
+#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
+#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
+#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
+#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
+#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
+#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
+#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
+#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
+#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
+#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
+#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
+#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
+\r
+\r
+// Port T register offsets\r
+#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
+#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
+#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
+#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
+#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
+#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
+\r
+// Port S\r
+#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
+#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
+#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
+#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
+#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
+#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
+#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
+\r
+// Port M\r
+#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
+#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
+#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
+#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
+#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
+#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
+#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
+\r
+#define MODDR PORTIO_8(IO_BASE + 0x257) /* Module routing register */\r
+\r
+// Port P\r
+#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
+#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
+#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
+#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
+#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
+#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
+#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
+#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
+\r
+// Port H\r
+#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
+#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
+#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
+#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
+#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
+#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
+#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
+#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
+\r
+// Port J\r
+#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
+#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
+#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
+#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
+#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
+#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
+#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
+#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
+\r
+\r
+\r
+// CAN4 Module \r
+#define CAN4_BASE (IO_BASE + 0x280)\r
+#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
+#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
+#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
+#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
+#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
+#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
+#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
+#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
+#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
+#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
+#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
+#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
+#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
+#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
+#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
+#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
+#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
+#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
+#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
+#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
+#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
+#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
+#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
+#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
+#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
+#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
+#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
+#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
+#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
+#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
+#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
+#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
+\r
+\r
+\r
+# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
+# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
+# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
+# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
+# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
+# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+\r
+#endif /* ifndef _REGS_HCS12XD_H_ */\r
}\r
\r
void *Os_ArchGetStackPtr( void ) {\r
+ void* val;\r
\r
-// return (void *)__get_MSP();\r
+ asm("sts _.tmp");\r
+ asm volatile("movw _.tmp, %0":"=m" (val));\r
+\r
+ return val;\r
}\r
\r
unsigned int Os_ArchGetScSize( void ) {\r
\r
\r
void Os_ArchSetupContext( OsPcbType *pcb ) {\r
- // TODO: Add lots of things here, see ppc55xx\r
-// uint16_t *context = (uint16_t *)pcb->stack.curr;\r
-// context[C_CONTEXT_OFF/4] = SC_PATTERN;\r
-\r
- /* Set LR to start function */\r
-// if( pcb->proc_type == PROC_EXTENDED ) {\r
-// context[VGPR_LR_OFF/4] = (uint16_t)Os_TaskStartExtended;\r
-// } else if( pcb->proc_type == PROC_BASIC ) {\r
-// context[VGPR_LR_OFF/4] = (uint16_t)Os_TaskStartBasic;\r
-// }\r
-// Os_StackSetEndmark(pcb);\r
-// Os_ArchSetupContext_asm(pcb->stack.curr,NULL);\r
+ // Nothing to be done here\r
}\r
\r
/**\r
*/\r
\r
void Os_ArchSetTaskEntry(OsPcbType *pcbPtr ) {\r
- uint16_t *context_words = (uint16_t *)pcbPtr->stack.curr;\r
uint8_t *context_bytes = (uint8_t *)pcbPtr->stack.curr;\r
+ uint16_t temp;\r
\r
/* Set Return to start function */\r
\r
context_bytes[8] = OS_KERNEL_CODE_PPAGE;\r
\r
if( pcbPtr->proc_type == PROC_EXTENDED ) {\r
- context_words[8] = (uint16_t)Os_TaskStartExtended;\r
+ temp = (uint16_t)Os_TaskStartExtended;\r
+ context_bytes[HIGH_BYTE_RETURN_ADRESS] = temp >> 8;\r
+ context_bytes[LOW_BYTE_RETURN_ADRESS] = temp & 0xFF;\r
} else if( pcbPtr->proc_type == PROC_BASIC ) {\r
- context_words[8] = (uint16_t)Os_TaskStartBasic;\r
+ temp = (uint16_t)Os_TaskStartBasic;\r
+ context_bytes[HIGH_BYTE_RETURN_ADRESS] = temp >> 8;\r
+ context_bytes[LOW_BYTE_RETURN_ADRESS] = temp & 0xFF;\r
}\r
}\r
\r
\r
void Os_ArchInit( void ) {\r
- // nothing to do here, yet :)\r
+ // Nothing to be done here\r
}\r
\r
#define _ASSEMBLER_\r
#include "kernel_offset.h"\r
+#include "context.h"\r
#include "asm_hc1x.sx"\r
#include "context.sx"\r
\r
#define SC_PATTERN 0xde\r
#define LC_PATTERN 0xad\r
\r
-#define CONTEXT_SIZE_W 9\r
-\r
+#if defined(CFG_HCS12D)\r
+#define Y_SP_OFFSET 6 // The offset from P to Y in the context\r
+#define CONTEXT_SIZE_W 9 // The context size in words\r
+#define HIGH_BYTE_RETURN_ADRESS 16 // The offset in the context that contains the high order byte of return address\r
+#define LOW_BYTE_RETURN_ADRESS 17 // The offset in the context that contains the low order byte of return address\r
+\r
+#elif defined(CFG_HCS12XD)\r
+#define Y_SP_OFFSET 7 // The offset from P to Y in the context\r
+#define CONTEXT_SIZE_W 10 // The context size in words ( Actual size 9+1/2)\r
+#define HIGH_BYTE_RETURN_ADRESS 17 // The offset in the context that contains the high order byte of return address\r
+#define LOW_BYTE_RETURN_ADRESS 18 // The offset in the context that contains the low order byte of return address\r
+#else\r
+#error "HC1X: Subarchitecture not defined."\r
+#endif\r
\r
#endif /* CONTEXT_H_ */\r
sty 1, -sp // save Y -> ctx(Y)\r
stx 2, -sp // save X -> ctx(X)\r
stab 2, -sp // save B -> ctx(B) (skipping ctx(A))\r
+#ifdef CFG_HCS12D\r
pshc // save CCR -> ctx(CCR)\r
+#endif\r
+#ifdef CFG_HCS12XD \r
+ .short 0x1839 // save CCR -> ctx(CCR)\r
+#endif \r
psha // save P -> ctx(P) *\r
movw _.tmp ,2,-sp // save tmp -> ctx(tmp)\r
movw _.xy, 2,-sp // save xy -> ctx(xy)\r
movw 2,sp+, _.z // load z <- ctx(z)\r
movw 2,sp+, _.xy // load xy <- ctx(xy)\r
movw 2,sp+, _.tmp // load tmp <- ctx(tmp)\r
- ldy 6,sp // load Y <- ctx(Y)\r
- movb 1,sp+, 6,sp // move ctx(P) -> callctx(P)\r
- pulc // load CCR <- ctx(CCR)\r
+ ldy Y_SP_OFFSET,sp // load Y <- ctx(Y)\r
+ movb 1,sp+, Y_SP_OFFSET,sp // move ctx(P) -> callctx(P)\r
+#ifdef CFG_HCS12D\r
+ pulc // save CCR -> ctx(CCR)\r
+#endif\r
+#ifdef CFG_HCS12XD\r
+ .short 0x1838 // load CCR <- ctx(CCR)\r
+#endif\r
puld // load D <- ctx(D)\r
pulx // load X <- ctx(X)\r
ins // skipping ctx(Yh)\r
movb 1,sp+, PPAGE // load P <- ctx(P)\r
.endm\r
\r
-\r
-
\ No newline at end of file
\r
}\r
\r
-void Irq_EOI( void ) {\r
-\r
-}\r
\r
// IRQ debug information\r
// Stores irq nr on erroneous interrupt\r
bad_irq_context_bank = (bank_and_ccr & 0xFF00) >> 8;\r
bad_irq_context_address = *(stack + 8);\r
\r
- for (;;);\r
+ for (;;)\r
+ asm("BGND"); // Jump to debugger\r
}\r
\r
void *Irq_Entry( uint8_t irq_nr, void *stack )\r
* @param vector\r
*/\r
void Irq_GenerateSoftInt( IrqType vector ) {\r
- (void)vector;\r
+ if (vector == IRQ_TYPE_SWI)\r
+ {\r
+ asm("swi");\r
+ }\r
+\r
+ if (vector == IRQ_TYPE_ILLEGAL)\r
+ {\r
+ asm(".short 0x1830"); // Trap instruction\r
+ }\r
}\r
\r
/**\r
#ifndef IRQ_TYPES_H\r
#define IRQ_TYPES_H\r
\r
+#define Irq_SOI()\r
+#define Irq_EOI()\r
+\r
#include "irq_defines.h"\r
\r
#define DECLARE_IRQ_PROTOTYPE(x) \\r
*/\r
\r
/** @req OS383 */\r
-uint32_t Os_SysTickGetTimeElapsed( void )\r
+uint32_t Os_SysTickGetValue( void )\r
{\r
#if 0\r
uint32_t timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
/* Default linker script, for normal executables */\r
/* Linker script for 68HC12 executable (PROM). */\r
-OUTPUT_FORMAT("elf32-m68hc12", "elf32-m68hc12",\r
- "elf32-m68hc12")\r
+OUTPUT_FORMAT("elf32-m68hc12", "elf32-m68hc12", "elf32-m68hc12")\r
OUTPUT_ARCH(m68hc12)\r
ENTRY(_start)\r
\r
\r
MEMORY\r
{\r
- page0 (rwx) : ORIGIN = 0x0, LENGTH = 256\r
-\r
- /* RAM */\r
- data (rwx) : ORIGIN = 0x2000, LENGTH = 8k\r
-\r
- eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k\r
- text (rx) : ORIGIN = 0x4000, LENGTH = 48k\r
- \r
- /* high fixed bank, reserve 0x100 vectors and security. */\r
- text_h (rx) : ORIGIN = 0xc000, LENGTH = 16k-0x100\r
- vectors (rx) : ORIGIN = 0xff80, LENGTH = 0x80\r
- \r
- /* Flash memory banks VMA:s */\r
- bank8 (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
- bank9 (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
- bank10 (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
- bank11 (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
- bank12 (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
- bank13 (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
- \r
- bank14 (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
- bank15 (rx) : ORIGIN = 0x10c000, LENGTH = 16k-0x100\r
- \r
- /* Flash memory banks LMA:s */\r
- /* iSystem winIDEA */\r
- bank8_lma (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
- bank9_lma (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
- bank10_lma (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
- bank11_lma (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
- bank12_lma (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
- bank13_lma (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
-\r
- bank14_lma (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
- bank15_lma (rx) : ORIGIN = 0x10c000, LENGTH = 16k-0x100\r
- vectors_lma (rx) : ORIGIN = 0x10ff80, LENGTH = 0x80\r
- \r
- /* Freescale Codewarrior Hiwave (s19, TBDML)\r
- bank8_lma (rx) : ORIGIN = 0x388000, LENGTH = 16k\r
- bank9_lma (rx) : ORIGIN = 0x398000, LENGTH = 16k\r
- bank10_lma (rx) : ORIGIN = 0x3a8000, LENGTH = 16k\r
- bank11_lma (rx) : ORIGIN = 0x3b8000, LENGTH = 16k\r
- bank12_lma (rx) : ORIGIN = 0x3c8000, LENGTH = 16k\r
- bank13_lma (rx) : ORIGIN = 0x3d8000, LENGTH = 16k\r
-\r
- bank14_lma (rx) : ORIGIN = 0x3e8000, LENGTH = 16k\r
- bank15_lma (rx) : ORIGIN = 0x3f8000, LENGTH = 16k-0x100\r
- vectors_lma (rx) : ORIGIN = 0x3fff80, LENGTH = 0x80\r
- */\r
+#include "memory.ldf"\r
}\r
\r
/* Setup the stack on the top of the data memory bank. */\r
\r
\r
/* PPAGE memory banks */\r
-\r
- .bank8 :\r
+ .bank_A :\r
{\r
- *(.bank8)\r
- *(.text.bank8*)\r
+ *(.bank_A)\r
+ *(.text.bank_A*)\r
\r
- /* BANK8 MODULES */\r
+ /* BANK_A MODULES */\r
Os_Cfg.o(.text)\r
EcuM.o(.text)\r
EcuM_Cfg.o(.text)\r
init.o(.text)\r
arch.o(.text)\r
task.o(.text)\r
- resource.o(.text)\r
alarm.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank8 AT>bank8_lma =0xff\r
+ } > bank_A AT>bank_A_lma =0xff\r
\r
- .bank9 :\r
+ .bank_B :\r
{\r
- *(.bank9)\r
- *(.text.bank9*)\r
+ *(.bank_B)\r
+ *(.text.bank_B*)\r
\r
- /* BANK9 MODULES */\r
+ /* BANK_B MODULES */\r
+ resource.o(.text)\r
sched_table.o(.text)\r
counter.o(.text)\r
sys_tick.o(.text)\r
newlib_port.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank9 AT>bank9_lma =0xff\r
+ } > bank_B AT>bank_B_lma =0xff\r
\r
\r
- .bank10 :\r
+ .bank_C :\r
{\r
- *(.bank10)\r
- *(.text.bank10*)\r
+ *(.bank_C)\r
+ *(.text.bank_C*)\r
\r
- /* BANK10 MODULES */ \r
+ /* BANK_C MODULES */\r
+ printf.o(.text) \r
*_memcpy.o(.text)\r
*_memset.o(.text)\r
*_abort.o(.text)\r
*_subdi3.o(.text)\r
*_addsub_sf.o(.text)\r
*udivmod.o(.text)\r
- *_negsi2.o(.text)\r
+ /* *_negsi2.o(.text) */\r
*_pack_sf.o(.text)\r
*_unpack_sf.o(.text)\r
*udivmodsi4.o(.text)\r
*_memcpy.o(.text)\r
\r
. = ALIGN(2);\r
- } > bank10 AT>bank10_lma =0xff\r
+ } > bank_C AT>bank_C_lma =0xff\r
\r
\r
- .bank11 :\r
+ .bank_D :\r
{\r
- *(.bank11)\r
+ *(.bank_D)\r
+ *(.text.bank_D*)\r
+\r
+ /* BANK_D MODULES */\r
+ Can*.o(.text)\r
+ Pdu*.o(.text)\r
+ Dio*.o(.text)\r
+\r
. = ALIGN(2);\r
- } > bank11 AT>bank11_lma =0xff\r
+ } > bank_D AT>bank_D_lma =0xff\r
\r
\r
- .bank12 :\r
+ .bank_E :\r
{\r
- *(.bank12)\r
+ *(.bank_E)\r
+ *(.text.bank_E*)\r
+\r
+ /* BANK_E MODULES */\r
+ Port*.o(.text)\r
+ Com*.o(.text)\r
+ test_*.o(.text)\r
+\r
. = ALIGN(2);\r
- } > bank12 AT>bank12_lma =0xff\r
+ } > bank_E AT>bank_E_lma =0xff\r
\r
\r
- .bank13 :\r
+ .bank_F :\r
{\r
- *(.bank13)\r
- . = ALIGN(2);\r
- } > bank13 AT>bank13_lma =0xff\r
+ *(.bank_F)\r
+ *(.text.bank_F*)\r
+\r
+ /* BANK_F MODULES */\r
+ Adc*.o(.text)\r
+ Dem*.o(.text)\r
+ IoHwAb*.o(.text)\r
+ . = ALIGN(2);\r
+ } > bank_F AT>bank_F_lma =0xff\r
\r
\r
/* Start of text section. */\r
.stext :\r
{\r
*(.stext)\r
- } > text AT>bank14_lma\r
+ } > text AT>bank_FIX1_lma\r
.init :\r
{\r
*(.init)\r
- } AT>bank14_lma =0\r
+ } AT>bank_FIX1_lma =0\r
.text :\r
{\r
/* Put startup code at beginning so that _start keeps same address. */\r
_etext = .;\r
PROVIDE (etext = .);\r
. = ALIGN(2);\r
- } > text AT>bank14_lma =0xa7a7a7a7\r
+ } > text AT>bank_FIX1_lma =0xa7a7a7a7\r
\r
.eh_frame :\r
{\r
KEEP (*(.eh_frame))\r
- } > text AT>bank14_lma\r
+ } > text AT>bank_FIX1_lma\r
\r
.gcc_except_table :\r
{\r
*(.gcc_except_table)\r
- } > text AT>bank14_lma\r
+ } > text AT>bank_FIX1_lma\r
\r
.rodata :\r
{\r
*(.rodata.*)\r
*(.gnu.linkonce.r*)\r
. = ALIGN(2);\r
- } > text_h AT>bank15_lma =0xffffffff\r
+ } > text_h AT>bank_FIX2_lma =0xffffffff\r
\r
.rodata1 :\r
{\r
*(.rodata1)\r
. = ALIGN(2);\r
- } > text_h AT>bank15_lma =0xffffffff\r
+ } > text_h AT>bank_FIX2_lma =0xffffffff\r
\r
/* Constructor and destructor tables are in ROM. */\r
/*\r
_edata = .;\r
PROVIDE (edata = .);\r
. = ALIGN(2);\r
- } > data AT>bank15_lma =0xffffffff\r
+ } > data AT>bank_FIX2_lma =0xffffffff\r
__data_section_size = SIZEOF(.data);\r
PROVIDE (__data_section_size = SIZEOF(.data));\r
__data_image_end = __data_image + __data_section_size;\r
*(.dem_eventmemory_pri)\r
} > data\r
\r
+ .noice_port 0x2000 :\r
+ {\r
+ *(.noice_port)\r
+ } > data\r
+ \r
/* SCz: this does not work yet... This is supposed to force the loading\r
of _map_data.o (from libgcc.a) when the .data section is not empty.\r
By doing so, this should bring the code that copies the .data section\r
*(.gnu.linkonce.b.*)\r
*(COMMON)\r
PROVIDE (_end = .);\r
- } > data AT>bank15_lma\r
+ } > data /* AT>bank_FIX2_lma */\r
__bss_size = SIZEOF(.bss);\r
PROVIDE (__bss_size = SIZEOF(.bss));\r
.eeprom :\r
.type _start,@function\r
\r
// Good information about the E500 is freescale doc: E500ABIUG.pdf\r
+ \r
+\r
+.global _redled\r
+_redled:\r
+ // mpc5567qrtech: light up led K2 \r
+ li r0, 0x0202\r
+ lis r3, 0xC3F9013A@h\r
+ ori r3, r3, 0xC3F90130@l\r
+ stw r0, 8(r3)\r
+ b _exit\r
+\r
_start:\r
// Set up the reserved registers in EABI: r1,r2 and r13\r
\r
// make space for initial backchain..\r
subi r1,r1,16\r
\r
+/* Store winIDEA terminal connected status */\r
+#if defined(USE_TTY_WINIDEA)\r
+ lis r3,g_TConn@h\r
+ ori r3,r3,g_TConn@l\r
+ lbz r4,0(r3)\r
+#endif\r
+\r
+ # Clear all SRAM\r
+init_RAM:\r
+ lis r11,0x4000 # base address of the SRAM, 64-bit word aligned\r
+ ori r11,r11,0 # not needed for this address but could be for others\r
+ li r12,640 # loop counter to get all of SRAM;\r
+ # 80k/4 bytes/32 GPRs = 640\r
+ mtctr r12\r
+\r
+init_ram_loop:\r
+ stmw r0,0(r11) # write all 32 GPRs to SRAM\r
+ addi r11,r11,128 # inc the ram ptr; 32 GPRs * 4 bytes = 128\r
+ bdnz init_ram_loop # loop for 80k of SRAM\r
+\r
+/* Restore winIDEA terminal connected status */\r
+#if defined(USE_TTY_WINIDEA)\r
+ stb r4,0(r3)\r
+#endif\r
+\r
// Copy initialized data from ROM to RAM\r
lis r3,__DATA_ROM@h\r
ori r3,r3,__DATA_ROM@l\r
cmplw r3,r4\r
bne+ 2b\r
3:\r
-\r
# Call main() with argc set to 1 and argv ignored\r
li r3,1\r
bl main\r
#if defined(USE_KERNEL)\r
#include "Os.h"\r
#include "irq.h"\r
+#include "arc.h"\r
#endif\r
\r
\r
#if defined(USE_KERNEL)\r
#include "Os.h"\r
#include "irq.h"\r
+#include "arc.h"\r
#endif\r
\r
\r
}\r
\r
if (canHwConfig->Can_Arc_Fifo) {\r
+ /*\r
+ * NOTE!!!\r
+ * Do not enable RxFIFO. See [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 14593].\r
+ */\r
+ \r
/* Note\r
* NOT tested at all\r
*/\r
canUnit->state = CANIF_CS_STARTED;\r
imask_t state = McuE_EnterCriticalSection();\r
if (canUnit->lock_cnt == 0) // REQ CAN196\r
+ {\r
Can_EnableControllerInterrupts(controller);\r
+ }\r
McuE_ExitCriticalSection(state);\r
break;\r
case CAN_T_WAKEUP: //CAN267\r
#include <string.h>\r
#include "mpc55xx.h"\r
\r
-#if ( DIO_VERSION_INFO_API == STD_ON )\r
-static Std_VersionInfoType _Dio_VersionInfo =\r
-{\r
- .vendorID = (uint16)1,\r
- .moduleID = (uint16)1,\r
- .instanceID = (uint8)1,\r
- .sw_major_version = (uint8)DIO_SW_MAJOR_VERSION,\r
- .sw_minor_version = (uint8)DIO_SW_MINOR_VERSION,\r
- .sw_patch_version = (uint8)DIO_SW_PATCH_VERSION,\r
- .ar_major_version = (uint8)DIO_AR_MAJOR_VERSION,\r
- .ar_minor_version = (uint8)DIO_AR_MINOR_VERSION,\r
- .ar_patch_version = (uint8)DIO_AR_PATCH_VERSION,\r
-};\r
-#endif\r
+#define CHANNEL_PTR (&DioChannelConfigData)\r
+#define CHANNEL_GRP_PTR (&DioConfigData)\r
+#define PORT_PTR (&DioPortConfigData)\r
+\r
\r
#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
static int Channel_Config_Contains(Dio_ChannelType channelId)\r
{\r
level = STD_LOW;\r
}\r
- cleanup: return (level);\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return (level);\r
}\r
\r
void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level)\r
VALIDATE_CHANNEL(channelId, DIO_WRITECHANNEL_ID);\r
// Write level to SIU.\r
SIU.GPDO [channelId].R = level;\r
- cleanup: return;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
}\r
\r
Dio_PortLevelType Dio_ReadPort(Dio_PortType portId)\r
vuint16_t *ptr = (vuint16_t *)&SIU.PGPDI0; // The GPDI 0-3 is organized in 32bit chunks but we want to step them in 16bit port-widths\r
#endif\r
level = ptr[portId]; // Read the bit pattern (16bits) to the port\r
- cleanup: return level;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
}\r
\r
void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level)\r
vuint16_t *ptr = (vuint16_t *)&SIU.PGPDO0; // The GPDO 0-3 is organized in 32bit chunks but we want to step them in 16bit port-widths\r
#endif\r
ptr[portId] = level; // Write the bit pattern (16bits) to the port\r
- cleanup: return;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
}\r
\r
Dio_PortLevelType Dio_ReadChannelGroup(\r
\r
// Shift down\r
level<<=channelGroupIdPtr->offset;\r
- cleanup: return level;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return level;\r
}\r
\r
void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr,\r
// Build the 32 bits Mask_Valule, and write to masked output register\r
ptr[channelGroupIdPtr->port] = (channelGroupIdPtr->mask << 16)&((level\r
<<channelGroupIdPtr->offset)|0xFFFF);\r
- cleanup: return;\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+ cleanup:\r
+#endif\r
+ return;\r
#else\r
return;\r
#endif\r
}\r
\r
-#if (DIO_VERSION_INFO_API == STD_ON)\r
-void Dio_GetVersionInfo(Std_VersionInfoType *versionInfo)\r
-{\r
- memcpy(versionInfo, &_Dio_VersionInfo, sizeof(Std_VersionInfoType));\r
-}\r
-#endif\r
-\r
}\r
}\r
\r
-struct tcd_t * Dma_GetTcd( Dma_ChannelType channel ) {\r
+volatile struct tcd_t * Dma_GetTcd( Dma_ChannelType channel ) {\r
return &EDMA.TCD[channel];\r
}\r
\r
void Dma_StartChannel (Dma_ChannelType channel);\r
void Dma_StopChannel (Dma_ChannelType channel);\r
Std_ReturnType Dma_ChannelDone (Dma_ChannelType channel);\r
-struct tcd_t * Dma_GetTcd( Dma_ChannelType channel );\r
+volatile struct tcd_t * Dma_GetTcd( Dma_ChannelType channel );\r
boolean Dma_CheckConfig( void );\r
\r
#endif /* DMA_H_ */\r
#if ( EEP_DEV_ERROR_DETECT == STD_ON ) // Report DEV errors\r
#define VALIDATE(_exp,_api,_err ) \\r
if( !(_exp) ) { \\r
- Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ Det_ReportError(MODULE_ID_EEP,0,_api,_err); \\r
return; \\r
}\r
\r
#define VALIDATE_W_RV(_exp,_api,_err,_rv ) \\r
if( !(_exp) ) { \\r
- Det_ReportError(MODULE_ID_GPT,0,_api,_err); \\r
+ Det_ReportError(MODULE_ID_EEP,0,_api,_err); \\r
return (_rv); \\r
}\r
\r
Eep_Arc_JobType mainState;\r
Spi_SequenceType currSeq;\r
uint32 chunkSize;\r
+ uint32 pageSize;
} Eep_JobInfoType;\r
\r
#define JOB_SET_STATE(_x,_y) job->state=(_x);job->mainState=(_y)\r
\r
} Eep_GlobalType;\r
\r
-#if 0\r
+#if 0 // Use SPI synchronous transmit
#define SPI_TRANSMIT_FUNC(_x) Spi_SyncTransmit(_x)\r
-#else\r
+#else // Use SPI asynchronous transmit
#define SPI_TRANSMIT_FUNC(_x,_y) Eep_AsyncTransmit(_x,_y)\r
\r
Std_ReturnType Eep_AsyncTransmit(Spi_SequenceType Sequence,Eep_JobInfoType *job) {\r
Eep_Global.status = MEMIF_IDLE;\r
Eep_Global.jobResultType = MEMIF_JOB_OK;\r
\r
+ Eep_SetMode( CFG_P()->EepDefaultMode );
+
}\r
\r
\r
job->chunkSize = Eep_Global.config->EepNormalWriteBlockSize;\r
}\r
\r
+ job->pageSize = Eep_Global.config->EepPageSize;
job->eepAddr = EepromAddress;\r
job->targetAddr = (uint8 *)DataBufferPtr;\r
job->left = Length;\r
job->chunkSize = Eep_Global.config->EepNormalReadBlockSize;\r
}\r
\r
+ job->pageSize = Eep_Global.config->EepPageSize; // Not relevant to compare/read operations, but set anyways.
job->eepAddr = EepromAddress;\r
job->targetAddr = TargetAddressPtr;\r
job->left = Length;\r
}\r
\r
\r
-void Eep_Cancel( void ){\r
- EEP_JOB_END_NOTIFICATION();\r
+void Eep_Cancel( void ) {
+ EEP_JOB_ERROR_NOTIFICATION();
\r
if (MEMIF_JOB_PENDING==Eep_Global.jobResultType) {\r
Eep_Global.jobResultType=MEMIF_JOB_CANCELLED;\r
static Spi_SeqResultType Eep_ProcessJob( Eep_JobInfoType *job ) {\r
Spi_SeqResultType rv;\r
_Bool done = 0;\r
+ uint32 chunkSize = 0;
+ uint32 sizeLeftInPage = 0;
\r
/* Check if previous sequence is OK */\r
rv = Spi_GetSequenceResult(job->currSeq);\r
/* Check status from erase cmd, read status from flash */\r
Spi_SetupEB( CFG_P()->EepDataChannel, NULL, &Eep_Global.ebReadStatus, 1);\r
Eep_Global.ebCmd = E2_RDSR;\r
- if( SPI_TRANSMIT_FUNC(CFG_P()->EepCmd2Sequence,job ) != E_OK ) {\r
- assert(0);\r
+ if( SPI_TRANSMIT_FUNC(CFG_P()->EepCmd2Sequence,job ) == E_OK )
+ {
+ SET_STATE(1,JOB_READ_STATUS_RESULT);
+ }
+ else
+ {
+ SET_STATE(1,JOB_READ_STATUS);
}\r
- SET_STATE(1,JOB_READ_STATUS_RESULT);\r
break;\r
\r
case JOB_READ_STATUS_RESULT:\r
DEBUG(DEBUG_LOW,"%s: READ_STATUS_RESULT\n",MODULE_NAME);\r
- if( Eep_Global.ebReadStatus&1 ) {\r
+ if( Eep_Global.ebReadStatus & 1 ) {\r
SET_STATE(0,JOB_READ_STATUS);\r
} else {\r
SET_STATE(0,JOB_MAIN);\r
break;\r
\r
case JOB_MAIN:\r
- if( job->left != 0 ) {\r
- if( job->left <= job->chunkSize ) {\r
- job->chunkSize = job->left;\r
+ if( job->left > 0 ) {
+ if( job->left <= job->chunkSize ) {
+ chunkSize = job->left;
+ } else {
+ chunkSize = job->chunkSize;
}\r
\r
Spi_ConvertToSpiAddr(Eep_Global.ebE2Addr,job->eepAddr);\r
\r
- switch(job->mainState) {\r
+ BOOL spiTransmitOK = FALSE;
\r
+ switch(job->mainState)
+ {
case EEP_ERASE:\r
/* NOT USED */\r
break;\r
case EEP_READ:\r
case EEP_COMPARE:\r
- DEBUG(DEBUG_LOW,"%s: READ s:%04x d:%04x l:%04x\n",MODULE_NAME,job->eepAddr, job->targetAddr, job->left);\r
+ DEBUG(DEBUG_LOW,"%s: READ s:%04x d:%04x l:%04x\n",MODULE_NAME,job->eepAddr, job->targetAddr, job->left);\r
Eep_Global.ebCmd = E2_READ;\r
- Spi_SetupEB( CFG_P()->EepDataChannel, NULL ,job->targetAddr,job->chunkSize);\r
- SPI_TRANSMIT_FUNC(CFG_P()->EepReadSequence,job );\r
+ Spi_SetupEB( CFG_P()->EepDataChannel, NULL ,(Spi_DataType*)job->targetAddr,chunkSize);
+ if (SPI_TRANSMIT_FUNC(CFG_P()->EepReadSequence,job) == E_OK) {
+ spiTransmitOK = TRUE;
+ }
break;\r
\r
case EEP_WRITE:\r
DEBUG(DEBUG_LOW,"%s: WRITE d:%04x s:%04x first data:%02x\n",MODULE_NAME,job->eepAddr,job->targetAddr,*job->targetAddr);\r
+
+ // Calculate how much space there is left in the current EEPROM page.
+ sizeLeftInPage = job->pageSize - (job->eepAddr % job->pageSize);
+
+ // Handle EEPROM page boundaries, i.e. make sure that we limit the chunk
+ // size so we don't write over the page boundary.
+ if (chunkSize > sizeLeftInPage) {\r
+ chunkSize = sizeLeftInPage;
+ } else {
+ // Do nothing since the size of the chunk to write is less than the
+ // available space left in the page.
+ }
+
Eep_Global.ebCmd = E2_WRITE;\r
Spi_ConvertToSpiAddr(Eep_Global.ebE2Addr,job->eepAddr);\r
- Spi_SetupEB( CFG_P()->EepDataChannel, job->targetAddr, NULL, job->chunkSize);\r
- SPI_TRANSMIT_FUNC(CFG_P()->EepWriteSequence,job );\r
+ Spi_SetupEB( CFG_P()->EepDataChannel, (const Spi_DataType*)job->targetAddr, NULL, chunkSize);
+ if (SPI_TRANSMIT_FUNC(CFG_P()->EepWriteSequence,job ) == E_OK) {
+ spiTransmitOK = TRUE;
+ }
break;\r
\r
default:\r
break;\r
}\r
\r
- job->eepAddr += job->chunkSize;\r
- job->targetAddr += job->chunkSize;\r
- job->left -= job->chunkSize;\r
- SET_STATE(1,JOB_READ_STATUS);\r
+ if (spiTransmitOK) {
+ job->eepAddr += chunkSize;
+ job->targetAddr += chunkSize;
+ job->left -= chunkSize;
+
+ SET_STATE(1,JOB_READ_STATUS);\r
+ } else {
+ SET_STATE(1,JOB_MAIN);
+ }
\r
} else {\r
/* We are done :) */\r
readJob.targetAddr = Eep_CompareBuffer;\r
} else {\r
// all other cases are bad\r
- firstTime = 1;\r
- Eep_Global.jobResultType = MEMIF_JOB_FAILED;\r
- Eep_Global.jobType = EEP_NONE;\r
- Eep_Global.status = MEMIF_IDLE;\r
+ firstTime = 1;\r
+ Eep_Global.jobResultType = MEMIF_JOB_FAILED;\r
+ Eep_Global.jobType = EEP_NONE;\r
+ Eep_Global.status = MEMIF_IDLE;\r
\r
- DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );\r
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_COMPARE_ID, EEP_E_COM_FAILURE ); // EEP056 (reporting to DET because DEM is missing)
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_COMPARE_ID, MEMIF_JOB_FAILED );
EEP_JOB_ERROR_NOTIFICATION();\r
}\r
}\r
Eep_Global.jobResultType = MEMIF_JOB_OK;\r
Eep_Global.jobType = EEP_NONE;\r
Eep_Global.status = MEMIF_IDLE;\r
- EEP_JOB_END_NOTIFICATION();\r
- } else if( jobResult == SPI_SEQ_PENDING ) {\r
- /* Busy, Do nothing */\r
- } else {\r
- // Error\r
- Eep_Global.jobResultType = MEMIF_JOB_FAILED;\r
- Eep_Global.jobType = EEP_NONE;\r
- Eep_Global.status = MEMIF_IDLE;\r
-\r
- switch(Eep_Global.jobType) {\r
- case EEP_ERASE:\r
- DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );\r
+ EEP_JOB_END_NOTIFICATION();\r
+ } else if( jobResult == SPI_SEQ_PENDING ) {\r
+ /* Busy, Do nothing */\r
+ } else {\r
+ // Error\r
+\r
+ Eep_EcoreJobType failedJobType = Eep_Global.jobType;
+
+ Eep_Global.jobResultType = MEMIF_JOB_FAILED;\r
+ Eep_Global.jobType = EEP_NONE;\r
+ Eep_Global.status = MEMIF_IDLE;\r
+\r
+ switch(failedJobType) {
+ case EEP_ERASE:\r
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_ERASE_ID, EEP_E_COM_FAILURE ); // EEP056 (reporting to DET because DEM is missing)
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_ERASE_ID, MEMIF_JOB_FAILED );
break;\r
- case EEP_READ:\r
- DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );\r
+ case EEP_READ:\r
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_READ_ID, EEP_E_COM_FAILURE ); // EEP056 (reporting to DET because DEM is missing)
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_READ_ID, MEMIF_JOB_FAILED );
break;\r
- case EEP_WRITE:\r
- DET_REPORTERROR(MODULE_ID_EEP,0, 0x9, MEMIF_JOB_FAILED );\r
+ case EEP_WRITE:\r
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_WRITE_ID, EEP_E_COM_FAILURE ); // EEP056 (reporting to DET because DEM is missing)
+ DET_REPORTERROR(MODULE_ID_EEP,0, EEP_WRITE_ID, MEMIF_JOB_FAILED );
break;\r
- default:\r
- assert(0);\r
+ default:\r
+ assert(0);\r
}\r
\r
EEP_JOB_ERROR_NOTIFICATION();\r
* High: 8x128K\r
*/\r
\r
-#define H7F_REG_BASE 0xFFFF8000\r
+#define H7F_REG_BASE (UINT32)&FLASH\r
#define MAIN_ARRAY_BASE 0x00000000\r
-#define SHADOW_ROW_BASE 0x00FF8000\r
+\r
+#ifdef CFG_MPC5516\r
+#define SHADOW_ROW_BASE 0x00FF8000\r
+#elif defined(CFG_MPC5567)\r
+#define SHADOW_ROW_BASE 0x00FFFC00\r
+#endif\r
+\r
#define SHADOW_ROW_SIZE 0x00008000\r
#define FLASH_PAGE_SIZE H7FB_PAGE_SIZE\r
\r
+#define FLASH_TOTAL_BLOCKS ( 20 )\r
+\r
#if 0\r
#define VFLAGS_ADDR_SECT (1<<0)\r
#define VFLAGS_ADDR_PAGE (1<<1)\r
return _rv; \\r
}\r
\r
+#define FLS_VALIDATE_READ_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\\r
+ int sectorIndex;\\r
+ int addrOk=0;\\r
+ const Fls_SectorType* sector;\\r
+ for (sectorIndex=0; sectorIndex<Fls_Global.config->FlsSectorListSize;sectorIndex++) {\\r
+ sector = &Fls_Global.config->FlsSectorList[sectorIndex];\\r
+ if((((uint32)_addr-sector->FlsSectorStartaddress) / sector->FlsSectorSize)<sector->FlsNumberOfSectors){\\r
+ /* Within the right adress space */\\r
+ addrOk=1;\\r
+ }\\r
+ }\\r
+ if (1!=addrOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_ADDRESS ); \\r
+ return _rv; \\r
+ }\r
+\r
#define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\\r
int i;\\r
int lengthOk=0;\\r
return _rv; \\r
}\r
\r
+#define FLS_VALIDATE_READ_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\\r
+ int i;\\r
+ int lengthOk=0;\\r
+ const Fls_SectorType* sectorPtr= &Fls_Global.config->FlsSectorList[0];\\r
+ for (i=0; i<Fls_Global.config->FlsSectorListSize;i++) {\\r
+ if ((sectorPtr->FlsSectorStartaddress + (sectorPtr->FlsNumberOfSectors * sectorPtr->FlsSectorSize))>=(uint32_t)(_addr+(_length))){\\r
+ lengthOk=1;\\r
+ }\\r
+ sectorPtr++;\\r
+ }\\r
+ if (!lengthOk){\\r
+ Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_LENGTH ); \\r
+ return _rv; \\r
+ }\r
+\r
#define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)\\r
int i;\\r
int lengthOk=0;\\r
}\r
\r
#define FLS_VALIDATE_PARAM_DATA_W_RV(_ptr,_api, _rv) \\r
- if( (_ptr)==((void *)0)) { \\r
+ if(( (uint32)(_ptr)%FLS_READ_PAGE_SIZE != 0 ) || ( (_ptr)==((void *)0))) { \
Det_ReportError(MODULE_ID_FLS,0,_api,FLS_E_PARAM_DATA); \\r
return _rv; \\r
}\r
#else\r
#define FLS_VALIDATE_PARAM_ADDRESS_SECTOR_W_RV(_addr, _api, _rv)\r
#define FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\r
+ #define FLS_VALIDATE_READ_PARAM_ADDRESS_PAGE_W_RV(_addr, _api, _rv)\r
#define FLS_VALIDATE_PARAM_LENGTH_SECTOR_W_RV(_addr, _length, _api, _rv)\r
#define FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\r
+ #define FLS_VALIDATE_READ_PARAM_LENGTH_PAGE_W_RV(_addr, _length, _api, _rv)\r
#define FLS_VALIDATE_STATUS_UNINIT_W_RV(_status, _api, _rv)\r
#define FLS_VALIDATE_STATUS_BUSY(_status, _api)\r
#define FLS_VALIDATE_STATUS_BUSY_W_RV(_status, _api, _rv)\r
MemIf_StatusType status;\r
MemIf_JobResultType jobResultType;\r
Fls_Arc_JobType jobType;\r
- MemIf_AddressType sourceAddr;\r
+ Fls_AddressType sourceAddr;\r
uint8 *targetAddr;\r
- MemIf_LengthType length;\r
+ Fls_LengthType length;\r
\r
Fls_ProgInfoType flashWriteInfo;\r
\r
MemIf_StatusType status;\r
MemIf_JobResultType jobResultType;\r
Fls_Arc_JobType jobType;\r
- MemIf_AddressType sourceAddr;\r
+ Fls_AddressType sourceAddr;\r
uint8 *targetAddr;\r
- MemIf_LengthType length;\r
+ Fls_LengthType length;\r
\r
Fls_ProgInfoType flashWriteInfo;\r
} Fls_GlobalType;\r
endBlock = address_to_block( addr + size - 1,&rem );\r
\r
// Check so our implementation holds..\r
- assert( endBlock<=32 );\r
+ assert( endBlock <= FLASH_TOTAL_BLOCKS );\r
\r
#define BLOCK_MASK 0x0003ffffUL\r
\r
\r
\r
// shift things in to make freescale driver happy\r
- eraseBlocks->lowEnabledBlocks = mask&0x3f; // ????\r
- eraseBlocks->midEnabledBlocks = (mask>>10)&3; // ????\r
- eraseBlocks->highEnabledBlocks = mask>>12;\r
+ eraseBlocks->lowEnabledBlocks = mask&0x3ff; // Bits 0..9 indicats low blocks
+ eraseBlocks->midEnabledBlocks = (mask>>10)&3; // Bits 10..11 indicats mid blocks
+ eraseBlocks->highEnabledBlocks = mask>>12; // Bits 12..19 indicats high blocks
\r
\r
return ;\r
}\r
\r
/* TargetAddress always from 0 to FLS_TOTAL_SIZE */\r
-Std_ReturnType Fls_Erase( MemIf_AddressType TargetAddress,\r
- MemIf_LengthType Length )\r
+Std_ReturnType Fls_Erase( Fls_AddressType TargetAddress,\r
+ Fls_LengthType Length )\r
{\r
- uint32 block;\r
- uint32 sBlock;\r
+ uint32 endBlock;\r
+ uint32 startBlock;\r
uint32 rem;\r
Fls_EraseBlockType eraseBlock;\r
Fls_EraseInfoType eraseInfo;\r
return E_NOT_OK;\r
\r
// TargetAddress\r
- sBlock = address_to_block(TargetAddress,&rem);\r
+ startBlock = address_to_block(TargetAddress,&rem);\r
\r
- if( (sBlock == (-1)) || (rem!=0) ) {\r
+ if( (startBlock == (-1)) || (rem!=0) ) {\r
DET_REPORTERROR(MODULE_ID_FLS,0,0x0,FLS_E_PARAM_ADDRESS );\r
return E_NOT_OK;\r
}\r
\r
- block = address_to_block(TargetAddress+Length,&rem);\r
+ endBlock = address_to_block(TargetAddress+Length,&rem);\r
\r
// Check if we trying to erase a partition that we are executing in\r
pc = Fls_GetPc();\r
uint32 pcBlock = address_to_block(pc,&rem);\r
uint8 *partMap = Fls_Global.config->FlsBlockToPartitionMap;\r
\r
- if( (partMap[pcBlock] >= partMap[sBlock]) && (partMap[pcBlock] <= partMap[block]) ) {\r
-// if( address_to_block(pc,&rem) == Fls_Global.config->FlsBlockToPartitionMap[block] ) {\r
+ if( (partMap[pcBlock] >= partMap[startBlock]) && (partMap[pcBlock] <= partMap[endBlock]) ) {\r
// Can't erase and in the same partition we are executing\r
assert(0);\r
}\r
}\r
\r
\r
-Std_ReturnType Fls_Write ( MemIf_AddressType TargetAddress,\r
+Std_ReturnType Fls_Write ( Fls_AddressType TargetAddress,\r
const uint8 *SourceAddressPtr,\r
- MemIf_LengthType Length )\r
+ Fls_LengthType Length )\r
{\r
Fls_EraseBlockType eraseBlock;\r
\r
Fls_Global.jobResultType = MEMIF_JOB_OK;\r
Fls_Global.status = MEMIF_IDLE;\r
Fls_Global.jobType = FLS_JOB_NONE;\r
+ FEE_JOB_END_NOTIFICATION();\r
break;\r
case FLS_JOB_WRITE:\r
{\r
}\r
}\r
\r
-Std_ReturnType Fls_Read ( MemIf_AddressType SourceAddress,\r
+Std_ReturnType Fls_Read ( Fls_AddressType SourceAddress,\r
uint8 *TargetAddressPtr,\r
- MemIf_LengthType Length )\r
+ Fls_LengthType Length )\r
{\r
FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_READ_ID, E_NOT_OK);\r
FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_READ_ID, E_NOT_OK);\r
- FLS_VALIDATE_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_READ_ID, E_NOT_OK);\r
- FLS_VALIDATE_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_READ_ID, E_NOT_OK);\r
- FLS_VALIDATE_PARAM_DATA_W_RV((void*)SourceAddress, FLS_READ_ID, E_NOT_OK)\r
+ FLS_VALIDATE_READ_PARAM_ADDRESS_PAGE_W_RV(SourceAddress, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_READ_PARAM_LENGTH_PAGE_W_RV(SourceAddress, Length, FLS_READ_ID, E_NOT_OK);\r
+ FLS_VALIDATE_PARAM_DATA_W_RV((void*)TargetAddressPtr, FLS_READ_ID, E_NOT_OK)\r
\r
// Always check if status is not busy\r
if (Fls_Global.status == MEMIF_BUSY )\r
}\r
\r
#if ( FLS_COMPARE_API == STD_ON )\r
-Std_ReturnType Fls_Compare( MemIf_AddressType SourceAddress,\r
+Std_ReturnType Fls_Compare( Fls_AddressType SourceAddress,\r
uint8 *TargetAddressPtr,\r
- MemIf_LengthType Length )\r
+ Fls_LengthType Length )\r
{\r
FLS_VALIDATE_STATUS_UNINIT_W_RV(Fls_Global.status, FLS_COMPARE_ID, E_NOT_OK);\r
FLS_VALIDATE_STATUS_BUSY_W_RV(Fls_Global.status, FLS_COMPARE_ID, E_NOT_OK);\r
memcpy(VersioninfoPtr, &_Fls_VersionInfo, sizeof(Std_VersionInfoType));\r
}\r
\r
+void Fls_Check( uint32 flsBaseAddress, uint32 flsTotalSize )\r
+{\r
+ // ECC checking is always on by default.\r
+ // If a non correctable error is discovered\r
+ // we will get an IVOR2 exception.\r
+\r
+ // Enable Flash Non_Correctible Reporting,\r
+ // Not really necessary but makes more information\r
+ // available in the MCM registers if an error occurs.\r
+ MCM.ECR.B.EFNCR = 1;\r
+\r
+ // Read flash in 32bit chunks, it's most efficient.\r
+ uint32* memoryChunkPtr = (uint32*)flsBaseAddress;\r
+ uint32* flsTotalSizePtr = (uint32*)flsTotalSize;\r
+ uint32 memoryChunk = *memoryChunkPtr; // The first read\r
+\r
+ // Read the rest of the flash, chunk by chunk\r
+ while(memoryChunkPtr < flsTotalSizePtr)\r
+ {\r
+ memoryChunk=*(memoryChunkPtr++);\r
+ }\r
+}\r
\r
\r
returnCode = Fls_H7F_ProgramStatus(pSSDConfig,pInfo);\r
break;\r
default:\r
+ returnCode = 0;\r
assert(0);\r
break;\r
}\r
return H7F_BUSY;\r
}\r
\r
+EXIT_EHV:\r
+\r
/* Clear MCR-PGM bit */\r
H7FMCR_BIT_CLEAR (MCRAddress, H7F_MCR_PGM);\r
\r
// Clear our struct....\r
memset( pInfo,0x0,sizeof(Fls_ProgInfoType) );\r
\r
-EXIT_EHV:\r
return returnCode;\r
}\r
\r
*/\r
void Fls_H7F_SetLock ( Fls_EraseBlockType *blocks, UINT8 logic )\r
{\r
- vuint32_t *reg;\r
+ vuint32_t *reg, *sreg;\r
struct FLASH_tag *flashHw = &FLASH;\r
\r
if( (blocks->lowEnabledBlocks != 0 ) ||\r
(blocks->midEnabledBlocks != 0 ) ||\r
(blocks->shadowBlocks != 0 ) )\r
{\r
- reg = &(flashHw->LMLR.R);\r
+ reg = &(flashHw->LMLR.R);\r
+ sreg = &(flashHw->SLMLR.R);\r
\r
// Check if sector is locked\r
if( !(*reg & 0x80000000 )) {\r
- // Unlock the sector with password\r
- *reg = FLASH_LMLR_PASSWORD;\r
- }\r
+ // Unlock the sector with password\r
+ *reg = FLASH_LMLR_PASSWORD;\r
+ }\r
+ if( !(*sreg & 0x80000000 )) {\r
+ // Unlock the sector with password\r
+ *sreg = FLASH_SLMLR_PASSWORD;\r
+ }\r
\r
// set/clear them\r
if( logic ) {\r
((~blocks->lowEnabledBlocks) & H7F_LML_LLOCK) |\r
((~blocks->shadowBlocks) & H7F_LML_SLOCK) ;\r
}\r
+ if( logic ) {\r
+ *sreg |= ((blocks->midEnabledBlocks<<16)& H7F_LML_MLOCK) +\r
+ (blocks->lowEnabledBlocks & H7F_LML_LLOCK) +\r
+ (blocks->shadowBlocks & H7F_LML_SLOCK);\r
+ } else {\r
+ *sreg &= ((~blocks->midEnabledBlocks<<16) & H7F_LML_MLOCK) |\r
+ ((~blocks->lowEnabledBlocks) & H7F_LML_LLOCK) |\r
+ ((~blocks->shadowBlocks) & H7F_LML_SLOCK) ;\r
+ }\r
}\r
#if 0\r
else {\r
\r
//-------------------------------------------------------------------\r
\r
-\r
-/**\r
- * ISR helper-function that handles the HW channels( 0 to 8 )\r
- *\r
- * @param channel - Channel that the raised the interrupt\r
+/*\r
+ * ISR for a given PIT channel (macro)\r
*/\r
-\r
-static void Gpt_IsrCh(Gpt_ChannelType channel)\r
-{\r
- const Gpt_ConfigType *config;\r
- int confCh;\r
-\r
- confCh = Gpt_Global.channelMap[channel];\r
- assert(confCh != GPT_CHANNEL_ILL);\r
-\r
- config = &Gpt_Global.config[confCh];\r
-\r
- if (config->GptChannelMode == GPT_MODE_ONESHOT)\r
- {\r
- // Disable the channel\r
- PIT.EN.R &= ~(1<<channel);\r
-\r
- Gpt_Unit[channel].state = GPT_STATE_STOPPED;\r
+#define GPT_ISR( _channel ) \\r
+ static void Gpt_Isr_Channel##_channel( void ) \\r
+ { \\r
+ const Gpt_ConfigType *config; \\r
+ int confCh; \\r
+ \\r
+ /* Find the config entry for the PIT channel. */ \\r
+ confCh = Gpt_Global.channelMap[ _channel ]; \\r
+ assert(confCh != GPT_CHANNEL_ILL); \\r
+ config = &Gpt_Global.config[ confCh ]; \\r
+ \\r
+ if( config->GptChannelMode == GPT_MODE_ONESHOT ) \\r
+ { \\r
+ /* Disable the channel. */ \\r
+ PIT.EN.R &= ~( 1 << _channel ); \\r
+ \\r
+ Gpt_Unit[_channel].state = GPT_STATE_STOPPED; \\r
+ } \\r
+ config->GptNotification(); \\r
+ \\r
+ /* Clear interrupt. */ \\r
+ PIT.FLG.R = ( 1 << _channel ); \\r
}\r
- config->GptNotification();\r
\r
- // Clear interrupt\r
- PIT.FLG.R = (1<<channel); // Added by Mattias 2009-01\r
-}\r
-\r
-//-------------------------------------------------------------------\r
-// Macro that counts leading zeroes.\r
-#define CNTLZW_INV(x) (31-cntlzw(x))\r
+#define STR__(x) #x\r
+#define XSTR__(x) STR__(x)\r
\r
-/**\r
- * ISR that handles all interrupts to the PIT channels\r
- * ( NOT the decrementer )\r
+/*\r
+ * Create instances of the ISR for each PIT channel.\r
*/\r
-\r
-static void Gpt_Isr(void)\r
-{\r
- uint32 flgMask= PIT.FLG.R;\r
- uint8 chNr = 0;\r
-\r
- // Loop over all interrupts\r
- for (; flgMask; flgMask&=~(1<<chNr))\r
- {\r
- // Find first channel that is requesting service.\r
- chNr = CNTLZW_INV(flgMask);\r
- Gpt_IsrCh(chNr);\r
- // Clear interrupt\r
- PIT.FLG.R = (1<<chNr);\r
- }\r
+GPT_ISR( 0 );\r
+GPT_ISR( 1 );\r
+GPT_ISR( 2 );\r
+GPT_ISR( 3 );\r
+GPT_ISR( 4 );\r
+GPT_ISR( 5 );\r
+GPT_ISR( 6 );\r
+GPT_ISR( 7 );\r
+GPT_ISR( 8 );\r
+\r
+#define GPT_ISR_INSTALL( _channel, _prio ) \\r
+{ \\r
+ TaskType tid; \\r
+ tid = Os_Arc_CreateIsr(Gpt_Isr_Channel##_channel, _prio, XSTR__(Gpt_##_channel)); \\r
+ Irq_AttachIsr2(tid, NULL, PIT_PITFLG_RTIF + _channel); \\r
}\r
\r
//-------------------------------------------------------------------\r
{\r
if (cfg->GptNotification != NULL)\r
{\r
-\r
-#if defined(USE_KERNEL)\r
- TaskType tid;\r
- tid = Os_Arc_CreateIsr(Gpt_Isr, 2, "Gpt_Isr");\r
- Irq_AttachIsr2(tid, NULL, PIT_PITFLG_RTIF + ch);\r
-#else\r
- IntCtrl_InstallVector(Gpt_Isr, PIT_PITFLG_RTIF + ch, 1, CPU_Z1);\r
-#endif\r
+ switch( ch )\r
+ {\r
+ case 0: GPT_ISR_INSTALL( 0, cfg->GptNotificationPriority ); break;\r
+ case 1: GPT_ISR_INSTALL( 1, cfg->GptNotificationPriority ); break;\r
+ case 2: GPT_ISR_INSTALL( 2, cfg->GptNotificationPriority ); break;\r
+ case 3: GPT_ISR_INSTALL( 3, cfg->GptNotificationPriority ); break;\r
+ case 4: GPT_ISR_INSTALL( 4, cfg->GptNotificationPriority ); break;\r
+ case 5: GPT_ISR_INSTALL( 5, cfg->GptNotificationPriority ); break;\r
+ case 6: GPT_ISR_INSTALL( 6, cfg->GptNotificationPriority ); break;\r
+ case 7: GPT_ISR_INSTALL( 7, cfg->GptNotificationPriority ); break;\r
+ case 8: GPT_ISR_INSTALL( 8, cfg->GptNotificationPriority ); break;\r
+ default:\r
+ {\r
+ // Unknown PIT channel.\r
+ assert( 0 );\r
+ break;\r
+ }\r
+ }\r
}\r
}\r
#if defined(USE_KERNEL)\r
{\r
remaining = get_spr(SPR_DEC);\r
}\r
+ else\r
+ {\r
+ /* We have written a fault in the fault log. Return 0. */\r
+ remaining = 0;\r
+ }\r
\r
return remaining;\r
}\r
{\r
timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
}\r
+ else\r
+ {\r
+ /* We have written a fault in the fault log. Return 0. */\r
+ timer = 0;\r
+ }\r
\r
return (timer);\r
}\r
#include <stdlib.h>\r
#include <string.h>\r
#include "LinIf_Cbk.h"\r
+#if defined(USE_KERNEL)\r
+#include "Os.h"\r
+#include "irq.h"\r
+#endif\r
\r
#define ESCI(exp) (volatile struct ESCI_tag *)(0xFFFA0000 + (0x4000 * exp))\r
\r
// Install the interrupt\r
if (Channel > 3)\r
{\r
+#if defined(USE_KERNEL)\r
+ TaskType tid;\r
+ tid = Os_Arc_CreateIsr(aIntFnc[Channel],LIN_PRIO,"Lin");\r
+ Irq_AttachIsr2(tid,NULL,SCI_E_COMB + Channel);\r
+#else\r
Irq_InstallVector(aIntFnc[Channel],SCI_E_COMB + Channel,LIN_PRIO,CPU_Z1);\r
+#endif\r
}\r
else\r
{\r
+#if defined(USE_KERNEL)\r
+ TaskType tid;\r
+ tid = Os_Arc_CreateIsr(aIntFnc[Channel],LIN_PRIO,"Lin");\r
+ Irq_AttachIsr2(tid,NULL,SCI_A_COMB + Channel);\r
+#else\r
Irq_InstallVector(aIntFnc[Channel],SCI_A_COMB + Channel,LIN_PRIO,CPU_Z1);\r
+#endif\r
}\r
\r
esciHw->CR2.B.MDIS = 0;/* The module is enabled by writing the ESCIx_CR2[MDIS] bit to 0. */\r
#include "Os.h"\r
#include "irq.h"\r
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#include "debug.h"\r
\r
Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);\r
#endif\r
\r
+ /*\r
+ * NOTE!!!\r
+ * This interrupt may be triggered more than expected.\r
+ * If you are going to use this interrupt, see [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 6764].\r
+ *\r
+ */\r
+\r
Mcu_Global.stats.lossOfLockCnt++;\r
// Clear interrupt\r
FMPLL.SYNSR.B.LOLF = 1;\r
#include "Std_Types.h"\r
#include "Port.h"\r
#include "mpc55xx.h"\r
-#include <string.h>\r
#include "Det.h"\r
#include "Cpu.h"\r
+#include <string.h>\r
/* SHORT ON HW\r
* Have a bunch of ports:\r
* - PAxx, input only port\r
*\r
*/\r
\r
+typedef enum\r
+{\r
+ PORT_UNINITIALIZED = 0, PORT_INITIALIZED,\r
+} Port_StateType;\r
+\r
static Port_StateType _portState = PORT_UNINITIALIZED;\r
+static const Port_ConfigType * _configPtr = &PortConfigData;\r
\r
#if (PORT_DEV_ERROR_DETECT)\r
#define VALIDATE_PARAM_CONFIG(_ptr,_api) \\r
if( (_ptr)==((void *)0) ) { \\r
Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_CONFIG ); \\r
- goto cleanup; \\r
+ return; \\r
}\r
\r
#define VALIDATE_STATE_INIT(_api)\\r
if(PORT_INITIALIZED!=_portState){\\r
Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_UNINIT ); \\r
- goto cleanup; \\r
+ return; \\r
}\r
\r
#define VALIDATE_PARAM_PIN(_pin, _api)\\r
if(_pin>sizeof(SIU.PCR)){\\r
Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_PIN ); \\r
- goto cleanup; \\r
+ return; \\r
}\r
#else\r
#define VALIDATE_PARAM_CONFIG(_ptr,_api)\r
static Std_VersionInfoType _Port_VersionInfo =\r
{\r
.vendorID = (uint16)1,\r
- .moduleID = (uint16)1,\r
+ .moduleID = (uint16) MODULE_ID_PORT,\r
.instanceID = (uint8)1,\r
.sw_major_version = (uint8)PORT_SW_MAJOR_VERSION,\r
.sw_minor_version = (uint8)PORT_SW_MINOR_VERSION,\r
};\r
#endif\r
\r
-const Port_ConfigType * _configPtr = &PortConfigData;\r
void Port_Init(const Port_ConfigType *configType)\r
{\r
VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);\r
// Pointers to the register memory areas\r
vuint16_t * padConfig = &(SIU.PCR[0].R);\r
vuint8_t * outConfig = &(SIU.GPDO[0].R);\r
-// vuint8_t * inConfig = &(SIU.GPDI[0].R);\r
+// vuint8_t * inConfig = &(SIU.GPDI[0].R); // Read only\r
\r
// Copy config to register areas\r
memcpy((void *)outConfig, configType->outConfig, configType->outCnt);\r
//memcpy((void *)inConfig, configType->inConfig, configType->inCnt);\r
_portState = PORT_INITIALIZED;\r
_configPtr = configType;\r
- cleanup: return;\r
+ return;\r
}\r
\r
-#if ( PORT_PIN_DIRECTION_CHANGES_ALLOWED == STD_ON )\r
+#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )\r
void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
{\r
VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
state = _Irq_Disable_save(); // Lock interrupts\r
SIU.PCR[pin].B.IBE = 1;\r
SIU.PCR[pin].B.OBE = 0;\r
- _Irq_Disable_restore(state); // Restore interrups\r
+ _Irq_Disable_restore(state); // Restore interrupts\r
}\r
else\r
{\r
state = _Irq_Disable_save(); // Lock interrupts\r
SIU.PCR[pin].B.IBE = 0;\r
SIU.PCR[pin].B.OBE = 1;\r
- _Irq_Disable_restore(state); // Restore interrups\r
+ _Irq_Disable_restore(state); // Restore interrupts\r
}\r
-cleanup:return;\r
+ return;\r
}\r
+#endif\r
\r
void Port_RefreshPortDirection( void )\r
{\r
VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);\r
vuint16_t * pcrPtr = &(SIU.PCR[0].R);\r
const uint16_t * padCfgPtr = _configPtr->padConfig;\r
- uint16_t bitMask = IBE_ENABLE|OBE_ENABLE;\r
+ uint16_t bitMask = PORT_IBE_ENABLE|PORT_OBE_ENABLE;\r
int i;\r
unsigned long state;\r
for (i=0; i < sizeof(SIU.PCR); i++)\r
padCfgPtr++;\r
}\r
\r
- cleanup:return;\r
+ return;\r
}\r
-#endif\r
\r
#if PORT_VERSION_INFO_API == STD_ON\r
void Port_GetVersionInfo(Std_VersionInfoType* versionInfo)\r
{\r
VALIDATE_STATE_INIT(PORT_GET_VERSION_INFO_ID);\r
memcpy(versionInfo, &_Port_VersionInfo, sizeof(Std_VersionInfoType));\r
- cleanup: return;\r
+ return;\r
}\r
#endif\r
\r
+#if (PORT_SET_PIN_MODE_API == STD_ON)\r
void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode)\r
{\r
VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
//characteristics of external pins. The PCRs can select the multiplexed function of a pin, selection of pullup\r
//or pulldown devices, the slew rate of I/O signals, open drain mode for output pins, and hysteresis.\r
SIU.PCR[Pin].R = Mode; // Put the selected mode to the PCR register\r
- cleanup: return;\r
+ return;\r
}\r
-\r
+#endif\r
#include "Os.h"\r
#endif\r
#include "Mcu.h"\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
+#include "irq.h"\r
+#include "arc.h"\r
+#endif\r
+\r
\r
#if PWM_DEV_EROR_DETECT==STD_ON\r
#define PWM_VALIDATE(_exp, _errid) \\r
#include "Det.h"\r
#include <stdlib.h>\r
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#undef DEBUG_LVL\r
#define DEBUG_LVL DEBUG_HIGH\r
\r
\r
#include "mpc55xx.h"\r
-#include "mcu.h"\r
+#include "Mcu.h"\r
void StartWatchdog(void)\r
{\r
// Setup watchdog\r
\r
#define MPC5516 1\r
\r
+#include "Compiler.h"\r
#include "typedefs.h"\r
\r
#ifdef __cplusplus\r
/****************************************************************************/\r
/* MODULE : CRP */\r
/****************************************************************************/\r
- struct CRP_tag {\r
+CC_EXTENSION struct CRP_tag {\r
\r
union {\r
vuint32_t R;\r
/****************************************************************************/\r
/* MODULE : DMAMUX */\r
/****************************************************************************/\r
- struct DMAMUX_tag {\r
+CC_EXTENSION struct DMAMUX_tag {\r
union {\r
vuint8_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : DSPI */\r
/****************************************************************************/\r
- struct DSPI_tag {\r
+CC_EXTENSION struct DSPI_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : External Bus Interface (EBI) */\r
/****************************************************************************/\r
- struct CS_tag {\r
+CC_EXTENSION struct CS_tag {\r
union { /* Base Register Bank */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : eDMA */\r
/****************************************************************************/\r
- struct EDMA_tag {\r
+CC_EXTENSION struct EDMA_tag {\r
union {\r
vuint32_t R;\r
struct {\r
\r
};\r
\r
- struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+ CC_EXTENSION struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
\r
struct tcd_alt1_t {\r
vuint32_t SADDR; /* source address */\r
/****************************************************************************/\r
/* MODULE : EMIOS */\r
/****************************************************************************/\r
- struct EMIOS_tag {\r
+ CC_EXTENSION struct EMIOS_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : EQADC */\r
/****************************************************************************/\r
- struct EQADC_tag {\r
+CC_EXTENSION struct EQADC_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : eSCI */\r
/****************************************************************************/\r
- struct ESCI_tag {\r
+CC_EXTENSION struct ESCI_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FLASH */\r
/****************************************************************************/\r
- struct FLASH_tag {\r
+CC_EXTENSION struct FLASH_tag {\r
union { /* Module Configuration Register */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FlexCAN */\r
/****************************************************************************/\r
- struct FLEXCAN_tag {\r
+CC_EXTENSION struct FLEXCAN_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FMPLL */\r
/****************************************************************************/\r
- struct FMPLL_tag {\r
+CC_EXTENSION struct FMPLL_tag {\r
union { /* JRichard */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : i2c */\r
/****************************************************************************/\r
- struct I2C_tag {\r
+CC_EXTENSION struct I2C_tag {\r
union {\r
vuint8_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : INTC */\r
/****************************************************************************/\r
- struct INTC_tag {\r
+CC_EXTENSION struct INTC_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : MCM */\r
/****************************************************************************/\r
- struct MCM_tag {\r
+CC_EXTENSION struct MCM_tag {\r
\r
uint32_t mcm_reserved1[5];\r
\r
/****************************************************************************/\r
/* MODULE : MPU */\r
/****************************************************************************/\r
- struct MPU_tag {\r
+CC_EXTENSION struct MPU_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : pit */\r
/****************************************************************************/\r
- struct PIT_tag {\r
+CC_EXTENSION struct PIT_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : sem4 */\r
/****************************************************************************/\r
- struct SEMA4_tag {\r
+CC_EXTENSION struct SEMA4_tag {\r
union {\r
vuint8_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : SIU */\r
/****************************************************************************/\r
- struct SIU_tag {\r
+CC_EXTENSION struct SIU_tag {\r
int32_t SIU_reserved0;\r
\r
union { /* MCU ID Register */\r
/* MODULE : FlexRay */\r
/****************************************************************************/\r
\r
- typedef union uMVR {\r
+CC_EXTENSION typedef union uMVR {\r
vuint16_t R;\r
struct {\r
vuint16_t CHIVER:8; /* CHI Version Number */\r
} B;\r
} MVR_t;\r
\r
- typedef union uMCR {\r
+CC_EXTENSION typedef union uMCR {\r
vuint16_t R;\r
struct {\r
vuint16_t MEN:1; /* module enable */\r
vuint16_t:1;\r
} B;\r
} MCR_t;\r
- typedef union uSTBSCR {\r
+CC_EXTENSION typedef union uSTBSCR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t STBPSEL:2; /* strobe port select */\r
} B;\r
} STBSCR_t;\r
- typedef union uSTBPCR {\r
+CC_EXTENSION typedef union uSTBPCR {\r
vuint16_t R;\r
struct {\r
vuint16_t:12;\r
} B;\r
} STBPCR_t;\r
\r
- typedef union uMBDSR {\r
+CC_EXTENSION typedef union uMBDSR {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
} B;\r
} MBDSR_t;\r
\r
- typedef union uMBSSUTR {\r
+CC_EXTENSION typedef union uMBSSUTR {\r
vuint16_t R;\r
struct {\r
\r
} B;\r
} MBSSUTR_t;\r
\r
- typedef union uPOCR {\r
+CC_EXTENSION typedef union uPOCR {\r
vuint16_t R;\r
vuint8_t byte[2];\r
struct {\r
} B;\r
} POCR_t;\r
/* protocol commands */\r
- typedef union uGIFER {\r
+CC_EXTENSION typedef union uGIFER {\r
vuint16_t R;\r
struct {\r
vuint16_t MIF:1; /* module interrupt flag */\r
vuint16_t TBIE:1; /* transmit buffer interrupt enable */\r
} B;\r
} GIFER_t;\r
- typedef union uPIFR0 {\r
+\r
+CC_EXTENSION typedef union uPIFR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */\r
vuint16_t CYSIF:1; /* cycle start interrupt flag */\r
} B;\r
} PIFR0_t;\r
- typedef union uPIFR1 {\r
+\r
+ CC_EXTENSION typedef union uPIFR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t EMCIF:1; /* error mode changed interrupt flag */\r
vuint16_t:4;\r
} B;\r
} PIFR1_t;\r
- typedef union uPIER0 {\r
+CC_EXTENSION typedef union uPIER0 {\r
vuint16_t R;\r
struct {\r
vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */\r
vuint16_t CYSIE:1; /* cycle start interrupt enable */\r
} B;\r
} PIER0_t;\r
- typedef union uPIER1 {\r
+CC_EXTENSION typedef union uPIER1 {\r
vuint16_t R;\r
struct {\r
vuint16_t EMCIE:1; /* error mode changed interrupt enable */\r
vuint16_t:4;\r
} B;\r
} PIER1_t;\r
- typedef union uCHIERFR {\r
+ CC_EXTENSION typedef union uCHIERFR {\r
vuint16_t R;\r
struct {\r
vuint16_t FRLBEF:1; /* flame lost channel B error flag */\r
vuint16_t ILSAEF:1; /* illegal access error flag */\r
} B;\r
} CHIERFR_t;\r
- typedef union uMBIVEC {\r
+ CC_EXTENSION typedef union uMBIVEC {\r
vuint16_t R;\r
struct {\r
\r
} B;\r
} MBIVEC_t;\r
\r
- typedef union uPSR0 {\r
+ CC_EXTENSION typedef union uPSR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t ERRMODE:2; /* error mode */\r
/* protocol states */\r
/* protocol sub-states */\r
/* wakeup status */\r
- typedef union uPSR1 {\r
+ CC_EXTENSION typedef union uPSR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t CSAA:1; /* cold start attempt abort flag */\r
vuint16_t APTAC:5; /* allow passive to active counter */\r
} B;\r
} PSR1_t;\r
- typedef union uPSR2 {\r
+ CC_EXTENSION typedef union uPSR2 {\r
vuint16_t R;\r
struct {\r
vuint16_t NBVB:1; /* NIT boundary violation on channel B */\r
vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */\r
} B;\r
} PSR2_t;\r
- typedef union uPSR3 {\r
+ CC_EXTENSION typedef union uPSR3 {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
vuint16_t AVFA:1; /* aggregated valid frame on channel A */\r
} B;\r
} PSR3_t;\r
- typedef union uCIFRR {\r
+ CC_EXTENSION typedef union uCIFRR {\r
vuint16_t R;\r
struct {\r
vuint16_t:8;\r
vuint16_t TBIFR:1; /* transmit buffer interrupt flag */\r
} B;\r
} CIFRR_t;\r
- typedef union uSFCNTR {\r
+ CC_EXTENSION typedef union uSFCNTR {\r
vuint16_t R;\r
struct {\r
vuint16_t SFEVB:4; /* sync frames channel B, even cycle */\r
} B;\r
} SFCNTR_t;\r
\r
- typedef union uSFTCCSR {\r
+ CC_EXTENSION typedef union uSFTCCSR {\r
vuint16_t R;\r
struct {\r
vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */\r
vuint16_t SIDEN:1; /* sync frame ID table enable */\r
} B;\r
} SFTCCSR_t;\r
- typedef union uSFIDRFR {\r
+ CC_EXTENSION typedef union uSFIDRFR {\r
vuint16_t R;\r
struct {\r
vuint16_t:6;\r
} B;\r
} SFIDRFR_t;\r
\r
- typedef union uTICCR {\r
+ CC_EXTENSION typedef union uTICCR {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
\r
} B;\r
} TICCR_t;\r
- typedef union uTI1CYSR {\r
+ CC_EXTENSION typedef union uTI1CYSR {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
} B;\r
} TI1CYSR_t;\r
\r
- typedef union uSSSR {\r
+ CC_EXTENSION typedef union uSSSR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
} B;\r
} SSSR_t;\r
\r
- typedef union uSSCCR {\r
+ CC_EXTENSION typedef union uSSCCR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t STATUSMASK:4; /* slot status mask */\r
} B;\r
} SSCCR_t;\r
- typedef union uSSR {\r
+ CC_EXTENSION typedef union uSSR {\r
vuint16_t R;\r
struct {\r
vuint16_t VFB:1; /* valid frame on channel B */\r
vuint16_t TCA:1; /* tx conflict on channel A */\r
} B;\r
} SSR_t;\r
- typedef union uMTSCFR {\r
+ CC_EXTENSION typedef union uMTSCFR {\r
vuint16_t R;\r
struct {\r
vuint16_t MTE:1; /* media access test symbol transmission enable */\r
} B;\r
} MTSCFR_t;\r
\r
- typedef union uRSBIR {\r
+ CC_EXTENSION typedef union uRSBIR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
} B;\r
} RSBIR_t;\r
\r
- typedef union uRFDSR {\r
+ CC_EXTENSION typedef union uRFDSR {\r
vuint16_t R;\r
struct {\r
vuint16_t FIFODEPTH:8; /* fifo depth */\r
} B;\r
} RFDSR_t;\r
\r
- typedef union uRFRFCFR {\r
+ CC_EXTENSION typedef union uRFRFCFR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
} B;\r
} RFRFCFR_t;\r
\r
- typedef union uRFRFCTR {\r
+ CC_EXTENSION typedef union uRFRFCTR {\r
vuint16_t R;\r
struct {\r
vuint16_t:4;\r
vuint16_t F0EN:1; /* filter enable */\r
} B;\r
} RFRFCTR_t;\r
- typedef union uPCR0 {\r
+ CC_EXTENSION typedef union uPCR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t ACTION_POINT_OFFSET:6;\r
} B;\r
} PCR0_t;\r
\r
- typedef union uPCR1 {\r
+ CC_EXTENSION typedef union uPCR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
} B;\r
} PCR1_t;\r
\r
- typedef union uPCR2 {\r
+ CC_EXTENSION typedef union uPCR2 {\r
vuint16_t R;\r
struct {\r
vuint16_t MINISLOT_AFTER_ACTION_POINT:6;\r
} B;\r
} PCR2_t;\r
\r
- typedef union uPCR3 {\r
+ CC_EXTENSION typedef union uPCR3 {\r
vuint16_t R;\r
struct {\r
vuint16_t WAKEUP_SYMBOL_RX_LOW:6;\r
} B;\r
} PCR3_t;\r
\r
- typedef union uPCR4 {\r
+ CC_EXTENSION typedef union uPCR4 {\r
vuint16_t R;\r
struct {\r
vuint16_t CAS_RX_LOW_MAX:7;\r
} B;\r
} PCR4_t;\r
\r
- typedef union uPCR5 {\r
+ CC_EXTENSION typedef union uPCR5 {\r
vuint16_t R;\r
struct {\r
vuint16_t TSS_TRANSMITTER:4;\r
} B;\r
} PCR5_t;\r
\r
- typedef union uPCR6 {\r
+ CC_EXTENSION typedef union uPCR6 {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
} B;\r
} PCR6_t;\r
\r
- typedef union uPCR7 {\r
+ CC_EXTENSION typedef union uPCR7 {\r
vuint16_t R;\r
struct {\r
vuint16_t DECODING_CORRECTION_B:9;\r
} B;\r
} PCR7_t;\r
\r
- typedef union uPCR8 {\r
+ CC_EXTENSION typedef union uPCR8 {\r
vuint16_t R;\r
struct {\r
vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;\r
} B;\r
} PCR8_t;\r
\r
- typedef union uPCR9 {\r
+ CC_EXTENSION typedef union uPCR9 {\r
vuint16_t R;\r
struct {\r
vuint16_t MINISLOT_EXISTS:1;\r
} B;\r
} PCR9_t;\r
\r
- typedef union uPCR10 {\r
+ CC_EXTENSION typedef union uPCR10 {\r
vuint16_t R;\r
struct {\r
vuint16_t SINGLE_SLOT_ENABLED:1;\r
} B;\r
} PCR10_t;\r
\r
- typedef union uPCR11 {\r
+ CC_EXTENSION typedef union uPCR11 {\r
vuint16_t R;\r
struct {\r
vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;\r
} B;\r
} PCR11_t;\r
\r
- typedef union uPCR12 {\r
+ CC_EXTENSION typedef union uPCR12 {\r
vuint16_t R;\r
struct {\r
vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;\r
} B;\r
} PCR12_t;\r
\r
- typedef union uPCR13 {\r
+ CC_EXTENSION typedef union uPCR13 {\r
vuint16_t R;\r
struct {\r
vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;\r
} B;\r
} PCR13_t;\r
\r
- typedef union uPCR14 {\r
+ CC_EXTENSION typedef union uPCR14 {\r
vuint16_t R;\r
struct {\r
vuint16_t RATE_CORRECTION_OUT:11;\r
} B;\r
} PCR14_t;\r
\r
- typedef union uPCR15 {\r
+ CC_EXTENSION typedef union uPCR15 {\r
vuint16_t R;\r
struct {\r
vuint16_t LISTEN_TIMEOUT_L:16;\r
} B;\r
} PCR15_t;\r
\r
- typedef union uPCR16 {\r
+ CC_EXTENSION typedef union uPCR16 {\r
vuint16_t R;\r
struct {\r
vuint16_t MACRO_INITIAL_OFFSET_B:7;\r
} B;\r
} PCR16_t;\r
\r
- typedef union uPCR17 {\r
+ CC_EXTENSION typedef union uPCR17 {\r
vuint16_t R;\r
struct {\r
vuint16_t NOISE_LISTEN_TIMEOUT_L:16;\r
} B;\r
} PCR17_t;\r
\r
- typedef union uPCR18 {\r
+ CC_EXTENSION typedef union uPCR18 {\r
vuint16_t R;\r
struct {\r
vuint16_t WAKEUP_PATTERN:6;\r
} B;\r
} PCR18_t;\r
\r
- typedef union uPCR19 {\r
+ CC_EXTENSION typedef union uPCR19 {\r
vuint16_t R;\r
struct {\r
vuint16_t DECODING_CORRECTION_A:9;\r
} B;\r
} PCR19_t;\r
\r
- typedef union uPCR20 {\r
+ CC_EXTENSION typedef union uPCR20 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_INITIAL_OFFSET_B:8;\r
} B;\r
} PCR20_t;\r
\r
- typedef union uPCR21 {\r
+ CC_EXTENSION typedef union uPCR21 {\r
vuint16_t R;\r
struct {\r
vuint16_t EXTERN_RATE_CORRECTION:3;\r
} B;\r
} PCR21_t;\r
\r
- typedef union uPCR22 {\r
+ CC_EXTENSION typedef union uPCR22 {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
} B;\r
} PCR22_t;\r
\r
- typedef union uPCR23 {\r
+ CC_EXTENSION typedef union uPCR23 {\r
vuint16_t R;\r
struct {\r
vuint16_t micro_per_cycle_l:16;\r
} B;\r
} PCR23_t;\r
\r
- typedef union uPCR24 {\r
+ CC_EXTENSION typedef union uPCR24 {\r
vuint16_t R;\r
struct {\r
vuint16_t CLUSTER_DRIFT_DAMPING:5;\r
} B;\r
} PCR24_t;\r
\r
- typedef union uPCR25 {\r
+ CC_EXTENSION typedef union uPCR25 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_PER_CYCLE_MIN_L:16;\r
} B;\r
} PCR25_t;\r
\r
- typedef union uPCR26 {\r
+ CC_EXTENSION typedef union uPCR26 {\r
vuint16_t R;\r
struct {\r
vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;\r
} B;\r
} PCR26_t;\r
\r
- typedef union uPCR27 {\r
+ CC_EXTENSION typedef union uPCR27 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_PER_CYCLE_MAX_L:16;\r
} B;\r
} PCR27_t;\r
\r
- typedef union uPCR28 {\r
+ CC_EXTENSION typedef union uPCR28 {\r
vuint16_t R;\r
struct {\r
vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;\r
} B;\r
} PCR28_t;\r
\r
- typedef union uPCR29 {\r
+ CC_EXTENSION typedef union uPCR29 {\r
vuint16_t R;\r
struct {\r
vuint16_t EXTERN_OFFSET_CORRECTION:3;\r
} B;\r
} PCR29_t;\r
\r
- typedef union uPCR30 {\r
+ CC_EXTENSION typedef union uPCR30 {\r
vuint16_t R;\r
struct {\r
vuint16_t:12;\r
} B;\r
} PCR30_t;\r
\r
- typedef struct uMSG_BUFF_CCS {\r
+ CC_EXTENSION typedef struct uMSG_BUFF_CCS {\r
union {\r
vuint16_t R;\r
struct {\r
} B;\r
} MBIDXR;\r
} MSG_BUFF_CCS_t;\r
- typedef union uSYSBADHR {\r
+ CC_EXTENSION typedef union uSYSBADHR {\r
vuint16_t R;\r
} SYSBADHR_t;\r
- typedef union uSYSBADLR {\r
+ CC_EXTENSION typedef union uSYSBADLR {\r
vuint16_t R;\r
} SYSBADLR_t;\r
- typedef union uPADR {\r
+ CC_EXTENSION typedef union uPADR {\r
vuint16_t R;\r
} PADR_t;\r
- typedef union uPDAR {\r
+ CC_EXTENSION typedef union uPDAR {\r
vuint16_t R;\r
} PDAR_t;\r
- typedef union uCASERCR {\r
+ CC_EXTENSION typedef union uCASERCR {\r
vuint16_t R;\r
} CASERCR_t;\r
- typedef union uCBSERCR {\r
+ CC_EXTENSION typedef union uCBSERCR {\r
vuint16_t R;\r
} CBSERCR_t;\r
- typedef union uCYCTR {\r
+ CC_EXTENSION typedef union uCYCTR {\r
vuint16_t R;\r
} CYCTR_t;\r
- typedef union uMTCTR {\r
+ CC_EXTENSION typedef union uMTCTR {\r
vuint16_t R;\r
} MTCTR_t;\r
- typedef union uSLTCTAR {\r
+ CC_EXTENSION typedef union uSLTCTAR {\r
vuint16_t R;\r
} SLTCTAR_t;\r
- typedef union uSLTCTBR {\r
+ CC_EXTENSION typedef union uSLTCTBR {\r
vuint16_t R;\r
} SLTCTBR_t;\r
- typedef union uRTCORVR {\r
+ CC_EXTENSION typedef union uRTCORVR {\r
vuint16_t R;\r
} RTCORVR_t;\r
- typedef union uOFCORVR {\r
+ CC_EXTENSION typedef union uOFCORVR {\r
vuint16_t R;\r
} OFCORVR_t;\r
- typedef union uSFTOR {\r
+ CC_EXTENSION typedef union uSFTOR {\r
vuint16_t R;\r
} SFTOR_t;\r
- typedef union uSFIDAFVR {\r
+ CC_EXTENSION typedef union uSFIDAFVR {\r
vuint16_t R;\r
} SFIDAFVR_t;\r
- typedef union uSFIDAFMR {\r
+ CC_EXTENSION typedef union uSFIDAFMR {\r
vuint16_t R;\r
} SFIDAFMR_t;\r
- typedef union uNMVR {\r
+ CC_EXTENSION typedef union uNMVR {\r
vuint16_t R;\r
} NMVR_t;\r
- typedef union uNMVLR {\r
+ CC_EXTENSION typedef union uNMVLR {\r
vuint16_t R;\r
} NMVLR_t;\r
- typedef union uT1MTOR {\r
+ CC_EXTENSION typedef union uT1MTOR {\r
vuint16_t R;\r
} T1MTOR_t;\r
- typedef union uTI2CR0 {\r
+ CC_EXTENSION typedef union uTI2CR0 {\r
vuint16_t R;\r
} TI2CR0_t;\r
- typedef union uTI2CR1 {\r
+ CC_EXTENSION typedef union uTI2CR1 {\r
vuint16_t R;\r
} TI2CR1_t;\r
- typedef union uSSCR {\r
+ CC_EXTENSION typedef union uSSCR {\r
vuint16_t R;\r
} SSCR_t;\r
- typedef union uRFSR {\r
+ CC_EXTENSION typedef union uRFSR {\r
vuint16_t R;\r
} RFSR_t;\r
- typedef union uRFSIR {\r
+ CC_EXTENSION typedef union uRFSIR {\r
vuint16_t R;\r
} RFSIR_t;\r
- typedef union uRFARIR {\r
+ CC_EXTENSION typedef union uRFARIR {\r
vuint16_t R;\r
} RFARIR_t;\r
- typedef union uRFBRIR {\r
+ CC_EXTENSION typedef union uRFBRIR {\r
vuint16_t R;\r
} RFBRIR_t;\r
- typedef union uRFMIDAFVR {\r
+ CC_EXTENSION typedef union uRFMIDAFVR {\r
vuint16_t R;\r
} RFMIDAFVR_t;\r
- typedef union uRFMIAFMR {\r
+ CC_EXTENSION typedef union uRFMIAFMR {\r
vuint16_t R;\r
} RFMIAFMR_t;\r
- typedef union uRFFIDRFVR {\r
+ CC_EXTENSION typedef union uRFFIDRFVR {\r
vuint16_t R;\r
} RFFIDRFVR_t;\r
- typedef union uRFFIDRFMR {\r
+ CC_EXTENSION typedef union uRFFIDRFMR {\r
vuint16_t R;\r
} RFFIDRFMR_t;\r
- typedef union uLDTXSLAR {\r
+ CC_EXTENSION typedef union uLDTXSLAR {\r
vuint16_t R;\r
} LDTXSLAR_t;\r
- typedef union uLDTXSLBR {\r
+ CC_EXTENSION typedef union uLDTXSLBR {\r
vuint16_t R;\r
} LDTXSLBR_t;\r
\r
volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */\r
} FR_tag_t;\r
\r
- typedef union uF_HEADER /* frame header */\r
+ CC_EXTENSION typedef union uF_HEADER /* frame header */\r
{\r
struct {\r
vuint16_t:5;\r
} B;\r
vuint16_t WORDS[3];\r
} F_HEADER_t;\r
- typedef union uS_STSTUS /* slot status */\r
+ CC_EXTENSION typedef union uS_STSTUS /* slot status */\r
{\r
struct {\r
vuint16_t VFB:1; /* Valid Frame on channel B */\r
#define FLASH_END 0xFFFFF\r
\r
/* Define instances of modules */\r
-//#define PBRIDGE_A (*( struct PBRIDGE_A_tag *) 0xC3F00000)\r
-#define MPU (*( struct MPU_tag *) 0xFFF10000)\r
-#define SEMA4 (*( struct SEMA4_tag *) 0xFFF14000)\r
-\r
-#define MCM (*( struct MCM_tag *) 0xFFF40000)\r
-#define EDMA (*( struct EDMA_tag *) 0xFFF44000)\r
-#define INTC (*( struct INTC_tag *) 0xFFF48000)\r
-\r
-#define EQADC (*( struct EQADC_tag *) 0xFFF80000)\r
-\r
-#define I2C (*( struct I2C_tag *) 0xFFF88000)\r
-\r
-#define DSPI_A (*( struct DSPI_tag *) 0xFFF90000)\r
-#define DSPI_B (*( struct DSPI_tag *) 0xFFF94000)\r
-#define DSPI_C (*( struct DSPI_tag *) 0xFFF98000)\r
-#define DSPI_D (*( struct DSPI_tag *) 0xFFF9C000)\r
-\r
-#define ESCI_A (*( struct ESCI_tag *) 0xFFFA0000)\r
-#define ESCI_B (*( struct ESCI_tag *) 0xFFFA4000)\r
-#define ESCI_C (*( struct ESCI_tag *) 0xFFFA8000)\r
-#define ESCI_D (*( struct ESCI_tag *) 0xFFFAC000)\r
-#define ESCI_E (*( struct ESCI_tag *) 0xFFFB0000)\r
-#define ESCI_F (*( struct ESCI_tag *) 0xFFFB4000)\r
-#define ESCI_G (*( struct ESCI_tag *) 0xFFFB8000)\r
-#define ESCI_H (*( struct ESCI_tag *) 0xFFFBC000)\r
-\r
-#define CAN_A (*( struct FLEXCAN_tag *) 0xFFFC0000)\r
-#define CAN_B (*( struct FLEXCAN_tag *) 0xFFFC4000)\r
-#define CAN_C (*( struct FLEXCAN_tag *) 0xFFFC8000)\r
-#define CAN_D (*( struct FLEXCAN_tag *) 0xFFFCC000)\r
-#define CAN_E (*( struct FLEXCAN_tag *) 0xFFFD0000)\r
-#define CAN_F (*( struct FLEXCAN_tag *) 0xFFFD4000)\r
-#define FR (*( struct FR_tag *) 0xFFFD8000)\r
-#define DMAMUX (*( struct DMAMUX_tag *) 0xFFFDC000)\r
-#define PIT (*( struct PIT_tag *) 0xFFFE0000)\r
-#define EMIOS (*( struct EMIOS_tag *) 0xFFFE4000)\r
-#define SIU (*( struct SIU_tag *) 0xFFFE8000)\r
-#define CRP (*( struct CRP_tag *) 0xFFFEC000)\r
-#define FMPLL (*( struct FMPLL_tag *) 0xFFFF0000)\r
-#define EBI (*( struct EBI_tag *) 0xFFFF4000)\r
-#define FLASH (*( struct FLASH_tag *) 0xFFFF8000)\r
+//#define PBRIDGE_A (*( volatile struct PBRIDGE_A_tag *) 0xC3F00000)\r
+#define MPU (*( volatile struct MPU_tag *) 0xFFF10000)\r
+#define SEMA4 (*( volatile struct SEMA4_tag *) 0xFFF14000)\r
+\r
+#define MCM (*( volatile struct MCM_tag *) 0xFFF40000)\r
+#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000)\r
+#define INTC (*( volatile struct INTC_tag *) 0xFFF48000)\r
+\r
+#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000)\r
+\r
+#define I2C (*( volatile struct I2C_tag *) 0xFFF88000)\r
+\r
+#define DSPI_A (*( volatile struct DSPI_tag *) 0xFFF90000)\r
+#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000)\r
+#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000)\r
+#define DSPI_D (*( volatile struct DSPI_tag *) 0xFFF9C000)\r
+\r
+#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFA0000)\r
+#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFA4000)\r
+#define ESCI_C (*( volatile struct ESCI_tag *) 0xFFFA8000)\r
+#define ESCI_D (*( volatile struct ESCI_tag *) 0xFFFAC000)\r
+#define ESCI_E (*( volatile struct ESCI_tag *) 0xFFFB0000)\r
+#define ESCI_F (*( volatile struct ESCI_tag *) 0xFFFB4000)\r
+#define ESCI_G (*( volatile struct ESCI_tag *) 0xFFFB8000)\r
+#define ESCI_H (*( volatile struct ESCI_tag *) 0xFFFBC000)\r
+\r
+#define CAN_A (*( volatile struct FLEXCAN_tag *) 0xFFFC0000)\r
+#define CAN_B (*( volatile struct FLEXCAN_tag *) 0xFFFC4000)\r
+#define CAN_C (*( volatile struct FLEXCAN_tag *) 0xFFFC8000)\r
+#define CAN_D (*( volatile struct FLEXCAN_tag *) 0xFFFCC000)\r
+#define CAN_E (*( volatile struct FLEXCAN_tag *) 0xFFFD0000)\r
+#define CAN_F (*( volatile struct FLEXCAN_tag *) 0xFFFD4000)\r
+#define FR (*( volatile struct FR_tag *) 0xFFFD8000)\r
+#define DMAMUX (*( volatile struct DMAMUX_tag *) 0xFFFDC000)\r
+#define PIT (*( volatile struct PIT_tag *) 0xFFFE0000)\r
+#define EMIOS (*( volatile struct EMIOS_tag *) 0xFFFE4000)\r
+#define SIU (*( volatile struct SIU_tag *) 0xFFFE8000)\r
+#define CRP (*( volatile struct CRP_tag *) 0xFFFEC000)\r
+#define FMPLL (*( volatile struct FMPLL_tag *) 0xFFFF0000)\r
+#define EBI (*( volatile struct EBI_tag *) 0xFFFF4000)\r
+#define FLASH (*( volatile struct FLASH_tag *) 0xFFFF8000)\r
\r
#ifdef __MWERKS__\r
#pragma pop\r
#ifndef _MPC5554_H_\r
#define _MPC5554_H_\r
\r
+#include "Compiler.h"\r
#include "typedefs.h"\r
\r
#ifdef __cplusplus\r
#ifndef _MPC5567_H_\r
#define _MPC5567_H_\r
\r
+#include "Compiler.h"\r
#include "typedefs.h"\r
\r
#ifdef __cplusplus\r
/****************************************************************************/\r
/* MODULE : PBRIDGE_A Peripheral Bridge */\r
/****************************************************************************/\r
- struct PBRIDGE_A_tag {\r
+ CC_EXTENSION struct PBRIDGE_A_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : PBRIDGE_B Peripheral Bridge */\r
/****************************************************************************/\r
- struct PBRIDGE_B_tag {\r
+ CC_EXTENSION struct PBRIDGE_B_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FMPLL */\r
/****************************************************************************/\r
- struct FMPLL_tag {\r
+ CC_EXTENSION struct FMPLL_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : External Bus Interface (EBI) */\r
/****************************************************************************/\r
- struct CS_tag {\r
+ CC_EXTENSION struct CS_tag {\r
union { /* Base Register Bank */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FLASH */\r
/****************************************************************************/\r
- struct FLASH_tag {\r
+ CC_EXTENSION struct FLASH_tag {\r
union { /* Module Configuration Register */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : SIU */\r
/****************************************************************************/\r
- struct SIU_tag {\r
+ CC_EXTENSION struct SIU_tag {\r
int32_t SIU_reserved0;\r
\r
union { /* MCU ID Register */\r
/****************************************************************************/\r
/* MODULE : EMIOS */\r
/****************************************************************************/\r
- struct EMIOS_tag {\r
+ CC_EXTENSION struct EMIOS_tag {\r
union {\r
vuint32_t R;\r
struct {\r
\r
/***************************Configuration Registers**************************/\r
\r
- struct ETPU_tag {\r
+ CC_EXTENSION struct ETPU_tag {\r
union { /* MODULE CONFIGURATION REGISTER */\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : XBAR CrossBar */\r
/****************************************************************************/\r
- struct XBAR_tag {\r
+ CC_EXTENSION struct XBAR_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : ECSM */\r
/****************************************************************************/\r
- struct ECSM_tag {\r
+ CC_EXTENSION struct ECSM_tag {\r
\r
uint32_t ecsm_reserved1[5];\r
\r
/****************************************************************************/\r
/* MODULE : eDMA */\r
/****************************************************************************/\r
- struct EDMA_tag {\r
+ CC_EXTENSION struct EDMA_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/* DMA2 Transfer Control Descriptor */\r
/****************************************************************************/\r
\r
- struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
+ CC_EXTENSION struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */\r
vuint32_t SADDR; /* source address */\r
\r
vuint16_t SMOD:5; /* source address modulo */\r
\r
};\r
\r
- struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
+ CC_EXTENSION struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */\r
\r
struct tcd_alt1_t {\r
vuint32_t SADDR; /* source address */\r
/****************************************************************************/\r
/* MODULE : INTC */\r
/****************************************************************************/\r
- struct INTC_tag {\r
+ CC_EXTENSION struct INTC_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : EQADC */\r
/****************************************************************************/\r
- struct EQADC_tag {\r
+ CC_EXTENSION struct EQADC_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : eSCI */\r
/****************************************************************************/\r
- struct ESCI_tag {\r
+ CC_EXTENSION struct ESCI_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FlexCAN */\r
/****************************************************************************/\r
- struct FLEXCAN2_tag {\r
+ CC_EXTENSION struct FLEXCAN2_tag {\r
union {\r
vuint32_t R;\r
struct {\r
/****************************************************************************/\r
/* MODULE : FEC */\r
/****************************************************************************/\r
- struct FEC_tag {\r
+ CC_EXTENSION struct FEC_tag {\r
\r
uint32_t fec_reserved_start[0x1];\r
\r
/* MODULE : FlexRay */\r
/****************************************************************************/\r
\r
- typedef union uMVR {\r
+ CC_EXTENSION typedef union uMVR {\r
vuint16_t R;\r
struct {\r
vuint16_t CHIVER:8; /* CHI Version Number */\r
} B;\r
} MVR_t;\r
\r
- typedef union uMCR {\r
+ CC_EXTENSION typedef union uMCR {\r
vuint16_t R;\r
struct {\r
vuint16_t MEN:1; /* module enable */\r
vuint16_t:1;\r
} B;\r
} MCR_t;\r
- typedef union uSTBSCR {\r
+ CC_EXTENSION typedef union uSTBSCR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t STBPSEL:2; /* strobe port select */\r
} B;\r
} STBSCR_t;\r
- typedef union uSTBPCR {\r
+ CC_EXTENSION typedef union uSTBPCR {\r
vuint16_t R;\r
struct {\r
vuint16_t:12;\r
} B;\r
} STBPCR_t;\r
\r
- typedef union uMBDSR {\r
+ CC_EXTENSION typedef union uMBDSR {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
vuint16_t MBSEG1DS:7; /* message buffer segment 1 data size */\r
} B;\r
} MBDSR_t;\r
- typedef union uMBSSUTR {\r
+ CC_EXTENSION typedef union uMBSSUTR {\r
vuint16_t R;\r
struct {\r
\r
} B;\r
} MBSSUTR_t;\r
\r
- typedef union uPOCR {\r
+ CC_EXTENSION typedef union uPOCR {\r
vuint16_t R;\r
vuint8_t byte[2];\r
struct {\r
} B;\r
} POCR_t;\r
/* protocol commands */\r
- typedef union uGIFER {\r
+ CC_EXTENSION typedef union uGIFER {\r
vuint16_t R;\r
struct {\r
vuint16_t MIF:1; /* module interrupt flag */\r
vuint16_t TBIE:1; /* transmit buffer interrupt enable */\r
} B;\r
} GIFER_t;\r
- typedef union uPIFR0 {\r
+ CC_EXTENSION typedef union uPIFR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t FATLIF:1; /* fatal protocol error interrupt flag */\r
vuint16_t CYSIF:1; /* cycle start interrupt flag */\r
} B;\r
} PIFR0_t;\r
- typedef union uPIFR1 {\r
+ CC_EXTENSION typedef union uPIFR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t EMCIF:1; /* error mode changed interrupt flag */\r
vuint16_t:4;\r
} B;\r
} PIFR1_t;\r
- typedef union uPIER0 {\r
+ CC_EXTENSION typedef union uPIER0 {\r
vuint16_t R;\r
struct {\r
vuint16_t FATLIE:1; /* fatal protocol error interrupt enable */\r
vuint16_t CYSIE:1; /* cycle start interrupt enable */\r
} B;\r
} PIER0_t;\r
- typedef union uPIER1 {\r
+ CC_EXTENSION typedef union uPIER1 {\r
vuint16_t R;\r
struct {\r
vuint16_t EMCIE:1; /* error mode changed interrupt enable */\r
vuint16_t:4;\r
} B;\r
} PIER1_t;\r
- typedef union uCHIERFR {\r
+ CC_EXTENSION typedef union uCHIERFR {\r
vuint16_t R;\r
struct {\r
vuint16_t FRLBEF:1; /* flame lost channel B error flag */\r
vuint16_t ILSAEF:1; /* illegal access error flag */\r
} B;\r
} CHIERFR_t;\r
- typedef union uMBIVEC {\r
+ CC_EXTENSION typedef union uMBIVEC {\r
vuint16_t R;\r
struct {\r
\r
} B;\r
} MBIVEC_t;\r
\r
- typedef union uPSR0 {\r
+ CC_EXTENSION typedef union uPSR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t ERRMODE:2; /* error mode */\r
/* protocol states */\r
/* protocol sub-states */\r
/* wakeup status */\r
- typedef union uPSR1 {\r
+ CC_EXTENSION typedef union uPSR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t CSAA:1; /* cold start attempt abort flag */\r
vuint16_t APTAC:5; /* allow passive to active counter */\r
} B;\r
} PSR1_t;\r
- typedef union uPSR2 {\r
+ CC_EXTENSION typedef union uPSR2 {\r
vuint16_t R;\r
struct {\r
vuint16_t NBVB:1; /* NIT boundary violation on channel B */\r
vuint16_t CLKCORRFAILCNT:4; /* clock correction failed counter */\r
} B;\r
} PSR2_t;\r
- typedef union uPSR3 {\r
+ CC_EXTENSION typedef union uPSR3 {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
vuint16_t AVFA:1; /* aggregated valid frame on channel A */\r
} B;\r
} PSR3_t;\r
- typedef union uCIFRR {\r
+ CC_EXTENSION typedef union uCIFRR {\r
vuint16_t R;\r
struct {\r
vuint16_t:8;\r
vuint16_t TBIFR:1; /* transmit buffer interrupt flag */\r
} B;\r
} CIFRR_t;\r
- typedef union uSFCNTR {\r
+ CC_EXTENSION typedef union uSFCNTR {\r
vuint16_t R;\r
struct {\r
vuint16_t SFEVB:4; /* sync frames channel B, even cycle */\r
} B;\r
} SFCNTR_t;\r
\r
- typedef union uSFTCCSR {\r
+ CC_EXTENSION typedef union uSFTCCSR {\r
vuint16_t R;\r
struct {\r
vuint16_t ELKT:1; /* even cycle tables lock and unlock trigger */\r
vuint16_t SIDEN:1; /* sync frame ID table enable */\r
} B;\r
} SFTCCSR_t;\r
- typedef union uSFIDRFR {\r
+ CC_EXTENSION typedef union uSFIDRFR {\r
vuint16_t R;\r
struct {\r
vuint16_t:6;\r
} B;\r
} SFIDRFR_t;\r
\r
- typedef union uTICCR {\r
+ CC_EXTENSION typedef union uTICCR {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
\r
} B;\r
} TICCR_t;\r
- typedef union uTI1CYSR {\r
+ CC_EXTENSION typedef union uTI1CYSR {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
} B;\r
} TI1CYSR_t;\r
\r
- typedef union uSSSR {\r
+ CC_EXTENSION typedef union uSSSR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
} B;\r
} SSSR_t;\r
\r
- typedef union uSSCCR {\r
+ CC_EXTENSION typedef union uSSCCR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t STATUSMASK:4; /* slot status mask */\r
} B;\r
} SSCCR_t;\r
- typedef union uSSR {\r
+ CC_EXTENSION typedef union uSSR {\r
vuint16_t R;\r
struct {\r
vuint16_t VFB:1; /* valid frame on channel B */\r
vuint16_t TCA:1; /* tx conflict on channel A */\r
} B;\r
} SSR_t;\r
- typedef union uMTSCFR {\r
+ CC_EXTENSION typedef union uMTSCFR {\r
vuint16_t R;\r
struct {\r
vuint16_t MTE:1; /* media access test symbol transmission enable */\r
vuint16_t CYCCNTVAL:6; /* cycle counter value */\r
} B;\r
} MTSCFR_t;\r
- typedef union uRSBIR {\r
+ CC_EXTENSION typedef union uRSBIR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
vuint16_t RSBIDX:8; /* receive shadow buffer index */\r
} B;\r
} RSBIR_t;\r
- typedef union uRFDSR {\r
+ CC_EXTENSION typedef union uRFDSR {\r
vuint16_t R;\r
struct {\r
vuint16_t FIFODEPTH:8; /* fifo depth */\r
} B;\r
} RFDSR_t;\r
\r
- typedef union uRFRFCFR {\r
+ CC_EXTENSION typedef union uRFRFCFR {\r
vuint16_t R;\r
struct {\r
vuint16_t WMD:1; /* write mode */\r
} B;\r
} RFRFCFR_t;\r
\r
- typedef union uRFRFCTR {\r
+ CC_EXTENSION typedef union uRFRFCTR {\r
vuint16_t R;\r
struct {\r
vuint16_t:4;\r
vuint16_t F0EN:1; /* filter enable */\r
} B;\r
} RFRFCTR_t;\r
- typedef union uPCR0 {\r
+ CC_EXTENSION typedef union uPCR0 {\r
vuint16_t R;\r
struct {\r
vuint16_t ACTION_POINT_OFFSET:6;\r
} B;\r
} PCR0_t;\r
\r
- typedef union uPCR1 {\r
+ CC_EXTENSION typedef union uPCR1 {\r
vuint16_t R;\r
struct {\r
vuint16_t:2;\r
} B;\r
} PCR1_t;\r
\r
- typedef union uPCR2 {\r
+ CC_EXTENSION typedef union uPCR2 {\r
vuint16_t R;\r
struct {\r
vuint16_t MINISLOT_AFTER_ACTION_POINT:6;\r
} B;\r
} PCR2_t;\r
\r
- typedef union uPCR3 {\r
+ CC_EXTENSION typedef union uPCR3 {\r
vuint16_t R;\r
struct {\r
vuint16_t WAKEUP_SYMBOL_RX_LOW:6;\r
} B;\r
} PCR3_t;\r
\r
- typedef union uPCR4 {\r
+ CC_EXTENSION typedef union uPCR4 {\r
vuint16_t R;\r
struct {\r
vuint16_t CAS_RX_LOW_MAX:7;\r
} B;\r
} PCR4_t;\r
\r
- typedef union uPCR5 {\r
+ CC_EXTENSION typedef union uPCR5 {\r
vuint16_t R;\r
struct {\r
vuint16_t TSS_TRANSMITTER:4;\r
} B;\r
} PCR5_t;\r
\r
- typedef union uPCR6 {\r
+ CC_EXTENSION typedef union uPCR6 {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
} B;\r
} PCR6_t;\r
\r
- typedef union uPCR7 {\r
+ CC_EXTENSION typedef union uPCR7 {\r
vuint16_t R;\r
struct {\r
vuint16_t DECODING_CORRECTION_B:9;\r
} B;\r
} PCR7_t;\r
\r
- typedef union uPCR8 {\r
+ CC_EXTENSION typedef union uPCR8 {\r
vuint16_t R;\r
struct {\r
vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;\r
} B;\r
} PCR8_t;\r
\r
- typedef union uPCR9 {\r
+ CC_EXTENSION typedef union uPCR9 {\r
vuint16_t R;\r
struct {\r
vuint16_t MINISLOT_EXISTS:1;\r
} B;\r
} PCR9_t;\r
\r
- typedef union uPCR10 {\r
+ CC_EXTENSION typedef union uPCR10 {\r
vuint16_t R;\r
struct {\r
vuint16_t SINGLE_SLOT_ENABLED:1;\r
} B;\r
} PCR10_t;\r
\r
- typedef union uPCR11 {\r
+ CC_EXTENSION typedef union uPCR11 {\r
vuint16_t R;\r
struct {\r
vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;\r
} B;\r
} PCR11_t;\r
\r
- typedef union uPCR12 {\r
+ CC_EXTENSION typedef union uPCR12 {\r
vuint16_t R;\r
struct {\r
vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;\r
} B;\r
} PCR12_t;\r
\r
- typedef union uPCR13 {\r
+ CC_EXTENSION typedef union uPCR13 {\r
vuint16_t R;\r
struct {\r
vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;\r
} B;\r
} PCR13_t;\r
\r
- typedef union uPCR14 {\r
+ CC_EXTENSION typedef union uPCR14 {\r
vuint16_t R;\r
struct {\r
vuint16_t RATE_CORRECTION_OUT:11;\r
} B;\r
} PCR14_t;\r
\r
- typedef union uPCR15 {\r
+ CC_EXTENSION typedef union uPCR15 {\r
vuint16_t R;\r
struct {\r
vuint16_t LISTEN_TIMEOUT_L:16;\r
} B;\r
} PCR15_t;\r
\r
- typedef union uPCR16 {\r
+ CC_EXTENSION typedef union uPCR16 {\r
vuint16_t R;\r
struct {\r
vuint16_t MACRO_INITIAL_OFFSET_B:7;\r
} B;\r
} PCR16_t;\r
\r
- typedef union uPCR17 {\r
+ CC_EXTENSION typedef union uPCR17 {\r
vuint16_t R;\r
struct {\r
vuint16_t NOISE_LISTEN_TIMEOUT_L:16;\r
} B;\r
} PCR17_t;\r
\r
- typedef union uPCR18 {\r
+ CC_EXTENSION typedef union uPCR18 {\r
vuint16_t R;\r
struct {\r
vuint16_t WAKEUP_PATTERN:6;\r
} B;\r
} PCR18_t;\r
\r
- typedef union uPCR19 {\r
+ CC_EXTENSION typedef union uPCR19 {\r
vuint16_t R;\r
struct {\r
vuint16_t DECODING_CORRECTION_A:9;\r
} B;\r
} PCR19_t;\r
\r
- typedef union uPCR20 {\r
+ CC_EXTENSION typedef union uPCR20 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_INITIAL_OFFSET_B:8;\r
} B;\r
} PCR20_t;\r
\r
- typedef union uPCR21 {\r
+ CC_EXTENSION typedef union uPCR21 {\r
vuint16_t R;\r
struct {\r
vuint16_t EXTERN_RATE_CORRECTION:3;\r
} B;\r
} PCR21_t;\r
\r
- typedef union uPCR22 {\r
+ CC_EXTENSION typedef union uPCR22 {\r
vuint16_t R;\r
struct {\r
vuint16_t:1;\r
} B;\r
} PCR22_t;\r
\r
- typedef union uPCR23 {\r
+ CC_EXTENSION typedef union uPCR23 {\r
vuint16_t R;\r
struct {\r
vuint16_t micro_per_cycle_l:16;\r
} B;\r
} PCR23_t;\r
\r
- typedef union uPCR24 {\r
+ CC_EXTENSION typedef union uPCR24 {\r
vuint16_t R;\r
struct {\r
vuint16_t CLUSTER_DRIFT_DAMPING:5;\r
} B;\r
} PCR24_t;\r
\r
- typedef union uPCR25 {\r
+ CC_EXTENSION typedef union uPCR25 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_PER_CYCLE_MIN_L:16;\r
} B;\r
} PCR25_t;\r
\r
- typedef union uPCR26 {\r
+ CC_EXTENSION typedef union uPCR26 {\r
vuint16_t R;\r
struct {\r
vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;\r
} B;\r
} PCR26_t;\r
\r
- typedef union uPCR27 {\r
+ CC_EXTENSION typedef union uPCR27 {\r
vuint16_t R;\r
struct {\r
vuint16_t MICRO_PER_CYCLE_MAX_L:16;\r
} B;\r
} PCR27_t;\r
\r
- typedef union uPCR28 {\r
+ CC_EXTENSION typedef union uPCR28 {\r
vuint16_t R;\r
struct {\r
vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;\r
} B;\r
} PCR28_t;\r
\r
- typedef union uPCR29 {\r
+ CC_EXTENSION typedef union uPCR29 {\r
vuint16_t R;\r
struct {\r
vuint16_t EXTERN_OFFSET_CORRECTION:3;\r
} B;\r
} PCR29_t;\r
\r
- typedef union uPCR30 {\r
+ CC_EXTENSION typedef union uPCR30 {\r
vuint16_t R;\r
struct {\r
vuint16_t:12;\r
} B;\r
} PCR30_t;\r
\r
- typedef struct uMSG_BUFF_CCS {\r
+ CC_EXTENSION typedef struct uMSG_BUFF_CCS {\r
union {\r
vuint16_t R;\r
struct {\r
volatile MSG_BUFF_CCS_t MBCCS[128]; /* message buffer configuration, control & status registers 0-31 *//*100 */\r
} FR_tag_t;\r
\r
- typedef union uF_HEADER /* frame header */\r
+ CC_EXTENSION typedef union uF_HEADER /* frame header */\r
{\r
struct {\r
vuint16_t:5;\r
} B;\r
vuint16_t WORDS[3];\r
} F_HEADER_t;\r
- typedef union uS_STSTUS /* slot status */\r
+ CC_EXTENSION typedef union uS_STSTUS /* slot status */\r
{\r
struct {\r
vuint16_t VFB:1; /* Valid Frame on channel B */\r
*/\r
\r
/** @req OS383 */\r
-uint32_t Os_SysTickGetTimeElapsed( void )\r
+TickType Os_SysTickGetValue( void )\r
{\r
uint32_t timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
return (timer);\r
-}\r
+}
+
+TickType Os_SysTickGetElapsedValue( uint32_t preValue ) {
+ uint32_t curr;
+ uint32_t max;
+
+ curr = get_spr(SPR_DEC);
+ max = get_spr(SPR_DECAR);
+ return Os_CounterDiff((max - curr),preValue,max);
+}
+\r
LDEBUG_PRINTF(" stack: curr=%p top=%p bottom=%p\n",\r
pcb->stack.curr,\r
pcb->stack.top,\r
- pcb->stack.top+ pcb->stack.size);\r
+ (void *)((size_t)pcb->stack.top+ (size_t)pcb->stack.size));\r
stack = pcb->stack.curr;\r
LDEBUG_PRINTF(" val : context=%08x LR=%08x CR=%08x\n",\r
(unsigned)stack[C_CONTEXT_OFF/4],\r
\r
}\r
\r
-\r
void Irq_EOI( void ) {\r
#if defined(CFG_MPC5516)\r
- struct INTC_tag *intc = &INTC;\r
+ volatile struct INTC_tag *intc = &INTC;\r
intc->EOIR_PRC0.R = 0;\r
#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
volatile struct INTC_tag *intc = &INTC;\r
else\r
{\r
#if defined(CFG_MPC5516)\r
- struct INTC_tag *intc = &INTC;\r
+ volatile struct INTC_tag *intc = &INTC;\r
vector = (intc->IACKR_PRC0.B.INTVEC_PRC0);\r
#elif defined(CFG_MPC5554)||defined(CFG_MPC5567)\r
volatile struct INTC_tag *intc = &INTC;\r
#define IRQ_TYPES_H\r
\r
\r
+#define Irq_SOI()\r
+\r
+/**\r
+ * End-Of-Interrupt. Called by the OS it wants to clear the interrupt.\r
+ */\r
+void Irq_EOI( void );\r
+\r
+\r
typedef enum\r
{\r
/* Software interrupts. */\r
DATA_TLB_EXCEPTION,\r
INSTRUCTION_TLB_EXCEPTION,\r
DEBUG_EXCEPTION,\r
- NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS,\r
+ NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS\r
}IrqType;\r
\r
typedef enum {\r
PERIPHERAL_CLOCK_ESCI_G,\r
PERIPHERAL_CLOCK_ESCI_H,\r
PERIPHERAL_CLOCK_IIC_A,\r
- PERIPHERAL_CLOCK_MLB,\r
+ PERIPHERAL_CLOCK_MLB\r
} McuE_PeriperalClock_t;\r
\r
\r
\r
typedef enum {\r
CPU_CORE0,\r
- CPU_CORE1,\r
+ CPU_CORE1\r
} Cpu_t;\r
\r
#define IRQ_INTERRUPT_OFFSET 0\r
gcc_version := $(word 3,$(shell ${CROSS_COMPILE}gcc --version))\r
gcc_split = $(subst ., ,$(gcc_version))\r
\r
-# If version 4.3 or above then use -te500v1\r
-ifeq ($(word 1,$(gcc_split)),4)\r
-ifneq ($(filter $(word 2,$(gcc_split)),3 4 5 6 7 8 9),)\r
-ppc_common-$(CFG_SPE) += -te500v1 -mhard-float # -mfloat-gprs=single -mspe=yes -mhard-float\r
-endif\r
-endif\r
+# If version 4.3 or above then use -te500v1 (CodeSourcery)\r
+#ifeq ($(word 1,$(gcc_split)),4)\r
+#ifneq ($(filter $(word 2,$(gcc_split)),3 4 5 6 7 8 9),)\r
+#ppc_common-$(CFG_SPE) += -te500v1 -mhard-float # -mfloat-gprs=single -mspe=yes -mhard-float\r
+#endif\r
+#endif\r
ifeq ($(ppc_common-y),)\r
ppc_common-$(CFG_SPE) += -mfloat-gprs=single -mspe=yes -mhard-float -mcpu=8540 -mno-eabi\r
endif\r
* Copyright (C) 2009 ArcCore AB <contact@arccore.com> \r
*/\r
\r
-/* For more info on sections check the E500 freescale doc: E500ABIUG.pdf\r
- *\r
- */\r
+#include "Calibration_Settings.h"\r
+/* Undef sections/keywords */ \r
+#undef PPC\r
+\r
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", "elf32-powerpc")\r
OUTPUT_ARCH(powerpc)\r
ENTRY(_start)\r
\r
\r
+\r
MEMORY\r
{\r
- /* MPC55xx Reset Control Word(RCW) */\r
- rcw(R) : ORIGIN = 0x00000000, LENGTH = 0x8\r
- flash(R) : ORIGIN = 0x00000008, LENGTH = 0x100000\r
- /* 5516S, 48K\r
- * 5517S,5516G,5516E, 64K RAM\r
- * 5517G,E , 80K RAM\r
- */\r
- ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
+#include "memory.ldf"\r
}\r
\r
SECTIONS\r
{\r
- .rcw : { *(.rcw) }> rcw\r
+/* __CALIB_RAM_START, __CALIB_RAM_END, __CALIB_ROM_START are needed by the a2l and the rte generator. \r
+ CALIBRATION_ENABLED, CALIBRATION_INITIALIZED_RAM, CALIBRATION_FLS_START are generated by rte \r
+*/\r
+#if defined(CALIBRATION_ENABLED)\r
+#if defined(CALIBRATION_INITIALIZED_RAM)\r
+/* when calibration is active a flash and ram area is needed. the rte will copy the calibration area from flash to ram. */\r
+ .calibration : AT(CALIBRATION_FLS_START) { \r
+ *(.calibration)\r
+ } > ram \r
+#else /* CALIBRATION_INITIALIZED_RAM */\r
+/* when calibration isnt active only a flash area is needed. */ \r
+ .calibration CALIBRATION_FLS_START : {\r
+ *(.calibration)\r
+ } > flash \r
+#endif\r
+\r
+__CALIB_RAM_START = ADDR(.calibration);\r
+__CALIB_RAM_END = ADDR(.calibration) + SIZEOF(.calibration);\r
+__CALIB_ROM_START = LOADADDR(.calibration);\r
+#else\r
+ /* failsafe to avoid trouble with defined calib variables if CALIBRATION_ENABLED is not set */\r
+ .calibration : {\r
+ *(.calibration)\r
+ } > flash\r
+ ASSERT(SIZEOF(.calibration) == 0, ".calibration section used but CALIBRATION_ENABLED is undefined")\r
+#endif /* CALIBRATION_ENABLED */\r
+\r
+\r
+#if defined(USE_FEE)\r
+#include "Fee_Memory_Cfg.h"\r
+\r
+ .fee_bank1 FEE_BANK1_OFFSET : {\r
+ . = . + FEE_BANK1_LENGTH;\r
+ } > flash\r
+\r
+ .fee_bank2 FEE_BANK2_OFFSET : {\r
+ . = . + FEE_BANK2_LENGTH;\r
+ } > flash\r
+#endif\r
+\r
+#if defined(USE_FEE) || defined(CALIBRATION_ENABLED)\r
+/* Place the rest of the code is in another flash partition that the calibration and fee banks. */\r
+__FLS_PROG_START__ = 0x20000; /* Must be aligned to a sector start. */\r
+#else\r
+\r
+__FLS_PROG_START__ = 0; /* Must be aligned to a sector start. */\r
+#endif\r
+\r
+ .rcw __FLS_PROG_START__ : { *(.rcw) } > flash\r
+\r
\r
.text :\r
{\r
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*);\r
__TEXT_END = .;\r
. = . + ALIGN(8);\r
- __DATA_ROM = .;\r
} > flash\r
+ \r
\r
- .data : AT(ALIGN(LOADADDR(.sbss2)+SIZEOF(.sbss2),4)) {\r
+ .data : {\r
+ . = . + ALIGN(4);\r
__DATA_RAM = .; *(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
- } > ram\r
+ } > ram AT> flash\r
\r
- .sdata : AT(ALIGN(LOADADDR(.data)+SIZEOF(.data),4)) {\r
+ .sdata : {\r
+ . = . + ALIGN(4);\r
__SDATA_START__ = .;\r
_SDA_BASE_ = .; /* r13 */\r
*(.sdata .sdata.* .gnu.linkonce.s.*)\r
*(PPC.EMB.sdata2 .PPC.EMB.sbss2)\r
. = . + ALIGN(8);\r
__DATA_END = .;\r
- } > ram\r
+ } > ram AT> flash\r
\r
.sbss :\r
{\r
.fixup : { . = . + ALIGN(16);*(.fixup); . = . + ALIGN(8); } > ram\r
.t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
.got : AT(ALIGN(LOADADDR(.sdata)+SIZEOF(.sdata),4)) { *(.got.plt) *(.got) } > ram\r
- .bss : { *(.bss .bss.* COMMON .gnu.linkonce.b.*);__BSS_END = .; } > ram\r
+ /* .bss : { *(.bss .bss.* COMMON .gnu.linkonce.b.*);__BSS_END = .; } > ram */\r
+ .bss : AT(ADDR(.bss)) { *(.bss .bss.* COMMON .gnu.linkonce.b.*);__BSS_END = .; } > ram\r
.init_stack ALIGN(16) (NOLOAD) : { __SP_END = .;. = . + 1000; __SP_INIT = .; } > ram\r
/* Fls RAM section */\r
.fls_ram ALIGN(16) (NOLOAD) : {\r
__RAM_START = ADDR(.sdata);\r
\r
__DATA_RAM = ADDR(.data);\r
+__DATA_ROM = LOADADDR(.data);\r
/*__DATA_END = ADDR(.sdata)+SIZEOF(.sdata);*/\r
/*__BSS_START = ADDR(.sbss);*/\r
__BSS_START = ADDR(.sbss);\r
obj-$(CFG_PPC) += crt0.o\r
-obj-$(CFG_HCS12D) += crt0.o\r
-vpath-$(CFG_ARM_CM3) += $(ARCH_PATH-y)kernel\r
-obj-$(CFG_ARM_CM3) += system_stm32f10x.o\r
+obj-$(CFG_HC1X) += crt0.o\r
+vpath-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32F10x_StdPeriph_Driver/src\r
+vpath-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32_ETH_Driver/src\r
+inc-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32F10x_StdPeriph_Driver/inc\r
+inc-$(CFG_ARM_CM3) += $(ROOTDIR)/$(ARCH_PATH-y)/drivers/STM32_ETH_Driver/inc\r
obj-$(CFG_ARM_CM3) += core_cm3.o\r
-\r
-obj-$(CFG_STM32_MD) += startup_stm32f10x_md.o\r
-obj-$(CFG_STM32_LD) += startup_stm32f10x_ld.o\r
-obj-$(CFG_STM32_HD) += startup_stm32f10x_hd.o\r
-obj-$(CFG_STM32_CL) += startup_stm32f10x_cl.o\r
+obj-$(CFG_ARM_CM3) += startup_stm32f10x.o\r
+#stm32 lib files needed by drivers\r
+obj-$(CFG_ARM_CM3) += stm32f10x_rcc.o\r
+obj-$(CFG_ARM_CM3)-$(USE_CAN) += stm32f10x_can.o\r
+obj-$(CFG_ARM_CM3)-$(USE_PORT) += stm32f10x_gpio.o\r
+obj-$(CFG_ARM_CM3)-$(USE_ADC) += stm32f10x_adc.o\r
+obj-$(CFG_ARM_CM3)-$(USE_ADC) += stm32f10x_dma.o\r
+obj-$(CFG_ARM_CM3)-$(USE_FLS) += stm32f10x_flash.o\r
+obj-$(CFG_ARM_CM3)-$(USE_PWM) += stm32f10x_tim.o\r
+obj-$(CFG_ARM_CM3)-$(USE_LWIP) += stm32_eth.o\r
+\r
+obj-$(USE_TTY_TMS570_KEIL) += GLCD.o\r
+obj-$(USE_TTY_TMS570_KEIL) += emif.o\r
+\r
+# Cortex R4\r
+obj-$(CFG_ARM_CR4) += startup_cr4.o\r
+\r
+# OS object files. \r
+# (checking if already included for compatability)\r
+ifeq ($(filter Os_Cfg.o,$(obj-y)),)\r
+obj-$(USE_KERNEL) += Os_Cfg.o\r
+endif\r
\r
#Ecu\r
-#obj-y += EcuM_$(BOARDDIR).o\r
-obj-y += EcuM.o\r
-obj-y += EcuM_Cfg.o\r
-obj-y += EcuM_Callout_template.o\r
-inc-y += $(ROOTDIR)/system/EcuM\r
-vpath-y += $(ROOTDIR)/system/EcuM\r
+obj-$(USE_ECUM) += EcuM.o\r
+obj-$(USE_ECUM) += EcuM_Main.o\r
+obj-$(USE_ECUM) += EcuM_Cfg.o\r
+obj-$(USE_ECUM) += EcuM_Callout_template.o\r
+inc-$(USE_ECUM) += $(ROOTDIR)/system/EcuM\r
+vpath-$(USE_ECUM) += $(ROOTDIR)/system/EcuM\r
\r
# Gpt\r
obj-$(USE_GPT) += Gpt.o\r
# Flash\r
obj-$(USE_FLS) += Fls.o\r
obj-$(USE_FLS) += Fls_Cfg.o\r
-obj-$(USE_FLS) += Fls_H7F.o\r
+obj-$(CFG_MPC55XX)-$(USE_FLS) += Fls_H7F.o\r
\r
# Bring in the freescale driver source \r
inc-$(CFG_MPC55XX) += $(ROOTDIR)/$(ARCH_PATH-y)/delivery/mpc5500_h7f/include\r
obj-$(USE_ADC) += Adc_Cfg.o\r
\r
# Include the kernel\r
+ifneq ($(USE_KERNEL),)\r
include $(ROOTDIR)/system/kernel/makefile\r
+endif\r
\r
# Spi\r
obj-$(USE_SPI) += Spi.o\r
obj-$(USE_SPI) += Spi_Lcfg.o\r
\r
+# NvM\r
+obj-$(USE_NVM) += NvM.o\r
+obj-$(USE_NVM) += NvM_Cfg.o\r
+inc-$(USE_NVM) += $(ROOTDIR)/memory/NvM\r
+vpath-$(USE_NVM) += $(ROOTDIR)/memory/NvM\r
+\r
+# Fee\r
+obj-$(USE_FEE) += Fee.o\r
+obj-$(USE_FEE) += Fee_Cfg.o\r
+inc-$(USE_FEE) += $(ROOTDIR)/memory/Fee\r
+vpath-$(USE_FEE) += $(ROOTDIR)/memory/Fee\r
+\r
#Eep\r
obj-$(USE_EEP) += Eep.o\r
obj-$(USE_EEP) += Eep_Lcfg.o\r
obj-$(USE_PWM) += Pwm_Cfg.o\r
\r
# Misc\r
-obj-y += Det.o\r
+obj-$(USE_DET) += Det.o\r
\r
# Lin\r
obj-$(USE_LIN) += Lin_PBcfg.o\r
\r
# ComM\r
obj-$(USE_COMM) += ComM.o\r
+obj-$(USE_COMM) += ComM_Cfg.o\r
inc-$(USE_COMM) += $(ROOTDIR)/communication/ComM\r
vpath-$(USE_COMM) += $(ROOTDIR)/communication/ComM\r
vpath-y += $(ROOTDIR)/communication/ComM\r
inc-$(USE_COMM) += $(ROOTDIR)/communication/ComM\r
\r
+# Nm\r
+obj-$(USE_NM) += Nm.o\r
+obj-$(USE_NM) += Nm_Cfg.o\r
+inc-$(USE_NM) += $(ROOTDIR)/communication/Nm\r
+vpath-$(USE_NM) += $(ROOTDIR)/communication/Nm\r
+\r
+# CanNm\r
+obj-$(USE_CANNM) += CanNm.o\r
+obj-$(USE_CANNM) += CanNm_LCfg.o\r
+inc-$(USE_CANNM) += $(ROOTDIR)/communication/CanNm\r
+vpath-$(USE_CANNM) += $(ROOTDIR)/communication/CanNm\r
+\r
+# CanSm\r
+obj-$(USE_CANSM) += CanSM.o\r
+obj-$(USE_CANSM) += CanSM_LCfg.o\r
+inc-$(USE_CANSM) += $(ROOTDIR)/communication/CanSM\r
+vpath-$(USE_CANSM) += $(ROOTDIR)/communication/CanSM\r
\r
# Com\r
obj-$(USE_COM) += Com_PbCfg.o\r
obj-$(USE_COM) += Com_Com.o\r
obj-$(USE_COM) += Com_Sched.o\r
obj-$(USE_COM) += Com.o\r
-obj-$(USE_COM) += Com_RunTest.o\r
obj-$(USE_COM) += Com_misc.o\r
-#obj-$(USE_COM) += Com_TestData.o\r
inc-$(USE_PDUR) += $(ROOTDIR)/communication/Com\r
inc-$(USE_COM) += $(ROOTDIR)/communication/Com\r
vpath-$(USE_COM) += $(ROOTDIR)/communication/Com\r
inc-$(USE_DCM) += $(ROOTDIR)/diagnostic/Dcm\r
vpath-$(USE_DCM) += $(ROOTDIR)/diagnostic/Dcm\r
\r
+obj-$(USE_RAMLOG) += ramlog.o\r
\r
+# Common stuff, if speciied\r
+VPATH += $(ROOTDIR)/common\r
\r
-#tests\r
-#obj-y += RunTests.o\r
-#obj-$(USE_CAN) += can_test.o\r
-#obj-$(USE_DIO) += dio_test.o\r
-#obj-$(USE_PORT) += port_test.o\r
-#obj-$(USE_CANIF) += canif_test.o\r
-#obj-$(USE_FLS) += fls_test.o\r
-#obj-y += mahi_test.o\r
-#obj-$(USE_GPT) += gpt_test.o\r
-#obj-$(USE_SPI) += spi_test.o\r
-#obj-$(USE_EEP) += eep_test.o\r
-#obj-y += det_test.o\r
-#obj-$(USE_MCU) += mcu_test.o\r
-#obj-$(USE_FLS_SST25XX) += xfls_test.o\r
-#obj-y += lin_test.o\r
-#obj-$(USE_PDUR) += pdur_test.o\r
-#obj-$(USE_COM) += com_test.o\r
-\r
-#inc-$(USE_TESTS) += $(ROOTDIR)/embunit/embUnit\r
-#inc-$(USE_TESTS) += $(ROOTDIR)/embunit/textui\r
-#inc-$(USE_TESTS) += $(ROOTDIR)/embunit\r
\r
-#libitem-$(USE_TESTS) += $(ROOTDIR)/embunit/embUnit/obj_$(ARCH)/libembunit.a\r
-#libitem-$(USE_TESTS) += $(ROOTDIR)/embunit/textui/obj_$(ARCH)/libtextui.a\r
+#TCF\r
+obj-$(USE_TCF) += tcf.o\r
+obj-$(USE_TCF) += Tcf_Cfg.o\r
+obj-$(USE_TCF) += sys_monitor.o\r
+obj-$(USE_TCF) += streams.o\r
+inc-$(USE_TCF) += $(ROOTDIR)/common/tcf\r
+vpath-$(USE_TCF) += $(ROOTDIR)/common/tcf\r
\r
+#SLEEP\r
+obj-$(USE_SLEEP) += sleep.o\r
\r
\r
-# Common\r
+# Newlib overrides (overridden by default)\r
+ifneq ($(CFG_STANDARD_NEWLIB),y)\r
obj-y += xtoa.o\r
-obj-y += arc.o\r
-#obj-y += malloc.o\r
-obj-$(USE_RAMLOG) += ramlog.o\r
-\r
+obj-y += newlib_port.o\r
# If we have configured console output we include printf. \r
-# Overridden to use lib implementation with CFG_USE_NEWLIB_PRINTF\r
-ifndef (CFG_USE_NEWLIB_PRINTF)\r
+# Overridden to use lib implementation with CFG_NEWLIB_PRINTF\r
+ifneq ($(CFG_NEWLIB_PRINTF),y)\r
+# TODO: This assumes that you print to console.. but you could\r
+# just print to a buffer, e.g. sprintf() \r
ifneq (,$(SELECT_CONSOLE) $(SELECT_OS_CONSOLE))\r
obj-y += printf.o\r
-endif\r
-endif\r
\r
-VPATH += $(ROOTDIR)/common\r
+endif # SELECT_CONSOLE\r
+endif # CFG_NEWLIB_PRINTF\r
+endif # CFG_STANDARD_NEWLIB\r
\r
-obj-y += newlib_port.o\r
obj-y += $(obj-y-y)\r
\r
vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+++ /dev/null
-\r
-# ARCH defines\r
-ARCH=arm_cm3\r
-ARCH_FAM=arm\r
-ARCH_MCU=arm_cm3\r
-\r
-# CFG (y/n) macros\r
-CFG=ARM ARM_CM3 BRD_ET_STM32_STAMP STM32_CL\r
-\r
-# What buildable modules does this board have, \r
-# default or private\r
-MOD_AVAIL=KERNEL MCU PWM ADC ARM_ITM_TERM DEM DCM IOHWAB\r
-#T32_TERM SIMPLE_PRINTF RAMLOG\r
-#\r
-\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
-\r
-# Use little heap\r
-def-y += HEAPSIZE=4000\r
-def-y += STM32F10X_CL\r
-\r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
*/\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "CanTp_Types.h"\r
\r
CanTp_GeneralType CanTpGeneralConfig =\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef CANTP_CFG_H_\r
#define CANTP_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DCM_CFG_H_\r
#define DCM_CFG_H_\r
/*\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Dcm.h"\r
#include "Rte_Dcm.h"\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DEM_CFG_H_\r
#define DEM_CFG_H_\r
/*\r
#define DEM_DEV_ERROR_DETECT STD_ON // Activate/Deactivate Dev Error Detection and Notification.\r
#define DEM_OBD_SUPPORT STD_OFF\r
#define DEM_PTO_SUPPORT STD_OFF\r
-#define DEM_TYPE_OF_DTC_SUPPORTED DEM_ISO14229_1\r
+#define DEM_TYPE_OF_DTC_SUPPORTED 0x01 // ISO14229-1\r
#define DEM_DTC_STATUS_AVAILABILITY_MASK 0xFF\r
#define DEM_CLEAR_ALL_EVENTS STD_OFF // All event or only events with DTC is cleared with Dem_ClearDTC\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DEM_INTERRID_H_\r
#define DEM_INTERRID_H_\r
\r
CANTP_E_OPER_NOT_SUPPORTED,\r
CANTP_E_COMM,\r
CANNM_E_CANIF_TRANSMIT_ERROR,\r
- CANM_E_NETWORK_TIMEOUT,\r
+ CANNM_E_NETWORK_TIMEOUT,\r
CANIF_TRCV_E_TRANSCEIVER,\r
CANIF_E_INVALID_DLC,\r
CANIF_STOPPED,\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DEMINTEVTID_H_\r
#define DEMINTEVTID_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Dem.h"\r
\r
/*********************\r
* Specification: Autosar v2.0.1, Final\r
*\r
*/\r
-#ifndef _DET_CFG_H_\r
-#define _DET_CFG_H_\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H\r
\r
#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
\r
-#endif /*_DET_CFG_H_*/\r
+#endif /*DET_CFG_H*/\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+#warning "This file is currently empty!!!"\r
\r
+#ifndef EA_CFG_H_\r
+#define EA_CFG_H_\r
\r
-\r
-\r
-\r
-#ifndef MEMIF_CFG_H_\r
-#define MEMIF_CFG_H_\r
-\r
-// TODO. include FEE and EA modules\r
-\r
-\r
-\r
-#endif /*MEMIF_CFG_H_*/\r
+#endif /*EA_CFG_H_*/\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-// This file is just examples of implementation for the stubs needed by\r
-// the EcuM. Every Autocore application should use an own version of this\r
-// file to implement the setup and tear down of the system.\r
-\r
-\r
-#include "EcuM.h"\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+\r
+#warning "This default file may only be used as an example!"
+
+#include "EcuM.h"
+#include "EcuM_Cbk.h"\r
#include "Det.h"\r
#if defined(USE_DEM)\r
#include "Dem.h"\r
#endif\r
#if defined(USE_IOHWAB)\r
#include "IoHwAb.h"\r
+#endif
+#if defined(USE_FLS)
+#include "Fls.h"
+#endif
+#if defined(USE_EEP)
+#include "Eep.h"
+#endif
+#if defined(USE_FEE)
+#include "Fee.h"
#endif\r
-\r
-void EcuM_AL_DriverInitZero()\r
+#if defined(USE_EA)
+#include "Ea.h"
+#endif
+#if defined(USE_NVM)
+#include "NvM.h"
+#endif
+#if defined(USE_COMM)
+#include "ComM.h"
+#endif
+#if defined(USE_NM)
+#include "Nm.h"
+#endif
+#if defined(USE_CANNM)
+#include "CanNm.h"
+#endif
+#if defined(USE_CANSM)
+#include "CanSM.h"
+#endif
+#if defined(USE_LINSM)
+#include "LinSM.h"
+#endif
+\r
+void EcuM_AL_DriverInitZero(void)\r
{\r
Det_Init();\r
Det_Start();\r
}\r
\r
-EcuM_ConfigType* EcuM_DeterminePbConfiguration()\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void)\r
{\r
return &EcuMConfig;\r
}\r
-\r
+
void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
-{\r
+{
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
#if defined(USE_MCU)\r
Mcu_Init(ConfigPtr->McuConfig);\r
\r
- // Set up default clock (Mcu_InitClock requires initRun==1)\r
- Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+ /* Set up default clock (Mcu_InitClock requires initRun==1) */
+ /* Ignoring return value */\r
+ (void) Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
\r
// Wait for PLL to sync.\r
- while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
- ;\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)
+ {\r
+ ;
+ }\r
#endif\r
\r
#if defined(USE_DEM)\r
// Setup ICU\r
// TODO\r
\r
+ // Setup PWM\r
#if defined(USE_PWM)\r
// Setup PWM\r
Pwm_Init(ConfigPtr->PwmConfig);\r
}\r
\r
void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
-{\r
+{
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules
+\r
#if defined(USE_SPI)\r
// Setup SPI\r
Spi_Init(ConfigPtr->SpiConfig);\r
\r
#if defined(USE_FLS)\r
// Setup Flash\r
- FlashInit(ConfigPtr->FlashConfig);\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
#endif\r
\r
- // Setup NVRAM Manaager\r
- // TODO\r
-\r
+#if defined(USE_FEE)
+ // Setup FEE
+ Fee_Init();
+#endif
+
+#if defined(USE_EA)
+ // Setup EA
+ Ea_init();
+#endif
+
+#if defined(USE_NVM)
+ // Setup NVRAM Manager and start the read all job
+ NvM_Init();
+ NvM_ReadAll();
+#endif
+
// Setup CAN tranceiver\r
// TODO\r
\r
#if defined(USE_CANTP)\r
// Setup CAN TP\r
CanTp_Init();\r
-#endif\r
+#endif
+
+#if defined(USE_CANSM)
+ CanSM_Init(ConfigPtr->CanSMConfig);
+#endif
\r
// Setup LIN\r
// TODO\r
// Setup PDU Router\r
PduR_Init(ConfigPtr->PduRConfig);\r
#endif\r
+
+#if defined(USE_CANNM)
+ // Setup Can Network Manager
+ CanNm_Init(ConfigPtr->CanNmConfig);
+#endif
+
+#if defined(USE_NM)
+ // Setup Network Management Interface
+ Nm_Init(ConfigPtr->NmConfig);
+#endif
\r
#if defined(USE_COM)\r
// Setup COM layer\r
#endif\r
}\r
\r
-void EcuM_AL_DriverInitThree(const EcuM_ConfigType ConfigPtr)\r
-{\r
- // Setup ComM\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+{
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules
\r
#if defined(USE_DEM)\r
// Setup DEM\r
Dem_Init();\r
#endif\r
\r
- // Setup FIM\r
-\r
-#if defined(USE_CANIF)\r
- // Startup the CAN interafce; due to the missing COM manager\r
-// CanIf_InitController(CANIF_Channel_1, CANIF_Channel_1_CONFIG_0);\r
-// CanIf_SetControllerMode(CANIF_Channel_1, CANIF_CS_STARTED);\r
-#endif\r
-\r
-\r
+#if defined(USE_COMM)
+ // Setup Communication Manager
+ ComM_Init(ConfigPtr->ComMConfig);
+#endif
}\r
+
+void EcuM_OnEnterRUN(void)
+{
+
+}
+
+void EcuM_OnExitRun(void)
+{
+
+}
+
+void EcuM_OnExitPostRun(void)
+{
+
+}
+
+void EcuM_OnPrepShutdown(void)
+{
+
+}
+
+void EcuM_OnGoSleep(void)
+{
+
+}
+
+void EcuM_OnGoOffOne(void)
+{
+
+}
+
+void EcuM_OnGoOffTwo(void)
+{
+
+}
+
+void EcuM_AL_SwitchOff(void)
+{
+
+}
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
\r
+#warning "This default file may only be used as an example!"
+
#include "EcuM.h"\r
\r
EcuM_ConfigType EcuMConfig =\r
.EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
.EcuMDefaultShutdownMode = 0, // Don't care\r
.EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,
\r
-#if defined(USE_MCU)\r
- .McuConfig = McuConfigData,\r
-#endif\r
-#if defined(USE_PORT)\r
- .PortConfig = &PortConfigData,\r
-#endif\r
-#if defined(USE_CAN)\r
- .CanConfig = &CanConfigData,\r
-#endif\r
-#if defined(USE_CANIF)\r
- .CanIfConfig = &CanIf_Config,\r
-#endif\r
-#if defined(USE_COM)\r
- .ComConfig = &ComConfiguration,\r
-#endif\r
-#if defined(USE_DMA)\r
- .DmaConfig = DmaConfig,\r
-#endif\r
-#if defined(USE_ADC)\r
- .AdcConfig = AdcConfig,\r
-#endif\r
-#if defined(USE_PWM)\r
- .PwmConfig = &PwmConfig,\r
-#endif\r
-#if defined(USE_GPT)\r
- .GptConfig = GptConfigData,\r
-#endif\r
+#if defined(USE_MCU)
+ .McuConfig = McuConfigData,
+#endif
+#if defined(USE_PORT)
+ .PortConfig = &PortConfigData,
+#endif
+#if defined(USE_CAN)
+ .CanConfig = &CanConfigData,
+#endif
+#if defined(USE_CANIF)
+ .CanIfConfig = &CanIf_Config,
+#endif
+#if defined(USE_CANSM)
+ .CanSMConfig = &CanSM_Config,
+#endif
+#if defined(USE_CANNM)
+ .CanNmConfig = &CanNm_Config,
+#endif
+#if defined(USE_COM)
+ .ComConfig = &ComConfiguration,
+#endif
+#if defined(USE_COMM)
+ .ComMConfig = &ComM_Config,
+#endif
+#if defined(USE_NM)
+ .NmConfig = &Nm_Config,
+#endif
+#if defined(USE_PDUR)
+ .PduRConfig = &PduR_Config,
+#endif
+#if defined(USE_DMA)
+ .DmaConfig = DmaConfig,
+#endif
+#if defined(USE_ADC)
+ .AdcConfig = AdcConfig,
+#endif
+#if defined(USE_PWM)
+ .PwmConfig = &PwmConfig,
+#endif
+#if defined(USE_GPT)
+ .GptConfig = GptConfigData,
+#endif
+#if defined(USE_FLS)
+ .FlashConfig = FlsConfigSet,
+#endif
};\r
-\r
-void EcuM_OnGoOffTwo( void ) {\r
-\r
-}\r
-\r
-void EcuM_AL_SwitchOff( void ) {\r
-\r
-}\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU):\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Thu Oct 14 15:29:52 CEST 2010\r
+ */\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#if ((ECUM_SW_MAJOR_VERSION != 2) && (ECUM_SW_MINOR_VERSION != 0))\r
+#error "EcuM: Configuration file version differs from BSW version."\r
+#endif\r
+\r
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-// Struct generated by the code generator depends on the\r
-// included modules\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#warning "This default file may only be used as an example!"
+
+#if ((ECUM_SW_MAJOR_VERSION != 2) && (ECUM_SW_MINOR_VERSION != 0))
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef _ECUM_GENERATED_TYPES_H_\r
#define _ECUM_GENERATED_TYPES_H_\r
\r
-#if defined(USE_MCU)\r
-#include "Mcu.h"\r
-#endif\r
-#if defined(USE_PORT)\r
-#include "Port.h"\r
-#endif\r
-#if defined(USE_CAN)\r
-#include "Can.h"\r
-#endif\r
-#if defined(USE_CANIF)\r
-#include "CanIf.h"\r
-#endif\r
-#if defined(USE_PWM)\r
-#include "Pwm.h"\r
-#endif\r
-#if defined(USE_COM)\r
-#include "Com.h"\r
-#endif\r
-#if defined(USE_DMA)\r
-#include "Dma.h"\r
-#endif\r
-#if defined(USE_ADC)\r
-#include "Adc.h"\r
-#endif\r
-#if defined(USE_GPT)\r
-#include "Gpt.h"\r
+#if defined(USE_MCU)
+#include "Mcu.h"
+#endif
+#if defined(USE_PORT)
+#include "Port.h"
+#endif
+#if defined(USE_CAN)
+#include "Can.h"
+#endif
+#if defined(USE_CANIF)
+#include "CanIf.h"
+#endif
+#if defined(USE_PWM)
+#include "Pwm.h"
+#endif
+#if defined(USE_COM)
+#include "Com.h"
+#endif
+#if defined(USE_PDUR)
+#include "PduR.h"
+#endif
+#if defined(USE_DMA)
+#include "Dma.h"
+#endif
+#if defined(USE_ADC)
+#include "Adc.h"
+#endif
+#if defined(USE_GPT)
+#include "Gpt.h"
+#endif
+#if defined(USE_COMM)
+#include "ComM.h"
+#endif
+#if defined(USE_NM)
+#include "Nm.h"
+#endif
+#if defined(USE_CANNM)
+#include "CanNm.h"
+#endif
+#if defined(USE_CANSM)
+#include "CanSM.h"
+#endif
+#if defined(USE_LINSM)
+#include "LinSM.h"
#endif\r
\r
typedef struct\r
EcuM_StateType EcuMDefaultShutdownTarget;\r
uint8 EcuMDefaultShutdownMode;\r
AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;
+ uint32 EcuMNvramReadAllTimeout;
+ uint32 EcuMNvramWriteAllTimeout;
\r
-#if defined(USE_MCU)\r
- const Mcu_ConfigType* McuConfig;\r
-#endif\r
-#if defined(USE_PORT)\r
- const Port_ConfigType* PortConfig;\r
-#endif\r
-#if defined(USE_CAN)\r
- const Can_ConfigType* CanConfig;\r
-#endif\r
-#if defined(USE_CANIF)\r
- const CanIf_ConfigType* CanIfConfig;\r
-#endif\r
-#if defined(USE_COM)\r
- const Com_ConfigType* ComConfig;\r
-#endif\r
-#if defined(USE_PWM)\r
- const Pwm_ConfigType* PwmConfig;\r
-#endif\r
-#if defined(USE_DMA)\r
- const Dma_ConfigType* DmaConfig;\r
-#endif\r
-#if defined(USE_ADC)\r
- const Adc_ConfigType* AdcConfig;\r
-#endif\r
-#if defined(USE_GPT)\r
- const Gpt_ConfigType* GptConfig;\r
-#endif\r
+#if defined(USE_MCU)
+ const Mcu_ConfigType* McuConfig;
+#endif
+#if defined(USE_PORT)
+ const Port_ConfigType* PortConfig;
+#endif
+#if defined(USE_CAN)
+ const Can_ConfigType* CanConfig;
+#endif
+#if defined(USE_CANIF)
+ const CanIf_ConfigType* CanIfConfig;
+#endif
+#if defined(USE_CANSM)
+ const CanSM_ConfigType* CanSMConfig;
+#endif
+#if defined(USE_NM)
+ const Nm_ConfigType* NmConfig;
+#endif
+#if defined(USE_CANNM)
+ const CanNm_ConfigType* CanNmConfig;
+#endif
+#if defined(USE_COMM)
+ const ComM_ConfigType* ComMConfig;
+#endif
+#if defined(USE_COM)
+ const Com_ConfigType* ComConfig;
+#endif
+#if defined(USE_PDUR)
+ const PduR_PBConfigType* PduRConfig;
+#endif
+#if defined(USE_PWM)
+ const Pwm_ConfigType* PwmConfig;
+#endif
+#if defined(USE_DMA)
+ const Dma_ConfigType* DmaConfig;
+#endif
+#if defined(USE_ADC)
+ const Adc_ConfigType* AdcConfig;
+#endif
+#if defined(USE_GPT)
+ const Gpt_ConfigType* GptConfig;
+#endif
+#if defined(USE_FLS)
+ const Fls_ConfigType* FlashConfig;
+#endif
} EcuM_ConfigType;\r
\r
#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Fee (Fee_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 22 09:35:51 CET 2010\r
+ */\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Fee.h"\r
+#include "NvM_Cbk.h"\r
+\r
+const Fee_BlockConfigType BlockConfigList[] = {\r
+};\r
+const Fee_ConfigType Fee_Config = {\r
+ .General = {\r
+ .NvmJobEndCallbackNotificationCallback = NULL,\r
+ .NvmJobErrorCallbackNotificationCallback = NULL,\r
+ },\r
+ .BlockConfig = BlockConfigList,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Fee (Fee_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 22 09:35:51 CET 2010\r
+ */\r
+\r
+
+#warning "This default file may only be used as an example!"\r
+\r
+\r
+#ifndef FEE_CFG_H_\r
+#define FEE_CFG_H_\r
+\r
+#include "MemIf_Types.h"\r
+#include "Fee_ConfigTypes.h"\r
+\r
+#define FEE_DEV_ERROR_DETECT STD_ON\r
+#define FEE_VERSION_INFO_API STD_ON\r
+#define FEE_POLLING_MODE STD_ON\r
+\r
+#define FEE_INDEX 0\r
+#define FEE_VIRTUAL_PAGE_SIZE 16\r
+\r
+#define FEE_NUM_OF_BLOCKS 5\r
+#define FEE_MAX_NUM_SETS 1\r
+\r
+#endif /*FEE_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Fee (Fee_Memory_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.3\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Tue Nov 23 14:44:22 CET 2010\r
+ */\r
+\r
+
+#ifndef FEE_MEMORY_CFG_H_\r
+#define FEE_MEMORY_CFG_H_\r
+\r
+
+#define FEE_BANK1_OFFSET 0x0000\r
+#define FEE_BANK2_OFFSET 0x4000\r
+#define FEE_BANK1_LENGTH 0x4000\r
+#define FEE_BANK2_LENGTH 0x4000\r
+\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef MEMIF_CFG_H_\r
+#define MEMIF_CFG_H_\r
+\r
+#include "MemIf_Types.h"\r
+\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+\r
+\r
+#define MEMIF_VERSION_INFO_API STD_ON // Activate/Deactivate ver info API.\r
+#define MEMIF_DEV_ERROR_DETECT STD_ON // Activate/Deactivate Dev Error Detection and Notification.\r
+\r
+#define MEMIF_NUMBER_OF_DEVICES 1 // Number of underlying memory abstraction modules.\r
+\r
+#if (MEMIF_NUMBER_OF_DEVICES == 1)\r
+#define MEMIF_DEVICE_TO_USE FLS_DRIVER_INDEX\r
+#endif\r
+#endif /*MEMIF_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module NvM (NvM_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 22 09:20:07 CET 2010\r
+ */\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+\r
+#include "NvM.h"\r
+\r
+const NvM_BlockDescriptorType BlockDescriptorList[] = {\r
+};\r
+\r
+const NvM_ConfigType NvM_Config = {\r
+ .Common = {\r
+ .MultiBlockCallback = NULL,\r
+ },\r
+ .BlockDescriptor = BlockDescriptorList, \r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module NvM (NvM_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 22 09:20:07 CET 2010\r
+ */\r
+\r
+
+#warning "This default file may only be used as an example!"\r
+\r
+ \r
+#ifndef NVM_CFG_H_\r
+#define NVM_CFG_H_\r
+\r
+#include "NvM_Types.h"\r
+#include "NvM_ConfigTypes.h"\r
+\r
+#define NVM_DEV_ERROR_DETECT STD_ON\r
+#define NVM_VERSION_INFO_API STD_ON\r
+#define NVM_SET_RAM_BLOCK_STATUS_API STD_OFF\r
+\r
+#define NVM_API_CONFIG_CLASS NVM_API_CONFIG_CLASS_1 // Class 1-3\r
+#define NVM_COMPILED_CONFIG_ID 0 // 0..65535\r
+#define NVM_CRC_NUM_OF_BYTES 0 // 1..65535\r
+#define NVM_DATASET_SELECTION_BITS 0 // 0..8\r
+#define NVM_DRV_MODE_SWITCH STD_OFF // OFF = SLOW, ON = FAST\r
+#define NVM_DYNAMIC_CONFIGURATION STD_OFF // OFF..ON\r
+#define NVM_JOB_PRIORIZATION STD_OFF // OFF..ON\r
+#define NVM_MAX_NUMBER_OF_WRITE_RETRIES 2 // 0..7\r
+#define NVM_POLLING_MODE STD_OFF // OFF..ON\r
+#define NVM_SIZE_IMMEDIATE_JOB_QUEUE 0 // 1..255\r
+#define NVM_SIZE_STANDARD_JOB_QUEUE 0 // 1..255\r
+\r
+#define NVM_NUM_OF_NVRAM_BLOCKS 0\r
+\r
+\r
+#endif /*NVM_CFG_H_*/\r
--- /dev/null
+\r
+Elmicro Card12 HC12 Controller Module with MC9S12DP512\r
+\r
+ http://elmicro.com/en/card12.html\r
+\r
+MC9S12DP512 Microcontroller Info:\r
+ MC9S12DP512 MCU with LQFP112 package\r
+ 512 KB Flash\r
+ 4 KB EEPROM\r
+ 14 KB RAM\r
+ 3x SPI\r
+ 2x SCI\r
+ 5x CAN\r
+ Enhanced Capture Timer\r
+ 8 Channel PWM\r
+ 16 Channel 10 Bit A/D-Converter\r
+ \r
+ \r
+Board Features:\r
+ 16 MHz Quarz Clock (8 MHz System Clock)\r
+ RS232 Ports with Transceiver MAX232A\r
+ PCA82C251 CAN Physical Interface\r
+ Special Reset Controller\r
+ Reset Switch\r
+ LED\r
+ BDM (Background Debug Mode) connector\r
+ All controller pins are available at two double row headers\r
+ 5V power supply\r
-\r
-# ARCH defines\r
-ARCH=hcs12d\r
-ARCH_FAM=hc1x\r
-ARCH_MCU=MC912DG128A\r
-\r
-# CFG (y/n) macros (These become CFG_XXX=y and def-y += CFG_XXX ) \r
-CFG=HC1X HCS12D MC912DG128A BRD_HCS12_ELMICRO_CARD12 SIMULATOR\r
-\r
-# What buildable modules does this board have, \r
-# default or private (These become MOD_XXX=y )\r
-MOD_AVAIL=KERNEL MCU GPT\r
-\r
-# Needed by us (These become USE_XXX=y and def-y += USE_XXX )\r
-MOD_USE=KERNEL MCU\r
-\r
+
+# ARCH defines
+ARCH=hcs12d
+ARCH_FAM=hc1x
+ARCH_MCU=MC912DG128A
+
+# CFG (y/n) macros (These become CFG_XXX=y and def-y += CFG_XXX )
+CFG=HC1X HCS12D MC912DG128A BRD_HCS12_ELMICRO_CARD12 SIMULATOR
+
+# What buildable modules does this board have,
+# default or private (These become MOD_XXX=y )
+MOD_AVAIL+=MCU GPT PORT DIO CAN ADC PWM
+# System + Communication + Diagnostic
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE
+# Additional
+MOD_AVAIL+=RAMLOG
+
+
+# Needed by us (These become USE_XXX=y and def-y += USE_XXX )
+MOD_USE=KERNEL MCU
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.c\r
+ *\r
+ * Created on: 2010-apr-24\r
+ * Author: Jonte\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Adc.h"\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+void Adc_Group0Notification (void);\r
+void Adc_Group1Notification (void);\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration[] =\r
+{\r
+ {\r
+ .convTime = ADC_CONVERSION_TIME_8_CLOCKS,\r
+ .resolution = ADC_RESOLUTION_10_BIT,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ },\r
+};\r
+\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_GROUP0_CHANNELS] =\r
+{\r
+ ADC_CH1,ADC_CH2,ADC_CH3,ADC_CH4\r
+};\r
+const Adc_ChannelType Adc_Group1ChannelList[ADC_NBR_OF_GROUP1_CHANNELS] =\r
+{\r
+ ADC_CH5,ADC_CH6,\r
+};\r
+\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+Adc_ValueGroupType Adc_Group1Buffer [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ {\r
+ .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ .groupCallback = Adc_Group0Notification,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .numberOfChannels = sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0],\r
+ },\r
+ {\r
+ .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ .groupCallback = Adc_Group1Notification,\r
+ .channelList = Adc_Group1ChannelList,\r
+ .resultBuffer = Adc_Group1Buffer,\r
+ .numberOfChannels = sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group0ChannelList[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP1],\r
+ },\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig[] =\r
+{\r
+ {\r
+ .hwConfigPtr = AdcHWUnitConfiguration,\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ }\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.h\r
+ *\r
+ * Created on: 2010-apr-24\r
+ * Author: Jonte\r
+ */\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_NOF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_4_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_16_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+typedef enum\r
+{\r
+ ADC_RESOLUTION_10_BIT,\r
+ ADC_RESOLUTION_8_BIT,\r
+}Adc_ResolutionType;\r
+\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINUOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+typedef struct\r
+{\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ void (*groupCallback)(void);\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+} Adc_GroupDefType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_POT1,\r
+ ADC_TEST_BOARD_POT2,\r
+ ADC_TEST_BOARD_POT3,\r
+ ADC_TEST_BOARD_POT4,\r
+ ADC_NBR_OF_GROUP0_CHANNELS,\r
+}Adc_Group0SignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_POT5,\r
+ ADC_TEST_BOARD_POT6,\r
+ ADC_NBR_OF_GROUP1_CHANNELS,\r
+}Adc_Group1SignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_GROUP1,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType convTime;\r
+ Adc_ResolutionType resolution;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig[];\r
+\r
+\r
+#endif /*ADC_CFG_H_*/\r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
--- /dev/null
+/* \r
+* Configuration of module Can (Can_Cfg.h)\r
+* \r
+* Created by: \r
+* Configured for (MCU): MPC551x\r
+* \r
+* Module editor vendor: ArcCore\r
+* Module editor version: 2.0.0\r
+* \r
+* \r
+* Generated by Arctic Studio (http://arccore.com)\r
+* on Wed Apr 21 10:15:00 CEST 2010\r
+*/\r
+\r
+\r
+#if (CAN_SW_MAJOR_VERSION != 1) \r
+#error "Can: Configuration file version differs from BSW version."\r
+#endif\r
+\r
+ \r
+\r
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_CTRL_0 = 0,\r
+ CAN_CTRL_1 = 1,\r
+ CAN_CTRL_2 = 2,\r
+ CAN_CTRL_3 = 3,\r
+ CAN_CTRL_4 = 4,\r
+ CAN_CONTROLLER_CNT = 5\r
+}CanControllerIdType;\r
+// End mc9s12 unique\r
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_2,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_1,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+\r
+/** Type for Can id filter mask */\r
+typedef struct\r
+{\r
+ uint8 idmr[8]; // Identifier Mask Register, 1 = ignore corresponding acceptance code register bit\r
+ uint8 idar[8]; // Identifier Acceptance Register\r
+ Can_Arc_IDAMType idam;\r
+}Can_FilterMaskType;\r
+// End mc9s12 unique\r
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
+\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/* \r
+* Configuration of module Can (Can_Lcfg.c)\r
+* \r
+* Created by: \r
+* Configured for (MCU): MPC551x\r
+* \r
+* Module editor vendor: ArcCore\r
+* Module editor version: 2.0.0\r
+* \r
+* \r
+* Generated by Arctic Studio (http://arccore.com)\r
+* on Wed Apr 21 10:15:00 CEST 2010\r
+*/\r
+\r
+#warning "This default file may only be used as an example!"\r
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+\r
+// Start mc9s12 unique\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_Mask_1[] = {\r
+ {\r
+ {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff},\r
+ {0,0,0,0,0,0,0,0},\r
+ CAN_ARC_IDAM_2_32BIT\r
+ },\r
+ {\r
+ {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff},\r
+ {0,0,0,0,0,0,0,0},\r
+ CAN_ARC_IDAM_2_32BIT\r
+ },\r
+};\r
+// End mc9s12 unique\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
+ {\r
+ .CanObjectId = HWObj_1,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = HWObj_2,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_0,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
\r
\r
/*\r
- * test_framework.h\r
+ * ComGlobals.h\r
*\r
- * Created on: 23 aug 2009\r
- * Author: mahi\r
+ * Created on: 2009-jan-11\r
+ * Author: Mattias\r
*/\r
\r
-#ifndef TEST_FRAMEWORK_H_\r
-#define TEST_FRAMEWORK_H_\r
+#ifndef COMGLOBALS_H_\r
+#define COMGLOBALS_H_\r
\r
-void test_done( void );\r
+#warning "This default file may only be used as an example!"\r
\r
-void test_fail( char *text,char *file, int line , const char *function );\r
-void test_ok( void );\r
+// PDU definitions\r
+enum {\r
+ // Used for PCAN.\r
+ PCAN_RX_FRAME_1 = 0,\r
+ PCAN_RX_FRAME_2 = 2,\r
+ PCAN_TX_FRAME_1 = 3,\r
+ PCAN_TX_FRAME_2 = 4,\r
\r
-#endif /* TEST_FRAMEWORK_H_ */\r
+ // Used for hardware test.\r
+ PDU_MSG_HARDWARE_TEST_ENGINE_STATUS = 0,\r
+ PDU_MSG_HARDWARE_TEST_ENGINE_CONTROL = 1,\r
+ PDU_MSG_HARDWARE_TEST_ROUTED_MSG = 2,\r
+\r
+ // Used for testing CanIf\r
+ PDU_MSG_RX234 = 8,\r
+ PDU_MSG_RX123 = 10,\r
+ PDU_MSG_TX789 = 9,\r
+ PDU_MSG_TX987 = 11\r
+\r
+};\r
+\r
+\r
+#endif /* COMGLOBALS_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+/** @addtogroup Dio DIO Driver\r
+ * @{ */\r
+\r
+/** @file Dio_Cfg.h\r
+ * Definitions of configuration parameters for the DIO Driver.\r
+ */\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+#define DIO_END_OF_LIST -1\r
+\r
+/** HW specific DIO port definitions. */\r
+/** @req DIO018 */\r
+/** @req DIO020 */\r
+typedef enum\r
+{\r
+ DIO_PORT_A = 0,\r
+ DIO_PORT_B,\r
+ DIO_PORT_E,\r
+ DIO_PORT_H,\r
+ DIO_PORT_J,\r
+ DIO_PORT_K,\r
+ DIO_PORT_M,\r
+ DIO_PORT_P,\r
+ DIO_PORT_S,\r
+ DIO_PORT_T\r
+} Dio_PortTypesType;\r
+\r
+/** @name DIO channels\r
+ * HW specific dio channels.\r
+ */\r
+// Pin Name GPIO(PCR)Num\r
+//@{\r
+//* req DIO015 */\r
+//* req DIO017 */\r
+typedef enum\r
+{\r
+ DIO_CHANNEL_A0,\r
+ DIO_CHANNEL_A1,\r
+ DIO_CHANNEL_A2,\r
+ DIO_CHANNEL_A3,\r
+ DIO_CHANNEL_A4,\r
+ DIO_CHANNEL_A5,\r
+ DIO_CHANNEL_A6,\r
+ DIO_CHANNEL_A7,\r
+\r
+ DIO_CHANNEL_B0,\r
+ DIO_CHANNEL_B1,\r
+ DIO_CHANNEL_B2,\r
+ DIO_CHANNEL_B3,\r
+ DIO_CHANNEL_B4,\r
+ DIO_CHANNEL_B5,\r
+ DIO_CHANNEL_B6,\r
+ DIO_CHANNEL_B7,\r
+\r
+ DIO_CHANNEL_E0,\r
+ DIO_CHANNEL_E1,\r
+ DIO_CHANNEL_E2,\r
+ DIO_CHANNEL_E3,\r
+ DIO_CHANNEL_E4,\r
+ DIO_CHANNEL_E5,\r
+ DIO_CHANNEL_E6,\r
+ DIO_CHANNEL_E7,\r
+\r
+ DIO_CHANNEL_H0,\r
+ DIO_CHANNEL_H1,\r
+ DIO_CHANNEL_H2,\r
+ DIO_CHANNEL_H3,\r
+ DIO_CHANNEL_H4,\r
+ DIO_CHANNEL_H5,\r
+ DIO_CHANNEL_H6,\r
+ DIO_CHANNEL_H7,\r
+\r
+ DIO_CHANNEL_J0,\r
+ DIO_CHANNEL_J1,\r
+ DIO_CHANNEL_J2,\r
+ DIO_CHANNEL_J3,\r
+ DIO_CHANNEL_J4,\r
+ DIO_CHANNEL_J5,\r
+ DIO_CHANNEL_J6,\r
+ DIO_CHANNEL_J7,\r
+\r
+ DIO_CHANNEL_K0,\r
+ DIO_CHANNEL_K1,\r
+ DIO_CHANNEL_K2,\r
+ DIO_CHANNEL_K3,\r
+ DIO_CHANNEL_K4,\r
+ DIO_CHANNEL_K5,\r
+ DIO_CHANNEL_K6,\r
+ DIO_CHANNEL_K7,\r
+\r
+ DIO_CHANNEL_M0,\r
+ DIO_CHANNEL_M1,\r
+ DIO_CHANNEL_M2,\r
+ DIO_CHANNEL_M3,\r
+ DIO_CHANNEL_M4,\r
+ DIO_CHANNEL_M5,\r
+ DIO_CHANNEL_M6,\r
+ DIO_CHANNEL_M7,\r
+\r
+ DIO_CHANNEL_P0,\r
+ DIO_CHANNEL_P1,\r
+ DIO_CHANNEL_P2,\r
+ DIO_CHANNEL_P3,\r
+ DIO_CHANNEL_P4,\r
+ DIO_CHANNEL_P5,\r
+ DIO_CHANNEL_P6,\r
+ DIO_CHANNEL_P7,\r
+\r
+ DIO_CHANNEL_S0,\r
+ DIO_CHANNEL_S1,\r
+ DIO_CHANNEL_S2,\r
+ DIO_CHANNEL_S3,\r
+ DIO_CHANNEL_S4,\r
+ DIO_CHANNEL_S5,\r
+ DIO_CHANNEL_S6,\r
+ DIO_CHANNEL_S7,\r
+\r
+ DIO_CHANNEL_T0,\r
+ DIO_CHANNEL_T1,\r
+ DIO_CHANNEL_T2,\r
+ DIO_CHANNEL_T3,\r
+ DIO_CHANNEL_T4,\r
+ DIO_CHANNEL_T5,\r
+ DIO_CHANNEL_T6,\r
+ DIO_CHANNEL_T7\r
+} Dio_ChannelTypesType;\r
+//@}\r
+\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL (DIO_CHANNEL_H7)\r
+\r
+// Standard board test led\r
+#define DIO_CHANNEL_NAME_BOARD_LED DIO_CHANNEL_NAME_LED_CHANNEL\r
+\r
+#define DIO_PORT_NAME_LED_PORT (DIO_PORT_H)\r
+\r
+#define DIO_GROUP_NAME_LED_PORT (&DioConfigData[0])\r
+\r
+// Channels\r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+\r
+\r
+#endif /*DIO_CFG_H_*/\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
-/** @addtogroup EcuM ECU State Manager\r
- * @{ */\r
+#warning "This default file may only be used as an example!"\r
\r
-/** @file EcuM_Cfg.h\r
- * Definitions of configuration parameters for ECU State Manager.\r
- * Initialization sequences are defined in EcuM_Callout_template.c\r
- */\r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
+const Dio_ChannelType DioChannelConfigData[] =\r
+{\r
+ DIO_CHANNEL_NAME_LED_CHANNEL,\r
+ DIO_END_OF_LIST,\r
+};\r
\r
-/** Build version info API */\r
-#define ECUM_VERSION_INFO_API STD_ON\r
-/** Using NVRAM Manager */\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-/** Enable Development Error Trace */\r
-#define ECUM_DEV_ERROR_DETECT STD_ON\r
+const Dio_PortType DioPortConfigData[] =\r
+{\r
+ DIO_PORT_NAME_LED_PORT,\r
+ DIO_END_OF_LIST\r
+};\r
\r
-#include "EcuM_Generated_Types.h"\r
+const Dio_ChannelGroupType DioConfigData[] =\r
+{\r
+ { .port = DIO_PORT_H, .offset = 7, .mask = 0x80, },\r
+ { .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
+};\r
\r
-#endif /*ECUM_CFG_H_*/\r
-/** @} */\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
\r
\r
#include "Gpt.h"\r
\r
#ifndef GPT_CFG_H_\r
#define GPT_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Std_Types.h"\r
\r
\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include <stdint.h>\r
#include "Mcu.h"\r
\r
#ifndef MCU_CFG_H_\r
#define MCU_CFG_H_\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#define MCU_DEV_ERROR_DETECT STD_ON\r
#define MCU_PERFORM_RESET_API STD_OFF\r
#define MCU_VERSION_INFO_API STD_ON\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Port.h"\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .corePullUpRegister = 0x90,\r
+ .coreReducedDriveRegister = 0x00,\r
+ .modeRoutingRegister = 0x00,\r
+\r
+ #if ( PORTA_CONFIGURABLE == STD_ON )\r
+ .portADirection = 0x00,\r
+ .portAOutValue = 0x00,\r
+ .portAMask = 0xFF,\r
+ #endif\r
+\r
+ #if ( PORTB_CONFIGURABLE == STD_ON )\r
+ .portBDirection 0x00,\r
+ .portBOutValue 0x00,\r
+ .portBMask = 0xFF,\r
+ #endif\r
+\r
+ #if ( PORTE_CONFIGURABLE == STD_ON )\r
+ .portEDirection = 0x00,\r
+ .portEOutValue = 0x00,\r
+ .portEMask = 0xFF,\r
+ #endif\r
+\r
+ #if ( PORTK_CONFIGURABLE == STD_ON )\r
+ .portKDirection = 0x00,\r
+ .portKOutValue = 0x00,\r
+ .portKMask = 0xFF,\r
+ #endif\r
+\r
+ #if ( PORTH_CONFIGURABLE == STD_ON )\r
+ .portHDirection = 0x80,\r
+ .portHOutValue = 0x00,\r
+ .portHMask = 0xFF,\r
+ .portHPullEnableRegister = 0x00,\r
+ .portHPullPolarityRegsiter = 0x00,\r
+ .portHReducedDriveRegister = 0x00,\r
+ #endif\r
+\r
+ #if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ .portJDirection = 0x00,\r
+ .portJOutValue = 0x00,\r
+ .portJMask = 0xFF,\r
+ .portJPullEnableRegister = 0xC3,\r
+ .portJPullPolarityRegsiter 0x00,\r
+ .portJReducedDriveRegister = 0x00,\r
+ #endif\r
+\r
+ #if ( PORTM_CONFIGURABLE == STD_ON )\r
+ .portMDirection = 0x00,\r
+ .portMOutValue = 0x00,\r
+ .portMMask = 0xFF,\r
+ .portMPullEnableRegister = 0x00,\r
+ .portMPullPolarityRegsiter = 0x00,\r
+ .portMWiredModeRegsiter = 0x00,\r
+ .portMReducedDriveRegister = 0x00,\r
+ #endif\r
+\r
+ #if ( PORTP_CONFIGURABLE == STD_ON )\r
+ .portPDirection = 0x00,\r
+ .portPOutValue = 0x00,\r
+ .portPMask = 0xFF,\r
+ .portPPullEnableRegister = 0x00,\r
+ .portPPullPolarityRegsiter = 0x00,\r
+ .portPReducedDriveRegister = 0x00,\r
+ #endif\r
+\r
+ #if ( PORTS_CONFIGURABLE == STD_ON )\r
+ .portSDirection = 0x00,\r
+ .portSOutValue = 0x00,\r
+ .portSMask = 0xFF,\r
+ .portSPullEnableRegister = 0xFF,\r
+ .portSPullPolarityRegsiter = 0x00,\r
+ .portSWiredModeRegsiter = 0x00,\r
+ .portSReducedDriveRegister = 0x00,\r
+ #endif\r
+\r
+ #if ( PORTT_CONFIGURABLE == STD_ON )\r
+ .portTDirection = 0x00,\r
+ .portTOutValue = 0x00,\r
+ .portTMask = 0xFF,\r
+ .portTPullEnableRegister = 0x00,\r
+ .portTPullPolarityRegsiter = 0x00,\r
+ .portTReducedDriveRegister = 0x00,\r
+ #endif\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Std_Types.h"\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
+/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+\r
+/** Parameter to enable/disable configuration on a port */\r
+#define PORTA_CONFIGURABLE STD_OFF\r
+#define PORTB_CONFIGURABLE STD_OFF\r
+#define PORTE_CONFIGURABLE STD_OFF\r
+#define PORTK_CONFIGURABLE STD_OFF\r
+#define PORTH_CONFIGURABLE STD_ON\r
+#define PORTJ_CONFIGURABLE STD_OFF\r
+#define PORTM_CONFIGURABLE STD_OFF\r
+#define PORTP_CONFIGURABLE STD_OFF\r
+#define PORTS_CONFIGURABLE STD_OFF\r
+#define PORTT_CONFIGURABLE STD_OFF\r
+\r
+#define PORT_A_BASE 0x0100\r
+#define PORT_B_BASE 0x0200\r
+#define PORT_E_BASE 0x0300\r
+#define PORT_K_BASE 0x0400\r
+#define PORT_H_BASE 0x0500\r
+#define PORT_J_BASE 0x0600\r
+#define PORT_M_BASE 0x0700\r
+#define PORT_P_BASE 0x0800\r
+#define PORT_S_BASE 0x0900\r
+#define PORT_T_BASE 0x0A00\r
+#define PORT_BITMASK 0x00FF\r
+#define PORT_BASEMASK 0xFF00;\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum\r
+{\r
+ PORT_PA0 = PORT_A_BASE,\r
+ PORT_PA1,\r
+ PORT_PA2,\r
+ PORT_PA3,\r
+ PORT_PA4,\r
+ PORT_PA5,\r
+ PORT_PA6,\r
+ PORT_PA7,\r
+ PORT_PB0 = PORT_B_BASE,\r
+ PORT_PB1,\r
+ PORT_PB2,\r
+ PORT_PB3,\r
+ PORT_PB4,\r
+ PORT_PB5,\r
+ PORT_PB6,\r
+ PORT_PB7,\r
+ PORT_PE0 = PORT_E_BASE,\r
+ PORT_PE1,\r
+ PORT_PE2,\r
+ PORT_PE3,\r
+ PORT_PE4,\r
+ PORT_PE5,\r
+ PORT_PE6,\r
+ PORT_PE7,\r
+ PORT_PH0 = PORT_H_BASE,\r
+ PORT_PH1,\r
+ PORT_PH2,\r
+ PORT_PH3,\r
+ PORT_PH4,\r
+ PORT_PH5,\r
+ PORT_PH6,\r
+ PORT_PH7,\r
+ PORT_PJ0 = PORT_J_BASE,\r
+ PORT_PJ1,\r
+ PORT_PJ2,\r
+ PORT_PJ3,\r
+ PORT_PJ4,\r
+ PORT_PJ5,\r
+ PORT_PJ6,\r
+ PORT_PJ7,\r
+ PORT_PK0 = PORT_K_BASE,\r
+ PORT_PK1,\r
+ PORT_PK2,\r
+ PORT_PK3,\r
+ PORT_PK4,\r
+ PORT_PK5,\r
+ PORT_PK6,\r
+ PORT_PK7,\r
+ PORT_PM0 = PORT_M_BASE,\r
+ PORT_PM1,\r
+ PORT_PM2,\r
+ PORT_PM3,\r
+ PORT_PM4,\r
+ PORT_PM5,\r
+ PORT_PM6,\r
+ PORT_PM7,\r
+ PORT_PP0 = PORT_P_BASE,\r
+ PORT_PP1,\r
+ PORT_PP2,\r
+ PORT_PP3,\r
+ PORT_PP4,\r
+ PORT_PP5,\r
+ PORT_PP6,\r
+ PORT_PP7,\r
+ PORT_PS0 = PORT_S_BASE,\r
+ PORT_PS1,\r
+ PORT_PS2,\r
+ PORT_PS3,\r
+ PORT_PS4,\r
+ PORT_PS5,\r
+ PORT_PS6,\r
+ PORT_PS7,\r
+ PORT_PT0 = PORT_T_BASE,\r
+ PORT_PT1,\r
+ PORT_PT2,\r
+ PORT_PT3,\r
+ PORT_PT4,\r
+ PORT_PT5,\r
+ PORT_PT6,\r
+ PORT_PT7,\r
+} Port_PinType;\r
+\r
+/** @req PORT124 */\r
+//typedef uint8 Port_PinModeType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct\r
+{\r
+ const uint8_t corePullUpRegister; // PUCR\r
+ const uint8_t coreReducedDriveRegister; // RDRIV\r
+ const uint8_t modeRoutingRegister; // MODRR\r
+\r
+ /**\r
+ * Every port has:\r
+ * a direction (input or output)\r
+ * a default out value\r
+ * a mask that is 0 if the direction is allowed to change during runtime\r
+ *\r
+ * Some ports have:\r
+ * a reduced drive conf (power saving)\r
+ * a pull enable conf (enable pull-up/pull-down\r
+ * a pull direction conf (pull-up or pull-down)\r
+ * a wired mode (enable open drain outputs)\r
+ */\r
+#if ( PORTA_CONFIGURABLE == STD_ON )\r
+ const uint8_t portADirection;\r
+ const uint8_t portAOutValue;\r
+ const uint8_t portAMask;\r
+#endif\r
+\r
+#if ( PORTB_CONFIGURABLE == STD_ON )\r
+ const uint8_t portBDirection;\r
+ const uint8_t portBOutValue;\r
+ const uint8_t portBMask;\r
+#endif\r
+\r
+#if ( PORTE_CONFIGURABLE == STD_ON )\r
+ const uint8_t portEDirection;\r
+ const uint8_t portEOutValue;\r
+ const uint8_t portEMask;\r
+#endif\r
+\r
+#if ( PORTK_CONFIGURABLE == STD_ON )\r
+ const uint8_t portKDirection;\r
+ const uint8_t portKOutValue;\r
+ const uint8_t portKMask;\r
+#endif\r
+\r
+#if ( PORTH_CONFIGURABLE == STD_ON )\r
+ const uint8_t portHDirection;\r
+ const uint8_t portHOutValue;\r
+ const uint8_t portHMask;\r
+ const uint8_t portHPullEnableRegister;\r
+ const uint8_t portHPullPolarityRegsiter;\r
+ const uint8_t portHReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ const uint8_t portJDirection;\r
+ const uint8_t portJOutValue;\r
+ const uint8_t portJMask;\r
+ const uint8_t portJPullEnableRegister;\r
+ const uint8_t portJPullPolarityRegsiter;\r
+ const uint8_t portJReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTM_CONFIGURABLE == STD_ON )\r
+ const uint8_t portMDirection;\r
+ const uint8_t portMOutValue;\r
+ const uint8_t portMMask;\r
+ const uint8_t portMPullEnableRegister;\r
+ const uint8_t portMPullPolarityRegsiter;\r
+ const uint8_t portMWiredModeRegsiter;\r
+ const uint8_t portMReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTP_CONFIGURABLE == STD_ON )\r
+ const uint8_t portPDirection;\r
+ const uint8_t portPOutValue;\r
+ const uint8_t portPMask;\r
+ const uint8_t portPPullEnableRegister;\r
+ const uint8_t portPPullPolarityRegsiter;\r
+ const uint8_t portPReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTS_CONFIGURABLE == STD_ON )\r
+ const uint8_t portSDirection;\r
+ const uint8_t portSOutValue;\r
+ const uint8_t portSMask;\r
+ const uint8_t portSPullEnableRegister;\r
+ const uint8_t portSPullPolarityRegsiter;\r
+ const uint8_t portSWiredModeRegsiter;\r
+ const uint8_t portSReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTT_CONFIGURABLE == STD_ON )\r
+ const uint8_t portTDirection;\r
+ const uint8_t portTOutValue;\r
+ const uint8_t portTMask;\r
+ const uint8_t portTPullEnableRegister;\r
+ const uint8_t portTPullPolarityRegsiter;\r
+ const uint8_t portTReducedDriveRegister;\r
+#endif\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+\r
+\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+\r
+\r
+\r
/*\r
- * Tests:\r
+ * Pwm_Cfg.c\r
*\r
- * OSEK constants\r
- * - OSMAXALLOWEDVALUE_x\r
- * - OSTICKSPERBASE_x\r
- * - OSMINCYCLE_x\r
- * - OSMAXALLOWEDVALUE\r
- * - OSTICKSPERBASE\r
- * - OSMINCYCLE\r
- * - OSTICKDURATION\r
- *\r
- * - INVALID_TASK\r
- *\r
- * - OSDEFAULTAPPMODE\r
- *\r
- * - OSServiceId_xx\r
- * - OSErrorGetServiceId\r
- * - OSError_x1_x2\r
- *\r
- * Autosar constants\r
- *\r
- * More tests here:\r
- *\r
- * Limitations:\r
+ * Author: jonte\r
*/\r
\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+const Pwm_ConfigType PwmConfig =\r
+{\r
+ .channels = {\r
+ {\r
+ .channel = PWM_CHANNEL_1,\r
+ DUTY_AND_PERIOD(0x6000,100),\r
+ .centerAlign = 0,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = 0,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD,\r
+ },\r
+ {\r
+ .channel = PWM_CHANNEL_2,\r
+ DUTY_AND_PERIOD(0x1000,100),\r
+ .centerAlign = 0,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = 1,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD,\r
+ },\r
+ },\r
+ .busPrescalerA = PRESCALER_128,\r
+ .busPrescalerB = PRESCALER_8,\r
+ .prescalerA = 1,\r
+ .prescalerB = 1,\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Pwm PWM Driver\r
+ * @{ */\r
+\r
+/** @file Pwm_Cfg.h\r
+ * Definitions of configuration parameters for PWM Driver.\r
+ */\r
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+/*\r
+ * PwmGeneral\r
+ */\r
+\r
+/*\r
+ * PWM003: The detection of development errors is configurable (ON/OFF) at\r
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
+ * the detection of all development errors\r
+ */\r
+/** Enable Development Error Trace */\r
+#define PWM_DEV_ERROR_DETECT STD_ON\r
+/** Build GetOutputState()\r
+ * Note: Not supported since pwm module doesn't support reading output.\r
+ */\r
+#define PWM_GET_OUTPUT_STATE STD_OFF\r
+/** Determines if module is configurable at runtime */\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+/** Use notifications\r
+ * Note: Only OFF mode available due to hw limitations.\r
+ */\r
+#define PWM_NOTIFICATION_SUPPORTED STD_OFF\r
+/** Build period and duty API */\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+\r
+/**\r
+ * Setting to ON freezes the current output state of a PWM channel when in\r
+ * debug mode.\r
+ */\r
+#define PWM_FREEZE_ENABLE STD_ON\r
+\r
+/**\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/**\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == channel id.\r
+ */\r
+typedef uint8 Pwm_ChannelType;\r
+\r
+/**\r
+ * PWM070: All time units used within the API services of the PWM module shall\r
+ * be of the unit ticks.\r
+ */\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_1 = 0,\r
+ PWM_CHANNEL_2 = 7,\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+/* 1 =PWMchannel output is high at the beginning of the period, then goes low when the duty count\r
+is reached. */\r
+#define POLARITY_NORMAL 1\r
+#define POLARITY_INVERSED 0\r
+\r
+/**\r
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,\r
+ * the following macro can be used to convert between that format and the\r
+ * driver format.\r
+ */\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (uint8)((uint32)((uint32)_duty*(uint32)_period)>>15), .period = _period\r
+\r
+\r
+typedef struct {\r
+ /** Number of duty ticks */\r
+ uint8_t duty;\r
+ /** Length of period, in ticks */\r
+ uint8_t period;\r
+ /** Center or left align */\r
+ uint8_t centerAlign:1;\r
+ /** Polarity of the channel */\r
+ uint8_t polarity:1;\r
+ /** Scaled clock enabled */\r
+ uint8_t scaledClockEnable:1;\r
+ /** idle state */\r
+ uint8_t idleState:1;\r
+\r
+ uint8_t reserved:4;\r
+\r
+ Pwm_ChannelClassType class;\r
+\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+typedef enum{\r
+ PRESCALER_1 = 0,\r
+ PRESCALER_2 = 1,\r
+ PRESCALER_4 = 2,\r
+ PRESCALER_8 = 3,\r
+ PRESCALER_16 = 4,\r
+ PRESCALER_32 = 5,\r
+ PRESCALER_64 = 6,\r
+ PRESCALER_128 = 7,\r
+}Pwm_PrescalerType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType channels[PWM_NUMBER_OF_CHANNELS];\r
+ Pwm_PrescalerType busPrescalerA;\r
+ Pwm_PrescalerType busPrescalerB;\r
+ uint8_t prescalerA;\r
+ uint8_t prescalerB;\r
+} Pwm_ConfigType;\r
+\r
+#endif\r
+/** @} */\r
--- /dev/null
+\r
+\r
+/* The board Elmicro Card12 comes with MC912D60A or MC912DG128A.\r
+ * This memory mapping is for MC9S12DG128 but is also compatible \r
+ * with MC912D60A (which has more memory).\r
+ */\r
+ \r
+page0 (rwx) : ORIGIN = 0x0, LENGTH = 256\r
+\r
+/* RAM */\r
+data (rwx) : ORIGIN = 0x1000, LENGTH = 12k\r
+\r
+eeprom (rx): ORIGIN = 0x0400, LENGTH = 3k\r
+text (rx) : ORIGIN = 0x4000, LENGTH = 48k\r
+ \r
+/* high fixed bank, reserve 0x100 vectors and security. */\r
+text_h (rx) : ORIGIN = 0xc002, LENGTH = 16k-0x102\r
+vectors (rx) : ORIGIN = 0xff80, LENGTH = 0x80\r
+ \r
+/* Flash memory banks VMA:s */\r
+bank_A (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+bank_B (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+bank_C (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+bank_D (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+bank_E (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+bank_F (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+ \r
+bank_FIX1 (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+bank_FIX2 (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
+ \r
+/* Flash memory banks LMA:s */\r
+/* iSystem winIDEA */\r
+bank_A_lma (rx) : ORIGIN = 0x0f0000, LENGTH = 16k\r
+bank_B_lma (rx) : ORIGIN = 0x0f4000, LENGTH = 16k\r
+bank_C_lma (rx) : ORIGIN = 0x0f8000, LENGTH = 16k\r
+bank_D_lma (rx) : ORIGIN = 0x0fc000, LENGTH = 16k\r
+bank_E_lma (rx) : ORIGIN = 0x100000, LENGTH = 16k\r
+bank_F_lma (rx) : ORIGIN = 0x104000, LENGTH = 16k\r
+\r
+bank_FIX1_lma (rx) : ORIGIN = 0x108000, LENGTH = 16k\r
+bank_FIX2_lma (rx) : ORIGIN = 0x10c002, LENGTH = 16k-0x102\r
+vectors_lma (rx) : ORIGIN = 0x10ff80, LENGTH = 0x80\r
+ \r
+/* Freescale Codewarrior Hiwave (s19, TBDML)\r
+bank_A_lma (rx) : ORIGIN = 0x388000, LENGTH = 16k\r
+bank_B_lma (rx) : ORIGIN = 0x398000, LENGTH = 16k\r
+bank_C_lma (rx) : ORIGIN = 0x3a8000, LENGTH = 16k\r
+bank_D_lma (rx) : ORIGIN = 0x3b8000, LENGTH = 16k\r
+bank_E_lma (rx) : ORIGIN = 0x3c8000, LENGTH = 16k\r
+bank_F_lma (rx) : ORIGIN = 0x3d8000, LENGTH = 16k\r
+\r
+bank_FIX1_lma (rx) : ORIGIN = 0x3e8000, LENGTH = 16k\r
+bank_FIX2_lma (rx) : ORIGIN = 0x3f8002, LENGTH = 16k-0x102\r
+vectors_lma (rx) : ORIGIN = 0x3fff80, LENGTH = 0x80\r
+*/\r
--- /dev/null
+\r
+Elmicro T-board HC12X Controller Module with MC9SX12DP512\r
+\r
+http://elmicro.com/en/hcs12tb.html#s12x\r
+\r
+MC9SX12DP512 Microcontroller Info:\r
+ MC9SX12DP512 MCU with LQFP112 package\r
+ 512 KB Flash\r
+ 4 KB EEPROM\r
+ 14 KB RAM\r
+ 3x SPI\r
+ 2x SCI\r
+ 5x CAN\r
+ Enhanced Capture Timer\r
+ 8 Channel PWM\r
+ 16 Channel 10 Bit A/D-Converter\r
+ \r
+ \r
+Board Features:\r
+ 16 MHz Quarz Clock (8 MHz System Clock)\r
+ Two RS232 Ports with Transceiver MAX232A\r
+ PCA82C251 CAN Physical Interface\r
+ Special Reset Controller\r
+ Reset Switch\r
+ LED, DIP and Potentiomer I/O\r
+ Operating Mode selectable via jumpers\r
+ BDM (Background Debug Mode) connector\r
+ All controller pins are available at two double row headers\r
+ 5V power supply\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=hcs12d\r
+ARCH_FAM=hc1x\r
+ARCH_MCU=MC912DG128A\r
+\r
+# CFG (y/n) macros (These become CFG_XXX=y and def-y += CFG_XXX ) \r
+CFG=HC1X HCS12XD MC912XDP512 BRD_HCS12X_ELMICRO_TBOARD SIMULATOR\r
+\r
+# What buildable modules does this board have, \r
+# default or private (These become MOD_XXX=y )\r
+MOD_AVAIL+=KERNEL MCU GPT DIO PORT COM CAN CANIF PWM ADC DEM DCM PDUR COMM NM CANNM CANSM CANTP RTE IOHWAB DET ECUM RAMLOG\r
+\r
+# Needed by us (These become USE_XXX=y and def-y += USE_XXX )\r
+MOD_USE=KERNEL MCU\r
--- /dev/null
+/*\r
+ * Configuration of module Adc (Adc_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 10:10:57 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Adc.h"\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+void Adc_ATDCallback (void);\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration[] =\r
+{\r
+ {\r
+ .convTime = ADC_CONVERSION_TIME_4_CLOCKS,\r
+ .resolution = ADC_RESOLUTION_10_BIT,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ },\r
+};\r
+const Adc_ChannelType Adc_ATDGroupChannelList[ADC_NBR_OF_ATDGROUP_CHANNELS] =\r
+{\r
+ ADC_CH2,\r
+};\r
+\r
+Adc_ValueGroupType Adc_ATDGroupBuffer [sizeof(Adc_ATDGroupChannelList)/sizeof(Adc_ATDGroupChannelList[0])];\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ {\r
+ .conversionMode = ADC_CONV_MODE_CONTINUOUS,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ .groupCallback = Adc_ATDCallback,\r
+ .channelList = Adc_ATDGroupChannelList,\r
+ .resultBuffer = Adc_ATDGroupBuffer, \r
+ .numberOfChannels = sizeof(Adc_ATDGroupChannelList)/sizeof(Adc_ATDGroupChannelList[0]),\r
+ .status = &AdcGroupStatus[0], \r
+ },\r
+};\r
+\r
+const Adc_ConfigType AdcConfig[] =\r
+{\r
+ {\r
+ .hwConfigPtr = AdcHWUnitConfiguration,\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ }\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Adc (Adc_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 10:10:57 CET 2010\r
+ */\r
+\r
+
+#if (ADC_SW_MAJOR_VERSION != 1)
+#error "Adc: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define ADC_DEINIT_API STD_OFF\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_OFF\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_NONE\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_NOF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_4_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_16_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+\r
+typedef enum\r
+{\r
+ ADC_RESOLUTION_10_BIT,\r
+ ADC_RESOLUTION_8_BIT,\r
+}Adc_ResolutionType;\r
+\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINUOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+typedef struct\r
+{\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ void (*groupCallback)(void);\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+} Adc_GroupDefType;\r
+\r
+#define ADC_NBR_OF_ATDGROUP_CHANNELS 1 \r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0, \r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType convTime;\r
+ Adc_ResolutionType resolution;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig[];\r
+\r
+#endif /* ADC_CFG_H_ */\r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+
+#if (CAN_SW_MAJOR_VERSION != 1)
+#error "Can: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_ON\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF // Not supported\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+typedef enum {\r
+ CAN_CTRL_0 = 0,\r
+ CAN_CTRL_1 = 1,\r
+ CAN_CTRL_2 = 2,\r
+ CAN_CTRL_3 = 3,\r
+ CAN_CTRL_4 = 4,\r
+ CAN_CONTROLLER_CNT = 5\r
+}CanControllerIdType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ TxBox,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ RxBox,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+typedef struct\r
+{\r
+ uint8 idmr[8]; // Identifier Mask Register, 1 = ignore corresponding acceptance code register bit\r
+ uint8 idar[8]; // Identifier Acceptance Register\r
+ Can_Arc_IDAMType idam;\r
+} Can_FilterMaskType;\r
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
+\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_CAN0_Mask_1 = {\r
+ {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF},\r
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0},\r
+ CAN_ARC_IDAM_2_32BIT\r
+};\r
+\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CAN0[] = {\r
+ {\r
+ .CanObjectId = RxBox,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_CAN0_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = TxBox,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_CAN0_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_0,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CAN0[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 15 12:06:55 CET 2010\r
+ */\r
+\r
+
+#if (DIO_SW_MAJOR_VERSION != 1)
+#error "Dio: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define DIO_VERSION_INFO_API STD_OFF\r
+#define DIO_DEV_ERROR_DETECT STD_OFF\r
+\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ DIO_PORT_A = 0,\r
+ DIO_PORT_E = 1,\r
+ DIO_PORT_B = 2,\r
+ DIO_PORT_H = 3,\r
+ DIO_PORT_J = 4,\r
+ DIO_PORT_K = 5,\r
+ DIO_PORT_M = 6,\r
+ DIO_PORT_P = 7,\r
+ DIO_PORT_S = 8,\r
+ DIO_PORT_T = 9,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_DI_PH0 24\r
+#define DIO_CHANNEL_NAME_DI_PH1 25\r
+#define DIO_CHANNEL_NAME_DI_PH2 26\r
+#define DIO_CHANNEL_NAME_DI_PH3 27\r
+#define DIO_CHANNEL_NAME_DI_PH4 28\r
+#define DIO_CHANNEL_NAME_DI_PH5 29\r
+#define DIO_CHANNEL_NAME_DI_PH6 30\r
+#define DIO_CHANNEL_NAME_DI_PH7 31\r
+#define DIO_CHANNEL_NAME_DO_PB0 16\r
+#define DIO_CHANNEL_NAME_DO_PB1 17\r
+#define DIO_CHANNEL_NAME_DO_PB2 18\r
+#define DIO_CHANNEL_NAME_DO_PB3 19\r
+#define DIO_CHANNEL_NAME_DO_PB4 20\r
+#define DIO_CHANNEL_NAME_DO_PB5 21\r
+#define DIO_CHANNEL_NAME_DO_PB6 22\r
+#define DIO_CHANNEL_NAME_DO_PB7 23\r
+#define DIO_CHANNEL_NAME_DI_PT0 72\r
+#define DIO_CHANNEL_NAME_DI_PT1 73\r
+#define DIO_CHANNEL_NAME_DO_PT2 74\r
+\r
+// Channel group\r
+#define DIO_GROUP_NAME_DI_DIP (&DioConfigData[0])\r
+#define DIO_GROUP_NAME_DO_LEDBAR (&DioConfigData[1])\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_DipSwitch (DIO_PORT_H)\r
+#define DIO_PORT_NAME_LEDBar (DIO_PORT_B)\r
+#define DIO_PORT_NAME_Timer (DIO_PORT_T)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 15 12:06:55 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_DI_PH0,\r
+ DIO_CHANNEL_NAME_DI_PH1,\r
+ DIO_CHANNEL_NAME_DI_PH2,\r
+ DIO_CHANNEL_NAME_DI_PH3,\r
+ DIO_CHANNEL_NAME_DI_PH4,\r
+ DIO_CHANNEL_NAME_DI_PH5,\r
+ DIO_CHANNEL_NAME_DI_PH6,\r
+ DIO_CHANNEL_NAME_DI_PH7,\r
+ DIO_CHANNEL_NAME_DO_PB0,\r
+ DIO_CHANNEL_NAME_DO_PB1,\r
+ DIO_CHANNEL_NAME_DO_PB2,\r
+ DIO_CHANNEL_NAME_DO_PB3,\r
+ DIO_CHANNEL_NAME_DO_PB4,\r
+ DIO_CHANNEL_NAME_DO_PB5,\r
+ DIO_CHANNEL_NAME_DO_PB6,\r
+ DIO_CHANNEL_NAME_DO_PB7,\r
+ DIO_CHANNEL_NAME_DI_PT0,\r
+ DIO_CHANNEL_NAME_DI_PT1,\r
+ DIO_CHANNEL_NAME_DO_PT2,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_DipSwitch, \r
+ DIO_PORT_NAME_LEDBar, \r
+ DIO_PORT_NAME_Timer, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = { \r
+ { \r
+ .port = DIO_PORT_NAME_DipSwitch,\r
+ .mask = 255, \r
+ .offset = 0, \r
+ }, \r
+ { \r
+ .port = DIO_PORT_NAME_LEDBar,\r
+ .mask = 255, \r
+ .offset = 0, \r
+ }, \r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = DIO_END_OF_LIST, \r
+ .mask = DIO_END_OF_LIST, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+/*\r
+ * Configuration of module Gpt (Gpt_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Gpt (Gpt_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:03 CET 2010\r
+ */\r
+\r
+
+#if (GPT_SW_MAJOR_VERSION != 1)
+#error "Gpt: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Std_Types.h"\r
+\r
+\r
+#define GPT_VARIANT_PC STD_OFF\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+/** HW PIT channels */\r
+#define GPT_CHANNEL_RTI 0\r
+#define GPT_CHANNEL_0 0\r
+#define GPT_CHANNEL_1 1\r
+#define GPT_CHANNEL_2 2\r
+#define GPT_CHANNEL_3 3\r
+#define GPT_CHANNEL_4 4\r
+#define GPT_CHANNEL_5 5\r
+#define GPT_CHANNEL_6 6\r
+#define GPT_CHANNEL_7 7\r
+\r
+#define GPT_CHANNEL_CNT 8\r
+\r
+#if defined(CFG_MPC55XX)\r
+#define GPT_CHANNEL_DEC 9\r
+#endif\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+\r
+#define GPT_DEV_ERROR_DETECT STD_OFF\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+#define GPT_DEINIT_API STD_OFF\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_OFF\r
+#define GPT_TIME_REMAINING_API STD_OFF\r
+#define GPT_TIME_ELAPSED_API STD_OFF\r
+#define GPT_VERSION_INFO_API STD_OFF\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+typedef struct {\r
+ uint32 GptChannelClkSrc;\r
+ Gpt_ChannelType GptChannelId;\r
+ Gpt_ChannelMode GptChannelMode;\r
+ void (*GptNotification)();\r
+ uint32 GptChannelPrescale;\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 1,\r
+ .Pll2 = 2,\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+
+#if (MCU_SW_MAJOR_VERSION != 2)
+#error "Mcu: Configuration file version differs from BSW version."
+#endif
+\r
+#warning "This default file may only be used as an example!"
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON \r
+#define MCU_PERFORM_RESET_API STD_OFF\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_Clock = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Port.h"\r
+\r
+#define PORT_UNDEFINED 0x00\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .corePullUpRegister = 0x90,\r
+ .coreReducedDriveRegister = 0x00,\r
+ .modeRoutingRegister = 0x00,\r
+\r
+ #if ( PORTA_CONFIGURABLE == STD_ON )\r
+ .portADirection = PORT_UNDEFINED,\r
+ .portAOutValue = PORT_UNDEFINED,\r
+ .portAMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTB_CONFIGURABLE == STD_ON )\r
+ .portBDirection = 0xFF,\r
+ .portBOutValue = PORT_UNDEFINED,\r
+ .portBMask = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTE_CONFIGURABLE == STD_ON )\r
+ .portEDirection = PORT_UNDEFINED,\r
+ .portEOutValue = PORT_UNDEFINED,\r
+ .portEMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTK_CONFIGURABLE == STD_ON )\r
+ .portKDirection = PORT_UNDEFINED,\r
+ .portKOutValue = PORT_UNDEFINED,\r
+ .portKMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTH_CONFIGURABLE == STD_ON )\r
+ .portHDirection = 0x0,\r
+ .portHOutValue = 0x0,\r
+ .portHMask = 0x0,\r
+ .portHPullEnableRegister = 0xFF,\r
+ .portHPullPolarityRegsiter = 0x0,\r
+ .portHReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ .portJDirection = 0x80,\r
+ .portJOutValue = 0xC0,\r
+ .portJMask = 0x40,\r
+ .portJPullEnableRegister = 0x0,\r
+ .portJPullPolarityRegsiter 0x0,\r
+ .portJReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTM_CONFIGURABLE == STD_ON )\r
+ .portMDirection = 0x0,\r
+ .portMOutValue = 0xC3,\r
+ .portMMask = 0x0,\r
+ .portMPullEnableRegister = 0x0,\r
+ .portMPullPolarityRegsiter = 0x0,\r
+ .portMWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portMReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTP_CONFIGURABLE == STD_ON )\r
+ .portPDirection = PORT_UNDEFINED,\r
+ .portPOutValue = PORT_UNDEFINED,\r
+ .portPMask = PORT_UNDEFINED,\r
+ .portPPullEnableRegister = PORT_UNDEFINED,\r
+ .portPPullPolarityRegsiter = PORT_UNDEFINED,\r
+ .portPReducedDriveRegister = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTS_CONFIGURABLE == STD_ON )\r
+ .portSDirection = 0x0,\r
+ .portSOutValue = 0xF,\r
+ .portSMask = 0x0,\r
+ .portSPullEnableRegister = 0x5,\r
+ .portSPullPolarityRegsiter = 0x0,\r
+ .portSWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portSReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTT_CONFIGURABLE == STD_ON )\r
+ .portTDirection = 0x4,\r
+ .portTOutValue = 0x3,\r
+ .portTMask = 0x0,\r
+ .portTPullEnableRegister = 0x0,\r
+ .portTPullPolarityRegsiter = 0x0,\r
+ .portTReducedDriveRegister = 0x0,\r
+ #endif\r
+};\r
+\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Nov 08 20:30:02 CET 2010\r
+ */\r
+\r
+
+#if (PORT_SW_MAJOR_VERSION != 1)
+#error "Port: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+\r
+/** Parameter to enable/disable configuration on a port */\r
+#define PORTA_CONFIGURABLE STD_OFF\r
+#define PORTB_CONFIGURABLE STD_ON\r
+#define PORTE_CONFIGURABLE STD_OFF\r
+#define PORTK_CONFIGURABLE STD_OFF\r
+#define PORTH_CONFIGURABLE STD_ON\r
+#define PORTJ_CONFIGURABLE STD_ON\r
+#define PORTM_CONFIGURABLE STD_ON\r
+#define PORTP_CONFIGURABLE STD_OFF\r
+#define PORTS_CONFIGURABLE STD_ON\r
+#define PORTT_CONFIGURABLE STD_ON\r
+\r
+#define PORT_A_BASE 0x0100\r
+#define PORT_B_BASE 0x0200\r
+#define PORT_E_BASE 0x0300\r
+#define PORT_K_BASE 0x0400\r
+#define PORT_H_BASE 0x0500\r
+#define PORT_J_BASE 0x0600\r
+#define PORT_M_BASE 0x0700\r
+#define PORT_P_BASE 0x0800\r
+#define PORT_S_BASE 0x0900\r
+#define PORT_T_BASE 0x0A00\r
+#define PORT_BITMASK 0x00FF\r
+#define PORT_BASEMASK 0xFF00;\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum\r
+{\r
+ PORT_PA0 = PORT_A_BASE,\r
+ PORT_PA1,\r
+ PORT_PA2,\r
+ PORT_PA3,\r
+ PORT_PA4,\r
+ PORT_PA5,\r
+ PORT_PA6,\r
+ PORT_PA7,\r
+ PORT_PB0 = PORT_B_BASE,\r
+ PORT_PB1,\r
+ PORT_PB2,\r
+ PORT_PB3,\r
+ PORT_PB4,\r
+ PORT_PB5,\r
+ PORT_PB6,\r
+ PORT_PB7,\r
+ PORT_PE0 = PORT_E_BASE,\r
+ PORT_PE1,\r
+ PORT_PE2,\r
+ PORT_PE3,\r
+ PORT_PE4,\r
+ PORT_PE5,\r
+ PORT_PE6,\r
+ PORT_PE7,\r
+ PORT_PH0 = PORT_H_BASE,\r
+ PORT_PH1,\r
+ PORT_PH2,\r
+ PORT_PH3,\r
+ PORT_PH4,\r
+ PORT_PH5,\r
+ PORT_PH6,\r
+ PORT_PH7,\r
+ PORT_PJ0 = PORT_J_BASE,\r
+ PORT_PJ1,\r
+ PORT_PJ2,\r
+ PORT_PJ3,\r
+ PORT_PJ4,\r
+ PORT_PJ5,\r
+ PORT_PJ6,\r
+ PORT_PJ7,\r
+ PORT_PK0 = PORT_K_BASE,\r
+ PORT_PK1,\r
+ PORT_PK2,\r
+ PORT_PK3,\r
+ PORT_PK4,\r
+ PORT_PK5,\r
+ PORT_PK6,\r
+ PORT_PK7,\r
+ PORT_PM0 = PORT_M_BASE,\r
+ PORT_PM1,\r
+ PORT_PM2,\r
+ PORT_PM3,\r
+ PORT_PM4,\r
+ PORT_PM5,\r
+ PORT_PM6,\r
+ PORT_PM7,\r
+ PORT_PP0 = PORT_P_BASE,\r
+ PORT_PP1,\r
+ PORT_PP2,\r
+ PORT_PP3,\r
+ PORT_PP4,\r
+ PORT_PP5,\r
+ PORT_PP6,\r
+ PORT_PP7,\r
+ PORT_PS0 = PORT_S_BASE,\r
+ PORT_PS1,\r
+ PORT_PS2,\r
+ PORT_PS3,\r
+ PORT_PS4,\r
+ PORT_PS5,\r
+ PORT_PS6,\r
+ PORT_PS7,\r
+ PORT_PT0 = PORT_T_BASE,\r
+ PORT_PT1,\r
+ PORT_PT2,\r
+ PORT_PT3,\r
+ PORT_PT4,\r
+ PORT_PT5,\r
+ PORT_PT6,\r
+ PORT_PT7,\r
+} Port_PinType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct\r
+{\r
+ const uint8_t corePullUpRegister; // PUCR\r
+ const uint8_t coreReducedDriveRegister; // RDRIV\r
+ const uint8_t modeRoutingRegister; // MODRR\r
+\r
+ /**\r
+ * Every port has:\r
+ * a direction (input or output)\r
+ * a default out value\r
+ * a mask that is 0 if the direction is allowed to change during runtime\r
+ *\r
+ * Some ports have:\r
+ * a reduced drive conf (power saving)\r
+ * a pull enable conf (enable pull-up/pull-down\r
+ * a pull direction conf (pull-up or pull-down)\r
+ * a wired mode (enable open drain outputs)\r
+ */\r
+#if ( PORTA_CONFIGURABLE == STD_ON )\r
+ const uint8_t portADirection;\r
+ const uint8_t portAOutValue;\r
+ const uint8_t portAMask;\r
+#endif\r
+\r
+#if ( PORTB_CONFIGURABLE == STD_ON )\r
+ const uint8_t portBDirection;\r
+ const uint8_t portBOutValue;\r
+ const uint8_t portBMask;\r
+#endif\r
+\r
+#if ( PORTE_CONFIGURABLE == STD_ON )\r
+ const uint8_t portEDirection;\r
+ const uint8_t portEOutValue;\r
+ const uint8_t portEMask;\r
+#endif\r
+\r
+#if ( PORTK_CONFIGURABLE == STD_ON )\r
+ const uint8_t portKDirection;\r
+ const uint8_t portKOutValue;\r
+ const uint8_t portKMask;\r
+#endif\r
+\r
+#if ( PORTH_CONFIGURABLE == STD_ON )\r
+ const uint8_t portHDirection;\r
+ const uint8_t portHOutValue;\r
+ const uint8_t portHMask;\r
+ const uint8_t portHPullEnableRegister;\r
+ const uint8_t portHPullPolarityRegsiter;\r
+ const uint8_t portHReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ const uint8_t portJDirection;\r
+ const uint8_t portJOutValue;\r
+ const uint8_t portJMask;\r
+ const uint8_t portJPullEnableRegister;\r
+ const uint8_t portJPullPolarityRegsiter;\r
+ const uint8_t portJReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTM_CONFIGURABLE == STD_ON )\r
+ const uint8_t portMDirection;\r
+ const uint8_t portMOutValue;\r
+ const uint8_t portMMask;\r
+ const uint8_t portMPullEnableRegister;\r
+ const uint8_t portMPullPolarityRegsiter;\r
+ const uint8_t portMWiredModeRegsiter;\r
+ const uint8_t portMReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTP_CONFIGURABLE == STD_ON )\r
+ const uint8_t portPDirection;\r
+ const uint8_t portPOutValue;\r
+ const uint8_t portPMask;\r
+ const uint8_t portPPullEnableRegister;\r
+ const uint8_t portPPullPolarityRegsiter;\r
+ const uint8_t portPReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTS_CONFIGURABLE == STD_ON )\r
+ const uint8_t portSDirection;\r
+ const uint8_t portSOutValue;\r
+ const uint8_t portSMask;\r
+ const uint8_t portSPullEnableRegister;\r
+ const uint8_t portSPullPolarityRegsiter;\r
+ const uint8_t portSWiredModeRegsiter;\r
+ const uint8_t portSReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTT_CONFIGURABLE == STD_ON )\r
+ const uint8_t portTDirection;\r
+ const uint8_t portTOutValue;\r
+ const uint8_t portTMask;\r
+ const uint8_t portTPullEnableRegister;\r
+ const uint8_t portTPullPolarityRegsiter;\r
+ const uint8_t portTReducedDriveRegister;\r
+#endif\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_SDA PORT_PJ6 \r
+#define PORT_PIN_NAME_SCL PORT_PJ7 \r
+#define PORT_PIN_NAME_TXD PORT_PM1 \r
+#define PORT_PIN_NAME_RXD PORT_PM0 \r
+#define PORT_PIN_NAME_PB0 PORT_PB0 \r
+#define PORT_PIN_NAME_PB1 PORT_PB1 \r
+#define PORT_PIN_NAME_PB2 PORT_PB2 \r
+#define PORT_PIN_NAME_PB3 PORT_PB3 \r
+#define PORT_PIN_NAME_PB4 PORT_PB4 \r
+#define PORT_PIN_NAME_PB5 PORT_PB5 \r
+#define PORT_PIN_NAME_PB6 PORT_PB6 \r
+#define PORT_PIN_NAME_PB7 PORT_PB7 \r
+#define PORT_PIN_NAME_PH0 PORT_PH0 \r
+#define PORT_PIN_NAME_PH1 PORT_PH1 \r
+#define PORT_PIN_NAME_PH2 PORT_PH2 \r
+#define PORT_PIN_NAME_PH3 PORT_PH3 \r
+#define PORT_PIN_NAME_PH4 PORT_PH4 \r
+#define PORT_PIN_NAME_PH5 PORT_PH5 \r
+#define PORT_PIN_NAME_PH6 PORT_PH6 \r
+#define PORT_PIN_NAME_PH7 PORT_PH7 \r
+#define PORT_PIN_NAME_PT0 PORT_PT0 \r
+#define PORT_PIN_NAME_PT1 PORT_PT1 \r
+#define PORT_PIN_NAME_BEEPER PORT_PT2 \r
+#define PORT_PIN_NAME_RXD0 PORT_PS0 \r
+#define PORT_PIN_NAME_TXD0 PORT_PS1 \r
+#define PORT_PIN_NAME_RXD1 PORT_PS2 \r
+#define PORT_PIN_NAME_TXD1 PORT_PS3 \r
+#define PORT_PIN_NAME_PM6 PORT_PM6 \r
+#define PORT_PIN_NAME_PM7 PORT_PM7 \r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 09:10:16 CET 2010\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Pwm.h"\r
+\r
+const Pwm_ConfigType PwmConfig =\r
+{\r
+ .channels = { \r
+ {\r
+ .channel = GREENLED,\r
+ DUTY_AND_PERIOD(4096,188.0),\r
+ .centerAlign = STD_OFF,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = STD_ON,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD\r
+ }, \r
+ {\r
+ .channel = REDLED,\r
+ DUTY_AND_PERIOD(24576,188.0),\r
+ .centerAlign = STD_OFF,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = STD_ON,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD\r
+ },\r
+ },\r
+ .busPrescalerA = PRESCALER_128,\r
+ .busPrescalerB = PRESCALER_2,\r
+ .prescalerA = 1,\r
+ .prescalerB = 1,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Nov 17 09:10:16 CET 2010\r
+ */\r
+\r
+
+#if (PWM_SW_MAJOR_VERSION != 1)
+#error "Pwm: Configuration file version differs from BSW version."
+#endif
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#define PWM_DEV_ERROR_DETECT STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_OFF\r
+#define PWM_FREEZE_ENABLE STD_OFF\r
+\r
+// Define what API functions to enable.\r
+#define PWM_GET_OUTPUT_STATE STD_OFF\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+#define PWM_DEINIT STD_OFF\r
+#define PWM_DUTYCYCLE STD_ON\r
+#define PWM_SET_OUTPUT_TO_IDLE STD_OFF\r
+#define PWM_VERSION_INFO_API STD_OFF\r
+\r
+\r
+\r
+/**\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/**\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == channel id.\r
+ */\r
+typedef uint8 Pwm_ChannelType;\r
+\r
+/**\r
+ * PWM070: All time units used within the API services of the PWM module shall\r
+ * be of the unit ticks.\r
+ */\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ GREENLED = 1 ,\r
+ REDLED = 0 ,\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+/* 1 =PWMchannel output is high at the beginning of the period, then goes low when the duty count\r
+is reached. */\r
+#define POLARITY_NORMAL 1\r
+#define POLARITY_INVERSED 0\r
+\r
+/**\r
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,\r
+ * the following macro can be used to convert between that format and the\r
+ * driver format.\r
+ */\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (uint8)((uint32)((uint32)_duty*(uint32)_period)>>15), .period = _period\r
+\r
+\r
+typedef struct {\r
+ /** Number of duty ticks */\r
+ uint8_t duty;\r
+ /** Length of period, in ticks */\r
+ uint8_t period;\r
+ /** Center or left align */\r
+ uint8_t centerAlign:1;\r
+ /** Polarity of the channel */\r
+ uint8_t polarity:1;\r
+ /** Scaled clock enabled */\r
+ uint8_t scaledClockEnable:1;\r
+ /** idle state */\r
+ uint8_t idleState:1;\r
+\r
+ uint8_t reserved:4;\r
+\r
+ Pwm_ChannelClassType class;\r
+\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+typedef enum{\r
+ PRESCALER_1 = 0,\r
+ PRESCALER_2 = 1,\r
+ PRESCALER_4 = 2,\r
+ PRESCALER_8 = 3,\r
+ PRESCALER_16 = 4,\r
+ PRESCALER_32 = 5,\r
+ PRESCALER_64 = 6,\r
+ PRESCALER_128 = 7,\r
+}Pwm_PrescalerType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType channels[PWM_NUMBER_OF_CHANNELS];\r
+ Pwm_PrescalerType busPrescalerA;\r
+ Pwm_PrescalerType busPrescalerB;\r
+ uint8_t prescalerA;\r
+ uint8_t prescalerB;\r
+} Pwm_ConfigType;\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+\r
+/* The board Elmicro HCS12 T-Board comes with HCS12X512DP.\r
+ * This memory mapping is for that CPU.\r
+ */\r
+ \r
+page0 (rwx) : ORIGIN = 0x0, LENGTH = 2k\r
+\r
+/* RAM */\r
+data (rwx) : ORIGIN = 0x1000, LENGTH = 12k\r
+\r
+eeprom (rx): ORIGIN = 0x0800, LENGTH = 2k\r
+text (rx) : ORIGIN = 0x4000, LENGTH = 48k\r
+ \r
+/* high fixed bank, reserve 0x100 vectors and security. */\r
+text_h (rx) : ORIGIN = 0xc002, LENGTH = 16k-0x102\r
+vectors (rx) : ORIGIN = 0xff80, LENGTH = 0x80\r
+ \r
+/* Flash memory banks VMA:s */\r
+bank_A (rx) : ORIGIN = 0x790000, LENGTH = 16k /* Page E0 */\r
+bank_B (rx) : ORIGIN = 0x794000, LENGTH = 16k /* Page E1 */\r
+bank_C (rx) : ORIGIN = 0x798000, LENGTH = 16k /* Page E2 */\r
+bank_D (rx) : ORIGIN = 0x79c000, LENGTH = 16k /* Page E3 */\r
+bank_E (rx) : ORIGIN = 0x7A0000, LENGTH = 16k /* Page E4 */\r
+bank_F (rx) : ORIGIN = 0x7A4000, LENGTH = 16k /* Page E5 */\r
+bank_G (rx) : ORIGIN = 0x7A8000, LENGTH = 16k /* Page E6 */\r
+bank_H (rx) : ORIGIN = 0x7Ac000, LENGTH = 16k /* Page E7 */\r
+bank_I (rx) : ORIGIN = 0x7B0000, LENGTH = 16k /* Page E8 */\r
+bank_J (rx) : ORIGIN = 0x7B4000, LENGTH = 16k /* Page E9 */\r
+bank_K (rx) : ORIGIN = 0x7B8000, LENGTH = 16k /* Page EA */\r
+bank_L (rx) : ORIGIN = 0x7Bc000, LENGTH = 16k /* Page EB */\r
+bank_M (rx) : ORIGIN = 0x7C0000, LENGTH = 16k /* Page EC */\r
+bank_N (rx) : ORIGIN = 0x7C4000, LENGTH = 16k /* Page ED */\r
+bank_O (rx) : ORIGIN = 0x7C8000, LENGTH = 16k /* Page EE */\r
+bank_P (rx) : ORIGIN = 0x7Cc000, LENGTH = 16k /* Page EF */\r
+ \r
+bank_Q (rx) : ORIGIN = 0x7D0000, LENGTH = 16k /* Page F0 */\r
+bank_R (rx) : ORIGIN = 0x7D4000, LENGTH = 16k /* Page F1 */\r
+bank_S (rx) : ORIGIN = 0x7D8000, LENGTH = 16k /* Page F2 */\r
+bank_T (rx) : ORIGIN = 0x7Dc000, LENGTH = 16k /* Page F3 */\r
+bank_U (rx) : ORIGIN = 0x7E0000, LENGTH = 16k /* Page F4 */\r
+bank_V (rx) : ORIGIN = 0x7E4000, LENGTH = 16k /* Page F5 */\r
+bank_W (rx) : ORIGIN = 0x7E8000, LENGTH = 16k /* Page F6 */\r
+bank_X (rx) : ORIGIN = 0x7Ec000, LENGTH = 16k /* Page F7 */\r
+bank_Y (rx) : ORIGIN = 0x7F0000, LENGTH = 16k /* Page F8 */\r
+bank_Z (rx) : ORIGIN = 0x7F4000, LENGTH = 16k /* Page F9 */\r
+bank_AA (rx) : ORIGIN = 0x7F8000, LENGTH = 16k /* Page FA */\r
+bank_AB (rx) : ORIGIN = 0x7Fc000, LENGTH = 16k /* Page FB */\r
+bank_AC (rx) : ORIGIN = 0x800000, LENGTH = 16k /* Page FC */\r
+bank_FIX1 (rx) : ORIGIN = 0x804000, LENGTH = 16k /* Page FD */\r
+/* bankxx (rx) : ORIGIN = 0x808000, LENGTH = 16k /* Page FE Not used Why?*/\r
+bank_FIX2 (rx) : ORIGIN = 0x80c002, LENGTH = 16k-0x102 /* Page FF */\r
+ \r
+/* NoICE Elf loading */ \r
+\r
+bank_A_lma (rx) : ORIGIN = 0x790000, LENGTH = 16k /* Page E0 */ \r
+bank_B_lma (rx) : ORIGIN = 0x794000, LENGTH = 16k /* Page E1 */\r
+bank_C_lma (rx) : ORIGIN = 0x798000, LENGTH = 16k /* Page E2 */\r
+bank_D_lma (rx) : ORIGIN = 0x79c000, LENGTH = 16k /* Page E3 */\r
+bank_E_lma (rx) : ORIGIN = 0x7A0000, LENGTH = 16k /* Page E4 */\r
+bank_F_lma (rx) : ORIGIN = 0x7A4000, LENGTH = 16k /* Page E5 */\r
+bank_G_lma (rx) : ORIGIN = 0x7A8000, LENGTH = 16k /* Page E6 */\r
+bank_H_lma (rx) : ORIGIN = 0x7Ac000, LENGTH = 16k /* Page E7 */\r
+bank_I_lma (rx) : ORIGIN = 0x7B0000, LENGTH = 16k /* Page E8 */\r
+bank_J_lma (rx) : ORIGIN = 0x7B4000, LENGTH = 16k /* Page E9 */\r
+bank_K_lma (rx) : ORIGIN = 0x7B8000, LENGTH = 16k /* Page EA */\r
+bank_L_lma (rx) : ORIGIN = 0x7Bc000, LENGTH = 16k /* Page EB */\r
+bank_M_lma (rx) : ORIGIN = 0x7C0000, LENGTH = 16k /* Page EC */\r
+bank_N_lma (rx) : ORIGIN = 0x7C4000, LENGTH = 16k /* Page ED */\r
+bank_O_lma (rx) : ORIGIN = 0x7C8000, LENGTH = 16k /* Page EE */\r
+bank_P_lma (rx) : ORIGIN = 0x7Cc000, LENGTH = 16k /* Page EF */\r
+\r
+bank_Q_lma (rx) : ORIGIN = 0x7D0000, LENGTH = 16k /* Page F0 */\r
+bank_R_lma (rx) : ORIGIN = 0x7D4000, LENGTH = 16k /* Page F1 */\r
+bank_S_lma (rx) : ORIGIN = 0x7D8000, LENGTH = 16k /* Page F2 */\r
+bank_T_lma (rx) : ORIGIN = 0x7Dc000, LENGTH = 16k /* Page F3 */\r
+bank_U_lma (rx) : ORIGIN = 0x7E0000, LENGTH = 16k /* Page F4 */\r
+bank_V_lma (rx) : ORIGIN = 0x7E4000, LENGTH = 16k /* Page F5 */\r
+bank_W_lma (rx) : ORIGIN = 0x7E8000, LENGTH = 16k /* Page F6 */\r
+bank_X_lma (rx) : ORIGIN = 0x7Ec000, LENGTH = 16k /* Page F7 */\r
+bank_Y_lma (rx) : ORIGIN = 0x7F0000, LENGTH = 16k /* Page F8 */\r
+bank_Z_lma (rx) : ORIGIN = 0x7F4000, LENGTH = 16k /* Page F9 */\r
+bank_AA_lma (rx) : ORIGIN = 0x7F8000, LENGTH = 16k /* Page FA */\r
+bank_AB_lma (rx) : ORIGIN = 0x7Fc000, LENGTH = 16k /* Page FB */\r
+bank_AC_lma (rx) : ORIGIN = 0x800000, LENGTH = 16k /* Page FC */\r
+bank_FIX1_lma (rx) : ORIGIN = 0x804000, LENGTH = 16k /* Page FD */\r
+/* bankxx_lma (rx) : ORIGIN = 0x808000, LENGTH = 16k /* Page FE Not used Why?*/\r
+bank_FIX2_lma (rx) : ORIGIN = 0x80c002, LENGTH = 16k-0x102 /* Page FF */\r
+vectors_lma (rx) : ORIGIN = 0x80ff80, LENGTH = 0x80\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>tboard_config</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="303715fd-6599-41c2-8c4e-d60c4b84b8de">\r
+ <SHORT-NAME>tboard_config</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">HCS12</SD>\r
+ <SD GID="GENDIR">/arc/boards/hcs12x_elmicro_tboard/config</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/tboard_config/SwComposition_tboard_config</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Mcu</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Port</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Dio</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Adc</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Pwm</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Gpt</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tboard_config/Can</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="fb9da4ba-41cc-4e91-8312-d2174ffea2e3">\r
+ <SHORT-NAME>SwComposition_tboard_config</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="869ab916-7358-4197-8551-225ce5236114">\r
+ <SHORT-NAME>Mcu</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Mcu</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="0202b255-3c62-4340-b071-021e6f6e5754">\r
+ <SHORT-NAME>McuGeneralConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuGeneralConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="3a863a59-9129-4971-bf33-1b2597733829">\r
+ <SHORT-NAME>McuModuleConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSrcFailureNotification</DEFINITION-REF>\r
+ <VALUE>DISABLED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuNumberOfMcuModes</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuRamSectors</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuResetSetting</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="42876123-e30b-411f-8916-e7ec0e06224e">\r
+ <SHORT-NAME>McuClockSettingConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuDefaultClockReference</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Mcu/McuModuleConfiguration/McuClockSettingConfig/Clock</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="48533cbf-b37f-4bdd-bef2-1c1d6f7c38f0">\r
+ <SHORT-NAME>Clock</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>1.6E7</VALUE>\r
+ </FLOAT-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllClock</DEFINITION-REF>\r
+ <VALUE>48000000</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0e26b112-e113-4683-bc63-25ab38641c7b">\r
+ <SHORT-NAME>McuModeSettingConf</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="a06e6eca-b8f3-40ee-b70a-526e9d07d86d">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="256a7c74-3a97-4041-a4f6-fdab77196a48">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fe36d864-a9cf-47e9-99f4-179f339fea26">\r
+ <SHORT-NAME>II2C</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="13de6916-4779-4cf9-aa84-6423f24b5c75">\r
+ <SHORT-NAME>SDA</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>38</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d40af306-47db-4163-866b-ed234f4d54aa">\r
+ <SHORT-NAME>SCL</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>39</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c9118c42-7541-4c3e-aee5-9b33fb38e7de">\r
+ <SHORT-NAME>CAN0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="48995106-5317-492c-a8be-9dc90f86dce9">\r
+ <SHORT-NAME>TXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>49</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f355a281-9d29-4662-bd38-93b45a67b181">\r
+ <SHORT-NAME>RXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="970071df-1367-4fa6-b8ba-d12184ac9016">\r
+ <SHORT-NAME>LEDBAR</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="e75826c4-11e9-4c78-a62e-f64155f4d104">\r
+ <SHORT-NAME>PB0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f13211c5-d930-4315-88ac-f7baf7a013e1">\r
+ <SHORT-NAME>PB1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>17</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1bc00010-6ebe-436f-92e1-2d6c0895aa46">\r
+ <SHORT-NAME>PB2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>18</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0009d8fa-ebd5-451b-83f7-8a7e7fcc0ced">\r
+ <SHORT-NAME>PB3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>19</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="68143d0f-27ba-4bae-ad00-b8ca9392392d">\r
+ <SHORT-NAME>PB4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6367f310-133b-4b10-9275-5519396b82ff">\r
+ <SHORT-NAME>PB5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>21</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="59aa2eb4-ebde-472b-b5c1-ceecfce4336d">\r
+ <SHORT-NAME>PB6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>22</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4a169d18-36d5-40a7-8831-faf22622a866">\r
+ <SHORT-NAME>PB7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>23</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a0e9802a-f4ed-4ad3-b495-49157e822336">\r
+ <SHORT-NAME>DIPSW</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="27cbd4e4-129a-4364-be2b-a0054fb86cbe">\r
+ <SHORT-NAME>PH0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>24</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="30a97936-de39-42de-a3a9-d1e30f12af4d">\r
+ <SHORT-NAME>PH1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>25</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="084b83ee-4c09-4111-b19d-276dab9070ae">\r
+ <SHORT-NAME>PH2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>26</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7f90b11-a909-451c-a93e-b0bbe01df46a">\r
+ <SHORT-NAME>PH3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>27</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="417bb21d-caf2-48c2-a198-814203dc94da">\r
+ <SHORT-NAME>PH4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>28</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6e4f5953-9390-42fd-b33d-86736b010307">\r
+ <SHORT-NAME>PH5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>29</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="02660e29-0e6a-4781-98c8-74a3c9b908ef">\r
+ <SHORT-NAME>PH6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d85861f9-9523-45ad-aa84-44647733487b">\r
+ <SHORT-NAME>PH7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>31</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="103ee4c6-92df-4eae-b87a-096ccf9b56e2">\r
+ <SHORT-NAME>TIMER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="18f35583-11aa-4af3-a7cb-6bf56494047e">\r
+ <SHORT-NAME>PT0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>72</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="58635cff-b40b-41d7-879a-ea79efc33e06">\r
+ <SHORT-NAME>PT1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>73</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="99e5f077-39d8-48c6-8085-6b0764b0c48d">\r
+ <SHORT-NAME>BEEPER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>74</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="95d6d2f4-2db4-4495-84ed-fa8032997f5b">\r
+ <SHORT-NAME>PWM</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="89bf9c10-ceb3-4d60-961c-1051ed4b031d">\r
+ <SHORT-NAME>PP0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="182cd6da-fc4c-4b21-8ad3-57e3e8c3568a">\r
+ <SHORT-NAME>PP1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a1fa03c0-2470-4914-aabd-17c992c74a92">\r
+ <SHORT-NAME>SCI0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9b4e54e6-bc5b-4ccb-b5d9-33670baae41c">\r
+ <SHORT-NAME>RXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1ae13d69-adf7-481a-929d-0c916d37daee">\r
+ <SHORT-NAME>TXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1d78b7b3-38f6-486c-89b2-3369eab9e7df">\r
+ <SHORT-NAME>SCI1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="19e08fdf-14d6-4cfe-aa28-969f9479fde7">\r
+ <SHORT-NAME>RXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>58</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="580e6d9e-8812-438d-9b01-94f8b2cda75f">\r
+ <SHORT-NAME>TXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>59</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="218ea307-52d6-4837-abfb-080872edd058">\r
+ <SHORT-NAME>PM6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>54</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ac024e84-9ae2-4303-a186-6a93ffc0902b">\r
+ <SHORT-NAME>PM7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>55</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="19e54a5c-c778-4d34-88ae-80eaf1fff9d8">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="a1348e64-fb51-4549-9d69-1b3da6d3ec94">\r
+ <SHORT-NAME>Dio</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Dio</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="4037aeab-f046-4253-9082-473b45fccdf9">\r
+ <SHORT-NAME>DioGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="cb003b50-d676-4dff-86ae-f975f01ee955">\r
+ <SHORT-NAME>DipSwitch</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioPortId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>DIO_PORT_H</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="ac1565ee-440f-4c0d-be1a-1330f47f5260">\r
+ <SHORT-NAME>DI_PH0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>24</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="be1b8a73-d855-4554-b15e-f940d58fdd7b">\r
+ <SHORT-NAME>DI_PH1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>25</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8e6d5222-e81c-4041-ae05-e637c9a41541">\r
+ <SHORT-NAME>DI_PH2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>26</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="09329128-fba2-4194-822b-01923007ec4d">\r
+ <SHORT-NAME>DI_PH3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>27</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="147e0262-87ca-4645-87db-21167948a9c1">\r
+ <SHORT-NAME>DI_DIP</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannelGroup</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannelGroup/DioPortMask</DEFINITION-REF>\r
+ <VALUE>255</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannelGroup/DioPortOffset</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="01f80048-1772-41d7-ae8d-ebdd98d37f80">\r
+ <SHORT-NAME>DI_PH4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>28</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="339e2336-aa2e-46e1-97d5-0aa37784642c">\r
+ <SHORT-NAME>DI_PH5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>29</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b4ed32a2-fc07-42cb-9bee-36c7ed359bf8">\r
+ <SHORT-NAME>DI_PH6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="beda3e33-ddf8-49ec-b3c1-11d5f1e34e4a">\r
+ <SHORT-NAME>DI_PH7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>31</VALUE>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c1093841-bee5-4737-aa88-b314fe6464f8">\r
+ <SHORT-NAME>LEDBar</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioPortId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>DIO_PORT_B</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="209c9ecf-db6a-4343-8135-b4755f2868da">\r
+ <SHORT-NAME>DO_PB0</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="d5983969-f90d-41a9-90b7-374bd3173a62">\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>17</VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="8262bafd-812e-4d57-814f-6d86abe5ecd2">\r
+ <SHORT-NAME>DO_PB2</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>18</VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="7bc30e88-2419-4463-94be-c8b1e0f70a9d">\r
+ <SHORT-NAME>DO_PB3</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>19</VALUE>\r
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+ <CONTAINER UUID="0e07df0b-9a29-47a8-bcd9-695647e85c16">\r
+ <SHORT-NAME>DO_PB4</SHORT-NAME>\r
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+ <INTEGER-VALUE>\r
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+ <VALUE>20</VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="fdf69493-298b-4f70-abf3-56a3b7f0abc2">\r
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+ <INTEGER-VALUE>\r
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+ <VALUE>21</VALUE>\r
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+ <CONTAINER UUID="11e005de-8adc-4c92-92da-ebec4863b4c9">\r
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+ <CONTAINER UUID="c80a0b93-35c4-46de-99bd-d60d9291033f">\r
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+ <INTEGER-VALUE>\r
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+ <VALUE>23</VALUE>\r
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+ <CONTAINER UUID="0a5ad5f4-89bf-447a-bf33-e34f6fdd44db">\r
+ <SHORT-NAME>DO_LEDBAR</SHORT-NAME>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannelGroup/DioPortMask</DEFINITION-REF>\r
+ <VALUE>255</VALUE>\r
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+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannelGroup/DioPortOffset</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <SHORT-NAME>Timer</SHORT-NAME>\r
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+ <INTEGER-VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>DIO_PORT_T</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="4851cc6e-1775-442d-aaa3-55b29fe287b9">\r
+ <SHORT-NAME>DI_PT0</SHORT-NAME>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>74</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="1f9d799c-8d10-40c2-81c3-bfec22ef0c3c">\r
+ <SHORT-NAME>Adc</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Adc</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="90fd5051-0762-42d0-b4c0-aa695a3be7f4">\r
+ <SHORT-NAME>AdcConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Adc/AdcConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="cfce80ce-4319-43f2-b959-1e012e1ce88c">\r
+ <SHORT-NAME>ATD_BLOCK</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/ArcAdcResolution</DEFINITION-REF>\r
+ <VALUE>10_BIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/ArcAdcConvTime</DEFINITION-REF>\r
+ <VALUE>4_CLOCKS</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/ArcAdcPrescaleDivideFactor</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9396794a-d8ed-4a2e-a8d6-8e9da5973fda">\r
+ <SHORT-NAME>ATD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelConvTime</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/ArcAdcChannelId</DEFINITION-REF>\r
+ <VALUE>ADC_CH2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelRefVoltsrcHigh</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelRefVoltsrcLow</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelResolution</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcChannel/AdcChannelSampTime</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2feb004b-6700-4a45-9aaf-dd8580c90574">\r
+ <SHORT-NAME>ATDGroup</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupAccessMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupConversionMode</DEFINITION-REF>\r
+ <VALUE>ADC_CONV_MODE_CONTINUOUS</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupPriority</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupReplacement</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupTriggSrc</DEFINITION-REF>\r
+ <VALUE>ADC_TRIGG_SRC_SW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcHwTrigSignal</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcHwTrigTimer</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcNotification</DEFINITION-REF>\r
+ <VALUE>ATDCallback</VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <LINKER-SYMBOL-VALUE>\r
+ <DEFINITION-REF DEST="LINKER-SYMBOL-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcResultBufferPointer</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </LINKER-SYMBOL-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcStreamingBufferMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcStreamingNumSamples</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Adc/AdcConfigSet/AdcHwUnit/AdcGroup/AdcGroupDefinition</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Adc/AdcConfigSet/ATD_BLOCK/ATD</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7415dd0-c862-4cd0-9fb4-cd5555390325">\r
+ <SHORT-NAME>AdcGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Adc/AdcGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcEnableQueuing</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcEnableStartStopGroupApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcGrpNotifCapability</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcHwTriggerApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcPriorityImplementation</DEFINITION-REF>\r
+ <VALUE>ADC_PRIORITY_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcReadGroupApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcGeneral/AdcVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="291e14c0-4fa0-49cf-ab60-4edd984099ed">\r
+ <SHORT-NAME>AdcPublishedInformation</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Adc/AdcPublishedInformation</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcPublishedInformation/AdcChannelValueSigned</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Adc/AdcPublishedInformation/AdcGroupFirstChannelFixed</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Adc/AdcPublishedInformation/AdcMaxChannelResolution</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="17747ce9-57d3-476c-8203-8c93cd2a5dcc">\r
+ <SHORT-NAME>Pwm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Pwm</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="ecc119e4-7869-41cc-af30-3792813737cf">\r
+ <SHORT-NAME>PwmChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="0d1ebc17-ef4d-4193-a492-7d8291ed2dca">\r
+ <SHORT-NAME>GreenLED</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmCenterAlign</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmScaledClockEnable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>4096</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>188.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>POLARITY_NORMAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a05dbf4b-56e8-4e6b-8139-4864371f67c2">\r
+ <SHORT-NAME>RedLED</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmCenterAlign</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmScaledClockEnable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>24576</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>188.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>POLARITY_NORMAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c2a3ced7-5cde-4ca0-804f-9adeb4730fc4">\r
+ <SHORT-NAME>PwmConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmGetOutputState</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetDutyCycle</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetOutputToIdle</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetPeriodAndDuty</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b4c0e419-333e-4370-8f36-28034d382f59">\r
+ <SHORT-NAME>PwmGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmFreezeEnable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDevErorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDutycycleUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmIndex</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmNotificationSupported</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmPeriodUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerA</DEFINITION-REF>\r
+ <VALUE>PRESCALER_128</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerB</DEFINITION-REF>\r
+ <VALUE>PRESCALER_2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerA</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerB</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="ef790408-8b7e-4a19-b347-51b4d423a531">\r
+ <SHORT-NAME>Gpt</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Gpt</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="98ae7b15-0802-4475-9429-0d1901fca0ff">\r
+ <SHORT-NAME>GptChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Gpt/GptChannelConfigSet</DEFINITION-REF>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="41029a14-7132-481b-93f9-56bb91cd516a">\r
+ <SHORT-NAME>GptConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptDeinitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptEnableDisableNotificationApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptTimeElapsedApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptTimeRemainingApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptConfigurationOfOptApiServices/GptWakeupFunctionalityApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="3fcedc0b-ba03-4192-a2e5-eadf681c0dad">\r
+ <SHORT-NAME>GptDriverConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Gpt/GptDriverConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptDriverConfiguration/GptDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Gpt/GptDriverConfiguration/GptReportWakeupSource</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="84bdd5be-ae8f-4920-8123-425502312b34">\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Can</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="bba8d9ee-ff87-446d-853b-536a783c874f">\r
+ <SHORT-NAME>CanConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a5208169-71d2-4f2e-b5fd-766509996c65">\r
+ <SHORT-NAME>CAN0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerActivation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerLoopback</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerBaudRate</DEFINITION-REF>\r
+ <VALUE>125</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanHWControllerId</DEFINITION-REF>\r
+ <VALUE>CAN_CTRL_0</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerPropSeg</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg1</DEFINITION-REF>\r
+ <VALUE>12</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg2</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="cd47453b-40ae-4958-bdb2-2c96b17c7952">\r
+ <SHORT-NAME>Mask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12IdamMaskType</DEFINITION-REF>\r
+ <VALUE>CAN_ARC_IDAM_2_32BIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12ArcIdmrValue</DEFINITION-REF>\r
+ <VALUE>18446744073709551615</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12ArcIdarValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a77c39d5-4ea7-4321-83c5-bbe27d61c01b">\r
+ <SHORT-NAME>RxBox</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>RECEIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ef1a36b6-b037-4177-99f8-3ae349f6157c">\r
+ <SHORT-NAME>TxBox</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>TRANSMIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tboard_config/Can/CanConfigSet/CAN0/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b5becc71-8e43-478d-aee9-bde788df0dad">\r
+ <SHORT-NAME>CanGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanDevErrorDetection</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanMultiplexedTransmission</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=linux\r
+ARCH_FAM=generic\r
+#ARCH=mpc55xx\r
+#ARCH_FAM=ppc\r
+#ARCH_MCU=mpc5516\r
+\r
+# CFG (y/n) macros\r
+CFG= BRD_LINUX\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL+=COM PDUR DET DCM DEM COMM CANSM CANTP CANIF CANNM NM RTE FEE NVM ECUM MCU\r
+\r
+# Needed by us\r
+MOD_USE=\r
+\r
+# Stubs\r
+obj-y += McuExtensionsStub.o
\ No newline at end of file
\r
\r
-Test board. \r
-=======================================================\r
-\r
-The regression test board comes in different variants.\r
\r
+The Freescale MPC5510 is an PowerPC process with a e200Z1+e200Z0 core. \r
+ \r
+Datasheets:\r
+ Eval board:\r
+ http://www.asyst.si/isystem/files/downloads/evaluation_boards/ITMPC5517_V10.pdf \r
+ \r
+ MPC5516/7\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5510&webpageId=1067371573986721160325&nodeId=0162468rH3bTdG06C10325&fromPage=tax\r
\r
-This file supports:\r
-- EVB5516\r
+Board:\r
+ 8Mhz external crystal\r
\r
+Info: \r
+ MPC5516/7 (I think that the board is always equipped with a MPC5517E now)\r
+ e200Z1 + e200Z0 (VLE only)\r
+ 48-66Mhz\r
+ 1.5MB Flash (MPC5516 1MB)\r
+ 80KB SRAM (MPC5516 64KB)\r
+ .. \r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL+=KERNEL MCU GPT LIN CAN CANIF CANTP PORT DIO WDG WDGM PWM COM ADC DMA DEM DCM PDUR IOHWAB\r
\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG NVM MEMIF FEE FLS \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+= RAMLOG \r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Adc.h"\r
#include "Dma.h"\r
#include "mpc5516.h"\r
* Definitions of configuration parameters for ADC Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef ADC_CFG_H_\r
#define ADC_CFG_H_\r
\r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "CanIf.h"\r
#include <stdlib.h>\r
\r
* Definitions of configuration parameters for CAN Interface.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef CANIF_CFG_H_\r
#define CANIF_CFG_H_\r
\r
#define CANIF_TRANSCEIVER_API STD_OFF /**< Not supported */\r
#define CANIF_TRANSMIT_CANCELLATION STD_OFF /**< Not supported */\r
\r
-//-------------------------------------------------------------------\r
-\r
-typedef struct {\r
- void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
- void (*RxIndication)(void *); //(const Can_PduType *);\r
- void (*ControllerBusOff)(uint8);\r
- void (*ControllerWakeup)(uint8);\r
- void (*Arc_Error)(uint8,uint32);\r
-} CanIf_CallbackType;\r
-\r
-\r
\r
//-------------------------------------------------------------------\r
\r
* Definitions of configuration parameters for CAN Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef CAN_CFG_H_\r
#define CAN_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include <stdlib.h>\r
#include "Can.h"\r
#include "CanIf_Cbk.h"\r
* Author: Mattias\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef COMGLOBALS_H_\r
#define COMGLOBALS_H_\r
\r
*/\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef COM_CFG_H_\r
#define COM_CFG_H_\r
\r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
\r
#define ComConfigurationTimeBase\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Com_PbCfg.h"\r
#include "Com_RunTest.h"\r
\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0xFF,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_EngineChangeSpeed,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_SIL2MESSAGE,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- //.ComSignalEndianess = BIG_ENDIAN,\r
+ //.ComSignalEndianess = COM_BIG_ENDIAN,\r
//.ComSignalInitValue = 0xFF,\r
//.ComSignalLength = 0,\r
//.ComSignalType = UINT16,\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef _COM_PBCFG_H\r
#define _COM_PBCFG_H\r
\r
* Specification: Autosar v2.0.1, Final\r
*/\r
\r
-#ifndef _DET_CFG_H_\r
-#define _DET_CFG_H_\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H\r
\r
#define DET_ENABLE_CALLBACKS STD_ON /**< Enable to use callback on errors */\r
#define DET_USE_RAMLOG STD_ON /**< Enable to log DET errors to ramlog */\r
#define DET_RAMLOG_SIZE (32) /**< Number of entries in ramlog */\r
#define DET_NUMBER_OF_CALLBACKS (5) /**< Number of callbacks */\r
\r
-#endif /*_DET_CFG_H_*/\r
+#endif /*DET_CFG_H*/\r
/** @} */\r
/** @file Dio_Cfg.h\r
* Definitions of configuration parameters for the DIO Driver.\r
*/\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DIO_CFG_H_\r
#define DIO_CFG_H_\r
\r
\r
// Channels \r
extern const Dio_ChannelType DioChannelConfigData[];\r
-#define CHANNEL_PTR (&DioChannelConfigData)\r
-\r
// Port\r
extern const Dio_PortType DioPortConfigData[];\r
-#define PORT_PTR (&DioPortConfigData)\r
-\r
// Channel group\r
extern const Dio_ChannelGroupType DioConfigData[];\r
-#define CHANNEL_GRP_PTR (&DioConfigData)\r
\r
// Mapping of logical ports to physical \r
#ifdef CFG_BRD_MPC5516IT\r
\r
// Channels \r
-#define LEDS_LED4 (DIO_CHANNEL_D4)\r
-#define LEDS_LED5 (DIO_CHANNEL_D5)\r
+#define DIO_CHANNEL_NAME_LEDS_LED4 (DIO_CHANNEL_D4)\r
+#define DIO_CHANNEL_NAME_LEDS_LED5 (DIO_CHANNEL_D5)\r
+\r
+// Standard board test led\r
+#define DIO_CHANNEL_NAME_BOARD_LED DIO_CHANNEL_NAME_LEDS_LED4\r
+\r
\r
// Port\r
-#define LED_PORT (DIO_PORT_D)\r
+#define DIO_PORT_NAME_LED_PORT (DIO_PORT_D)\r
\r
// Channel group\r
-#define LED_GRP_PTR (&DioConfigData[0])\r
+#define DIO_GROUP_NAME_LED_GRP_PTR (&DioConfigData[0])\r
\r
#else\r
//\r
// Channels\r
// \r
-#define CONTROL_BUS_EN \r
-#define CONTROL_BUS_STB\r
-#define CONTROL_BUS_ERR\r
-#define CONTROL_BUS_S_PLUS_ST\r
-#define CONTROL_BUS_S_MINUS_ST\r
-#define CONTROL_BUS_S_PLUS_IN\r
+#define DIO_CONTROL_BUS_EN \r
+#define DIO_CONTROL_BUS_STB\r
+#define DIO_CONTROL_BUS_ERR\r
+#define DIO_CONTROL_BUS_S_PLUS_ST\r
+#define DIO_CONTROL_BUS_S_MINUS_ST\r
+#define DIO_CONTROL_BUS_S_PLUS_IN\r
\r
-#define MULTILINK_SO_IN\r
-#define MULTILINK_SO_ST\r
+#define DIO_MULTILINK_SO_IN\r
+#define DIO_MULTILINK_SO_ST\r
\r
-#define DATALINK_CANERR\r
-#define DATALINK_CANEN\r
-#define DATALINK_CANSTB\r
+#define DIO_DATALINK_CANERR\r
+#define DIO_DATALINK_CANEN\r
+#define DIO_DATALINK_CANSTB\r
\r
-#define RF_PWM\r
-#define RF_C1\r
-#define RF_C2\r
+#define DIO_RF_PWM\r
+#define DIO_RF_C1\r
+#define DIO_RF_C2\r
\r
-#define IO_SOUND_EN\r
-#define IO_SOUND\r
+#define DIO_IO_SOUND_EN\r
+#define DIO_IO_SOUND\r
\r
//\r
// Channel groups\r
//\r
-#define CONTROL_BUS (DioConfigData)\r
-#define MULTILINK_BUS (DioConfigData)\r
-#define RF (DioConfigData)\r
-#define IO (DioConfigData)\r
+#define DIO_CONTROL_BUS (DioConfigData)\r
+#define DIO_MULTILINK_BUS (DioConfigData)\r
+#define DIO_RF (DioConfigData)\r
+#define DIO_IO (DioConfigData)\r
\r
//\r
// Port mapping\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Dio.h"\r
#include "Dio_Cfg.h"\r
\r
const Dio_ChannelType DioChannelConfigData[] =\r
-{ LEDS_LED4, LEDS_LED5, DIO_END_OF_LIST, };\r
+{ DIO_CHANNEL_NAME_LEDS_LED4, DIO_CHANNEL_NAME_LEDS_LED5, DIO_END_OF_LIST, };\r
\r
const Dio_PortType DioPortConfigData[] =\r
-{ LED_PORT, DIO_END_OF_LIST };\r
+{ DIO_PORT_NAME_LED_PORT, DIO_END_OF_LIST };\r
\r
const Dio_ChannelGroupType DioConfigData[] =\r
{\r
- { .port = LED_PORT, .offset = 4, .mask = 0x30, },\r
+ { .port = DIO_PORT_NAME_LED_PORT, .offset = 4, .mask = 0x30, },\r
{ .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
};\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Dma.h"\r
\r
const Dma_MuxConfigType DmaMuxConfig [DMA_NUMBER_OF_CHANNELS] =\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DMA_CFG_H_\r
#define DMA_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef EEP_CFG_H_\r
#define EEP_CFG_H_\r
\r
// This parameter is the number of bytes written within one job processing cycle in fast mode\r
Eep_LengthType EepFastWriteBlockSize;\r
\r
+ // This parameter is the EEPROM page size, i.e. number of bytes.
+ Eep_LengthType EepPageSize;
+
// This parameter is the EEPROM device base address.\r
Eep_AddressType EepBaseAddress;\r
} Eep_ConfigType;\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Eep.h"\r
#include "Spi.h"\r
#include "Spi_Cfg.h"\r
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#undef DEBUG_LVL\r
#define DEBUG_LVL DEBUG_LOW\r
.EepJobCallCycle = 0.2,\r
\r
// This parameter is the used size of EEPROM device in bytes.\r
- .EepSize = 0x8000,\r
+// .EepSize = 0x8000,\r
+ .EepSize = 0x2000,\r
\r
// This parameter is a reference to a callback function for positive job result\r
.Eep_JobEndNotification = &_JobEndNotify,\r
// This parameter is the default EEPROM device mode after initialization.\r
.EepDefaultMode = MEMIF_MODE_FAST,\r
\r
+ // Number of bytes read within one job processing cycle in normal mode.
+ .EepNormalReadBlockSize = 4,
+
// This parameter is the number of bytes read within one job processing cycle in fast mode\r
.EepFastReadBlockSize = 64,\r
\r
- .EepNormalReadBlockSize = 4,\r
-\r
// Number of bytes written within one job processing cycle in normal mode.\r
.EepNormalWriteBlockSize = 1,\r
\r
+ // This parameter is the number of bytes written within one job processing cycle in fast mode
+ .EepFastWriteBlockSize = 64,
+
// This parameter is a reference to a callback function for negative job result\r
.Eep_JobErrorNotification = &_JobErrorNotify,\r
\r
- // This parameter is the number of bytes written within one job processing cycle in fast mode\r
- .EepFastWriteBlockSize = 64,\r
+ // This parameter is the EEPROM page size, i.e. number of bytes.
+ .EepPageSize = 64,
\r
// This parameter is the EEPROM device base address.\r
.EepBaseAddress = 0\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Eep.h"\r
#include "Spi.h"\r
#include "Spi_Cfg.h"\r
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#undef DEBUG_LVL\r
#define DEBUG_LVL DEBUG_LOW\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Fls.h"\r
#include <stdlib.h>\r
\r
* Definitions of configuration parameters for Flash Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef FLS_CFG_H_\r
#define FLS_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Fls.h"\r
#include <stdlib.h>\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef FLS_SST25XX_CFG_H_\r
#define FLS_SST25XX_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Gpt.h"\r
#include "Gpt_Cfg.h"\r
#include <stdlib.h>\r
* Definitions of configuration parameters for GPT Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef GPT_CFG_H_\r
#define GPT_CFG_H_\r
#include "Std_Types.h"\r
* Definitions of configuration parameters for LIN Interface.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef LINIF_CFG_H_\r
#define LINIF_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "LinIf_Cfg.h"\r
#include "Lin_Cfg.h"\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef LINSM_CFG_H_\r
#define LINSM_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "LinSM_Cfg.h"\r
#include "LinIf_Cfg.h"\r
#include "Lin_Cfg.h"\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
* Definitions of configuration parameters for LIN Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef LIN_CFG_H_\r
#define LIN_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Mcu.h"\r
#include "Lin.h"\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Lin_Cfg.h"\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
* Definitions of configuration parameters for MCU Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_H_\r
#define MCU_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#define PDUR_MODULE_ID 51\r
#define PDUR_INSTANCE_ID 0\r
\r
#endif\r
\r
// Interfaces\r
-#define PDUR_CANIF_SUPPORT\r
-//#define PDUR_CANTP_SUPPORT\r
-//#define PDUR_FRIF_SUPPORT\r
-//#define PDUR_FRTP_SUPPORT\r
-#define PDUR_LINIF_SUPPORT\r
-//#define PDUR_LINTP_SUPPORT\r
-#define PDUR_COM_SUPPORT\r
-#define PDUR_DCM_SUPPORT\r
+#define PDUR_CANIF_SUPPORT STD_ON\r
+#define PDUR_CANTP_SUPPORT STD_OFF\r
+#define PDUR_FRIF_SUPPORT STD_OFF\r
+#define PDUR_FRTP_SUPPORT STD_OFF\r
+#define PDUR_LINIF_SUPPORT STD_OFF\r
+#define PDUR_LINTP_SUPPORT STD_OFF\r
+#define PDUR_COM_SUPPORT STD_ON\r
+#define PDUR_DCM_SUPPORT STD_OFF\r
\r
\r
//#define PDUR_MAX_TX_BUFFER_NUMBER\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#define PDUR_ZERO_COST_OPERATION STD_ON\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Port_Cfg.h"\r
\r
// All: PA,OBE,IBE,ODE,HYS,SRC,WPE,WPS\r
// Input: PA,OBE,IBE,HYS,WPE,WPS\r
// Output: PA,OBE,IBE,ODE,SRC,(WPE,WPS)\r
\r
-#define PCR_PWM PCR_BOOTCFG\r
+#define PCR_PWM PORT_PCR_BOOTCFG\r
#define PCR_ADC (0)\r
-#define PCR_IO_INPUT PCR_BOOTCFG\r
-#define PCR_IO_OUTPUT OBE_ENABLE\r
-#define PCR_CAN (0)\r
-#define PCR_SPI PCR_BOOTCFG\r
-#define PCR_I2C PCR_BOOTCFG\r
+#define PCR_IO_INPUT PORT_PCR_BOOTCFG\r
+#define PCR_IO_OUTPUT PORT_OBE_ENABLE\r
+#define PCR_CAN (0)\r
+#define PCR_SPI PORT_PCR_BOOTCFG\r
+#define PCR_I2C PORT_PCR_BOOTCFG\r
\r
\r
const uint16_t PortPadConfigData[] =\r
{\r
// pad 0-15\r
- PCR_ADC|PA_FUNC1, /* PA0, AN0 */\r
- PCR_RESET, /* PA1 */\r
- PCR_RESET, /* PA2 */\r
- PCR_RESET, /* PA3 */\r
- PCR_RESET, /* PA4 */\r
- PCR_RESET, /* PA5 */\r
- PCR_RESET, /* PA6, */\r
- PCR_RESET, /* PA7(input only) */\r
- PCR_RESET, /* PA8(input only) */\r
- PCR_RESET, /* PA9(input only) */\r
- PCR_RESET, /* PA10(input only) */\r
- PCR_RESET, /* PA11(input only) */\r
- PCR_RESET, /* PA12(input only) */\r
- PCR_RESET, /* PA13(input only) */\r
- PCR_RESET, /* PA14(input only) */\r
- PCR_RESET, /* PA15(input only) */\r
+ PCR_ADC|PORT_PA_FUNC1, /* PA0, AN0 */\r
+ PORT_PCR_RESET, /* PA1 */\r
+ PORT_PCR_RESET, /* PA2 */\r
+ PORT_PCR_RESET, /* PA3 */\r
+ PORT_PCR_RESET, /* PA4 */\r
+ PORT_PCR_RESET, /* PA5 */\r
+ PORT_PCR_RESET, /* PA6, */\r
+ PORT_PCR_RESET, /* PA7(input only) */\r
+ PORT_PCR_RESET, /* PA8(input only) */\r
+ PORT_PCR_RESET, /* PA9(input only) */\r
+ PORT_PCR_RESET, /* PA10(input only) */\r
+ PORT_PCR_RESET, /* PA11(input only) */\r
+ PORT_PCR_RESET, /* PA12(input only) */\r
+ PORT_PCR_RESET, /* PA13(input only) */\r
+ PORT_PCR_RESET, /* PA14(input only) */\r
+ PORT_PCR_RESET, /* PA15(input only) */\r
\r
// pad 16-31\r
- PCR_RESET, /* PB0 */\r
- PCR_RESET, /* PB1 */\r
- PCR_RESET, /* PB2 */\r
- PCR_RESET, /* PB3 */\r
- PCR_RESET, /* PB4 */\r
- PCR_RESET, /* PB5 */\r
- PCR_RESET, /* PB6 */\r
- PCR_RESET, /* PB7 */\r
- PCR_RESET, /* PB8 */\r
- PCR_RESET, /* PB9 */\r
- PCR_RESET, /* PB10 */\r
- PCR_RESET, /* PB11 */\r
- PCR_RESET, /* PB12 */\r
- PCR_RESET, /* PB13 */\r
- PCR_RESET, /* PB14 */\r
- PCR_RESET, /* PB15 */\r
+ PORT_PCR_RESET, /* PB0 */\r
+ PORT_PCR_RESET, /* PB1 */\r
+ PORT_PCR_RESET, /* PB2 */\r
+ PORT_PCR_RESET, /* PB3 */\r
+ PORT_PCR_RESET, /* PB4 */\r
+ PORT_PCR_RESET, /* PB5 */\r
+ PORT_PCR_RESET, /* PB6 */\r
+ PORT_PCR_RESET, /* PB7 */\r
+ PORT_PCR_RESET, /* PB8 */\r
+ PORT_PCR_RESET, /* PB9 */\r
+ PORT_PCR_RESET, /* PB10 */\r
+ PORT_PCR_RESET, /* PB11 */\r
+ PORT_PCR_RESET, /* PB12 */\r
+ PORT_PCR_RESET, /* PB13 */\r
+ PORT_PCR_RESET, /* PB14 */\r
+ PORT_PCR_RESET, /* PB15 */\r
\r
// pad 32-47\r
- PCR_RESET, /* PC0/emios0 */\r
- PCR_RESET, // PC1\r
- PCR_RESET, // PC2\r
- PCR_RESET, /* PC3 */\r
- PCR_RESET, /* PC4 */\r
- PCR_RESET, /* PC5 */\r
- PCR_RESET, /* PC6 */\r
- PCR_RESET, /* PC7 */\r
- PCR_RESET, /* PC8 */\r
- PCR_RESET, /* PC9 */\r
- PCR_RESET, /* PC10 */\r
- PCR_RESET, /* PC11 */\r
- PCR_RESET, /* PC12 */\r
- PCR_RESET, /* PC13 */\r
- PCR_RESET, /* PC14 */\r
- PCR_RESET, /* PC15 */\r
+ PORT_PCR_RESET, /* PC0/emios0 */\r
+ PORT_PCR_RESET, // PC1\r
+ PORT_PCR_RESET, // PC2\r
+ PORT_PCR_RESET, /* PC3 */\r
+ PORT_PCR_RESET, /* PC4 */\r
+ PORT_PCR_RESET, /* PC5 */\r
+ PORT_PCR_RESET, /* PC6 */\r
+ PORT_PCR_RESET, /* PC7 */\r
+ PORT_PCR_RESET, /* PC8 */\r
+ PORT_PCR_RESET, /* PC9 */\r
+ PORT_PCR_RESET, /* PC10 */\r
+ PORT_PCR_RESET, /* PC11 */\r
+ PORT_PCR_RESET, /* PC12 */\r
+ PORT_PCR_RESET, /* PC13 */\r
+ PORT_PCR_RESET, /* PC14 */\r
+ PORT_PCR_RESET, /* PC15 */\r
\r
// pad 48-63\r
- (PCR_CAN|PA_FUNC1), /* PD0, CAN_A, Tx */\r
- (PCR_CAN|PA_FUNC1), /* PD1, CAN_A, Rx */\r
- PCR_BOOTCFG, /* PD2 */\r
- PCR_RESET, /* PD3 */\r
+ (PCR_CAN|PORT_PA_FUNC1), /* PD0, CAN_A, Tx */\r
+ (PCR_CAN|PORT_PA_FUNC1), /* PD1, CAN_A, Rx */\r
+ PORT_PCR_BOOTCFG, /* PD2 */\r
+ PORT_PCR_RESET, /* PD3 */\r
PCR_IO_OUTPUT, /* PD4, LED */\r
PCR_IO_OUTPUT, /* PD5, LED */\r
- PCR_RESET, /* PD6 , SCI_RS232??*/\r
- PCR_RESET, /* PD7 , SCI_RS232??*/\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD8 LIN TX */\r
- (PA_FUNC1 | IBE_ENABLE), /* PD9 LIN RX */\r
- PCR_RESET, /* PD10 */\r
- PCR_RESET, /* PD11 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD12 SPIB_CS0 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD13 SPIB_CLK*/\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD14 SPIB_SO*/\r
- (PA_FUNC1 | IBE_ENABLE), /* PD15 SPIB_SI*/\r
+ PORT_PCR_RESET, /* PD6 , SCI_RS232??*/\r
+ PORT_PCR_RESET, /* PD7 , SCI_RS232??*/\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD8 LIN TX */\r
+ (PORT_PA_FUNC1 | PORT_IBE_ENABLE), /* PD9 LIN RX */\r
+ PORT_PCR_RESET, /* PD10 */\r
+ PORT_PCR_RESET, /* PD11 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD12 SPIB_CS0 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD13 SPIB_CLK*/\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD14 SPIB_SO*/\r
+ (PORT_PA_FUNC1 | PORT_IBE_ENABLE), /* PD15 SPIB_SI*/\r
\r
// pad 64-79\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE0 SPIA_CS1 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE1 SPIA_CS2*/\r
- PCR_RESET, /* PE2 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE3 SPIA_CLK*/\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE4 SPIA_SO*/\r
- (PA_FUNC1 | IBE_ENABLE), /* PE5 SPIA_SI*/\r
- PCR_RESET, /* PE6 */\r
- PCR_RESET, /* PE7 */\r
- PCR_RESET, /* PE8 */\r
- PCR_RESET, /* PE9 */\r
- PCR_RESET, /* PE10 */\r
- PCR_RESET, /* PE11 */\r
- PCR_RESET, /* PE12 */\r
- PCR_RESET, /* PE13 */\r
- PCR_RESET, /* PE14 */\r
- PCR_RESET, /* PE15 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE0 SPIA_CS1 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE1 SPIA_CS2*/\r
+ PORT_PCR_RESET, /* PE2 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE3 SPIA_CLK*/\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE4 SPIA_SO*/\r
+ (PORT_PA_FUNC1 | PORT_IBE_ENABLE), /* PE5 SPIA_SI*/\r
+ PORT_PCR_RESET, /* PE6 */\r
+ PORT_PCR_RESET, /* PE7 */\r
+ PORT_PCR_RESET, /* PE8 */\r
+ PORT_PCR_RESET, /* PE9 */\r
+ PORT_PCR_RESET, /* PE10 */\r
+ PORT_PCR_RESET, /* PE11 */\r
+ PORT_PCR_RESET, /* PE12 */\r
+ PORT_PCR_RESET, /* PE13 */\r
+ PORT_PCR_RESET, /* PE14 */\r
+ PORT_PCR_RESET, /* PE15 */\r
\r
// pad 80-95\r
- PCR_RESET, /* PF0 */\r
- PCR_RESET, /* PF1 */\r
- PCR_RESET, /* PF2 */\r
- PCR_RESET, /* PF3 */\r
- PCR_RESET, /* PF4 */\r
- PCR_RESET, /* PF5 */\r
- PCR_RESET, /* PF6 */\r
- PCR_RESET, /* PF7 */\r
- PCR_RESET, /* PF8 */\r
- PCR_RESET, /* PF9 */\r
- PCR_RESET, /* PF10 */\r
- PCR_RESET, /* PF11 */\r
- PA_FUNC2|OBE_ENABLE|PULL_UP, /* PF12 SCI_D Transmit, J1708 Tx*/\r
- PA_FUNC2|IBE_ENABLE|PULL_UP, /* PF13 SCI_D Receive, J1708 Rx*/\r
- PCR_RESET, /* PF14 */\r
- PCR_RESET, /* PF15 */\r
+ PORT_PCR_RESET, /* PF0 */\r
+ PORT_PCR_RESET, /* PF1 */\r
+ PORT_PCR_RESET, /* PF2 */\r
+ PORT_PCR_RESET, /* PF3 */\r
+ PORT_PCR_RESET, /* PF4 */\r
+ PORT_PCR_RESET, /* PF5 */\r
+ PORT_PCR_RESET, /* PF6 */\r
+ PORT_PCR_RESET, /* PF7 */\r
+ PORT_PCR_RESET, /* PF8 */\r
+ PORT_PCR_RESET, /* PF9 */\r
+ PORT_PCR_RESET, /* PF10 */\r
+ PORT_PCR_RESET, /* PF11 */\r
+ PORT_PA_FUNC2|PORT_OBE_ENABLE|PORT_PULL_UP, /* PF12 SCI_D Transmit, J1708 Tx*/\r
+ PORT_PA_FUNC2|PORT_IBE_ENABLE|PORT_PULL_UP, /* PF13 SCI_D Receive, J1708 Rx*/\r
+ PORT_PCR_RESET, /* PF14 */\r
+ PORT_PCR_RESET, /* PF15 */\r
\r
// pad 96-111\r
- PCR_RESET, /* PG0 */\r
- PA_FUNC2|IBE_ENABLE|PULL_UP, /* PG1 eMIOS[17], J1708 Edgedetect*/\r
- PCR_RESET, /* PG2 */\r
- PCR_RESET, /* PG3 */\r
- PCR_RESET, /* PG4 */\r
- PCR_RESET, /* PG5 */\r
- PCR_RESET, /* PG6 */\r
- PCR_RESET, /* PG7 */\r
- PCR_RESET, /* PG8 */\r
- PCR_RESET, /* PG9 */\r
- PCR_RESET, /* PG10 */\r
- PCR_RESET, /* PG11 */\r
- PCR_RESET, /* PG12 */\r
- PCR_RESET, /* PG13 */\r
- PCR_RESET, /* PG14 */\r
- PCR_RESET, /* PG15 */\r
+ PORT_PCR_RESET, /* PG0 */\r
+ PORT_PA_FUNC2|PORT_IBE_ENABLE|PORT_PULL_UP, /* PG1 eMIOS[17], J1708 Edgedetect*/\r
+ PORT_PCR_RESET, /* PG2 */\r
+ PORT_PCR_RESET, /* PG3 */\r
+ PORT_PCR_RESET, /* PG4 */\r
+ PORT_PCR_RESET, /* PG5 */\r
+ PORT_PCR_RESET, /* PG6 */\r
+ PORT_PCR_RESET, /* PG7 */\r
+ PORT_PCR_RESET, /* PG8 */\r
+ PORT_PCR_RESET, /* PG9 */\r
+ PORT_PCR_RESET, /* PG10 */\r
+ PORT_PCR_RESET, /* PG11 */\r
+ PORT_PCR_RESET, /* PG12 */\r
+ PORT_PCR_RESET, /* PG13 */\r
+ PORT_PCR_RESET, /* PG14 */\r
+ PORT_PCR_RESET, /* PG15 */\r
\r
// pad 112-127\r
- PCR_RESET, /* PH0 */\r
- PCR_RESET, /* PH1 */\r
- PCR_RESET, /* PH2 */\r
- PCR_RESET, /* PH3 */\r
- PCR_RESET, /* PH4 */\r
- PCR_RESET, /* PH5 */\r
- PCR_RESET, /* PH6 */\r
- PCR_RESET, /* PH7 */\r
- PCR_RESET, /* PH8 */\r
- PCR_RESET, /* PH9 */\r
- PCR_RESET, /* PH10 */\r
- PCR_RESET, /* PH11 */\r
- PCR_RESET, /* PH12 */\r
- PCR_RESET, /* PH13 */\r
- PCR_RESET, /* PH14 */\r
- PCR_RESET, /* PH15 */\r
+ PORT_PCR_RESET, /* PH0 */\r
+ PORT_PCR_RESET, /* PH1 */\r
+ PORT_PCR_RESET, /* PH2 */\r
+ PORT_PCR_RESET, /* PH3 */\r
+ PORT_PCR_RESET, /* PH4 */\r
+ PORT_PCR_RESET, /* PH5 */\r
+ PORT_PCR_RESET, /* PH6 */\r
+ PORT_PCR_RESET, /* PH7 */\r
+ PORT_PCR_RESET, /* PH8 */\r
+ PORT_PCR_RESET, /* PH9 */\r
+ PORT_PCR_RESET, /* PH10 */\r
+ PORT_PCR_RESET, /* PH11 */\r
+ PORT_PCR_RESET, /* PH12 */\r
+ PORT_PCR_RESET, /* PH13 */\r
+ PORT_PCR_RESET, /* PH14 */\r
+ PORT_PCR_RESET, /* PH15 */\r
\r
// pad 128-143\r
- PCR_RESET, /* PJ0 */\r
- PCR_RESET, /* PJ1 */\r
- PCR_RESET, /* PJ2 */\r
- PCR_RESET, /* PJ3 */\r
- PCR_RESET, /* PJ4 */\r
- PCR_RESET, /* PJ5 */\r
- PCR_RESET, /* PJ6 */\r
- PCR_RESET, /* PJ7 */\r
- PCR_RESET, /* PJ8 */\r
- PCR_RESET, /* PJ9 */\r
- PCR_RESET, /* PJ10 */\r
- PCR_RESET, /* PJ11 */\r
- PCR_RESET, /* PJ12 */\r
- PCR_RESET, /* PJ13 */\r
- PCR_RESET, /* PJ14 */\r
- PCR_RESET, /* PJ15 */\r
+ PORT_PCR_RESET, /* PJ0 */\r
+ PORT_PCR_RESET, /* PJ1 */\r
+ PORT_PCR_RESET, /* PJ2 */\r
+ PORT_PCR_RESET, /* PJ3 */\r
+ PORT_PCR_RESET, /* PJ4 */\r
+ PORT_PCR_RESET, /* PJ5 */\r
+ PORT_PCR_RESET, /* PJ6 */\r
+ PORT_PCR_RESET, /* PJ7 */\r
+ PORT_PCR_RESET, /* PJ8 */\r
+ PORT_PCR_RESET, /* PJ9 */\r
+ PORT_PCR_RESET, /* PJ10 */\r
+ PORT_PCR_RESET, /* PJ11 */\r
+ PORT_PCR_RESET, /* PJ12 */\r
+ PORT_PCR_RESET, /* PJ13 */\r
+ PORT_PCR_RESET, /* PJ14 */\r
+ PORT_PCR_RESET, /* PJ15 */\r
\r
// pad 144-145\r
- PCR_RESET, /* PK0 (input only) */\r
- PCR_RESET, /* PK1 (input only)*/\r
+ PORT_PCR_RESET, /* PK0 (input only) */\r
+ PORT_PCR_RESET, /* PK1 (input only)*/\r
};\r
\r
\r
-#define GPDO_RESET 0\r
+#define PORT_GPDO_RESET 0\r
\r
const uint8_t PortOutConfigData[] =\r
{\r
// pad 16-31\r
- GPDO_RESET, /* PB0 */\r
- GPDO_RESET, /* PB1 */\r
- GPDO_RESET, /* PB2 */\r
- GPDO_RESET, /* PB3 */\r
- GPDO_RESET, /* PB4 */\r
- GPDO_RESET, /* PB5 */\r
- GPDO_RESET, /* PB6 */\r
- GPDO_RESET, /* PB7 */\r
- GPDO_RESET, /* PB8 */\r
- GPDO_RESET, /* PB9 */\r
- GPDO_RESET, /* PB10 */\r
- GPDO_RESET, /* PB11 */\r
- GPDO_RESET, /* PB12 */\r
- GPDO_RESET, /* PB13 */\r
- GPDO_RESET, /* PB14 */\r
- GPDO_RESET, /* PB15 */\r
+ PORT_GPDO_RESET, /* PB0 */\r
+ PORT_GPDO_RESET, /* PB1 */\r
+ PORT_GPDO_RESET, /* PB2 */\r
+ PORT_GPDO_RESET, /* PB3 */\r
+ PORT_GPDO_RESET, /* PB4 */\r
+ PORT_GPDO_RESET, /* PB5 */\r
+ PORT_GPDO_RESET, /* PB6 */\r
+ PORT_GPDO_RESET, /* PB7 */\r
+ PORT_GPDO_RESET, /* PB8 */\r
+ PORT_GPDO_RESET, /* PB9 */\r
+ PORT_GPDO_RESET, /* PB10 */\r
+ PORT_GPDO_RESET, /* PB11 */\r
+ PORT_GPDO_RESET, /* PB12 */\r
+ PORT_GPDO_RESET, /* PB13 */\r
+ PORT_GPDO_RESET, /* PB14 */\r
+ PORT_GPDO_RESET, /* PB15 */\r
\r
// pad 32-47\r
- GPDO_RESET, /* PC0 */\r
- GPDO_RESET, /* PC1 */\r
- GPDO_RESET, /* PC2 */\r
- GPDO_RESET, /* PC3 */\r
- GPDO_RESET, /* PC4 */\r
- GPDO_RESET, /* PC5 */\r
- GPDO_RESET, /* PC6 */\r
- GPDO_RESET, /* PC7 */\r
- GPDO_RESET, /* PC8 */\r
- GPDO_RESET, /* PC9 */\r
- GPDO_RESET, /* PC10 */\r
- GPDO_RESET, /* PC11 */\r
- GPDO_RESET, /* PC12 */\r
- GPDO_RESET, /* PC13 */\r
- GPDO_RESET, /* PC14 */\r
- GPDO_RESET, /* PC15 */\r
+ PORT_GPDO_RESET, /* PC0 */\r
+ PORT_GPDO_RESET, /* PC1 */\r
+ PORT_GPDO_RESET, /* PC2 */\r
+ PORT_GPDO_RESET, /* PC3 */\r
+ PORT_GPDO_RESET, /* PC4 */\r
+ PORT_GPDO_RESET, /* PC5 */\r
+ PORT_GPDO_RESET, /* PC6 */\r
+ PORT_GPDO_RESET, /* PC7 */\r
+ PORT_GPDO_RESET, /* PC8 */\r
+ PORT_GPDO_RESET, /* PC9 */\r
+ PORT_GPDO_RESET, /* PC10 */\r
+ PORT_GPDO_RESET, /* PC11 */\r
+ PORT_GPDO_RESET, /* PC12 */\r
+ PORT_GPDO_RESET, /* PC13 */\r
+ PORT_GPDO_RESET, /* PC14 */\r
+ PORT_GPDO_RESET, /* PC15 */\r
\r
// pad 48-63\r
- GPDO_RESET, /* PD0 */\r
- GPDO_RESET, /* PD1 */\r
- GPDO_RESET, /* PD2 */\r
- GPDO_RESET, /* PD3 */\r
- GPDO_RESET, /* PD4 */\r
- GPDO_RESET, /* PD5 */\r
- GPDO_RESET, /* PD6 */\r
- GPDO_RESET, /* PD7 */\r
- GPDO_RESET, /* PD8 */\r
- GPDO_RESET, /* PD9 */\r
- GPDO_RESET, /* PD10 */\r
- GPDO_RESET, /* PD11 */\r
- GPDO_RESET, /* PD12 */\r
- GPDO_RESET, /* PD13 */\r
- GPDO_RESET, /* PD14 */\r
- GPDO_RESET, /* PD15 */\r
+ PORT_GPDO_RESET, /* PD0 */\r
+ PORT_GPDO_RESET, /* PD1 */\r
+ PORT_GPDO_RESET, /* PD2 */\r
+ PORT_GPDO_RESET, /* PD3 */\r
+ PORT_GPDO_RESET, /* PD4 */\r
+ PORT_GPDO_RESET, /* PD5 */\r
+ PORT_GPDO_RESET, /* PD6 */\r
+ PORT_GPDO_RESET, /* PD7 */\r
+ PORT_GPDO_RESET, /* PD8 */\r
+ PORT_GPDO_RESET, /* PD9 */\r
+ PORT_GPDO_RESET, /* PD10 */\r
+ PORT_GPDO_RESET, /* PD11 */\r
+ PORT_GPDO_RESET, /* PD12 */\r
+ PORT_GPDO_RESET, /* PD13 */\r
+ PORT_GPDO_RESET, /* PD14 */\r
+ PORT_GPDO_RESET, /* PD15 */\r
\r
// pad 64-79\r
- GPDO_RESET, /* PE0 */\r
- GPDO_RESET, /* PE1 */\r
- GPDO_RESET, /* PE2 */\r
- GPDO_RESET, /* PE3 */\r
- GPDO_RESET, /* PE4 */\r
- GPDO_RESET, /* PE5 */\r
- GPDO_RESET, /* PE6 */\r
- GPDO_RESET, /* PE7 */\r
- GPDO_RESET, /* PE8 */\r
- GPDO_RESET, /* PE9 */\r
- GPDO_RESET, /* PE10 */\r
- GPDO_RESET, /* PE11 */\r
- GPDO_RESET, /* PE12 */\r
- GPDO_RESET, /* PE13 */\r
- GPDO_RESET, /* PE14 */\r
- GPDO_RESET, /* PE15 */\r
+ PORT_GPDO_RESET, /* PE0 */\r
+ PORT_GPDO_RESET, /* PE1 */\r
+ PORT_GPDO_RESET, /* PE2 */\r
+ PORT_GPDO_RESET, /* PE3 */\r
+ PORT_GPDO_RESET, /* PE4 */\r
+ PORT_GPDO_RESET, /* PE5 */\r
+ PORT_GPDO_RESET, /* PE6 */\r
+ PORT_GPDO_RESET, /* PE7 */\r
+ PORT_GPDO_RESET, /* PE8 */\r
+ PORT_GPDO_RESET, /* PE9 */\r
+ PORT_GPDO_RESET, /* PE10 */\r
+ PORT_GPDO_RESET, /* PE11 */\r
+ PORT_GPDO_RESET, /* PE12 */\r
+ PORT_GPDO_RESET, /* PE13 */\r
+ PORT_GPDO_RESET, /* PE14 */\r
+ PORT_GPDO_RESET, /* PE15 */\r
\r
// pad 80-95\r
- GPDO_RESET, /* PF0 */\r
- GPDO_RESET, /* PF1 */\r
- GPDO_RESET, /* PF2 */\r
- GPDO_RESET, /* PF3 */\r
- GPDO_RESET, /* PF4 */\r
- GPDO_RESET, /* PF5 */\r
- GPDO_RESET, /* PF6 */\r
- GPDO_RESET, /* PF7 */\r
- GPDO_RESET, /* PF8 */\r
- GPDO_RESET, /* PF9 */\r
- GPDO_RESET, /* PF10 */\r
- GPDO_RESET, /* PF11 */\r
- GPDO_RESET, /* PF12 */\r
- GPDO_RESET, /* PF13 */\r
- GPDO_RESET, /* PF14 */\r
- GPDO_RESET, /* PF15 */\r
+ PORT_GPDO_RESET, /* PF0 */\r
+ PORT_GPDO_RESET, /* PF1 */\r
+ PORT_GPDO_RESET, /* PF2 */\r
+ PORT_GPDO_RESET, /* PF3 */\r
+ PORT_GPDO_RESET, /* PF4 */\r
+ PORT_GPDO_RESET, /* PF5 */\r
+ PORT_GPDO_RESET, /* PF6 */\r
+ PORT_GPDO_RESET, /* PF7 */\r
+ PORT_GPDO_RESET, /* PF8 */\r
+ PORT_GPDO_RESET, /* PF9 */\r
+ PORT_GPDO_RESET, /* PF10 */\r
+ PORT_GPDO_RESET, /* PF11 */\r
+ PORT_GPDO_RESET, /* PF12 */\r
+ PORT_GPDO_RESET, /* PF13 */\r
+ PORT_GPDO_RESET, /* PF14 */\r
+ PORT_GPDO_RESET, /* PF15 */\r
\r
// pad 96-111\r
- GPDO_RESET, /* PG0 */\r
- GPDO_RESET, /* PG1 */\r
- GPDO_RESET, /* PG2 */\r
- GPDO_RESET, /* PG3 */\r
- GPDO_RESET, /* PG4 */\r
- GPDO_RESET, /* PG5 */\r
- GPDO_RESET, /* PG6 */\r
- GPDO_RESET, /* PG7 */\r
- GPDO_RESET, /* PG8 */\r
- GPDO_RESET, /* PG9 */\r
- GPDO_RESET, /* PG10 */\r
- GPDO_RESET, /* PG11 */\r
- GPDO_RESET, /* PG12 */\r
- GPDO_RESET, /* PG13 */\r
- GPDO_RESET, /* PG14 */\r
- GPDO_RESET, /* PG15 */\r
+ PORT_GPDO_RESET, /* PG0 */\r
+ PORT_GPDO_RESET, /* PG1 */\r
+ PORT_GPDO_RESET, /* PG2 */\r
+ PORT_GPDO_RESET, /* PG3 */\r
+ PORT_GPDO_RESET, /* PG4 */\r
+ PORT_GPDO_RESET, /* PG5 */\r
+ PORT_GPDO_RESET, /* PG6 */\r
+ PORT_GPDO_RESET, /* PG7 */\r
+ PORT_GPDO_RESET, /* PG8 */\r
+ PORT_GPDO_RESET, /* PG9 */\r
+ PORT_GPDO_RESET, /* PG10 */\r
+ PORT_GPDO_RESET, /* PG11 */\r
+ PORT_GPDO_RESET, /* PG12 */\r
+ PORT_GPDO_RESET, /* PG13 */\r
+ PORT_GPDO_RESET, /* PG14 */\r
+ PORT_GPDO_RESET, /* PG15 */\r
\r
// pad 112-127\r
- GPDO_RESET, /* PH0 */\r
- GPDO_RESET, /* PH1 */\r
- GPDO_RESET, /* PH2 */\r
- GPDO_RESET, /* PH3 */\r
- GPDO_RESET, /* PH4 */\r
- GPDO_RESET, /* PH5 */\r
- GPDO_RESET, /* PH6 */\r
- GPDO_RESET, /* PH7 */\r
- GPDO_RESET, /* PH8 */\r
- GPDO_RESET, /* PH9 */\r
- GPDO_RESET, /* PH10 */\r
- GPDO_RESET, /* PH11 */\r
- GPDO_RESET, /* PH12 */\r
- GPDO_RESET, /* PH13 */\r
- GPDO_RESET, /* PH14 */\r
- GPDO_RESET, /* PH15 */\r
+ PORT_GPDO_RESET, /* PH0 */\r
+ PORT_GPDO_RESET, /* PH1 */\r
+ PORT_GPDO_RESET, /* PH2 */\r
+ PORT_GPDO_RESET, /* PH3 */\r
+ PORT_GPDO_RESET, /* PH4 */\r
+ PORT_GPDO_RESET, /* PH5 */\r
+ PORT_GPDO_RESET, /* PH6 */\r
+ PORT_GPDO_RESET, /* PH7 */\r
+ PORT_GPDO_RESET, /* PH8 */\r
+ PORT_GPDO_RESET, /* PH9 */\r
+ PORT_GPDO_RESET, /* PH10 */\r
+ PORT_GPDO_RESET, /* PH11 */\r
+ PORT_GPDO_RESET, /* PH12 */\r
+ PORT_GPDO_RESET, /* PH13 */\r
+ PORT_GPDO_RESET, /* PH14 */\r
+ PORT_GPDO_RESET, /* PH15 */\r
\r
// pad 128-143\r
- GPDO_RESET, /* PJ0 */\r
- GPDO_RESET, /* PJ1 */\r
- GPDO_RESET, /* PJ2 */\r
- GPDO_RESET, /* PJ3 */\r
- GPDO_RESET, /* PJ4 */\r
- GPDO_RESET, /* PJ5 */\r
- GPDO_RESET, /* PJ6 */\r
- GPDO_RESET, /* PJ7 */\r
- GPDO_RESET, /* PJ8 */\r
- GPDO_RESET, /* PJ9 */\r
- GPDO_RESET, /* PJ10 */\r
- GPDO_RESET, /* PJ11 */\r
- GPDO_RESET, /* PJ12 */\r
- GPDO_RESET, /* PJ13 */\r
- GPDO_RESET, /* PJ14 */\r
- GPDO_RESET, /* PJ15 */\r
+ PORT_GPDO_RESET, /* PJ0 */\r
+ PORT_GPDO_RESET, /* PJ1 */\r
+ PORT_GPDO_RESET, /* PJ2 */\r
+ PORT_GPDO_RESET, /* PJ3 */\r
+ PORT_GPDO_RESET, /* PJ4 */\r
+ PORT_GPDO_RESET, /* PJ5 */\r
+ PORT_GPDO_RESET, /* PJ6 */\r
+ PORT_GPDO_RESET, /* PJ7 */\r
+ PORT_GPDO_RESET, /* PJ8 */\r
+ PORT_GPDO_RESET, /* PJ9 */\r
+ PORT_GPDO_RESET, /* PJ10 */\r
+ PORT_GPDO_RESET, /* PJ11 */\r
+ PORT_GPDO_RESET, /* PJ12 */\r
+ PORT_GPDO_RESET, /* PJ13 */\r
+ PORT_GPDO_RESET, /* PJ14 */\r
+ PORT_GPDO_RESET, /* PJ15 */\r
};\r
\r
//#define GPDI_RESET 0\r
* Definitions of configuration parameters for Port Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef PORT_CFG_H_\r
#define PORT_CFG_H_\r
\r
#define PORT_VERSION_INFO_API STD_ON\r
/** Enable Development Error Trace */\r
#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Allow Pin mode changes during runtime */\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
/** Build change pin direction API */\r
-#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
\r
/** HW specific symbolic names of pins */\r
typedef enum\r
{\r
- PA0,\r
- PA1,\r
- PA2,\r
- PA3,\r
- PA4,\r
- PA5,\r
- PA6,\r
- PA7,\r
- PA8,\r
- PA9,\r
- PA10,\r
- PA11,\r
- PA12,\r
- PA13,\r
- PA14,\r
- PA15,\r
- PB0,\r
- PB1,\r
- PB2,\r
- PB3,\r
- PB4,\r
- PB5,\r
- PB6,\r
- PB7,\r
- PB8,\r
- PB9,\r
- PB10,\r
- PB11,\r
- PB12,\r
- PB13,\r
- PB14,\r
- PB15,\r
- PC0,\r
- PC1,\r
- PC2,\r
- PC3,\r
- PC4,\r
- PC5,\r
- PC6,\r
- PC7,\r
- PC8,\r
- PC9,\r
- PC10,\r
- PC11,\r
- PC12,\r
- PC13,\r
- PC14,\r
- PC15,\r
- PD0,\r
- PD1,\r
- PD2,\r
- PD3,\r
- PD4,\r
- PD5,\r
- PD6,\r
- PD7,\r
- PD8,\r
- PD9,\r
- PD10,\r
- PD11,\r
- PD12,\r
- PD13,\r
- PD14,\r
- PD15,\r
- PE0,\r
- PE1,\r
- PE2,\r
- PE3,\r
- PE4,\r
- PE5,\r
- PE6,\r
- PE7,\r
- PE8,\r
- PE9,\r
- PE10,\r
- PE11,\r
- PE12,\r
- PE13,\r
- PE14,\r
- PE15,\r
- PF0,\r
- PF1,\r
- PF2,\r
- PF3,\r
- PF4,\r
- PF5,\r
- PF6,\r
- PF7,\r
- PF8,\r
- PF9,\r
- PF10,\r
- PF11,\r
- PF12,\r
- PF13,\r
- PF14,\r
- PF15,\r
- PG0,\r
- PG1,\r
- PG2,\r
- PG3,\r
- PG4,\r
- PG5,\r
- PG6,\r
- PG7,\r
- PG8,\r
- PG9,\r
- PG10,\r
- PG11,\r
- PG12,\r
- PG13,\r
- PG14,\r
- PG15,\r
- PH0,\r
- PH1,\r
- PH2,\r
- PH3,\r
- PH4,\r
- PH5,\r
- PH6,\r
- PH7,\r
- PH8,\r
- PH9,\r
- PH10,\r
- PH11,\r
- PH12,\r
- PH13,\r
- PH14,\r
- PH15,\r
- PJ0,\r
- PJ1,\r
- PJ2,\r
- PJ3,\r
- PJ4,\r
- PJ5,\r
- PJ6,\r
- PJ7,\r
- PJ8,\r
- PJ9,\r
- PJ10,\r
- PJ11,\r
- PJ12,\r
- PJ13,\r
- PJ14,\r
- PJ15,\r
- PK0,\r
- PK1\r
+ PORT_PA0,\r
+ PORT_PA1,\r
+ PORT_PA2,\r
+ PORT_PA3,\r
+ PORT_PA4,\r
+ PORT_PA5,\r
+ PORT_PA6,\r
+ PORT_PA7,\r
+ PORT_PA8,\r
+ PORT_PA9,\r
+ PORT_PA10,\r
+ PORT_PA11,\r
+ PORT_PA12,\r
+ PORT_PA13,\r
+ PORT_PA14,\r
+ PORT_PA15,\r
+ PORT_PB0,\r
+ PORT_PB1,\r
+ PORT_PB2,\r
+ PORT_PB3,\r
+ PORT_PB4,\r
+ PORT_PB5,\r
+ PORT_PB6,\r
+ PORT_PB7,\r
+ PORT_PB8,\r
+ PORT_PB9,\r
+ PORT_PB10,\r
+ PORT_PB11,\r
+ PORT_PB12,\r
+ PORT_PB13,\r
+ PORT_PB14,\r
+ PORT_PB15,\r
+ PORT_PC0,\r
+ PORT_PC1,\r
+ PORT_PC2,\r
+ PORT_PC3,\r
+ PORT_PC4,\r
+ PORT_PC5,\r
+ PORT_PC6,\r
+ PORT_PC7,\r
+ PORT_PC8,\r
+ PORT_PC9,\r
+ PORT_PC10,\r
+ PORT_PC11,\r
+ PORT_PC12,\r
+ PORT_PC13,\r
+ PORT_PC14,\r
+ PORT_PC15,\r
+ PORT_PD0,\r
+ PORT_PD1,\r
+ PORT_PD2,\r
+ PORT_PD3,\r
+ PORT_PD4,\r
+ PORT_PD5,\r
+ PORT_PD6,\r
+ PORT_PD7,\r
+ PORT_PD8,\r
+ PORT_PD9,\r
+ PORT_PD10,\r
+ PORT_PD11,\r
+ PORT_PD12,\r
+ PORT_PD13,\r
+ PORT_PD14,\r
+ PORT_PD15,\r
+ PORT_PE0,\r
+ PORT_PE1,\r
+ PORT_PE2,\r
+ PORT_PE3,\r
+ PORT_PE4,\r
+ PORT_PE5,\r
+ PORT_PE6,\r
+ PORT_PE7,\r
+ PORT_PE8,\r
+ PORT_PE9,\r
+ PORT_PE10,\r
+ PORT_PE11,\r
+ PORT_PE12,\r
+ PORT_PE13,\r
+ PORT_PE14,\r
+ PORT_PE15,\r
+ PORT_PF0,\r
+ PORT_PF1,\r
+ PORT_PF2,\r
+ PORT_PF3,\r
+ PORT_PF4,\r
+ PORT_PF5,\r
+ PORT_PF6,\r
+ PORT_PF7,\r
+ PORT_PF8,\r
+ PORT_PF9,\r
+ PORT_PF10,\r
+ PORT_PF11,\r
+ PORT_PF12,\r
+ PORT_PF13,\r
+ PORT_PF14,\r
+ PORT_PF15,\r
+ PORT_PG0,\r
+ PORT_PG1,\r
+ PORT_PG2,\r
+ PORT_PG3,\r
+ PORT_PG4,\r
+ PORT_PG5,\r
+ PORT_PG6,\r
+ PORT_PG7,\r
+ PORT_PG8,\r
+ PORT_PG9,\r
+ PORT_PG10,\r
+ PORT_PG11,\r
+ PORT_PG12,\r
+ PORT_PG13,\r
+ PORT_PG14,\r
+ PORT_PG15,\r
+ PORT_PH0,\r
+ PORT_PH1,\r
+ PORT_PH2,\r
+ PORT_PH3,\r
+ PORT_PH4,\r
+ PORT_PH5,\r
+ PORT_PH6,\r
+ PORT_PH7,\r
+ PORT_PH8,\r
+ PORT_PH9,\r
+ PORT_PH10,\r
+ PORT_PH11,\r
+ PORT_PH12,\r
+ PORT_PH13,\r
+ PORT_PH14,\r
+ PORT_PH15,\r
+ PORT_PJ0,\r
+ PORT_PJ1,\r
+ PORT_PJ2,\r
+ PORT_PJ3,\r
+ PORT_PJ4,\r
+ PORT_PJ5,\r
+ PORT_PJ6,\r
+ PORT_PJ7,\r
+ PORT_PJ8,\r
+ PORT_PJ9,\r
+ PORT_PJ10,\r
+ PORT_PJ11,\r
+ PORT_PJ12,\r
+ PORT_PJ13,\r
+ PORT_PJ14,\r
+ PORT_PJ15,\r
+ PORT_PK0,\r
+ PORT_PK1\r
} Port_PinType;\r
\r
/** @name HW specific register bits. */\r
//@{\r
-#define BIT0 (1<<15)\r
-#define BIT1 (1<<14)\r
-#define BIT2 (1<<13)\r
-#define BIT3 (1<<12)\r
-#define BIT4 (1<<11)\r
-#define BIT5 (1<<10)\r
-#define BIT6 (1<<9)\r
-#define BIT7 (1<<8)\r
-#define BIT8 (1<<7)\r
-#define BIT9 (1<<6)\r
-#define BIT10 (1<<5)\r
-#define BIT11 (1<<4)\r
-#define BIT12 (1<<3)\r
-#define BIT13 (1<<2)\r
-#define BIT14 (1<<1)\r
-#define BIT15 (1<<0)\r
-\r
-#define WPE_BIT BIT14\r
-#define WPS_BIT BIT15\r
-#define SRC0 BIT12\r
-#define SRC1 BIT13\r
-\r
-#define PULL_UP (WPE_BIT|WPS_BIT)\r
-#define PULL_DOWN (WPE_BIT)\r
-#define PULL_NONE 0\r
-#define SLEW_RATE_MIN 0\r
-#define SLEW_RATE_MED BIT13\r
-#define SLEW_RATE_MAX (BIT12|BIT13)\r
-#define HYS_ENABLE BIT11\r
-#define ODE_ENABLE BIT10\r
-#define IBE_ENABLE BIT7\r
-#define OBE_ENABLE BIT6\r
-#define PA_IO 0\r
-#define PA_FUNC1 (BIT5)\r
-#define PA_FUNC2 (BIT4)\r
-#define PA_FUNC3 (BIT4|BIT5)\r
-\r
-#define NORMAL_INPUT (BIT15)\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_PA_IO 0\r
+#define PORT_PA_FUNC1 (PORT_BIT5)\r
+#define PORT_PA_FUNC2 (PORT_BIT4)\r
+#define PORT_PA_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+\r
+#define PORT_NORMAL_INPUT (PORT_BIT15)\r
\r
// Should be this out of reset\r
-#define PCR_RESET (0)\r
-#define PCR_BOOTCFG (IBE_ENABLE|PULL_DOWN)\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_PCR_BOOTCFG (PORT_IBE_ENABLE|PORT_PULL_DOWN)\r
//@}\r
\r
-#define EVB_TEST_CONFIG (&PortConfigData)\r
+#define PORT_EVB_TEST_CONFIG (&PortConfigData)\r
\r
/** Top level configuration container */\r
typedef struct\r
* Author: nian\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Pwm.h"\r
#include "Pwm_Cfg.h"\r
\r
* Definitions of configuration parameters for PWM Driver.\r
*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef PWM_CFG_H_\r
#define PWM_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef SPI_CFG_H_\r
#define SPI_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Spi.h"\r
#include "Spi_Cfg.h"\r
#include <stdlib.h>\r
--- /dev/null
+/* Flash sizes\r
+ * 5516, 1.0M\r
+ * 5517, 1.5M\r
+ */\r
+flash(R) : ORIGIN = 0x00000000, LENGTH = 1M\r
+/* Ram sizes\r
+ * 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x00c000\r
--- /dev/null
+\r
+The Freescale MPC5510 is an PowerPC process with a e200Z1+e200Z0 core. \r
+The simulator environment ONLY supports one core.\r
+ \r
+Datasheets:\r
+ \r
+ MPC5516/7\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5510&webpageId=1067371573986721160325&nodeId=0162468rH3bTdG06C10325&fromPage=tax\r
+ \r
+Info: \r
+ MPC5516\r
+ 1.5MB Flash (MPC5516 1MB)\r
+ 80KB SRAM (MPC5516 64KB)\r
+ .. \r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL=KERNEL MCU GPT LIN CAN WDG WDGM DEM DCM IOHWAB\r
\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef CANIF_CFG_H_\r
#define CANIF_CFG_H_\r
\r
#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
\r
-//-------------------------------------------------------------------\r
-\r
-typedef struct {\r
- void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
- void (*RxIndication)(void *); //(const Can_PduType *);\r
- void (*ControllerBusOff)(uint8);\r
- void (*ControllerWakeup)(uint8);\r
- void (*Arc_Error)(uint8,uint32);\r
-} CanIf_CallbackType;\r
-\r
-\r
\r
//-------------------------------------------------------------------\r
/*\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef CAN_CFG_H_\r
#define CAN_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include <stdlib.h>\r
#include "Can.h"\r
#include "CanIf_Cbk.h"\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef COM_CFG_H_\r
#define COM_CFG_H_\r
\r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
/*\r
* ComGeneral pre-compile time configuration parameters.\r
* Specification: Autosar v2.0.1, Final\r
*\r
*/\r
-#ifndef _DET_CFG_H_\r
-#define _DET_CFG_H_\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H\r
\r
#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
\r
-#endif /*_DET_CFG_H_*/\r
+#endif /*DET_CFG_H*/\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-/* Link time config */\r
-\r
-#include "Std_Types.h"\r
-#include "Os.h"\r
-#include "Mcu.h"\r
-#include "Gpt.h"\r
-#include <assert.h>\r
-#include "Cpu.h"\r
-\r
-//#include "ComM.h"\r
-//#include "WdgM.h"\r
-\r
-//#include "Dem.h"\r
-//#include "Det.h"\r
-//#include "NvM.h"\r
-//#include "rte.h"\r
-\r
-extern void os_exception_IVPR();\r
-extern void os_exception_IVOR10();\r
-// The OS startup hook\r
-\r
-#if 0\r
-void StartupHook( void ) {\r
-\r
- // There a several things we need to connect here\r
- // * counter id for the system counter is 0\r
- // * that need to be attached to Gpt\r
- // --> We need to tell the OS that what Gpt channel it's\r
- // counter is connected to.\r
-\r
- // TODO: We need counter information here..\r
- // How do I get that information from the OS???\r
-\r
- //? GetCounterAlarmBase()\r
-\r
-// Gpt_StartTimer(GPT_CHANNEL_DEC, 100 );\r
-// Gpt_EnableNotification(GPT_CHANNEL_DEC);\r
-// Gpt_SetMode(0);\r
-}\r
-#endif\r
-\r
-extern void os_system_timer( void );\r
-\r
-void EcuM_Init( void );\r
-int main( void ) {\r
-\r
- EcuM_Init();\r
- return 0;\r
-}\r
-\r
-void EcuM_Init( void ) {\r
- /* Call all mandatory interfaces, see 8.7.1 */\r
-\r
- /* I'm giving up on the MCU configuration. From what I\r
- * can tell from the documentation the Mcu_Init()\r
- */\r
-\r
-#if 0\r
- ComM_ConfigType comMConfig;\r
- WdgM_ConfigType wdgmConfig;\r
-#endif\r
-\r
-// Startup I\r
- {\r
- const Mcu_ConfigType mcuConfig;\r
- Mcu_Init(&mcuConfig);\r
- }\r
-// Mcu_GetResetReason();\r
-#if 0\r
- Det_Init();\r
-#if defined(USE_DEM)\r
- Dem_PreInit();\r
-#endif\r
- EcuM_AL_DriverInitOne();\r
-#endif\r
-\r
-\r
- {\r
- // If we assume the OS will require SYSTEM_COUNTER to function.\r
- // We should either get the values from SYSTEM_COUNTER\r
-\r
- Gpt_ConfigType GptConfigData[] =\r
- { {\r
- .GptChannelId = GPT_CHANNEL_DEC,\r
- .GptChannelMode = GPT_MODE_CONTINUOUS,\r
- .GptChannelClkSrc = 0,\r
- .GptNotification = os_system_timer,\r
- }\r
- };\r
- Gpt_Init(&GptConfigData[0]);\r
-\r
- // The timer is actually started in StartupHook()\r
- }\r
-\r
-\r
-// EcuM_SelectShutdownTarget(target,mode);\r
- StartOS(OSDEFAULTAPPMODE);\r
-// Startup II\r
- //EcuM_AL_DriverInitTwo();\r
-\r
-#if 0\r
- ComM_Init(&comMConfig);\r
- WdgM_Init(&wdgmConfig);\r
- NvM_Init();\r
- NvM_ReadAll();\r
- NvM_WriteAll();\r
- NvM_CancelWriteAll();\r
-\r
-#if defined(USE_DEM)\r
- Dem_PreInit();\r
- Dem_Init();\r
- {\r
- Dem_EventIdType id = 0;\r
- Dem_EventStatusType status = 0;\r
- Dem_ReportErrorStatus(id,status);\r
- }\r
-#endif\r
- Rte_Start();\r
- Rte_Stop();\r
-#endif\r
-\r
- ShutdownOS(E_OK);\r
- EnableAllInterrupts();\r
- DisableAllInterrupts();\r
-\r
-// Det_ReportError(1,2,3,4);\r
-}\r
-\r
-void EcuM_Shutdown( void ) {\r
-\r
-}\r
-\r
-void EcuM_GetVersionInfo( Std_VersionInfoType *versioninfo ) {\r
-\r
-}\r
-\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Gpt.h"\r
#include "Gpt_Cfg.h"\r
#include <stdlib.h>\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef GPT_CFG_H_\r
#define GPT_CFG_H_\r
#include "Std_Types.h"\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_H_\r
#define MCU_CFG_H_\r
\r
--- /dev/null
+flash(R) : ORIGIN = 0x00000000, LENGTH = 1M\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+The Freescale MPC5554 is an PowerPC process with a e200Z6 core. \r
+The difference between this and the MPC551xsim is that this supports VLE.\r
+ \r
+Datasheets:\r
+ \r
+Info: \r
+ MPC5554\r
+ 2MB Flash\r
+ 64KB SRAM\r
+ .. \r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL+=KERNEL MCU GPT LIN CAN COM WDG WDGM DEM DCM IOHWAB\r
\r
-# Needed by kernel\r
-MOD_USE+=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
* Specification: Autosar v2.0.1, Final\r
*\r
*/\r
-#ifndef _DET_CFG_H_\r
-#define _DET_CFG_H_\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H\r
\r
#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
\r
-#endif /*_DET_CFG_H_*/\r
+#endif /*DET_CFG_H*/\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_H_\r
#define MCU_CFG_H_\r
\r
--- /dev/null
+\r
+\r
+/* MPC55xx Reset Control Word(RCW) */\r
+rcw : ORIGIN = 0x00000000, LENGTH = 0x8\r
+flash(R) : ORIGIN = 0x00000008, LENGTH = 2M\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+\r
+The Freescale MPC5567 is an PowerPC process with a e200z6 core. \r
+The EVAL board used is the "ODEEP" concept. \r
+ \r
+Datasheets:\r
+ ODEEP \r
+ http://www.odeep.se/ \r
+ \r
+ MPC5567\r
+ http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5567\r
+ \r
+Info: \r
+ MPC5567\r
+ 80-132Mhz\r
+ 2MB Flash \r
+ 80kB SRAM\r
+ 2 × SCI\r
+ 3 × DSPI\r
+ 5 × CAN\r
+ FlexRay\r
+ Ethernet\r
+ 24-ch PWM\r
+ 32-ch ETPU\r
+ 24-ch EMIOS\r
+ 2-ch × 20-ch, 12bit ADC\r
+ \r
+Memory Map:\r
+ 0x0000_0000 -> Flash\r
+ 0x4000_0000 -> SRAM\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL=KERNEL MCU WDG WDGM PORT DIO WDG WDGM PWM CAN CANIF COM ADC DMA DEM DCM CANTP PDUR IOHWAB\r
\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG NVM MEMIF FEE FLS \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Adc.h"\r
#include "Dma.h"\r
#include "mpc5516.h"\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef ADC_CFG_H_\r
#define ADC_CFG_H_\r
\r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "CanIf.h"\r
#include <stdlib.h>\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef CANIF_CFG_H_\r
#define CANIF_CFG_H_\r
\r
#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
\r
-//-------------------------------------------------------------------\r
-\r
-typedef struct {\r
- void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
- void (*RxIndication)(void *); //(const Can_PduType *);\r
- void (*ControllerBusOff)(uint8);\r
- void (*ControllerWakeup)(uint8);\r
- void (*Arc_Error)(uint8,uint32);\r
-} CanIf_CallbackType;\r
-\r
-\r
-\r
//-------------------------------------------------------------------\r
/*\r
* CanIfHrhRangeConfig container\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef CAN_CFG_H_\r
#define CAN_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include <stdlib.h>\r
#include "Can.h"\r
#include "CanIf_Cbk.h"\r
\r
\r
\r
-/*\r
- * ComGlobals.h\r
- *\r
- * Created on: 2009-jan-11\r
- * Author: Mattias\r
- */\r
+#warning "This default file may only be used as an example!"\r
\r
#ifndef COMGLOBALS_H_\r
#define COMGLOBALS_H_\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef COM_CFG_H_\r
#define COM_CFG_H_\r
\r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
/*\r
* ComGeneral pre-compile time configuration parameters.\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Com_PbCfg.h"\r
#include "Com_RunTest.h"\r
\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0xFF,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_EngineChangeSpeed,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_SIL2MESSAGE,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- //.ComSignalEndianess = BIG_ENDIAN,\r
+ //.ComSignalEndianess = COM_BIG_ENDIAN,\r
//.ComSignalInitValue = 0xFF,\r
//.ComSignalLength = 0,\r
//.ComSignalType = UINT16,\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef _COM_PBCFG_H\r
#define _COM_PBCFG_H\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
/*\r
* Development Error Tracer driver\r
*\r
* Specification: Autosar v2.0.1, Final\r
*\r
*/\r
-#ifndef _DET_CFG_H_\r
-#define _DET_CFG_H_\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H\r
\r
#define DET_ENABLE_CALLBACKS STD_ON // Enable to use callback on errors\r
#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
#define DET_RAMLOG_SIZE (32) // Number of entries in ramlog\r
#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
\r
-#endif /*_DET_CFG_H_*/\r
+#endif /*DET_CFG_H*/\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DIO_CFG_H_\r
#define DIO_CFG_H_\r
\r
\r
// Channels\r
extern const Dio_ChannelType DioChannelConfigData[];\r
-#define CHANNEL_PTR (&DioChannelConfigData)\r
-\r
// Port\r
extern const Dio_PortType DioPortConfigData[];\r
-#define PORT_PTR (&DioPortConfigData)\r
-\r
// Channel group\r
extern const Dio_ChannelGroupType DioConfigData[];\r
-#define CHANNEL_GRP_PTR (&DioConfigData)\r
\r
// Mapping of logical ports to physical\r
\r
// Channels\r
-#define LED_K2 (125)\r
+#define DIO_CHANNEL_NAME_LED_K2 (125)\r
+\r
+// Standard board test led\r
+#define DIO_CHANNEL_NAME_BOARD_LED DIO_CHANNEL_NAME_LED_K2\r
\r
// Port\r
// No ports available for MPC5567\r
\r
// Channel group\r
-#define LED_GRP_PTR (&DioConfigData[0])\r
+#define DIO_GROUP_NAME_LED_GRP_PTR (&DioConfigData[0])\r
\r
//\r
// Channels\r
//\r
-#define CONTROL_BUS_EN\r
-#define CONTROL_BUS_STB\r
-#define CONTROL_BUS_ERR\r
-#define CONTROL_BUS_S_PLUS_ST\r
-#define CONTROL_BUS_S_MINUS_ST\r
-#define CONTROL_BUS_S_PLUS_IN\r
+#define DIO_CONTROL_BUS_EN\r
+#define DIO_CONTROL_BUS_STB\r
+#define DIO_CONTROL_BUS_ERR\r
+#define DIO_CONTROL_BUS_S_PLUS_ST\r
+#define DIO_CONTROL_BUS_S_MINUS_ST\r
+#define DIO_CONTROL_BUS_S_PLUS_IN\r
\r
-#define MULTILINK_SO_IN\r
-#define MULTILINK_SO_ST\r
+#define DIO_MULTILINK_SO_IN\r
+#define DIO_MULTILINK_SO_ST\r
\r
-#define DATALINK_CANERR\r
-#define DATALINK_CANEN\r
-#define DATALINK_CANSTB\r
+#define DIO_DATALINK_CANERR\r
+#define DIO_DATALINK_CANEN\r
+#define DIO_DATALINK_CANSTB\r
\r
-#define RF_PWM\r
-#define RF_C1\r
-#define RF_C2\r
+#define DIO_RF_PWM\r
+#define DIO_RF_C1\r
+#define DIO_RF_C2\r
\r
-#define IO_SOUND_EN\r
-#define IO_SOUND\r
+#define DIO_IO_SOUND_EN\r
+#define DIO_IO_SOUND\r
\r
//\r
// Channel groups\r
//\r
-#define CONTROL_BUS (DioConfigData)\r
-#define MULTILINK_BUS (DioConfigData)\r
-#define RF (DioConfigData)\r
-#define IO (DioConfigData)\r
+#define DIO_CONTROL_BUS (DioConfigData)\r
+#define DIO_MULTILINK_BUS (DioConfigData)\r
+#define DIO_RF (DioConfigData)\r
+#define DIO_IO (DioConfigData)\r
\r
//\r
// Port mapping\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Dio.h"\r
#include "Dio_Cfg.h"\r
\r
const Dio_ChannelType DioChannelConfigData[] =\r
-{ LED_K2, DIO_END_OF_LIST, };\r
+{ DIO_CHANNEL_NAME_LED_K2, DIO_END_OF_LIST, };\r
\r
// No ports available for 5567\r
const Dio_PortType DioPortConfigData[] =\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Dma.h"\r
\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef DMA_CFG_H_\r
#define DMA_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef EEP_CFG_H_\r
#define EEP_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Eep.h"\r
#include "Spi.h"\r
#include "Spi_Cfg.h"\r
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#undef DEBUG_LVL\r
#define DEBUG_LVL DEBUG_LOW\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Eep.h"\r
#include "Spi.h"\r
#include "Spi_Cfg.h"\r
\r
-//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
#undef DEBUG_LVL\r
#define DEBUG_LVL DEBUG_LOW\r
\r
\r
#include "Fls.h"\r
+#include "Fls_Cfg.h"\r
#include <stdlib.h>\r
\r
\r
\r
\r
const Fls_SectorType fls_evbSectorList[] = {\r
- { // L0->L7\r
- .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
- .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
- .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
- // Number of continuous sectors with the above characteristics.\r
- .FlsNumberOfSectors = (uint32)8,// L0->L7 , 8 sectors\r
- },\r
- { // L8,L9\r
- .FlsSectorStartaddress = (Fls_AddressType)0x00020000,\r
- .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
- .FlsSectorSize = (Fls_LengthType)(64 KB), // 64Kbyte\r
- .FlsNumberOfSectors = (uint32)2,// L8,L9 , 2 sectors\r
- },\r
- { // M0->H7\r
- .FlsSectorStartaddress = (Fls_AddressType)0x00040000,\r
- .FlsPageSize = (Fls_LengthType)8, // Read page size of 128 bits (4 words), (8 bytes)\r
+ { // L0\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00000000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)1,// L0 , 1 sectors\r
+ },\r
+ { // L1-L2\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00004000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(48 KB), // 48Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)2,// L1->L2 , 2 sectors\r
+ },\r
+ { // L3\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x0001C000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(16 KB), // 16Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)8,// L0->L7 , 8 sectors\r
+ },\r
+ { // L4-L5\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00020000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
+ .FlsSectorSize = (Fls_LengthType)(128 KB), // 128Kbyte\r
+ // Number of continuous sectors with the above characteristics.\r
+ .FlsNumberOfSectors = (uint32)2,// L4->L5 , 8 sectors\r
+ },\r
+ { // H0->H11\r
+ .FlsSectorStartaddress = (Fls_AddressType)0x00060000, // Start address of this sector\r
+ .FlsPageSize = (Fls_LengthType)4, // Page size 8 words = 32bytes\r
.FlsSectorSize = (Fls_LengthType)(128 KB), // 128Kbyte\r
- .FlsNumberOfSectors = (uint32)6,// M0->H7\r
+ .FlsNumberOfSectors = (uint32)12,// H0->H11\r
}\r
};\r
\r
/*\r
* Block to partition map\r
*/\r
-uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,2,2,3,3,4,4,5,5,6,6,7,7,8,8 };\r
+uint8 Fls_BlockToPartitionMap[] = { 1,1,1,1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9 };\r
\r
const Fls_ConfigType FlsConfigSet[]=\r
{\r
\r
\r
\r
-\r
#ifndef FLS_CFG_H_\r
#define FLS_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Fls.h"\r
#include <stdlib.h>\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef FLS_SST25XX_CFG_H_\r
#define FLS_SST25XX_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Gpt.h"\r
#include "Gpt_Cfg.h"\r
#include <stdlib.h>\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef GPT_CFG_H_\r
#define GPT_CFG_H_\r
#include "Std_Types.h"\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef LINIF_CFG_H_\r
#define LINIF_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "LinIf_Cfg.h"\r
#include "Lin_Cfg.h"\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef LINSM_CFG_H_\r
#define LINSM_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "LinSM_Cfg.h"\r
#include "LinIf_Cfg.h"\r
#include "Lin_Cfg.h"\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef LIN_CFG_H_\r
#define LIN_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Mcu.h"\r
#include "Lin.h"\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Lin_Cfg.h"\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_H_\r
#define MCU_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#define PDUR_MODULE_ID 51\r
#define PDUR_INSTANCE_ID 0\r
\r
#endif\r
\r
// Interfaces\r
-#define PDUR_CANIF_SUPPORT\r
-//#define PDUR_CANTP_SUPPORT\r
-//#define PDUR_FRIF_SUPPORT\r
-//#define PDUR_FRTP_SUPPORT\r
-#define PDUR_LINIF_SUPPORT\r
-//#define PDUR_LINTP_SUPPORT\r
-#define PDUR_COM_SUPPORT\r
-#define PDUR_DCM_SUPPORT\r
+#define PDUR_CANIF_SUPPORT STD_ON\r
+#define PDUR_CANTP_SUPPORT STD_OFF\r
+#define PDUR_FRIF_SUPPORT STD_OFF\r
+#define PDUR_FRTP_SUPPORT STD_OFF\r
+#define PDUR_LINIF_SUPPORT STD_OFF\r
+#define PDUR_LINTP_SUPPORT STD_OFF\r
+#define PDUR_COM_SUPPORT STD_ON\r
+#define PDUR_DCM_SUPPORT STD_OFF\r
\r
\r
//#define PDUR_MAX_TX_BUFFER_NUMBER\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#define PDUR_ZERO_COST_OPERATION STD_ON\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
/*\r
* Port_Cfg.c\r
*\r
\r
\r
const uint16_t PortPadConfigData[] = {\r
- PCR_RESET, // SIU_PCR0\r
- PCR_RESET, // SIU_PCR1\r
- PCR_RESET, // SIU_PCR2\r
- PCR_RESET, // SIU_PCR3\r
- PCR_RESET, // SIU_PCR4\r
- PCR_RESET, // SIU_PCR5\r
- PCR_RESET, // SIU_PCR6\r
- PCR_RESET, // SIU_PCR7\r
- PCR_RESET, // SIU_PCR8\r
- PCR_RESET, // SIU_PCR9\r
- PCR_RESET, // SIU_PCR10\r
- PCR_RESET, // SIU_PCR11\r
- PCR_RESET, // SIU_PCR12\r
- PCR_RESET, // SIU_PCR13\r
- PCR_RESET, // SIU_PCR14\r
- PCR_RESET, // SIU_PCR15\r
- PCR_RESET, // SIU_PCR16\r
- PCR_RESET, // SIU_PCR17\r
- PCR_RESET, // SIU_PCR18\r
- PCR_RESET, // SIU_PCR19\r
- PCR_RESET, // SIU_PCR20\r
- PCR_RESET, // SIU_PCR21\r
- PCR_RESET, // SIU_PCR22\r
- PCR_RESET, // SIU_PCR23\r
- PCR_RESET, // SIU_PCR24\r
- PCR_RESET, // SIU_PCR25\r
- PCR_RESET, // SIU_PCR26\r
- PCR_RESET, // SIU_PCR27\r
- PCR_RESET, // SIU_PCR28\r
- PCR_RESET, // SIU_PCR29\r
- PCR_RESET, // SIU_PCR30\r
- PCR_RESET, // SIU_PCR31\r
- PCR_RESET, // SIU_PCR32\r
- PCR_RESET, // SIU_PCR33\r
- PCR_RESET, // SIU_PCR34\r
- PCR_RESET, // SIU_PCR35\r
- PCR_RESET, // SIU_PCR36\r
- PCR_RESET, // SIU_PCR37\r
- PCR_RESET, // SIU_PCR38\r
- PCR_RESET, // SIU_PCR39\r
- PCR_RESET, // SIU_PCR40\r
- PCR_RESET, // SIU_PCR41\r
- PCR_RESET, // SIU_PCR42\r
- PCR_RESET, // SIU_PCR43\r
- PCR_RESET, // SIU_PCR44\r
- PCR_RESET, // SIU_PCR45\r
- PCR_RESET, // SIU_PCR46\r
- PCR_RESET, // SIU_PCR47\r
- PCR_RESET, // SIU_PCR48\r
- PCR_RESET, // SIU_PCR49\r
- PCR_RESET, // SIU_PCR50\r
- PCR_RESET, // SIU_PCR51\r
- PCR_RESET, // SIU_PCR52\r
- PCR_RESET, // SIU_PCR53\r
- PCR_RESET, // SIU_PCR54\r
- PCR_RESET, // SIU_PCR55\r
- PCR_RESET, // SIU_PCR56\r
- PCR_RESET, // SIU_PCR57\r
- PCR_RESET, // SIU_PCR58\r
- PCR_RESET, // SIU_PCR59\r
- PCR_RESET, // SIU_PCR60\r
- PCR_RESET, // SIU_PCR61\r
- PCR_RESET, // SIU_PCR62\r
- PCR_RESET, // SIU_PCR63\r
- PCR_RESET, // SIU_PCR64\r
- PCR_RESET, // SIU_PCR65\r
- PCR_RESET, // SIU_PCR66\r
- PCR_RESET, // SIU_PCR67\r
- PCR_RESET, // SIU_PCR68\r
- PCR_RESET, // SIU_PCR69\r
- PCR_RESET, // SIU_PCR70\r
- PCR_RESET, // SIU_PCR71\r
- PCR_RESET, // SIU_PCR72\r
- PCR_RESET, // SIU_PCR73\r
- PCR_RESET, // SIU_PCR74\r
- PCR_RESET, // SIU_PCR75\r
- PCR_RESET, // SIU_PCR76\r
- PCR_RESET, // SIU_PCR77\r
- PCR_RESET, // SIU_PCR78\r
- PCR_RESET, // SIU_PCR79\r
- PCR_RESET, // SIU_PCR80\r
- PCR_RESET, // SIU_PCR81\r
- PCR_RESET, // SIU_PCR82\r
- PCR_RESET, // SIU_PCR83\r
- PCR_RESET, // SIU_PCR84\r
- PCR_RESET, // SIU_PCR85\r
- PCR_RESET, // SIU_PCR86\r
- PCR_RESET, // SIU_PCR87\r
- PCR_RESET, // SIU_PCR88\r
- PCR_RESET, // SIU_PCR89\r
- PCR_RESET, // SIU_PCR90\r
- PCR_RESET, // SIU_PCR91\r
- PCR_RESET, // SIU_PCR92\r
- PCR_RESET, // SIU_PCR93\r
- PCR_RESET, // SIU_PCR94\r
- PCR_RESET, // SIU_PCR95\r
- PCR_RESET, // SIU_PCR96\r
- PCR_RESET, // SIU_PCR97\r
- PCR_RESET, // SIU_PCR98\r
- PCR_RESET, // SIU_PCR99\r
- PCR_RESET, // SIU_PCR100\r
- PCR_RESET, // SIU_PCR101\r
- PCR_RESET, // SIU_PCR102\r
- PCR_RESET, // SIU_PCR103\r
- PCR_RESET, // SIU_PCR104\r
- PCR_RESET, // SIU_PCR105\r
- PCR_RESET, // SIU_PCR106\r
- PCR_RESET, // SIU_PCR107\r
- PCR_RESET, // SIU_PCR108\r
- PCR_RESET, // SIU_PCR109\r
- PCR_RESET, // SIU_PCR110\r
- PCR_RESET, // SIU_PCR111\r
- PCR_RESET, // SIU_PCR112\r
- PCR_RESET, // SIU_PCR113\r
- PCR_RESET, // SIU_PCR114\r
- PCR_RESET, // SIU_PCR115\r
- PCR_RESET, // SIU_PCR116\r
- PCR_RESET, // SIU_PCR117\r
- PCR_RESET, // SIU_PCR118\r
- PCR_RESET, // SIU_PCR119\r
- PCR_RESET, // SIU_PCR120\r
- PCR_RESET, // SIU_PCR121\r
- PCR_RESET, // SIU_PCR122\r
- PCR_RESET, // SIU_PCR123\r
- PCR_RESET, // SIU_PCR124\r
- PCR_IO_OUTPUT, // SIU_PCR125 detta borde vara dioden som sitter på K2\r
- PCR_RESET, // SIU_PCR126\r
- PCR_RESET, // SIU_PCR127\r
- PCR_RESET, // SIU_PCR128\r
- PCR_RESET, // SIU_PCR129\r
- PCR_RESET, // SIU_PCR130\r
- PCR_RESET, // SIU_PCR131\r
- PCR_RESET, // SIU_PCR132\r
- PCR_RESET, // SIU_PCR133\r
- PCR_RESET, // SIU_PCR134\r
- PCR_RESET, // SIU_PCR135\r
- PCR_RESET, // SIU_PCR136\r
- PCR_RESET, // SIU_PCR137\r
- PCR_RESET, // SIU_PCR138\r
- PCR_RESET, // SIU_PCR139\r
- PCR_RESET, // SIU_PCR140\r
- PCR_RESET, // SIU_PCR141\r
- PCR_RESET, // SIU_PCR142\r
- PCR_RESET, // SIU_PCR143\r
- PCR_RESET, // SIU_PCR144\r
- PCR_RESET, // SIU_PCR145\r
- PCR_RESET, // SIU_PCR146\r
- PCR_RESET, // SIU_PCR147\r
- PCR_RESET, // SIU_PCR148\r
- PCR_RESET, // SIU_PCR149\r
- PCR_RESET, // SIU_PCR150\r
- PCR_RESET, // SIU_PCR151\r
- PCR_RESET, // SIU_PCR152\r
- PCR_RESET, // SIU_PCR153\r
- PCR_RESET, // SIU_PCR154\r
- PCR_RESET, // SIU_PCR155\r
- PCR_RESET, // SIU_PCR156\r
- PCR_RESET, // SIU_PCR157\r
- PCR_RESET, // SIU_PCR158\r
- PCR_RESET, // SIU_PCR159\r
- PCR_RESET, // SIU_PCR160\r
- PCR_RESET, // SIU_PCR161\r
- PCR_RESET, // SIU_PCR162\r
- PCR_RESET, // SIU_PCR163\r
- PCR_RESET, // SIU_PCR164\r
- PCR_RESET, // SIU_PCR165\r
- PCR_RESET, // SIU_PCR166\r
- PCR_RESET, // SIU_PCR167\r
- PCR_RESET, // SIU_PCR168\r
- PCR_RESET, // SIU_PCR169\r
- PCR_RESET, // SIU_PCR170\r
- PCR_RESET, // SIU_PCR171\r
- PCR_RESET, // SIU_PCR172\r
- PCR_RESET, // SIU_PCR173\r
- PCR_RESET, // SIU_PCR174\r
- PCR_RESET, // SIU_PCR175\r
- PCR_RESET, // SIU_PCR176\r
- PCR_RESET, // SIU_PCR177\r
- PCR_RESET, // SIU_PCR178\r
- PCR_RESET, // SIU_PCR179\r
- PCR_RESET, // SIU_PCR180\r
- PCR_RESET, // SIU_PCR181\r
- PCR_RESET, // SIU_PCR182\r
- PCR_RESET, // SIU_PCR183\r
- PCR_RESET, // SIU_PCR184\r
- PCR_RESET, // SIU_PCR185\r
- PCR_RESET, // SIU_PCR186\r
- PCR_RESET, // SIU_PCR187\r
- PCR_RESET, // SIU_PCR188\r
- PA_PRIMARY_FUNC|OBE_ENABLE, // SIU_PCR189; This one should be EMIOS channel 10\r
- PCR_RESET, // SIU_PCR190\r
- PA_PRIMARY_FUNC|OBE_ENABLE, // SIU_PCR191; EMIOS channel 12\r
- PCR_RESET, // SIU_PCR192\r
- PCR_RESET, // SIU_PCR193\r
- PCR_RESET, // SIU_PCR194\r
- PCR_RESET, // SIU_PCR195\r
- PCR_RESET, // SIU_PCR196\r
- PCR_RESET, // SIU_PCR197\r
- PCR_RESET, // SIU_PCR198\r
- PCR_RESET, // SIU_PCR199\r
- PCR_RESET, // SIU_PCR200\r
- PCR_RESET, // SIU_PCR201\r
- PCR_RESET, // SIU_PCR202\r
- PCR_RESET, // SIU_PCR203\r
- PCR_RESET, // SIU_PCR204\r
- PCR_RESET, // SIU_PCR205\r
- PCR_RESET, // SIU_PCR206\r
- PCR_RESET, // SIU_PCR207\r
- PCR_RESET, // SIU_PCR208\r
- PCR_RESET, // SIU_PCR209\r
- PCR_RESET, // SIU_PCR210\r
- PCR_RESET, // SIU_PCR211\r
- PCR_RESET, // SIU_PCR212\r
- PCR_RESET, // SIU_PCR213\r
- PCR_RESET, // SIU_PCR214\r
- PCR_RESET, // SIU_PCR215\r
- PCR_RESET, // SIU_PCR216\r
- PCR_RESET, // SIU_PCR217\r
- PCR_RESET, // SIU_PCR218\r
- PCR_RESET, // SIU_PCR219\r
- PCR_RESET, // SIU_PCR220\r
- PCR_RESET, // SIU_PCR221\r
- PCR_RESET, // SIU_PCR222\r
- PCR_RESET, // SIU_PCR223\r
- PCR_RESET, // SIU_PCR224\r
- PCR_RESET, // SIU_PCR225\r
- PCR_RESET, // SIU_PCR226\r
- PCR_RESET, // SIU_PCR227\r
- PCR_RESET, // SIU_PCR228\r
- PCR_RESET, // SIU_PCR229\r
- PCR_RESET, // SIU_PCR230\r
+ PORT_PCR_RESET, // SIU_PCR0\r
+ PORT_PCR_RESET, // SIU_PCR1\r
+ PORT_PCR_RESET, // SIU_PCR2\r
+ PORT_PCR_RESET, // SIU_PCR3\r
+ PORT_PCR_RESET, // SIU_PCR4\r
+ PORT_PCR_RESET, // SIU_PCR5\r
+ PORT_PCR_RESET, // SIU_PCR6\r
+ PORT_PCR_RESET, // SIU_PCR7\r
+ PORT_PCR_RESET, // SIU_PCR8\r
+ PORT_PCR_RESET, // SIU_PCR9\r
+ PORT_PCR_RESET, // SIU_PCR10\r
+ PORT_PCR_RESET, // SIU_PCR11\r
+ PORT_PCR_RESET, // SIU_PCR12\r
+ PORT_PCR_RESET, // SIU_PCR13\r
+ PORT_PCR_RESET, // SIU_PCR14\r
+ PORT_PCR_RESET, // SIU_PCR15\r
+ PORT_PCR_RESET, // SIU_PCR16\r
+ PORT_PCR_RESET, // SIU_PCR17\r
+ PORT_PCR_RESET, // SIU_PCR18\r
+ PORT_PCR_RESET, // SIU_PCR19\r
+ PORT_PCR_RESET, // SIU_PCR20\r
+ PORT_PCR_RESET, // SIU_PCR21\r
+ PORT_PCR_RESET, // SIU_PCR22\r
+ PORT_PCR_RESET, // SIU_PCR23\r
+ PORT_PCR_RESET, // SIU_PCR24\r
+ PORT_PCR_RESET, // SIU_PCR25\r
+ PORT_PCR_RESET, // SIU_PCR26\r
+ PORT_PCR_RESET, // SIU_PCR27\r
+ PORT_PCR_RESET, // SIU_PCR28\r
+ PORT_PCR_RESET, // SIU_PCR29\r
+ PORT_PCR_RESET, // SIU_PCR30\r
+ PORT_PCR_RESET, // SIU_PCR31\r
+ PORT_PCR_RESET, // SIU_PCR32\r
+ PORT_PCR_RESET, // SIU_PCR33\r
+ PORT_PCR_RESET, // SIU_PCR34\r
+ PORT_PCR_RESET, // SIU_PCR35\r
+ PORT_PCR_RESET, // SIU_PCR36\r
+ PORT_PCR_RESET, // SIU_PCR37\r
+ PORT_PCR_RESET, // SIU_PCR38\r
+ PORT_PCR_RESET, // SIU_PCR39\r
+ PORT_PCR_RESET, // SIU_PCR40\r
+ PORT_PCR_RESET, // SIU_PCR41\r
+ PORT_PCR_RESET, // SIU_PCR42\r
+ PORT_PCR_RESET, // SIU_PCR43\r
+ PORT_PCR_RESET, // SIU_PCR44\r
+ PORT_PCR_RESET, // SIU_PCR45\r
+ PORT_PCR_RESET, // SIU_PCR46\r
+ PORT_PCR_RESET, // SIU_PCR47\r
+ PORT_PCR_RESET, // SIU_PCR48\r
+ PORT_PCR_RESET, // SIU_PCR49\r
+ PORT_PCR_RESET, // SIU_PCR50\r
+ PORT_PCR_RESET, // SIU_PCR51\r
+ PORT_PCR_RESET, // SIU_PCR52\r
+ PORT_PCR_RESET, // SIU_PCR53\r
+ PORT_PCR_RESET, // SIU_PCR54\r
+ PORT_PCR_RESET, // SIU_PCR55\r
+ PORT_PCR_RESET, // SIU_PCR56\r
+ PORT_PCR_RESET, // SIU_PCR57\r
+ PORT_PCR_RESET, // SIU_PCR58\r
+ PORT_PCR_RESET, // SIU_PCR59\r
+ PORT_PCR_RESET, // SIU_PCR60\r
+ PORT_PCR_RESET, // SIU_PCR61\r
+ PORT_PCR_RESET, // SIU_PCR62\r
+ PORT_PCR_RESET, // SIU_PCR63\r
+ PORT_PCR_RESET, // SIU_PCR64\r
+ PORT_PCR_RESET, // SIU_PCR65\r
+ PORT_PCR_RESET, // SIU_PCR66\r
+ PORT_PCR_RESET, // SIU_PCR67\r
+ PORT_PCR_RESET, // SIU_PCR68\r
+ PORT_PCR_RESET, // SIU_PCR69\r
+ PORT_PCR_RESET, // SIU_PCR70\r
+ PORT_PCR_RESET, // SIU_PCR71\r
+ PORT_PCR_RESET, // SIU_PCR72\r
+ PORT_PCR_RESET, // SIU_PCR73\r
+ PORT_PCR_RESET, // SIU_PCR74\r
+ PORT_PCR_RESET, // SIU_PCR75\r
+ PORT_PCR_RESET, // SIU_PCR76\r
+ PORT_PCR_RESET, // SIU_PCR77\r
+ PORT_PCR_RESET, // SIU_PCR78\r
+ PORT_PCR_RESET, // SIU_PCR79\r
+ PORT_PCR_RESET, // SIU_PCR80\r
+ PORT_PCR_RESET, // SIU_PCR81\r
+ PORT_PCR_RESET, // SIU_PCR82\r
+ PORT_PCR_RESET, // SIU_PCR83\r
+ PORT_PCR_RESET, // SIU_PCR84\r
+ PORT_PCR_RESET, // SIU_PCR85\r
+ PORT_PCR_RESET, // SIU_PCR86\r
+ PORT_PCR_RESET, // SIU_PCR87\r
+ PORT_PCR_RESET, // SIU_PCR88\r
+ PORT_PCR_RESET, // SIU_PCR89\r
+ PORT_PCR_RESET, // SIU_PCR90\r
+ PORT_PCR_RESET, // SIU_PCR91\r
+ PORT_PCR_RESET, // SIU_PCR92\r
+ PORT_PCR_RESET, // SIU_PCR93\r
+ PORT_PCR_RESET, // SIU_PCR94\r
+ PORT_PCR_RESET, // SIU_PCR95\r
+ PORT_PCR_RESET, // SIU_PCR96\r
+ PORT_PCR_RESET, // SIU_PCR97\r
+ PORT_PCR_RESET, // SIU_PCR98\r
+ PORT_PCR_RESET, // SIU_PCR99\r
+ PORT_PCR_RESET, // SIU_PCR100\r
+ PORT_PCR_RESET, // SIU_PCR101\r
+ PORT_PCR_RESET, // SIU_PCR102\r
+ PORT_PCR_RESET, // SIU_PCR103\r
+ PORT_PCR_RESET, // SIU_PCR104\r
+ PORT_PCR_RESET, // SIU_PCR105\r
+ PORT_PCR_RESET, // SIU_PCR106\r
+ PORT_PCR_RESET, // SIU_PCR107\r
+ PORT_PCR_RESET, // SIU_PCR108\r
+ PORT_PCR_RESET, // SIU_PCR109\r
+ PORT_PCR_RESET, // SIU_PCR110\r
+ PORT_PCR_RESET, // SIU_PCR111\r
+ PORT_PCR_RESET, // SIU_PCR112\r
+ PORT_PCR_RESET, // SIU_PCR113\r
+ PORT_PCR_RESET, // SIU_PCR114\r
+ PORT_PCR_RESET, // SIU_PCR115\r
+ PORT_PCR_RESET, // SIU_PCR116\r
+ PORT_PCR_RESET, // SIU_PCR117\r
+ PORT_PCR_RESET, // SIU_PCR118\r
+ PORT_PCR_RESET, // SIU_PCR119\r
+ PORT_PCR_RESET, // SIU_PCR120\r
+ PORT_PCR_RESET, // SIU_PCR121\r
+ PORT_PCR_RESET, // SIU_PCR122\r
+ PORT_PCR_RESET, // SIU_PCR123\r
+ PORT_PCR_RESET, // SIU_PCR124\r
+ PORT_PCR_IO_OUTPUT, // SIU_PCR125 detta borde vara dioden som sitter på K2\r
+ PORT_PCR_RESET, // SIU_PCR126\r
+ PORT_PCR_RESET, // SIU_PCR127\r
+ PORT_PCR_RESET, // SIU_PCR128\r
+ PORT_PCR_RESET, // SIU_PCR129\r
+ PORT_PCR_RESET, // SIU_PCR130\r
+ PORT_PCR_RESET, // SIU_PCR131\r
+ PORT_PCR_RESET, // SIU_PCR132\r
+ PORT_PCR_RESET, // SIU_PCR133\r
+ PORT_PCR_RESET, // SIU_PCR134\r
+ PORT_PCR_RESET, // SIU_PCR135\r
+ PORT_PCR_RESET, // SIU_PCR136\r
+ PORT_PCR_RESET, // SIU_PCR137\r
+ PORT_PCR_RESET, // SIU_PCR138\r
+ PORT_PCR_RESET, // SIU_PCR139\r
+ PORT_PCR_RESET, // SIU_PCR140\r
+ PORT_PCR_RESET, // SIU_PCR141\r
+ PORT_PCR_RESET, // SIU_PCR142\r
+ PORT_PCR_RESET, // SIU_PCR143\r
+ PORT_PCR_RESET, // SIU_PCR144\r
+ PORT_PCR_RESET, // SIU_PCR145\r
+ PORT_PCR_RESET, // SIU_PCR146\r
+ PORT_PCR_RESET, // SIU_PCR147\r
+ PORT_PCR_RESET, // SIU_PCR148\r
+ PORT_PCR_RESET, // SIU_PCR149\r
+ PORT_PCR_RESET, // SIU_PCR150\r
+ PORT_PCR_RESET, // SIU_PCR151\r
+ PORT_PCR_RESET, // SIU_PCR152\r
+ PORT_PCR_RESET, // SIU_PCR153\r
+ PORT_PCR_RESET, // SIU_PCR154\r
+ PORT_PCR_RESET, // SIU_PCR155\r
+ PORT_PCR_RESET, // SIU_PCR156\r
+ PORT_PCR_RESET, // SIU_PCR157\r
+ PORT_PCR_RESET, // SIU_PCR158\r
+ PORT_PCR_RESET, // SIU_PCR159\r
+ PORT_PCR_RESET, // SIU_PCR160\r
+ PORT_PCR_RESET, // SIU_PCR161\r
+ PORT_PCR_RESET, // SIU_PCR162\r
+ PORT_PCR_RESET, // SIU_PCR163\r
+ PORT_PCR_RESET, // SIU_PCR164\r
+ PORT_PCR_RESET, // SIU_PCR165\r
+ PORT_PCR_RESET, // SIU_PCR166\r
+ PORT_PCR_RESET, // SIU_PCR167\r
+ PORT_PCR_RESET, // SIU_PCR168\r
+ PORT_PCR_RESET, // SIU_PCR169\r
+ PORT_PCR_RESET, // SIU_PCR170\r
+ PORT_PCR_RESET, // SIU_PCR171\r
+ PORT_PCR_RESET, // SIU_PCR172\r
+ PORT_PCR_RESET, // SIU_PCR173\r
+ PORT_PCR_RESET, // SIU_PCR174\r
+ PORT_PCR_RESET, // SIU_PCR175\r
+ PORT_PCR_RESET, // SIU_PCR176\r
+ PORT_PCR_RESET, // SIU_PCR177\r
+ PORT_PCR_RESET, // SIU_PCR178\r
+ PORT_PCR_RESET, // SIU_PCR179\r
+ PORT_PCR_RESET, // SIU_PCR180\r
+ PORT_PCR_RESET, // SIU_PCR181\r
+ PORT_PCR_RESET, // SIU_PCR182\r
+ PORT_PCR_RESET, // SIU_PCR183\r
+ PORT_PCR_RESET, // SIU_PCR184\r
+ PORT_PCR_RESET, // SIU_PCR185\r
+ PORT_PCR_RESET, // SIU_PCR186\r
+ PORT_PCR_RESET, // SIU_PCR187\r
+ PORT_PCR_RESET, // SIU_PCR188\r
+ PORT_PA_PRIMARY_FUNC|PORT_OBE_ENABLE, // SIU_PCR189; This one should be EMIOS channel 10\r
+ PORT_PCR_RESET, // SIU_PCR190\r
+ PORT_PA_PRIMARY_FUNC|PORT_OBE_ENABLE, // SIU_PCR191; EMIOS channel 12\r
+ PORT_PCR_RESET, // SIU_PCR192\r
+ PORT_PCR_RESET, // SIU_PCR193\r
+ PORT_PCR_RESET, // SIU_PCR194\r
+ PORT_PCR_RESET, // SIU_PCR195\r
+ PORT_PCR_RESET, // SIU_PCR196\r
+ PORT_PCR_RESET, // SIU_PCR197\r
+ PORT_PCR_RESET, // SIU_PCR198\r
+ PORT_PCR_RESET, // SIU_PCR199\r
+ PORT_PCR_RESET, // SIU_PCR200\r
+ PORT_PCR_RESET, // SIU_PCR201\r
+ PORT_PCR_RESET, // SIU_PCR202\r
+ PORT_PCR_RESET, // SIU_PCR203\r
+ PORT_PCR_RESET, // SIU_PCR204\r
+ PORT_PCR_RESET, // SIU_PCR205\r
+ PORT_PCR_RESET, // SIU_PCR206\r
+ PORT_PCR_RESET, // SIU_PCR207\r
+ PORT_PCR_RESET, // SIU_PCR208\r
+ PORT_PCR_RESET, // SIU_PCR209\r
+ PORT_PCR_RESET, // SIU_PCR210\r
+ PORT_PCR_RESET, // SIU_PCR211\r
+ PORT_PCR_RESET, // SIU_PCR212\r
+ PORT_PCR_RESET, // SIU_PCR213\r
+ PORT_PCR_RESET, // SIU_PCR214\r
+ PORT_PCR_RESET, // SIU_PCR215\r
+ PORT_PCR_RESET, // SIU_PCR216\r
+ PORT_PCR_RESET, // SIU_PCR217\r
+ PORT_PCR_RESET, // SIU_PCR218\r
+ PORT_PCR_RESET, // SIU_PCR219\r
+ PORT_PCR_RESET, // SIU_PCR220\r
+ PORT_PCR_RESET, // SIU_PCR221\r
+ PORT_PCR_RESET, // SIU_PCR222\r
+ PORT_PCR_RESET, // SIU_PCR223\r
+ PORT_PCR_RESET, // SIU_PCR224\r
+ PORT_PCR_RESET, // SIU_PCR225\r
+ PORT_PCR_RESET, // SIU_PCR226\r
+ PORT_PCR_RESET, // SIU_PCR227\r
+ PORT_PCR_RESET, // SIU_PCR228\r
+ PORT_PCR_RESET, // SIU_PCR229\r
+ PORT_PCR_RESET, // SIU_PCR230\r
};\r
\r
const uint8_t PortOutConfigData[] = {\r
- GPDO_RESET, // SIU_GPDO0\r
- GPDO_RESET, // SIU_GPDO1\r
- GPDO_RESET, // SIU_GPDO2\r
- GPDO_RESET, // SIU_GPDO3\r
- GPDO_RESET, // SIU_GPDO4\r
- GPDO_RESET, // SIU_GPDO5\r
- GPDO_RESET, // SIU_GPDO6\r
- GPDO_RESET, // SIU_GPDO7\r
- GPDO_RESET, // SIU_GPDO8\r
- GPDO_RESET, // SIU_GPDO9\r
- GPDO_RESET, // SIU_GPDO10\r
- GPDO_RESET, // SIU_GPDO11\r
- GPDO_RESET, // SIU_GPDO12\r
- GPDO_RESET, // SIU_GPDO13\r
- GPDO_RESET, // SIU_GPDO14\r
- GPDO_RESET, // SIU_GPDO15\r
- GPDO_RESET, // SIU_GPDO16\r
- GPDO_RESET, // SIU_GPDO17\r
- GPDO_RESET, // SIU_GPDO18\r
- GPDO_RESET, // SIU_GPDO19\r
- GPDO_RESET, // SIU_GPDO20\r
- GPDO_RESET, // SIU_GPDO21\r
- GPDO_RESET, // SIU_GPDO22\r
- GPDO_RESET, // SIU_GPDO23\r
- GPDO_RESET, // SIU_GPDO24\r
- GPDO_RESET, // SIU_GPDO25\r
- GPDO_RESET, // SIU_GPDO26\r
- GPDO_RESET, // SIU_GPDO27\r
- GPDO_RESET, // SIU_GPDO28\r
- GPDO_RESET, // SIU_GPDO29\r
- GPDO_RESET, // SIU_GPDO30\r
- GPDO_RESET, // SIU_GPDO31\r
- GPDO_RESET, // SIU_GPDO32\r
- GPDO_RESET, // SIU_GPDO33\r
- GPDO_RESET, // SIU_GPDO34\r
- GPDO_RESET, // SIU_GPDO35\r
- GPDO_RESET, // SIU_GPDO36\r
- GPDO_RESET, // SIU_GPDO37\r
- GPDO_RESET, // SIU_GPDO38\r
- GPDO_RESET, // SIU_GPDO39\r
- GPDO_RESET, // SIU_GPDO40\r
- GPDO_RESET, // SIU_GPDO41\r
- GPDO_RESET, // SIU_GPDO42\r
- GPDO_RESET, // SIU_GPDO43\r
- GPDO_RESET, // SIU_GPDO44\r
- GPDO_RESET, // SIU_GPDO45\r
- GPDO_RESET, // SIU_GPDO46\r
- GPDO_RESET, // SIU_GPDO47\r
- GPDO_RESET, // SIU_GPDO48\r
- GPDO_RESET, // SIU_GPDO49\r
- GPDO_RESET, // SIU_GPDO50\r
- GPDO_RESET, // SIU_GPDO51\r
- GPDO_RESET, // SIU_GPDO52\r
- GPDO_RESET, // SIU_GPDO53\r
- GPDO_RESET, // SIU_GPDO54\r
- GPDO_RESET, // SIU_GPDO55\r
- GPDO_RESET, // SIU_GPDO56\r
- GPDO_RESET, // SIU_GPDO57\r
- GPDO_RESET, // SIU_GPDO58\r
- GPDO_RESET, // SIU_GPDO59\r
- GPDO_RESET, // SIU_GPDO60\r
- GPDO_RESET, // SIU_GPDO61\r
- GPDO_RESET, // SIU_GPDO62\r
- GPDO_RESET, // SIU_GPDO63\r
- GPDO_RESET, // SIU_GPDO64\r
- GPDO_RESET, // SIU_GPDO65\r
- GPDO_RESET, // SIU_GPDO66\r
- GPDO_RESET, // SIU_GPDO67\r
- GPDO_RESET, // SIU_GPDO68\r
- GPDO_RESET, // SIU_GPDO69\r
- GPDO_RESET, // SIU_GPDO70\r
- GPDO_RESET, // SIU_GPDO71\r
- GPDO_RESET, // SIU_GPDO72\r
- GPDO_RESET, // SIU_GPDO73\r
- GPDO_RESET, // SIU_GPDO74\r
- GPDO_RESET, // SIU_GPDO75\r
- GPDO_RESET, // SIU_GPDO76\r
- GPDO_RESET, // SIU_GPDO77\r
- GPDO_RESET, // SIU_GPDO78\r
- GPDO_RESET, // SIU_GPDO79\r
- GPDO_RESET, // SIU_GPDO80\r
- GPDO_RESET, // SIU_GPDO81\r
- GPDO_RESET, // SIU_GPDO82\r
- GPDO_RESET, // SIU_GPDO83\r
- GPDO_RESET, // SIU_GPDO84\r
- GPDO_RESET, // SIU_GPDO85\r
- GPDO_RESET, // SIU_GPDO86\r
- GPDO_RESET, // SIU_GPDO87\r
- GPDO_RESET, // SIU_GPDO88\r
- GPDO_RESET, // SIU_GPDO89\r
- GPDO_RESET, // SIU_GPDO90\r
- GPDO_RESET, // SIU_GPDO91\r
- GPDO_RESET, // SIU_GPDO92\r
- GPDO_RESET, // SIU_GPDO93\r
- GPDO_RESET, // SIU_GPDO94\r
- GPDO_RESET, // SIU_GPDO95\r
- GPDO_RESET, // SIU_GPDO96\r
- GPDO_RESET, // SIU_GPDO97\r
- GPDO_RESET, // SIU_GPDO98\r
- GPDO_RESET, // SIU_GPDO99\r
- GPDO_RESET, // SIU_GPDO100\r
- GPDO_RESET, // SIU_GPDO101\r
- GPDO_RESET, // SIU_GPDO102\r
- GPDO_RESET, // SIU_GPDO103\r
- GPDO_RESET, // SIU_GPDO104\r
- GPDO_RESET, // SIU_GPDO105\r
- GPDO_RESET, // SIU_GPDO106\r
- GPDO_RESET, // SIU_GPDO107\r
- GPDO_RESET, // SIU_GPDO108\r
- GPDO_RESET, // SIU_GPDO109\r
- GPDO_RESET, // SIU_GPDO110\r
- GPDO_RESET, // SIU_GPDO111\r
- GPDO_RESET, // SIU_GPDO112\r
- GPDO_RESET, // SIU_GPDO113\r
- GPDO_RESET, // SIU_GPDO114\r
- GPDO_RESET, // SIU_GPDO115\r
- GPDO_RESET, // SIU_GPDO116\r
- GPDO_RESET, // SIU_GPDO117\r
- GPDO_RESET, // SIU_GPDO118\r
- GPDO_RESET, // SIU_GPDO119\r
- GPDO_RESET, // SIU_GPDO120\r
- GPDO_RESET, // SIU_GPDO121\r
- GPDO_RESET, // SIU_GPDO122\r
- GPDO_RESET, // SIU_GPDO123\r
- GPDO_RESET, // SIU_GPDO124\r
- GPDO_RESET, // SIU_GPDO125\r
- GPDO_RESET, // SIU_GPDO126\r
- GPDO_RESET, // SIU_GPDO127\r
- GPDO_RESET, // SIU_GPDO128\r
- GPDO_RESET, // SIU_GPDO129\r
- GPDO_RESET, // SIU_GPDO130\r
- GPDO_RESET, // SIU_GPDO131\r
- GPDO_RESET, // SIU_GPDO132\r
- GPDO_RESET, // SIU_GPDO133\r
- GPDO_RESET, // SIU_GPDO134\r
- GPDO_RESET, // SIU_GPDO135\r
- GPDO_RESET, // SIU_GPDO136\r
- GPDO_RESET, // SIU_GPDO137\r
- GPDO_RESET, // SIU_GPDO138\r
- GPDO_RESET, // SIU_GPDO139\r
- GPDO_RESET, // SIU_GPDO140\r
- GPDO_RESET, // SIU_GPDO141\r
- GPDO_RESET, // SIU_GPDO142\r
- GPDO_RESET, // SIU_GPDO143\r
- GPDO_RESET, // SIU_GPDO144\r
- GPDO_RESET, // SIU_GPDO145\r
- GPDO_RESET, // SIU_GPDO146\r
- GPDO_RESET, // SIU_GPDO147\r
- GPDO_RESET, // SIU_GPDO148\r
- GPDO_RESET, // SIU_GPDO149\r
- GPDO_RESET, // SIU_GPDO150\r
- GPDO_RESET, // SIU_GPDO151\r
- GPDO_RESET, // SIU_GPDO152\r
- GPDO_RESET, // SIU_GPDO153\r
- GPDO_RESET, // SIU_GPDO154\r
- GPDO_RESET, // SIU_GPDO155\r
- GPDO_RESET, // SIU_GPDO156\r
- GPDO_RESET, // SIU_GPDO157\r
- GPDO_RESET, // SIU_GPDO158\r
- GPDO_RESET, // SIU_GPDO159\r
- GPDO_RESET, // SIU_GPDO160\r
- GPDO_RESET, // SIU_GPDO161\r
- GPDO_RESET, // SIU_GPDO162\r
- GPDO_RESET, // SIU_GPDO163\r
- GPDO_RESET, // SIU_GPDO164\r
- GPDO_RESET, // SIU_GPDO165\r
- GPDO_RESET, // SIU_GPDO166\r
- GPDO_RESET, // SIU_GPDO167\r
- GPDO_RESET, // SIU_GPDO168\r
- GPDO_RESET, // SIU_GPDO169\r
- GPDO_RESET, // SIU_GPDO170\r
- GPDO_RESET, // SIU_GPDO171\r
- GPDO_RESET, // SIU_GPDO172\r
- GPDO_RESET, // SIU_GPDO173\r
- GPDO_RESET, // SIU_GPDO174\r
- GPDO_RESET, // SIU_GPDO175\r
- GPDO_RESET, // SIU_GPDO176\r
- GPDO_RESET, // SIU_GPDO177\r
- GPDO_RESET, // SIU_GPDO178\r
- GPDO_RESET, // SIU_GPDO179\r
- GPDO_RESET, // SIU_GPDO180\r
- GPDO_RESET, // SIU_GPDO181\r
- GPDO_RESET, // SIU_GPDO182\r
- GPDO_RESET, // SIU_GPDO183\r
- GPDO_RESET, // SIU_GPDO184\r
- GPDO_RESET, // SIU_GPDO185\r
- GPDO_RESET, // SIU_GPDO186\r
- GPDO_RESET, // SIU_GPDO187\r
- GPDO_RESET, // SIU_GPDO188\r
- GPDO_RESET, // SIU_GPDO189\r
- GPDO_RESET, // SIU_GPDO190\r
- GPDO_RESET, // SIU_GPDO191\r
- GPDO_RESET, // SIU_GPDO192\r
- GPDO_RESET, // SIU_GPDO193\r
- GPDO_RESET, // SIU_GPDO194\r
- GPDO_RESET, // SIU_GPDO195\r
- GPDO_RESET, // SIU_GPDO196\r
- GPDO_RESET, // SIU_GPDO197\r
- GPDO_RESET, // SIU_GPDO198\r
- GPDO_RESET, // SIU_GPDO199\r
- GPDO_RESET, // SIU_GPDO200\r
- GPDO_RESET, // SIU_GPDO201\r
- GPDO_RESET, // SIU_GPDO202\r
- GPDO_RESET, // SIU_GPDO203\r
- GPDO_RESET, // SIU_GPDO204\r
- GPDO_RESET, // SIU_GPDO205\r
- GPDO_RESET, // SIU_GPDO206\r
- GPDO_RESET, // SIU_GPDO207\r
- GPDO_RESET, // SIU_GPDO208\r
- GPDO_RESET, // SIU_GPDO209\r
- GPDO_RESET, // SIU_GPDO210\r
- GPDO_RESET, // SIU_GPDO211\r
- GPDO_RESET, // SIU_GPDO212\r
- GPDO_RESET, // SIU_GPDO213\r
+ PORT_GPDO_RESET, // SIU_GPDO0\r
+ PORT_GPDO_RESET, // SIU_GPDO1\r
+ PORT_GPDO_RESET, // SIU_GPDO2\r
+ PORT_GPDO_RESET, // SIU_GPDO3\r
+ PORT_GPDO_RESET, // SIU_GPDO4\r
+ PORT_GPDO_RESET, // SIU_GPDO5\r
+ PORT_GPDO_RESET, // SIU_GPDO6\r
+ PORT_GPDO_RESET, // SIU_GPDO7\r
+ PORT_GPDO_RESET, // SIU_GPDO8\r
+ PORT_GPDO_RESET, // SIU_GPDO9\r
+ PORT_GPDO_RESET, // SIU_GPDO10\r
+ PORT_GPDO_RESET, // SIU_GPDO11\r
+ PORT_GPDO_RESET, // SIU_GPDO12\r
+ PORT_GPDO_RESET, // SIU_GPDO13\r
+ PORT_GPDO_RESET, // SIU_GPDO14\r
+ PORT_GPDO_RESET, // SIU_GPDO15\r
+ PORT_GPDO_RESET, // SIU_GPDO16\r
+ PORT_GPDO_RESET, // SIU_GPDO17\r
+ PORT_GPDO_RESET, // SIU_GPDO18\r
+ PORT_GPDO_RESET, // SIU_GPDO19\r
+ PORT_GPDO_RESET, // SIU_GPDO20\r
+ PORT_GPDO_RESET, // SIU_GPDO21\r
+ PORT_GPDO_RESET, // SIU_GPDO22\r
+ PORT_GPDO_RESET, // SIU_GPDO23\r
+ PORT_GPDO_RESET, // SIU_GPDO24\r
+ PORT_GPDO_RESET, // SIU_GPDO25\r
+ PORT_GPDO_RESET, // SIU_GPDO26\r
+ PORT_GPDO_RESET, // SIU_GPDO27\r
+ PORT_GPDO_RESET, // SIU_GPDO28\r
+ PORT_GPDO_RESET, // SIU_GPDO29\r
+ PORT_GPDO_RESET, // SIU_GPDO30\r
+ PORT_GPDO_RESET, // SIU_GPDO31\r
+ PORT_GPDO_RESET, // SIU_GPDO32\r
+ PORT_GPDO_RESET, // SIU_GPDO33\r
+ PORT_GPDO_RESET, // SIU_GPDO34\r
+ PORT_GPDO_RESET, // SIU_GPDO35\r
+ PORT_GPDO_RESET, // SIU_GPDO36\r
+ PORT_GPDO_RESET, // SIU_GPDO37\r
+ PORT_GPDO_RESET, // SIU_GPDO38\r
+ PORT_GPDO_RESET, // SIU_GPDO39\r
+ PORT_GPDO_RESET, // SIU_GPDO40\r
+ PORT_GPDO_RESET, // SIU_GPDO41\r
+ PORT_GPDO_RESET, // SIU_GPDO42\r
+ PORT_GPDO_RESET, // SIU_GPDO43\r
+ PORT_GPDO_RESET, // SIU_GPDO44\r
+ PORT_GPDO_RESET, // SIU_GPDO45\r
+ PORT_GPDO_RESET, // SIU_GPDO46\r
+ PORT_GPDO_RESET, // SIU_GPDO47\r
+ PORT_GPDO_RESET, // SIU_GPDO48\r
+ PORT_GPDO_RESET, // SIU_GPDO49\r
+ PORT_GPDO_RESET, // SIU_GPDO50\r
+ PORT_GPDO_RESET, // SIU_GPDO51\r
+ PORT_GPDO_RESET, // SIU_GPDO52\r
+ PORT_GPDO_RESET, // SIU_GPDO53\r
+ PORT_GPDO_RESET, // SIU_GPDO54\r
+ PORT_GPDO_RESET, // SIU_GPDO55\r
+ PORT_GPDO_RESET, // SIU_GPDO56\r
+ PORT_GPDO_RESET, // SIU_GPDO57\r
+ PORT_GPDO_RESET, // SIU_GPDO58\r
+ PORT_GPDO_RESET, // SIU_GPDO59\r
+ PORT_GPDO_RESET, // SIU_GPDO60\r
+ PORT_GPDO_RESET, // SIU_GPDO61\r
+ PORT_GPDO_RESET, // SIU_GPDO62\r
+ PORT_GPDO_RESET, // SIU_GPDO63\r
+ PORT_GPDO_RESET, // SIU_GPDO64\r
+ PORT_GPDO_RESET, // SIU_GPDO65\r
+ PORT_GPDO_RESET, // SIU_GPDO66\r
+ PORT_GPDO_RESET, // SIU_GPDO67\r
+ PORT_GPDO_RESET, // SIU_GPDO68\r
+ PORT_GPDO_RESET, // SIU_GPDO69\r
+ PORT_GPDO_RESET, // SIU_GPDO70\r
+ PORT_GPDO_RESET, // SIU_GPDO71\r
+ PORT_GPDO_RESET, // SIU_GPDO72\r
+ PORT_GPDO_RESET, // SIU_GPDO73\r
+ PORT_GPDO_RESET, // SIU_GPDO74\r
+ PORT_GPDO_RESET, // SIU_GPDO75\r
+ PORT_GPDO_RESET, // SIU_GPDO76\r
+ PORT_GPDO_RESET, // SIU_GPDO77\r
+ PORT_GPDO_RESET, // SIU_GPDO78\r
+ PORT_GPDO_RESET, // SIU_GPDO79\r
+ PORT_GPDO_RESET, // SIU_GPDO80\r
+ PORT_GPDO_RESET, // SIU_GPDO81\r
+ PORT_GPDO_RESET, // SIU_GPDO82\r
+ PORT_GPDO_RESET, // SIU_GPDO83\r
+ PORT_GPDO_RESET, // SIU_GPDO84\r
+ PORT_GPDO_RESET, // SIU_GPDO85\r
+ PORT_GPDO_RESET, // SIU_GPDO86\r
+ PORT_GPDO_RESET, // SIU_GPDO87\r
+ PORT_GPDO_RESET, // SIU_GPDO88\r
+ PORT_GPDO_RESET, // SIU_GPDO89\r
+ PORT_GPDO_RESET, // SIU_GPDO90\r
+ PORT_GPDO_RESET, // SIU_GPDO91\r
+ PORT_GPDO_RESET, // SIU_GPDO92\r
+ PORT_GPDO_RESET, // SIU_GPDO93\r
+ PORT_GPDO_RESET, // SIU_GPDO94\r
+ PORT_GPDO_RESET, // SIU_GPDO95\r
+ PORT_GPDO_RESET, // SIU_GPDO96\r
+ PORT_GPDO_RESET, // SIU_GPDO97\r
+ PORT_GPDO_RESET, // SIU_GPDO98\r
+ PORT_GPDO_RESET, // SIU_GPDO99\r
+ PORT_GPDO_RESET, // SIU_GPDO100\r
+ PORT_GPDO_RESET, // SIU_GPDO101\r
+ PORT_GPDO_RESET, // SIU_GPDO102\r
+ PORT_GPDO_RESET, // SIU_GPDO103\r
+ PORT_GPDO_RESET, // SIU_GPDO104\r
+ PORT_GPDO_RESET, // SIU_GPDO105\r
+ PORT_GPDO_RESET, // SIU_GPDO106\r
+ PORT_GPDO_RESET, // SIU_GPDO107\r
+ PORT_GPDO_RESET, // SIU_GPDO108\r
+ PORT_GPDO_RESET, // SIU_GPDO109\r
+ PORT_GPDO_RESET, // SIU_GPDO110\r
+ PORT_GPDO_RESET, // SIU_GPDO111\r
+ PORT_GPDO_RESET, // SIU_GPDO112\r
+ PORT_GPDO_RESET, // SIU_GPDO113\r
+ PORT_GPDO_RESET, // SIU_GPDO114\r
+ PORT_GPDO_RESET, // SIU_GPDO115\r
+ PORT_GPDO_RESET, // SIU_GPDO116\r
+ PORT_GPDO_RESET, // SIU_GPDO117\r
+ PORT_GPDO_RESET, // SIU_GPDO118\r
+ PORT_GPDO_RESET, // SIU_GPDO119\r
+ PORT_GPDO_RESET, // SIU_GPDO120\r
+ PORT_GPDO_RESET, // SIU_GPDO121\r
+ PORT_GPDO_RESET, // SIU_GPDO122\r
+ PORT_GPDO_RESET, // SIU_GPDO123\r
+ PORT_GPDO_RESET, // SIU_GPDO124\r
+ PORT_GPDO_RESET, // SIU_GPDO125\r
+ PORT_GPDO_RESET, // SIU_GPDO126\r
+ PORT_GPDO_RESET, // SIU_GPDO127\r
+ PORT_GPDO_RESET, // SIU_GPDO128\r
+ PORT_GPDO_RESET, // SIU_GPDO129\r
+ PORT_GPDO_RESET, // SIU_GPDO130\r
+ PORT_GPDO_RESET, // SIU_GPDO131\r
+ PORT_GPDO_RESET, // SIU_GPDO132\r
+ PORT_GPDO_RESET, // SIU_GPDO133\r
+ PORT_GPDO_RESET, // SIU_GPDO134\r
+ PORT_GPDO_RESET, // SIU_GPDO135\r
+ PORT_GPDO_RESET, // SIU_GPDO136\r
+ PORT_GPDO_RESET, // SIU_GPDO137\r
+ PORT_GPDO_RESET, // SIU_GPDO138\r
+ PORT_GPDO_RESET, // SIU_GPDO139\r
+ PORT_GPDO_RESET, // SIU_GPDO140\r
+ PORT_GPDO_RESET, // SIU_GPDO141\r
+ PORT_GPDO_RESET, // SIU_GPDO142\r
+ PORT_GPDO_RESET, // SIU_GPDO143\r
+ PORT_GPDO_RESET, // SIU_GPDO144\r
+ PORT_GPDO_RESET, // SIU_GPDO145\r
+ PORT_GPDO_RESET, // SIU_GPDO146\r
+ PORT_GPDO_RESET, // SIU_GPDO147\r
+ PORT_GPDO_RESET, // SIU_GPDO148\r
+ PORT_GPDO_RESET, // SIU_GPDO149\r
+ PORT_GPDO_RESET, // SIU_GPDO150\r
+ PORT_GPDO_RESET, // SIU_GPDO151\r
+ PORT_GPDO_RESET, // SIU_GPDO152\r
+ PORT_GPDO_RESET, // SIU_GPDO153\r
+ PORT_GPDO_RESET, // SIU_GPDO154\r
+ PORT_GPDO_RESET, // SIU_GPDO155\r
+ PORT_GPDO_RESET, // SIU_GPDO156\r
+ PORT_GPDO_RESET, // SIU_GPDO157\r
+ PORT_GPDO_RESET, // SIU_GPDO158\r
+ PORT_GPDO_RESET, // SIU_GPDO159\r
+ PORT_GPDO_RESET, // SIU_GPDO160\r
+ PORT_GPDO_RESET, // SIU_GPDO161\r
+ PORT_GPDO_RESET, // SIU_GPDO162\r
+ PORT_GPDO_RESET, // SIU_GPDO163\r
+ PORT_GPDO_RESET, // SIU_GPDO164\r
+ PORT_GPDO_RESET, // SIU_GPDO165\r
+ PORT_GPDO_RESET, // SIU_GPDO166\r
+ PORT_GPDO_RESET, // SIU_GPDO167\r
+ PORT_GPDO_RESET, // SIU_GPDO168\r
+ PORT_GPDO_RESET, // SIU_GPDO169\r
+ PORT_GPDO_RESET, // SIU_GPDO170\r
+ PORT_GPDO_RESET, // SIU_GPDO171\r
+ PORT_GPDO_RESET, // SIU_GPDO172\r
+ PORT_GPDO_RESET, // SIU_GPDO173\r
+ PORT_GPDO_RESET, // SIU_GPDO174\r
+ PORT_GPDO_RESET, // SIU_GPDO175\r
+ PORT_GPDO_RESET, // SIU_GPDO176\r
+ PORT_GPDO_RESET, // SIU_GPDO177\r
+ PORT_GPDO_RESET, // SIU_GPDO178\r
+ PORT_GPDO_RESET, // SIU_GPDO179\r
+ PORT_GPDO_RESET, // SIU_GPDO180\r
+ PORT_GPDO_RESET, // SIU_GPDO181\r
+ PORT_GPDO_RESET, // SIU_GPDO182\r
+ PORT_GPDO_RESET, // SIU_GPDO183\r
+ PORT_GPDO_RESET, // SIU_GPDO184\r
+ PORT_GPDO_RESET, // SIU_GPDO185\r
+ PORT_GPDO_RESET, // SIU_GPDO186\r
+ PORT_GPDO_RESET, // SIU_GPDO187\r
+ PORT_GPDO_RESET, // SIU_GPDO188\r
+ PORT_GPDO_RESET, // SIU_GPDO189\r
+ PORT_GPDO_RESET, // SIU_GPDO190\r
+ PORT_GPDO_RESET, // SIU_GPDO191\r
+ PORT_GPDO_RESET, // SIU_GPDO192\r
+ PORT_GPDO_RESET, // SIU_GPDO193\r
+ PORT_GPDO_RESET, // SIU_GPDO194\r
+ PORT_GPDO_RESET, // SIU_GPDO195\r
+ PORT_GPDO_RESET, // SIU_GPDO196\r
+ PORT_GPDO_RESET, // SIU_GPDO197\r
+ PORT_GPDO_RESET, // SIU_GPDO198\r
+ PORT_GPDO_RESET, // SIU_GPDO199\r
+ PORT_GPDO_RESET, // SIU_GPDO200\r
+ PORT_GPDO_RESET, // SIU_GPDO201\r
+ PORT_GPDO_RESET, // SIU_GPDO202\r
+ PORT_GPDO_RESET, // SIU_GPDO203\r
+ PORT_GPDO_RESET, // SIU_GPDO204\r
+ PORT_GPDO_RESET, // SIU_GPDO205\r
+ PORT_GPDO_RESET, // SIU_GPDO206\r
+ PORT_GPDO_RESET, // SIU_GPDO207\r
+ PORT_GPDO_RESET, // SIU_GPDO208\r
+ PORT_GPDO_RESET, // SIU_GPDO209\r
+ PORT_GPDO_RESET, // SIU_GPDO210\r
+ PORT_GPDO_RESET, // SIU_GPDO211\r
+ PORT_GPDO_RESET, // SIU_GPDO212\r
+ PORT_GPDO_RESET, // SIU_GPDO213\r
};\r
\r
const Port_ConfigType PortConfigData =\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef PORT_CFG_H_\r
#define PORT_CFG_H_\r
\r
\r
#define PORT_VERSION_INFO_API STD_ON\r
#define PORT_DEV_ERROR_DETECT STD_ON\r
-#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
\r
typedef uint16 Port_PinType;\r
\r
-#define BIT0 (1<<15)\r
-#define BIT1 (1<<14)\r
-#define BIT2 (1<<13)\r
-#define BIT3 (1<<12)\r
-#define BIT4 (1<<11)\r
-#define BIT5 (1<<10)\r
-#define BIT6 (1<<9)\r
-#define BIT7 (1<<8)\r
-#define BIT8 (1<<7)\r
-#define BIT9 (1<<6)\r
-#define BIT10 (1<<5)\r
-#define BIT11 (1<<4)\r
-#define BIT12 (1<<3)\r
-#define BIT13 (1<<2)\r
-#define BIT14 (1<<1)\r
-#define BIT15 (1<<0)\r
-\r
-#define WPS_BIT BIT15\r
-#define WPE_BIT BIT14\r
-#define SRC1_BIT BIT13\r
-#define SRC0_BIT BIT12\r
-#define HYS_BIT BIT11\r
-#define ODE_BIT BIT10\r
-#define DSC1_BIT BIT9\r
-#define DSC0_BIT BIT8\r
-#define IBE_BIT BIT7\r
-#define OBE_BIT BIT6\r
-#define PA2_BIT BIT5\r
-#define PA1_BIT BIT4\r
-#define PA0_BIT BIT3\r
-\r
-#define PULL_UP (WPE_BIT|WPS_BIT)\r
-#define PULL_DOWN (WPE_BIT)\r
-#define PULL_NONE (0)\r
-#define SLEW_RATE_MIN (0)\r
-#define SLEW_RATE_MED (SRC1_BIT)\r
-#define SLEW_RATE_MAX (SRC1_BIT|SRC0_BIT)\r
-#define HYS_ENABLE (HYS_BIT)\r
-#define ODE_ENABLE (ODE_BIT)\r
-#define IBE_ENABLE (IBE_BIT)\r
-#define OBE_ENABLE (OBE_BIT)\r
-\r
-#define PA_IO (0)\r
-#define PA_PRIMARY_FUNC (PA2_BIT)\r
-#define PA_ALTERNATE_FUNC1 (PA1_BIT)\r
-#define PA_PRIMARY_FUNC1 (PA1_BIT|PA2_BIT)\r
-#define PA_ALTERNATE_FUNC2 (PA0_BIT)\r
-\r
-#define PCR_IO_INPUT (IBE_ENABLE|PULL_DOWN)\r
-#define PCR_IO_OUTPUT (OBE_ENABLE)\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_SRC1_BIT PORT_BIT13\r
+#define PORT_SRC0_BIT PORT_BIT12\r
+#define PORT_HYS_BIT PORT_BIT11\r
+#define PORT_ODE_BIT PORT_BIT10\r
+#define PORT_DSC1_BIT PORT_BIT9\r
+#define PORT_DSC0_BIT PORT_BIT8\r
+#define PORT_IBE_BIT PORT_BIT7\r
+#define PORT_OBE_BIT PORT_BIT6\r
+#define PORT_PA2_BIT PORT_BIT5\r
+#define PORT_PA1_BIT PORT_BIT4\r
+#define PORT_PA0_BIT PORT_BIT3\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE (0)\r
+#define PORT_SLEW_RATE_MIN (0)\r
+#define PORT_SLEW_RATE_MED (PORT_SRC1_BIT)\r
+#define PORT_SLEW_RATE_MAX (PORT_SRC1_BIT|PORT_SRC0_BIT)\r
+#define PORT_HYS_ENABLE (PORT_HYS_BIT)\r
+#define PORT_ODE_ENABLE (PORT_ODE_BIT)\r
+#define PORT_IBE_ENABLE (PORT_IBE_BIT)\r
+#define PORT_OBE_ENABLE (PORT_OBE_BIT)\r
+\r
+#define PORT_PA_IO (0)\r
+#define PORT_PA_PRIMARY_FUNC (PORT_PA2_BIT)\r
+#define PORT_PA_ALTERNATE_FUNC1 (PORT_PA1_BIT)\r
+#define PORT_PA_PRIMARY_FUNC1 (PORT_PA1_BIT|PORT_PA2_BIT)\r
+#define PORT_PA_ALTERNATE_FUNC2 (PORT_PA0_BIT)\r
+\r
+#define PORT_PCR_IO_INPUT (PORT_IBE_ENABLE|PORT_PULL_DOWN)\r
+#define PORT_PCR_IO_OUTPUT (PORT_OBE_ENABLE)\r
\r
// Should be this out of reset\r
-#define PCR_RESET (0)\r
-#define PCR_BOOTCFG (PCR_IO_INPUT)\r
-#define GPDO_RESET (0)\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_PCR_BOOTCFG (PORT_PCR_IO_INPUT)\r
+#define PORT_GPDO_RESET (0)\r
\r
typedef struct\r
{\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef PWM_CFG_H_\r
#define PWM_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef SPI_CFG_H_\r
#define SPI_CFG_H_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#include "Spi.h"\r
#include "Spi_Cfg.h"\r
#include <stdlib.h>\r
--- /dev/null
+/* MPC55xx Reset Control Word(RCW) */\r
+flash(R) : ORIGIN = 0x00000000, LENGTH = 2M\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x014000\r
-\r
-# ARCH defines\r
-ARCH=mpc55xx\r
-ARCH_FAM=ppc\r
-ARCH_MCU=mpc5633\r
-\r
-# CFG (y/n) macros\r
-CFG=PPC BOOKE E200Z3 MPC55XX MPC5633 BRD_MPC5633SIM SPE\r
-\r
-# What buildable modules does this board have, \r
-# default or private\r
-MOD_AVAIL=KERNEL RAMLOG MCU WDG WDGM PORT DIO WDG WDGM PWM CAN CANIF COM ADC DMA\r
-\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
-\r
-\r
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5633
+
+# CFG (y/n) macros
+CFG=PPC BOOKE E200Z3 MPC55XX MPC5633 BRD_MPC5633SIM SPE SIMULATOR
+
+# What buildable modules does this board have,
+# default or private
+
+# Memory + Peripherals
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG
+# System + Communication + Diagnostic
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE
+# Additional
+MOD_AVAIL+=RAMLOG
+
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
\r
\r
\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef MCU_CFG_H_\r
#define MCU_CFG_H_\r
\r
--- /dev/null
+flash(R) : ORIGIN = 0x00000000, LENGTH = 0x100000\r
+/* 5516S, 48K\r
+ * 5517S,5516G,5516E, 64K RAM\r
+ * 5517G,E , 80K RAM\r
+ */\r
+ram(RW) : ORIGIN = 0x40000000, LENGTH = 0x100000\r
--- /dev/null
+\r
+\r
+The STMicroelectronics STM32F103RB is an ARM 32-bit Cortex-M3 Microcontroller, \r
+\r
+ 72MHz\r
+ 128kB Flash \r
+ 20kB SRAM\r
+ 16-bit Timers with Input Capture, Output Compare and PWM, 16-bit 6-ch Advanced Timer \r
+ 2 16-bit Watchdog Timers \r
+ SysTick Timer \r
+ 2 SPI\r
+ 2 I2C \r
+ 3 USART \r
+ USB 2.0 Full Speed Interface \r
+ CAN 2.0B Active\r
+ 2 12-bit 16-ch A/D Converter \r
+ Fast I/O Ports\r
+ \r
+Memory Map\r
+ 0x0800_0000 -> Flash\r
+ 0x2000_0000 -> SRAM\r
+ 0x4000_0000 -> Internal registers\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cm3\r
+ARCH_FAM=arm\r
+ARCH_MCU=arm_cm3\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CM3\r
+# Add our board \r
+CFG+=BRD_STM32_MCBSTM32 \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_MD\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM GPT \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+= RAMLOG \r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
+# Use little heap\r
+def-y += HEAPSIZE=3000\r
+# Select the right device in ST header files.\r
+# [ STM32F10X_LD | STM32F10X_MD | STM32F10X_HD |STM32F10X_CL ]\r
+def-y += STM32F10X_MD\r
+\r
.groupConfigPtr = AdcGroupConfiguration,\r
.nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
};\r
-\r
+
* Created on: 2009-okt-02\r
* Author: Fredrik\r
*/\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef ADC_CFG_H_\r
#define ADC_CFG_H_\r
\r
-/* \r
-* Configuration of module Can (Can_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (CAN_SW_MAJOR_VERSION != 1) \r
-#error "Can: Configuration file version differs from BSW version."\r
-#endif\r
-\r
- \r
-\r
-\r
+/*
+* Configuration of module Can (Can_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+
+#if (CAN_SW_MAJOR_VERSION != 1)
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+\r
+#warning "This default file may only be used as an example!"
+
#ifndef CAN_CFG_H_\r
#define CAN_CFG_H_\r
\r
#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
\r
\r
+// Start stm32 unique
typedef enum {\r
- FLEXCAN_A = 0,\r
- CAN_CTRL_A = 0,\r
- FLEXCAN_B = 1,\r
- CAN_CTRL_B = 1,\r
- FLEXCAN_C = 2,\r
- CAN_CTRL_C = 2,\r
- FLEXCAN_D = 3,\r
- CAN_CTRL_D = 3,\r
- FLEXCAN_E = 4,\r
- CAN_CTRL_E = 4,\r
- FLEXCAN_F = 5,\r
- CAN_CTRL_F = 5,\r
- CAN_CONTROLLER_CNT = 6\r
+ CAN_CTRL_1 = 0,\r
+ CAN_CTRL_2 = 1,\r
+ CAN_CONTROLLER_CNT = 2\r
}CanControllerIdType;\r
+// End stm32 unique
\r
\r
typedef enum {\r
\r
\r
typedef enum {\r
+ HWObj_2,\r
NUM_OF_HTHS\r
} Can_Arc_HTHType;\r
\r
\r
typedef enum {\r
- RxMailboxes,\r
+ HWObj_1,\r
NUM_OF_HRHS\r
} Can_Arc_HRHType;\r
\r
// Specifies the InstanceId of this module instance. If only one instance is\r
// present it shall have the Id 0\r
int CanIndex;\r
-} Can_GeneralType;\r
-\r
-\r
-typedef uint32 Can_FilterMaskType;\r
-\r
+} Can_GeneralType;
+
+typedef uint32_t Can_FilterMaskType;
\r
typedef struct Can_HardwareObjectStruct {\r
// Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
--- /dev/null
+/*
+* Configuration of module Can (Can_Lcfg.c)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_Mask_1[] = {
+ 0xffffffff,
+ 0xffffffff,
+};\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
+ {\r
+ .CanObjectId = HWObj_1,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = HWObj_2,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_1,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+#define DIO_END_OF_LIST -1\r
+\r
+/** @name DIO channels\r
+ * HW specific dio channels.\r
+ */\r
+// Pin Name GPIO(PCR)Num\r
+//@{\r
+//* req DIO015 */\r
+//* req DIO017 */\r
+typedef enum\r
+{\r
+ DIO_CHANNEL_A0,\r
+ DIO_CHANNEL_A1,\r
+ DIO_CHANNEL_A2,\r
+ DIO_CHANNEL_A3,\r
+ DIO_CHANNEL_A4,\r
+ DIO_CHANNEL_A5,\r
+ DIO_CHANNEL_A6,\r
+ DIO_CHANNEL_A7,\r
+ DIO_CHANNEL_A8,\r
+ DIO_CHANNEL_A9,\r
+ DIO_CHANNEL_A10,\r
+ DIO_CHANNEL_A11,\r
+ DIO_CHANNEL_A12,\r
+ DIO_CHANNEL_A13,\r
+ DIO_CHANNEL_A14,\r
+ DIO_CHANNEL_A15,\r
+\r
+ DIO_CHANNEL_B0,\r
+ DIO_CHANNEL_B1,\r
+ DIO_CHANNEL_B2,\r
+ DIO_CHANNEL_B3,\r
+ DIO_CHANNEL_B4,\r
+ DIO_CHANNEL_B5,\r
+ DIO_CHANNEL_B6,\r
+ DIO_CHANNEL_B7,\r
+ DIO_CHANNEL_B8,\r
+ DIO_CHANNEL_B9,\r
+ DIO_CHANNEL_B10,\r
+ DIO_CHANNEL_B11,\r
+ DIO_CHANNEL_B12,\r
+ DIO_CHANNEL_B13,\r
+ DIO_CHANNEL_B14,\r
+ DIO_CHANNEL_B15,\r
+\r
+ DIO_CHANNEL_C0,\r
+ DIO_CHANNEL_C1,\r
+ DIO_CHANNEL_C2,\r
+ DIO_CHANNEL_C3,\r
+ DIO_CHANNEL_C4,\r
+ DIO_CHANNEL_C5,\r
+ DIO_CHANNEL_C6,\r
+ DIO_CHANNEL_C7,\r
+ DIO_CHANNEL_C8,\r
+ DIO_CHANNEL_C9,\r
+ DIO_CHANNEL_C10,\r
+ DIO_CHANNEL_C11,\r
+ DIO_CHANNEL_C12,\r
+ DIO_CHANNEL_C13,\r
+ DIO_CHANNEL_C14,\r
+ DIO_CHANNEL_C15,\r
+\r
+ DIO_CHANNEL_D0,\r
+ DIO_CHANNEL_D1,\r
+ DIO_CHANNEL_D2,\r
+ DIO_CHANNEL_D3,\r
+ DIO_CHANNEL_D4,\r
+ DIO_CHANNEL_D5,\r
+ DIO_CHANNEL_D6,\r
+ DIO_CHANNEL_D7,\r
+ DIO_CHANNEL_D8,\r
+ DIO_CHANNEL_D9,\r
+ DIO_CHANNEL_D10,\r
+ DIO_CHANNEL_D11,\r
+ DIO_CHANNEL_D12,\r
+ DIO_CHANNEL_D13,\r
+ DIO_CHANNEL_D14,\r
+ DIO_CHANNEL_D15,\r
+\r
+ DIO_CHANNEL_E0,\r
+ DIO_CHANNEL_E1,\r
+ DIO_CHANNEL_E2,\r
+ DIO_CHANNEL_E3,\r
+ DIO_CHANNEL_E4,\r
+ DIO_CHANNEL_E5,\r
+ DIO_CHANNEL_E6,\r
+ DIO_CHANNEL_E7,\r
+ DIO_CHANNEL_E8,\r
+ DIO_CHANNEL_E9,\r
+ DIO_CHANNEL_E10,\r
+ DIO_CHANNEL_E11,\r
+ DIO_CHANNEL_E12,\r
+ DIO_CHANNEL_E13,\r
+ DIO_CHANNEL_E14,\r
+ DIO_CHANNEL_E15,\r
+\r
+ DIO_CHANNEL_F0,\r
+ DIO_CHANNEL_F1,\r
+ DIO_CHANNEL_F2,\r
+ DIO_CHANNEL_F3,\r
+ DIO_CHANNEL_F4,\r
+ DIO_CHANNEL_F5,\r
+ DIO_CHANNEL_F6,\r
+ DIO_CHANNEL_F7,\r
+ DIO_CHANNEL_F8,\r
+ DIO_CHANNEL_F9,\r
+ DIO_CHANNEL_F10,\r
+ DIO_CHANNEL_F11,\r
+ DIO_CHANNEL_F12,\r
+ DIO_CHANNEL_F13,\r
+ DIO_CHANNEL_F14,\r
+ DIO_CHANNEL_F15,\r
+\r
+} Dio_Hw_ChannelType;\r
+//@}\r
+\r
+/** HW specific DIO port definitions. */\r
+/** @req DIO018 */\r
+/** @req DIO020 */\r
+typedef enum {\r
+ DIO_PORT_A,\r
+ DIO_PORT_B,\r
+ DIO_PORT_C,\r
+ DIO_PORT_D,\r
+ DIO_PORT_E,\r
+ DIO_PORT_F,\r
+} Dio_Hw_PortType;\r
+\r
+// Channels\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL1 (DIO_CHANNEL_B13)\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL2 (DIO_CHANNEL_B14)\r
+\r
+// Channel group\r
+#define DIO_GROUP_NAME_LED_GROUP (&DioConfigData[0])\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_LED_PORT (DIO_PORT_B)\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels\r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+\r
+#endif /* DIO_CFG_H_ */\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
\r
+const Dio_ChannelType DioChannelConfigData[] =\r
+{\r
+ DIO_CHANNEL_NAME_LED_CHANNEL1,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL2,\r
+ DIO_END_OF_LIST,\r
+};\r
\r
+const Dio_PortType DioPortConfigData[] =\r
+{\r
+ DIO_PORT_NAME_LED_PORT,\r
+ DIO_END_OF_LIST\r
+};\r
\r
-\r
-\r
-\r
-\r
-\r
-/*\r
- * WdgM_Lcfg.h\r
- *\r
- * Created on: 2009-jul-22\r
- * Author: rosa\r
- */\r
-\r
-#ifndef WDGM_LCFG_H_\r
-#define WDGM_LCFG_H_\r
-\r
-typedef enum\r
+const Dio_ChannelGroupType DioConfigData[] =\r
{\r
- WDBG_ALIVE_LOOP_BLINK_COMPONENT,\r
- WDBG_NBR_OF_ALIVE_SIGNALS\r
-}WdgM_SupervisedEntityIdType;\r
+ { .port = DIO_PORT_B, .offset = 7, .mask = 0x80, },\r
+ { .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
+};\r
\r
-#endif /* WDGM_LCFG_H_ */\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+
+const Fls_SectorType fls_SectorList[] = {
+ {
+ .FlsSectorStartaddress = (Fls_AddressType)0x08000000, // Start address of this sector
+ .FlsPageSize = (Fls_LengthType)(1 KB), // Page size of 1k
+ .FlsSectorSize = (Fls_LengthType)(1 KB),
+ // Number of continuous sectors with the above characteristics.
+ .FlsNumberOfSectors = (uint32)255
+ }
+};
+\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+ .FlsSectorList = &fls_SectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_SectorList)/sizeof(Fls_SectorType),\r
+ .FlsBlockToPartitionMap = NULL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef FLS_CFG_H_\r
+#define FLS_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define FLS_BASE_ADDRESS 0x08000000\r
+#define FLS_TOTAL_SIZE 0x40000 // from addr 0x0800_0000 to 0x0804_0000\r
+\r
+// Configuration description of a flashable sector\r
+typedef struct {\r
+ // Number of continuous sectors with the above characteristics.\r
+ Fls_LengthType FlsNumberOfSectors;\r
+\r
+ // Size of one page of this sector. Implementation Type: Fls_LengthType.\r
+ Fls_LengthType FlsPageSize;\r
+\r
+ // Size of this sector. Implementation Type: Fls_LengthTyp\r
+ Fls_LengthType FlsSectorSize;\r
+\r
+ // Start address of this sector\r
+ Fls_AddressType FlsSectorStartaddress;\r
+\r
+} Fls_SectorType;\r
+\r
+\r
+typedef struct {\r
+ // List of flash:able sectors and pages\r
+ const Fls_SectorType *FlsSectorList;\r
+\r
+ // Size of List of the FlsSectorList\r
+ const uint32 FlsSectorListSize;\r
+\r
+ uint8 *FlsBlockToPartitionMap;\r
+\r
+} Fls_ConfigType;\r
+\r
+extern const Fls_ConfigType FlsConfigSet[];\r
+\r
+\r
+#endif /* FLS_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+\r
+extern void Gpt2Notification(void);\r
+extern void OneWireEventhandler(void);\r
+extern void OneWireSequenceHandler(void);\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_TIM_2,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_TIM_3,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = OneWireSequenceHandler,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },\r
+ {\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Gpt GPT Driver\r
+ * @{ */\r
+\r
+/** @file Gpt_Cfg.h\r
+ * Definitions of configuration parameters for GPT Driver.\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Configuration is pre-compile only. Not supported. */\r
+#define GPT_VARIANT_PC STD_OFF\r
+/** Configuration is a mix of pre-compile and post-build */\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/** HW PIT channels */\r
+#define GPT_CHANNEL_TIM_1 0\r
+#define GPT_CHANNEL_TIM_2 1\r
+#define GPT_CHANNEL_TIM_3 2\r
+#define GPT_CHANNEL_TIM_4 3\r
+\r
+#define GPT_CHANNEL_CNT (GPT_CHANNEL_TIM_4 + 1)\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+/** Enable Development Error Trace */\r
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+/** Enables/Disables wakeup source reporting. Not supported. */\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+/** Build DeInit API */\r
+#define GPT_DEINIT_API STD_ON\r
+/** Build notification API */\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
+/** Build time remaining API */\r
+#define GPT_TIME_REMAINING_API STD_ON\r
+/** Build time elapsed API */\r
+#define GPT_TIME_ELAPSED_API STD_ON\r
+/** Build version info API */\r
+#define GPT_VERSION_INFO_API STD_ON\r
+/** Build wakeup API. Not supported */\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+/** This container contains the channel-wide configuration (parameters) of the\r
+ * GPT Driver */\r
+typedef struct {\r
+ /** GPT187: The GPT module specific clock input for the timer unit can\r
+ * statically be configured and allows to select different clock sources\r
+ * (external clock, internal GPT specific clock) per channel */\r
+ uint32 GptChannelClkSrc;\r
+\r
+ /** Channel Id of the GPT channel. */\r
+ Gpt_ChannelType GptChannelId;\r
+\r
+ /** Specifies the behaviour of the timer channel after the timeout has expired. */\r
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ /** Function pointer to callback function */\r
+ void (*GptNotification)();\r
+\r
+ /** GPT module specific prescaler factor per channel */\r
+ uint32 GptChannelPrescale;\r
+\r
+ /** GPT188: Enables wakeup capability of CPU for a channel when timeout\r
+ * period expires. This might be different to enabling the notification\r
+ * depending on hardware capabilities. Not supported. */\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+/** The list of channel configurations */\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
+/** @} */\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
#ifndef MCU_CFG_C_\r
#define MCU_CFG_C_\r
\r
.McuRamSectionSize = 0xFF,\r
}\r
};\r
+
+const Mcu_PerClockConfigType McuPerClockConfigData =
+{
+ .AHBClocksEnable = RCC_AHBPeriph_DMA1,
+ .APB1ClocksEnable = RCC_APB1Periph_TIM2 | RCC_APB1Periph_CAN1,
+ .APB2ClocksEnable = (RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA |
+ RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO),
+};
\r
Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
{\r
{\r
.McuClockReferencePointFrequency = 8000000UL,\r
- .Pll1 = 1,\r
- .Pll2 = 104,\r
- .Pll3 = 5,\r
+ .Pll1 = 9,\r
+ .Pll2 = 0,\r
+ .Pll3 = 0,\r
},\r
- {\r
- .McuClockReferencePointFrequency = 16000000UL,\r
- .Pll1 = 3,\r
- .Pll2 = 83,\r
- .Pll3 = 5,\r
- }\r
};\r
\r
\r
- const Mcu_ConfigType McuConfigData[] = {\r
+const Mcu_ConfigType McuConfigData[] = {\r
{\r
// Enables/Disables clock failure notification. In case this feature is not supported\r
// by HW the setting should be disabled.\r
\r
// This parameter shall represent the number of Modes available for the\r
// MCU. calculationFormula = Number of configured McuModeSettingConf\r
- .McuNumberOfMcuModes = 1, /* NOT USED */\r
+// .McuNumberOfMcuModes = 1, /* NOT USED */\r
\r
// This parameter shall represent the number of RAM sectors available for\r
// the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
.McuClockSettings = MCU_NBR_OF_CLOCKS,\r
\r
// Default clock frequency used\r
- .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_80MHZ,\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_8MHZ,\r
\r
// This parameter relates to the MCU specific reset configuration. This ap-\r
// plies to the function Mcu_PerformReset, which performs a microcontroller\r
// reset using the hardware feature of the microcontroller.\r
- .McuResetSetting = 0, /* NOT USED */\r
+// .McuResetSetting = 0, /* NOT USED */\r
\r
// This container contains the configuration (parameters) for the\r
// Clock settings of the MCU. Please see MCU031 for more in-\r
// This container contains the configuration (parameters) for the\r
// Mode setting of the MCU. Please see MCU035 for more infor-\r
// mation on the MCU mode settings.\r
- .McuModeSettingConfig = 0,\r
+// .McuModeSettingConfig = 0,\r
\r
// This container contains the configuration (parameters) for the\r
// RAM Sector setting. Please see MCU030 for more information\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#warning "This default file may only be used as an example!"
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+#endif
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
+typedef struct {
+ uint32 AHBClocksEnable;
+ uint32 APB1ClocksEnable;
+ uint32 APB2ClocksEnable;
+} Mcu_PerClockConfigType;
+
+extern const Mcu_PerClockConfigType McuPerClockConfigData;
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_8MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+\r
+#include "Port_Cfg.h"\r
+#include "stm32f10x_gpio.h"
+
+
+const uint32 remaps[] = {
+ GPIO_Remap1_CAN1,
+ GPIO_PartialRemap2_TIM2,
+};
+
+const GpioPinCnfMode_Type GPIOConf[] =
+{
+ /*GPIOA*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOB*/
+ {
+ .GpioPinCnfMode_15 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_14 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_12 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_11 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_10 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_9 = GPIO_OUTPUT_10MHz_MODE | GPIO_ALT_PUSHPULL_CNF,/* PB9 is CAN1_TX, remapped: */
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF,/* PB8 is CAN1_RX, remapped: */
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOC*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_11 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_10 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_OUTPUT_2MHz_MODE | GPIO_INPUT_PULLUP_CNF,
+ .GpioPinCnfMode_3 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_2 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_1 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_0 = GPIO_OUTPUT_2MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ },
+ /*GPIOD*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOE*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOF*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOG*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ }
+};
+
+const GpioPinOutLevel_Type GPIOOutConf[] =
+{
+ /* GPIOA */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOB */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOC */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOD */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOE */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOF */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOG */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+};
+
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = 7, // TODO Replace with sizeof expression\r
+ .padConfig = GPIOConf,
+ .outConfig = GPIOOutConf,\r
+
+ .remapCount = sizeof(remaps) / sizeof(uint32),
+ .remaps = &remaps[0]
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Port Port Driver
+ * @{ */
+
+/** @file Port_Cfg.h
+ * Definitions of configuration parameters for Port Driver.
+ */
+
+#warning "This default file may only be used as an example!"
+
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+
+/** Build version info API */
+#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */
+/** Enable Development Error Trace */
+#define PORT_DEV_ERROR_DETECT STD_ON
+/** Build change pin direction API */
+#define PORT_SET_PIN_DIRECTION_API STD_ON
+/** Allow Pin mode changes during runtime (not avail on this CPU) */
+#define PORT_SET_PIN_MODE_API STD_OFF
+
+#define GPIO_INPUT_MODE (0)
+#define GPIO_OUTPUT_10MHz_MODE (1)
+#define GPIO_OUTPUT_2MHz_MODE (2)
+#define GPIO_OUTPUT_50MHz_MODE (3)
+
+/* Valid for input modes. */
+#define GPIO_ANALOG_INPUT_CNF (0 << 2)
+#define GPIO_FLOATING_INPUT_CNF (1 << 2)
+#define GPIO_INPUT_PULLUP_CNF (2 << 2)
+#define GPIO_RESERVED_CNF (3 << 2)
+
+/* Valid for output modes. */
+#define GPIO_OUTPUT_PUSHPULL_CNF (0 << 2)
+#define GPIO_OUTPUT_OPENDRAIN_CNF (1 << 2)
+#define GPIO_ALT_PUSHPULL_CNF (2 << 2)
+#define GPIO_ALT_OPENDRAIN_CNF (3 << 2)
+
+#define GPIO_OUTPUT_LOW (0)
+#define GPIO_OUTPUT_HIGH (1)
+
+typedef struct
+{
+ uint8_t GpioPinCnfMode_0:4;
+ uint8_t GpioPinCnfMode_1:4;
+ uint8_t GpioPinCnfMode_2:4;
+ uint8_t GpioPinCnfMode_3:4;
+ uint8_t GpioPinCnfMode_4:4;
+ uint8_t GpioPinCnfMode_5:4;
+ uint8_t GpioPinCnfMode_6:4;
+ uint8_t GpioPinCnfMode_7:4;
+ uint8_t GpioPinCnfMode_8:4;
+ uint8_t GpioPinCnfMode_9:4;
+ uint8_t GpioPinCnfMode_10:4;
+ uint8_t GpioPinCnfMode_11:4;
+ uint8_t GpioPinCnfMode_12:4;
+ uint8_t GpioPinCnfMode_13:4;
+ uint8_t GpioPinCnfMode_14:4;
+ uint8_t GpioPinCnfMode_15:4;
+}GpioPinCnfMode_Type;
+
+typedef struct
+{
+ uint8_t GpioPinOutLevel_0:1;
+ uint8_t GpioPinOutLevel_1:1;
+ uint8_t GpioPinOutLevel_2:1;
+ uint8_t GpioPinOutLevel_3:1;
+ uint8_t GpioPinOutLevel_4:1;
+ uint8_t GpioPinOutLevel_5:1;
+ uint8_t GpioPinOutLevel_6:1;
+ uint8_t GpioPinOutLevel_7:1;
+ uint8_t GpioPinOutLevel_8:1;
+ uint8_t GpioPinOutLevel_9:1;
+ uint8_t GpioPinOutLevel_10:1;
+ uint8_t GpioPinOutLevel_11:1;
+ uint8_t GpioPinOutLevel_12:1;
+ uint8_t GpioPinOutLevel_13:1;
+ uint8_t GpioPinOutLevel_14:1;
+ uint8_t GpioPinOutLevel_15:1;
+}GpioPinOutLevel_Type;
+
+/* To be compatible with Port.h */
+typedef uint8_t Port_PinType;
+\r
+/** Top level configuration container */
+typedef struct\r
+{
+ /** Total number of pins */
+ uint16_t padCnt;
+ /** List of pin configurations */
+ const GpioPinCnfMode_Type *padConfig;
+ const GpioPinOutLevel_Type *outConfig;
+ /** Total number of pin default levels */\r
+
+ uint16_t remapCount;
+ const uint32_t* remaps;
+} Port_ConfigType;\r
+
+/** Instance of the top level configuration container */
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
+/** @} */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+\r
+\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+extern void MyPwmNotificationRoutine(void);\r
+\r
+// TODO remove, just put here for lazyness\r
+void MyPwmNotificationRoutine(void){\r
+}\r
+/* -----------------------------------------------------------------------\r
+ TIM4CLK = 72 MHz, Prescaler = 7199, TIM4 counter clock = 72 MHz\r
+ TIM4 ARR Register = 10000 => TIM4 Frequency = TIM4 counter clock/(ARR*(PSC + 1)\r
+ TIM4 Frequency = 1 Hz.\r
+ TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 12.5%\r
+\r
+\r
+ NOTE!!! All channels on one TIM uses the same Time base. The last configured will\r
+ set the Time base.\r
+ ----------------------------------------------------------------------- */\r
+const Pwm_ConfigType PwmConfig = {\r
+ .Channels = {\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 10000, 0x4000/*50%*/, 29, PWM_HIGH),\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 10000, 0x4000/*50%*/, 29, PWM_LOW)\r
+ },\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ .NotificationHandlers = {\r
+ MyPwmNotificationRoutine, // PWM_CHANNEL_1\r
+ NULL // PWM_CHANNEL_2\r
+ }\r
+#endif\r
+};\r
+\r
+\r
* Created on: 2009-okt-02\r
* Author: jonte\r
*/\r
+#warning "This default file may only be used as an example!"\r
+\r
#ifndef PWM_CFG_H_\r
#define PWM_CFG_H_\r
\r
* Maps a symbolic name to a hardware channel\r
*/\r
typedef enum {\r
- PWM_CHANNEL_1 = PWM_CHANNEL_43, //PB8\r
- PWM_CHANNEL_2 = PWM_CHANNEL_44, //PB9\r
+ PWM_CHANNEL_1 = PWM_CHANNEL_23, //PB10\r
+ PWM_CHANNEL_2 = PWM_CHANNEL_24, //PB11\r
PWM_NUMBER_OF_CHANNELS = 2\r
} Pwm_NamedChannelsType;\r
\r
--- /dev/null
+\r
+\r
+flash(R) : ORIGIN = 0x08000000, LENGTH = 128K\r
+ram(RW) : ORIGIN = 0x20000000, LENGTH = 20K\r
--- /dev/null
+\r
+\r
+The STMicroelectronics STM32F107VCT is an ARM 32-bit Cortex-M3 Microcontroller.\r
+Order info is STM3210C-EVAL.\r
+ \r
+Datasheets:\r
+ STM3210C-EVAL \r
+ http://www.st.com/stonline/products/literature/um/15082.pdf \r
+ \r
+ STM32F107VCT\r
+ http://www.st.com/stonline/products/literature/ds/15274.pdf\r
+ \r
+Info: \r
+ STM32F107VC\r
+ 72MHz\r
+ 256kB Flash \r
+ 64kB SRAM\r
+ 5 × USARTs,\r
+ 4 × 16-bit timers,\r
+ 2 × basic timers,\r
+ 3 × SPIs,\r
+ 2 × I2S,\r
+ 1 × I2C,\r
+ USB OTG FS,\r
+ 2 × CANs,\r
+ 1 × PWM timer,\r
+ 2 × ADCs,\r
+ 2 × DACs,\r
+ Ethernet\r
+ \r
+Memory Map:\r
+ 0x0800_0000 -> Flash\r
+ 0x2000_0000 -> SRAM\r
+ 0x4000_0000 -> Internal registers\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cm3\r
+ARCH_FAM=arm\r
+ARCH_MCU=arm_cm3\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CM3\r
+# Add our board \r
+CFG+=BRD_STM32_STM3210C \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_CL\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM GPT \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG TCF LWIP SLEEP RTE\r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
+# Select the right device in ST header files.\r
+# [ STM32F10X_LD | STM32F10X_MD | STM32F10X_HD |STM32F10X_CL ]\r
+def-y += STM32F10X_CL\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+\r
+#include "Adc.h"\r
+#include "stm32f10x_adc.h"\r
+\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+/* Configuration goes here. */\r
+void Adc_Group0Notification (void)\r
+{\r
+}\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+};\r
+\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_GROUP0_CHANNELS] =\r
+{\r
+ ADC_CH1,ADC_CH1,ADC_CH1,ADC_CH1\r
+};\r
+\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ {\r
+ // NOT SUPPORTED .accessMode = ADC_ACCESS_MODE_SINGLE,\r
+ .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ // NOT SUPPORTED .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ // NOT SUPPORTED .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group0Notification,\r
+ // NOT SUPPORTED .streamBufferMode = ADC_NO_STREAMING,\r
+ // NOT SUPPORTED .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .numberOfChannels = sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0]},\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+/* Group definitions. */\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_POT,\r
+ ADC_TEST_BOARD_POT2,\r
+ ADC_TEST_BOARD_POT3,\r
+ ADC_TEST_BOARD_POT4,\r
+ ADC_NBR_OF_GROUP0_CHANNELS,\r
+}Adc_Group0SignalType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK\r
+}Adc_ClockSourceType;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DISABLED,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ Adc_ClockSourceType clockSource;\r
+ uint8_t hwUnitId;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_64_CLOCKS,\r
+ ADC_CONVERSION_TIME_128_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+/* Channel definitions, std container */\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType adcChannelConvTime;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;\r
+ // NOT SUPPORTED Adc_ResolutionType adcChannelResolution;\r
+ // NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;\r
+} Adc_ChannelConfigurationType;\r
+\r
+/* Used ?? */\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+/* Implementation specific */\r
+typedef struct\r
+{\r
+ // NOT SUPPORTED Adc_GroupAccessModeType accessMode;\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ // NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;\r
+ // NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;\r
+ void (*groupCallback)(void);\r
+ // NOT SUPPORTED Adc_StreamBufferModeType streamBufferMode;\r
+ // NOT SUPPORTED Adc_StreamNumSampleType streamNumSamples;\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ // NOT SUPPORTED Adc_CommandType *commandBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+ // NOT SUPPORTED Dma_ChannelType dmaCommandChannel;\r
+ // NOT SUPPORTED Dma_ChannelType dmaResultChannel;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMACommands;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMAResults;\r
+} Adc_GroupDefType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_ChannelConfigurationType* channelConfigPtr;\r
+ const uint16_t nbrOfChannels;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+ const uint16_t nbrOfGroups;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig [];\r
+\r
+\r
+#endif /*ADC_CFG_H_*/\r
-/* \r
-* Configuration of module Can (Can_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (CAN_SW_MAJOR_VERSION != 1) \r
-#error "Can: Configuration file version differs from BSW version."\r
-#endif\r
-\r
- \r
-\r
-\r
+/*
+* Configuration of module Can (Can_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+
+#if (CAN_SW_MAJOR_VERSION != 1)
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+\r
+#warning "This default file may only be used as an example!"
+
#ifndef CAN_CFG_H_\r
#define CAN_CFG_H_\r
\r
#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
\r
\r
+// Start stm32 unique
typedef enum {\r
- FLEXCAN_A = 0,\r
- CAN_CTRL_A = 0,\r
- FLEXCAN_B = 1,\r
- CAN_CTRL_B = 1,\r
- FLEXCAN_C = 2,\r
- CAN_CTRL_C = 2,\r
- FLEXCAN_D = 3,\r
- CAN_CTRL_D = 3,\r
- FLEXCAN_E = 4,\r
- CAN_CTRL_E = 4,\r
- FLEXCAN_F = 5,\r
- CAN_CTRL_F = 5,\r
- CAN_CONTROLLER_CNT = 6\r
+ CAN_CTRL_1 = 0,\r
+ CAN_CTRL_2 = 1,\r
+ CAN_CONTROLLER_CNT = 2\r
}CanControllerIdType;\r
+// End stm32 unique
\r
\r
typedef enum {\r
\r
\r
typedef enum {\r
- HWObj_1,\r
+ HWObj_2,\r
NUM_OF_HTHS\r
} Can_Arc_HTHType;\r
\r
\r
typedef enum {\r
+ HWObj_1,\r
NUM_OF_HRHS\r
} Can_Arc_HRHType;\r
\r
// Specifies the InstanceId of this module instance. If only one instance is\r
// present it shall have the Id 0\r
int CanIndex;\r
-} Can_GeneralType;\r
-\r
-\r
-typedef uint32 Can_FilterMaskType;\r
-\r
+} Can_GeneralType;
+
+typedef uint32_t Can_FilterMaskType;
\r
typedef struct Can_HardwareObjectStruct {\r
// Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
--- /dev/null
+/*
+* Configuration of module Can (Can_Lcfg.c)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_Mask_1[] = {
+ 0xffffffff,
+ 0xffffffff,
+};\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
+ {\r
+ .CanObjectId = HWObj_1,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = HWObj_2,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_1,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+#define DIO_END_OF_LIST -1\r
+\r
+/** @name DIO channels\r
+ * HW specific dio channels.\r
+ */\r
+// Pin Name GPIO(PCR)Num\r
+//@{\r
+//* req DIO015 */\r
+//* req DIO017 */\r
+typedef enum\r
+{\r
+ DIO_CHANNEL_A0,\r
+ DIO_CHANNEL_A1,\r
+ DIO_CHANNEL_A2,\r
+ DIO_CHANNEL_A3,\r
+ DIO_CHANNEL_A4,\r
+ DIO_CHANNEL_A5,\r
+ DIO_CHANNEL_A6,\r
+ DIO_CHANNEL_A7,\r
+ DIO_CHANNEL_A8,\r
+ DIO_CHANNEL_A9,\r
+ DIO_CHANNEL_A10,\r
+ DIO_CHANNEL_A11,\r
+ DIO_CHANNEL_A12,\r
+ DIO_CHANNEL_A13,\r
+ DIO_CHANNEL_A14,\r
+ DIO_CHANNEL_A15,\r
+\r
+ DIO_CHANNEL_B0,\r
+ DIO_CHANNEL_B1,\r
+ DIO_CHANNEL_B2,\r
+ DIO_CHANNEL_B3,\r
+ DIO_CHANNEL_B4,\r
+ DIO_CHANNEL_B5,\r
+ DIO_CHANNEL_B6,\r
+ DIO_CHANNEL_B7,\r
+ DIO_CHANNEL_B8,\r
+ DIO_CHANNEL_B9,\r
+ DIO_CHANNEL_B10,\r
+ DIO_CHANNEL_B11,\r
+ DIO_CHANNEL_B12,\r
+ DIO_CHANNEL_B13,\r
+ DIO_CHANNEL_B14,\r
+ DIO_CHANNEL_B15,\r
+\r
+ DIO_CHANNEL_C0,\r
+ DIO_CHANNEL_C1,\r
+ DIO_CHANNEL_C2,\r
+ DIO_CHANNEL_C3,\r
+ DIO_CHANNEL_C4,\r
+ DIO_CHANNEL_C5,\r
+ DIO_CHANNEL_C6,\r
+ DIO_CHANNEL_C7,\r
+ DIO_CHANNEL_C8,\r
+ DIO_CHANNEL_C9,\r
+ DIO_CHANNEL_C10,\r
+ DIO_CHANNEL_C11,\r
+ DIO_CHANNEL_C12,\r
+ DIO_CHANNEL_C13,\r
+ DIO_CHANNEL_C14,\r
+ DIO_CHANNEL_C15,\r
+\r
+ DIO_CHANNEL_D0,\r
+ DIO_CHANNEL_D1,\r
+ DIO_CHANNEL_D2,\r
+ DIO_CHANNEL_D3,\r
+ DIO_CHANNEL_D4,\r
+ DIO_CHANNEL_D5,\r
+ DIO_CHANNEL_D6,\r
+ DIO_CHANNEL_D7,\r
+ DIO_CHANNEL_D8,\r
+ DIO_CHANNEL_D9,\r
+ DIO_CHANNEL_D10,\r
+ DIO_CHANNEL_D11,\r
+ DIO_CHANNEL_D12,\r
+ DIO_CHANNEL_D13,\r
+ DIO_CHANNEL_D14,\r
+ DIO_CHANNEL_D15,\r
+\r
+ DIO_CHANNEL_E0,\r
+ DIO_CHANNEL_E1,\r
+ DIO_CHANNEL_E2,\r
+ DIO_CHANNEL_E3,\r
+ DIO_CHANNEL_E4,\r
+ DIO_CHANNEL_E5,\r
+ DIO_CHANNEL_E6,\r
+ DIO_CHANNEL_E7,\r
+ DIO_CHANNEL_E8,\r
+ DIO_CHANNEL_E9,\r
+ DIO_CHANNEL_E10,\r
+ DIO_CHANNEL_E11,\r
+ DIO_CHANNEL_E12,\r
+ DIO_CHANNEL_E13,\r
+ DIO_CHANNEL_E14,\r
+ DIO_CHANNEL_E15,\r
+\r
+ DIO_CHANNEL_F0,\r
+ DIO_CHANNEL_F1,\r
+ DIO_CHANNEL_F2,\r
+ DIO_CHANNEL_F3,\r
+ DIO_CHANNEL_F4,\r
+ DIO_CHANNEL_F5,\r
+ DIO_CHANNEL_F6,\r
+ DIO_CHANNEL_F7,\r
+ DIO_CHANNEL_F8,\r
+ DIO_CHANNEL_F9,\r
+ DIO_CHANNEL_F10,\r
+ DIO_CHANNEL_F11,\r
+ DIO_CHANNEL_F12,\r
+ DIO_CHANNEL_F13,\r
+ DIO_CHANNEL_F14,\r
+ DIO_CHANNEL_F15,\r
+\r
+} Dio_Hw_ChannelType;\r
+//@}\r
+\r
+/** HW specific DIO port definitions. */\r
+/** @req DIO018 */\r
+/** @req DIO020 */\r
+typedef enum {\r
+ DIO_PORT_A,\r
+ DIO_PORT_B,\r
+ DIO_PORT_C,\r
+ DIO_PORT_D,\r
+ DIO_PORT_E,\r
+ DIO_PORT_F,\r
+} Dio_Hw_PortType;\r
+\r
+// Channels\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL1 (DIO_CHANNEL_D7)\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL2 (DIO_CHANNEL_D13)\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL3 (DIO_CHANNEL_D3)\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL4 (DIO_CHANNEL_D4)\r
+\r
+// Channel group\r
+#define DIO_GROUP_NAME_LED_GROUP (&DioConfigData[0])\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_LED_PORT (DIO_PORT_D)\r
+\r
+// Channels\r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+\r
+#endif /* DIO_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] =\r
+{\r
+ DIO_CHANNEL_NAME_LED_CHANNEL1,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL2,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL3,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL4,\r
+ DIO_END_OF_LIST,\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] =\r
+{\r
+ DIO_PORT_NAME_LED_PORT,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] =\r
+{\r
+ { .port = DIO_PORT_D, .offset = 0, .mask = 0x1094, },\r
+ { .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
+};\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+
+const Fls_SectorType fls_SectorList[] = {
+ {
+ .FlsSectorStartaddress = (Fls_AddressType)0x08000000, // Start address of this sector
+ .FlsPageSize = (Fls_LengthType)(1 KB), // Page size of 1k
+ .FlsSectorSize = (Fls_LengthType)(1 KB),
+ // Number of continuous sectors with the above characteristics.
+ .FlsNumberOfSectors = (uint32)255
+ }
+};
+\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+ .FlsSectorList = &fls_SectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_SectorList)/sizeof(Fls_SectorType),\r
+ .FlsBlockToPartitionMap = NULL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef FLS_CFG_H_\r
+#define FLS_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define FLS_BASE_ADDRESS 0x08000000\r
+#define FLS_TOTAL_SIZE 0x40000 // from addr 0x0800_0000 to 0x0804_0000\r
+\r
+// Configuration description of a flashable sector\r
+typedef struct {\r
+ // Number of continuous sectors with the above characteristics.\r
+ Fls_LengthType FlsNumberOfSectors;\r
+\r
+ // Size of one page of this sector. Implementation Type: Fls_LengthType.\r
+ Fls_LengthType FlsPageSize;\r
+\r
+ // Size of this sector. Implementation Type: Fls_LengthTyp\r
+ Fls_LengthType FlsSectorSize;\r
+\r
+ // Start address of this sector\r
+ Fls_AddressType FlsSectorStartaddress;\r
+\r
+} Fls_SectorType;\r
+\r
+\r
+typedef struct {\r
+ // List of flash:able sectors and pages\r
+ const Fls_SectorType *FlsSectorList;\r
+\r
+ // Size of List of the FlsSectorList\r
+ const uint32 FlsSectorListSize;\r
+\r
+ uint8 *FlsBlockToPartitionMap;\r
+\r
+} Fls_ConfigType;\r
+\r
+extern const Fls_ConfigType FlsConfigSet[];\r
+\r
+\r
+#endif /* FLS_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Gpt.h"\r
+#include "Gpt_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+#if defined(USE_KERNEL)\r
+extern void OsTick( void );\r
+#endif\r
+\r
+\r
+extern void Gpt2Notification(void);\r
+extern void OneWireEventhandler(void);\r
+extern void OneWireSequenceHandler(void);\r
+\r
+const Gpt_ConfigType GptConfigData[] =\r
+{\r
+ {\r
+ .GptChannelId = GPT_CHANNEL_TIM_2,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = NULL,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },{\r
+ .GptChannelId = GPT_CHANNEL_TIM_3,\r
+ .GptChannelMode = GPT_MODE_ONESHOT,\r
+ .GptChannelClkSrc = 0,\r
+ .GptNotification = OneWireSequenceHandler,\r
+ .GptChannelPrescale = 72, // 1MHz\r
+ .GptEnableWakeup = FALSE,\r
+ },\r
+ {\r
+ // Last channel in list\r
+ .GptChannelId = GPT_CHANNEL_ILL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @addtogroup Gpt GPT Driver\r
+ * @{ */\r
+\r
+/** @file Gpt_Cfg.h\r
+ * Definitions of configuration parameters for GPT Driver.\r
+ */\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef GPT_CFG_H_\r
+#define GPT_CFG_H_\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Configuration is pre-compile only. Not supported. */\r
+#define GPT_VARIANT_PC STD_OFF\r
+/** Configuration is a mix of pre-compile and post-build */\r
+#define GPT_VARIANT_PB STD_ON\r
+\r
+//#define DEC_TEST\r
+//#define GPT_TEST\r
+\r
+/** HW PIT channels */\r
+#define GPT_CHANNEL_TIM_1 0\r
+#define GPT_CHANNEL_TIM_2 1\r
+#define GPT_CHANNEL_TIM_3 2\r
+#define GPT_CHANNEL_TIM_4 3\r
+\r
+#define GPT_CHANNEL_CNT (GPT_CHANNEL_TIM_4 + 1)\r
+\r
+// Illegal channel\r
+#define GPT_CHANNEL_ILL 31\r
+\r
+/** Enable Development Error Trace */\r
+#define GPT_DEV_ERROR_DETECT STD_ON\r
+/** Enables/Disables wakeup source reporting. Not supported. */\r
+#define GPT_REPORT_WAKEUP_SOURCE STD_OFF\r
+/** Build DeInit API */\r
+#define GPT_DEINIT_API STD_ON\r
+/** Build notification API */\r
+#define GPT_ENABLE_DISABLE_NOTIFICATION_API STD_ON\r
+/** Build time remaining API */\r
+#define GPT_TIME_REMAINING_API STD_ON\r
+/** Build time elapsed API */\r
+#define GPT_TIME_ELAPSED_API STD_ON\r
+/** Build version info API */\r
+#define GPT_VERSION_INFO_API STD_ON\r
+/** Build wakeup API. Not supported */\r
+#define GPT_WAKEUP_FUNCTIONALITY_API STD_OFF\r
+\r
+\r
+/** This container contains the channel-wide configuration (parameters) of the\r
+ * GPT Driver */\r
+typedef struct {\r
+ /** GPT187: The GPT module specific clock input for the timer unit can\r
+ * statically be configured and allows to select different clock sources\r
+ * (external clock, internal GPT specific clock) per channel */\r
+ uint32 GptChannelClkSrc;\r
+\r
+ /** Channel Id of the GPT channel. */\r
+ Gpt_ChannelType GptChannelId;\r
+\r
+ /** Specifies the behaviour of the timer channel after the timeout has expired. */\r
+ Gpt_ChannelMode GptChannelMode;\r
+\r
+ /** Function pointer to callback function */\r
+ void (*GptNotification)();\r
+\r
+ /** GPT module specific prescaler factor per channel */\r
+ uint32 GptChannelPrescale;\r
+\r
+ /** GPT188: Enables wakeup capability of CPU for a channel when timeout\r
+ * period expires. This might be different to enabling the notification\r
+ * depending on hardware capabilities. Not supported. */\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+/** The list of channel configurations */\r
+extern const Gpt_ConfigType GptConfigData[];\r
+\r
+#endif /*GPT_CFG_H_*/\r
+/** @} */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+
+
+const Mcu_PerClockConfigType McuPerClockConfigData =
+{
+ .AHBClocksEnable = RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_ETH_MAC |
+ RCC_AHBPeriph_ETH_MAC_Tx | RCC_AHBPeriph_ETH_MAC_Rx,
+ .APB1ClocksEnable = RCC_APB1Periph_TIM2 | RCC_APB1Periph_CAN1,
+ .APB2ClocksEnable = (RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA |
+ RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC |
+ RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO),
+};
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 25000000UL,\r
+ .Pll1 = 9,\r
+ .Pll2 = 8,\r
+ .Pll3 = 0,\r
+ },\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+// .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_25MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+// .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+// .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#warning "This default file may only be used as an example!"
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+#endif
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
+typedef struct {
+ uint32 AHBClocksEnable;
+ uint32 APB1ClocksEnable;
+ uint32 APB2ClocksEnable;
+} Mcu_PerClockConfigType;
+
+extern const Mcu_PerClockConfigType McuPerClockConfigData;
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_25MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+\r
+#include "Port_Cfg.h"
+#include "stm32f10x_gpio.h"
+
+
+const uint32 remaps[] = {
+ GPIO_Remap_ETH,
+ GPIO_Remap2_CAN1,
+ GPIO_Remap_CAN2,
+};\r
+
+const GpioPinCnfMode_Type GPIOConf[] =
+{
+ /*GPIOA*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOB*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_12 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_11 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_OUTPUT_10MHz_MODE | GPIO_ALT_PUSHPULL_CNF,/* PB6 is CAN2_TX, remapped: */
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF,/* PB5 is CAN2_RX, remapped: */
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOC*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_ANALOG_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_1 = GPIO_OUTPUT_50MHz_MODE | GPIO_ALT_PUSHPULL_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOD*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_3 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_OUTPUT_10MHz_MODE | GPIO_ALT_PUSHPULL_CNF,/* PD1 is CAN1_TX, remapped: */
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_INPUT_PULLUP_CNF,/* PD0 is CAN1_RX, remapped: */
+ },
+ /*GPIOE*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOF*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ },
+ /*GPIOG*/
+ {
+ .GpioPinCnfMode_15 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_14 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_13 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_12 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_11 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_10 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_9 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_8 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_7 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_6 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_5 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_4 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_3 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_2 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_1 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ .GpioPinCnfMode_0 = GPIO_INPUT_MODE | GPIO_FLOATING_INPUT_CNF,
+ }
+};
+
+const GpioPinOutLevel_Type GPIOOutConf[] =
+{
+ /* GPIOA */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOB */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_HIGH,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOC */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOD */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOE */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOF */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+ /* GPIOG */
+ {
+ .GpioPinOutLevel_0 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_1 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_2 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_5 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_6 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_8 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_9 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_10 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_11 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_12 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_LOW,
+ .GpioPinOutLevel_15 = GPIO_OUTPUT_LOW,
+ },
+};
+
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = 7, // TODO Replace with sizeof expression\r
+ .padConfig = GPIOConf,
+ .outConfig = GPIOOutConf,
+
+ .remapCount = sizeof(remaps) / sizeof(uint32),
+ .remaps = &remaps[0]\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Port Port Driver
+ * @{ */
+
+/** @file Port_Cfg.h
+ * Definitions of configuration parameters for Port Driver.
+ */
+
+#warning "This default file may only be used as an example!"
+
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+
+/** Build version info API */
+#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */
+/** Enable Development Error Trace */
+#define PORT_DEV_ERROR_DETECT STD_ON
+/** Build change pin direction API */
+#define PORT_SET_PIN_DIRECTION_API STD_ON
+/** Allow Pin mode changes during runtime (not avail on this CPU) */
+#define PORT_SET_PIN_MODE_API STD_OFF
+
+#define GPIO_INPUT_MODE (0)
+#define GPIO_OUTPUT_10MHz_MODE (1)
+#define GPIO_OUTPUT_2MHz_MODE (2)
+#define GPIO_OUTPUT_50MHz_MODE (3)
+
+/* Valid for input modes. */
+#define GPIO_ANALOG_INPUT_CNF (0 << 2)
+#define GPIO_FLOATING_INPUT_CNF (1 << 2)
+#define GPIO_INPUT_PULLUP_CNF (2 << 2)
+#define GPIO_RESERVED_CNF (3 << 2)
+
+/* Valid for output modes. */
+#define GPIO_OUTPUT_PUSHPULL_CNF (0 << 2)
+#define GPIO_OUTPUT_OPENDRAIN_CNF (1 << 2)
+#define GPIO_ALT_PUSHPULL_CNF (2 << 2)
+#define GPIO_ALT_OPENDRAIN_CNF (3 << 2)
+
+#define GPIO_OUTPUT_LOW (0)
+#define GPIO_OUTPUT_HIGH (1)
+
+typedef struct
+{
+ uint8_t GpioPinCnfMode_0:4;
+ uint8_t GpioPinCnfMode_1:4;
+ uint8_t GpioPinCnfMode_2:4;
+ uint8_t GpioPinCnfMode_3:4;
+ uint8_t GpioPinCnfMode_4:4;
+ uint8_t GpioPinCnfMode_5:4;
+ uint8_t GpioPinCnfMode_6:4;
+ uint8_t GpioPinCnfMode_7:4;
+ uint8_t GpioPinCnfMode_8:4;
+ uint8_t GpioPinCnfMode_9:4;
+ uint8_t GpioPinCnfMode_10:4;
+ uint8_t GpioPinCnfMode_11:4;
+ uint8_t GpioPinCnfMode_12:4;
+ uint8_t GpioPinCnfMode_13:4;
+ uint8_t GpioPinCnfMode_14:4;
+ uint8_t GpioPinCnfMode_15:4;
+}GpioPinCnfMode_Type;
+
+typedef struct
+{
+ uint8_t GpioPinOutLevel_0:1;
+ uint8_t GpioPinOutLevel_1:1;
+ uint8_t GpioPinOutLevel_2:1;
+ uint8_t GpioPinOutLevel_3:1;
+ uint8_t GpioPinOutLevel_4:1;
+ uint8_t GpioPinOutLevel_5:1;
+ uint8_t GpioPinOutLevel_6:1;
+ uint8_t GpioPinOutLevel_7:1;
+ uint8_t GpioPinOutLevel_8:1;
+ uint8_t GpioPinOutLevel_9:1;
+ uint8_t GpioPinOutLevel_10:1;
+ uint8_t GpioPinOutLevel_11:1;
+ uint8_t GpioPinOutLevel_12:1;
+ uint8_t GpioPinOutLevel_13:1;
+ uint8_t GpioPinOutLevel_14:1;
+ uint8_t GpioPinOutLevel_15:1;
+}GpioPinOutLevel_Type;
+
+/* To be compatible with Port.h */
+typedef uint8_t Port_PinType;
+\r
+/** Top level configuration container */
+typedef struct\r
+{
+ /** Total number of pins */
+ uint16_t padCnt;
+ /** List of pin configurations */
+ const GpioPinCnfMode_Type *padConfig;
+ const GpioPinOutLevel_Type *outConfig;
+ /** Total number of pin default levels */
+
+ uint16_t remapCount;
+ const uint32_t* remaps;
+\r
+} Port_ConfigType;\r
+
+/** Instance of the top level configuration container */
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
+/** @} */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+\r
+\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+extern void MyPwmNotificationRoutine(void);\r
+\r
+// TODO remove, just put here for lazyness\r
+void MyPwmNotificationRoutine(void){\r
+}\r
+/* -----------------------------------------------------------------------\r
+ TIM4CLK = 72 MHz, Prescaler = 7199, TIM4 counter clock = 72 MHz\r
+ TIM4 ARR Register = 10000 => TIM4 Frequency = TIM4 counter clock/(ARR*(PSC + 1)\r
+ TIM4 Frequency = 1 Hz.\r
+ TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 12.5%\r
+\r
+\r
+ NOTE!!! All channels on one TIM uses the same Time base. The last configured will\r
+ set the Time base.\r
+ ----------------------------------------------------------------------- */\r
+const Pwm_ConfigType PwmConfig = {\r
+ .Channels = {\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 10000, 0x4000/*50%*/, 29, PWM_HIGH),\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 10000, 0x4000/*50%*/, 29, PWM_LOW)\r
+ },\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ .NotificationHandlers = {\r
+ MyPwmNotificationRoutine, // PWM_CHANNEL_1\r
+ NULL // PWM_CHANNEL_2\r
+ }\r
+#endif\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+#warning "This default file may only be used as an example!"\r
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+/****************************************************************************\r
+ * Global configuration options and defines\r
+ */\r
+/*\r
+ * PWM003: The detection of development errors is configurable (STD_ON/STD_OFF) at\r
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
+ * the detection of all development errors\r
+ */\r
+#define PWM_DEV_EROR_DETECT STD_ON\r
+#define PWM_GET_OUTPUT_STATE STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_ON\r
+\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+\r
+/*\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only STD_ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/*\r
+ * Setting to STD_ON freezes the current output state of a PWM channel when in\r
+ * debug mode.\r
+ */\r
+#define PWM_FREEZE_ENABLE STD_ON\r
+\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/*\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == eemios channel id.\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_11 = 0, // TIM1 Channel 1\r
+ PWM_CHANNEL_12,\r
+ PWM_CHANNEL_13,\r
+ PWM_CHANNEL_14,\r
+ PWM_CHANNEL_21, // TIM2 Channel 1\r
+ PWM_CHANNEL_22,\r
+ PWM_CHANNEL_23,\r
+ PWM_CHANNEL_24,\r
+ PWM_CHANNEL_31, // TIM3 Channel 1\r
+ PWM_CHANNEL_32,\r
+ PWM_CHANNEL_33,\r
+ PWM_CHANNEL_34,\r
+ PWM_CHANNEL_41, // TIM4 Channel 1\r
+ PWM_CHANNEL_42,\r
+ PWM_CHANNEL_43,\r
+ PWM_CHANNEL_44,\r
+ PWM_TOTAL_NOF_CHANNELS,\r
+} Pwm_ChannelType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_1 = PWM_CHANNEL_23, //PB10\r
+ PWM_CHANNEL_2 = PWM_CHANNEL_24, //PB11\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+\r
+/* NEW NEW */\r
+\r
+typedef enum {\r
+ PWM_CHANNEL_PRESCALER_1=0,\r
+ PWM_CHANNEL_PRESCALER_2,\r
+ PWM_CHANNEL_PRESCALER_3,\r
+ PWM_CHANNEL_PRESCALER_4,\r
+} Pwm_ChannelPrescalerType;\r
+\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period\r
+\r
+typedef struct {\r
+ /* Number of duty ticks */\r
+ uint32_t duty:32;\r
+ /* Length of period, in ticks */\r
+ uint32_t period:32;\r
+ /* Counter */\r
+ uint32_t counter:32;\r
+ /* Enable freezing the channel when in debug mode */\r
+ uint32_t freezeEnable:1;\r
+ /* Disable output */\r
+ uint32_t outputDisable:1;\r
+ /* Select which bus disables the bus\r
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */\r
+ uint32_t outputDisableSelect:2;\r
+ /* Prescale the emios clock some more? */\r
+ Pwm_ChannelPrescalerType prescaler:2;\r
+ /* Prescale the emios clock some more? */\r
+ uint32_t usePrescaler:1;\r
+ /* Whether to use DMA. Currently unsupported */\r
+ uint32_t useDma:1;\r
+ uint32_t reserved_2:1;\r
+ /* Input filter. Ignored in output mode. */\r
+ uint32_t inputFilter:4;\r
+ /* Input filter clock source. Ignored in output mode */\r
+ uint32_t filterClockSelect:1;\r
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */\r
+ uint32_t flagEnable:1;\r
+ uint32_t reserved_3:3;\r
+ /* Trigger a match on channel A */\r
+ uint32_t forceMatchA:1;\r
+ /* Triggers a match on channel B */\r
+ uint32_t forceMatchB:1;\r
+ uint32_t reserved_4:1;\r
+ /* We can use different buses for the counter. Use the internal counter */\r
+ uint32_t busSelect:2;\r
+ /* What edges to flag on? */\r
+ uint32_t edgeSelect:1;\r
+ /* Polarity of the channel */\r
+ uint32_t edgePolarity:1;\r
+ /* EMIOS mode. 0x58 for buffered output PWM */\r
+ uint32_t mode:7;\r
+} Pwm_ChannelRegisterType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelRegisterType r;\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];\r
+#endif\r
+} Pwm_ConfigType;\r
+\r
+// Channel configuration macro.\r
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \\r
+ {\\r
+ .channel = _hwchannel,\\r
+ .r = {\\r
+ DUTY_AND_PERIOD(_duty, _period),\\r
+ .freezeEnable = 1,\\r
+ .outputDisable = 0,\\r
+ .usePrescaler = 1,\\r
+ .prescaler = _prescaler,\\r
+ .useDma = 0,\\r
+ .flagEnable = 0, /* See PWM052 */ \\r
+ .busSelect = 3, /* Use the internal counter bus */\\r
+ .edgePolarity = _polarity,\\r
+ .mode = 0\\r
+ }\\r
+ }\r
+\r
+#endif /*PWM_CFG_H_*/\r
--- /dev/null
+\r
+\r
+flash(R) : ORIGIN = 0x08000000, LENGTH = 256K\r
+ram(RW) : ORIGIN = 0x20000000, LENGTH = 64K\r
--- /dev/null
+\r
+\r
+The Texas Instruments TMS570LS is an ARM 32-bit Cortes-R4 microcontroller.\r
+\r
+ \r
+Datasheets: \r
+ http://focus.ti.com/lit/ug/spnu489a/spnu489a.pdf \r
+
\ No newline at end of file
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cr4\r
+ARCH_FAM=arm\r
+ARCH_MCU=tms570ls\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CR4\r
+# Add our board \r
+CFG+= \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_CL\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+MOD_AVAIL+=MCU\r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE CAN PORT DIO\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
--- /dev/null
+/* These defines are overriden by rte generated file with the same name */\r
+#undef CALIBRATION_INITIALIZED_RAM\r
+#undef CALIBRATION_ENABLED\r
+#undef CALIBRATION_FLS_START\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Dec 10 11:45:13 CET 2010\r
+ */\r
+\r
+
+#if (DIO_SW_MAJOR_VERSION != 1)
+#error "Dio: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+#include "Port.h"\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ DIO_PORT_A = 0,\r
+ DIO_PORT_B = 1,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_DioChannel_1 PORT_PAD_3\r
+\r
+// Channel group\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_DioPort_1 (DIO_PORT_A)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Dec 10 11:45:13 CET 2010\r
+ */\r
+\r
+\r
+ \r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_DioChannel_1,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_DioPort_1, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = {\r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = DIO_END_OF_LIST, \r
+ .mask = DIO_END_OF_LIST, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Oct 25 12:52:40 CEST 2010\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 4, // REFCLKDIV\r
+ .Pll2 = 100, // PLLMULT\r
+ .Pll3 = 2, // ODPLL\r
+ .Pll4 = 2, // PLLDIV\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+#endif
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
+typedef struct {
+ uint32 AHBClocksEnable;
+ uint32 APB1ClocksEnable;
+ uint32 APB2ClocksEnable;
+} Mcu_PerClockConfigType;
+
+extern const Mcu_PerClockConfigType McuPerClockConfigData;
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_25MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Dec 10 11:45:10 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include "Port.h"\r
+\r
+\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .pins = {\r
+ {\r
+ .pin = PORT_PIN_DCAN1_TX,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_DCAN1_RX,\r
+ .conf = ( PORT_PIN_IN | PORT_FUNC | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_DCAN2_TX,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_DCAN2_RX,\r
+ .conf = ( PORT_PIN_IN | PORT_FUNC | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_DCAN3_TX,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_DCAN3_RX,\r
+ .conf = ( PORT_PIN_IN | PORT_FUNC | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_GIOA0,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC_NO | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_GIOA3,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC_NO | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_GIOA4,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC_NO | PORT_PULL_NONE ),\r
+ }, \r
+ {\r
+ .pin = PORT_PIN_GIOA5,\r
+ .conf = ( PORT_PIN_OUT | PORT_FUNC_NO | PORT_PULL_NONE ),\r
+ }, \r
+ }\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Dec 10 11:45:10 CET 2010\r
+ */\r
+\r
+
+#if (PORT_SW_MAJOR_VERSION != 1)
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
+/** Allow Pin mode changes during runtime */\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+\r
+#define PORT_NUMBER_OF_PINS 10\r
+\r
+#define PORT_FUNC (1 << 1)\r
+#define PORT_FUNC_NO (0 << 1)\r
+#define PORT_PULL_NONE (1 << 2)\r
+#define PORT_PULL_UP (1 << 3)\r
+#define PORT_PULL_DOWN (0 << 3)\r
+#define PORT_ODE_ENABLE (1 << 4)\r
+#define PORT_DIRECTION_CHANGEABLE (1 << 5)\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum\r
+{\r
+ PORT_PIN_DCAN1_TX = 0x0800,\r
+ PORT_PIN_DCAN1_RX = 0x0801,\r
+ PORT_PIN_DCAN2_TX = 0x0900,\r
+ PORT_PIN_DCAN2_RX = 0x0901,\r
+ PORT_PIN_DCAN3_TX = 0x0a00,\r
+ PORT_PIN_DCAN3_RX = 0x0a01,\r
+ PORT_PIN_GIOA0 = 0x0000,\r
+ PORT_PIN_GIOA3 = 0x0003,\r
+ PORT_PIN_GIOA4 = 0x0004,\r
+ PORT_PIN_GIOA5 = 0x0005, \r
+} Port_PinType;\r
+\r
+/** Port pad mappings */\r
+#define PORT_PAD_106 0x0800 // PORT_PIN_DCAN1_TX\r
+#define PORT_PAD_107 0x0801 // PORT_PIN_DCAN1_RX\r
+#define PORT_PAD_108 0x0900 // PORT_PIN_DCAN2_TX\r
+#define PORT_PAD_109 0x0901 // PORT_PIN_DCAN2_RX\r
+#define PORT_PAD_110 0x0a00 // PORT_PIN_DCAN3_TX\r
+#define PORT_PAD_111 0x0a01 // PORT_PIN_DCAN3_RX\r
+#define PORT_PAD_0 0x0000 // PORT_PIN_GIOA0\r
+#define PORT_PAD_3 0x0003 // PORT_PIN_GIOA3\r
+#define PORT_PAD_4 0x0004 // PORT_PIN_GIOA4\r
+#define PORT_PAD_5 0x0005 // PORT_PIN_GIOA5\r
+\r
+typedef struct {\r
+ Port_PinType pin;\r
+ uint8 conf;\r
+} Port_ConfiguredPinType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct\r
+{\r
+ const Port_ConfiguredPinType pins[PORT_NUMBER_OF_PINS];\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+\r
+intvecs(R) : ORIGIN = 0x0000000, LENGTH = 0x60\r
+flash(R) : ORIGIN = 0x00000060, LENGTH = 2M\r
+ram(RW) : ORIGIN = 0x08000000, LENGTH = 160K\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+/*
+ * DESCRIPTION
+ * A circular buffer implementation.
+ *
+ * This file implements the following versions:
+ * 1. CirqBuffDynXXXX
+ * - The size of the data is not known of compile time
+ * (semidynamic, since there is no free() function )
+ * 2. CirqBuffXXX
+ * - A static implementation, data is known at compile time.
+ * (implemented in the header file?)
+ *
+ * Implementation note:
+ * - CirqBuffDynXXXX, valgrind: OK
+ * - coverage: Not run
+ *
+ */
+//#define _TEST_CIRQ_BUFFER_DYN_
+#include <stdlib.h>
+#include <string.h>
+#include <stdint.h>
+#include "Cpu.h"
+#include "cirq_buffer.h"
+
+#ifdef _TEST_CIRQ_BUFFER_DYN_
+#include <assert.h>
+#endif
+
+#define MEMCPY(_x,_y,_z) __builtin_memcpy(_x,_y,_z)
+//#define MEMCPY(_x,_y,_z) memcpy(_x,_y,_z)
+
+
+/* TODO: Not threadsafe, add DisableAllInterrts()/EnableAllInterrupts() */
+
+CirqBufferType CirqBuffStatCreate(void *buffer, int maxCnt, size_t dataSize) {
+ CirqBufferType cirqbuffer;
+ cirqbuffer.bufStart = buffer;
+ cirqbuffer.maxCnt = maxCnt;
+ cirqbuffer.bufEnd = (char *)cirqbuffer.bufStart + dataSize*maxCnt;
+ cirqbuffer.head = cirqbuffer.bufStart;
+ cirqbuffer.tail = cirqbuffer.bufStart;
+ cirqbuffer.dataSize = dataSize;
+ cirqbuffer.currCnt = 0;
+ return cirqbuffer;
+}
+
+CirqBufferType *CirqBuffDynCreate( size_t size, size_t dataSize ) {
+ CirqBufferType *cPtr;
+ cPtr = malloc(sizeof(CirqBufferType));
+ if( cPtr == NULL ) {
+ return NULL;
+ }
+ cPtr->maxCnt = size;
+ cPtr->dataSize = dataSize;
+ cPtr->bufStart = malloc(dataSize*size);
+ cPtr->bufEnd = (char *)cPtr->bufStart + dataSize*size;
+ cPtr->head = cPtr->bufStart;
+ cPtr->tail = cPtr->bufStart;
+ cPtr->currCnt = 0;
+ return cPtr;
+}
+
+
+
+int CirqBuffDynDestroy(CirqBufferType *cPtr ) {
+ free(cPtr->bufStart);
+ free(cPtr);
+ return 0;
+}
+
+int CirqBuffPush( CirqBufferType *cPtr, void *dataPtr ) {
+ uint32_t flags;
+ Irq_Save(flags);
+ if( (cPtr->currCnt == cPtr->maxCnt) || (cPtr==NULL) ) {
+ Irq_Restore(flags);
+ return 1; /* No more room */
+ }
+ MEMCPY(cPtr->head,dataPtr,cPtr->dataSize);
+ cPtr->head = (char *)cPtr->head + cPtr->dataSize;
+ if( cPtr->head == cPtr->bufEnd) {
+ cPtr->head = cPtr->bufStart;
+ }
+ ++cPtr->currCnt;
+ Irq_Restore(flags);
+
+ return 0;
+}
+
+int CirqBuffPop(CirqBufferType *cPtr, void *dataPtr ) {
+ uint32_t flags;
+ Irq_Save(flags);
+ if( (cPtr->currCnt == 0) || (cPtr==NULL) ) {
+ Irq_Restore(flags);
+ return 1;
+ }
+ MEMCPY(dataPtr,cPtr->tail,cPtr->dataSize);
+ cPtr->tail = (char *)cPtr->tail + cPtr->dataSize;
+ if( cPtr->tail == cPtr->bufEnd) {
+ cPtr->tail = cPtr->bufStart;
+ }
+ --cPtr->currCnt;
+ Irq_Restore(flags);
+ return 0;
+}
+
+
+
+#ifdef _TEST_CIRQ_BUFFER_DYN_
+int main( void ) {
+ CirqBufferType *cPtr;
+ uint8_t *dataPtr;
+ int rv;
+
+#define DATA_SIZE 4
+#define QSIZE 8
+ cPtr = CirqBuffDynCreate(QSIZE, DATA_SIZE );
+
+ dataPtr = malloc(DATA_SIZE);
+ dataPtr[0] = 1;
+ rv = CirqBuffPush(cPtr,dataPtr);
+ assert(rv == 0);
+ free(dataPtr);
+
+ dataPtr = malloc(DATA_SIZE);
+ dataPtr[0] = 2;
+ rv = CirqBuffPush(cPtr,dataPtr);
+ assert(rv == 0);
+ free(dataPtr);
+
+ dataPtr = malloc(DATA_SIZE);
+ rv = CirqBuffPop(cPtr,dataPtr);
+ assert( dataPtr[0] == 1);
+ assert(rv == 0);
+ free(dataPtr);
+
+ dataPtr = malloc(DATA_SIZE);
+ rv = CirqBuffPop(cPtr,dataPtr);
+ assert( dataPtr[0] == 2);
+ assert(rv == 0);
+ free(dataPtr);
+
+ CirqBuffDynDestroy(cPtr);
+}
+#endif
+
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * A message box implementation.\r
+ *\r
+ * Notes:\r
+ * - Uses heap\r
+ * - Do NOT use Arc_MBoxDestroy() call, it's there for testing purposes only.
+ */\r
+\r
+//#define _TEST_MBOX_\r
+\r
+#include "mbox.h"\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+\r
+\r
+#ifdef _TEST_MBOX_\r
+#include <stdio.h>\r
+#include <assert.h>\r
+#endif\r
+\r
+\r
+\r
+Arc_MBoxType* Arc_MBoxCreate( size_t size ) {\r
+ Arc_MBoxType *mPtr;\r
+\r
+ mPtr = malloc(sizeof(Arc_MBoxType));\r
+ mPtr->cirqPtr = CirqBuffDynCreate(size,sizeof(void *));\r
+\r
+ return mPtr;\r
+}\r
+\r
+\r
+void Arc_MBoxDestroy( Arc_MBoxType *mPtr ) {\r
+ CirqBuffDynDestroy(mPtr->cirqPtr);\r
+ free(mPtr);\r
+}\r
+\r
+/**\r
+ * Post a message to a box, non-blocking.\r
+ *
+ */\r
+int Arc_MBoxPost( Arc_MBoxType *mPtr, void *msg ) {\r
+ int rv;\r
+ rv = CirqBuffPush(mPtr->cirqPtr,msg);\r
+ if( rv != 0) {\r
+ return 1;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ *
+ */\r
+int Arc_MBoxFetch(Arc_MBoxType *mPtr, void *msg)\r
+{\r
+ int rv;\r
+ rv = CirqBuffPop(mPtr->cirqPtr,msg);\r
+ if(rv != 0) {\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+#ifdef _TEST_MBOX_\r
+int main( void ) {\r
+ Arc_MBoxType *myBoxes[10];\r
+ uint8_t *dataPtr;\r
+\r
+ printf("Hej\n");\r
+\r
+ myBoxes[0] = Arc_MBoxCreate(2);\r
+ myBoxes[1] = Arc_MBoxCreate(4);\r
+\r
+ dataPtr = malloc(10);\r
+ dataPtr[0] = 1;\r
+ Arc_MBoxPost(myBoxes[0],&dataPtr);\r
+\r
+ dataPtr = malloc(20);\r
+ dataPtr[0] = 2;\r
+ Arc_MBoxPost(myBoxes[0],&dataPtr);\r
+\r
+ Arc_MBoxFetch(myBoxes[0],&dataPtr);\r
+ assert(dataPtr[0] == 1);\r
+ free(dataPtr);\r
+\r
+ Arc_MBoxFetch(myBoxes[0],&dataPtr);\r
+ assert(dataPtr[0] == 2);\r
+ free(dataPtr);\r
+\r
+ Arc_MBoxDestroy(myBoxes[0]);\r
+ Arc_MBoxDestroy(myBoxes[1]);\r
+ return 0;\r
+}\r
+\r
+#endif\r
\r
#if defined(CFG_ARM_CM3)\r
#include "irq_types.h"\r
-#include "core_cm3.h"\r
+#include "stm32f10x.h"\r
+#endif\r
+\r
+#ifdef USE_TTY_TCF_STREAMS\r
+#include "streams.h"\r
#endif\r
\r
\r
#if defined(MC912DG128A)\r
static volatile unsigned char g_TWBuffer[TWBUFF_LEN];\r
static volatile unsigned char g_TRBuffer[TRBUFF_LEN];\r
-static volatile char g_TConn __attribute__ ((section (".winidea_port")));\r
+volatile char g_TConn __attribute__ ((section (".winidea_port")));\r
\r
#else\r
static volatile unsigned char g_TWBuffer[TWBUFF_LEN] __attribute__ ((aligned (0x100))); // Transmit to WinIDEA terminal\r
static volatile unsigned char g_TRBuffer[TRBUFF_LEN] __attribute__ ((aligned (0x100)));\r
-static volatile char g_TConn __attribute__ ((section (".winidea_port")));\r
+volatile char g_TConn __attribute__ ((section (".winidea_port")));\r
+\r
+#endif\r
+\r
+#endif\r
+\r
+#ifdef USE_TTY_CODE_COMPOSER\r
+\r
+#define _DTOPEN (0xF0)\r
+#define _DTCLOSE (0xF1)\r
+#define _DTREAD (0xF2)\r
+#define _DTWRITE (0xF3)\r
+#define _DTLSEEK (0xF4)\r
+#define _DTUNLINK (0xF5)\r
+#define _DTGETENV (0xF6)\r
+#define _DTRENAME (0xF7)\r
+#define _DTGETTIME (0xF8)\r
+#define _DTGETCLK (0xF9)\r
+#define _DTSYNC (0xFF)\r
+\r
+#define LOADSHORT(x,y,z) { x[(z)] = (unsigned short) (y); \\r
+ x[(z)+1] = (unsigned short) (y) >> 8; }\r
+\r
+#define UNLOADSHORT(x,z) ((short) ( (short) x[(z)] + \\r
+ ((short) x[(z)+1] << 8)))\r
+\r
+#define PACKCHAR(val, base, byte) ( (base)[(byte)] = (val) )\r
+\r
+#define UNPACKCHAR(base, byte) ( (base)[byte] )\r
+\r
+\r
+static unsigned char parmbuf[8];\r
+#define BUFSIZ 512\r
+#define CC_BUFFER_SIZE ((BUFSIZ)+32)\r
+volatile unsigned int _CIOBUF_[CC_BUFFER_SIZE] __attribute__ ((section (".cio")));\r
+\r
+/***************************************************************************/\r
+/* */\r
+/* WRITEMSG() - Sends the passed data and parameters on to the host. */\r
+/* */\r
+/***************************************************************************/\r
+void writemsg(unsigned char command,\r
+ register const unsigned char *parm,\r
+ register const char *data,\r
+ unsigned int length)\r
+{\r
+ volatile unsigned char *p = (volatile unsigned char *)(_CIOBUF_+1);\r
+ unsigned int i;\r
+\r
+ /***********************************************************************/\r
+ /* THE LENGTH IS WRITTEN AS A TARGET INT */\r
+ /***********************************************************************/\r
+ _CIOBUF_[0] = length;\r
+\r
+ /***********************************************************************/\r
+ /* THE COMMAND IS WRITTEN AS A TARGET BYTE */\r
+ /***********************************************************************/\r
+ *p++ = command;\r
+\r
+ /***********************************************************************/\r
+ /* PACK THE PARAMETERS AND DATA SO THE HOST READS IT AS BYTE STREAM */\r
+ /***********************************************************************/\r
+ for (i = 0; i < 8; i++) PACKCHAR(*parm++, p, i);\r
+ for (i = 0; i < length; i++) PACKCHAR(*data++, p, i+8);\r
+\r
+ /***********************************************************************/\r
+ /* THE BREAKPOINT THAT SIGNALS THE HOST TO DO DATA TRANSFER */\r
+ /***********************************************************************/\r
+ __asm(" .global C$$IO$$");\r
+ __asm("C$$IO$$: nop");\r
+}\r
+\r
+/***************************************************************************/\r
+/* */\r
+/* READMSG() - Reads the data and parameters passed from the host. */\r
+/* */\r
+/***************************************************************************/\r
+void readmsg(register unsigned char *parm,\r
+ register char *data)\r
+{\r
+ volatile unsigned char *p = (volatile unsigned char *)(_CIOBUF_+1);\r
+ unsigned int i;\r
+ unsigned int length;\r
+\r
+ /***********************************************************************/\r
+ /* THE LENGTH IS READ AS A TARGET INT */\r
+ /***********************************************************************/\r
+ length = _CIOBUF_[0];\r
+\r
+ /***********************************************************************/\r
+ /* UNPACK THE PARAMETERS AND DATA */\r
+ /***********************************************************************/\r
+ for (i = 0; i < 8; i++) *parm++ = UNPACKCHAR(p, i);\r
+ if (data != NULL)\r
+ for (i = 0; i < length; i++) *data++ = UNPACKCHAR(p, i+8);\r
+}\r
+\r
+/****************************************************************************/\r
+/* HOSTWRITE() - Pass the write command and its arguments to the host. */\r
+/****************************************************************************/\r
+int HOSTwrite(int dev_fd, const char *buf, unsigned count)\r
+{\r
+ int result;\r
+\r
+ if (count > BUFSIZ) count = BUFSIZ;\r
+\r
+ LOADSHORT(parmbuf,dev_fd,0);\r
+ LOADSHORT(parmbuf,count,2);\r
+ writemsg(_DTWRITE,parmbuf,(char *)buf,count);\r
+ readmsg(parmbuf,NULL);\r
+\r
+ result = UNLOADSHORT(parmbuf,0);\r
+\r
+ return result;\r
+}\r
\r
#endif\r
\r
+#ifdef USE_TTY_TMS570_KEIL\r
+#include "GLCD.h"\r
#endif\r
\r
#define FILE_RAMLOG 3\r
\r
+/* Location MUST match NoICE configuration */\r
+#ifdef USE_TTY_NOICE\r
+static volatile char VUART_TX __attribute__ ((section (".noice_port")));\r
+static volatile char VUART_RX __attribute__ ((section (".noice_port")));\r
+volatile unsigned char START_VUART = 0;\r
+#endif\r
+\r
/*\r
* T32 stuff\r
*/\r
(void)g_TRBuffer[0];\r
#endif\r
\r
+#ifdef USE_TTY_NOICE\r
+ // Not tested at all\r
+ int retval;\r
+ while (VUART_RX != 0)\r
+ {\r
+ }\r
+\r
+ retval = VUART_RX;\r
+ VUART_RX = 0;\r
+#endif\r
+\r
/* Only support write for now, return 0 read */\r
return 0;\r
}\r
\r
int write( int fd, const void *_buf, size_t nbytes)\r
{\r
- char *buf = (char *)_buf;\r
//(void)fd; // Normally 0- ?, 1-stdout, 2-stderr,\r
// Added 3-ramlog,\r
\r
\r
if( fd <= STDERR_FILENO ) {\r
+#ifdef USE_TTY_NOICE\r
+ char *buf1 = (char *)_buf;\r
+ if (START_VUART)\r
+ {\r
+ for (int i = 0; i < nbytes; i++) {\r
+ char c = buf1[i];\r
+ if (c == '\n')\r
+ {\r
+ while (VUART_TX != 0)\r
+ {\r
+ }\r
+\r
+ VUART_TX = '\r';\r
+ }\r
+\r
+ while (VUART_TX != 0)\r
+ {\r
+ }\r
+\r
+ VUART_TX = c;\r
+ }\r
+ }\r
+#endif\r
+\r
#ifdef USE_TTY_WINIDEA\r
if (g_TConn)\r
{\r
+ char *buf = (char *)_buf;\r
unsigned char nCnt,nLen;\r
for(nCnt=0; nCnt<nbytes; nCnt++)\r
{\r
#endif\r
\r
#ifdef USE_TTY_T32\r
+ char *buf = (char *)_buf;\r
for (int i = 0; i < nbytes; i++) {\r
if (*(buf + i) == '\n') {\r
t32_writebyte ('\r');\r
#endif\r
\r
#ifdef USE_TTY_ARM_ITM\r
+ char *buf = (char *)_buf;\r
for (int i = 0; i < nbytes; i++) {\r
ITM_SendChar(*(buf + i));\r
}\r
#endif\r
\r
-#if defined(USE_RAMLOG)\r
+#ifdef USE_TTY_TCF_STREAMS\r
+ char *buf = (char *)_buf;\r
for (int i = 0; i < nbytes; i++) {\r
- ramlog_chr (*(buf + i));\r
+ TCF_TTY_SendChar(*(buf + i));\r
+ }\r
+#endif\r
+\r
+#ifdef USE_TTY_CODE_COMPOSER\r
+ HOSTwrite(fd, _buf, nbytes);\r
+#endif\r
+\r
+#ifdef USE_TTY_TMS570_KEIL\r
+ for (int i = 0; i < nbytes; i++) {\r
+ GLCD_PrintChar((_buf + i));\r
+ }\r
+#endif\r
+\r
+#if defined(USE_RAMLOG)\r
+ {\r
+ char *buf = (char *)_buf;\r
+ for (int i = 0; i < nbytes; i++) {\r
+ ramlog_chr (*(buf + i));\r
+ }\r
}\r
#endif\r
\r
#if defined(USE_RAMLOG)\r
/* RAMLOG support */\r
if(fd == FILE_RAMLOG) {\r
+ char *buf = (char *)_buf;\r
for (int i = 0; i < nbytes; i++) {\r
ramlog_chr (*(buf + i));\r
}\r
unsigned char *prev_heap_end;\r
\r
/* initialize */\r
- if( heap_end == 0 )\r
+ if( heap_end == 0 ){\r
heap_end = _heap;\r
-\r
- prev_heap_end = heap_end;\r
+ }\r
+ prev_heap_end = heap_end;\r
\r
if( heap_end + incr - _heap > HEAPSIZE ) {\r
/* heap overflow - announce on stderr */\r
}\r
#if defined(CFG_ARM)\r
void _exit( int status ) {\r
+#ifdef USE_TTY_CODE_COMPOSER\r
+ __asm(" .global C$$EXIT");\r
+ __asm("C$$EXIT: nop");\r
+#endif\r
while(1);\r
}\r
#endif\r
* snprintf(buf,) -> vsnprintf(buf,)\r
*\r
* IMPLEMENTATION NOTE:\r
- * If printing more than the limit, e.g. using vsnprintf() then\r
- * the emit function will only stop printing, but not interrupted\r
- * (The code will get more complicated that way)\r
+ * - If printing more than the limit, e.g. using vsnprintf() then\r
+ * the emit function will only stop printing, but not interrupted\r
+ * (The code will get more complicated that way)\r
+ * - ANSI-C and POSIX, streams and POSIX filenumbers.\r
+ * POSIX file-numbers exist in unistd.h and are only to be used by the porting\r
+ * newlib interface i.e. newlib_port.c.\r
+ * The filenumber is actually just a cast of the steampointer and save in the member\r
+ * _cookie in FILE.\r
+ *\r
*/\r
\r
#include <unistd.h>\r
\r
//#define HOST_TEST 1\r
\r
-#ifdef HOST_TEST\r
-#define _STDOUT stdout\r
-#define _STDIN stdin\r
-#define _STDERR stderr\r
-#else\r
-#define _STDOUT (FILE *)STDOUT_FILENO\r
-#define _STDINT STDIN_FILENO\r
-#define _STDERR (FILE *)STDERR_FILENO\r
-#endif\r
-\r
-\r
int arc_putchar(int fd, int c);\r
int print(FILE *file, char **buffer, size_t n, const char *format, va_list ap);\r
+static inline int emitChar( FILE *file, char **buf, char c, int *left );\r
+\r
+int fputs( const char *s, FILE *file ) {\r
+ int left = ~(size_t)0;\r
+ while(*s) {\r
+ emitChar(file,NULL,*s++,&left);\r
+ }\r
+ return 0;\r
+}\r
+\r
\r
int printf(const char *format, ...) {\r
va_list ap;\r
int rv;\r
\r
va_start(ap, format);\r
- rv = vfprintf(_STDOUT, format, ap);\r
+ rv = vfprintf(stdout, format, ap);\r
va_end(ap);\r
return rv;\r
}\r
}\r
\r
int vprintf(const char *format, va_list ap) {\r
- return vfprintf(_STDOUT, format, ap);\r
+ return vfprintf(stdout, format, ap);\r
}\r
\r
int vsprintf(char *buffer, const char *format, va_list ap) {\r
\r
int vfprintf(FILE *file, const char *format, va_list ap) {\r
int rv;\r
- /* Just print to _STDOUT */\r
+ /* Just print to stdout */\r
rv = print(file,NULL,~(size_t)0, format,ap);\r
return rv;\r
}\r
\r
+\r
int vsnprintf(char *buffer, size_t n, const char *format, va_list ap) {\r
int rv;\r
\r
}\r
\r
\r
+/*\r
+ * The integer only counterpart\r
+ */\r
+int iprintf(const char *format, ...) __attribute__ ((alias("printf")));\r
+int fiprintf(FILE *file, const char *format, ...) __attribute__ ((alias("fprintf")));\r
+int siprintf(char *buffer, const char *format, ...) __attribute__ ((alias("sprintf")));\r
+int sniprintf(char *buffer, size_t n, const char *format, ...) __attribute__ ((alias("snprintf")));\r
+int viprintf(const char *format, va_list ap) __attribute__ ((alias("vprintf")));\r
+int vsiprintf(char *buffer, const char *format, va_list ap) __attribute__ ((alias("vsprintf")));\r
+int vfiprintf(FILE *file, const char *format, va_list ap) __attribute__ ((alias("vfprintf")));\r
+\r
/**\r
*\r
* @param file The file to print to\r
--(*left);\r
if( buf == NULL ) {\r
#if HOST_TEST\r
- putc(c, _STDOUT);\r
- fflush(_STDOUT);\r
+ putc(c, stdout);\r
+ fflush(stdout);\r
#else\r
- arc_putchar((int)file, c);\r
+ arc_putchar((int)file->_cookie, c);\r
#endif\r
} else {\r
**buf = c;\r
#define FL_ALIGN_LEFT (1<<4)\r
#define FL_TYPE_SIGNED_INT (1<<5)\r
#define FL_TYPE_UNSIGNED_INT (1<<6)\r
-\r
+#define FL_TYPE_POINTER (1<<7)\r
\r
static void emitString( FILE *file, char **buffer, char *string, int width, int flags, int *left) {\r
char pad;\r
}\r
}\r
\r
-void emitInt( FILE *file, char **buffer, int base, int width, int flags, va_list ap, int *left )\r
+void emitInt( FILE *file, char **buffer, int val, int base, int width, int flags, int *left )\r
{\r
char lBuf[12]; // longest is base 10, 2^32\r
char *str = lBuf;\r
- int val;\r
\r
if( flags & FL_TYPE_SIGNED_INT ) {\r
- val = (int )va_arg( ap, int );\r
xtoa(val,str,base ,(val < 0));\r
} else {\r
- xtoa((unsigned)va_arg( ap, int ),str,base ,0);\r
+ xtoa((unsigned)val,str,base ,0);\r
}\r
\r
emitString(file,buffer,str,width,flags,left);\r
}\r
\r
-\r
-\r
#define PRINT_CHAR(_c) *buffer++= (_c);\r
\r
\r
}\r
\r
/* Find flags */\r
- switch (ch) {\r
- case '0':\r
+ if (ch == '0')\r
+ {\r
flags = FL_ZERO;\r
- break;\r
- case ' ':\r
+ }\r
+ else if (ch == ' ')\r
+ {\r
flags = FL_SPACE;\r
- break;\r
- case '-':\r
+ }\r
+ else if (ch == '-')\r
+ {\r
flags = FL_ALIGN_LEFT;\r
- break;\r
- default:\r
+ }\r
+ else\r
+ {\r
/* Not supported or no flag */\r
flags = FL_NONE;\r
format--;\r
- break;\r
}\r
\r
ch = *format++;\r
}\r
\r
/* Find type */\r
- switch (ch) {\r
- case 'c':\r
+ if (ch =='c')\r
+ {\r
emitChar(file,buffer,(char )va_arg( ap, int ),&left);\r
- break;\r
- case 'd':\r
+ }\r
+ else if (ch == 'd')\r
+ {\r
flags |= FL_TYPE_SIGNED_INT;\r
- emitInt(file,buffer,10,width,flags,ap,&left);\r
- break;\r
- case 'u':\r
+ emitInt(file,buffer,va_arg( ap, int ),10,width,flags,&left);\r
+ }\r
+ else if (ch == 'u')\r
+ {\r
flags |= FL_TYPE_UNSIGNED_INT;\r
- emitInt(file,buffer,10,width,flags,ap,&left);\r
- break;\r
- case 'x':\r
+ emitInt(file,buffer,va_arg( ap, int ),10,width,flags,&left);\r
+ }\r
+ else if (ch == 'x')\r
+ {\r
flags |= FL_TYPE_UNSIGNED_INT;\r
- emitInt(file,buffer,16,width,flags,ap,&left);\r
- break;\r
- case 's':\r
+ emitInt(file,buffer,va_arg( ap, int ),16,width,flags,&left);\r
+ }\r
+ else if (ch == 'p')\r
+ {\r
+ flags |= FL_TYPE_POINTER;\r
+ emitInt(file,buffer,va_arg( ap, int ),16,width,flags,&left);\r
+ }\r
+ else if (ch == 's')\r
+ {\r
str = (char *)va_arg( ap, int );\r
\r
if( str == NULL ) {\r
}\r
\r
emitString(file,buffer,str,width,flags,&left);\r
- break;\r
- default:\r
+ }\r
+ else\r
+ {\r
assert(0); // oops\r
- break;\r
}\r
-\r
} else {\r
flags = FL_NONE;\r
emitChar(file,buffer,ch,&left);\r
}\r
}\r
- va_end(ap);\r
+// va_end(ap); // Removed, TODO: Check the va_start/va_end handling (used in calling functions also).\r
if(buffer!=0) {\r
left = 0;\r
emitChar(file,buffer,'\0',&left);\r
return 0; // Wrong.. but for now.\r
}\r
\r
-#if defined(HOST_TEST)\r
+#if 0\r
int main(void) {\r
char *ptr = NULL;\r
char buff[30];\r
\r
printf("decimal: 00c000 = %06x \n", 0xc000);\r
\r
- fprintf(_STDOUT, "string: %s = foobar \n", "foobar");\r
+ fprintf(stdout, "string: %s = foobar \n", "foobar");\r
sprintf(buff, "string: %s = foobar \n", "foobar");\r
printf("%s",buff);\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "sleep.h"\r
+#include "Mcu.h"\r
+#include "Os.h"\r
+\r
+struct timeoutlist_t{\r
+ uint32_t timeout;\r
+ boolean active;\r
+ EventMaskType mask;\r
+};\r
+static struct timeoutlist_t timeoutlist[OS_TASK_CNT];\r
+\r
+static uint32_t ticks = 0;\r
+\r
+void SleepInit()\r
+{\r
+ uint32_t i;\r
+\r
+ for(i=0;i<OS_TASK_CNT;i++)\r
+ {\r
+ timeoutlist[i].active = FALSE;\r
+ }\r
+}\r
+\r
+void Sleep(uint32_t nofTicks, TaskType TaskID, EventMaskType Mask )\r
+{\r
+ uint32 pval = McuE_EnterCriticalSection();\r
+ if(nofTicks == 0){\r
+ nofTicks=1;\r
+ }\r
+ if(TaskID < OS_TASK_CNT){\r
+ timeoutlist[TaskID].timeout = ticks + nofTicks;\r
+ timeoutlist[TaskID].active = TRUE;\r
+ timeoutlist[TaskID].mask = Mask;\r
+ }else{\r
+ /* Error */\r
+ ErrorHook(E_OS_LIMIT);\r
+ }\r
+ McuE_ExitCriticalSection(pval);\r
+}\r
+\r
+\r
+void SleepTask(void)\r
+{\r
+ uint32_t i;\r
+ for(;;) {\r
+ // Alarms every tick\r
+ WaitEvent(EVENT_MASK_SLEEP_ALARM_TASK);\r
+ ClearEvent(EVENT_MASK_SLEEP_ALARM_TASK);\r
+\r
+ ticks++;\r
+\r
+ for(i=0;i<OS_TASK_CNT;i++)\r
+ {\r
+ if((timeoutlist[i].active == TRUE) && (timeoutlist[i].timeout == ticks))\r
+ {\r
+ timeoutlist[i].active = FALSE;\r
+ SetEvent(i,timeoutlist[i].mask);\r
+ }\r
+ }\r
+ }\r
+\r
+}\r
--- /dev/null
+/*\r
+ * tcf_cfg.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+#include "Tcf_Cfg.h"\r
+\r
+//Service includes\r
+#include "sys_monitor.h"\r
+#include "streams.h"\r
+\r
+const char locator_hello[] = "E\0Locator\0Hello\0[\"Locator\",\"SysMonitor\",\"AsciiStreams\",\"FileSystem\"]\0\x03\x01";\r
+\r
+const TCF_Service_Info tcfServiceCfgList[] = {\r
+ {"Locator", handle_LocatorCommand, handle_LocatorEvent},\r
+ {"FileSystem", handle_FileSystemCommand, handle_FileSystemEvent},\r
+ {"SysMonitor", handle_SysMonCommand, handle_SysMonEvent},\r
+ {"AsciiStreams", handle_StreamsCommand, handle_StreamsEvent},\r
+ {"NULL", NULL},\r
+};\r
--- /dev/null
+/*\r
+ * Tcf_Cfg.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef TCF_CFG_H_\r
+#define TCF_CFG_H_\r
+\r
+#include "tcf.h"\r
+\r
+typedef struct {\r
+ char name[16];\r
+ TCF_Service_CommandHandler commandHandler;\r
+ TCF_Service_EventHandler eventHandler;\r
+} TCF_Service_Info;\r
+\r
+extern const TCF_Service_Info tcfServiceCfgList[];\r
+\r
+extern const char locator_hello[];\r
+\r
+#endif /* TCF_CFG_H_ */\r
--- /dev/null
+/*\r
+ * streams.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#include "Std_Types.h"\r
+#include "streams.h"\r
+#include "tcf.h"\r
+#include <string.h>\r
+#include "internal.h"\r
+#include "xtoa.h"\r
+#include "cirq_buffer.h"\r
+\r
+const char Streams_PID[] = "\"PID\":";\r
+const char Streams_Read[] = "read";\r
+const char Streams_Write[] = "write";\r
+const char Streams_Subscribe[] = "subcribe";\r
+const char Streams_Unsubscribe[] = "unsubscribe";\r
+const char Streams_Connect[] = "connect";\r
+const char Streams_Disconnect[] = "disconnect";\r
+const char Streams_EndofStream[] = "eos";\r
+\r
+const char Streams_LostSize[] = "\"lost size\":";\r
+const char Streams_EOS[] = "\"EOS\":";\r
+const char Streams_true[] = "true";\r
+const char Streams_false[] = "false";\r
+\r
+typedef struct {\r
+ char* id;\r
+ char* size;\r
+ char* data;\r
+} TCF_Streams_Command;\r
+\r
+#define TCF_TTY_SIZE 800\r
+\r
+static boolean tty_initialized = FALSE;\r
+static CirqBufferType cirqBuf;\r
+char tty_buffer[TCF_TTY_SIZE] = "";\r
+\r
+void init_streams()\r
+{\r
+ cirqBuf = CirqBuffStatCreate(tty_buffer, TCF_TTY_SIZE, sizeof(char));\r
+ tty_initialized = TRUE;\r
+}\r
+\r
+uint8_t TCF_TTY_SendChar (uint8_t ch)\r
+{\r
+ int rv = 1;\r
+ if(tty_initialized == TRUE){\r
+ rv = CirqBuffPush(&cirqBuf,&ch);\r
+ }\r
+\r
+ return rv;\r
+}\r
+uint32_t TCF_TTY_ReadString(char *str, uint16_t max_len)\r
+{\r
+ char ch;\r
+ int rv;\r
+ int len = 0;\r
+ if(tty_initialized == TRUE){\r
+ do{\r
+ rv = CirqBuffPop(&cirqBuf,&ch);\r
+ if(rv==0){\r
+ len++;\r
+ *str++=ch;\r
+ if(ch == '\0'){\r
+ rv = 1;\r
+ }\r
+ }\r
+ }while((rv == 0) && (len < max_len));\r
+ }\r
+\r
+ return len;\r
+}\r
+\r
+\r
+uint16_t handle_StreamsEvent(TCF_Event* event, char* buf){\r
+ return 0;\r
+}\r
+\r
+static Std_ReturnType parse_read(char* msg, TCF_Streams_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->id = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->size = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+static Std_ReturnType parse_write(char* msg, TCF_Streams_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->id = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->size = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->data = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+static Std_ReturnType parse_id(char* msg, TCF_Streams_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->id = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+char tmp_stream[200] = "";\r
+uint16_t handle_StreamsCommand(TCF_Command* command, char* buf) {\r
+ TCF_Streams_Command streams_cmd;\r
+\r
+ /* Start building return message */\r
+ start_tcf_field(buf, (char *)TCF_S_R); /* Start */\r
+ append_tcf_field(buf, command->token); /* Token */\r
+\r
+ if (strcmp(command->commandName, Streams_Read) == 0) {\r
+ /* C \95 <token> \95 Streams \95 read \95 <string: stream ID> \95 <int: size> \95 */\r
+ /* R \95 <token> \95 <string: data> \95 <error report> \95 <int: lost size> \95 <boolean: EOS> */\r
+ if(parse_read(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+\r
+ /* Add data field */\r
+ mystrcat(buf, JSON_Stringify);\r
+ int len = TCF_TTY_ReadString(tmp_stream, 199);\r
+ if(len >= 200){\r
+ return 0;\r
+ }\r
+ tmp_stream[len] = '\0'; /* Terminate to be sure */\r
+ mystrcat(buf, tmp_stream);\r
+ mystrcat(buf, JSON_Stringify);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ //mystrcat(buf, Streams_LostSize);\r
+ ultoa(0,tmp_stream,10);\r
+ mystrcat(buf,tmp_stream);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ //mystrcat(buf, Streams_EOS);\r
+ mystrcat(buf, Streams_false);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+ } else if (strcmp(command->commandName, Streams_Write) == 0) {\r
+ /* C \95 <token> \95 Streams \95 write \95 <string: stream ID> \95 <int: size> \95 <string: data> \95 */\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_write(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+ } else if (strcmp(command->commandName, Streams_Subscribe) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }else if (strcmp(command->commandName, Streams_Unsubscribe) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }else if (strcmp(command->commandName, Streams_Connect) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }else if (strcmp(command->commandName, Streams_Disconnect) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }\r
+\r
+ convert_to_tcf_message(buf);\r
+ uint16_t len = message_length(buf, TCF_MAX_FIELD_LENGTH);\r
+\r
+ return len;\r
+}\r
--- /dev/null
+/*\r
+ * streams.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef STREAMS_H_\r
+#define STREAMS_H_\r
+\r
+#include "Std_Types.h"\r
+#include "tcf.h"\r
+\r
+uint8_t TCF_TTY_SendChar (uint8_t ch);\r
+void init_streams();\r
+\r
+uint16_t handle_StreamsCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_StreamsEvent(TCF_Event* event, char* buf);\r
+\r
+#endif /* STREAMS_H_ */\r
--- /dev/null
+/*\r
+ * sys_monitor.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#include "Std_Types.h"\r
+#include "sys_monitor.h"\r
+#include "tcf.h"\r
+#include <string.h>\r
+#include "internal.h"\r
+#include "xtoa.h"\r
+\r
+const char SysMon_PID[] = "\"PID\":";\r
+const char SysMon_Prio[] = "\"Priority\":";\r
+const char SysMon_Stackstart[] = "\"StackStart\":";\r
+const char SysMon_Stackend[] = "\"StackEnd\":";\r
+const char SysMon_Stackcurr[] = "\"StackCurr\":";\r
+const char SysMon_State[] = "\"State\":";\r
+\r
+static void AddState(char *buf, state_t state)\r
+{\r
+ /* "RSDZTW" where\r
+ R is running,\r
+ S is sleeping in an interruptible wait,\r
+ D is waiting in uninterruptible disk sleep,\r
+ Z is zombie,\r
+ T is traced or stopped (on a signal), and\r
+ W is paging */\r
+ switch(state)\r
+ {\r
+ case ST_READY:\r
+ mystrcat(buf,"\"D\"");\r
+ break;\r
+ case ST_WAITING:\r
+ mystrcat(buf,"\"S\"");\r
+ break;\r
+ case ST_SUSPENDED:\r
+ mystrcat(buf,"\"T\"");\r
+ break;\r
+ case ST_RUNNING:\r
+ mystrcat(buf,"\"R\"");\r
+ break;\r
+ case ST_NOT_STARTED:\r
+ mystrcat(buf,"\"T\"");\r
+ break;\r
+ }\r
+}\r
+\r
+uint16_t handle_SysMonEvent(TCF_Event* event, char* buf){\r
+ return 0;\r
+}\r
+\r
+\r
+uint16_t handle_SysMonCommand(TCF_Command* command, char* buf) {\r
+ OsPcbType *iterPcbPtr;\r
+\r
+ /* Start building return message */\r
+ start_tcf_field(buf, (char *)TCF_S_R); /* Start */\r
+ append_tcf_field(buf, command->token); /* Token */\r
+\r
+ if (strcmp(command->commandName, TCF_getChildren) == 0) {\r
+ boolean first = TRUE;\r
+\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add data field */\r
+ mystrcat(buf, JSON_ListStart);\r
+ TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {\r
+ if(iterPcbPtr->proc_type < 4)\r
+ {\r
+ if(first){\r
+ first = FALSE;\r
+ }else{\r
+ mystrcat(buf, JSON_Separator);\r
+ }\r
+ mystrcat(buf, JSON_Stringify);\r
+ mystrcat(buf, iterPcbPtr->name);\r
+ mystrcat(buf, JSON_Stringify);\r
+ }\r
+ }\r
+ mystrcat(buf, JSON_ListEnd);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ } else if (strcmp(command->commandName, TCF_getContext) == 0) {\r
+ char tmp[20] = "";\r
+\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add data field */\r
+ char *arg = command->arguments + 1; /* add 1 for " */\r
+ TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {\r
+ if(strncmp(arg, iterPcbPtr->name, strlen(command->arguments)-2) == 0)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ mystrcat(buf, JSON_ObjStart);\r
+ mystrcat(buf, TCF_ID);\r
+ mystrcat(buf, command->arguments);\r
+\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, TCF_File);\r
+ mystrcat(buf, command->arguments);\r
+\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_PID);\r
+ ultoa(iterPcbPtr->pid,tmp,10);\r
+ mystrcat(buf, tmp);\r
+\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Prio);\r
+ ultoa(iterPcbPtr->prio,tmp,10);\r
+ mystrcat(buf, tmp);\r
+\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Stackstart);\r
+ ultoa((uint32_t)iterPcbPtr->stack.top,tmp,10);\r
+ mystrcat(buf, tmp);\r
+\r
+/* mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Stackend);\r
+ ultoa((uint32_t)iterPcbPtr->stack.top + iterPcbPtr->stack.size,tmp,10);\r
+ mystrcat(buf, tmp);\r
+\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_Stackcurr);\r
+ ultoa((uint32_t)iterPcbPtr->stack.curr,tmp,10);\r
+ mystrcat(buf, tmp);\r
+*/\r
+ mystrcat(buf, JSON_Separator);\r
+ mystrcat(buf, SysMon_State);\r
+ AddState(buf,iterPcbPtr->state);\r
+\r
+ mystrcat(buf, JSON_ObjEnd);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }\r
+\r
+ convert_to_tcf_message(buf);\r
+ uint16_t len = message_length(buf, TCF_MAX_FIELD_LENGTH);\r
+\r
+ return len;\r
+}\r
--- /dev/null
+/*\r
+ * sys_monitor.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef SYSMONITOR_H_\r
+#define SYSMONITOR_H_\r
+\r
+#include "Std_Types.h"\r
+#include "tcf.h"\r
+\r
+uint16_t handle_SysMonCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_SysMonEvent(TCF_Event* event, char* buf);\r
+\r
+#endif /* SYSMONITOR_H_ */\r
--- /dev/null
+/*\r
+ * tcf.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#define USE_LDEBUG_PRINTF\r
+#include "debug.h"\r
+\r
+#include "Std_Types.h"\r
+#include <string.h>\r
+#ifdef USE_LWIP\r
+#include "lwip/tcp.h"\r
+#include "lwip/udp.h"\r
+#include "tcp_handler.h"\r
+#endif\r
+#include "tcf.h"\r
+#include "Tcf_Cfg.h"\r
+#include "xtoa.h"\r
+#include "streams.h"\r
+\r
+\r
+#define TCF_TCP_PORT 1534\r
+\r
+const char TCF_getChildren[] = "getChildren";\r
+const char TCF_getContext[] = "getContext";\r
+const char TCF_ID[] = "\"ID\":";\r
+const char TCF_File[] = "\"File\":";\r
+const char TCF_Service[] = "\"Service\":";\r
+const char TCF_Code[] = "\"Code\":";\r
+\r
+\r
+const char JSON_ObjStart[] = "{";\r
+const char JSON_ObjEnd[] = "}";\r
+const char JSON_null[] = "null";\r
+const char JSON_Separator[] = ",";\r
+\r
+const char JSON_Stringify[] = "\"";\r
+const char JSON_ListStart[] = "[";\r
+const char JSON_ListEnd[] = "]";\r
+\r
+struct tcf_tcp_state\r
+{\r
+ int num;\r
+};\r
+\r
+char *mystrcat(char *s1, const char *s2)\r
+{\r
+ char *s;\r
+\r
+ for(s = s1;*s;++s)\r
+ ;\r
+\r
+ while(*s2)\r
+ *s++ = *s2++;\r
+ *s = '\0';\r
+\r
+ return s1;\r
+}\r
+\r
+\r
+uint16_t message_length(const char* msg, uint16_t max_length) {\r
+ uint16_t i;\r
+ for (i = 0; i < max_length; ++i) {\r
+ if (msg[i] == '\x01') {\r
+ return i+1;\r
+ }\r
+ }\r
+ return max_length;\r
+}\r
+\r
+void start_tcf_field(char* start, char* field) {\r
+ strcpy(start, field);\r
+ mystrcat(start, TCF_S_EOFIELD_MARKER);\r
+}\r
+\r
+void append_tcf_field(char* start, char* field) {\r
+ mystrcat(start, field);\r
+ mystrcat(start, TCF_S_EOFIELD_MARKER);\r
+}\r
+\r
+void convert_to_tcf_message(char* start) {\r
+ mystrcat(start, TCF_S_EOM);\r
+ size_t length = strlen(start);\r
+ int i;\r
+ for (i = 0; i < length; ++i) {\r
+ if (start[i] == TCF_C_EOFIELD_MARKER) {\r
+ start[i] = TCF_C_EOFIELD;\r
+ }\r
+ }\r
+}\r
+\r
+char* get_next_tcf_field(char* chars, uint16_t maxlen) {\r
+ int i;\r
+ for(i = 0; i < maxlen; i++) {\r
+ if (chars[i] == TCF_FIELD_DELIMITER) {\r
+ return &chars[i+1];\r
+ }\r
+ }\r
+ return (char*) NULL;\r
+}\r
+\r
+char* get_next_tcf_msg(char* chars, uint16_t *len) {\r
+ int i;\r
+ for(i = 0; i < *len-1; i++) {\r
+ if (chars[i] == '\x03' && chars[i+1] == '\x01') {\r
+ *len -= (i + 1);\r
+ return &chars[i+2];\r
+ }\r
+ }\r
+ *len= 0;\r
+ return (char*) NULL;\r
+}\r
+\r
+static Std_ReturnType parse_command(char* msg, TCF_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->token = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->serviceName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->commandName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->arguments = curr;\r
+\r
+ command->args_len = len -((uint32_t)curr - (uint32_t)msg);\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType parse_event(char* msg, TCF_Event* event){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, TCF_MAX_FIELD_LENGTH);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ event->serviceName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, TCF_MAX_FIELD_LENGTH);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ event->eventName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, TCF_MAX_FIELD_LENGTH);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ event->eventData = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+uint16_t handle_LocatorCommand(TCF_Command* command, char* buf) {\r
+ return 0;\r
+}\r
+\r
+uint16_t handle_LocatorEvent(TCF_Event* event, char* buf) {\r
+ uint16_t len = 0;\r
+ if(strcmp(event->eventName, "Hello") == 0)\r
+ {\r
+ len = message_length(locator_hello, TCF_MAX_FIELD_LENGTH);\r
+ memcpy(buf,locator_hello,len);\r
+ }else if(strcmp(event->eventName, "peerHeartBeat") == 0){\r
+\r
+ }\r
+\r
+ return len;\r
+}\r
+\r
+uint16_t handle_FileSystemCommand(TCF_Command* command, char* buf) {\r
+ char tmp[20] = "";\r
+\r
+ /* Start building return message */\r
+ start_tcf_field(buf, (char *)TCF_S_R); /* Start */\r
+ append_tcf_field(buf, command->token); /* Token */\r
+\r
+ /* Add error field */\r
+ mystrcat(buf, JSON_ObjStart);\r
+\r
+ mystrcat(buf, TCF_Code);\r
+ ultoa(TCF_UNSUPPORTED,tmp,10);\r
+ mystrcat(buf, tmp);\r
+\r
+ mystrcat(buf, JSON_ObjEnd);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add data field */\r
+ mystrcat(buf, JSON_null);\r
+ mystrcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ convert_to_tcf_message(buf);\r
+ uint16_t len = message_length(buf, TCF_MAX_FIELD_LENGTH);\r
+\r
+ return len;\r
+}\r
+\r
+uint16_t handle_FileSystemEvent(TCF_Event* event, char* buf) {\r
+ return 0;\r
+}\r
+\r
+/* Not reentrant so buffers can be static */\r
+char outbuf[TCF_MAX_FIELD_LENGTH] = "";\r
+\r
+static void handle_event(char *buf, uint16_t len)\r
+{\r
+ char *msg = (char *)buf;\r
+ uint8 index;\r
+ uint16_t outlen = 0;\r
+ TCF_Event event;\r
+\r
+ if (parse_event(msg, &event) == E_OK) {\r
+ /* Find and call the requested agent */\r
+ index = 0;\r
+ while(tcfServiceCfgList[index].eventHandler != NULL){\r
+ if(strcmp(event.serviceName, tcfServiceCfgList[index].name) == 0){\r
+ outlen = tcfServiceCfgList[index].eventHandler(&event, outbuf);\r
+ break;\r
+ }\r
+ index++;\r
+ }\r
+ }\r
+\r
+ if(outlen > 0){\r
+#ifdef USE_LWIP\r
+ TcpSendData(outbuf, outlen);\r
+#endif\r
+ }\r
+}\r
+\r
+static void handle_command(char *buf, uint16_t len)\r
+{\r
+ char *msg = (char *)buf;\r
+ uint8 index;\r
+ uint16_t outlen = 0;\r
+ TCF_Command command;\r
+\r
+ if (parse_command(msg, &command, len) == E_OK) {\r
+ //LDEBUG_PRINTF("C %s\n\r", command.token);\r
+ /* Find and call the requested agent */\r
+ index = 0;\r
+ while(tcfServiceCfgList[index].commandHandler != NULL){\r
+ if(strcmp(command.serviceName, tcfServiceCfgList[index].name) == 0){\r
+ outlen = tcfServiceCfgList[index].commandHandler(&command, outbuf);\r
+ break;\r
+ }\r
+ index++;\r
+ }\r
+\r
+ if(outlen > 0){\r
+#ifdef USE_LWIP\r
+ //LDEBUG_PRINTF("R %s\n\r", command.token);\r
+ TcpSendData(outbuf, outlen);\r
+#endif\r
+ }else{\r
+ LDEBUG_PRINTF("TCF: len=0:%s\n\r", command.token);\r
+ }\r
+ }else{\r
+ LDEBUG_PRINTF("TCF: Parse failed:%s\n\r", command.token);\r
+ }\r
+}\r
+\r
+static void handle_incoming(const void* buf, uint16_t len) {\r
+ char *msg = (char *)buf;\r
+ if(len > 0){\r
+ do{\r
+ if ((msg[0] == 'C') && (msg[1] == '\0')) {\r
+ handle_command(msg, len);\r
+ } else if ((msg[0] == 'E') && (msg[1] == '\0')) {\r
+ handle_event(msg, len);\r
+ }else{\r
+ len=0;\r
+ }\r
+\r
+ /* Check if more than one message in buffer */\r
+ if(len > 0){\r
+ msg = get_next_tcf_msg(msg, &len);\r
+ }\r
+ }while((msg != NULL) && (len > 0));\r
+ }\r
+}\r
+\r
+void InitTcf(void){\r
+#ifdef USE_LWIP\r
+ CreateTcpSocket(TCF_TCP_PORT, handle_incoming);\r
+#endif\r
+ init_streams();\r
+}\r
--- /dev/null
+/*\r
+ * tcf.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef TCF_H_\r
+#define TCF_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define TCF_C_EOFIELD '\x00'\r
+#define TCF_C_EOFIELD_MARKER '\x04'\r
+\r
+#define TCF_S_EOFIELD "\x00"\r
+#define TCF_S_EOFIELD_MARKER "\x04"\r
+#define TCF_S_R "R"\r
+#define TCF_S_EOM "\x03\x01"\r
+\r
+#define TCF_FIELD_DELIMITER ('\x00')\r
+#define TCF_MAX_FIELD_LENGTH (1400)\r
+\r
+extern const char TCF_getChildren[];\r
+extern const char TCF_getContext[];\r
+extern const char TCF_ID[];\r
+extern const char TCF_File[];\r
+extern const char TCF_Service[];\r
+extern const char TCF_Code[];\r
+\r
+extern const char JSON_ObjStart[];\r
+extern const char JSON_ObjEnd[];\r
+extern const char JSON_null[];\r
+extern const char JSON_Separator[];\r
+\r
+extern const char JSON_Stringify[];\r
+extern const char JSON_ListStart[];\r
+extern const char JSON_ListEnd[];\r
+\r
+/* Standard error codes: */\r
+\r
+typedef enum{\r
+ TCF_OTHER = 1,\r
+ TCF_JSON_SYNTAX = 2,\r
+ TCF_PROTOCOL = 3,\r
+ TCF_BUFFER_OVERFLOW = 4,\r
+ TCF_CHANNEL_CLOSED = 5,\r
+ TCF_COMMAND_CANCELLED = 6,\r
+ TCF_UNKNOWN_PEER = 7,\r
+ TCF_BASE64 = 8,\r
+ TCF_EOF = 9,\r
+ TCF_ALREADY_STOPPED = 10,\r
+ TCF_ALREADY_EXITED = 11,\r
+ TCF_ALREADY_RUNNING = 12,\r
+ TCF_ALREADY_ATTACHED = 13,\r
+ TCF_IS_RUNNING = 14,\r
+ TCF_INV_DATA_SIZE = 15,\r
+ TCF_INV_CONTEXT = 16,\r
+ TCF_INV_ADDRESS = 17,\r
+ TCF_INV_EXPRESSION = 18,\r
+ TCF_INV_FORMAT = 19,\r
+ TCF_INV_NUMBER = 20,\r
+ TCF_INV_DWARF = 21,\r
+ TCF_SYM_NOT_FOUND = 22,\r
+ TCF_UNSUPPORTED = 23,\r
+ TCF_INV_DATA_TYPE = 24,\r
+ TCF_INV_COMMAND = 25,\r
+} TCF_ErrorCode_t;\r
+\r
+\r
+typedef struct {\r
+ char* serviceName;\r
+ char* eventName;\r
+ char* eventData;\r
+} TCF_Event;\r
+\r
+typedef struct {\r
+ char* token;\r
+ char* serviceName;\r
+ char* commandName;\r
+ char* arguments;\r
+ uint16_t args_len;\r
+} TCF_Command;\r
+\r
+typedef struct {\r
+ char* token;\r
+ char* error;\r
+ char* data;\r
+} TCF_Result;\r
+\r
+typedef uint16_t (*TCF_Service_CommandHandler)(TCF_Command* command, char* buf);\r
+typedef uint16_t (*TCF_Service_EventHandler)(TCF_Event* command, char* buf);\r
+\r
+void InitTcf(void);\r
+uint16_t message_length(const char* msg, uint16_t max_length);\r
+char* get_next_tcf_field(char* chars, uint16_t maxlen);\r
+void start_tcf_field(char* start, char* field);\r
+void append_tcf_field(char* start, char* field);\r
+void convert_to_tcf_message(char* start);\r
+void tcf_compile_result(TCF_Result* result, char* buffer);\r
+\r
+/* Locator and Filesystem handlers are in tcf.c file. To be moved */\r
+uint16_t handle_LocatorCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_LocatorEvent(TCF_Event* event, char* buf);\r
+uint16_t handle_FileSystemCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_FileSystemEvent(TCF_Event* event, char* buf);\r
+\r
+char *mystrcat(char *s1, const char *s2);\r
+\r
+#endif /* TCF_H_ */\r
\r
#include "Can.h"\r
#include "CanIf_Cbk.h"\r
-#include "string.h"\r
+#include <string.h>\r
\r
-// Added by Mattias 2008-11-18\r
#include "debug.h"\r
#include "PduR.h"\r
\r
#include "CanTp_Cbk.h"\r
#endif\r
\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+\r
#if 0\r
// TODO: Include upper layer functions, See CANIF208 and CANIF233\r
#include "PduR_CanIf.h"\r
Det_ReportError(MODULE_ID_CANIF, 0, _api, _err); \\r
return; \\r
}\r
-#undef DET_REPORTERROR\r
#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
\r
#else\r
CanIf_ChannelPrivateType channelData[CANIF_CHANNEL_CNT];\r
} CanIf_GlobalType;\r
\r
+void CanIf_PreInit_InitController(uint8 Controller, uint8 ConfigurationIndex);\r
+\r
static CanIf_Arc_ChannelIdType CanIf_Arc_FindHrhChannel( Can_Arc_HRHType hrh )\r
{\r
const CanIf_InitHohConfigType *hohConfig;\r
do\r
{\r
hrhConfig++;\r
- if (hrhConfig->CanIfHrhIdSymRef == hrh)\r
+ if (hrhConfig->CanIfHrhIdSymRef == hrh){\r
return hrhConfig->CanIfCanControllerHrhIdRef;\r
+ }\r
} while(!hrhConfig->CanIf_Arc_EOL);\r
} while(!hohConfig->CanIf_Arc_EOL);\r
\r
\r
CanIf_ConfigPtr = ConfigPtr;\r
\r
- for (uint16 i = 0; i < CANIF_CHANNEL_CNT; i++)\r
+ for (uint8 i = 0; i < CANIF_CHANNEL_CNT; i++)\r
{\r
CanIf_Global.channelData[i].ControllerMode = CANIF_CS_STOPPED;\r
CanIf_Global.channelData[i].PduMode = CANIF_GET_OFFLINE;\r
+ CanIf_PreInit_InitController(i, CanIf_ConfigPtr->Arc_ChannelDefaultConfIndex[i]);\r
}\r
\r
- // NOTE!\r
- // Do NOT initialise the Can Drivers and Tranceivers, see CANIF085\r
\r
CanIf_Global.initRun = TRUE;\r
}\r
/*\r
* Controller :: CanIf_Arc_ChannelIdType (CanIf-specific id to abstract from Can driver/controllers)\r
* ConfigurationIndex :: CanIf_Arc_ConfigurationIndexType\r
- * /tojo\r
*/\r
void CanIf_InitController(uint8 Controller, uint8 ConfigurationIndex)\r
{\r
// We call this a CanIf channel. Hopefully makes it easier to follow.\r
CanIf_Arc_ChannelIdType channel = Controller;\r
+ CanIf_ControllerModeType mode;\r
\r
VALIDATE_NO_RV(CanIf_Global.initRun, CANIF_INIT_CONTROLLER_ID, CANIF_E_UNINIT );\r
VALIDATE_NO_RV(channel < CANIF_CHANNEL_CNT, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);\r
VALIDATE_NO_RV(ConfigurationIndex < CANIF_CHANNEL_CONFIGURATION_CNT, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_POINTER);\r
\r
-#if (CANIF_DEV_ERROR_DETECT == STD_ON)\r
- CanIf_ControllerModeType mode;\r
-\r
- if (CanIf_GetControllerMode(channel, &mode) == E_OK)\r
- {\r
- VALIDATE_NO_RV((mode != CANIF_CS_UNINIT), CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE );\r
- }\r
- else\r
- {\r
- VALIDATE_NO_RV(FALSE, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE);\r
- }\r
-#endif\r
-\r
if (CanIf_GetControllerMode(channel, &mode) == E_OK)\r
{\r
if (mode == CANIF_CS_STARTED)\r
else if (mode != CANIF_CS_STOPPED)\r
{\r
VALIDATE_NO_RV(FALSE, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE); // CANIF092\r
- }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ VALIDATE_NO_RV(FALSE, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER_MODE);\r
}\r
\r
// CANIF293: ..Subsequently the CAN Interface calls the corresponding\r
CanIf_SetControllerMode(channel, CANIF_CS_STOPPED);\r
}\r
\r
+void CanIf_PreInit_InitController(uint8 Controller, uint8 ConfigurationIndex){\r
+ // We call this a CanIf channel. Hopefully makes it easier to follow.\r
+ CanIf_Arc_ChannelIdType channel = Controller;\r
+\r
+ VALIDATE_NO_RV(channel < CANIF_CHANNEL_CNT, CANIF_INIT_ID, CANIF_E_PARAM_CONTROLLER);\r
+ VALIDATE_NO_RV(ConfigurationIndex < CANIF_CHANNEL_CONFIGURATION_CNT, CANIF_INIT_ID, CANIF_E_PARAM_POINTER);\r
+\r
+\r
+ const CanControllerIdType canControllerId = ARC_GET_CHANNEL_CONTROLLER(channel);\r
+ // Validate that the configuration at the index match the right channel\r
+ VALIDATE_NO_RV(CanIf_ConfigPtr->ControllerConfig[ConfigurationIndex].CanIfControllerIdRef == channel, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);\r
+ const Can_ControllerConfigType *canConfig = CanIf_ConfigPtr->ControllerConfig[ConfigurationIndex].CanIfInitControllerRef;\r
+ // Validate that the CanIfControllerConfig points to configuration for the right Can Controller\r
+ VALIDATE_NO_RV(canConfig->CanControllerId == canControllerId, CANIF_INIT_CONTROLLER_ID, CANIF_E_PARAM_CONTROLLER);\r
+\r
+ Can_InitController(canControllerId, canConfig);\r
+}\r
+\r
//-------------------------------------------------------------------\r
\r
Std_ReturnType CanIf_SetControllerMode(uint8 Controller,\r
switch (oldMode)\r
{\r
case CANIF_CS_SLEEP:\r
- if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK)\r
+ if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STOPPED;\r
break;\r
default:\r
}\r
\r
CanIf_SetPduMode(channel, CANIF_SET_ONLINE);\r
- if (Can_SetControllerMode(canControllerId, CAN_T_START) == CAN_NOT_OK)\r
+ if (Can_SetControllerMode(canControllerId, CAN_T_START) == CAN_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STARTED;\r
}\r
break;\r
{\r
switch (oldMode) {\r
case CANIF_CS_STARTED:\r
- if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK)\r
+ if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STOPPED;\r
break;\r
default:\r
break;\r
}\r
\r
- if (Can_SetControllerMode(canControllerId, CAN_T_SLEEP) == CAN_NOT_OK)\r
+ if (Can_SetControllerMode(canControllerId, CAN_T_SLEEP) == CAN_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_SLEEP;\r
}\r
\r
switch (oldMode)\r
{\r
case CANIF_CS_SLEEP:\r
- if (Can_SetControllerMode(canControllerId, CAN_T_WAKEUP) == CAN_NOT_OK)\r
+ if (Can_SetControllerMode(canControllerId, CAN_T_WAKEUP) == CAN_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
break;\r
default:\r
// Just fall through for other cases\r
}\r
\r
CanIf_SetPduMode(channel, CANIF_SET_OFFLINE);\r
- if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK)\r
+ if (Can_SetControllerMode(canControllerId, CAN_T_STOP) == CAN_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
CanIf_Global.channelData[channel].ControllerMode = CANIF_CS_STOPPED;\r
+ break;\r
}\r
\r
case CANIF_CS_UNINIT:\r
} else {\r
return &CanIf_ConfigPtr->InitConfig->CanIfTxPduConfigPtr[id];\r
}\r
-/*\r
- for (uint16 i = 0; i < CanIf_ConfigPtr->InitConfig->CanIfNumberOfCanTXPduIds; i++)\r
- {\r
- if (entry->CanIfTxPduId == id)\r
- {\r
- return entry;\r
- }\r
- entry++;\r
}\r
\r
- return 0;\r
- */\r
-}\r
-\r
//-------------------------------------------------------------------\r
\r
Std_ReturnType CanIf_Transmit(PduIdType CanTxPduId,\r
CanIf_Arc_ChannelIdType channel = txEntry->CanIfCanTxPduHthRef->CanIfCanControllerIdRef;\r
\r
// Get and verify the controller mode\r
- if (CanIf_GetControllerMode(channel, &csMode) == E_NOT_OK)\r
+ if (CanIf_GetControllerMode(channel, &csMode) == E_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
\r
- if (csMode != CANIF_CS_STARTED) // CANIF_161\r
+ if (csMode != CANIF_CS_STARTED){ // CANIF_161\r
return E_NOT_OK;\r
+ }\r
\r
// Get and verify the PDU channel mode control\r
- if (CanIf_GetPduMode(channel, &pduMode) == E_NOT_OK)\r
+ if (CanIf_GetPduMode(channel, &pduMode) == E_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
\r
- if ((pduMode != CANIF_GET_TX_ONLINE) && (pduMode != CANIF_GET_ONLINE))\r
+ if ((pduMode != CANIF_GET_TX_ONLINE) && (pduMode != CANIF_GET_ONLINE)){\r
return E_NOT_OK;\r
+ }\r
\r
canPdu.id = txEntry->CanIfCanTxPduIdCanId;\r
\r
\r
Can_ReturnType rVal = Can_Write(txEntry->CanIfCanTxPduHthRef->CanIfHthIdSymRef, &canPdu);\r
\r
- if (rVal == CAN_NOT_OK)\r
+ if (rVal == CAN_NOT_OK){\r
return E_NOT_OK;\r
+ }\r
\r
if (rVal == CAN_BUSY) // CANIF 082, CANIF 161\r
{\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;\r
break;\r
case CANIF_SET_RX_OFFLINE:\r
- if (oldMode == CANIF_GET_RX_ONLINE)\r
+ if (oldMode == CANIF_GET_RX_ONLINE){\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;\r
- else if (oldMode == CANIF_GET_ONLINE)\r
+ } else if (oldMode == CANIF_GET_ONLINE){\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_TX_ONLINE;\r
- else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)\r
+ } else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE){\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE;\r
+ }\r
\r
// Other oldmodes don't care\r
break;\r
case CANIF_SET_RX_ONLINE:\r
- if (oldMode == CANIF_GET_OFFLINE)\r
+ if (oldMode == CANIF_GET_OFFLINE){\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_RX_ONLINE;\r
- else if (oldMode == CANIF_GET_TX_ONLINE)\r
+ } else if (oldMode == CANIF_GET_TX_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_ONLINE;\r
- else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)\r
+ } else if (oldMode == CANIF_GET_OFFLINE_ACTIVE){\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;\r
+ }\r
\r
// Other oldmodes don't care\r
break;\r
case CANIF_SET_TX_OFFLINE:\r
- if (oldMode == CANIF_GET_TX_ONLINE)\r
+ if (oldMode == CANIF_GET_TX_ONLINE){\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;\r
- else if (oldMode == CANIF_GET_ONLINE)\r
+ } else if (oldMode == CANIF_GET_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_RX_ONLINE;\r
- else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)\r
+ } else if (oldMode == CANIF_GET_OFFLINE_ACTIVE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE;\r
- else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)\r
+ } else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_RX_ONLINE;\r
+ }\r
\r
// Other oldmodes don't care\r
break;\r
case CANIF_SET_TX_ONLINE:\r
- if (oldMode == CANIF_GET_OFFLINE)\r
+ if (oldMode == CANIF_GET_OFFLINE){\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_TX_ONLINE;\r
- else if (oldMode == CANIF_GET_RX_ONLINE)\r
+ } else if (oldMode == CANIF_GET_RX_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_ONLINE;\r
- else if (oldMode == CANIF_GET_OFFLINE_ACTIVE)\r
+ } else if (oldMode == CANIF_GET_OFFLINE_ACTIVE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_TX_ONLINE;\r
- else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE)\r
+ } else if (oldMode == CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_ONLINE;\r
+ }\r
\r
// Other oldmodes don't care\r
break;\r
break;\r
\r
case CANIF_SET_TX_OFFLINE_ACTIVE:\r
- if (oldMode == CANIF_GET_OFFLINE)\r
+ if (oldMode == CANIF_GET_OFFLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE;\r
- else if (oldMode == CANIF_GET_RX_ONLINE)\r
+ } else if (oldMode == CANIF_GET_RX_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;\r
- else if (oldMode == CANIF_GET_TX_ONLINE)\r
+ } else if (oldMode == CANIF_GET_TX_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE;\r
- else if (oldMode == CANIF_GET_ONLINE)\r
+ } else if (oldMode == CANIF_GET_ONLINE) {\r
CanIf_Global.channelData[channel].PduMode = CANIF_GET_OFFLINE_ACTIVE_RX_ONLINE;\r
+ }\r
\r
// Other oldmodes don't care\r
break;\r
}\r
\r
// Check that this is an extended or standard id\r
- if (((CanId & 0x80000000) && (txEntry->CanIfTxPduIdCanIdType == ARC_CAN_ID_TYPE_29)) ||\r
- (((CanId & 0x80000000) == 0) && (txEntry->CanIfTxPduIdCanIdType == ARC_CAN_ID_TYPE_11)))\r
+ if (((CanId & U0x80000000) && (txEntry->CanIfTxPduIdCanIdType == ARC_CAN_ID_TYPE_29)) ||\r
+ (((CanId & U0x80000000) == 0) && (txEntry->CanIfTxPduIdCanIdType == ARC_CAN_ID_TYPE_11)))\r
{\r
// Update the CanID\r
//txEntry->CanIfCanTxPduIdCanId = CanId; // TODO How do we fix this from a const pointer\r
const CanIf_TxPduConfigType* entry =\r
&CanIf_ConfigPtr->InitConfig->CanIfTxPduConfigPtr[canTxPduId];\r
\r
- /* Find the CAN id in the TxPduList */\r
- /*\r
- for (uint16 i = 0; i < CanIf_ConfigPtr->InitConfig->CanIfNumberOfCanTXPduIds; i++)\r
- {\r
- if (entry->CanIfTxPduId == canTxPduId)\r
- {\r
- */\r
if (entry->CanIfUserTxConfirmation != NULL)\r
{\r
CanIf_ChannelGetModeType mode;\r
}\r
}\r
return;\r
- /*\r
- }\r
-\r
- entry++;\r
- }\r
- */\r
- // Did not find the PDU, something is wrong\r
-\r
}\r
\r
void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc,\r
\r
if (CanIf_GetPduMode(channel, &mode) == E_OK)\r
{\r
- if (mode == CANIF_GET_OFFLINE || mode == CANIF_GET_TX_ONLINE ||\r
- mode == CANIF_GET_OFFLINE_ACTIVE)\r
+ if ( (mode == CANIF_GET_OFFLINE) || (mode == CANIF_GET_TX_ONLINE) ||\r
+ (mode == CANIF_GET_OFFLINE_ACTIVE) )\r
{\r
// Receiver path is disabled so just drop it\r
return;\r
else\r
{\r
entry++;\r
- continue; // Not a supported filter type, so just drop the frame\r
+ continue; // Go to next entry
}\r
}\r
else\r
break;\r
\r
case CANIF_USER_TYPE_CAN_NM:\r
+#if defined(USE_CANNM)\r
+ CanNm_RxIndication(entry->CanIfCanRxPduId,CanSduPtr);\r
+ return;\r
+#endif\r
+ break;\r
+\r
case CANIF_USER_TYPE_CAN_PDUR:\r
// Send Can frame to PDU router\r
+#if defined(USE_PDUR)\r
PduR_CanIfRxIndication(entry->CanIfCanRxPduId,CanSduPtr);\r
return;\r
+#endif\r
break;\r
\r
case CANIF_USER_TYPE_CAN_TP:\r
// Send Can frame to CAN TP\r
#if defined(USE_CANTP)\r
{\r
- PduInfoType CanTpRxPdu;\r
- CanTpRxPdu.SduLength = CanDlc;\r
- CanTpRxPdu.SduDataPtr = (uint8 *)CanSduPtr;\r
- CanTp_RxIndication(entry->CanIfCanRxPduId, &CanTpRxPdu); /** @req CANTP019 */\r
+ PduInfoType CanTpRxPdu;\r
+ CanTpRxPdu.SduLength = CanDlc;\r
+ CanTpRxPdu.SduDataPtr = (uint8 *)CanSduPtr;\r
+ CanTp_RxIndication(entry->CanIfCanRxPduId, &CanTpRxPdu);\r
}\r
return;\r
#endif\r
\r
void CanIf_SetWakeupEvent(uint8 Controller)\r
{\r
+#if ( CANIF_DEV_ERROR_DETECT == STD_ON )\r
// We call this a CanIf channel. Hopefully makes it easier to follow.\r
CanIf_Arc_ChannelIdType channel = Controller;\r
+#endif\r
\r
VALIDATE_NO_RV(FALSE, CANIF_SETWAKEUPEVENT_ID, CANIF_E_NOK_NOSUPPORT);\r
VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_SETWAKEUPEVENT_ID, CANIF_E_UNINIT );\r
\r
void CanIf_Arc_Error(uint8 Controller, Can_Arc_ErrorType Error)\r
{\r
+#if ( CANIF_DEV_ERROR_DETECT == STD_ON )\r
// We call this a CanIf channel. Hopefully makes it easier to follow.\r
CanIf_Arc_ChannelIdType channel = Controller;\r
+#endif\r
\r
VALIDATE_NO_RV( CanIf_Global.initRun, CANIF_ARCERROR_ID, CANIF_E_UNINIT );\r
VALIDATE_NO_RV( channel < CANIF_CHANNEL_CNT, CANIF_ARCERROR_ID, CANIF_E_PARAM_CONTROLLER );\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+//lint -emacro(904,CANNM_VALIDATE_INIT,CANNM_VALIDATE_CHANNEL,CANNM_VALIDATE_NOTNULL) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
+\r
+\r
+/* Globally fulfilled requirements */\r
+/** @req CANNM081 */\r
+/** @req CANNM044 */\r
+/** @req CANNM050 */\r
+/** @req CANNM088 */\r
+/** @req CANNM089 */\r
+/** @req CANNM090 */\r
+/** @req CANNM093 */\r
+/** @req CANNM206 */\r
+/** @req CANNM125 */\r
+/** @req CANNM140 */\r
+/** @req CANNM142 */\r
+/** @req CANNM145 */\r
+/** @req CANNM146 */\r
+/** @req CANNM039 */\r
+/** @req CANNM001.mandatory */\r
+/** @req CANNM158 */\r
+/** @req CANNM161 */\r
+/** @req CANNM162 */\r
+/** @req CANNM086 */\r
+/** @req CANNM019 */\r
+/** @req CANNM189 */\r
+/** @req CANNM190 */\r
+/** @req CANNM191 */\r
+/** @req CANNM016 */\r
+/** @req CANNM195 */\r
+/** @req CANNM197.toolchain */\r
+/** @req CANNM198.toolchain */\r
+/** @req CANNM026 */\r
+/** @req CANNM201 */\r
+\r
+#include "ComStack_Types.h" /** @req CANNM082 */\r
+#include "CanNm.h" /** @req CANNM082 */\r
+#include "CanNm_Internal.h"\r
+#include "Nm_Cbk.h" /** @req CANNM082 */\r
+#include "NmStack_Types.h" /** @req CANNM082 */\r
+//#include SchM_CanNm.h //Not implemented. (CANNM082)\r
+#include "MemMap.h" /** @req CANNM082 */\r
+\r
+/** @req CANNM083 */\r
+#include "CanIf.h"\r
+#include "Nm.h"\r
+\r
+#include <string.h>\r
+\r
+#if (CANNM_DEV_ERROR_DETECT == STD_ON)\r
+#include "Det.h" /** @req CANNM082 */\r
+#endif\r
+#if defined(USE_DEM)\r
+#include "Dem.h" /** @req CANNM082 */\r
+#endif\r
+\r
+\r
+static const CanNm_ConfigType* CanNm_ConfigPtr;\r
+\r
+//lint -save -e785 //PC-Lint exception: Too few initializers for aggregate...\r
+CanNm_InternalType CanNm_Internal = {\r
+ .InitStatus = CANNM_UNINIT,\r
+};\r
+//lint -restore\r
+\r
+/** Initialize the complete CanNm module, i.e. all channels which are activated */\r
+/** @req CANNM041 */\r
+void CanNm_Init( const CanNm_ConfigType * const cannmConfigPtr ){\r
+ CANNM_VALIDATE_NOTNULL(cannmConfigPtr, CANNM_SERVICEID_INIT);\r
+\r
+ CanNm_ConfigPtr = cannmConfigPtr; /**< @req CANNM060 */\r
+\r
+ uint8 channel;\r
+ for (channel = 0; channel < CANNM_CHANNEL_COUNT; channel++) {\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[channel];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[channel];\r
+ if (ChannelConf->Active) { /**< @req CANNM204 */\r
+ ChannelInternal->Mode = NM_MODE_BUS_SLEEP; /**< @req CANNM144 */\r
+ ChannelInternal->State = NM_STATE_BUS_SLEEP; /**< @req CANNM141 */\r
+ ChannelInternal->Requested = FALSE; /**< @req CANNM143 */\r
+\r
+ /** @req CANNM085 */\r
+ memset(ChannelInternal->TxMessageSdu, 0x00, 8);\r
+ memset(ChannelInternal->RxMessageSdu, 0x00, 8);\r
+\r
+ /** @req CANNM025 */\r
+ uint8* destUserData = CanNm_Internal_GetUserDataPtr(ChannelConf, ChannelInternal->TxMessageSdu);\r
+ uint8 userDataLength = CanNm_Internal_GetUserDataLength(ChannelConf);\r
+ memset(destUserData, 0xFF, userDataLength);\r
+\r
+#if (CANNM_NODE_ID_ENABLED == STD_ON)\r
+ /** @req CANNM013 */\r
+ if (ChannelConf->NidPosition != CANNM_PDU_OFF) {\r
+ ChannelInternal->TxMessageSdu[ChannelConf->NidPosition] = ChannelConf->NodeId;\r
+ }\r
+#endif\r
+ } else {\r
+ ChannelInternal->State = NM_STATE_UNINIT;\r
+ }\r
+ }\r
+\r
+ CanNm_Internal.InitStatus = CANNM_INIT;\r
+\r
+ /** @req CANNM061 */\r
+ /** @req CANNM033 */\r
+}\r
+\r
+/** Passive startup of the AUTOSAR CAN NM. It triggers the transition from Bus-\r
+ * Sleep Mode to the Network Mode in Repeat Message State.\r
+ * This service has no effect if the current state is not equal to Bus-Sleep Mode. In\r
+ * that case NM_E_NOT_EXECUTED is returned. */\r
+Nm_ReturnType CanNm_PassiveStartUp( const NetworkHandleType nmChannelHandle ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_PASSIVESTARTUP, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_PASSIVESTARTUP, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+ Nm_ReturnType status = NM_E_OK;\r
+\r
+ if (ChannelInternal->Mode == NM_MODE_BUS_SLEEP) {\r
+ CanNm_Internal_BusSleep_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM128 @req CANNM095.3 */\r
+ status = NM_E_OK;\r
+ } else {\r
+ status = NM_E_NOT_EXECUTED; /**< @req CANNM147 */\r
+ }\r
+ return status;\r
+}\r
+\r
+/** Request the network, since ECU needs to communicate on the bus. Network\r
+ * state shall be changed to \91requested\92 */\r
+Nm_ReturnType CanNm_NetworkRequest( const NetworkHandleType nmChannelHandle ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_NETWORKREQUEST, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_NETWORKREQUEST, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+\r
+ ChannelInternal->Requested = TRUE; /**< @req CANNM104 */\r
+\r
+ if (ChannelInternal->Mode == NM_MODE_BUS_SLEEP) {\r
+ CanNm_Internal_BusSleep_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM129 @req CANNM095.1 */\r
+ } else if (ChannelInternal->Mode == NM_MODE_PREPARE_BUS_SLEEP) {\r
+ CanNm_Internal_PrepareBusSleep_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM123 @req CANNM095.2 */\r
+ } else if (ChannelInternal->Mode == NM_MODE_NETWORK) {\r
+ if (ChannelInternal->State == NM_STATE_READY_SLEEP) {\r
+ CanNm_Internal_ReadySleep_to_NormalOperation(ChannelConf, ChannelInternal); /**< @req CANNM110 */\r
+ }\r
+ } else {\r
+ //Nothing to be done\r
+ }\r
+ return NM_E_OK;\r
+}\r
+\r
+/** Release the network, since ECU doesn\92t have to communicate on the bus. Network\r
+ * state shall be changed to \91released\92. */\r
+Nm_ReturnType CanNm_NetworkRelease( const NetworkHandleType nmChannelHandle ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_NETWORKRELEASE, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_NETWORKRELEASE, NM_E_NOT_OK);\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+\r
+ ChannelInternal->Requested = FALSE; /**< @req CANNM105 */\r
+\r
+ if (ChannelInternal->Mode == NM_MODE_NETWORK) {\r
+ if (ChannelInternal->State == NM_STATE_NORMAL_OPERATION) {\r
+ CanNm_Internal_NormalOperation_to_ReadySleep(ChannelConf, ChannelInternal); /**< @req CANNM118 */\r
+ }\r
+ }\r
+ return NM_E_OK;\r
+}\r
+\r
+/** Disable the NM PDU transmission ability due to a ISO14229 Communication\r
+ * Control (28hex) service */\r
+Nm_ReturnType CanNm_DisableCommunication( const NetworkHandleType nmChannelHandle ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_DISABLECOMMUNICATION, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_DISABLECOMMUNICATION, NM_E_NOT_OK);\r
+ return NM_E_NOT_OK;\r
+}\r
+\r
+/** Enable the NM PDU transmission ability due to a ISO14229 Communication\r
+ * Control (28hex) service */\r
+Nm_ReturnType CanNm_EnableCommunication( const NetworkHandleType nmChannelHandle ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_ENABLECOMMUNICATION, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_ENABLECOMMUNICATION, NM_E_NOT_OK);\r
+ return NM_E_NOT_OK;\r
+}\r
+\r
+#if (CANNM_USER_DATA_ENABLED == STD_ON) /**< @req CANNM053.1 */\r
+/** Set user data for NM messages transmitted next on the bus. */\r
+/** @req CANNM159 @req CANNM015 */\r
+Nm_ReturnType CanNm_SetUserData( const NetworkHandleType nmChannelHandle, const uint8* const nmUserDataPtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_SETUSERDATA, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_SETUSERDATA, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+ uint8* destUserData = CanNm_Internal_GetUserDataPtr(ChannelConf, ChannelInternal->TxMessageSdu);\r
+ uint8 userDataLength = CanNm_Internal_GetUserDataLength(ChannelConf);\r
+\r
+ memcpy(destUserData, nmUserDataPtr, userDataLength);\r
+\r
+ return NM_E_OK;\r
+}\r
+#endif\r
+\r
+#if (CANNM_USER_DATA_ENABLED == STD_ON) /**< @req CANNM053.2 */\r
+/** Get user data out of the most recently received NM message. */\r
+/** @req CANNM160 @req CANNM031 */\r
+Nm_ReturnType CanNm_GetUserData( const NetworkHandleType nmChannelHandle, uint8* const nmUserDataPtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_GETUSERDATA, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_GETUSERDATA, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+ uint8* sourceUserData = CanNm_Internal_GetUserDataPtr(ChannelConf, ChannelInternal->RxMessageSdu);\r
+ uint8 userDataLength = CanNm_Internal_GetUserDataLength(ChannelConf);\r
+\r
+ memcpy(nmUserDataPtr, sourceUserData, userDataLength);\r
+\r
+ return NM_E_OK;\r
+}\r
+#endif\r
+\r
+#if (CANNM_NODE_ID_ENABLED == STD_ON)\r
+/** Get node identifier out of the most recently received NM PDU. */\r
+/** @req CANNM132 */\r
+Nm_ReturnType CanNm_GetNodeIdentifier( const NetworkHandleType nmChannelHandle, uint8 * const nmNodeIdPtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_GETNODEIDENTIFIER, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_GETNODEIDENTIFIER, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+ Nm_ReturnType status = NM_E_OK;\r
+\r
+ if (ChannelConf->NidPosition == CANNM_PDU_OFF) {\r
+ status = NM_E_NOT_EXECUTED;\r
+ } else {\r
+ *nmNodeIdPtr = ChannelInternal->RxMessageSdu[ChannelConf->NidPosition];\r
+ status = NM_E_OK;\r
+ }\r
+ return status;\r
+}\r
+\r
+/** Get node identifier configured for the local node. */\r
+/** @req CANNM133 */\r
+Nm_ReturnType CanNm_GetLocalNodeIdentifier( const NetworkHandleType nmChannelHandle, uint8 * const nmNodeIdPtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_GETLOCALNODEIDENTIFIER, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_GETLOCALNODEIDENTIFIER, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ *nmNodeIdPtr = ChannelConf->NodeId;\r
+\r
+ return NM_E_OK;\r
+}\r
+#endif\r
+\r
+#if (CANNM_NODE_DETECTION_ENABLED == STD_ON)\r
+/** Set Repeat Message Request Bit for NM messages transmitted next on the bus. */\r
+/** @req CANNM135 @req CANNM136 */\r
+Nm_ReturnType CanNm_RepeatMessageRequest( const NetworkHandleType nmChannelHandle ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_REPEATMESSAGEREQUEST, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_REPEATMESSAGEREQUEST, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+ Nm_ReturnType status = NM_E_NOT_EXECUTED; /**< @req CANNM137 */\r
+\r
+ if (ChannelConf->CbvPosition != CANNM_PDU_OFF) {\r
+ if (ChannelInternal->State == NM_STATE_READY_SLEEP) {\r
+ ChannelInternal->TxMessageSdu[ChannelConf->CbvPosition] = CANNM_CBV_REPEAT_MESSAGE_REQUEST; /**< @req CANNM113 */\r
+ CanNm_Internal_ReadySleep_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM112 */\r
+ status = NM_E_OK;\r
+ } else if (ChannelInternal->State == NM_STATE_NORMAL_OPERATION) {\r
+ ChannelInternal->TxMessageSdu[ChannelConf->CbvPosition] = CANNM_CBV_REPEAT_MESSAGE_REQUEST; /**< @req CANNM121 */\r
+ CanNm_Internal_NormalOperation_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM120 */\r
+ status = NM_E_OK;\r
+ } else {\r
+ //Nothing to be done\r
+ }\r
+ }\r
+ return status;\r
+}\r
+#endif\r
+\r
+#if ((CANNM_NODE_ID_ENABLED == STD_ON) || (CANNM_NODE_DETECTION_ENABLED == STD_ON) || (CANNM_USER_DATA_ENABLED == STD_ON))\r
+/** Get the whole PDU data out of the most recently received NM message. */\r
+/** @req CANNM138 @req CANNM139 */\r
+Nm_ReturnType CanNm_GetPduData( const NetworkHandleType nmChannelHandle, uint8 * const nmPduDataPtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_GETPDUDATA, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_GETPDUDATA, NM_E_NOT_OK);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+\r
+ memcpy(nmPduDataPtr, ChannelInternal->RxMessageSdu, ChannelConf->PduLength);\r
+\r
+ return NM_E_OK;\r
+}\r
+#endif\r
+\r
+/** Returns the state and the mode of the network management. */\r
+/** @req CANNM091 */\r
+Nm_ReturnType CanNm_GetState( const NetworkHandleType nmChannelHandle, Nm_StateType * const nmStatePtr, Nm_ModeType * const nmModePtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_GETSTATE, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_GETSTATE, NM_E_NOT_OK);\r
+\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+ *nmStatePtr = ChannelInternal->State;\r
+ *nmModePtr = ChannelInternal->Mode;\r
+\r
+ return NM_E_OK;\r
+}\r
+\r
+/** Request bus synchronization. */\r
+Nm_ReturnType CanNm_RequestBusSynchronization( const NetworkHandleType nmChannelHandle ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_REQUESTBUSSYNCHRONIZATION, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_REQUESTBUSSYNCHRONIZATION, NM_E_NOT_OK);\r
+ // Not implemented\r
+ return NM_E_NOT_OK;\r
+}\r
+\r
+/** Check if remote sleep indication takes place or not. */\r
+Nm_ReturnType CanNm_CheckRemoteSleepIndication( const NetworkHandleType nmChannelHandle, boolean * const nmRemoteSleepIndPtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_CHECKREMOTESLEEPINDICATION, NM_E_NOT_OK);\r
+ CANNM_VALIDATE_CHANNEL(nmChannelHandle, CANNM_SERVICEID_CHECKREMOTESLEEPINDICATION, NM_E_NOT_OK);\r
+ (void)nmRemoteSleepIndPtr;\r
+ // Not implemented\r
+ return NM_E_NOT_OK;\r
+}\r
+\r
+\r
+// Functions called by CAN Interface\r
+// ---------------------------------\r
+\r
+/** This service confirms a previous successfully processed CAN transmit request.\r
+ * This callback service is called by the CanIf and implemented by the CanNm. */\r
+/** @req CANNM034.deferred */\r
+void CanNm_TxConfirmation( PduIdType canNmTxPduId ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_TXCONFIRMATION);\r
+ CANNM_VALIDATE_CHANNEL(canNmTxPduId, CANNM_SERVICEID_TXCONFIRMATION);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[canNmTxPduId];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[canNmTxPduId];\r
+\r
+ if (ChannelInternal->Mode == NM_MODE_NETWORK) {\r
+ CanNm_Internal_NetworkMode_to_NetworkMode(ChannelConf, ChannelInternal); /**< @req CANNM099.1 */\r
+ }\r
+}\r
+\r
+/** This service indicates a successful reception of a received NM message to the\r
+ * CanNm after passing all filters and validation checks.\r
+ * This callback service is called by the CAN Interface and implemented by the CanNm. */\r
+void CanNm_RxIndication( PduIdType canNmRxPduId, const uint8 *canSduPtr ){\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_RXINDICATION);\r
+ CANNM_VALIDATE_CHANNEL(canNmRxPduId, CANNM_SERVICEID_RXINDICATION);\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[canNmRxPduId];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[canNmRxPduId];\r
+\r
+ memcpy(ChannelInternal->RxMessageSdu, canSduPtr, ChannelConf->PduLength); /**< @req CANNM035 */\r
+\r
+ boolean repeatMessageBitIndication = FALSE;\r
+ if (ChannelConf->CbvPosition != CANNM_PDU_OFF) {\r
+ uint8 cbv = ChannelInternal->RxMessageSdu[ChannelConf->CbvPosition];\r
+ repeatMessageBitIndication = cbv & CANNM_CBV_REPEAT_MESSAGE_REQUEST;\r
+ }\r
+\r
+ if (ChannelInternal->Mode == NM_MODE_BUS_SLEEP) {\r
+ CanNm_Internal_BusSleep_to_BusSleep(ChannelConf, ChannelInternal); /**< @req CANNM127.2 */\r
+ } else if (ChannelInternal->Mode == NM_MODE_PREPARE_BUS_SLEEP) {\r
+ CanNm_Internal_PrepareBusSleep_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM124 @req CANNM095.4 */\r
+ } else if (ChannelInternal->Mode == NM_MODE_NETWORK) {\r
+ CanNm_Internal_NetworkMode_to_NetworkMode(ChannelConf, ChannelInternal); /**< @req CANNM098.1 */\r
+ if (repeatMessageBitIndication) {\r
+ if (ChannelInternal->State == NM_STATE_READY_SLEEP) {\r
+ CanNm_Internal_ReadySleep_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM111 */\r
+ } else if (ChannelInternal->State == NM_STATE_NORMAL_OPERATION) {\r
+ CanNm_Internal_NormalOperation_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM119 */\r
+ } else {\r
+ //Nothing to be done\r
+ }\r
+ }\r
+ } else {\r
+ //Nothing to be done\r
+ }\r
+#if (CANNM_PDU_RX_INDICATION_ENABLED == STD_ON)\r
+ // TODO: call NM rx indication\r
+#endif\r
+}\r
+\r
+\r
+\r
+\r
+// ----------------------------------------------------------------------------\r
+// Internal functions\r
+// ----------------------------------------------------------------------------\r
+// Accessed through CanNm_MainFunction_<channel>\r
+void CanNm_MainFunction(NetworkHandleType nmChannelHandle);\r
+\r
+void CanNm_MainFunction( NetworkHandleType nmChannelHandle ) {\r
+ CANNM_VALIDATE_INIT(CANNM_SERVICEID_ARC_MAINFUNCTION);\r
+\r
+ /** @req CANNM108 */\r
+\r
+ const CanNm_ChannelType* ChannelConf = &CanNm_ConfigPtr->Channels[nmChannelHandle];\r
+ CanNm_Internal_ChannelType* ChannelInternal = &CanNm_Internal.Channels[nmChannelHandle];\r
+ if (ChannelInternal->Mode == NM_MODE_NETWORK) {\r
+ CanNm_Internal_TickTimeoutTime(ChannelConf, ChannelInternal);\r
+#if (CANNM_PASSIVE_MODE_ENABLED != STD_ON) /**< @req CANNM072 */\r
+ if ((ChannelInternal->State == NM_STATE_REPEAT_MESSAGE) ||\r
+ (ChannelInternal->State == NM_STATE_NORMAL_OPERATION)) {\r
+ /** @req CANNM051 @req CANNM032 @req CANNM087.1 @req CANNM100.6 */\r
+ CanNm_Internal_TickMessageCycleTime(ChannelConf, ChannelInternal);\r
+ }\r
+#endif\r
+ if (ChannelInternal->State == NM_STATE_REPEAT_MESSAGE) {\r
+ CanNm_Internal_TickRepeatMessageTime(ChannelConf, ChannelInternal); /**< @req CANNM102.2 */\r
+ }\r
+ } else if (ChannelInternal->Mode == NM_MODE_PREPARE_BUS_SLEEP) {\r
+ CanNm_Internal_TickWaitBusSleepTime(ChannelConf, ChannelInternal); /**< @req CANNM115.2 */\r
+ } else {\r
+ //Nothing to be done\r
+ }\r
+}\r
+\r
+// Timer helpers\r
+// -------------\r
+\r
+static inline void CanNm_Internal_TickTimeoutTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ if (ChannelConf->MainFunctionPeriod >= ChannelInternal->TimeoutTimeLeft) {\r
+ ChannelInternal->TimeoutTimeLeft = 0;\r
+ if (ChannelInternal->State == NM_STATE_REPEAT_MESSAGE) {\r
+#if defined(USE_DEM)\r
+ Dem_ReportErrorStatus(CANNM_E_NETWORK_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
+#endif\r
+ CanNm_Internal_RepeatMessage_to_RepeatMessage(ChannelConf, ChannelInternal); /**< @req CANNM101.1 */\r
+ } else if (ChannelInternal->State == NM_STATE_NORMAL_OPERATION) {\r
+#if defined(USE_DEM)\r
+ Dem_ReportErrorStatus(CANNM_E_NETWORK_TIMEOUT, DEM_EVENT_STATUS_FAILED);\r
+#endif\r
+ CanNm_Internal_NormalOperation_to_NormalOperation(ChannelConf, ChannelInternal); /**< @req CANNM117.1 */\r
+ } else if (ChannelInternal->State == NM_STATE_READY_SLEEP) {\r
+ CanNm_Internal_ReadySleep_to_PrepareBusSleep(ChannelConf, ChannelInternal); /**< @req CANNM109 */\r
+ } else {\r
+ //Nothing to be done\r
+ }\r
+ } else {\r
+ ChannelInternal->TimeoutTimeLeft -= ChannelConf->MainFunctionPeriod;\r
+ }\r
+}\r
+\r
+/** @req CANNM102.1 */\r
+static inline void CanNm_Internal_TickRepeatMessageTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ if (ChannelConf->MainFunctionPeriod >= ChannelInternal->RepeatMessageTimeLeft) {\r
+ ChannelInternal->RepeatMessageTimeLeft = 0;\r
+ if (ChannelInternal->State == NM_STATE_REPEAT_MESSAGE) {\r
+ if (ChannelInternal->Requested) {\r
+ CanNm_Internal_RepeatMessage_to_NormalOperation(ChannelConf, ChannelInternal); /**< @req CANNM103 */\r
+ } else {\r
+ CanNm_Internal_RepeatMessage_to_ReadySleep(ChannelConf, ChannelInternal); /**< @req CANNM104 */\r
+ }\r
+ }\r
+ } else {\r
+ ChannelInternal->RepeatMessageTimeLeft -= ChannelConf->MainFunctionPeriod;\r
+ }\r
+}\r
+\r
+/** @req CANNM115.1 */\r
+static inline void CanNm_Internal_TickWaitBusSleepTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ if (ChannelConf->MainFunctionPeriod >= ChannelInternal->WaitBusSleepTimeLeft) {\r
+ ChannelInternal->WaitBusSleepTimeLeft = 0;\r
+ if (ChannelInternal->Mode == NM_MODE_PREPARE_BUS_SLEEP) {\r
+ CanNm_Internal_PrepareBusSleep_to_BusSleep(ChannelConf, ChannelInternal);\r
+ }\r
+ } else {\r
+ ChannelInternal->WaitBusSleepTimeLeft -= ChannelConf->MainFunctionPeriod;\r
+ }\r
+}\r
+\r
+static inline void CanNm_Internal_TickMessageCycleTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ if (ChannelConf->MainFunctionPeriod >= ChannelInternal->MessageCycleTimeLeft) {\r
+ ChannelInternal->MessageCycleTimeLeft = 0;\r
+ if ((ChannelInternal->State == NM_STATE_REPEAT_MESSAGE) ||\r
+ (ChannelInternal->State == NM_STATE_NORMAL_OPERATION)) {\r
+ ChannelInternal->MessageCycleTimeLeft = ChannelConf->MessageCycleTime; /**< @req CANNM040 */\r
+ /** @req CANNM087.2 @req CANNM100.5 */\r
+ CanNm_Internal_TransmitMessage(ChannelConf, ChannelInternal);\r
+ }\r
+ } else {\r
+ ChannelInternal->MessageCycleTimeLeft -= ChannelConf->MainFunctionPeriod;\r
+ }\r
+}\r
+\r
+// Message helpers\r
+// ---------------\r
+\r
+static inline void CanNm_Internal_TransmitMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ PduInfoType pdu = {\r
+ .SduDataPtr = ChannelInternal->TxMessageSdu,\r
+ .SduLength = ChannelConf->PduLength,\r
+ };\r
+ Std_ReturnType status = CanIf_Transmit(ChannelConf->CanIfPduId, &pdu);\r
+ (void)status;\r
+ // TODO: what to do if Transmit fails?\r
+}\r
+\r
+static inline uint8 CanNm_Internal_GetUserDataOffset( const CanNm_ChannelType* ChannelConf ) {\r
+ uint8 userDataPos = 0;\r
+ userDataPos += (ChannelConf->NidPosition == CANNM_PDU_OFF) ? 0 : 1;\r
+ userDataPos += (ChannelConf->CbvPosition == CANNM_PDU_OFF) ? 0 : 1;\r
+ return userDataPos;\r
+}\r
+\r
+static inline uint8* CanNm_Internal_GetUserDataPtr( const CanNm_ChannelType* ChannelConf, uint8* MessageSduPtr ) {\r
+ uint8 userDataOffset = CanNm_Internal_GetUserDataOffset(ChannelConf);\r
+ return &MessageSduPtr[userDataOffset];\r
+}\r
+\r
+static inline uint8 CanNm_Internal_GetUserDataLength( const CanNm_ChannelType* ChannelConf ) {\r
+ uint8 userDataOffset = CanNm_Internal_GetUserDataOffset(ChannelConf);\r
+ return ChannelConf->PduLength - userDataOffset;\r
+}\r
+\r
+static inline void CanNm_Internal_ClearCbv( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ if (ChannelConf->CbvPosition != CANNM_PDU_OFF) {\r
+ ChannelInternal->TxMessageSdu[ChannelConf->CbvPosition] = 0x00;\r
+ }\r
+}\r
+\r
+// Transition helpers\r
+// ------------------\r
+\r
+static inline void CanNm_Internal_PrepareBusSleep_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_REPEAT_MESSAGE;\r
+ ChannelInternal->TimeoutTimeLeft = ChannelConf->TimeoutTime; /**< @req CANNM096.1 */\r
+ ChannelInternal->RepeatMessageTimeLeft = ChannelConf->RepeatMessageTime;\r
+ ChannelInternal->MessageCycleTimeLeft = ChannelConf->MessageCycleOffsetTime; /**< @req CANNM100.2 */\r
+ // Notify 'Network Mode'\r
+ Nm_NetworkMode(ChannelConf->NmNetworkHandle); /**< @req CANNM097.1 */\r
+}\r
+\r
+static inline void CanNm_Internal_PrepareBusSleep_to_BusSleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_BUS_SLEEP;\r
+ ChannelInternal->State = NM_STATE_BUS_SLEEP;\r
+ // Notify 'Bus-Sleep Mode'\r
+ Nm_BusSleepMode(ChannelConf->NmNetworkHandle); /**< @req CANNM126 */\r
+}\r
+\r
+static inline void CanNm_Internal_BusSleep_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_REPEAT_MESSAGE;\r
+ ChannelInternal->TimeoutTimeLeft = ChannelConf->TimeoutTime; /**< @req CANNM096.2 */\r
+ ChannelInternal->RepeatMessageTimeLeft = ChannelConf->RepeatMessageTime;\r
+ ChannelInternal->MessageCycleTimeLeft = ChannelConf->MessageCycleOffsetTime; /**< @req CANNM100.1 */\r
+ // Notify 'Network Mode'\r
+ Nm_NetworkMode(ChannelConf->NmNetworkHandle); /**< @req CANNM097.2 */\r
+}\r
+static inline void CanNm_Internal_BusSleep_to_BusSleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ // Notify 'Network Start'\r
+ Nm_NetworkStartIndication(ChannelConf->NmNetworkHandle); /**< @req CANNM127.1 */\r
+ (void) ChannelInternal; //Just to avoid 715 PC-Lint warning about not used.\r
+}\r
+\r
+static inline void CanNm_Internal_RepeatMessage_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->TimeoutTimeLeft = ChannelConf->TimeoutTime; /**< @req CANNM101.2 */\r
+ // TODO: Notify 'Network Timeout'?\r
+}\r
+static inline void CanNm_Internal_RepeatMessage_to_ReadySleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_READY_SLEEP;\r
+#if (CANNM_NODE_DETECTION_ENABLED == STD_ON)\r
+ /** @req CANNM107.1 */\r
+ CanNm_Internal_ClearCbv(ChannelConf, ChannelInternal);\r
+#endif\r
+}\r
+static inline void CanNm_Internal_RepeatMessage_to_NormalOperation( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_NORMAL_OPERATION;\r
+#if (CANNM_NODE_DETECTION_ENABLED == STD_ON)\r
+ /** @req CANNM107.2 */\r
+ CanNm_Internal_ClearCbv(ChannelConf, ChannelInternal);\r
+#endif\r
+}\r
+\r
+static inline void CanNm_Internal_NormalOperation_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_REPEAT_MESSAGE;\r
+ ChannelInternal->RepeatMessageTimeLeft = ChannelConf->RepeatMessageTime;\r
+ ChannelInternal->MessageCycleTimeLeft = ChannelConf->MessageCycleOffsetTime; /**< @req CANNM100.3 */\r
+}\r
+static inline void CanNm_Internal_NormalOperation_to_ReadySleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_READY_SLEEP;\r
+ (void) ChannelConf; //Just to avoid 715 PC-Lint warning about not used.\r
+}\r
+static inline void CanNm_Internal_NormalOperation_to_NormalOperation( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->TimeoutTimeLeft = ChannelConf->TimeoutTime; /**< @req CANNM117.2 */\r
+}\r
+\r
+static inline void CanNm_Internal_ReadySleep_to_NormalOperation( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_NORMAL_OPERATION;\r
+ ChannelInternal->MessageCycleTimeLeft = ChannelConf->MessageCycleOffsetTime; /**< @req CANNM116 */\r
+}\r
+static inline void CanNm_Internal_ReadySleep_to_PrepareBusSleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_PREPARE_BUS_SLEEP;\r
+ ChannelInternal->State = NM_STATE_PREPARE_BUS_SLEEP;\r
+ ChannelInternal->WaitBusSleepTimeLeft = ChannelConf->WaitBusSleepTime;\r
+ // Notify 'Prepare Bus-Sleep Mode'\r
+ Nm_PrepareBusSleepMode(ChannelConf->NmNetworkHandle); /**< @req CANNM114 */\r
+}\r
+static inline void CanNm_Internal_ReadySleep_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->Mode = NM_MODE_NETWORK;\r
+ ChannelInternal->State = NM_STATE_REPEAT_MESSAGE;\r
+ ChannelInternal->RepeatMessageTimeLeft = ChannelConf->RepeatMessageTime;\r
+ ChannelInternal->MessageCycleTimeLeft = ChannelConf->MessageCycleOffsetTime; /**< @req CANNM100.4 */\r
+}\r
+\r
+static inline void CanNm_Internal_NetworkMode_to_NetworkMode( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal ) {\r
+ ChannelInternal->TimeoutTimeLeft = ChannelConf->TimeoutTime; /**< @req CANNM098.2 @req CANNM099.2 */\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+//lint -emacro(904,CANSM_VALIDATE_INIT,CANSM_VALIDATE_NETWORK,CANSM_VALIDATE_POINTER,CANSM_VALIDATE_MODE) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
+\r
+/* Globally fulfilled requirements */\r
+/** @req CANSM069 */\r
+/** @req CANSM077 */\r
+/** @req CANSM076 */\r
+/** @req CANSM078 */\r
+/** @req CANSM079 */\r
+/** @req CANSM237 */\r
+/** @req CANSM156.bswbuilder */\r
+\r
+#include "ComStack_Types.h"\r
+#include "CanSM.h" /**< @req CANSM013 */\r
+#include "Com.h" /**< @req CANSM172 */\r
+#include "ComM.h" /**< @req CANSM174 */\r
+#include "ComM_BusSm.h" /**< @req CANSM191 */\r
+#include "Det.h" /**< @req CANSM015 */\r
+#if defined(USE_DEM)\r
+#include "Dem.h" /**< @req CANSM014 */\r
+#endif\r
+#include "CanIf.h" /**< @req CANSM017 */\r
+#include "CanSM_Internal.h"\r
+\r
+static CanSM_Internal_NetworkType CanSM_InternalNetworks[CANSM_NETWORK_COUNT];\r
+\r
+static CanSM_InternalType CanSM_Internal = {\r
+ .InitStatus = CANSM_STATUS_UNINIT,\r
+ .Networks = CanSM_InternalNetworks,\r
+};\r
+\r
+static const CanSM_ConfigType* CanSM_Config;\r
+\r
+/** @req CANSM217.exceptTranceiver */\r
+void CanSM_Init( const CanSM_ConfigType* ConfigPtr ) {\r
+ CANSM_VALIDATE_POINTER(ConfigPtr, CANSM_SERVICEID_INIT); /**< @req CANSM179 */\r
+\r
+ CanSM_Config = ConfigPtr;\r
+ Std_ReturnType status = E_OK;\r
+ Std_ReturnType totalStatus = E_OK;\r
+\r
+ for (uint8 i = 0; i < CANSM_NETWORK_COUNT; ++i) {\r
+ status = CanSM_Internal_RequestComMode(i, COMM_NO_COMMUNICATION); /**< @req CANSM211 */\r
+ if (status > totalStatus) {\r
+ totalStatus = status;\r
+ }\r
+ }\r
+\r
+ if (totalStatus == E_OK) {\r
+ CanSM_Internal.InitStatus = CANSM_STATUS_INIT;\r
+ } else {\r
+ // TODO report error?\r
+ }\r
+}\r
+\r
+\r
+/** @req CANSM181 @req CANSM183 @req CANSM182.partially @req CANSM184 */\r
+Std_ReturnType CanSM_RequestComMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode ) {\r
+ CANSM_VALIDATE_INIT(CANSM_SERVICEID_REQUESTCOMMODE, E_NOT_OK);\r
+ CANSM_VALIDATE_NETWORK(NetworkHandle, CANSM_SERVICEID_REQUESTCOMMODE, E_NOT_OK);\r
+ CANSM_VALIDATE_MODE(ComM_Mode, CANSM_SERVICEID_REQUESTCOMMODE, E_NOT_OK);\r
+\r
+ return CanSM_Internal_RequestComMode(NetworkHandle, ComM_Mode);\r
+}\r
+\r
+/** @req CANSM032.partially @req CANSM212 @req CANSM219.exceptTranceiver @req CANSM218.exceptTranceiver\r
+ * @req CANSM231 @req CANSM232 */\r
+Std_ReturnType CanSM_Internal_RequestComMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode ) {\r
+ CanSM_Internal_NetworkType* NetworkInternal = &CanSM_Internal.Networks[NetworkHandle];\r
+ NetworkInternal->RequestedMode = ComM_Mode;\r
+\r
+ Std_ReturnType overallStatus = E_OK;\r
+ Std_ReturnType status;\r
+ status = CanSM_Internal_RequestCanIfMode(NetworkHandle, ComM_Mode); /**< @req CANSM240 */\r
+ if (status > overallStatus){\r
+ overallStatus = status;\r
+ }\r
+ status = CanSM_Internal_RequestComGroupMode(NetworkHandle, ComM_Mode); /**< @req CANSM241 */\r
+ if (status > overallStatus) {\r
+ overallStatus = status;\r
+ }\r
+\r
+ if (overallStatus == E_OK) {\r
+ NetworkInternal->CurrentMode = ComM_Mode;\r
+ ComM_BusSM_ModeIndication(NetworkHandle, ComM_Mode); /**< @req CANSM089 */\r
+ }\r
+\r
+ return overallStatus;\r
+}\r
+\r
+/** @req CANSM039 @req CANSM044 */\r
+Std_ReturnType CanSM_Internal_RequestCanIfMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode ) {\r
+ const CanSM_NetworkType* Network = &CanSM_Config->Networks[NetworkHandle];\r
+ CanIf_ControllerModeType CanIf_Mode = CANIF_CS_STARTED;\r
+ Std_ReturnType totalStatus = E_OK;\r
+\r
+ switch (ComM_Mode) {\r
+ case COMM_NO_COMMUNICATION:\r
+/* CAN wake-up capability is not implemented so we cannot set\r
+ * controllers into sleep because then we would be unable to\r
+ * wake except on internal requests.\r
+ */\r
+#if 0\r
+ CanIf_Mode = CANIF_CS_SLEEP;\r
+#endif\r
+ CanIf_Mode = CANIF_CS_STARTED;\r
+ break;\r
+ case COMM_FULL_COMMUNICATION:\r
+ CanIf_Mode = CANIF_CS_STARTED;\r
+ break;\r
+ default:\r
+ totalStatus = E_NOT_OK;\r
+ break;\r
+ }\r
+\r
+ if (totalStatus == E_OK) {\r
+ for (uint8 i = 0; i < Network->ControllerCount; ++i) {\r
+ const CanSM_ControllerType* Controller = &Network->Controllers[i];\r
+ Std_ReturnType status =\r
+ CanIf_SetControllerMode(Controller->CanIfControllerId, CanIf_Mode);\r
+ if (status > totalStatus) {\r
+ totalStatus = status;\r
+ }\r
+ }\r
+ }\r
+ return totalStatus;\r
+}\r
+\r
+/** @req CANSM173 */\r
+Std_ReturnType CanSM_Internal_RequestComGroupMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode ) {\r
+ const CanSM_NetworkType* Network = &CanSM_Config->Networks[NetworkHandle];\r
+ Std_ReturnType status = E_OK;\r
+\r
+ switch (ComM_Mode) {\r
+ case COMM_NO_COMMUNICATION:\r
+ Com_IpduGroupStop(Network->ComRxPduGroupId);\r
+ Com_IpduGroupStop(Network->ComTxPduGroupId);\r
+ break;\r
+ case COMM_SILENT_COMMUNICATION:\r
+ Com_IpduGroupStart(Network->ComRxPduGroupId, FALSE);\r
+ Com_IpduGroupStop(Network->ComTxPduGroupId);\r
+ break;\r
+ case COMM_FULL_COMMUNICATION:\r
+ Com_IpduGroupStart(Network->ComRxPduGroupId, FALSE);\r
+ Com_IpduGroupStart(Network->ComTxPduGroupId, FALSE);\r
+ break;\r
+ default:\r
+ status = E_NOT_OK;\r
+ break;\r
+ }\r
+ return status;\r
+}\r
+\r
+/** @req CANSM090 @req CANSM185 @req CANSM187 @req CANSM186 @req CANSM188 */\r
+Std_ReturnType CanSM_GetCurrentComMode( NetworkHandleType NetworkHandle, ComM_ModeType* ComM_ModePtr ) {\r
+ CANSM_VALIDATE_INIT(CANSM_SERVICEID_GETCURRENTCOMMODE, E_NOT_OK);\r
+ CANSM_VALIDATE_NETWORK(NetworkHandle, CANSM_SERVICEID_GETCURRENTCOMMODE, E_NOT_OK);\r
+\r
+ ComM_ModeType ComM_Mode = COMM_FULL_COMMUNICATION;\r
+\r
+ const CanSM_NetworkType* Network = &CanSM_Config->Networks[NetworkHandle];\r
+ Std_ReturnType totalStatus = E_OK;\r
+ for (uint8 i = 0; i < Network->ControllerCount; ++i) {\r
+ const CanSM_ControllerType* Controller = &Network->Controllers[i];\r
+ CanIf_ControllerModeType CanIf_Mode;\r
+ Std_ReturnType status =\r
+ CanIf_GetControllerMode(Controller->CanIfControllerId, &CanIf_Mode);\r
+ if (status > totalStatus) {\r
+ totalStatus = status;\r
+ }\r
+\r
+ if (CanIf_Mode != CANIF_CS_STARTED) {\r
+ ComM_Mode = COMM_NO_COMMUNICATION;\r
+ }\r
+ }\r
+\r
+ *ComM_ModePtr = ComM_Mode;\r
+ return totalStatus;\r
+}\r
+\r
+\r
+void CanSM_MainFunction() {\r
+ CANSM_VALIDATE_INIT(CANSM_SERVICEID_MAINFUNCTION);\r
+}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CANSM_INTERNAL_H\r
+#define CANSM_INTERNAL_H\r
+\r
+#include "CanSM.h"\r
+\r
+/** @req CANSM027 @req CANSM028 @req CANSM071 */\r
+#if (CANSM_DEV_ERROR_DETECT == STD_ON)\r
+#define CANSM_DET_REPORTERROR(serviceId, errorId) \\r
+ Det_ReportError(MODULE_ID_CANSM, 0, serviceId, errorId)\r
+\r
+#define CANSM_VALIDATE(expression, serviceId, errorId, ...) \\r
+ if (!(expression)) { \\r
+ CANSM_DET_REPORTERROR(serviceId, errorId); \\r
+ return __VA_ARGS__; \\r
+ }\r
+\r
+#else\r
+#define CANSM_DET_REPORTERROR(...)\r
+#define CANSM_VALIDATE(...)\r
+#endif\r
+\r
+#define CANSM_VALIDATE_INIT(serviceID, ...) \\r
+ CANSM_VALIDATE((CanSM_Internal.InitStatus == CANSM_STATUS_INIT), serviceID, CANSM_E_UNINIT, __VA_ARGS__)\r
+\r
+#define CANSM_VALIDATE_POINTER(pointer, serviceID, ...) \\r
+ CANSM_VALIDATE( (pointer != NULL), serviceID, CANSM_E_PARAM_POINTER, __VA_ARGS__)\r
+\r
+#define CANSM_VALIDATE_NETWORK(net, serviceID, ...) \\r
+ CANSM_VALIDATE( (net < CANSM_NETWORK_COUNT), serviceID, CANSM_E_INVALID_NETWORK_HANDLE, __VA_ARGS__)\r
+\r
+#define CANSM_VALIDATE_MODE(mode, serviceID, ...) \\r
+ CANSM_VALIDATE( (mode <= COMM_FULL_COMMUNICATION) && (mode != COMM_SILENT_COMMUNICATION), serviceID, CANSM_E_INVALID_NETWORK_MODE, __VA_ARGS__)\r
+\r
+typedef enum {\r
+ CANSM_STATUS_UNINIT,\r
+ CANSM_STATUS_INIT\r
+} CanSM_Internal_InitStatusType;\r
+\r
+\r
+typedef struct {\r
+ uint8 CanIfControllerId;\r
+} CanSM_Internal_ControllerType;\r
+\r
+typedef struct {\r
+ CanSM_Internal_ControllerType* Controllers;\r
+ ComM_ModeType CurrentMode;\r
+ ComM_ModeType RequestedMode;\r
+} CanSM_Internal_NetworkType;\r
+\r
+typedef struct {\r
+ CanSM_Internal_InitStatusType InitStatus;\r
+ CanSM_Internal_NetworkType* Networks;\r
+} CanSM_InternalType;\r
+\r
+Std_ReturnType CanSM_Internal_RequestComMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode );\r
+Std_ReturnType CanSM_Internal_RequestCanIfMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode );\r
+Std_ReturnType CanSM_Internal_RequestComGroupMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode );\r
+\r
+#endif /* CANSM_INTERNAL_H */\r
* TBD.\r
*/\r
\r
+/*\r
+ * General requirements\r
+ */\r
+\r
+/** @req CANTP001 */\r
+/** @req CANTP019 */\r
+/** @req CANTP020 */\r
+/** @req CANTP156.Partially */\r
/** @req CANTP150 */\r
/** @req CANTP151 */\r
/** @req CANTP152 */\r
/** @req CANTP158 */\r
/** @req CANTP003 */\r
/** @req CANTP216 */\r
+/** @req CANTP217 */\r
+\r
+/*\r
+ * Environmental requirements
+ */\r
+/** @req CANTP164 */\r
+/** @req CANTP199 */\r
+\r
\r
+#include "CanTp.h" /** @req CANTP219 */\r
+#include "CanTp_Cbk.h" /** @req CANTP233 */\r
#include "Det.h"\r
#include "CanIf.h"\r
-#include "CanTp_Cfg.h" /** @req CANTP156 */\r
-#include "CanTp_Cbk.h" /** @req CANTP156 *//** @req CANTP233 */\r
-#include "CanTp.h" /** @req CANTP156 */ /** @req CANTP219 */\r
-#include "SchM_CanTp.h" /** @req CANTP156 */\r
+#include "SchM_CanTp.h"\r
#include "PduR_CanTp.h"\r
-//#include "MemMap.h" /** @req CANTP156 */\r
+//#include "MemMap.h"\r
#include <string.h>\r
//#define USE_DEBUG_PRINTF\r
#include "debug.h"\r
\r
+#define CANTP_IMMEDIATE_TX_CONFIRMATION STD_OFF\r
+\r
#if ( CANTP_DEV_ERROR_DETECT == STD_ON ) /** @req CANTP006 *//** @req CANTP134 */\r
\r
/** @req CANTP132 */ /** @req CANTP021 */\r
Det_ReportError(MODULE_ID_CANTP, 0, _api, _err); \\r
return; \\r
}\r
-#undef DET_REPORTERROR\r
#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
\r
#else\r
\r
#endif\r
\r
-//#define INLINE inline\r
+//#define INLINE\r
#define INLINE inline\r
\r
#define TIMER_DECREMENT(timer) \\r
\r
TX_WAIT_CAN_TP_TRANSMIT_CAN_TP_PROVIDE_TX_BUFFER, /** @req CANTP226 */\r
TX_WAIT_CAN_TP_TRANSMIT_PENDING, /* CanTP_Transmit was called but no buffer was received (BUSY). */\r
- TX_WAIT_SEND_CONSECUTIVE_FRAME, TX_WAIT_FLOW_CONTROL\r
+ TX_WAIT_SEND_CONSECUTIVE_FRAME, TX_WAIT_FLOW_CONTROL,\r
+ TX_WAIT_TX_CONFIRMATION\r
} ISO15765TransferStateTypes;\r
\r
typedef enum {\r
uint8 STmin; // In case we are transmitters the remote node can configure this value (only valid for TX).\r
uint8 BS; // Blocksize (only valid for TX).\r
boolean NasNarPending;\r
+#if (CANTP_IMMEDIATE_TX_CONFIRMATION == STD_OFF)\r
+ boolean txConfirmed;\r
+#endif\r
uint32 NasNarTimeoutCount; // CanTpNas, CanTpNar.\r
ISO15765TransferStateTypes state; // Transfer state machine. TODO: Can this be initialized here?\r
} ISO15765TransferControlType;\r
\r
// - - - - - - - - - - - - - -\r
\r
-#if (CANTP_VERSION_INFO_API == STD_ON) /** @req CANTP162 *//** @req CANTP163 */\r
-static Std_VersionInfoType _CanTp_VersionInfo =\r
-{\r
- .vendorID = (uint16)1,\r
- .moduleID = (uint16)1,\r
- .instanceID = (uint8)1,\r
- .sw_major_version = (uint8)CANTP_SW_MAJOR_VERSION,\r
- .sw_minor_version = (uint8)CANTP_SW_MINOR_VERSION,\r
- .sw_patch_version = (uint8)CANTP_SW_PATCH_VERSION,\r
- .ar_major_version = (uint8)CANTP_AR_MAJOR_VERSION,\r
- .ar_minor_version = (uint8)CANTP_AR_MINOR_VERSION,\r
- .ar_patch_version = (uint8)CANTP_AR_PATCH_VERSION,\r
-};\r
-#endif /* DEM_VERSION_INFO_API */\r
-\r
-// - - - - - - - - - - - - - -\r
-\r
CanTp_RunTimeDataType CanTpRunTimeData = { .initRun = FALSE,\r
.internalState = CANTP_OFF }; /** @req CANTP168 */\r
\r
\r
switch (*formatType) {\r
case CANTP_STANDARD:\r
- DEBUG( DEBUG_MEDIUM, "CANTP_STANDARD\n")\r
+ DEBUG( DEBUG_MEDIUM, "CANTP_STANDARD\n");\r
tpci = CanTpRxPduPtr->SduDataPtr[0];\r
break;\r
case CANTP_EXTENDED:\r
- DEBUG( DEBUG_MEDIUM, "CANTP_EXTENDED\n")\r
+ DEBUG( DEBUG_MEDIUM, "CANTP_EXTENDED\n");\r
tpci = CanTpRxPduPtr->SduDataPtr[1];\r
break;\r
default:\r
break;\r
case FIRST_FRAME:\r
// Parse the data length form the first frame.\r
- res = CanTpRxPduPtr->SduDataPtr[tpci_offset + 1] + (PduLengthType)((CanTpRxPduPtr->SduDataPtr[tpci_offset]) & 0xf << 8);\r
+ res = CanTpRxPduPtr->SduDataPtr[tpci_offset + 1] + ((PduLengthType)((CanTpRxPduPtr->SduDataPtr[tpci_offset]) & 0xf) << 8);\r
break;\r
default:\r
res = 0; // TODO: maybe we should have an error code here.\r
\r
// - - - - - - - - - - - - - -\r
\r
-void initRx15765RuntimeData(const CanTp_RxNSduType *rxConfigParams,\r
+static void initRx15765RuntimeData(const CanTp_RxNSduType *rxConfigParams,\r
CanTp_ChannelPrivateType *rxRuntimeParams) {\r
\r
rxRuntimeParams->iso15765.state = IDLE;\r
\r
// - - - - - - - - - - - - - -\r
\r
-void initTx15765RuntimeData(const CanTp_TxNSduType *txConfigParams,\r
+static void initTx15765RuntimeData(const CanTp_TxNSduType *txConfigParams,\r
CanTp_ChannelPrivateType *txRuntimeParams) {\r
\r
txRuntimeParams->iso15765.state = IDLE;\r
PduLengthType segmentSize, PduLengthType *bytesWrittenSuccessfully) {\r
\r
BufReq_ReturnType ret = BUFREQ_NOT_OK;\r
- boolean error = FALSE;\r
+ boolean endLoop = FALSE;\r
*bytesWrittenSuccessfully = 0;\r
\r
- while ((*bytesWrittenSuccessfully < segmentSize) && error == FALSE) {\r
+ while ((*bytesWrittenSuccessfully < segmentSize) && (!endLoop)) {\r
// Copy the data that resides in the buffer.\r
if (rxRuntime->pdurBuffer != NULL) {\r
while ((*bytesWrittenSuccessfully < segmentSize ) && (rxRuntime->pdurBuffer->SduLength > rxRuntime->pdurBufferCount)) {\r
rxRuntime->pdurBufferCount = 0; // The buffer is emptied.\r
} else if (ret == BUFREQ_BUSY) {\r
rxRuntime->transferCount += *bytesWrittenSuccessfully;\r
- error = TRUE;\r
- break;\r
+ endLoop = TRUE;\r
} else {\r
- error = TRUE; // Let calling function handle this error.\r
- break;\r
+ endLoop = TRUE; // Let calling function handle this error.\r
}\r
} else {\r
rxRuntime->transferCount += segmentSize; //== bytesWrittenSuccessfully\r
ret = BUFREQ_OK;\r
- break;\r
+ endLoop = TRUE;\r
}\r
}\r
return ret;\r
}\r
txRuntime->iso15765.NasNarTimeoutCount = CANTP_CONVERT_MS_TO_MAIN_CYCLES(txConfig->CanTpNas); /** @req CANTP075 */\r
txRuntime->iso15765.NasNarPending = TRUE;\r
+#if (CANTP_IMMEDIATE_TX_CONFIRMATION == STD_OFF)\r
+ txRuntime->iso15765.txConfirmed = FALSE;\r
+#endif\r
return CanIf_Transmit(txConfig->CanIf_PduId, PduInfoPtr);\r
}\r
\r
// - - - - - - - - - - - - - -\r
\r
-static INLINE void sendFlowControlFrame(const CanTp_RxNSduType *rxConfig,\r
- CanTp_ChannelPrivateType *rxRuntime, BufReq_ReturnType flowStatus) {\r
- int indexCount = 0;\r
+static INLINE void sendFlowControlFrame(const CanTp_RxNSduType *rxConfig, CanTp_ChannelPrivateType *rxRuntime, BufReq_ReturnType flowStatus) {\r
+ uint8 indexCount = 0;\r
Std_ReturnType ret = E_NOT_OK;\r
PduInfoType pduInfo;\r
uint8 sduData[8]; // Note that buffer in declared on the stack.\r
uint16 spaceFreePduRBuffer = 0;\r
- uint8 computedBs = 0; // req:CanTp064 and example.\r
+ uint16 computedBs = 0;\r
\r
DEBUG( DEBUG_MEDIUM, "sendFlowControlFrame called!\n");\r
pduInfo.SduDataPtr = &sduData[0];\r
sduData[indexCount++] = ISO15765_TPCI_FC | ISO15765_FLOW_CONTROL_STATUS_CTS;\r
spaceFreePduRBuffer = rxRuntime->pdurBuffer->SduLength - rxRuntime->pdurBufferCount;\r
if (rxConfig->CanTpAddressingFormant == CANTP_EXTENDED) { /** @req CANTP094 *//** @req CANTP095 */\r
- computedBs = spaceFreePduRBuffer / MAX_PAYLOAD_SF_EXT_ADDR + 1; // + 1 is for local buffer.\r
+ computedBs = (spaceFreePduRBuffer / MAX_PAYLOAD_SF_EXT_ADDR) + 1; // + 1 is for local buffer.\r
} else {\r
- computedBs = spaceFreePduRBuffer / MAX_PAYLOAD_SF_STD_ADDR + 1; // + 1 is for local buffer.\r
+ computedBs = (spaceFreePduRBuffer / MAX_PAYLOAD_SF_STD_ADDR) + 1; // + 1 is for local buffer.\r
}\r
if (computedBs > rxConfig->CanTpBs) { // /** @req CANTP091 *//** @req CANTP084 */\r
computedBs = rxConfig->CanTpBs;\r
}\r
DEBUG( DEBUG_MEDIUM, "computedBs:%d\n", computedBs);\r
- sduData[indexCount++] = computedBs;\r
+ sduData[indexCount++] = computedBs; // 734 PC-lint: Okej att casta till uint8?\r
sduData[indexCount++] = (uint8) rxConfig->CanTpSTmin;\r
- rxRuntime->iso15765.nextFlowControlCount = (uint8) computedBs;\r
+ rxRuntime->iso15765.nextFlowControlCount = computedBs;\r
pduInfo.SduLength = indexCount;\r
break;\r
}\r
\r
static INLINE void handleConsecutiveFrame(const CanTp_RxNSduType *rxConfig,\r
CanTp_ChannelPrivateType *rxRuntime, const PduInfoType *rxPduData) {\r
- int indexCount = 0;\r
+ uint8 indexCount = 0;\r
uint8 segmentNumber = 0;\r
uint8 extendedAddress = 0;\r
PduLengthType bytesLeftToCopy = 0;\r
rxRuntime->mode = CANTP_RX_WAIT;\r
} else {\r
currentSegmentMaxSize = CANIF_PDU_MAX_LENGTH - indexCount;\r
- bytesLeftToCopy = rxRuntime->transferTotal\r
- - rxRuntime->transferCount;\r
+ bytesLeftToCopy = rxRuntime->transferTotal - rxRuntime->transferCount;\r
if (bytesLeftToCopy < currentSegmentMaxSize) {\r
currentSegmentSize = bytesLeftToCopy; // 1-5.\r
} else {\r
rxRuntime->mode = CANTP_RX_WAIT;\r
} else if (ret == BUFREQ_BUSY) {\r
boolean dataCopyFailure = FALSE;\r
- PduLengthType bytesNotCopiedToPdurRxBuffer =\r
- currentSegmentSize - bytesCopiedToPdurRxBuffer;\r
+ PduLengthType bytesNotCopiedToPdurRxBuffer = currentSegmentSize - bytesCopiedToPdurRxBuffer;\r
if (rxConfig->CanTpAddressingFormant == CANTP_STANDARD) {\r
if ( copySegmentToLocalRxBuffer(rxRuntime, /** @req CANTP067 */\r
&rxPduData->SduDataPtr[1 + bytesCopiedToPdurRxBuffer],\r
rxRuntime->iso15765.state = IDLE;\r
rxRuntime->mode = CANTP_RX_WAIT;\r
dataCopyFailure = TRUE;\r
- DEBUG( DEBUG_MEDIUM, "Unexpected error, could not copy 'unaligned leftover' "\r
- "data to local buffer!\n");\r
+ DEBUG( DEBUG_MEDIUM, "Unexpected error, could not copy 'unaligned leftover' " "data to local buffer!\n");\r
}\r
} else {\r
if ( copySegmentToLocalRxBuffer(rxRuntime, /** @req CANTP067 */\r
rxRuntime->iso15765.state = IDLE;\r
rxRuntime->mode = CANTP_RX_WAIT;\r
dataCopyFailure = TRUE;\r
- DEBUG( DEBUG_MEDIUM, "Unexpected error, could not copy 'unaligned leftover' "\r
- "data to local buffer!\n");\r
+ DEBUG( DEBUG_MEDIUM, "Unexpected error, could not copy 'unaligned leftover' " "data to local buffer!\n");\r
}\r
}\r
- if ( dataCopyFailure == FALSE ) {\r
+ if ( !dataCopyFailure ) {\r
rxRuntime->iso15765.framesHandledCount++;\r
rxRuntime->iso15765.stateTimeoutCount = CANTP_CONVERT_MS_TO_MAIN_CYCLES(rxConfig->CanTpNbr);\r
rxRuntime->iso15765.state = RX_WAIT_SDU_BUFFER;\r
}\r
}\r
}\r
-}\r
+} // 438, 550 PC-lint: extendedAdress not accessed. Extended adress needs to be implemented. Ticket #136\r
\r
// - - - - - - - - - - - - - -\r
\r
PduLengthType consecutiveFrameActualPayload = 0;\r
PduLengthType remaningSduDataSize = 0;\r
PduInfoType pduInfo;\r
- int copyCount = 0;\r
- int indexCount = 0;\r
+ uint16 copyCount = 0;\r
+ uint16 indexCount = 0;\r
\r
if (txConfig->CanTpAddressingMode == CANTP_EXTENDED) { /** @req CANTP094 *//** @req CANTP095 */\r
sduData[indexCount++] = (uint8) txConfig->CanTpNTa->CanTpNTa; // Target address.\r
\r
if (txRuntime->transferTotal <= txRuntime->transferCount) {\r
// Transfer finished!\r
+#if (CANTP_IMMEDIATE_TX_CONFIRMATION == STD_OFF)\r
+ txRuntime->iso15765.state = TX_WAIT_TX_CONFIRMATION;\r
+#else\r
+ PduR_CanTpTxConfirmation(txConfig->PduR_PduId, NTFRSLT_OK); /** @req CANTP074 *//** @req CANTP09 *//** @req CANTP204 */\r
txRuntime->iso15765.state = IDLE;\r
txRuntime->mode = CANTP_TX_WAIT;\r
- PduR_CanTpTxConfirmation(txConfig->PduR_PduId, NTFRSLT_OK); /** @req CANTP074 *//** @req CANTP09 *//** @req CANTP204 */\r
+#endif\r
} else if (txRuntime->iso15765.nextFlowControlCount == 0) {\r
if (txRuntime->iso15765.BS) { // Check if receiver expects flow control.\r
// Time to send flow control!\r
- txRuntime->iso15765.stateTimeoutCount = CANTP_CONVERT_MS_TO_MAIN_CYCLES(txConfig->CanTpNbs); /*CanTp: 264*/\r
+ txRuntime->iso15765.stateTimeoutCount = CANTP_CONVERT_MS_TO_MAIN_CYCLES(txConfig->CanTpNbs); /** @req CANTP264 */\r
txRuntime->iso15765.state = TX_WAIT_FLOW_CONTROL;\r
} else {\r
// Send next consecutive frame!\r
}\r
switch (txPduData->SduDataPtr[indexCount++] & ISO15765_TPCI_FS_MASK) {\r
case ISO15765_FLOW_CONTROL_STATUS_CTS:\r
+#if 1\r
+ { // This construction is added to make the hcs12 compiler happy.\r
+ const uint8 bs = txPduData->SduDataPtr[indexCount++];\r
+ txRuntime->iso15765.BS = bs;\r
+ txRuntime->iso15765.nextFlowControlCount = bs;\r
+ }\r
+ txRuntime->iso15765.STmin = txPduData->SduDataPtr[indexCount++];\r
+#else\r
txRuntime->iso15765.BS = txPduData->SduDataPtr[indexCount++];\r
txRuntime->iso15765.nextFlowControlCount = txRuntime->iso15765.BS;\r
txRuntime->iso15765.STmin = txPduData->SduDataPtr[indexCount++];\r
+#endif\r
DEBUG( DEBUG_MEDIUM, "txRuntime->iso15765.STmin = %d\n", txRuntime->iso15765.STmin);\r
ret = sendConsecutiveFrame(txConfig, txRuntime);\r
if (ret == E_OK) {\r
} else {\r
DEBUG( DEBUG_MEDIUM, "Ignoring flow control, we do not expect it!");\r
}\r
-}\r
+} // 438, 550 PC-lint: extendAdress används inte. EN BUG? Behöver fixas\r
+\r
\r
// - - - - - - - - - - - - - -\r
\r
(void) initRx15765RuntimeData(rxConfig, rxRuntime); /** @req CANTP124 */\r
pduLength = getPduLength(&rxConfig->CanTpAddressingFormant, SINGLE_FRAME, rxPduData);\r
\r
- VALIDATE_NO_RV( rxRuntime->pdurBuffer->SduDataPtr != NULL,\r
+ if (rxRuntime->pdurBuffer != NULL) {\r
+ VALIDATE_NO_RV( rxRuntime->pdurBuffer->SduDataPtr != NULL,\r
SERVICE_ID_CANTP_RX_INDICATION, CANTP_E_INVALID_RX_LENGTH );\r
+ }\r
\r
if (rxConfig->CanTpAddressingFormant == CANTP_STANDARD) { /** @req CANTP094 *//** @req CANTP095 */\r
data = &rxPduData->SduDataPtr[1];\r
// Validate that that there is a reason for using the segmented transfers and\r
// if not simply skip (single frame should have been used).\r
if (rxConfig->CanTpAddressingFormant == CANTP_STANDARD) { /** @req CANTP094 *//** @req CANTP095 */\r
- if (pduLength <= MAX_PAYLOAD_SF_STD_ADDR)\r
+ if (pduLength <= MAX_PAYLOAD_SF_STD_ADDR){\r
return;\r
+ }\r
} else {\r
- if (pduLength <= MAX_PAYLOAD_SF_EXT_ADDR)\r
+ if (pduLength <= MAX_PAYLOAD_SF_EXT_ADDR){\r
return;\r
+ }\r
}\r
// Validate that the SDU is full length in this first frame.\r
if (rxPduData->SduLength < CANIF_PDU_MAX_LENGTH) {\r
\r
// - - - - - - - - - - - - - -\r
\r
-static INLINE Std_ReturnType calcRequiredProtocolFrameType(\r
- const CanTp_TxNSduType *txConfig, CanTp_ChannelPrivateType *txRuntime,\r
- ISO15765FrameType *iso15765Frame) {\r
+static INLINE ISO15765FrameType calcRequiredProtocolFrameType(\r
+ const CanTp_TxNSduType *txConfig, CanTp_ChannelPrivateType *txRuntime) {\r
\r
- Std_ReturnType ret;\r
+ ISO15765FrameType ret = INVALID_FRAME;\r
if (txConfig->CanTpAddressingMode == CANTP_EXTENDED) {\r
- if ( txRuntime->transferTotal > MAX_PAYLOAD_CF_EXT_ADDR ) {\r
- VALIDATE( txConfig->CanTpTxTaType == CANTP_FUNCTIONAL,\r
- SERVICE_ID_CANTP_TRANSMIT, CANTP_E_INVALID_TATYPE );\r
- }\r
- if (txRuntime->transferTotal > MAX_PAYLOAD_CF_EXT_ADDR) {\r
+ if (txRuntime->transferTotal <= MAX_PAYLOAD_CF_EXT_ADDR) {\r
+ ret = SINGLE_FRAME;\r
+ } else {\r
if (txConfig->CanTpTxTaType == CANTP_PHYSICAL) {\r
- *iso15765Frame = FIRST_FRAME;\r
- ret = E_OK;\r
+ ret = FIRST_FRAME;\r
} else {\r
- *iso15765Frame = NONE;\r
- ret = E_NOT_OK;\r
+ DET_REPORTERROR( MODULE_ID_CANTP, 0, SERVICE_ID_CANTP_TRANSMIT, CANTP_E_INVALID_TATYPE );\r
}\r
- } else {\r
- *iso15765Frame = SINGLE_FRAME;\r
- ret = E_OK;\r
}\r
- } else {\r
- if ( txRuntime->transferTotal > MAX_PAYLOAD_CF_EXT_ADDR ) {\r
- VALIDATE( txConfig->CanTpTxTaType == CANTP_FUNCTIONAL,\r
- SERVICE_ID_CANTP_TRANSMIT, CANTP_E_INVALID_TATYPE );\r
- }\r
- if (txRuntime->transferTotal > MAX_PAYLOAD_CF_STD_ADDR) {\r
+ } else { // CANTP_STANDARD\r
+ if (txRuntime->transferTotal <= MAX_PAYLOAD_CF_STD_ADDR) {\r
+ ret = SINGLE_FRAME;\r
+ } else {\r
if (txConfig->CanTpTxTaType == CANTP_PHYSICAL) {\r
- *iso15765Frame = FIRST_FRAME;\r
- ret = E_OK;\r
+ ret = FIRST_FRAME;\r
} else {\r
- *iso15765Frame = NONE;\r
- ret = E_NOT_OK;\r
+ DET_REPORTERROR( MODULE_ID_CANTP, 0, SERVICE_ID_CANTP_TRANSMIT, CANTP_E_INVALID_TATYPE );\r
}\r
- } else {\r
- *iso15765Frame = SINGLE_FRAME;\r
- ret = E_OK;\r
}\r
}\r
+\r
return ret;\r
}\r
\r
static INLINE Std_ReturnType sendSingleFrame(const CanTp_TxNSduType *txConfig,\r
CanTp_ChannelPrivateType *txRuntime) {\r
Std_ReturnType ret;\r
- int indexCount = 0;\r
+ uint16 indexCount = 0;\r
PduInfoType pduInfo;\r
uint8 sduData[CANIF_PDU_MAX_LENGTH];\r
\r
if (txConfig->CanTpAddressingMode == CANTP_EXTENDED) { /** @req CANTP094 *//** @req CANTP095 */\r
sduData[indexCount++] = (uint8) txConfig->CanTpNTa->CanTpNTa; // Target address.\r
}\r
- sduData[indexCount++] = ISO15765_TPCI_SF | txRuntime->transferTotal;\r
+ sduData[indexCount++] = ISO15765_TPCI_SF | txRuntime->transferTotal; // 734 PC-lint: Okej att casta till uint8?\r
for (int i = 0; i < txRuntime->transferTotal; i++) {\r
sduData[indexCount++] = txRuntime->pdurBuffer->SduDataPtr[i];\r
}\r
static INLINE Std_ReturnType sendFirstFrame(const CanTp_TxNSduType *txConfig,\r
CanTp_ChannelPrivateType *txRuntime) {\r
Std_ReturnType ret;\r
- int indexCount = 0;\r
- int i = 0;\r
+ uint8 indexCount = 0;\r
+ uint8 i = 0;\r
PduInfoType pduInfo;\r
uint8 sduData[CANIF_PDU_MAX_LENGTH];\r
\r
VALIDATE( txRuntime->pdurBuffer->SduDataPtr != NULL,\r
SERVICE_ID_CANTP_TRANSMIT, CANTP_E_INVALID_TX_BUFFER );\r
if (pdurResp == BUFREQ_OK) {\r
- res = calcRequiredProtocolFrameType(txConfig, txRuntime, &iso15765Frame);\r
+ iso15765Frame = calcRequiredProtocolFrameType(txConfig, txRuntime);\r
switch (iso15765Frame) {\r
case SINGLE_FRAME:\r
res = sendSingleFrame(txConfig, txRuntime); /** @req CANTP231 */\r
if (res == E_OK) {\r
+#if (CANTP_IMMEDIATE_TX_CONFIRMATION == STD_OFF)\r
+ txRuntime->iso15765.state = TX_WAIT_TX_CONFIRMATION;\r
+#else\r
PduR_CanTpTxConfirmation(txConfig->PduR_PduId, NTFRSLT_OK); /** @req CANTP204 */\r
+ txRuntime->iso15765.state = IDLE;\r
+ txRuntime->mode = CANTP_TX_WAIT;\r
+#endif\r
} else {\r
PduR_CanTpTxConfirmation(txConfig->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP204 */\r
+ txRuntime->iso15765.state = IDLE;\r
+ txRuntime->mode = CANTP_TX_WAIT;\r
}\r
- txRuntime->iso15765.state = IDLE;\r
- txRuntime->mode = CANTP_TX_WAIT;\r
break;\r
case FIRST_FRAME: {\r
txRuntime->iso15765.stateTimeoutCount = CANTP_CONVERT_MS_TO_MAIN_CYCLES(txConfig->CanTpNbs); /** @req CANTP264 */\r
SERVICE_ID_CANTP_TRANSMIT, CANTP_E_UNINIT ); /** @req CANTP031 */\r
VALIDATE( CanTpTxSduId < CANTP_NSDU_CONFIG_LIST_SIZE, SERVICE_ID_CANTP_TRANSMIT, CANTP_E_INVALID_TX_ID );\r
\r
- txConfig = (CanTp_TxNSduType*)&CanTpConfig.CanTpNSduList[CanTpTxSduId].configData;\r
+ txConfig =&CanTpConfig.CanTpNSduList[CanTpTxSduId].configData.CanTpTxNSdu;\r
\r
txRuntime = &CanTpRunTimeData.runtimeDataList[txConfig->CanTpTxChannel]; // Runtime data.\r
if (txRuntime->iso15765.state == IDLE) {\r
\r
#if FRTP_CANCEL_TRANSMIT_REQUEST\r
Std_ReturnType FrTp_CancelTransmitRequest(PduIdType FrTpTxPduId,\r
- FrTp_CancelReasonType FrTpCancelReason) /** @req CANTP246 */\r
+ FrTp_CancelReasonType FrTpCancelReason)\r
{\r
return E_NOT_OK;\r
}\r
// - - - - - - - - - - - - - -\r
\r
\r
-void CanTp_Init() /** @req CANTP208 */\r
+void CanTp_Init(void)\r
{\r
CanTp_ChannelPrivateType *runtimeData;\r
const CanTp_TxNSduType *txConfigParams;\r
// - - - - - - - - - - - - - -\r
\r
void CanTp_RxIndication(PduIdType CanTpRxPduId, /** @req CANTP078 */ /** @req CANTP035 */\r
- const PduInfoType *CanTpRxPduPtr) /** @req CANTP214 */\r
+ const PduInfoType *CanTpRxPduPtr)\r
{\r
CanTpFifoQueueItem item;\r
VALIDATE_NO_RV( CanTpRunTimeData.internalState == CANTP_ON,\r
// - - - - - - - - - - - - - -\r
\r
void CanTp_RxIndication_Main(PduIdType CanTpRxPduId,\r
- const PduInfoType *CanTpRxPduPtr) /** @req CANTP214 */\r
+ const PduInfoType *CanTpRxPduPtr)\r
{\r
const CanTp_RxNSduType *rxConfigParams; // Params reside in ROM.\r
const CanTp_TxNSduType *txConfigParams;\r
DEBUG( DEBUG_MEDIUM, "calling handleSingleFrame!\n");\r
handleSingleFrame(rxConfigParams, runtimeParams, CanTpRxPduPtr);\r
}\r
- else\r
+ else{\r
DEBUG( DEBUG_MEDIUM, "Single frame received on ISO15765-Tx - is ignored!\n");\r
+ }\r
break;\r
}\r
case FIRST_FRAME: {\r
if (rxConfigParams != NULL) {\r
DEBUG( DEBUG_MEDIUM, "calling handleFirstFrame!\n");\r
handleFirstFrame(rxConfigParams, runtimeParams, CanTpRxPduPtr);\r
- } else\r
+ }else{\r
DEBUG( DEBUG_MEDIUM, "First frame received on ISO15765-Tx - is ignored!\n");\r
+ }\r
break;\r
}\r
case CONSECUTIVE_FRAME: {\r
if (rxConfigParams != NULL) {\r
DEBUG( DEBUG_MEDIUM, "calling handleConsecutiveFrame!\n");\r
handleConsecutiveFrame(rxConfigParams, runtimeParams, CanTpRxPduPtr);\r
- } else\r
+ } else {\r
DEBUG( DEBUG_MEDIUM, "Consecutive frame received on ISO15765-Tx - is ignored!\n");\r
+ }\r
break;\r
}\r
case FLOW_CONTROL_CTS_FRAME: {\r
if (txConfigParams != NULL) {\r
DEBUG( DEBUG_MEDIUM, "calling handleFlowControlFrame!\n");\r
handleFlowControlFrame(txConfigParams, runtimeParams, CanTpRxPduPtr);\r
- } else\r
+ } else {\r
DEBUG( DEBUG_MEDIUM, "Flow control frame received on ISO15765-Rx - is ignored!\n");\r
+ }\r
break;\r
}\r
case INVALID_FRAME: {\r
\r
// - - - - - - - - - - - - - -\r
\r
-#if (CANTP_VERSION_INFO_API == STD_ON)\r
-void CanTp_GetVersionInfo(Std_VersionInfoType* versionInfo) /** @req CANTP210 */\r
-{\r
- memcpy(versionInfo, &_CanTp_VersionInfo, sizeof(Std_VersionInfoType));\r
-}\r
-#endif /* DEM_VERSION_INFO_API */\r
-\r
-// - - - - - - - - - - - - - -\r
-\r
-void CanTp_TxConfirmation(PduIdType PduId) /** @req CANTP215 */ /** @req CANTP076 *//** @req CANTP215 */\r
+void CanTp_TxConfirmation(PduIdType CanTpTxPduId) /** @req CANTP076 */\r
{\r
const CanTp_RxNSduType *rxConfigParams = NULL;\r
const CanTp_TxNSduType *txConfigParams = NULL;\r
\r
VALIDATE_NO_RV( CanTpRunTimeData.internalState == CANTP_ON,\r
SERVICE_ID_CANTP_TX_CONFIRMATION, CANTP_E_UNINIT ); /** @req CANTP031 */\r
- VALIDATE_NO_RV( PduId < CANTP_NSDU_CONFIG_LIST_SIZE,\r
+ VALIDATE_NO_RV( CanTpTxPduId < CANTP_NSDU_CONFIG_LIST_SIZE,\r
SERVICE_ID_CANTP_TX_CONFIRMATION, CANTP_E_INVALID_TX_ID ); /** @req CANTP158 */\r
\r
/** @req CANTP236 */\r
- if ( CanTpConfig.CanTpNSduList[PduId].direction == IS015765_TRANSMIT ) {\r
- txConfigParams = (CanTp_TxNSduType*)&CanTpConfig.CanTpNSduList[PduId].configData;\r
+ if ( CanTpConfig.CanTpNSduList[CanTpTxPduId].direction == IS015765_TRANSMIT ) {\r
+ txConfigParams = (CanTp_TxNSduType*)&CanTpConfig.CanTpNSduList[CanTpTxPduId].configData;\r
CanTpRunTimeData.runtimeDataList[txConfigParams->CanTpTxChannel].iso15765.NasNarPending = FALSE;\r
+#if (CANTP_IMMEDIATE_TX_CONFIRMATION == STD_OFF)\r
+ CanTpRunTimeData.runtimeDataList[txConfigParams->CanTpTxChannel].iso15765.txConfirmed = TRUE;\r
+#endif\r
} else {\r
- rxConfigParams = (CanTp_RxNSduType*)&CanTpConfig.CanTpNSduList[PduId].configData;\r
+ rxConfigParams = (CanTp_RxNSduType*)&CanTpConfig.CanTpNSduList[CanTpTxPduId].configData;\r
CanTpRunTimeData.runtimeDataList[rxConfigParams->CanTpRxChannel].iso15765.NasNarPending = FALSE;\r
}\r
}\r
\r
// - - - - - - - - - - - - - -\r
\r
-void CanTp_Shutdown() /** @req CANTP202 *//** @req CANTP200 *//** @req CANTP211 *//** @req CANTP010 */\r
+void CanTp_Shutdown(void) /** @req CANTP202 *//** @req CANTP200 *//** @req CANTP010 */\r
{\r
VALIDATE_NO_RV( CanTpRunTimeData.internalState == CANTP_ON,\r
SERVICE_ID_CANTP_SHUTDOWN, CANTP_E_UNINIT ); /** @req CANTP031 */\r
// - - - - - - - - - - - - - -\r
\r
\r
-void CanTp_MainFunction() /** @req CANTP213 */\r
+void CanTp_MainFunction(void)\r
{\r
BufReq_ReturnType ret;\r
CanTpFifoQueueItem item;\r
case TX_WAIT_CAN_TP_TRANSMIT_CAN_TP_PROVIDE_TX_BUFFER:\r
{\r
TIMER_DECREMENT(txRuntimeListItem->iso15765.stateTimeoutCount); /** @req CANTP185 */\r
- if (txRuntimeListItem->iso15765.stateTimeoutCount == 0)\r
+ if (txRuntimeListItem->iso15765.stateTimeoutCount == 0){\r
PduR_CanTpTxConfirmation(txConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP204 *//** @req CANTP185 */\r
+ }\r
txRuntimeListItem->iso15765.state = IDLE;\r
txRuntimeListItem->mode = CANTP_TX_WAIT;\r
break;\r
handleConsecutiveFrameSent(txConfigListItem, txRuntimeListItem);\r
} else {\r
DEBUG( DEBUG_MEDIUM, "ERROR: Consecutive frame could not be sent!\n");\r
+ PduR_CanTpTxConfirmation(txConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP204 */\r
txRuntimeListItem->iso15765.state = IDLE;\r
txRuntimeListItem->mode = CANTP_TX_WAIT;\r
- PduR_CanTpTxConfirmation(txConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP204 */\r
}\r
} else {\r
DEBUG( DEBUG_MEDIUM, "Waiting for STmin timer to expire!\n");\r
TIMER_DECREMENT(txRuntimeListItem->iso15765.stateTimeoutCount);\r
if (txRuntimeListItem->iso15765.stateTimeoutCount == 0) {\r
DEBUG( DEBUG_MEDIUM, "State TX_WAIT_FLOW_CONTROL timed out!\n");\r
+ PduR_CanTpTxConfirmation(txConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP204 */ /** @req CANTP185 */\r
+ txRuntimeListItem->iso15765.state = IDLE;\r
+ txRuntimeListItem->mode = CANTP_TX_WAIT;\r
+ }\r
+ break;\r
+#if (CANTP_IMMEDIATE_TX_CONFIRMATION == STD_OFF)\r
+ case TX_WAIT_TX_CONFIRMATION:\r
+ if (txRuntimeListItem->iso15765.txConfirmed) {\r
+ PduR_CanTpTxConfirmation(txConfigListItem->PduR_PduId, NTFRSLT_OK); /** @req CANTP074 *//** @req CANTP09 *//** @req CANTP204 */\r
txRuntimeListItem->iso15765.state = IDLE;\r
txRuntimeListItem->mode = CANTP_TX_WAIT;\r
- PduR_CanTpTxConfirmation(txConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP204 */ /** @req CANTP185 */\r
}\r
break;\r
+#endif\r
default:\r
break;\r
}\r
TIMER_DECREMENT (rxRuntimeListItem->iso15765.stateTimeoutCount);\r
if (rxRuntimeListItem->iso15765.stateTimeoutCount == 0) {\r
DEBUG( DEBUG_MEDIUM, "TIMEOUT!\n");\r
+ PduR_CanTpRxIndication(rxConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK);\r
rxRuntimeListItem->iso15765.state = IDLE;\r
rxRuntimeListItem->mode = CANTP_RX_WAIT;\r
- PduR_CanTpRxIndication(rxConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK);\r
}\r
break;\r
}\r
rxRuntimeListItem->mode = CANTP_RX_WAIT;\r
}\r
} else if (ret == BUFREQ_NOT_OK ) {\r
+ PduR_CanTpRxIndication(rxConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP205 */\r
rxRuntimeListItem->iso15765.state = IDLE;\r
rxRuntimeListItem->mode = CANTP_RX_WAIT;\r
- PduR_CanTpRxIndication(rxConfigListItem->PduR_PduId, NTFRSLT_E_NOT_OK); /** @req CANTP205 */\r
} else if ( ret == BUFREQ_BUSY ) {\r
DEBUG( DEBUG_MEDIUM, "Still busy!\n");\r
}\r
//#include <stdio.h>\r
#include <string.h>\r
#include "Com.h"\r
-#include "Com_Types.h"\r
+#include "Com_Arc_Types.h"\r
+#include "Com_Internal.h"\r
+#include "Com_misc.h"\r
#include "debug.h"\r
\r
-#ifdef COM_DEV_ERROR_DETECT\r
-#include "Det.h"\r
-#endif\r
-\r
const Com_ConfigType * ComConfig;\r
\r
-Com_Arc_IPdu_type Com_Arc_IPdu[COM_N_IPDUS];\r
-Com_Arc_Signal_type Com_Arc_Signal[COM_N_SIGNALS];\r
-Com_Arc_GroupSignal_type Com_Arc_GroupSignal[COM_N_GROUP_SIGNALS];\r
-\r
-Com_Arc_Config_type Com_Arc_Config = {\r
- .ComIPdu = Com_Arc_IPdu,\r
- .ComSignal = Com_Arc_Signal,\r
- .ComGroupSignal = Com_Arc_GroupSignal\r
-};\r
-\r
\r
void Com_Init(const Com_ConfigType *config ) {\r
DEBUG(DEBUG_LOW, "--Initialization of COM--\n");\r
uint32 earliestDeadline;\r
uint32 firstTimeout;\r
\r
- Com_Arc_Config.OutgoingPdu.SduDataPtr = malloc(8);\r
-\r
// Initialize each IPdu\r
//ComIPdu_type *IPdu;\r
//Com_Arc_IPdu_type *Arc_IPdu;\r
const ComSignal_type *Signal;\r
const ComGroupSignal_type *GroupSignal;\r
- for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
+ for (uint16 i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
Com_Arc_Config.ComNIPdu++;\r
\r
- ComGetIPdu(i);\r
- ComGetArcIPdu(i);\r
+ const ComIPdu_type *IPdu = GET_IPdu(i);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(i);\r
\r
- if (i >= COM_MAX_NR_IPDU) {\r
+ if (i >= COM_N_IPDUS) {\r
DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_TOO_MANY_IPDU);\r
- assert(0);\r
failure = 1;\r
break;\r
}\r
\r
// If this is a TX and cyclic IPdu, configure the first deadline.\r
- if (IPdu->ComIPduDirection == SEND &&\r
- (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC || IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED)) {\r
+ if ( (IPdu->ComIPduDirection == SEND) &&\r
+ ( (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC) || (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED) )) {\r
//IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer = IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeTimeOffsetFactor;\r
}\r
\r
\r
// Reset earliest deadline.\r
- earliestDeadline = -1; // Gives the max value of uint32 due to overflow.\r
- firstTimeout = -1;\r
-\r
- // Reserve memory for all defined signals.\r
- Arc_IPdu->ComIPduDataPtr = malloc(IPdu->ComIPduSize);\r
- if (Arc_IPdu->ComIPduDataPtr == NULL) {\r
- failure = 1;\r
- }\r
+ earliestDeadline = 0xffffffffu;\r
+ firstTimeout = 0xffffffffu;\r
\r
// Initialize the memory with the default value.\r
if (IPdu->ComIPduDirection == SEND) {\r
}\r
\r
// For each signal in this PDU.\r
- Arc_IPdu->NComIPduSignalRef = 0;\r
- for (int j = 0; IPdu->ComIPduSignalRef != NULL && IPdu->ComIPduSignalRef[j] != NULL; j++) {\r
+ //Arc_IPdu->NComIPduSignalRef = 0;\r
+ for (uint16 j = 0; (IPdu->ComIPduSignalRef != NULL) && (IPdu->ComIPduSignalRef[j] != NULL) ; j++) {\r
Signal = IPdu->ComIPduSignalRef[j];\r
- ComGetArcSignal(Signal->ComHandleId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(Signal->ComHandleId);\r
\r
// If this signal already has been configured this is most likely an error.\r
if (Arc_Signal->ComIPduDataPtr != NULL) {\r
}\r
\r
// Increment helper counters\r
- Arc_IPdu->NComIPduSignalRef = j + 1;\r
+ //Arc_IPdu->NComIPduSignalRef = j + 1;\r
\r
Arc_Signal->ComIPduDataPtr = Arc_IPdu->ComIPduDataPtr;\r
Arc_Signal->ComIPduHandleId = i;\r
\r
// Clear update bits\r
if (Signal->ComSignalArcUseUpdateBit) {\r
- clearBit(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ CLEARBIT(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
}\r
\r
// If this signal is a signal group\r
if (Signal->Com_Arc_IsSignalGroup) {\r
- Arc_Signal->Com_Arc_ShadowBuffer = malloc(IPdu->ComIPduSize);\r
-\r
- if (Arc_Signal->Com_Arc_ShadowBuffer == NULL) {\r
- failure = 1;\r
- }\r
\r
// For each group signal of this signal group.\r
- for(int h = 0; Signal->ComGroupSignal[h] != NULL; h++) {\r
+ for(uint8 h = 0; Signal->ComGroupSignal[h] != NULL; h++) {\r
GroupSignal = Signal->ComGroupSignal[h];\r
- ComGetArcGroupSignal(GroupSignal->ComHandleId);\r
+ Com_Arc_GroupSignal_type *Arc_GroupSignal = GET_ArcGroupSignal(GroupSignal->ComHandleId);\r
// Set pointer to shadow buffer\r
Arc_GroupSignal->Com_Arc_ShadowBuffer = Arc_Signal->Com_Arc_ShadowBuffer;\r
// Initialize group signal data.\r
// Initialize signal data.\r
Com_WriteSignalDataToPdu(Signal->ComHandleId, Signal->ComSignalInitValue);\r
}\r
-\r
- // Check filter configuration\r
- if (IPdu->ComIPduDirection == RECEIVE) {\r
-\r
- // This represents an invalid configuration of the UINT8_N datatype\r
- if ((Signal->ComSignalType == UINT8_N\r
- &&\r
- (Signal->ComFilter.ComFilterAlgorithm == MASKED_NEW_EQUALS_X\r
- || Signal->ComFilter.ComFilterAlgorithm == MASKED_NEW_DIFFERS_X\r
- || Signal->ComFilter.ComFilterAlgorithm == MASKED_NEW_DIFFERS_MASKED_OLD\r
- || Signal->ComFilter.ComFilterAlgorithm == NEW_IS_WITHIN\r
- || Signal->ComFilter.ComFilterAlgorithm == NEW_IS_OUTSIDE\r
- || Signal->ComFilter.ComFilterAlgorithm == ONE_EVERY_N))) {\r
-\r
- DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_FILTER_CONFIGURATION);\r
- failure = 1;\r
- }\r
-\r
- // This represens an invalid configuration of the BOOLEAN datatype\r
- if ((Signal->ComSignalType == BOOLEAN\r
- &&\r
- (Signal->ComFilter.ComFilterAlgorithm == NEW_IS_WITHIN\r
- || Signal->ComFilter.ComFilterAlgorithm == NEW_IS_OUTSIDE))) {\r
-\r
-\r
- DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_FILTER_CONFIGURATION);\r
- failure = 1;\r
- }\r
- // Initialize filter values. COM230\r
- //signal.ComFilter.ComFilterNewValue = ComConfig->ComIPdu[i].ComTxIPdu.ComTxIPduUnusedAreasDefault;\r
- //signal.ComFilter.ComFilterOldValue = ComConfig->ComIPdu[i].ComTxIPdu.ComTxIPduUnusedAreasDefault;\r
- }\r
}\r
\r
// Configure per I-PDU based deadline monitoring.\r
- for (int j = 0; IPdu->ComIPduSignalRef != NULL && IPdu->ComIPduSignalRef[j] != NULL; j++) {\r
+ for (uint16 j = 0; (IPdu->ComIPduSignalRef != NULL) && (IPdu->ComIPduSignalRef[j] != NULL); j++) {\r
Signal = IPdu->ComIPduSignalRef[j];\r
- ComGetArcSignal(Signal->ComHandleId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(Signal->ComHandleId);\r
\r
- if (Signal->ComTimeoutFactor > 0 && !Signal->ComSignalArcUseUpdateBit) {\r
+ if ( (Signal->ComTimeoutFactor > 0) && (!Signal->ComSignalArcUseUpdateBit) ) {\r
Arc_Signal->ComTimeoutFactor = earliestDeadline;\r
Arc_Signal->Com_Arc_DeadlineCounter = firstTimeout;\r
}\r
\r
// An error occurred.\r
if (failure) {\r
- // Free allocated memory\r
- for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
- // Release memory for all defined signals.\r
- //free(ComConfig->ComIPdu[i].ComIPduDataPtr);\r
- }\r
DEBUG(DEBUG_LOW, "--Initialization of COM failed--\n");\r
//DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, 0x01, COM_E_INVALID_FILTER_CONFIGURATION);\r
} else {\r
}\r
\r
void Com_IpduGroupStart(Com_PduGroupIdType IpduGroupId,boolean Initialize) {\r
- for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
+ (void)Initialize; // Nothing to be done. This is just to avoid Lint warning.\r
+ for (uint16 i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
if (ComConfig->ComIPdu[i].ComIPduGroupRef == IpduGroupId) {\r
Com_Arc_Config.ComIPdu[i].Com_Arc_IpduStarted = 1;\r
}\r
}\r
\r
void Com_IpduGroupStop(Com_PduGroupIdType IpduGroupId) {\r
- for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
+ for (uint16 i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
if (ComConfig->ComIPdu[i].ComIPduGroupRef == IpduGroupId) {\r
Com_Arc_Config.ComIPdu[i].Com_Arc_IpduStarted = 0;\r
}\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#ifndef COM_ARC_TYPES_H_\r
+#define COM_ARC_TYPES_H_\r
\r
-\r
-\r
-\r
+#include "Std_Types.h"\r
+#include "Com_Types.h"\r
\r
\r
typedef struct {\r
\r
typedef struct {\r
\r
- Com_Arc_Filter_type ComFilter;\r
-\r
uint32 Com_Arc_DeadlineCounter;\r
uint32 ComTimeoutFactor;\r
void *ComIPduDataPtr;\r
\r
- uint8 ComIPduHandleId;\r
+ uint16 ComIPduHandleId;\r
uint8 ComSignalUpdated;\r
- //uint8 Com_Arc_EOL;\r
- //uint8 Com_Arc_IsSignalGroup;\r
\r
/* For signal groups */\r
void *Com_Arc_ShadowBuffer;\r
\r
typedef struct {\r
void *Com_Arc_ShadowBuffer;\r
- //uint8 ComIPduHandleId;\r
-\r
uint8 ComSignalUpdated;\r
uint8 Com_Arc_EOL;\r
} Com_Arc_GroupSignal_type;\r
\r
-\r
-/*\r
-typedef struct {\r
- void *Com_Arc_ShadowBuffer;\r
- void *Com_Arc_IPduDataPtr;\r
- uint8 Com_Arc_EOL;\r
-} Com_Arc_SignalGroup_type;\r
-*/\r
-\r
typedef struct {\r
uint8 ComTxIPduNumberOfRepetitionsLeft;\r
uint32 ComTxModeRepetitionPeriodTimer;\r
\r
Com_Arc_TxIPduTimer_type Com_Arc_TxIPduTimers;\r
void *ComIPduDataPtr;\r
-\r
- uint8 Com_Arc_NIPduSignalGroupRef;\r
-\r
- uint8 NComIPduSignalRef;\r
-\r
uint8 Com_Arc_IpduStarted;\r
-\r
} Com_Arc_IPdu_type;\r
\r
typedef struct {\r
uint16 ComNIPdu;\r
Com_Arc_IPdu_type *ComIPdu; // Only used in PduIdCheck()\r
- //Com_Arc_IPduGroup_type *ComIPduGroup;\r
Com_Arc_Signal_type *ComSignal;\r
- //Com_Arc_SignalGroup_type *ComSignalGroup;\r
Com_Arc_GroupSignal_type *ComGroupSignal;\r
PduInfoType OutgoingPdu;\r
} Com_Arc_Config_type;\r
+\r
+#endif\r
\r
#include <stdlib.h>\r
#include <string.h>\r
-#include "Com_Com.h"\r
+#include "Com_Arc_Types.h"\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
+#include "Com_misc.h"\r
#include "debug.h"\r
-#include "CanIf.h"\r
#include "PduR.h"\r
-#include "PduR_Com.h"\r
-#include "Byteorder.h"\r
+#include "Det.h"\r
+\r
\r
uint8 Com_SendSignal(Com_SignalIdType SignalId, const void *SignalDataPtr) {\r
- COM_VALIDATE_SIGNAL(SignalId, 0x0a, E_NOT_OK);\r
+ VALIDATE_SIGNAL(SignalId, 0x0a, E_NOT_OK);\r
// Store pointer to signal for easier coding.\r
- ComGetSignal(SignalId);\r
- ComGetArcSignal(SignalId);\r
- ComGetIPdu(Arc_Signal->ComIPduHandleId);\r
- ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ const ComSignal_type * Signal = GET_Signal(SignalId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(SignalId);\r
+ const ComIPdu_type *IPdu = GET_IPdu(Arc_Signal->ComIPduHandleId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
//DEBUG(DEBUG_LOW, "Com_SendSignal: id %d, nBytes %d, BitPosition %d, intVal %d\n", SignalId, nBytes, signal->ComBitPosition, (uint32)*(uint8 *)SignalDataPtr);\r
\r
\r
// If the signal has an update bit. Set it!\r
if (Signal->ComSignalArcUseUpdateBit) {\r
- setBit(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ SETBIT(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
}\r
\r
/*\r
}\r
\r
uint8 Com_ReceiveSignal(Com_SignalIdType SignalId, void* SignalDataPtr) {\r
- COM_VALIDATE_SIGNAL(SignalId, 0x0b, E_NOT_OK);\r
+ VALIDATE_SIGNAL(SignalId, 0x0b, E_NOT_OK);\r
DEBUG(DEBUG_LOW, "Com_ReceiveSignal: SignalId %d\n", SignalId);\r
\r
// Com_CopyFromSignal(&ComConfig->ComSignal[SignalId], SignalDataPtr);\r
}\r
\r
Std_ReturnType Com_TriggerTransmit(PduIdType ComTxPduId, uint8 *SduPtr) {\r
- PduIdCheck(ComTxPduId, 0x13, E_NOT_OK);\r
+ PDU_ID_CHECK(ComTxPduId, 0x13, E_NOT_OK);\r
/*\r
* COM260: This function must not check the transmission mode of the I-PDU\r
* since it should be possible to use it regardless of the transmission mode.\r
/*\r
* COM395: This function must override the IPdu callouts used in Com_TriggerIPduTransmit();\r
*/\r
- ComGetIPdu(ComTxPduId);\r
- ComGetArcIPdu(ComTxPduId);\r
+ const ComIPdu_type *IPdu = GET_IPdu(ComTxPduId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(ComTxPduId);\r
\r
memcpy(SduPtr, Arc_IPdu->ComIPduDataPtr, IPdu->ComIPduSize);\r
return E_OK;\r
}\r
\r
\r
+//lint -esym(904, Com_TriggerIPduSend) //PC-Lint Exception of rule 14.7\r
void Com_TriggerIPduSend(PduIdType ComTxPduId) {\r
- PduIdCheck(ComTxPduId, 0x17);\r
+ PDU_ID_CHECK(ComTxPduId, 0x17);\r
\r
//DEBUG(DEBUG_MEDIUM, "Com_TriggerIPduSend sending IPdu %d... ", ComTxPduId);\r
- ComGetIPdu(ComTxPduId);\r
- ComGetArcIPdu(ComTxPduId);\r
+ const ComIPdu_type *IPdu = GET_IPdu(ComTxPduId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(ComTxPduId);\r
\r
// Is the IPdu ready for transmission?\r
if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
// Send IPdu!\r
if (PduR_ComTransmit(IPdu->ArcIPduOutgoingId, &Com_Arc_Config.OutgoingPdu) == E_OK) {\r
// Clear all update bits for the contained signals\r
- for (int i = 0; i < Arc_IPdu->NComIPduSignalRef; i++) {\r
+ for (uint8 i = 0; (IPdu->ComIPduSignalRef != NULL) && (IPdu->ComIPduSignalRef[i] != NULL); i++) {\r
+ //for (int i = 0; i < Arc_IPdu->NComIPduSignalRef; i++) {\r
if (IPdu->ComIPduSignalRef[i]->ComSignalArcUseUpdateBit) {\r
- clearBit(Arc_IPdu->ComIPduDataPtr, IPdu->ComIPduSignalRef[i]->ComUpdateBitPosition);\r
+ CLEARBIT(Arc_IPdu->ComIPduDataPtr, IPdu->ComIPduSignalRef[i]->ComUpdateBitPosition);\r
}\r
}\r
}\r
}\r
}\r
\r
-Std_ReturnType Com_RxIndication(PduIdType ComRxPduId, const uint8* SduPtr) {\r
- PduIdCheck(ComRxPduId, 0x14, E_NOT_OK);\r
+//lint -esym(904, Com_RxIndication) //PC-Lint Exception of rule 14.7\r
+void Com_RxIndication(PduIdType ComRxPduId, const uint8* SduPtr) {\r
+ PDU_ID_CHECK(ComRxPduId, 0x14);\r
\r
- ComGetIPdu(ComRxPduId);\r
- ComGetArcIPdu(ComRxPduId);\r
+ const ComIPdu_type *IPdu = GET_IPdu(ComRxPduId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(ComRxPduId);\r
\r
// If Ipdu is stopped\r
if (!Arc_IPdu->Com_Arc_IpduStarted) {\r
- return E_OK;\r
+ return;\r
}\r
\r
// Check callout status\r
if (!IPdu->ComIPduCallout(ComRxPduId, SduPtr)) {\r
// TODO Report error to DET.\r
// Det_ReportError();\r
- return E_NOT_OK;\r
+ return;\r
}\r
}\r
\r
memcpy(Arc_IPdu->ComIPduDataPtr, SduPtr, IPdu->ComIPduSize);\r
\r
// For each signal.\r
- const ComSignal_type *signal;\r
- for (int i = 0; IPdu->ComIPduSignalRef[i] != NULL; i++) {\r
- signal = IPdu->ComIPduSignalRef[i];\r
- ComGetArcSignal(signal->ComHandleId);\r
+ const ComSignal_type *comSignal;\r
+ for (uint8 i = 0; IPdu->ComIPduSignalRef[i] != NULL; i++) {\r
+ comSignal = IPdu->ComIPduSignalRef[i];\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(comSignal->ComHandleId);\r
\r
// If this signal uses an update bit, then it is only considered if this bit is set.\r
- if (!signal->ComSignalArcUseUpdateBit ||\r
- (signal->ComSignalArcUseUpdateBit && testBit(Arc_IPdu->ComIPduDataPtr, signal->ComUpdateBitPosition))) {\r
+ if ( (!comSignal->ComSignalArcUseUpdateBit) ||\r
+ ( (comSignal->ComSignalArcUseUpdateBit) && (TESTBIT(Arc_IPdu->ComIPduDataPtr, comSignal->ComUpdateBitPosition)) ) ) {\r
\r
- if (signal->ComTimeoutFactor > 0) { // If reception deadline monitoring is used.\r
+ if (comSignal->ComTimeoutFactor > 0) { // If reception deadline monitoring is used.\r
// Reset the deadline monitoring timer.\r
- Arc_Signal->Com_Arc_DeadlineCounter = signal->ComTimeoutFactor;\r
+ Arc_Signal->Com_Arc_DeadlineCounter = comSignal->ComTimeoutFactor;\r
}\r
\r
- /*\r
- // Zero new filter value.\r
- IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterArcNewValue = 0;\r
-\r
- //Fix this!!!\r
- Com_CopyFromSignal(IPdu->ComIPduSignalRef[i], &IPdu->ComIPduSignalRef[i]->ComFilter.ComFilterArcNewValue);\r
- */\r
- // Perform filtering\r
- //if (Com_Filter(IPdu->ComIPduSignalRef[i])) {\r
-\r
- // Check the signal processing mode.\r
- if (IPdu->ComIPduSignalProcessing == IMMEDIATE) {\r
- // If signal processing mode is IMMEDIATE, notify the signal callback.\r
- if (IPdu->ComIPduSignalRef[i]->ComNotification != NULL) {\r
- IPdu->ComIPduSignalRef[i]->ComNotification();\r
- }\r
-\r
- } else {\r
- // Signal processing mode is DEFERRED, mark the signal as updated.\r
- Arc_Signal->ComSignalUpdated = 1;\r
+ // Check the signal processing mode.\r
+ if (IPdu->ComIPduSignalProcessing == IMMEDIATE) {\r
+ // If signal processing mode is IMMEDIATE, notify the signal callback.\r
+ if (IPdu->ComIPduSignalRef[i]->ComNotification != NULL) {\r
+ IPdu->ComIPduSignalRef[i]->ComNotification();\r
}\r
- //}\r
+\r
+ } else {\r
+ // Signal processing mode is DEFERRED, mark the signal as updated.\r
+ Arc_Signal->ComSignalUpdated = 1;\r
+ }\r
+\r
} else {\r
- DEBUG(DEBUG_LOW, "Com_RxIndication: Ignored signal %d of I-PD %d since its update bit was not set\n", signal->ComHandleId, ComRxPduId);\r
+ DEBUG(DEBUG_LOW, "Com_RxIndication: Ignored signal %d of I-PD %d since its update bit was not set\n", comSignal->ComHandleId, ComRxPduId);\r
}\r
}\r
\r
- return E_OK;\r
+ return;\r
}\r
\r
void Com_TxConfirmation(PduIdType ComTxPduId) {\r
- PduIdCheck(ComTxPduId, 0x15);\r
+ PDU_ID_CHECK(ComTxPduId, 0x15);\r
+ (void)ComTxPduId; // Nothing to be done. This is just to avoid Lint warning.\r
}\r
\r
\r
Std_ReturnType Com_SendSignalGroup(Com_SignalGroupIdType SignalGroupId) {\r
//#warning Com_SendSignalGroup should be performed atomically. Should we disable interrupts here?\r
- ComGetSignal(SignalGroupId);\r
- ComGetArcSignal(SignalGroupId);\r
- ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
- ComGetIPdu(Arc_Signal->ComIPduHandleId);\r
+ const ComSignal_type * Signal = GET_Signal(SignalGroupId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(SignalGroupId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ const ComIPdu_type *IPdu = GET_IPdu(Arc_Signal->ComIPduHandleId);\r
\r
\r
// Copy shadow buffer to Ipdu data space\r
const ComGroupSignal_type *groupSignal;\r
- for (int i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
+ for (uint8 i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
groupSignal = Signal->ComGroupSignal[i];\r
// TODO CopyData\r
// Com_CopyData(Arc_IPdu->ComIPduDataPtr, Arc_Signal->Com_Arc_ShadowBuffer, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
\r
// If the signal has an update bit. Set it!\r
if (Signal->ComSignalArcUseUpdateBit) {\r
- setBit(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
+ SETBIT(Arc_IPdu->ComIPduDataPtr, Signal->ComUpdateBitPosition);\r
}\r
\r
/*\r
\r
Std_ReturnType Com_ReceiveSignalGroup(Com_SignalGroupIdType SignalGroupId) {\r
//#warning Com_ReceiveSignalGroup should be performed atomically. Should we disable interrupts here?\r
- ComGetSignal(SignalGroupId);\r
- ComGetArcSignal(SignalGroupId);\r
+ const ComSignal_type * Signal = GET_Signal(SignalGroupId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(SignalGroupId);\r
\r
// Copy Ipdu data buffer to shadow buffer.\r
const ComGroupSignal_type *groupSignal;\r
- for (int i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
+ for (uint8 i = 0; Signal->ComGroupSignal[i] != NULL; i++) {\r
groupSignal = Signal->ComGroupSignal[i];\r
// TODO: CopyData\r
// Com_CopyData(Arc_Signal->Com_Arc_ShadowBuffer, Arc_IPdu->ComIPduDataPtr, groupSignal->ComBitSize, groupSignal->ComBitPosition, groupSignal->ComBitPosition);\r
}\r
\r
void Com_UpdateShadowSignal(Com_SignalIdType SignalId, const void *SignalDataPtr) {\r
- ComGetArcGroupSignal(SignalId);\r
+ Com_Arc_GroupSignal_type *Arc_GroupSignal = GET_ArcGroupSignal(SignalId);\r
// TODO: CopyData\r
// Com_CopyData(Arc_GroupSignal->Com_Arc_ShadowBuffer, SignalDataPtr, GroupSignal->ComBitSize, GroupSignal->ComBitPosition, 0);\r
Com_WriteSignalDataToPduBuffer(SignalId, TRUE, SignalDataPtr, (void *)Arc_GroupSignal->Com_Arc_ShadowBuffer);\r
}\r
\r
void Com_ReceiveShadowSignal(Com_SignalIdType SignalId, void *SignalDataPtr) {\r
- ComGetArcGroupSignal(SignalId);\r
+ Com_Arc_GroupSignal_type *Arc_GroupSignal = GET_ArcGroupSignal(SignalId);\r
// TODO: CopyData\r
// Com_CopyData(SignalDataPtr, Arc_GroupSignal->Com_Arc_ShadowBuffer, GroupSignal->ComBitSize, 0, GroupSignal->ComBitPosition);\r
Com_ReadSignalDataFromPduBuffer(SignalId, TRUE, SignalDataPtr, (void *)Arc_GroupSignal->Com_Arc_ShadowBuffer);\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * NB! This file is for COM internal use only and may only be included from COM C-files!\r
+ */\r
+\r
+\r
+\r
+#ifndef COM_INTERNAL_H_\r
+#define COM_INTERNAL_H_\r
+\r
+#include "Com_Arc_Types.h"\r
+\r
+extern const Com_ConfigType *ComConfig;\r
+extern Com_Arc_Config_type Com_Arc_Config;\r
+\r
+\r
+\r
+#ifdef COM_DEV_ERROR_DETECT\r
+#include "Det.h"\r
+\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)\r
+\r
+\r
+// Define macro for parameter check.\r
+#define PDU_ID_CHECK(PduId,ApiId,...) \\r
+ if (PduId >= Com_Arc_Config.ComNIPdu) { \\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_INVALID_PDU_ID); \\r
+ return __VA_ARGS__; \\r
+ } \\r
+\r
+#define VALIDATE_SIGNAL(SignalId, ApiId, ...) \\r
+ if (ComConfig->ComSignal[SignalId].Com_Arc_IsSignalGroup) { \\r
+ DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_ERROR_SIGNAL_IS_SIGNALGROUP); \\r
+ return __VA_ARGS__; \\r
+ } \\r
+\r
+\r
+#else\r
+\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+\r
+#define PDU_ID_CHECK(PduId,ApiId,...)\r
+#define VALIDATE_SIGNAL(PduId, ApiId, ...)\r
+#endif\r
+\r
+\r
+#define TESTBIT(source,bit) ( *( (uint8 *)source + (bit / 8) ) & (uint8)(1u << (bit % 8)) )\r
+#define SETBIT(dest,bit) ( *( (uint8 *)dest + (bit / 8) ) |= (uint8)(1u << (bit % 8)) )\r
+#define CLEARBIT(dest,bit) ( *( (uint8 *)dest + (bit / 8) ) &= (uint8)~(uint8)(1u << (bit % 8)) )\r
+\r
+\r
+#define GET_Signal(SignalId) \\r
+ (&ComConfig->ComSignal[SignalId])\r
+\r
+#define GET_ArcSignal(SignalId) \\r
+ (&Com_Arc_Config.ComSignal[SignalId])\r
+\r
+#define GET_IPdu(IPduId) \\r
+ (&ComConfig->ComIPdu[IPduId])\r
+\r
+#define GET_ArcIPdu(IPduId) \\r
+ (&Com_Arc_Config.ComIPdu[IPduId])\r
+\r
+#define GET_GroupSignal(GroupSignalId) \\r
+ (&ComConfig->ComGroupSignal[GroupSignalId])\r
+\r
+#define GET_ArcGroupSignal(GroupSignalId) \\r
+ (&Com_Arc_Config.ComGroupSignal[GroupSignalId])\r
+\r
+\r
+\r
+#endif /* COM_INTERNAL_H_ */\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#include "Com_RunTest.h"\r
-#include "Com.h"\r
-#include "debug.h"\r
-#include <stdlib.h>\r
-\r
-//#define DEBUG_LVL DEBUG_MEDIUM\r
-\r
-static uint8 RTE_ReceivedData[8] = {9,9,9,9,9,9,9,9};\r
-\r
-static void PrintReceivedData(int nBytes) {\r
- DEBUG(DEBUG_HIGH, "Received data: ");\r
- for (int i = 0; i < nBytes; i++) {\r
- DEBUG(DEBUG_HIGH, "%d ", RTE_ReceivedData[i]);\r
- }\r
- DEBUG(DEBUG_HIGH,"\n");\r
-}\r
-\r
-void RTE_Notification(void) {\r
- DEBUG(DEBUG_HIGH, "RTE received notification.");\r
-\r
- Com_ReceiveSignal(11, (void *)RTE_ReceivedData);\r
-\r
- PrintReceivedData(8);\r
-\r
- DEBUG(DEBUG_HIGH, "Received data (signal %d): %d\n", 11, (sint8)RTE_ReceivedData[0]);\r
-}\r
-\r
-uint8 SIL2value;\r
-uint8 SIL2quality;\r
-void RTE_SIL2MESSAGE() {\r
- Com_ReceiveSignalGroup(2);\r
- Com_ReceiveShadowSignal(0, &SIL2value);\r
- Com_ReceiveShadowSignal(1, &SIL2quality);\r
-\r
- DEBUG(DEBUG_HIGH, "SIL2 message received! value: %d, quality: %d\n", SIL2value, SIL2quality);\r
-}\r
-\r
-static uint16 newSpeed;\r
-static uint16 setNewSpeed = 0;\r
-void RTE_EngineChangeSpeed() {\r
- setNewSpeed = 1;\r
-}\r
-\r
-void RTE_EngineMain() {\r
- if (setNewSpeed) {\r
- Com_ReceiveSignal(1, (void *)&newSpeed);\r
-\r
- LDEBUG_PRINTF("Setting engine speed to %d rpm\n", newSpeed);\r
- /*\r
- static uint16 sig;\r
- sig = rand() % 10000;\r
- */\r
- Com_SendSignal(0, (void *)&newSpeed);\r
- setNewSpeed = 0;\r
- }\r
-}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef COM_RUNTEST_H_\r
-#define COM_RUNTEST_H_\r
-\r
-void RTE_Notification(void);\r
-void RTE_EngineMain(void);\r
-void RTE_EngineChangeSpeed(void);\r
-void RTE_SIL2MESSAGE(void);\r
-\r
-#endif /* COM_RUNTEST_H_ */\r
\r
\r
\r
-\r
-\r
-#include "Com_Sched.h"\r
+#include "Com_Arc_Types.h"\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
+#include "Com_misc.h"\r
#include <string.h>\r
#include "debug.h"\r
\r
} \\r
\r
\r
-void Com_MainFunctionRx() {\r
+\r
+void Com_MainFunctionRx(void) {\r
//DEBUG(DEBUG_MEDIUM, "Com_MainFunctionRx() excecuting\n");\r
const ComSignal_type *signal;\r
- for (int i = 0; !ComConfig->ComSignal[i].Com_Arc_EOL; i++) {\r
+ for (uint16 i = 0; !ComConfig->ComSignal[i].Com_Arc_EOL; i++) {\r
signal = &ComConfig->ComSignal[i];\r
- ComGetArcSignal(signal->ComHandleId);\r
- ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(signal->ComHandleId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
// Monitor signal reception deadline\r
- if (Arc_IPdu->Com_Arc_IpduStarted && Arc_Signal->ComTimeoutFactor > 0) {\r
+ if ( (Arc_IPdu->Com_Arc_IpduStarted) && (Arc_Signal->ComTimeoutFactor > 0) ) {\r
\r
// Decrease deadline monitoring timer.\r
timerDec(Arc_Signal->Com_Arc_DeadlineCounter);\r
}\r
\r
\r
-void Com_MainFunctionTx() {\r
+void Com_MainFunctionTx(void) {\r
//DEBUG(DEBUG_MEDIUM, "Com_MainFunctionTx() excecuting\n");\r
// Decrease timers.\r
const ComIPdu_type *IPdu;\r
- for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
+ for (uint16 i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
IPdu = &ComConfig->ComIPdu[i];\r
- ComGetArcIPdu(i);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(i);\r
\r
// Is this a IPdu that should be transmitted?\r
- if (IPdu->ComIPduDirection == SEND && Arc_IPdu->Com_Arc_IpduStarted) {\r
+ if ( (IPdu->ComIPduDirection == SEND) && (Arc_IPdu->Com_Arc_IpduStarted) ) {\r
// Decrease minimum delay timer\r
timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer);\r
\r
// If IPDU has periodic or mixed transmission mode.\r
- if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC\r
- || IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED) {\r
+ if ( (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == PERIODIC)\r
+ || (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED) ) {\r
\r
timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer);\r
\r
// Is it time for a direct transmission?\r
- if (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED\r
- && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) {\r
+ if ( (IPdu->ComTxIPdu.ComTxModeTrue.ComTxModeMode == MIXED)\r
+ && (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduNumberOfRepetitionsLeft > 0) ) {\r
\r
timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
\r
// Is it time for a transmission?\r
- if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer == 0\r
- && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ if ( (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer == 0)\r
+ && (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) ) {\r
\r
Com_TriggerIPduSend(i);\r
\r
}\r
\r
// Is it time for a cyclic transmission?\r
- if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer == 0 && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ if ( (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeTimePeriodTimer == 0) && (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) ) {\r
\r
Com_TriggerIPduSend(i);\r
\r
timerDec(Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer);\r
\r
// Is it time for a transmission?\r
- if (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer == 0 && Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) {\r
+ if ( (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxModeRepetitionPeriodTimer == 0) && (Arc_IPdu->Com_Arc_TxIPduTimers.ComTxIPduMinimumDelayTimer == 0) ) {\r
Com_TriggerIPduSend(i);\r
\r
// Reset periodic timer\r
}\r
}\r
}\r
-\r
- // Send scheduled packages.\r
- // Cyclic\r
- for (int i = 0; !ComConfig->ComIPdu[i].Com_Arc_EOL; i++) {\r
- if (ComConfig->ComIPdu[i].ComIPduDirection == SEND) {\r
-\r
- }\r
- }\r
}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-extern Com_ConfigType ComConfig_TEST;\r
-\r
-extern const PduR_PBConfigType PduRConfigData_TEST[];\r
-\r
-\r
-PduR_StdRTableType PduRConfigData_TEST = {\r
- .TargetPduId = 0,\r
- .NRoutingPaths = 6,\r
- .RoutingTable = {\r
- {\r
- .FctPtrs = &PduR_StdLinFctPtrs,\r
- .DestPduId = 0,\r
- .SduLength = 2,\r
- .DataProvision = PDUR_DIRECT,\r
- .BufferDepth = 3,\r
- },\r
- {\r
- .FctPtrs = &PduR_StdLinFctPtrs,\r
- .DestPduId = 1,\r
- .SduLength = 8,\r
- .DataProvision = PDUR_NO_PROVISION,\r
- },\r
- {\r
- .FctPtrs = &PduR_StdLinFctPtrs,\r
- .DestPduId = 2,\r
- .SduLength = 8,\r
- .DataProvision = PDUR_TRIGGER_TRANSMIT,\r
- .BufferDepth = 3,\r
- },\r
- {\r
- .FctPtrs = &PduR_StdLinFctPtrs,\r
- .DestPduId = 3,\r
- .SduLength = 8,\r
- .DataProvision = PDUR_DIRECT,\r
- .PduR_GatewayMode = 1,\r
- .BufferDepth = 4,\r
- },\r
-\r
- /* Gateway mode between lin interfaces but without buffers inbetween */\r
- {\r
- .FctPtrs = &PduR_StdLinFctPtrs,\r
- .DestPduId = 4,\r
- .SduLength = 8,\r
- .DataProvision = PDUR_NO_PROVISION,\r
- .PduR_GatewayMode = 1,\r
- },\r
-\r
- /* Gateway mode between lin interfaces using trigger transmit data provision */\r
- {\r
- .FctPtrs = &PduR_StdLinFctPtrs,\r
- .DestPduId = 5,\r
- .SduLength = 8,\r
- .DataProvision = PDUR_TRIGGER_TRANSMIT,\r
- .PduR_GatewayMode = 1,\r
- .BufferDepth = 4,\r
- },\r
- }\r
-};\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef COM_TESTDATA_H_\r
-#define COM_TESTDATA_H_\r
-\r
-extern Com_ConfigType ComConfig_TEST;\r
-\r
-extern const PduR_PBConfigType PduRConfigData_TEST[];\r
-\r
-#endif /* COM_TESTDATA_H_ */\r
\r
\r
\r
-\r
-\r
-\r
-#include <stdlib.h>\r
#include <string.h>\r
+\r
+#include "Com_Arc_Types.h"\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
#include "Com_misc.h"\r
\r
\r
+\r
void Com_ReadSignalDataFromPdu(\r
const Com_SignalIdType signalId,\r
void *signalData) {\r
\r
// Get PDU\r
- ComGetSignal(signalId);\r
- ComGetArcSignal(Signal->ComHandleId);\r
- ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ const ComSignal_type * Signal = GET_Signal(signalId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(Signal->ComHandleId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
// Get data\r
Com_ReadSignalDataFromPduBuffer(\r
void *signalData) {\r
\r
// Get PDU\r
- ComGetSignal(parentSignalId);\r
- ComGetArcSignal(Signal->ComHandleId);\r
- ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ const ComSignal_type * Signal = GET_Signal(parentSignalId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(Signal->ComHandleId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
// Get data\r
Com_ReadSignalDataFromPduBuffer(\r
uint8 bitSize;\r
\r
if (!isGroupSignal) {\r
- ComGetSignal(signalId);\r
+ const ComSignal_type * Signal = GET_Signal(signalId);\r
signalType = Signal->ComSignalType;\r
signalEndianess = Signal->ComSignalEndianess;\r
signalLength = Signal->ComBitSize / 8;\r
bitPosition = Signal->ComBitPosition;\r
bitSize = Signal->ComBitSize;\r
} else {\r
- ComGetGroupSignal(signalId);\r
+ const ComGroupSignal_type *GroupSignal = GET_GroupSignal(signalId);\r
signalType = GroupSignal->ComSignalType;\r
signalEndianess = GroupSignal->ComSignalEndianess;\r
signalLength = GroupSignal->ComBitSize / 8;\r
\r
// Pointer to a byte of the source and dest respectively.\r
uint8 *signalDataBytes = (uint8 *)signalData;\r
- uint8 *pduBufferBytes = (uint8 *)pduBuffer;\r
+ const uint8 *pduBufferBytes = (const uint8 *)pduBuffer;\r
uint8 startBitOffset = 0;\r
\r
if (signalEndianess != CPU_ENDIANESS) {\r
// Swap source bytes before reading\r
// TODO: Must adapt to larger PDUs!\r
uint8 pduBufferBytes_swap[8];\r
- int i = 0;\r
- for (i = 0; i < 8; ++i) {\r
+ for (uint8 i = 0; i < 8; ++i) {\r
pduBufferBytes_swap[i] = pduBufferBytes[7 - i];\r
}\r
startBitOffset = intelBitNrToPduOffset(bitPosition, bitSize, 64);\r
+ //lint -save -esym(960,12.5) PC-Lint Exception: OK. PC-Lint Wrong interpretation of MISRA rule 12.5.\r
Com_ReadDataSegment(\r
signalDataBytes, pduBufferBytes_swap, destSize,\r
startBitOffset, bitSize,\r
SignalTypeSignedness(signalType));\r
-\r
+ //lint -restore\r
} else {\r
startBitOffset = motorolaBitNrToPduOffset(bitPosition);\r
Com_ReadDataSegment(\r
const void *signalData) {\r
\r
// Get PDU\r
- ComGetSignal(signalId);\r
- ComGetArcSignal(Signal->ComHandleId);\r
- ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ const ComSignal_type * Signal = GET_Signal(signalId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(Signal->ComHandleId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
// Get data\r
Com_WriteSignalDataToPduBuffer(\r
const void *signalData) {\r
\r
// Get PDU\r
- ComGetSignal(parentSignalId);\r
- ComGetArcSignal(Signal->ComHandleId);\r
- ComGetArcIPdu(Arc_Signal->ComIPduHandleId);\r
+ const ComSignal_type * Signal = GET_Signal(parentSignalId);\r
+ Com_Arc_Signal_type * Arc_Signal = GET_ArcSignal(Signal->ComHandleId);\r
+ Com_Arc_IPdu_type *Arc_IPdu = GET_ArcIPdu(Arc_Signal->ComIPduHandleId);\r
\r
// Get data\r
Com_WriteSignalDataToPduBuffer(\r
uint8 bitSize;\r
\r
if (!isGroupSignal) {\r
- ComGetSignal(signalId);\r
+ const ComSignal_type * Signal = GET_Signal(signalId);\r
signalType = Signal->ComSignalType;\r
signalLength = Signal->ComBitSize / 8;\r
bitPosition = Signal->ComBitPosition;\r
bitSize = Signal->ComBitSize;\r
} else {\r
- ComGetGroupSignal(signalId);\r
+ const ComGroupSignal_type *GroupSignal = GET_GroupSignal(signalId);\r
signalType = GroupSignal->ComSignalType;\r
signalLength = GroupSignal->ComBitSize / 8;\r
bitPosition = GroupSignal->ComBitPosition;\r
}\r
\r
\r
- uint8 *signalDataBytes = (uint8 *)signalData;\r
+ const uint8 *signalDataBytes = (const uint8 *)signalData;\r
uint8 *pduBufferBytes = (uint8 *)pduBuffer;\r
uint8 startBitOffset = motorolaBitNrToPduOffset(bitPosition);\r
uint8 signalBufferSize = SignalTypeToSize(signalType, signalLength);\r
Com_WriteDataSegment(pduBufferBytes, signalDataBytes, signalBufferSize, startBitOffset, bitSize);\r
}\r
\r
-uint8 Com_Filter(ComSignal_type *signal) {\r
- ComGetArcSignal(signal->ComHandleId);\r
- const ComFilter_type * filter = &signal->ComFilter;\r
- uint8 success = 0;\r
- if (filter->ComFilterAlgorithm == ALWAYS) {\r
- success = 1;\r
-\r
- } else if (filter->ComFilterAlgorithm == NEVER) {\r
- success = 0;\r
-\r
- } else if (filter->ComFilterAlgorithm == ONE_EVERY_N) {\r
- // Treat the special cases that should not exists.\r
- if (filter->ComFilterPeriodFactor < 2) {\r
- // If PeriodFactor is 0 then every package is discarded.\r
- // If PeriodFactor is 1 then every package is passed through.\r
- success = filter->ComFilterPeriodFactor;\r
-\r
- } else {\r
- if (filter->ComFilterArcN == 0) {\r
- success = 1;\r
- } else {\r
- success = 0;\r
- }\r
- Arc_Signal->ComFilter.ComFilterArcN++;\r
- if (filter->ComFilterArcN >= filter->ComFilterPeriodFactor) {\r
- Arc_Signal->ComFilter.ComFilterArcN = 0;\r
- }\r
- }\r
-\r
- } else if (filter->ComFilterAlgorithm == NEW_IS_OUTSIDE) {\r
- if ((filter->ComFilterMin > filter->ComFilterArcNewValue)\r
- || (filter->ComFilterArcNewValue > filter->ComFilterMax)) {\r
- success = 1;\r
- } else {\r
- success = 0;\r
- }\r
-\r
-\r
- } else if (filter->ComFilterAlgorithm == NEW_IS_WITHIN) {\r
- if (filter->ComFilterMin <= filter->ComFilterArcNewValue\r
- && filter->ComFilterArcNewValue <= filter->ComFilterMax) {\r
- success = 1;\r
- } else {\r
- success = 0;\r
- }\r
-\r
-\r
- } else if (filter->ComFilterAlgorithm == MASKED_NEW_DIFFERS_MASKED_OLD) {\r
- if ((filter->ComFilterArcNewValue & filter->ComFilterMask)\r
- != (filter->ComFilterArcNewValue & filter->ComFilterMask)) {\r
- success = 1;\r
- } else {\r
- success = 0;\r
- }\r
-\r
- } else if (filter->ComFilterAlgorithm == MASKED_NEW_DIFFERS_X) {\r
- if ((filter->ComFilterArcNewValue & filter->ComFilterMask) != filter->ComFilterX) {\r
- success = 1;\r
- } else {\r
- success = 0;\r
- }\r
-\r
- } else if (filter->ComFilterAlgorithm == MASKED_NEW_EQUALS_X) {\r
- if ((filter->ComFilterArcNewValue & filter->ComFilterMask) == filter->ComFilterX) {\r
- success = 1;\r
- } else {\r
- success = 0;\r
- }\r
- }\r
-\r
- if (success) {\r
- Arc_Signal->ComFilter.ComFilterArcOldValue = filter->ComFilterArcNewValue;\r
- return 1;\r
- } else return 0;\r
-}\r
-\r
\r
/*\r
* Read an arbitrary signal segment from buffer.\r
\r
boolean negative;\r
\r
- if ( signedOutput && (*(source + sourceStartByte) & (0x80 >> segmentStartBitOffsetInsideByte)) ) {\r
+ if ( signedOutput && (*(source + sourceStartByte) & (0x80u >> segmentStartBitOffsetInsideByte)) ) {\r
negative = TRUE;\r
- sourceStartByteMask = (0xFF00 >> segmentStartBitOffsetInsideByte);\r
+ sourceStartByteMask = (0xFF00u >> segmentStartBitOffsetInsideByte);\r
memset(dest, 0xFF, destByteLength);\r
} else {\r
negative = FALSE;\r
- sourceStartByteMask = (0x00FF >> segmentStartBitOffsetInsideByte);\r
- memset(dest, 0x00, destByteLength);\r
+ sourceStartByteMask = (0x00FFu >> segmentStartBitOffsetInsideByte);\r
+ memset(dest, 0x00u, destByteLength);\r
}\r
\r
// setup to point to end (LSB) of buffers\r
if (negative) {\r
// compiles and writes one destination byte on each iteration\r
do {\r
- shiftReg = *(source - sourceByteNr) | 0xFF00; // read source byte (already matching "byte space")\r
+ shiftReg = *(source - sourceByteNr) | 0xFF00u; // read source byte (already matching "byte space")\r
if (sourceByteNr == sourceByteLength) { // if we are on the last source byte..\r
shiftReg |= sourceStartByteMask; // ..we need to mask out stuff we don't want\r
}\r
shiftReg >>= sourceAlignmentShift; // shift down to align\r
- *(dest - destByteNr) &= shiftReg | 0xFF00; // write into destination byte\r
+ *(dest - destByteNr) &= shiftReg | 0xFF00u; // write into destination byte\r
\r
sourceByteNr++; // move to next source byte\r
- if (sourceAlignmentShift != 0 // do we have more bits for current dest. byte in this source byte?\r
- && sourceByteNr <= sourceByteLength) {\r
- shiftReg = *(source - sourceByteNr) | 0xFF00; // read next source byte\r
+ if ( (sourceAlignmentShift != 0) // do we have more bits for current dest. byte in this source byte?\r
+ && (sourceByteNr <= sourceByteLength) ) {\r
+ shiftReg = *(source - sourceByteNr) | 0xFF00u; // read next source byte\r
if (sourceByteNr == sourceByteLength) { // if we are on the last source byte..\r
shiftReg |= sourceStartByteMask; // ..we need to mask out stuff we don't want\r
}\r
- shiftReg = ~(shiftReg); // shifting inverted to shift in 1:s\r
+ shiftReg = (uint16)~(shiftReg); // shifting inverted to shift in 1:s\r
shiftReg <<= 8; // shift up (to match destination "byte space")\r
- shiftReg = ~(shiftReg);\r
+ shiftReg = (uint16)~shiftReg;\r
shiftReg >>= sourceAlignmentShift; // shift down to align\r
- *(dest - destByteNr) &= shiftReg | 0xFF00; // write into destination byte\r
+ *(dest - destByteNr) &= shiftReg | 0xFF00u; // write into destination byte\r
}\r
destByteNr++;\r
} while (destByteNr < segmentByteLength);\r
} else { // positive\r
do {\r
- shiftReg = *(source - sourceByteNr) & 0x00FF; // read source byte (already matching "byte space")\r
+ shiftReg = *(source - sourceByteNr) & 0x00FFu; // read source byte (already matching "byte space")\r
if (sourceByteNr == sourceByteLength) { // if we are on the last source byte..\r
shiftReg &= sourceStartByteMask; // ..we need to mask out stuff we don't want\r
}\r
shiftReg >>= sourceAlignmentShift; // shift down to align\r
- *(dest - destByteNr) |= shiftReg & 0x00FF; // write into destination byte\r
+ *(dest - destByteNr) |= shiftReg & 0x00FFu; // write into destination byte\r
\r
sourceByteNr++; // move to next source byte\r
if (sourceAlignmentShift != 0 // do we have more bits for current dest. byte in this source byte?\r
&& sourceByteNr <= sourceByteLength) {\r
- shiftReg = *(source - sourceByteNr) & 0x00FF; // read next source byte\r
+ shiftReg = *(source - sourceByteNr) & 0x00FFu; // read next source byte\r
if (sourceByteNr == sourceByteLength) { // if we are on the last source byte..\r
shiftReg &= sourceStartByteMask; // ..we need to mask out stuff we don't want\r
}\r
shiftReg <<= 8; // shift up (to match destination "byte space")\r
shiftReg >>= sourceAlignmentShift; // shift down to align\r
- *(dest - destByteNr) |= shiftReg & 0x00FF; // write into destination byte\r
+ *(dest - destByteNr) |= shiftReg & 0x00FFu; // write into destination byte\r
}\r
destByteNr++;\r
} while (destByteNr < segmentByteLength);\r
\r
/*\r
* Copies the <segmentBitLength> least significant bits from <signal> into <pdu>.\r
- * The bit segment is placed in <pdu> som that the most significant bit ends up\r
+ * The bit segment is placed in <pdu> so that the most significant bit ends up\r
* at <segmentStartBitOffset> from the msb of <pdu>.\r
*/\r
-void Com_WriteDataSegment(uint8 *pdu, const uint8 *signal, uint8 destByteLength,\r
+void Com_WriteDataSegment(uint8 *pdu, const uint8 *signalDataPtr, uint8 destByteLength,\r
uint8 segmentStartBitOffset, uint8 segmentBitLength) {\r
uint8 pduEndBitOffset = segmentStartBitOffset + segmentBitLength - 1;\r
uint8 pduStartByte = segmentStartBitOffset / 8;\r
uint8 pduByteLength = pduEndByte - pduStartByte;\r
\r
uint8 segmentStartBitOffsetInsideByte = segmentStartBitOffset % 8;\r
- uint8 pduStartByteMask = (0xFF >> segmentStartBitOffsetInsideByte);\r
+ uint8 pduStartByteMask = (0xFFu >> segmentStartBitOffsetInsideByte);\r
\r
uint8 pduAlignmentShift = 7 - (pduEndBitOffset % 8);\r
uint8 segmentByteLength = 1 + (segmentBitLength - 1) / 8;\r
\r
// setup to point to end (LSB) of buffers\r
pdu += pduEndByte;\r
- signal += destByteLength - 1;\r
+ signalDataPtr += destByteLength - 1;\r
\r
// splits and writes one source byte on each iteration\r
do {\r
- shiftReg = *(signal - signalByteNr) & 0x00FF;\r
+ shiftReg = *(signalDataPtr - signalByteNr) & 0x00FFu;\r
clearReg = 0x00FF;\r
+ //lint -save -e701 -e734 //PC-Lint Wrong interpretation of MISRA rule 10.5.\r
shiftReg <<= pduAlignmentShift;\r
clearReg <<= pduAlignmentShift;\r
+ //lint -restore\r
if (pduByteNr == pduByteLength) {\r
shiftReg &= pduStartByteMask;\r
clearReg &= pduStartByteMask;\r
}\r
- *(pdu - pduByteNr) &= ~(clearReg & 0x00FF);\r
- *(pdu - pduByteNr) |= shiftReg & 0x00FF;\r
+ *(pdu - pduByteNr) &= (uint16)~(clearReg & 0x00FFu);\r
+ *(pdu - pduByteNr) |= shiftReg & 0x00FFu;\r
\r
pduByteNr++;\r
- if (pduAlignmentShift != 0\r
- && pduByteNr <= pduByteLength) {\r
- shiftReg = *(signal - signalByteNr) & 0x00FF;\r
+ if ( (pduAlignmentShift != 0)\r
+ && (pduByteNr <= pduByteLength) ) {\r
+ shiftReg = *(signalDataPtr - signalByteNr) & 0x00FFu;\r
clearReg = 0x00FF;\r
+ //lint -save -e701 -e734 //PC-Lint Wrong interpretation of MISRA rule 10.5.\r
shiftReg <<= pduAlignmentShift;\r
clearReg <<= pduAlignmentShift;\r
shiftReg >>= 8;\r
clearReg >>= 8;\r
+ //lint -restore\r
if (pduByteNr == pduByteLength) {\r
shiftReg &= pduStartByteMask;\r
clearReg &= pduStartByteMask;\r
}\r
- *(pdu - pduByteNr) &= ~(clearReg & 0x00FF);\r
- *(pdu - pduByteNr) |= shiftReg & 0x00FF;\r
+ *(pdu - pduByteNr) &= (uint16)~(clearReg & 0x00FFu);\r
+ *(pdu - pduByteNr) |= shiftReg & 0x00FFu;\r
}\r
signalByteNr++;\r
} while (signalByteNr < segmentByteLength);\r
*/\r
uint8 motorolaBitNrToPduOffset (uint8 motorolaBitNr) {\r
uint8 byte = motorolaBitNr / 8;\r
+ uint8 offsetToByteStart = (uint8) (byte * 8u);\r
uint8 offsetInsideByte = motorolaBitNr % 8;\r
- return byte * 8 + (7 - offsetInsideByte);\r
+ return (uint8) (offsetToByteStart + (7u - offsetInsideByte));\r
}\r
\r
/*\r
* intelBitNr (after PDU byte-swap): 39 38 37 36 35 34 33 32 31 ... 3 2 1 0\r
* intelBitNrToPduOffset: 0 1 2 3 4 5 6 7 8 ... 36 37 38 39\r
*/\r
-uint8 intelBitNrToPduOffset (uint8 intelBitNr, uint8 segmentBitLength, uint8 pduBitLenght) {\r
- return pduBitLenght - (intelBitNr + segmentBitLength);\r
+uint8 intelBitNrToPduOffset (uint8 intelBitNr, uint8 segmentBitLength, uint8 pduBitLength) {\r
+ return pduBitLength - (intelBitNr + segmentBitLength);\r
}\r
#ifndef COM_MISC_H_\r
#define COM_MISC_H_\r
\r
-#include "Com.h"\r
-/*\r
- * The following function are exported only for testing purposes.\r
- */\r
-uint8 Com_Filter(ComSignal_type *signal);\r
+\r
\r
// Read data from PDU\r
void Com_ReadSignalDataFromPdu(\r
void Com_ReadDataSegment(uint8 *dest, const uint8 *source, uint8 destByteLength,\r
uint8 segmentStartBitOffset, uint8 segmentBitLength, boolean signedOutput);\r
\r
-void Com_WriteDataSegment(uint8 *pdu, const uint8 *signal, uint8 destByteLength,\r
+void Com_WriteDataSegment(uint8 *pdu, const uint8 *signalDataPtr, uint8 destByteLength,\r
uint8 segmentStartBitOffset, uint8 segmentBitLength);\r
\r
uint8 motorolaBitNrToPduOffset (uint8 motorolaBitNr);\r
-uint8 intelBitNrToPduOffset (uint8 intelBitNr, uint8 segmentBitLength, uint8 pduBitLenght);\r
+uint8 intelBitNrToPduOffset (uint8 intelBitNr, uint8 segmentBitLength, uint8 pduBitLength);\r
\r
\r
#endif /* COM_MISC_H_ */\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+//lint -emacro(904,COMM_VALIDATE_INIT,COMM_VALIDATE_CHANNEL,COMM_VALIDATE_USER,COMM_VALIDATE_PARAMETER) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
\r
+/* Globally fulfilled requirements */\r
+/** @req COMM43 */\r
+/** @req COMM38 */\r
+/** @req COMM463.partially */\r
+/** @req COMM686 */\r
+/** @req COMM51 */\r
+/** @req COMM191 */\r
+/** @req COMM301 */\r
+/** @req COMM488 */\r
+/** @req COMM599 */\r
+/** @req COMM509 */\r
+/** @req COMM269 */\r
+/** @req COMM458 */\r
+/** @req COMM640 */\r
+/** @req COMM459 */\r
+/** @req COMM462 */\r
+/** @req COMM457.bswbuilder */\r
+/** @req COMM419.bswbuilder */\r
+/** @req COMM460.bswbuilder */\r
+/** @req COMM549.bswbuilder */\r
+/** @req COMM464 */\r
\r
+#include <string.h>\r
+#include "ComM.h"\r
+#include "ComM_Dcm.h"\r
+#include "ComM_EcuM.h"\r
+#if (COMM_DEV_ERROR_DETECT == STD_ON)\r
+#include "Det.h"\r
+#endif\r
\r
+/** @req COMM507 @req COMM508 */\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
\r
+#include "ComM_BusSm.h"\r
+#include "ComM_Internal.h"\r
\r
+/** @req COMM506 @req COMM353 */\r
+#include "CanSM.h"\r
\r
+/** @req COMM347 */\r
+#if defined(USE_NM) || defined(COMM_TESTS)\r
+#include "Nm.h"\r
+#endif\r
\r
+static ComM_InternalType ComM_Internal = {\r
+ .InitStatus = COMM_UNINIT,\r
+ .InhibitCounter = 0,\r
+#if (COMM_NO_COM == STD_ON)\r
+ .NoCommunication = TRUE,\r
+#else\r
+ .NoCommunication = FALSE,\r
+#endif\r
+};\r
\r
-#include "ComM.h"\r
-#include "ComM_BusSm.h"\r
+static const ComM_ConfigType * ComM_Config;\r
+\r
+\r
+void ComM_Init(const ComM_ConfigType * Config ){\r
+ COMM_VALIDATE_PARAMETER( (Config != NULL), COMM_SERVICEID_INIT);\r
+ COMM_VALIDATE_PARAMETER( (Config->Channels != NULL), COMM_SERVICEID_INIT);\r
+ COMM_VALIDATE_PARAMETER( (Config->Users != NULL), COMM_SERVICEID_INIT);\r
+\r
+ ComM_Config = Config;\r
+\r
+ for (uint8 i = 0; i < COMM_CHANNEL_COUNT; ++i) {\r
+ ComM_Internal.Channels[i].Mode = COMM_NO_COMMUNICATION; /**< @req COMM485 */\r
+ ComM_Internal.Channels[i].SubMode = COMM_SUBMODE_NONE;\r
+ ComM_Internal.Channels[i].UserRequestMask = 0;\r
+ ComM_Internal.Channels[i].InhibitionStatus = COMM_INHIBITION_STATUS_NONE;\r
+ ComM_Internal.Channels[i].NmIndicationMask = COMM_NM_INDICATION_NONE;\r
+ }\r
+\r
+ for (uint8 i = 0; i < COMM_USER_COUNT; ++i) {\r
+ ComM_Internal.Users[i].RequestedMode = COMM_NO_COMMUNICATION;\r
+ }\r
+\r
+ ComM_Internal.InhibitCounter = 0;\r
+ ComM_Internal.InitStatus = COMM_INIT;\r
+ /** @req COMM313 */\r
+}\r
+\r
+void ComM_DeInit(){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_DEINIT);\r
+\r
+ ComM_Internal.InitStatus = COMM_UNINIT;\r
+}\r
+\r
+Std_ReturnType ComM_GetStatus( ComM_InitStatusType* Status ){\r
+ COMM_VALIDATE_PARAMETER( (Status != NULL), COMM_SERVICEID_GETSTATUS, E_NOT_OK);\r
+\r
+ *Status = ComM_Internal.InitStatus;\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType ComM_GetInhibitionStatus( NetworkHandleType Channel, ComM_InhibitionStatusType* Status ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_GETINHIBITIONSTATUS, COMM_E_UNINIT);\r
+\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+ *Status = ChannelInternal->InhibitionStatus;\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType ComM_RequestComMode( ComM_UserHandleType User, ComM_ModeType ComMode ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_REQUESTCOMMODE, COMM_E_UNINIT);\r
+ COMM_VALIDATE_USER(User, COMM_SERVICEID_REQUESTCOMMODE, E_NOT_OK);\r
+ /** @req COMM151 */\r
+ COMM_VALIDATE_PARAMETER((ComMode != COMM_SILENT_COMMUNICATION), COMM_SERVICEID_REQUESTCOMMODE, E_NOT_OK);\r
+\r
+ return ComM_Internal_RequestComMode(User, ComMode);\r
+}\r
+\r
+static Std_ReturnType ComM_Internal_RequestComMode(\r
+ ComM_UserHandleType User, ComM_ModeType ComMode ){\r
+\r
+ const ComM_UserType* UserConfig = &ComM_Config->Users[User];\r
+ ComM_Internal_UserType* UserInternal = &ComM_Internal.Users[User];\r
+\r
+ UserInternal->RequestedMode = ComMode; /**< @req COMM471 @req COMM500 @req COMM92 */\r
+ uint32 userMask = (1LU << User);\r
+\r
+ Std_ReturnType requestStatus = E_OK;\r
+\r
+ /* Go through users channels. Relay to SMs. Collect overall success status */\r
+ for (uint8 i = 0; i < UserConfig->ChannelCount; ++i) {\r
+ const ComM_ChannelType* Channel = UserConfig->ChannelList[i];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel->Number];\r
+\r
+ /** @req COMM784.1 @req COMM304 @req COMM625 */\r
+ // Put user request into mask\r
+ if (ComMode == COMM_NO_COMMUNICATION) {\r
+ ChannelInternal->UserRequestMask &= ~(userMask);\r
+ } else if (ComMode == COMM_FULL_COMMUNICATION) {\r
+ ChannelInternal->UserRequestMask |= userMask;\r
+ } else {\r
+ //Nothing to be done.\r
+ }\r
+\r
+ // take request -> new state\r
+ Std_ReturnType status = ComM_Internal_UpdateChannelState(Channel, TRUE);\r
+ if (status > requestStatus){\r
+ requestStatus = status;\r
+ }\r
+\r
+ }\r
+\r
+ return requestStatus;\r
+}\r
+\r
+Std_ReturnType ComM_GetMaxComMode( ComM_UserHandleType User, ComM_ModeType* ComMode ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_GETMAXCOMMODE, COMM_E_UNINIT);\r
+ COMM_VALIDATE_USER(User, COMM_SERVICEID_GETMAXCOMMODE, E_NOT_OK);\r
+ // Not implemented\r
+ (void)ComMode;\r
+ return E_NOT_OK;\r
+}\r
+\r
+/** @req COMM80 */\r
+Std_ReturnType ComM_GetRequestedComMode( ComM_UserHandleType User, ComM_ModeType* ComMode ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_GETREQUESTEDCOMMODE, COMM_E_UNINIT);\r
+ COMM_VALIDATE_USER(User, COMM_SERVICEID_GETREQUESTEDCOMMODE, E_NOT_OK);\r
+\r
+ ComM_Internal_UserType* UserInternal = &ComM_Internal.Users[User];\r
+ *ComMode = UserInternal->RequestedMode;\r
+ return E_OK;\r
+}\r
+\r
+/** @req COMM84 */\r
+Std_ReturnType ComM_GetCurrentComMode( ComM_UserHandleType User, ComM_ModeType* ComMode ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_GETCURRENTCOMMODE, COMM_E_UNINIT);\r
+ COMM_VALIDATE_USER(User, COMM_SERVICEID_GETCURRENTCOMMODE, E_NOT_OK);\r
+\r
+ return ComM_Internal_PropagateGetCurrentComMode(User, ComMode);\r
+}\r
+\r
+Std_ReturnType ComM_PreventWakeUp( NetworkHandleType Channel, boolean Status ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_PREVENTWAKEUP, COMM_E_UNINIT);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_PREVENTWAKEUP, E_NOT_OK);\r
+#if (COMM_MODE_LIMITATION_ENABLED == STD_ON)\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+ if (Status) {\r
+ ChannelInternal->InhibitionStatus |= (COMM_INHIBITION_STATUS_WAKE_UP);\r
+ } else {\r
+ ChannelInternal->InhibitionStatus &= ~(COMM_INHIBITION_STATUS_WAKE_UP);\r
+ }\r
+ return E_OK;\r
+#else\r
+ return E_NOT_OK;\r
+#endif\r
+}\r
+\r
+/** @req COMM361 @req COMM105.1 @req COMM800 */\r
+Std_ReturnType ComM_LimitChannelToNoComMode( NetworkHandleType Channel, boolean Status ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_LIMITCHANNELTONOCOMMODE, COMM_E_UNINIT);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_LIMITCHANNELTONOCOMMODE, E_NOT_OK);\r
+#if (COMM_MODE_LIMITATION_ENABLED == STD_ON)\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+ if (Status) {\r
+ ChannelInternal->InhibitionStatus |= (COMM_INHIBITION_STATUS_NO_COMMUNICATION);\r
+ } else {\r
+ ChannelInternal->InhibitionStatus &= ~(COMM_INHIBITION_STATUS_NO_COMMUNICATION);\r
+ }\r
+ return ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+#else\r
+ return E_NOT_OK;\r
+#endif\r
+}\r
+\r
+/** @req COMM105.2 @req COMM801.partially */\r
+Std_ReturnType ComM_LimitECUToNoComMode( boolean Status ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_LIMITECUTONOCOMMODE, COMM_E_UNINIT);\r
+#if (COMM_MODE_LIMITATION_ENABLED == STD_ON)\r
+ ComM_Internal.NoCommunication = Status;\r
+ uint8 Channel;\r
+ Std_ReturnType totalStatus = E_OK;\r
+ for (Channel = 0; Channel < COMM_CHANNEL_COUNT; Channel++) {\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ Std_ReturnType status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ if (status > totalStatus) {\r
+ totalStatus = status;\r
+ }\r
+ }\r
+ return totalStatus;\r
+#else\r
+ return E_NOT_OK;\r
+#endif\r
+}\r
+\r
+/** @req COMM143 @req COMM802 */\r
+Std_ReturnType ComM_ReadInhibitCounter( uint16* CounterValue ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_READINHIBITCOUNTER, COMM_E_UNINIT);\r
+#if (COMM_MODE_LIMITATION_ENABLED == STD_ON)\r
+ *CounterValue = ComM_Internal.InhibitCounter;\r
+ return E_OK;\r
+#else\r
+ return E_NOT_OK;\r
+#endif\r
+}\r
+\r
+/** @req COMM803 */\r
+Std_ReturnType ComM_ResetInhibitCounter(){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_RESETINHIBITCOUNTER, COMM_E_UNINIT);\r
+#if (COMM_MODE_LIMITATION_ENABLED == STD_ON)\r
+ ComM_Internal.InhibitCounter = 0;\r
+ return E_OK;\r
+#else\r
+ return E_NOT_OK;\r
+#endif\r
+}\r
+\r
+Std_ReturnType ComM_SetECUGroupClassification( ComM_InhibitionStatusType Status ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_SETECUGROUPCLASSIFICATION, COMM_E_UNINIT);\r
+ // Not implemented\r
+ (void)Status;\r
+ return E_NOT_OK;\r
+}\r
+\r
+\r
+// Network Management Interface Callbacks\r
+// --------------------------------------\r
+/** @req COMM804 */\r
+void ComM_Nm_NetworkStartIndication( NetworkHandleType Channel ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_NM_NETWORKSTARTINDICATION);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_NM_NETWORKSTARTINDICATION);\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+\r
+ // Used to simulate Wake-up\r
+ ChannelInternal->NmIndicationMask |= COMM_NM_INDICATION_RESTART;\r
+ Std_ReturnType status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ if (status != E_OK) {\r
+ // TODO: report error?\r
+ }\r
+}\r
+\r
+/** @req COMM807 */\r
+void ComM_Nm_NetworkMode( NetworkHandleType Channel ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_NM_NETWORKMODE);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_NM_NETWORKMODE);\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+\r
+ ChannelInternal->NmIndicationMask |= COMM_NM_INDICATION_NETWORK_MODE;\r
+ Std_ReturnType status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ if (status != E_OK) {\r
+ // TODO: report error?\r
+ }\r
+}\r
+\r
+/** @req COMM809 */\r
+void ComM_Nm_PrepareBusSleepMode( NetworkHandleType Channel ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_NM_PREPAREBUSSLEEPMODE);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_NM_PREPAREBUSSLEEPMODE);\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
\r
-void ComM_Init( ComM_ConfigType *config ) {\r
+ ChannelInternal->NmIndicationMask |= COMM_NM_INDICATION_PREPARE_BUS_SLEEP;\r
+ Std_ReturnType status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ if (status != E_OK) {\r
+ // TODO: report error?\r
+ }\r
+}\r
+\r
+/** @req COMM811 */\r
+void ComM_Nm_BusSleepMode( NetworkHandleType Channel ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_NM_BUSSLEEPMODE);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_NM_BUSSLEEPMODE);\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+\r
+ ChannelInternal->NmIndicationMask |= COMM_NM_INDICATION_BUS_SLEEP;\r
+ Std_ReturnType status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ if (status != E_OK) {\r
+ // TODO: report error?\r
+ }\r
+}\r
+\r
+/** @req COMM813 */\r
+void ComM_Nm_RestartIndication( NetworkHandleType Channel ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_NM_RESTARTINDICATION);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_NM_RESTARTINDICATION);\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+\r
+ ChannelInternal->NmIndicationMask |= COMM_NM_INDICATION_RESTART;\r
+ Std_ReturnType status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ if (status != E_OK) {\r
+ // TODO: report error?\r
+ }\r
+\r
+}\r
+\r
+\r
+// ECU State Manager Callbacks\r
+// ---------------------------\r
+\r
+void ComM_EcuM_RunModeIndication( NetworkHandleType Channel ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_ECUM_RUNMODEINDICATION);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_ECUM_RUNMODEINDICATION);\r
+}\r
+\r
+void ComM_EcuM_WakeUpIndication( NetworkHandleType Channel ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_ECUM_WAKEUPINDICATION);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_ECUM_WAKEUPINDICATION);\r
+}\r
+\r
+\r
+// Diagnostic Communication Manager Callbacks\r
+// ------------------------------------------\r
+\r
+void ComM_DCM_ActiveDiagnostic(void){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_DCM_ACTIVEDIAGNOSTIC);\r
+}\r
+\r
+void ComM_DCM_InactiveDiagnostic(void){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_DCM_INACTIVEDIAGNOSTIC);\r
+}\r
+\r
+\r
+// Bus State Manager Callbacks\r
+// ---------------------------\r
+\r
+void ComM_BusSM_ModeIndication( NetworkHandleType Channel, ComM_ModeType ComMode ){\r
+ COMM_VALIDATE_INIT(COMM_SERVICEID_BUSSM_MODEINDICATION);\r
+ COMM_VALIDATE_CHANNEL(Channel, COMM_SERVICEID_BUSSM_MODEINDICATION);\r
+ // Not implemented\r
+ (void)ComMode;\r
+}\r
+\r
+\r
+// Scheduled main function\r
+// -----------------------\r
+\r
+// Prototype right here because this function should not be exposed\r
+void ComM_MainFunction(NetworkHandleType Channel);\r
+\r
+/** @req COMM429 */\r
+void ComM_MainFunction(NetworkHandleType Channel) {\r
+ const ComM_ChannelType* ChannelConf = &ComM_Config->Channels[Channel];\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[Channel];\r
+\r
+ if ((ChannelConf->NmVariant == COMM_NM_VARIANT_NONE) ||\r
+ (ChannelConf->NmVariant == COMM_NM_VARIANT_LIGHT)) {\r
+ Std_ReturnType status = ComM_Internal_TickFullComMinTime(ChannelConf, ChannelInternal);\r
+ if (status != E_OK) {\r
+ // TODO: Report error?\r
+ }\r
+ }\r
+ if (ChannelConf->NmVariant == COMM_NM_VARIANT_LIGHT) {\r
+ Std_ReturnType status = ComM_Internal_TickLightTime(ChannelConf, ChannelInternal);\r
+ if (status != E_OK) {\r
+ // TODO: Report error?\r
+ }\r
+ }\r
+\r
+}\r
\r
- ( void )config;\r
+// ----------------------------------------------------------------------------\r
+// Internal functions\r
+// ----------------------------------------------------------------------------\r
+\r
+static inline Std_ReturnType ComM_Internal_TickFullComMinTime(const ComM_ChannelType* ChannelConf, ComM_Internal_ChannelType* ChannelInternal) {\r
+ Std_ReturnType status = E_OK;\r
+ if (ChannelInternal->Mode == COMM_FULL_COMMUNICATION) {\r
+ if (ChannelConf->MainFunctionPeriod >= ChannelInternal->FullComMinDurationTimeLeft) {\r
+ ChannelInternal->FullComMinDurationTimeLeft = 0;\r
+ status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ } else {\r
+ ChannelInternal->FullComMinDurationTimeLeft -= ChannelConf->MainFunctionPeriod;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+static inline boolean ComM_Internal_FullComMinTime_AllowsExit(const ComM_ChannelType* ChannelConf, const ComM_Internal_ChannelType* ChannelInternal) {\r
+ boolean rv;\r
+ /** @req COMM311 */\r
+ if ((ChannelConf->NmVariant == COMM_NM_VARIANT_LIGHT) ||\r
+ (ChannelConf->NmVariant == COMM_NM_VARIANT_NONE)){\r
+ rv = (ChannelInternal->FullComMinDurationTimeLeft == 0);\r
+ } else {\r
+ rv = TRUE;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static inline Std_ReturnType ComM_Internal_TickLightTime(const ComM_ChannelType* ChannelConf, ComM_Internal_ChannelType* ChannelInternal) {\r
+ Std_ReturnType status = E_OK;\r
+ if ((ChannelInternal->Mode == COMM_FULL_COMMUNICATION) &&\r
+ (ChannelInternal->SubMode == COMM_SUBMODE_READY_SLEEP)) {\r
+ if (ChannelConf->MainFunctionPeriod >= ChannelInternal->LightTimeoutTimeLeft) {\r
+ ChannelInternal->LightTimeoutTimeLeft = 0;\r
+ status = ComM_Internal_UpdateChannelState(ChannelConf, FALSE);\r
+ } else {\r
+ ChannelInternal->LightTimeoutTimeLeft -= ChannelConf->MainFunctionPeriod;\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+/** @req COMM678.2 */\r
+static Std_ReturnType ComM_Internal_PropagateGetCurrentComMode( ComM_UserHandleType User, ComM_ModeType* ComMode ){\r
+ const ComM_UserType* UserConfig = &ComM_Config->Users[User];\r
+\r
+ ComM_ModeType requestMode = COMM_FULL_COMMUNICATION;\r
+ Std_ReturnType totalStatus = E_OK;\r
+ /* Go through users channels. Relay to SMs. Collect overall mode and success status */\r
+ for (uint8 i = 0; i < UserConfig->ChannelCount; ++i) {\r
+ const ComM_ChannelType* Channel = UserConfig->ChannelList[i];\r
+ Std_ReturnType status = E_OK;\r
+ ComM_ModeType mode = COMM_FULL_COMMUNICATION;\r
+ switch (Channel->BusType) {\r
+ case COMM_BUS_TYPE_CAN:\r
+ status = CanSM_GetCurrentComMode(Channel->BusSMNetworkHandle, &mode);\r
+ break;\r
+ default:\r
+ status = E_NOT_OK;\r
+ break;\r
+ }\r
+ if (status == E_OK) {\r
+ if (mode < requestMode) { /** @req ComM176 */\r
+ requestMode = mode;\r
+ }\r
+ } else {\r
+ totalStatus = status;\r
+ }\r
+ }\r
+ *ComMode = requestMode;\r
+ return totalStatus;\r
}\r
\r
-void ComM_BusSM_ModeIndication(NetworkHandleType Channel,ComM_ModeType ComMode){\r
+/** @req COMM281.partially @req COMM70 @req COMM73 @req COMM71 @req COMM72\r
+ * @req COMM69 @req COMM402 @req COMM434 @req COMM678.1 @req COMM168 @req COMM676.partially */\r
+static Std_ReturnType ComM_Internal_PropagateComMode( const ComM_ChannelType* ChannelConf ){\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[ChannelConf->Number];\r
+ ComM_ModeType ComMode = ChannelInternal->Mode;\r
+\r
+ Std_ReturnType busSMStatus = E_OK;\r
+ switch (ChannelConf->BusType) {\r
+#if defined(USE_CANSM) || defined(COMM_TESTS)\r
+ case COMM_BUS_TYPE_CAN:\r
+ busSMStatus = CanSM_RequestComMode(ChannelConf->BusSMNetworkHandle, ComMode);\r
+ break;\r
+#endif\r
+#if defined(USE_LINSM)\r
+ case COMM_BUS_TYPE_LIN:\r
+ busSMStatus = LinSM_RequestComMode(ChannelConf->BusSMNetworkHandle, ComMode);\r
+ break;\r
+#endif\r
+ default:\r
+ busSMStatus = E_NOT_OK;\r
+ }\r
+\r
+ return busSMStatus;\r
+}\r
+\r
+/** @req COMM472 @req COMM602 @req COMM261 */\r
+static Std_ReturnType ComM_Internal_NotifyNm( const ComM_ChannelType* ChannelConf){\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[ChannelConf->Number];\r
+\r
+ Std_ReturnType globalStatus = E_OK;\r
+\r
+ if ((ChannelConf->NmVariant == COMM_NM_VARIANT_FULL) ||\r
+ (ChannelConf->NmVariant == COMM_NM_VARIANT_PASSIVE)) {\r
+#if defined(USE_NM) || defined(COMM_TESTS)\r
+ Nm_ReturnType nmStatus = NM_E_OK;\r
+ if (ChannelInternal->Mode == COMM_FULL_COMMUNICATION) {\r
+ if (ChannelInternal->SubMode == COMM_SUBMODE_NETWORK_REQUESTED) {\r
+ nmStatus = Nm_NetworkRequest(ChannelConf->NmChannelHandle); /**< @req COMM129.1 */\r
+ } else if (ChannelInternal->SubMode == COMM_SUBMODE_READY_SLEEP) {\r
+ nmStatus = Nm_NetworkRelease(ChannelConf->NmChannelHandle); /**< @req COMM133.1 */\r
+ } else {\r
+ //Nothing to be done.\r
+ }\r
+ }\r
+ if (nmStatus != NM_E_OK) {\r
+ globalStatus = E_NOT_OK;\r
+ }\r
+#else\r
+ globalStatus = E_NOT_OK;\r
+#endif\r
+ }\r
+\r
+ return globalStatus;\r
+}\r
\r
+/* Processes all requests etc. and makes state machine transitions accordingly */\r
+static Std_ReturnType ComM_Internal_UpdateChannelState( const ComM_ChannelType* ChannelConf, boolean isRequest ) {\r
+ ComM_Internal_ChannelType* ChannelInternal = &ComM_Internal.Channels[ChannelConf->Number];\r
+ Std_ReturnType status = E_OK;\r
+ switch (ChannelInternal->Mode) {\r
+ case COMM_NO_COMMUNICATION:\r
+ status = ComM_Internal_UpdateFromNoCom(ChannelConf, ChannelInternal, isRequest);\r
+ break;\r
+ case COMM_SILENT_COMMUNICATION:\r
+ status = ComM_Internal_UpdateFromSilentCom(ChannelConf, ChannelInternal, isRequest);\r
+ break;\r
+ case COMM_FULL_COMMUNICATION:\r
+ status = ComM_Internal_UpdateFromFullCom(ChannelConf, ChannelInternal, isRequest);\r
+ break;\r
+ default:\r
+ status = E_NOT_OK;\r
+ break;\r
+ }\r
+ return status;\r
}\r
\r
+static inline Std_ReturnType ComM_Internal_UpdateFromNoCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal, boolean isRequest) {\r
+ Std_ReturnType status = E_OK;\r
+ if (ChannelInternal->NmIndicationMask & COMM_NM_INDICATION_RESTART) { /**< @req COMM207.partial */\r
+ // "restart" indication\r
+ status = ComM_Internal_Enter_NetworkRequested(ChannelConf, ChannelInternal); /**< @req COMM583 */\r
+ ChannelInternal->NmIndicationMask &= ~(COMM_NM_INDICATION_RESTART);\r
+ } else {\r
+ if ((ChannelInternal->InhibitionStatus & COMM_INHIBITION_STATUS_NO_COMMUNICATION) ||\r
+ (ChannelInternal->InhibitionStatus & COMM_INHIBITION_STATUS_WAKE_UP) ||\r
+ (ComM_Internal.NoCommunication == TRUE)) {\r
+ // Inhibition is active\r
+ /** @req COMM302 @req COMM218 @req COMM219 @req COMM215.3 @req COMM216.3 */\r
+ if (isRequest){\r
+ ComM_Internal.InhibitCounter++;\r
+ }\r
+ } else {\r
+ if (ChannelInternal->UserRequestMask != 0) {\r
+ // Channel is requested\r
+ status = ComM_Internal_Enter_NetworkRequested(ChannelConf, ChannelInternal); /**< @req COMM784.2 */\r
+ } else {\r
+ // Channel is not requested\r
+ }\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+static inline Std_ReturnType ComM_Internal_UpdateFromSilentCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal, boolean isRequest) {\r
+ Std_ReturnType status = E_OK;\r
+ if (ChannelInternal->NmIndicationMask & COMM_NM_INDICATION_RESTART) { /**< @req COMM207.partial */\r
+ // "restart" indication\r
+ status = ComM_Internal_Enter_ReadySleep(ChannelConf, ChannelInternal); /**< @req COMM296.1 */\r
+ ChannelInternal->NmIndicationMask &= ~(COMM_NM_INDICATION_RESTART);\r
+ } else if (ChannelInternal->NmIndicationMask & COMM_NM_INDICATION_BUS_SLEEP) {\r
+ // "bus sleep" indication\r
+ status = ComM_Internal_Enter_NoCom(ChannelConf, ChannelInternal); /**< @req COMM295 */\r
+ ChannelInternal->NmIndicationMask &= ~(COMM_NM_INDICATION_BUS_SLEEP);\r
+ } else if (ChannelInternal->NmIndicationMask & COMM_NM_INDICATION_NETWORK_MODE) {\r
+ // "network mode" indication\r
+ status = ComM_Internal_Enter_ReadySleep(ChannelConf, ChannelInternal); /**< @req COMM296.2 */\r
+ ChannelInternal->NmIndicationMask &= ~(COMM_NM_INDICATION_NETWORK_MODE);\r
+ } else {\r
+ if ((ChannelInternal->InhibitionStatus & COMM_INHIBITION_STATUS_NO_COMMUNICATION) ||\r
+ (ComM_Internal.NoCommunication == TRUE)) {\r
+ // Inhibition is active\r
+ /** @req COMM215.2 @req COMM216.2 */\r
+ if (isRequest) {\r
+ ComM_Internal.InhibitCounter++;\r
+ }\r
+ } else {\r
+ if (ChannelInternal->UserRequestMask != 0) {\r
+ // Channel is requested\r
+ status = ComM_Internal_Enter_NetworkRequested(ChannelConf, ChannelInternal); /**< @req COMM785 */\r
+ } else {\r
+ // Stay in SILENT\r
+ }\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+static inline Std_ReturnType ComM_Internal_UpdateFromFullCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal, boolean isRequest) {\r
+ Std_ReturnType status = E_OK;\r
+ if (ChannelInternal->NmIndicationMask & COMM_NM_INDICATION_BUS_SLEEP) {\r
+ // "bus sleep" indication\r
+ status = ComM_Internal_Enter_NoCom(ChannelConf, ChannelInternal); /**< @req COMM637 */\r
+ ChannelInternal->NmIndicationMask &= ~(COMM_NM_INDICATION_BUS_SLEEP);\r
+ } else if ((ChannelInternal->NmIndicationMask & COMM_NM_INDICATION_PREPARE_BUS_SLEEP) &&\r
+ (ChannelInternal->SubMode == COMM_SUBMODE_READY_SLEEP)) {\r
+ // "prepare bus sleep" indication\r
+ status = ComM_Internal_Enter_SilentCom(ChannelConf, ChannelInternal); /**< @req COMM299 */\r
+ ChannelInternal->NmIndicationMask &= ~(COMM_NM_INDICATION_PREPARE_BUS_SLEEP);\r
+ } else {\r
+ if ((ChannelInternal->InhibitionStatus & COMM_INHIBITION_STATUS_NO_COMMUNICATION) ||\r
+ (ComM_Internal.NoCommunication == TRUE)) {\r
+ // Inhibition is active\r
+ if (ComM_Internal_FullComMinTime_AllowsExit(ChannelConf, ChannelInternal)) { /**< @req COMM205.1 */\r
+ if (ChannelInternal->SubMode == COMM_SUBMODE_READY_SLEEP) {\r
+ if ((ChannelConf->NmVariant == COMM_NM_VARIANT_LIGHT) &&\r
+ (ChannelInternal->LightTimeoutTimeLeft == 0)) {\r
+ status = ComM_Internal_Enter_NoCom(ChannelConf, ChannelInternal); /**< @req COMM610.1 */\r
+ }\r
+ } else {\r
+ /** @req COMM478.seeAlsoCOMM52 @req COMM303 @req COMM215.1 @req COMM216.1 */\r
+ status = ComM_Internal_Enter_ReadySleep(ChannelConf, ChannelInternal);\r
+ }\r
+ }\r
+ if (isRequest){\r
+ ComM_Internal.InhibitCounter++;\r
+ }\r
+ } else {\r
+ if (ChannelInternal->UserRequestMask == 0) {\r
+ // Channel no longer requested\r
+ if (ComM_Internal_FullComMinTime_AllowsExit(ChannelConf, ChannelInternal)) { /**< @req COMM205.1 */\r
+ if (ChannelInternal->SubMode == COMM_SUBMODE_READY_SLEEP) {\r
+ if ((ChannelConf->NmVariant == COMM_NM_VARIANT_LIGHT) &&\r
+ (ChannelInternal->LightTimeoutTimeLeft == 0)) {\r
+ status = ComM_Internal_Enter_NoCom(ChannelConf, ChannelInternal); /**< @req COMM610.2 */\r
+ }\r
+ } else {\r
+ status = ComM_Internal_Enter_ReadySleep(ChannelConf, ChannelInternal);\r
+ }\r
+ }\r
+ } else {\r
+ // Channel is requested\r
+ if (ChannelInternal->SubMode != COMM_SUBMODE_NETWORK_REQUESTED) {\r
+ status = ComM_Internal_Enter_NetworkRequested(ChannelConf, ChannelInternal); /**< @req COMM479 */\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return status;\r
+}\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_NoCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal) {\r
+ ChannelInternal->Mode = COMM_NO_COMMUNICATION;\r
+ return ComM_Internal_PropagateComMode(ChannelConf);\r
+}\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_SilentCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal) {\r
+ ChannelInternal->Mode = COMM_SILENT_COMMUNICATION;\r
+ return ComM_Internal_PropagateComMode(ChannelConf);\r
+}\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_NetworkRequested(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal) {\r
+ boolean propagateToBusSM = (ChannelInternal->Mode != COMM_FULL_COMMUNICATION);\r
+ ChannelInternal->FullComMinDurationTimeLeft = COMM_T_MIN_FULL_COM_MODE_DURATION;\r
+ ChannelInternal->Mode = COMM_FULL_COMMUNICATION;\r
+ ChannelInternal->SubMode = COMM_SUBMODE_NETWORK_REQUESTED;\r
+\r
+ Std_ReturnType status, globalStatus = E_OK;\r
+ status = ComM_Internal_NotifyNm(ChannelConf); /**< @req COMM129.2 */\r
+ if (status > globalStatus){\r
+ globalStatus = status;\r
+ }\r
+ if (propagateToBusSM) {\r
+ status = ComM_Internal_PropagateComMode(ChannelConf);\r
+ if (status > globalStatus){\r
+ globalStatus = status;\r
+ }\r
+ }\r
+ return globalStatus;\r
+}\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_ReadySleep(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal) {\r
+ boolean propagateToBusSM = (ChannelInternal->Mode != COMM_FULL_COMMUNICATION);\r
+ ChannelInternal->LightTimeoutTimeLeft = ChannelConf->LightTimeout;\r
+ ChannelInternal->Mode = COMM_FULL_COMMUNICATION;\r
+ ChannelInternal->SubMode = COMM_SUBMODE_READY_SLEEP;\r
+\r
+ Std_ReturnType status, globalStatus = E_OK;\r
+ status = ComM_Internal_NotifyNm(ChannelConf); /**< @req COMM133.1 */\r
+ if (status > globalStatus){\r
+ globalStatus = status;\r
+ }\r
+ if (propagateToBusSM) {\r
+ status = ComM_Internal_PropagateComMode(ChannelConf);\r
+ if (status > globalStatus){\r
+ globalStatus = status;\r
+ }\r
+ }\r
+ return globalStatus;\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef COMM_INTERNAL_H\r
+#define COMM_INTERNAL_H\r
+\r
+#include "ComM_Types.h"\r
+\r
+/** @req COMM612 @req COMM511 @req COMM512 @req COMM270 @req COMM523 */\r
+#if (COMM_DEV_ERROR_DETECT == STD_ON)\r
+#define COMM_DET_REPORTERROR(serviceId, errorId) \\r
+ Det_ReportError(MODULE_ID_COMM, 0, serviceId, errorId)\r
+\r
+#define COMM_VALIDATE(expression, serviceId, errorId, ...) \\r
+ if (!(expression)) { \\r
+ COMM_DET_REPORTERROR(serviceId, errorId); \\r
+ return __VA_ARGS__; \\r
+ }\r
+\r
+#else\r
+#define COMM_DET_REPORTERROR(...)\r
+#define COMM_VALIDATE(...)\r
+#endif\r
+\r
+#define COMM_VALIDATE_INIT(serviceID, ...) \\r
+ COMM_VALIDATE((ComM_Internal.InitStatus == COMM_INIT), serviceID, COMM_E_NOT_INITED, __VA_ARGS__)\r
+\r
+#define COMM_VALIDATE_PARAMETER(expression, serviceID, ...) \\r
+ COMM_VALIDATE(expression, serviceID, COMM_E_WRONG_PARAMETERS, __VA_ARGS__)\r
+\r
+#define COMM_VALIDATE_CHANNEL(channel, serviceID, ...) \\r
+ COMM_VALIDATE_PARAMETER( (channel < COMM_CHANNEL_COUNT), serviceID, __VA_ARGS__)\r
+\r
+#define COMM_VALIDATE_USER(user, serviceID, ...) \\r
+ COMM_VALIDATE_PARAMETER( (user < COMM_USER_COUNT), serviceID, __VA_ARGS__)\r
+\r
+\r
+typedef enum {\r
+ COMM_SUBMODE_NETWORK_REQUESTED,\r
+ COMM_SUBMODE_READY_SLEEP,\r
+ COMM_SUBMODE_NONE\r
+} ComM_Internal_SubModeType;\r
+\r
+typedef struct {\r
+ ComM_ModeType Mode;\r
+ ComM_Internal_SubModeType SubMode;\r
+ uint32 UserRequestMask;\r
+ ComM_InhibitionStatusType InhibitionStatus;\r
+ uint32 FullComMinDurationTimeLeft;\r
+ uint32 LightTimeoutTimeLeft;\r
+ uint8 NmIndicationMask;\r
+} ComM_Internal_ChannelType;\r
+\r
+typedef struct {\r
+ ComM_ModeType RequestedMode;\r
+} ComM_Internal_UserType;\r
+\r
+typedef struct {\r
+ ComM_InitStatusType InitStatus;\r
+ ComM_Internal_ChannelType Channels[COMM_CHANNEL_COUNT];\r
+ ComM_Internal_UserType Users[COMM_USER_COUNT];\r
+ boolean NoCommunication;\r
+ uint16 InhibitCounter; /**< @req COMM138 @req COMM141 */\r
+} ComM_InternalType;\r
+\r
+#define COMM_NM_INDICATION_NONE (uint8)(0u)\r
+#define COMM_NM_INDICATION_NETWORK_MODE (uint8)(1u)\r
+#define COMM_NM_INDICATION_PREPARE_BUS_SLEEP (uint8)(1u << 1)\r
+#define COMM_NM_INDICATION_BUS_SLEEP (uint8)(1u << 2)\r
+#define COMM_NM_INDICATION_RESTART (uint8)(1u << 3)\r
+\r
+/* Delegate request to users channels and call ComM_Internal_UpdateChannelState */\r
+static Std_ReturnType ComM_Internal_RequestComMode(\r
+ ComM_UserHandleType User, ComM_ModeType ComMode );\r
+\r
+/* Looks at stored requests for Channel and updates state accordingly */\r
+static Std_ReturnType ComM_Internal_UpdateChannelState( const ComM_ChannelType* ChannelConf, boolean isRequest );\r
+\r
+static inline Std_ReturnType ComM_Internal_UpdateFromNoCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal, boolean isRequest);\r
+\r
+static inline Std_ReturnType ComM_Internal_UpdateFromSilentCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal, boolean isRequest);\r
+\r
+static inline Std_ReturnType ComM_Internal_UpdateFromFullCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal, boolean isRequest);\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_NoCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal);\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_SilentCom(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal);\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_NetworkRequested(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal);\r
+\r
+static inline Std_ReturnType ComM_Internal_Enter_ReadySleep(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal);\r
+\r
+/* Propagates channel mode to BusSM */\r
+static Std_ReturnType ComM_Internal_PropagateComMode( const ComM_ChannelType* ChannelConf );\r
+\r
+/* Requests/releases Nm network according to channel mode */\r
+static Std_ReturnType ComM_Internal_NotifyNm( const ComM_ChannelType* ChannelConf);\r
+\r
+/* Propagate query to channel Bus SMs. Collect overall mode and status */\r
+static Std_ReturnType ComM_Internal_PropagateGetCurrentComMode(\r
+ ComM_UserHandleType User, ComM_ModeType* ComMode );\r
+\r
+/* Tick 'Min full com duration' timeout, and update state if needed */\r
+static inline Std_ReturnType ComM_Internal_TickFullComMinTime(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal);\r
+\r
+static inline boolean ComM_Internal_FullComMinTime_AllowsExit(const ComM_ChannelType* ChannelConf,\r
+ const ComM_Internal_ChannelType* ChannelInternal);\r
+\r
+/* Tick 'Light nm' timeout, and update state if needed */\r
+static inline Std_ReturnType ComM_Internal_TickLightTime(const ComM_ChannelType* ChannelConf,\r
+ ComM_Internal_ChannelType* ChannelInternal);\r
+\r
+#endif /* COMM_INTERNAL_H */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "CanNm.h"\r
+#include "Nm.h"\r
+#include "Nm_Internal.h"\r
+\r
+/* Globally fulfilled requirements */\r
+/** @req NM006 */\r
+/** @req NM026 */\r
+\r
+const Nm_ConfigType* Nm_ConfigPtr;\r
+\r
+/** Initializes the NM Interface. */\r
+void Nm_Init( Nm_ConfigType * const nmConfigPtr ){\r
+ Nm_ConfigPtr = nmConfigPtr;\r
+}\r
+\r
+/** This service returns the version information of this module */\r
+void Nm_GetVersionInfo( Std_VersionInfoType* nmVerInfoPtr ){}\r
+\r
+/** This function calls the <BusNm>_PassiveStartUp function\r
+ * (e.g. CanNm_PassiveStartUp function is called if channel is configured as CAN). */\r
+Nm_ReturnType Nm_PassiveStartUp( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(PassiveStartUp, ChannelConf);\r
+}\r
+\r
+/** This function calls the <BusNm>_NetworkRequest\r
+ * (e.g. CanNm_NetworkRequest function is called if channel is configured as CAN). */\r
+Nm_ReturnType Nm_NetworkRequest( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(NetworkRequest, ChannelConf)\r
+}\r
+\r
+/** This function calls the <BusNm>_NetworkRelease bus specific function\r
+ * (e.g. CanNm_NetworkRelease function is called if channel is configured as CAN). */\r
+Nm_ReturnType Nm_NetworkRelease( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(NetworkRelease, ChannelConf)\r
+}\r
+\r
+/** This function calls the CanNm_NetworkRelease bus specific function, to disable\r
+ * the NM PDU transmission ability due to a ISO14229 Communication Control (28hex) service */\r
+Nm_ReturnType Nm_DisableCommunication( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(DisableCommunication, ChannelConf)\r
+}\r
+\r
+/** This function calls the CanNm_NetworkRequest bus specific function, to enable\r
+ * the NM PDU transmission ability due to a ISO14229 Communication Control (28hex) service */\r
+Nm_ReturnType Nm_EnableCommunication( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(EnableCommunication, ChannelConf)\r
+}\r
+\r
+/** Set user data for NM messages transmitted next on the bus.\r
+ * For that purpose <BusNm>_SetUserData shall be called\r
+ * (e.g. CanNm_SetUserData function is called if channel is configured as CAN). */\r
+#if (NM_USER_DATA_ENABLED == STD_ON)\r
+Nm_ReturnType Nm_SetUserData( const NetworkHandleType NetworkHandle, const uint8 * const nmUserDataPtr ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(SetUserData, ChannelConf, nmUserDataPtr)\r
+}\r
+#endif\r
+\r
+/** Get user data out of the last successfully received NM message.\r
+ * For that purpose <BusNm>_GetUserData shall be called\r
+ * (e.g. CanNm_GetUserData function is called if channel is configured as CAN). */\r
+#if (NM_USER_DATA_ENABLED == STD_ON)\r
+Nm_ReturnType Nm_GetUserData( const NetworkHandleType NetworkHandle, uint8 * const nmUserDataPtr, uint8 * const nmNodeIdPtr ){\r
+ /* For some reason the signature of this service differs from its busNm equivalents... */\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ switch(ChannelConf->BusType) {\r
+#if defined(USE_CANNM)\r
+ case NM_BUSNM_CANNM:\r
+ NM_BUSNM_GET_USERDATA_AND_NODEID( CanNm, ChannelConf, nmUserDataPtr, nmNodeIdPtr )\r
+#endif\r
+#if defined(USE_FRNM)\r
+ case NM_BUSNM_FRNM:\r
+ NM_BUSNM_GET_USERDATA_AND_NODEID( FrNm, ChannelConf, nmUserDataPtr, nmNodeIdPtr )\r
+#endif\r
+#if defined(USE_LINNM)\r
+ case NM_BUSNM_LINNM:\r
+ NM_BUSNM_GET_USERDATA_AND_NODEID( LinNm, ChannelConf, nmUserDataPtr, nmNodeIdPtr )\r
+#endif\r
+ default: return NM_E_NOT_OK;\r
+ }\r
+}\r
+#endif\r
+\r
+/** Get the whole PDU data out of the most recently received NM message.\r
+ * For that purpose CanNm_GetPduData shall be called. */\r
+#if ((NM_NODE_ID_ENABLED == STD_ON) || (NM_NODE_DETECTION_ENABLED == STD_ON) || (NM_USER_DATA_ENABLED == STD_ON))\r
+Nm_ReturnType Nm_GetPduData( const NetworkHandleType NetworkHandle, uint8 * const nmPduData ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(GetPduData, ChannelConf, nmPduData)\r
+}\r
+#endif\r
+\r
+/** Set Repeat Message Request Bit for NM messages transmitted next on the bus.\r
+ * For that purpose <BusNm>_RepeatMessageRequest shall be called\r
+ * (e.g. CanNm_RepeatMessageRequest function is called if channel is configured as CAN) */\r
+Nm_ReturnType Nm_RepeatMessageRequest( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(RepeatMessageRequest, ChannelConf)\r
+}\r
+\r
+/** Get node identifier out of the last successfully received NM-message.\r
+ * The function <BusNm>_GetNodeIdentifier shall be called. */\r
+#if (NM_NODE_ID_ENABLED == STD_ON)\r
+Nm_ReturnType Nm_GetNodeIdentifier( const NetworkHandleType NetworkHandle, uint8 * const nmNodeIdPtr ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(GetNodeIdentifier, ChannelConf, nmNodeIdPtr)\r
+}\r
+\r
+/** Get node identifier configured for the local node.\r
+ * For that purpose <BusNm>_GetLocalNodeIdentifier shall be called\r
+ * (e.g. CanNm_GetLocalNodeIdentifier function is called if channel is configured as CAN). */\r
+Nm_ReturnType Nm_GetLocalNodeIdentifier( const NetworkHandleType NetworkHandle, uint8 * const nmNodeIdPtr ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(GetLocalNodeIdentifier, ChannelConf, nmNodeIdPtr)\r
+}\r
+#endif\r
+\r
+/** Check if remote sleep indication takes place or not. This in turn calls the\r
+ * <BusNm>_CheckRemoteSleepIndication for the bus specific NM layer\r
+ * (e.g. CanNm_CheckRemoteSleepIndication function is called if channel is configured as CAN). */\r
+Nm_ReturnType Nm_CheckRemoteSleepIndication( const NetworkHandleType NetworkHandle, boolean * const nmRemoteSleepIndPtr ){\r
+ return E_NOT_OK;\r
+}\r
+\r
+/** Returns the state of the network management. This function in turn calls the\r
+ * <BusNm>_GetState function (e.g. CanNm_GetState function is called if channel is configured as CAN). */\r
+Nm_ReturnType Nm_GetState( const NetworkHandleType NetworkHandle, Nm_StateType* const nmStatePtr, Nm_ModeType* const nmModePtr ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ NM_CALL_BUSNM(GetState, ChannelConf, nmStatePtr, nmModePtr)\r
+}\r
+\r
+/** Notification that a NM-message has been received in the Bus-Sleep Mode, what\r
+ * indicates that some nodes in the network have already entered the Network Mode.\r
+ * The callback function shall start the network management state machine. */\r
+/** @req NM012.partially.1 */\r
+void Nm_NetworkStartIndication( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ ComM_Nm_NetworkStartIndication(ChannelConf->ComMNetworkHandle);\r
+}\r
+\r
+/** Notification that the network management has entered Network Mode. The\r
+ * callback function shall enable transmission of application messages. */\r
+/** @req NM012.partially.2 */\r
+void Nm_NetworkMode( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ ComM_Nm_NetworkMode(ChannelConf->ComMNetworkHandle);\r
+}\r
+\r
+/** Notification that the network management has entered Prepare Bus-Sleep Mode.\r
+ * The callback function shall disable transmission of application messages. */\r
+/** @req NM012.partially.3 */\r
+void Nm_PrepareBusSleepMode( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ ComM_Nm_PrepareBusSleepMode(ChannelConf->ComMNetworkHandle);\r
+}\r
+\r
+/** Notification that the network management has entered Bus-Sleep Mode. */\r
+/** @req NM012.partially.4 */\r
+void Nm_BusSleepMode( const NetworkHandleType NetworkHandle ){\r
+ const Nm_ChannelType* ChannelConf = &Nm_ConfigPtr->Channels[NetworkHandle];\r
+ ComM_Nm_BusSleepMode(ChannelConf->ComMNetworkHandle);\r
+}\r
+\r
+/** Notification that a NM message has been received. */\r
+void Nm_PduRxIndication( const NetworkHandleType NetworkHandle ){}\r
+\r
+/** Notification that the CAN Generic NM state has changed. */\r
+void Nm_StateChangeNotification(\r
+ const NetworkHandleType nmNetworkHandle,\r
+ const Nm_StateType nmPreviousState,\r
+ const Nm_StateType nmCurrentState ){}\r
+\r
+/** This function implements the processes of the NM Interface, which need a fix\r
+ * cyclic scheduling. This function is supplied for the NM coordinator functionality\r
+ * (Nm020). However, specific implementation may not need it (Nm093) */\r
+/** @req 121 */\r
+void Nm_MainFunction(){}\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef NM_INTERNAL_H_\r
+#define NM_INTERNAL_H_\r
+\r
+\r
+/* macros to remove unavailable BusNm calls */\r
+#if defined(USE_CANNM)\r
+#define NM_CALL_BUSNM_CASE_CAN( service, channelconf, args... ) \\r
+ case NM_BUSNM_CANNM: \\r
+ return CanNm_##service(channelconf->BusNmNetworkHandle , ## args);\r
+#else\r
+#define NM_CALL_BUSNM_CASE_CAN( service, channelconf, args...)\r
+#endif\r
+\r
+#if defined(USE_FRNM)\r
+#define NM_CALL_BUSNM_CASE_FR( service, channelconf, args... ) \\r
+ case NM_BUSNM_FRNM: \\r
+ return FrNm_##service(channelconf->BusNmNetworkHandle , ## args);\r
+#else\r
+#define NM_CALL_BUSNM_CASE_FR( service, channelconf, args...)\r
+#endif\r
+\r
+#if defined(USE_LINNM)\r
+#define NM_CALL_BUSNM_CASE_LIN( service, channelconf, args... ) \\r
+ case NM_BUSNM_LINNM: \\r
+ return LinNm_##service(channelconf->BusNmNetworkHandle , ## args);\r
+#else\r
+#define NM_CALL_BUSNM_CASE_LIN( service, channelconf, args...)\r
+#endif\r
+\r
+/* complete switch for BusNm_<service>(...) calls */\r
+#define NM_CALL_BUSNM( service, channelconf, extra...) \\r
+ switch(channelconf->BusType) { \\r
+ NM_CALL_BUSNM_CASE_CAN( service, channelconf, ## extra) \\r
+ NM_CALL_BUSNM_CASE_FR( service, channelconf, ## extra) \\r
+ NM_CALL_BUSNM_CASE_LIN( service, channelconf, ## extra) \\r
+ default: return NM_E_NOT_OK; \\r
+ }\r
+\r
+#define NM_BUSNM_GET_USERDATA_AND_NODEID( busnm, channelconf, dataptr, nodeidptr) \\r
+ { \\r
+ Nm_ReturnType rv, globalReturnVal = NM_E_OK; \\r
+ rv = busnm##_GetUserData(channelconf->BusNmNetworkHandle, dataptr); \\r
+ if (rv > globalReturnVal) globalReturnVal = rv; \\r
+ rv = busnm##_GetNodeIdentifier(channelconf->BusNmNetworkHandle, nodeidptr); \\r
+ if (rv > globalReturnVal) globalReturnVal = rv; \\r
+ return globalReturnVal; \\r
+ }\r
+\r
+\r
+#endif /* NM_INTERNAL_H_ */\r
#include "Dem.h"\r
#endif\r
#include "PduR.h"\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
#include "debug.h"\r
\r
+\r
/*\r
* The state of the PDU router.\r
*/\r
-PduR_StateType PduRState = PDUR_UNINIT;\r
+PduR_StateType PduRState = PDUR_UNINIT; // 960, 31 PC-Lint: Borde åtgärdas\r
\r
const PduR_PBConfigType * PduRConfig;\r
\r
// Otherwise raise an error.\r
if (PduRState != PDUR_UNINIT) {\r
// Raise error and return.\r
- DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, 0x00, PDUR_E_INVALID_REQUEST);\r
+ PDUR_DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, 0x00, PDUR_E_INVALID_REQUEST);\r
return;\r
}\r
\r
if (ConfigPtr == NULL) {\r
- DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, 0x00, PDUR_E_CONFIG_PTR_INVALID);\r
+ PDUR_DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, 0x00, PDUR_E_CONFIG_PTR_INVALID);\r
return;\r
} else {\r
PduRConfig = ConfigPtr;\r
uint8 failed = 0;\r
\r
// Initialize buffers.\r
- int bufferNr = 0;\r
- int i = 0;\r
+ uint16 bufferNr = 0;\r
PduRRoutingPath_type *path;\r
PduRConfig->PduRRoutingTable->NRoutingPaths = 0;\r
- for (i = 0; !PduRConfig->PduRRoutingTable->PduRRoutingPath[i].PduR_Arc_EOL && !failed; i++) {\r
+ for (uint16 i = 0; (!PduRConfig->PduRRoutingTable->PduRRoutingPath[i].PduR_Arc_EOL) && (!failed); i++) {\r
PduRConfig->PduRRoutingTable->NRoutingPaths++;\r
path = &PduRConfig->PduRRoutingTable->PduRRoutingPath[i];\r
\r
failed = 1;\r
break;\r
}\r
+ // 586 PC-Lint (malloc) ticket #135\r
if ((buffer->Buffer = (uint8 *)malloc(buffer->Depth * sizeof(uint8) * path->SduLength)) == 0) {\r
DEBUG(DEBUG_LOW,"PduR_Init: Initialization of buffer failed. Buffer space could not be allocated for buffer number %d\n", bufferNr);\r
failed = 1;\r
(*ptr) = (*ptr) + Buffer->Length;\r
\r
// TODO make more efficient without multiplication.\r
- if (*ptr >= Buffer->Buffer + Buffer->Depth * Buffer->Length) {\r
+ //lint -e946 //PC-Lint Exception of MISRA rule 17.3\r
+ if ( *ptr >= ( Buffer->Buffer + (Buffer->Depth * Buffer->Length) ) ) {\r
*ptr = Buffer->Buffer;\r
}\r
//*val = (*val + 1) % Buffer->Depth;\r
\r
uint8 PduR_BufferIsFull(PduRTxBuffer_type *Buffer) {\r
imask_t state = McuE_EnterCriticalSection();\r
+ uint8 rv = 0;\r
if (Buffer->NrItems < Buffer->Depth) {\r
- return 0;\r
+ rv = 0;\r
} else {\r
- return 1;\r
+ rv = 1;\r
}\r
McuE_ExitCriticalSection(state);\r
+ return rv;\r
}\r
\r
\r
}\r
#endif\r
\r
-uint32 PduR_GetConfigurationId () {\r
- //DevCheck(0,1,0x18,E_NOT_OK);\r
+uint32 PduR_GetConfigurationId (void) {\r
+ //PduR_DevCheck(0,1,0x18,E_NOT_OK);\r
return PduRConfig->PduRConfigurationId;\r
}\r
#endif // End of not Zero Cost Operation Mode\r
\r
void PduR_CanIfRxIndication(PduIdType CanRxPduId,const uint8* CanSduPtr) {\r
#if (PDUR_CANIF_SUPPORT == STD_ON)\r
- DevCheck(CanRxPduId,CanSduPtr,0x0e);\r
+ PduR_DevCheck(CanRxPduId,CanSduPtr,0x0e);\r
\r
DEBUG(DEBUG_LOW,"----------------------\n");\r
DEBUG(DEBUG_LOW,"PduR_CanIfRxIndication: received indication with id %d and data %d\n", CanRxPduId, *CanSduPtr);\r
\r
void PduR_CanIfTxConfirmation(PduIdType CanTxPduId) {\r
#if (PDUR_CANIF_SUPPORT == STD_ON)\r
- DevCheck(CanTxPduId,1,0x0f);\r
+ PduR_DevCheck(CanTxPduId,1,0x0f);\r
\r
DEBUG(DEBUG_LOW,"----------------------\n");\r
DEBUG(DEBUG_LOW,"PduR_CanIfTxConfirmation: received confirmation with id %d\n", CanTxPduId);\r
\r
void PduR_CanTpTxConfirmation(PduIdType CanTpTxPduId, NotifResultType Result) {\r
#if (PDUR_CANTP_SUPPORT == STD_ON)\r
- DevCheck(CanTpTxPduId,1,0x0f);\r
+ PduR_DevCheck(CanTpTxPduId,1,0x0f);\r
\r
DEBUG(DEBUG_LOW,"----------------------\n");\r
DEBUG(DEBUG_LOW,"PduR_CanIfTxConfirmation: received confirmation with id %d\n", CanTxPduId);\r
Std_ReturnType PduR_ComTransmit(PduIdType ComTxPduId, const PduInfoType* PduInfoPtr) {\r
BufReq_ReturnType retVal = BUFREQ_NOT_OK;\r
#if (PDUR_COM_SUPPORT == STD_ON)\r
- DevCheck(ComTxPduId,PduInfoPtr,0x15, E_NOT_OK);\r
+ PduR_DevCheck(ComTxPduId,PduInfoPtr,0x15, E_NOT_OK);\r
\r
//DEBUG(DEBUG_LOW,"PduR_ComTransmit: received transmit request with id %d and data %d\n", ComTxPduId, *PduInfoPtr->SduDataPtr);\r
PduRRoutingPath_type *route = &PduRConfig->PduRRoutingTable->PduRRoutingPath[ComTxPduId];\r
Std_ReturnType PduR_DcmTransmit(PduIdType DcmTxPduId, const PduInfoType* PduInfoPtr) {\r
BufReq_ReturnType retVal = BUFREQ_NOT_OK;\r
#if (PDUR_DCM_SUPPORT == STD_ON)\r
- DevCheck(DcmTxPduId,PduInfoPtr,0x15, E_NOT_OK);\r
+ PduR_DevCheck(DcmTxPduId,PduInfoPtr,0x15, E_NOT_OK);\r
\r
//DEBUG(DEBUG_LOW,"PduR_ComTransmit: received transmit request with id %d and data %d\n", ComTxPduId, *PduInfoPtr->SduDataPtr);\r
\r
\r
if (route->PduR_GatewayMode == 0) {\r
// This is an ordinary request.\r
+ // 534 PC-Lint (ignoring return value) ticket #134:\r
route->FctPtrs.TargetIndicationFctPtr(route->PduRDestPdu.DestPduId, SduPtr); // Send PDU to next receptor.\r
\r
\r
- } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) {\r
+ } else if ( (route->PduR_GatewayMode == 1) && (route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) ) {\r
// This is a gateway request, but without any data provision (buffer usage).\r
PduInfoType PduInfo = {\r
- .SduDataPtr = (uint8 *)SduPtr,\r
+ .SduDataPtr = (uint8 *)SduPtr, // 926, 960 PC-Lint: Beror på att funktion PduR_LoIfRxIndication(...) fel-definerad TICKET 130\r
.SduLength = route->SduLength\r
};\r
+ // 534 PC-Lint (ignoring return value) ticket #134:\r
route->FctPtrs.TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, &PduInfo); // Send PDU to next receptor.\r
\r
\r
- } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) {\r
+ } else if ( (route->PduR_GatewayMode == 1) && (route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) ) {\r
// Ths is a gateway request which uses trigger transmit data provision. PDUR255\r
DEBUG(DEBUG_LOW,"\tUsing gateway mode with trigger transmit provision\n");\r
\r
}\r
}\r
\r
- } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_DIRECT) {\r
+ } else if ( (route->PduR_GatewayMode == 1) && (route->PduRDestPdu.DataProvision == PDUR_DIRECT) ) {\r
// This is a gateway request using a direct data provision fifo. PDUR258\r
DEBUG(DEBUG_LOW,"\tUsing gateway mode with direct provision\n");\r
\r
// Make new PduInfoPackage\r
DEBUG(DEBUG_LOW,"\tNo transfer confirmation pending. Forwarding packet.\n");\r
PduInfoType PduInfoPtr = {\r
- .SduDataPtr = (uint8 *)SduPtr,\r
+ .SduDataPtr = (uint8 *)SduPtr, // 926, 960 PC-Lint: Beror på att funktion PduR_LoIfRxIndication(...) fel-definerad TICKET 130\r
.SduLength = route->SduLength\r
};\r
if (route->FctPtrs.TargetTransmitFctPtr(route->PduRDestPdu.DestPduId, &PduInfoPtr) == E_OK) {\r
DEBUG(DEBUG_LOW,"\tTransmission failed. PDUR_E_PDU_INSTANCE_LOST\n");\r
}\r
}\r
+ } else {\r
+ // Nothing to be done.\r
}\r
}\r
\r
// This is an ordinary request.\r
route->FctPtrs.TargetConfirmationFctPtr(route->PduRDestPdu.DestPduId); // Forward confirmation\r
\r
- } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) {\r
+ } else if ( (route->PduR_GatewayMode == 1) && (route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) ) {\r
// A gateway request without provision. Just forward confirmation.\r
route->FctPtrs.TargetConfirmationFctPtr(route->PduRDestPdu.DestPduId); // Forward confirmation\r
\r
\r
- } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) {\r
+ } else if ( (route->PduR_GatewayMode == 1) && (route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) ) {\r
// The route is using gateway mode and trigger transmit data provision. PDUR256\r
DEBUG(DEBUG_LOW,"\tUsing gateway mode with trigger transmit data provision.\n", PduId);\r
\r
}\r
\r
\r
- } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_DIRECT) {\r
+ } else if ( (route->PduR_GatewayMode == 1) && (route->PduRDestPdu.DataProvision == PDUR_DIRECT) ) {\r
// The route is using a direct data provision fifo. PDUR259\r
DEBUG(DEBUG_LOW,"\tUsing gateway mode with direct data provision.\n", PduId);\r
\r
}\r
}\r
}\r
+ } else {\r
+ // Nothing to be done.\r
}\r
}\r
\r
// Find out if this is a gateway or ordinary trigger.\r
//if (route->PduRDestPdu.DataProvision == PDUR_NO_PROVISION) { // This is an ordinary trigger.\r
if (route->PduR_GatewayMode == 0) { // This is an ordinary trigger.\r
+ // 534 PC-Lint (ignoring return value) ticket #134:\r
route->FctPtrs.TargetTriggerTransmitFctPtr(route->PduRDestPdu.DestPduId, SduPtr);\r
\r
- } else if (route->PduR_GatewayMode == 1 && route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) { // The route is using a trigger transmit fifo. PDUR256\r
+ } else if ( (route->PduR_GatewayMode == 1) && (route->PduRDestPdu.DataProvision == PDUR_TRIGGER_TRANSMIT) ) { // The route is using a trigger transmit fifo. PDUR256\r
DEBUG(DEBUG_LOW,"\tUsing gateway mode with trigger transmit data provision.\n", PduId);\r
memcpy((void *)SduPtr, (void *)route->PduRDestPdu.TxBufferRef->First, sizeof(uint8) * route->SduLength);\r
\r
+ } else {\r
+ // Nothing to be done.\r
}\r
}\r
\r
\r
void PduR_LinIfRxIndication(PduIdType LinRxPduId, const uint8* LinSduPtr) {\r
#if (PDUR_LINIF_SUPPORT == STD_ON)\r
- DevCheck(LinRxPduId,LinSduPtr,0x0e);\r
+ PduR_DevCheck(LinRxPduId,LinSduPtr,0x0e);\r
\r
DEBUG(DEBUG_LOW,"----------------------\n");\r
DEBUG(DEBUG_LOW,"PduR_LinIfRxIndication: received indication with id %d and data %d\n", LinRxPduId, *LinSduPtr);\r
\r
void PduR_LinIfTxConfirmation(PduIdType LinTxPduId) {\r
#if (PDUR_LINIF_SUPPORT == STD_ON)\r
- DevCheck(LinTxPduId,1,0x0f);\r
+ PduR_DevCheck(LinTxPduId,1,0x0f);\r
\r
DEBUG(DEBUG_LOW,"----------------------\n");\r
DEBUG(DEBUG_LOW,"PduR_LinIfTxConfirmation: received confirmation with id %d\n", LinTxPduId);\r
\r
void PduR_LinIfTriggerTransmit(PduIdType LinTxPduId, uint8* LinSduPtr) {\r
#if (PDUR_LINIF_SUPPORT == STD_ON)\r
- DevCheck(LinTxPduId,LinSduPtr,0x10);\r
+ PduR_DevCheck(LinTxPduId,LinSduPtr,0x10);\r
\r
DEBUG(DEBUG_LOW,"----------------------\n");\r
DEBUG(DEBUG_LOW,"PduR_LinIfTriggerTransmit: received request with id %d\n", LinTxPduId);\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+// 904 PC-Lint: OK. Allow VALIDATE, VALIDATE_RV and VALIDATE_NO_RV to return value.\r
+//lint -emacro(904,VALIDATE_RV,VALIDATE_NO_RV,VALIDATE)\r
\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DCM054.Partially */ /** @req DCM055.Partially */ /** @req DCM110 */ /** @req DCM107 */ /** @req DCM332 */\r
+/** @req DCM012 */ /** @req DCM044 */ /** @req DCM364 */ /** @req DCM041 */\r
+/** @req DCM042 */ /** @req DCM049 */\r
+/** @req DCM033 */\r
+/** @req DCM171 */\r
+/** @req DCM333 */ /** @req DCM334 */\r
+/** @req DCM018 */\r
+/** @req DCM048 */\r
+ /** @req DCM040.Uninit */\r
+ /** @req DCM040.Param */\r
+ /** @req DCM043 */\r
+ /** @req DCM048 */\r
\r
#include <string.h>\r
#include "Dcm.h"\r
#include "Dcm_Internal.h"\r
#include "Dem.h"\r
-#include "Det.h"\r
#include "MemMap.h"\r
//#include "SchM_Dcm.h"\r
-#include "ComM_Dcm.h"\r
+//#include "ComM_Dcm.h"\r
#include "PduR_Dcm.h"\r
#include "ComStack_Types.h"\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
\r
// State variable\r
typedef enum\r
DCM_INITIALIZED\r
} Dcm_StateType;\r
\r
+//lint -esym(551,dcmState) PC-Lint - Turn of warning of dcmState not accessed when having DCM_DEV_ERROR_DETECT to STD_OFF\r
static Dcm_StateType dcmState = DCM_UNINITIALIZED;\r
\r
-#if (DCM_VERSION_INFO_API == STD_ON)\r
-static Std_VersionInfoType _Dcm_VersionInfo =\r
-{\r
- .vendorID = (uint16)1,\r
- .moduleID = (uint16)1,\r
- .instanceID = (uint8)1,\r
- .sw_major_version = (uint8)DCM_SW_MAJOR_VERSION,\r
- .sw_minor_version = (uint8)DCM_SW_MINOR_VERSION,\r
- .sw_patch_version = (uint8)DCM_SW_PATCH_VERSION,\r
- .ar_major_version = (uint8)DCM_AR_MAJOR_VERSION,\r
- .ar_minor_version = (uint8)DCM_AR_MINOR_VERSION,\r
- .ar_patch_version = (uint8)DCM_AR_PATCH_VERSION,\r
-};\r
-#endif /* DCM_VERSION_INFO_API */\r
-\r
-\r
\r
/*********************************************\r
* Interface for upper layer modules (8.3.1) *\r
* Procedure: Dcm_GetVersionInfo\r
* Reentrant: Yes\r
*/\r
-#if (DCM_VERSION_INFO_API == STD_ON)\r
-void Dcm_GetVersionInfo(Std_VersionInfoType *versionInfo) {\r
- memcpy(versionInfo, &_Dcm_VersionInfo, sizeof(Std_VersionInfoType));\r
-}\r
-#endif /* DCM_VERSION_INFO_API */\r
-\r
+// Defined in Dcm.h\r
\r
\r
/*\r
* Procedure: Dcm_Init\r
* Reentrant: No\r
*/\r
-void Dcm_Init(void)\r
+void Dcm_Init(void) /** @req DCM037 */\r
{\r
- if ((DCM_Config.Dsl == NULL) || (DCM_Config.Dsd == NULL) || (DCM_Config.Dsp == NULL)) {\r
-#if (DCM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DCM, 0, DCM_INIT_ID, DCM_E_CONFIG_INVALID);\r
-#endif\r
+ VALIDATE_NO_RV((DCM_Config.Dsl != NULL) && (DCM_Config.Dsd != NULL) && (DCM_Config.Dsp != NULL), DCM_INIT_ID, DCM_E_CONFIG_INVALID);\r
\r
- }\r
- else {\r
- DslInit();\r
- DsdInit();\r
- DspInit();\r
+ DslInit();\r
+ DsdInit();\r
+ DspInit();\r
\r
- dcmState = DCM_INITIALIZED;\r
- }\r
+ dcmState = DCM_INITIALIZED;\r
\r
return;\r
}\r
/*\r
* Interface for basic software scheduler\r
*/\r
-void Dcm_MainFunction(void)\r
+void Dcm_MainFunction(void) /** @req DCM362 */\r
{\r
+ VALIDATE_NO_RV(dcmState == DCM_INITIALIZED, DCM_MAIN_ID, DCM_E_UNINIT);\r
+\r
DsdMain();\r
DspMain();\r
DslMain();\r
}\r
\r
+\r
/***********************************************\r
* Interface for BSW modules and SW-Cs (8.3.2) *\r
***********************************************/\r
BufReq_ReturnType Dcm_ProvideRxBuffer(PduIdType dcmRxPduId, PduLengthType tpSduLength, PduInfoType **pduInfoPtr)\r
{\r
- BufReq_ReturnType returnCode = BUFREQ_OK;\r
+ BufReq_ReturnType returnCode;\r
+\r
+ VALIDATE_RV(dcmState == DCM_INITIALIZED, DCM_PROVIDE_RX_BUFFER_ID, DCM_E_UNINIT, BUFREQ_NOT_OK);\r
+ VALIDATE_RV(dcmRxPduId < DCM_DSL_RX_PDU_ID_LIST_LENGTH, DCM_PROVIDE_RX_BUFFER_ID, DCM_E_PARAM, BUFREQ_NOT_OK);\r
\r
+ //lint --e(929) // PC-Lint exception, MISRA 11.4 Ok by atosar\r
+ //lint --e(960) // PC-Lint exception, MISRA 11.5 Ok by atosar\r
returnCode = DslProvideRxBufferToPdur(dcmRxPduId, tpSduLength, (const PduInfoType**)pduInfoPtr);\r
\r
return returnCode;\r
\r
void Dcm_RxIndication(PduIdType dcmRxPduId, NotifResultType result)\r
{\r
+ VALIDATE_NO_RV(dcmState == DCM_INITIALIZED, DCM_RX_INDICATION_ID, DCM_E_UNINIT);\r
+ VALIDATE_NO_RV(dcmRxPduId < DCM_DSL_RX_PDU_ID_LIST_LENGTH, DCM_RX_INDICATION_ID, DCM_E_PARAM);\r
+\r
DslRxIndicationFromPduR(dcmRxPduId, result);\r
}\r
\r
\r
-Std_ReturnType Dcm_GetActiveProtocol(Dcm_ProtocolType *protocolId)\r
+Std_ReturnType Dcm_GetActiveProtocol(Dcm_ProtocolType *activeProtocol)\r
{\r
- Std_ReturnType returnCode = E_OK;\r
+ Std_ReturnType returnCode;\r
+\r
+ VALIDATE_RV(dcmState == DCM_INITIALIZED, DCM_GET_ACTIVE_PROTOCOL_ID, DCM_E_UNINIT, E_NOT_OK);\r
\r
- returnCode = DslGetActiveProtocol(protocolId);\r
+ returnCode = DslGetActiveProtocol(activeProtocol);\r
\r
return returnCode;\r
}\r
\r
Std_ReturnType Dcm_GetSecurityLevel(Dcm_SecLevelType *secLevel)\r
{\r
- Std_ReturnType returnCode = E_OK;\r
+ Std_ReturnType returnCode;\r
+\r
+ VALIDATE_RV(dcmState == DCM_INITIALIZED, DCM_GET_SECURITY_LEVEL_ID, DCM_E_UNINIT, E_NOT_OK);\r
\r
returnCode = DslGetSecurityLevel(secLevel);\r
\r
\r
Std_ReturnType Dcm_GetSesCtrlType(Dcm_SesCtrlType *sesCtrlType)\r
{\r
- Std_ReturnType returnCode = E_OK;\r
+ Std_ReturnType returnCode;\r
+\r
+ VALIDATE_RV(dcmState == DCM_INITIALIZED, DCM_GET_SES_CTRL_TYPE_ID, DCM_E_UNINIT, E_NOT_OK);\r
\r
returnCode = DslGetSesCtrlType(sesCtrlType);\r
\r
\r
BufReq_ReturnType Dcm_ProvideTxBuffer(PduIdType dcmTxPduId, PduInfoType **pduInfoPtr, PduLengthType length)\r
{\r
- BufReq_ReturnType returnCode = BUFREQ_OK;\r
+ BufReq_ReturnType returnCode;\r
\r
+ VALIDATE_RV(dcmState == DCM_INITIALIZED, DCM_PROVIDE_TX_BUFFER_ID, DCM_E_UNINIT, BUFREQ_NOT_OK);\r
+ VALIDATE_RV(dcmTxPduId < DCM_DSL_TX_PDU_ID_LIST_LENGTH, DCM_PROVIDE_TX_BUFFER_ID, DCM_E_PARAM, BUFREQ_NOT_OK);\r
+\r
+ //lint --e(929) // PC-Lint exception, MISRA 11.4 Ok by atosar\r
+ //lint --e(960) // PC-Lint exception, MISRA 11.5 Ok by atosar\r
returnCode = DslProvideTxBuffer(dcmTxPduId, (const PduInfoType**)pduInfoPtr, length);\r
\r
return returnCode;\r
\r
void Dcm_TxConfirmation(PduIdType dcmTxPduId, NotifResultType result)\r
{\r
+ VALIDATE_NO_RV(dcmState == DCM_INITIALIZED, DCM_TX_CONFIRMATION_ID, DCM_E_UNINIT);\r
+ VALIDATE_NO_RV(dcmTxPduId < DCM_DSL_TX_PDU_ID_LIST_LENGTH, DCM_TX_CONFIRMATION_ID, DCM_E_PARAM);\r
+\r
DslTxConfirmation(dcmTxPduId, result);\r
}\r
\r
\r
\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DCM600 */ // Generated by BSW builder\r
+\r
+\r
#include <string.h>\r
#include "Dcm.h"\r
#include "Dcm_Internal.h"\r
-#include "Det.h"\r
#include "MemMap.h"\r
\r
typedef struct {\r
static boolean suppressPosRspMsg;\r
\r
/*\r
- * Local functions
+ * Local functions\r
*/\r
\r
\r
-static boolean askApplicationForServicePermission(uint8 *requestData, uint16 dataSize)\r
+static Std_ReturnType askApplicationForServicePermission(uint8 *requestData, uint16 dataSize)\r
{\r
Std_ReturnType returnCode = E_OK;\r
const Dcm_DslServiceRequestIndicationType *serviceRequestIndication = DCM_Config.Dsl->DslServiceRequestIndication;\r
Std_ReturnType result;\r
\r
- while (!serviceRequestIndication->Arc_EOL && (returnCode != E_REQUEST_NOT_ACCEPTED)) {\r
+ while ((!serviceRequestIndication->Arc_EOL) && (returnCode != E_REQUEST_NOT_ACCEPTED)) {\r
if (serviceRequestIndication->Indication != NULL) {\r
result = serviceRequestIndication->Indication(requestData, dataSize);\r
- if (result != E_OK)\r
+ if (result != E_OK){\r
returnCode = result;\r
+ }\r
}\r
serviceRequestIndication++;\r
}\r
static void createAndSendNcr(Dcm_NegativeResponseCodeType responseCode)\r
{\r
if (!((msgData.addrType == DCM_PROTOCOL_FUNCTIONAL_ADDR_TYPE)\r
- && ((responseCode == DCM_E_SERVICENOTSUPPORTED) || (responseCode == DCM_E_SUBFUNCTIONNOTSUPPORTED) || (responseCode == DCM_E_REQUESTOUTOFRANGE)))) { /** @req DCM001 **/\r
+ && ((responseCode == DCM_E_SERVICENOTSUPPORTED) || (responseCode == DCM_E_SUBFUNCTIONNOTSUPPORTED) || (responseCode == DCM_E_REQUESTOUTOFRANGE)))) { /** @req DCM001 */\r
msgData.pduTxData->SduDataPtr[0] = SID_NEGATIVE_RESPONSE;\r
msgData.pduTxData->SduDataPtr[1] = currentSid;\r
msgData.pduTxData->SduDataPtr[2] = responseCode;\r
msgData.pduTxData->SduLength = 3;\r
- DslDsdProcessingDone(msgData.rxPduId, DSD_TX_RESPONSE_READY); /** @req DCM114 **/ /** @req DCM232.1 **/\r
+ DslDsdProcessingDone(msgData.rxPduId, DSD_TX_RESPONSE_READY); /** @req DCM114 */ /** @req DCM232.Ncr */\r
}\r
else {\r
DslDsdProcessingDone(msgData.rxPduId, DSD_TX_RESPONSE_SUPPRESSED);\r
\r
static void selectServiceFunction(uint8 sid)\r
{\r
- switch (sid) /** @req DCM221 **/\r
+ /** @req DCM442.Partially */\r
+ switch (sid) /** @req DCM221 */\r
{\r
case SID_DIAGNOSTIC_SESSION_CONTROL:\r
DspUdsDiagnosticSessionControl(msgData.pduRxData, msgData.pduTxData);\r
boolean returnStatus = TRUE;\r
const Dcm_DsdServiceType *service = msgData.serviceTable->DsdService;\r
\r
- while ((service->DsdSidTabServiceId != sid) && !service->Arc_EOL) {\r
+ while ((service->DsdSidTabServiceId != sid) && (!service->Arc_EOL)) {\r
service++;\r
}\r
\r
\r
\r
/*\r
- * Exported functions
+ * Exported functions\r
*/\r
\r
void DsdInit(void)\r
Std_ReturnType result;\r
const Dcm_DsdServiceType *sidConfPtr = NULL;\r
\r
- currentSid = msgData.pduRxData->SduDataPtr[0]; /** @req DCM198 **/\r
+ currentSid = msgData.pduRxData->SduDataPtr[0]; /** @req DCM198 */\r
\r
- /** @req DCM178 **/\r
- if (DCM_RESPOND_ALL_REQUEST || ((currentSid & 0x7F) < 0x40)) { /** @req DCM084 **/\r
- if (lookupSid(currentSid, &sidConfPtr)) { /** @req DCM192 **/ /** @req DCM193 **/ /** @req DCM196 **/\r
+ /** @req DCM178 */\r
+ //lint --e(506, 774) PC-Lint exception Misra 13.7, 14.1 Allow configuration variables in boolean expression\r
+ if ((DCM_RESPOND_ALL_REQUEST == STD_ON) || ((currentSid & 0x7Fu) < 0x40)) { /** @req DCM084 */\r
+ if (lookupSid(currentSid, &sidConfPtr)) { /** @req DCM192 */ /** @req DCM193 */ /** @req DCM196 */\r
// SID found!\r
- if (DspCheckSessionLevel(sidConfPtr->DsdSidTabSessionLevelRef)) { /** @req DCM211 **/\r
- if (DspCheckSecurityLevel(sidConfPtr->DsdSidTabSecurityLevelRef)) { /** @req DCM217 **/\r
- if (DCM_REQUEST_INDICATION_ENABLED) { /** @req DCM218 **/\r
+ if (DspCheckSessionLevel(sidConfPtr->DsdSidTabSessionLevelRef)) { /** @req DCM211 */\r
+ if (DspCheckSecurityLevel(sidConfPtr->DsdSidTabSecurityLevelRef)) { /** @req DCM217 */\r
+ //lint --e(506, 774) PC-Lint exception Misra 13.7, 14.1 Allow configuration variables in boolean expression\r
+ if (DCM_REQUEST_INDICATION_ENABLED == STD_ON) { /** @req DCM218 */\r
result = askApplicationForServicePermission(msgData.pduRxData->SduDataPtr, msgData.pduRxData->SduLength);\r
+ } else {\r
+ result = E_OK;\r
}\r
- if (!DCM_REQUEST_INDICATION_ENABLED || result == E_OK) {\r
+ //lint --e(506, 774) PC-Lint exception Misra 13.7, 14.1 Allow configuration variables in boolean expression\r
+ if (result == E_OK) {\r
// Yes! All conditions met!\r
// Check if response shall be suppressed\r
- if (sidConfPtr->DsdSidTabSubfuncAvail && (msgData.pduRxData->SduDataPtr[1] & SUPPRESS_POS_RESP_BIT)) { /** @req DCM204 **/\r
- suppressPosRspMsg = TRUE; /** @req DCM202 **/\r
- msgData.pduRxData->SduDataPtr[1] &= ~SUPPRESS_POS_RESP_BIT; /** @req DCM201 **/\r
+ if ( (sidConfPtr->DsdSidTabSubfuncAvail) && (msgData.pduRxData->SduDataPtr[1] & SUPPRESS_POS_RESP_BIT) ) { /** @req DCM204 */\r
+ suppressPosRspMsg = TRUE; /** @req DCM202 */\r
+ msgData.pduRxData->SduDataPtr[1] &= ~SUPPRESS_POS_RESP_BIT; /** @req DCM201 */\r
}\r
else\r
{\r
- suppressPosRspMsg = FALSE; /** @req DCM202 **/\r
+ suppressPosRspMsg = FALSE; /** @req DCM202 */\r
}\r
selectServiceFunction(currentSid);\r
}\r
else {\r
if (result == E_REQUEST_ENV_NOK) {\r
- createAndSendNcr(DCM_E_CONDITIONSNOTCORRECT); /** @req DCM463 **/\r
+ createAndSendNcr(DCM_E_CONDITIONSNOTCORRECT); /** @req DCM463 */\r
}\r
else {\r
- // Do not send any response /** @req DCM462 **/\r
+ // Do not send any response /** @req DCM462 */\r
DslDsdProcessingDone(msgData.rxPduId, DSD_TX_RESPONSE_SUPPRESSED);\r
}\r
}\r
}\r
else {\r
- createAndSendNcr(DCM_E_SECUTITYACCESSDENIED); /** @req DCM217 **/\r
+ createAndSendNcr(DCM_E_SECUTITYACCESSDENIED); /** @req DCM217 */\r
}\r
}\r
else {\r
- createAndSendNcr(DCM_E_SERVICENOTSUPPORTEDINACTIVESESSION); /** @req DCM211 **/\r
+ createAndSendNcr(DCM_E_SERVICENOTSUPPORTEDINACTIVESESSION); /** @req DCM211 */\r
}\r
}\r
else {\r
- createAndSendNcr(DCM_E_SERVICENOTSUPPORTED); /** @req DCM197 **/\r
+ createAndSendNcr(DCM_E_SERVICENOTSUPPORTED); /** @req DCM197 */\r
}\r
}\r
else {\r
}\r
\r
\r
+\r
void DsdDspProcessingDone(Dcm_NegativeResponseCodeType responseCode)\r
{\r
if (responseCode == DCM_E_POSITIVERESPONSE) {\r
- if (!suppressPosRspMsg) { /** @req DCM200 **/ /** @req DCM231 **/\r
- /** @req DCM222 **/\r
- msgData.pduTxData->SduDataPtr[0] = currentSid | SID_RESPONSE_BIT; /** @req DCM223 **/ /** @req DCM224 **/\r
- DslDsdProcessingDone(msgData.rxPduId, DSD_TX_RESPONSE_READY); /** @req DCM114 **/ /** @req DCM225 **/ /** @req DCM232.2 **/\r
+ if (!suppressPosRspMsg) { /** @req DCM200 */ /** @req DCM231 */\r
+ /** @req DCM222 */\r
+ msgData.pduTxData->SduDataPtr[0] = currentSid | SID_RESPONSE_BIT; /** @req DCM223 */ /** @req DCM224 */\r
+ DslDsdProcessingDone(msgData.rxPduId, DSD_TX_RESPONSE_READY); /** @req DCM114 */ /** @req DCM225 */ /** @req DCM232.Ok */\r
}\r
else {\r
- DspDcmConfirmation(msgData.txPduId); /** @req DCM236 **/ /** @req DCM240 **/\r
+ DspDcmConfirmation(msgData.txPduId); /** @req DCM236 */ /** @req DCM240 */\r
DslDsdProcessingDone(msgData.rxPduId, DSD_TX_RESPONSE_SUPPRESSED);\r
}\r
}\r
else {\r
- createAndSendNcr(responseCode); /** @req DCM228 **/\r
+ createAndSendNcr(responseCode); /** @req DCM228 */\r
}\r
\r
}\r
\r
void DsdDataConfirmation(PduIdType confirmPduId, NotifResultType result)\r
{\r
- DspDcmConfirmation(confirmPduId); /** @req DCM236 **/\r
+ (void)result; /* Currently not used */\r
+ DspDcmConfirmation(confirmPduId); /** @req DCM236 */\r
}\r
\r
\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DCM030 */\r
+\r
+\r
#include <string.h>\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
#include "Dcm.h"\r
#include "Dcm_Internal.h"\r
-#include "Det.h"\r
#include "MemMap.h"\r
+#if defined(USE_COMM)\r
#include "ComM_Dcm.h"\r
+#endif\r
#include "PduR_Dcm.h"\r
#include "ComStack_Types.h"\r
//#define USE_DEBUG_PRINTF\r
#include "debug.h"\r
\r
-#define DECREMENT(timer) { if (timer > 0) timer--; }\r
+#define DECREMENT(timer) { if (timer > 0){timer--;} }\r
#define DCM_CONVERT_MS_TO_MAIN_CYCLES(x) ((x)/DCM_MAIN_FUNCTION_PERIOD_TIME_MS)\r
\r
\r
+#if (DCM_PAGEDBUFFER_ENABLED)\r
+#error "DCM_PAGEDBUFFER_ENABLED is set to STD_ON, this is not supported by the code."\r
+#endif\r
+\r
/*\r
* Type definitions.\r
*/\r
-typedef struct {\r
- const Dcm_DslProtocolRxType *protocolRx;\r
- const Dcm_DslMainConnectionType *mainConnection;\r
- const Dcm_DslConnectionType *connection;\r
- const Dcm_DslProtocolRowType *protocolRow;\r
-} DcmDsl_ProtocolConfigurationType;\r
-\r
-#define MAX_PARALLEL_PROTOCOLS_ALLOWED 1\r
+// #define MAX_PARALLEL_PROTOCOLS_ALLOWED 1\r
\r
typedef struct {\r
boolean initRun;\r
//boolean diagnosticRequestPending; // This is a "semaphore" because DSD and DCM can handle multiple/parallel request at the moment.\r
- const Dcm_DslProtocolRowType *preemptedProtocol; // Points to the currently active protocol.\r
const Dcm_DslProtocolRowType *activeProtocol; // Points to the currently active protocol.\r
- Dcm_DslRunTimeProtocolParametersType\r
- protocolList[MAX_PARALLEL_PROTOCOLS_ALLOWED];\r
+// const Dcm_DslProtocolRowType *preemptedProtocol; // Points to the currently active protocol - reserved for future use\r
+// Dcm_DslRunTimeProtocolParametersType protocolList[MAX_PARALLEL_PROTOCOLS_ALLOWED]; // Reserved for future use\r
} DcmDsl_RunTimeDataType;\r
\r
static DcmDsl_RunTimeDataType DcmDslRunTimeData = {\r
.initRun = FALSE,\r
- .preemptedProtocol = NULL,\r
- .activeProtocol = NULL };\r
-\r
-// ################# DUMMIES START #################\r
-\r
-/*\r
- * Local types\r
- */\r
-\r
-void ComM_DCM_ActivateDiagnostic() {\r
- ;\r
-}\r
-\r
-void ComM_DCM_InactivateDiagnostic() {\r
- ;\r
-}\r
+ .activeProtocol = NULL\r
+// .preemptedProtocol = NULL,\r
+// .protocolList = {}\r
+};\r
\r
// ################# HELPER FUNCTIONS START #################\r
\r
//\r
// This function reset/stars the session (S3) timer. See requirement\r
-// @DCM141 when that action should be taken.\r
+// DCM141 when that action should be taken.\r
//\r
static inline void startS3SessionTimer(Dcm_DslRunTimeProtocolParametersType *runtime, const Dcm_DslProtocolRowType *protocolRow) {\r
const Dcm_DslProtocolTimingRowType *timeParams;\r
\r
//\r
// This function reset/stars the session (S3) timer. See requirement\r
-// @DCM141 when that action should be taken.\r
+// DCM141 when that action should be taken.\r
//\r
static inline void stopS3SessionTimer(Dcm_DslRunTimeProtocolParametersType *runtime) {\r
runtime->S3ServerTimeoutCount = 0;\r
// - - - - - - - - - - -\r
\r
//\r
-// This function implements the requirement @DCM139 when\r
+// This function implements the requirement DCM139 when\r
// transition from one session to another.\r
//\r
-static void changeDiagnosticSession(Dcm_DslRunTimeProtocolParametersType *runtime,\r
- Dcm_SesCtrlType newSession) {\r
+static void changeDiagnosticSession(Dcm_DslRunTimeProtocolParametersType *runtime, Dcm_SesCtrlType newSession) {\r
\r
- /** @req DCM139 **/\r
+ /** @req DCM139 */\r
\r
switch (runtime->sessionControl) {\r
case DCM_DEFAULT_SESSION: // "default".\r
break;\r
\r
default:\r
- // TODO: Log this error.\r
- DEBUG(DEBUG_MEDIUM, "Old session invalid")\r
+ DET_REPORTERROR(MODULE_ID_DCM, 0, DCM_CHANGE_DIAGNOSTIC_SESSION_ID, DCM_E_PARAM);\r
+ DEBUG(DEBUG_MEDIUM, "Old session invalid");\r
break;\r
}\r
\r
break;\r
\r
default:\r
- // TODO: Log this error.\r
- DEBUG(DEBUG_MEDIUM, "New session invalid")\r
+ DET_REPORTERROR(MODULE_ID_DCM, 0, DCM_CHANGE_DIAGNOSTIC_SESSION_ID, DCM_E_PARAM);\r
+ DEBUG(DEBUG_MEDIUM, "New session invalid");\r
break;\r
}\r
}\r
\r
// - - - - - - - - - - -\r
\r
-void DslResetSessionTimeoutTimer() {\r
- const Dcm_DslProtocolRowType *activeProtocol = NULL;\r
- Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
+void DslResetSessionTimeoutTimer(void) {\r
+ const Dcm_DslProtocolRowType *activeProtocol;\r
+ Dcm_DslRunTimeProtocolParametersType *runtime;\r
+\r
activeProtocol = DcmDslRunTimeData.activeProtocol;\r
runtime = activeProtocol->DslRunTimeProtocolParameters;\r
- startS3SessionTimer(runtime, activeProtocol); // @DCM141\r
+ startS3SessionTimer(runtime, activeProtocol); /** @req DCM141 */\r
}\r
\r
// - - - - - - - - - - -\r
\r
-void DslGetCurrentServiceTable(const Dcm_DsdServiceTableType **currentServiceTable) {\r
- const Dcm_DslProtocolRowType *activeProtocol = NULL;\r
+void DslGetCurrentServiceTable(const Dcm_DsdServiceTableType **currentServiceTable) { /** @req DCM195 */\r
+ const Dcm_DslProtocolRowType *activeProtocol;\r
+\r
activeProtocol = DcmDslRunTimeData.activeProtocol;\r
if (activeProtocol != NULL) {\r
*currentServiceTable = activeProtocol->DslProtocolSIDTable;\r
\r
// - - - - - - - - - - -\r
\r
-Std_ReturnType DslGetActiveProtocol(Dcm_ProtocolType *protocolId) { /** @req DCM340 **/\r
+Std_ReturnType DslGetActiveProtocol(Dcm_ProtocolType *protocolId) { /** @req DCM340 */\r
Std_ReturnType ret = E_NOT_OK;\r
- const Dcm_DslProtocolRowType *activeProtocol = NULL;\r
+ const Dcm_DslProtocolRowType *activeProtocol;\r
+\r
activeProtocol = DcmDslRunTimeData.activeProtocol;\r
if (activeProtocol != NULL) {\r
*protocolId = activeProtocol->DslProtocolID;\r
\r
// - - - - - - - - - - -\r
\r
-void DslSetSecurityLevel(Dcm_SecLevelType secLevel) { /** @req DCM020 **/\r
- const Dcm_DslProtocolRowType *activeProtocol = NULL;\r
- Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
+void DslSetSecurityLevel(Dcm_SecLevelType secLevel) { /** @req DCM020 */\r
+ const Dcm_DslProtocolRowType *activeProtocol;\r
+ Dcm_DslRunTimeProtocolParametersType *runtime;\r
+\r
activeProtocol = DcmDslRunTimeData.activeProtocol;\r
runtime = activeProtocol->DslRunTimeProtocolParameters;\r
runtime->securityLevel = secLevel;\r
\r
// - - - - - - - - - - -\r
\r
-Std_ReturnType DslGetSecurityLevel(Dcm_SecLevelType *secLevel) { /** @req DCM020 **//** @req DCM338 **/\r
+Std_ReturnType DslGetSecurityLevel(Dcm_SecLevelType *secLevel) { /** @req DCM020 *//** @req DCM338 */\r
Std_ReturnType ret = E_NOT_OK;\r
- const Dcm_DslProtocolRowType *activeProtocol = NULL;\r
+ const Dcm_DslProtocolRowType *activeProtocol;\r
Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
+\r
activeProtocol = DcmDslRunTimeData.activeProtocol;\r
if (activeProtocol != NULL) {\r
runtime = activeProtocol->DslRunTimeProtocolParameters;\r
\r
// - - - - - - - - - - -\r
\r
-void DslSetSesCtrlType(Dcm_SesCtrlType sesCtrl) { /** @req DCM022 **/\r
- const Dcm_DslProtocolRowType *activeProtocol = NULL;\r
+void DslSetSesCtrlType(Dcm_SesCtrlType sesCtrl) { /** @req DCM022 */\r
+ const Dcm_DslProtocolRowType *activeProtocol;\r
Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
+\r
activeProtocol = DcmDslRunTimeData.activeProtocol;\r
if (activeProtocol != NULL) {\r
runtime = activeProtocol->DslRunTimeProtocolParameters;\r
\r
// - - - - - - - - - - -\r
\r
-Std_ReturnType DslGetSesCtrlType(Dcm_SesCtrlType *sesCtrlType) { /** @req DCM022 **//** @req DCM339 **/\r
+Std_ReturnType DslGetSesCtrlType(Dcm_SesCtrlType *sesCtrlType) { /** @req DCM022 *//** @req DCM339 */\r
Std_ReturnType ret = E_NOT_OK;\r
- const Dcm_DslProtocolRowType *activeProtocol = NULL;\r
+ const Dcm_DslProtocolRowType *activeProtocol;\r
Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
+\r
activeProtocol = DcmDslRunTimeData.activeProtocol;\r
if (activeProtocol != NULL) {\r
runtime = activeProtocol->DslRunTimeProtocolParameters;\r
imask_t state = McuE_EnterCriticalSection();\r
switch (responseResult) {\r
case DSD_TX_RESPONSE_READY:\r
- runtime->externalTxBufferStatus = DSD_PENDING_RESPONSE_SIGNALED; /** @req DCM114 **/\r
+ runtime->externalTxBufferStatus = DSD_PENDING_RESPONSE_SIGNALED; /** @req DCM114 */\r
break;\r
- case DSD_TX_RESPONSE_SUPPRESSED:\r
+ case DSD_TX_RESPONSE_SUPPRESSED: /** @req DCM238 */\r
DEBUG( DEBUG_MEDIUM, "DslDsdProcessingDone called with DSD_TX_RESPONSE_SUPPRESSED.\n");\r
releaseExternalRxTxBuffersHelper(rxPduIdRef);\r
break;\r
const Dcm_DslConnectionType *connection = NULL;\r
const Dcm_DslProtocolRowType *protocolRow = NULL;\r
Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
+ Std_ReturnType transmitResult;\r
\r
- /** @req DCM119 **/\r
+ /** @req DCM119 */\r
imask_t state = McuE_EnterCriticalSection();\r
if (findRxPduIdParentConfigurationLeafs(protocol->DslRunTimeProtocolParameters->diagReqestRxPduId, &protocolRx, &mainConnection, &connection, &protocolRow, &runtime)) {\r
if (runtime->localTxBuffer.status == NOT_IN_USE) {\r
runtime->localTxBuffer.PduInfo.SduDataPtr = runtime->localTxBuffer.buffer;\r
runtime->localTxBuffer.PduInfo.SduLength = 3;\r
runtime->localTxBuffer.status = DCM_TRANSMIT_SIGNALED; // In the DslProvideTxBuffer 'callback' this state signals it is the local buffer we are interested in sending.\r
- PduR_DcmTransmit(mainConnection->DslProtocolTx->DcmDslProtocolTxPduId, &(runtime->localTxBuffer.PduInfo));/** @req DCM115, the P2ServerMin has not been implemented. **/\r
+ transmitResult = PduR_DcmTransmit(mainConnection->DslProtocolTx->DcmDslProtocolTxPduId, &(runtime->localTxBuffer.PduInfo));/** @req DCM115.Partially */ /* The P2ServerMin has not been implemented. */\r
+ if (transmitResult != E_OK) {\r
+ // TODO: What to do here?\r
+ }\r
}\r
}\r
McuE_ExitCriticalSection(state);\r
uint16 i;\r
\r
for (i = 0; !DCM_Config.Dsl->DslCallbackDCMRequestService[i].Arc_EOL; i++) {\r
- if (DCM_Config.Dsl->DslCallbackDCMRequestService[i].StartProtocol\r
- != NULL) {\r
- ret = DCM_Config.Dsl->DslCallbackDCMRequestService[i]. StartProtocol(\r
- protocolId);\r
- if (ret != E_OK) { // qqq: eqvivalent to DCM_E_OK?\r
+ if (DCM_Config.Dsl->DslCallbackDCMRequestService[i].StartProtocol != NULL) {\r
+ ret = DCM_Config.Dsl->DslCallbackDCMRequestService[i]. StartProtocol(protocolId);\r
+ if (ret != E_OK) {\r
break;\r
}\r
}\r
static boolean isTesterPresentCommand(const PduInfoType *rxPdu) {\r
boolean ret = FALSE;\r
if ((rxPdu->SduDataPtr[0] == SID_TESTER_PRESENT) && (rxPdu->SduDataPtr[1] & SUPPRESS_POS_RESP_BIT)) {\r
- return TRUE;\r
+ ret = TRUE;\r
}\r
return ret;\r
}\r
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
// Implements 'void Dcm_Init(void)' for DSL.\r
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
-void DslInit(void) { /** @req DCM037 - for DSL submodule. **/\r
- const Dcm_DslProtocolRowType *listEntry = NULL;\r
+void DslInit(void) {\r
+ const Dcm_DslProtocolRowType *listEntry;\r
Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
\r
listEntry = DCM_Config.Dsl->DslProtocol->DslProtocolRowList;\r
runtime->externalTxBufferStatus = DCM_IDLE;\r
runtime->localRxBuffer.status = DCM_IDLE;\r
runtime->localTxBuffer.status = DCM_IDLE;\r
- runtime->securityLevel = DCM_SEC_LEV_LOCKED; /** @req DCM033 **/\r
- runtime->sessionControl = DCM_DEFAULT_SESSION;\r
+ runtime->securityLevel = DCM_SEC_LEV_LOCKED; /** @req DCM033 */\r
+ runtime->sessionControl = DCM_DEFAULT_SESSION; /** @req DCM034 */\r
listEntry->DslProtocolRxBufferID->externalBufferRuntimeData->status = BUFFER_AVAILABLE;\r
listEntry->DslProtocolRxBufferID->externalBufferRuntimeData->status = BUFFER_AVAILABLE;\r
listEntry++;\r
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
\r
void DslMain(void) {\r
- const Dcm_DslProtocolRowType *protocolRowEntry = NULL;\r
+ const Dcm_DslProtocolRowType *protocolRowEntry;\r
const Dcm_DslProtocolTimingRowType *timeParams = NULL;\r
Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
- int debug_count = 0;\r
\r
protocolRowEntry = DCM_Config.Dsl->DslProtocol->DslProtocolRowList;\r
while (protocolRowEntry->Arc_EOL == FALSE) {\r
if (runtime->sessionControl != DCM_DEFAULT_SESSION) { // Timeout if tester present is lost.\r
DECREMENT(runtime->S3ServerTimeoutCount);\r
if (runtime->S3ServerTimeoutCount == 0) {\r
- changeDiagnosticSession(runtime, DCM_DEFAULT_SESSION); /** @req DCM140 **/\r
+ changeDiagnosticSession(runtime, DCM_DEFAULT_SESSION); /** @req DCM140 */\r
}\r
}\r
switch (runtime->externalTxBufferStatus) { // #### TX buffer state. ####\r
if (DCM_Config.Dsl->DslDiagResp != NULL) {\r
if (DCM_Config.Dsl->DslDiagResp->DslDiagRespForceRespPendEn == TRUE) {\r
if (runtime->responsePendingCount != 0) {\r
- sendResponse(protocolRowEntry, DCM_E_RESPONSEPENDING); /** @req DCM024 **/\r
+ sendResponse(protocolRowEntry, DCM_E_RESPONSEPENDING); /** @req DCM024 */\r
DECREMENT( runtime->responsePendingCount );\r
} else {\r
- sendResponse(protocolRowEntry, DCM_E_GENERALREJECT); /** @req DCM120 **/\r
+ sendResponse(protocolRowEntry, DCM_E_GENERALREJECT); /** @req DCM120 */\r
releaseExternalRxTxBuffers(protocolRowEntry, runtime);\r
}\r
} else {\r
const Dcm_DslMainConnectionType *mainConnection = NULL;\r
const Dcm_DslConnectionType *connection = NULL;\r
const Dcm_DslProtocolRowType *protocolRow = NULL;\r
+ Std_ReturnType transmitResult;\r
+\r
if (findRxPduIdParentConfigurationLeafs(runtime->diagReqestRxPduId, &protocolRx, &mainConnection, &connection, &protocolRow, &runtime)) {\r
- const uint32 txPduId = mainConnection->DslProtocolTx->DcmDslProtocolTxPduId;\r
+ const PduIdType txPduId = mainConnection->DslProtocolTx->DcmDslProtocolTxPduId;\r
DEBUG( DEBUG_MEDIUM, "runtime->externalTxBufferStatus enter state DCM_TRANSMIT_SIGNALED.\n" );\r
runtime->externalTxBufferStatus = DCM_TRANSMIT_SIGNALED;\r
- PduR_DcmTransmit(txPduId, &runtime->diagnosticResponseFromDsd); /** @req DCM237 **//* Will trigger PduR (CanTP) to call DslProvideTxBuffer(). */\r
+ transmitResult = PduR_DcmTransmit(txPduId, &runtime->diagnosticResponseFromDsd); /** @req DCM237 *//* Will trigger PduR (CanTP) to call DslProvideTxBuffer(). */\r
+ if (transmitResult != E_OK) {\r
+ // TODO: What to do here?\r
+ }\r
} else {\r
DEBUG( DEBUG_MEDIUM, "***** WARNING, THIS IS UNEXPECTED !!! ********.\n" );\r
- const uint32 txPduId = protocolRowEntry->DslConnection->DslMainConnection->DslProtocolTx->DcmDslProtocolTxPduId;\r
+ const PduIdType txPduId = protocolRowEntry->DslConnection->DslMainConnection->DslProtocolTx->DcmDslProtocolTxPduId;\r
DEBUG( DEBUG_MEDIUM, "runtime->externalTxBufferStatus enter state DSD_PENDING_RESPONSE_SIGNALED.\n", txPduId);\r
runtime->externalTxBufferStatus = DCM_TRANSMIT_SIGNALED;\r
DEBUG( DEBUG_MEDIUM, "Calling PduR_DcmTransmit with txPduId = %d from DslMain\n", txPduId);\r
- PduR_DcmTransmit(txPduId, &runtime->diagnosticResponseFromDsd); /** @req DCM237 **//* Will trigger PduR (CanTP) to call DslProvideTxBuffer(). */\r
+ transmitResult = PduR_DcmTransmit(txPduId, &runtime->diagnosticResponseFromDsd); /** @req DCM237 *//* Will trigger PduR (CanTP) to call DslProvideTxBuffer(). */\r
+ if (transmitResult != E_OK) {\r
+ // TODO: What to do here?\r
+ }\r
}\r
}\r
break;\r
}\r
}\r
protocolRowEntry++;\r
- debug_count++;\r
}\r
}\r
\r
// received a FF or a single frame and needs to obtain a buffer from the\r
// receiver so that received data can be forwarded.\r
\r
-BufReq_ReturnType DslProvideRxBufferToPdur(PduIdType dcmRxPduId, /** @req DCM094 **/\r
- PduLengthType tpSduLength, const PduInfoType **pduInfoPtr) {\r
+BufReq_ReturnType DslProvideRxBufferToPdur(PduIdType dcmRxPduId, PduLengthType tpSduLength, const PduInfoType **pduInfoPtr) {\r
BufReq_ReturnType ret = BUFREQ_NOT_OK;\r
const Dcm_DslProtocolRxType *protocolRx = NULL;\r
const Dcm_DslMainConnectionType *mainConnection = NULL;\r
imask_t state = McuE_EnterCriticalSection();\r
if (findRxPduIdParentConfigurationLeafs(dcmRxPduId, &protocolRx, &mainConnection, &connection, &protocolRow, &runtime)) {\r
const Dcm_DslBufferType *externalRxBuffer = protocolRow->DslProtocolRxBufferID;\r
- if (externalRxBuffer->pduInfo.SduLength >= tpSduLength) { /** @req DCM443 **/\r
+ if (externalRxBuffer->pduInfo.SduLength >= tpSduLength) { /** @req DCM443 */\r
if ((runtime->externalRxBufferStatus == NOT_IN_USE) && (externalRxBuffer->externalBufferRuntimeData->status == BUFFER_AVAILABLE)) {\r
DEBUG( DEBUG_MEDIUM, "External buffer available!\n");\r
// ### EXTERNAL BUFFER IS AVAILABLE; GRAB IT AND REMEBER THAT WE OWN IT! ###\r
runtime->diagnosticRequestFromTester.SduDataPtr = externalRxBuffer->pduInfo.SduDataPtr;\r
runtime->diagnosticRequestFromTester.SduLength = tpSduLength;\r
*pduInfoPtr = &(runtime->diagnosticRequestFromTester);\r
- runtime->externalRxBufferStatus = PROVIDED_TO_PDUR; /** @req DCM342 **/\r
+ runtime->externalRxBufferStatus = PROVIDED_TO_PDUR; /** @req DCM342 */\r
ret = BUFREQ_OK;\r
} else {\r
DEBUG( DEBUG_MEDIUM, "Local buffer available!\n");\r
// The buffer is in use by the PduR, we can not help this because then\r
// we would have two different Rx-indications with same PduId but we\r
// will not know which buffer the indication should free.\r
- ret = BUFREQ_BUSY; /** @req DCM445 **/\r
+ ret = BUFREQ_BUSY; /** @req DCM445 */\r
}\r
}\r
} else {\r
- ret = BUFREQ_OVFL; /** @req DCM444 **/\r
+ ret = BUFREQ_OVFL; /** @req DCM444 */\r
}\r
if (ret == BUFREQ_OK) {\r
- stopS3SessionTimer(runtime); /** @req DCM141 **/\r
+ stopS3SessionTimer(runtime); /** @req DCM141 */\r
}\r
}\r
McuE_ExitCriticalSection(state);\r
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\r
// This function is called called by the PduR typically when CanTp has\r
// received the diagnostic request, copied it to the provided buffer and need to indicate\r
-// this to the DCM (DSL) module via propritary API.\r
+// this to the DCM (DSL) module via proprietary API.\r
\r
-void DslRxIndicationFromPduR(PduIdType dcmRxPduId, NotifResultType result) { /** @req DCM093 **/\r
+void DslRxIndicationFromPduR(PduIdType dcmRxPduId, NotifResultType result) {\r
const Dcm_DslProtocolRxType *protocolRx = NULL;\r
const Dcm_DslMainConnectionType *mainConnection = NULL;\r
const Dcm_DslConnectionType *connection = NULL;\r
Std_ReturnType higherLayerResp;\r
imask_t state;\r
\r
- /** @req DCM345, this needs to be verified when connection to CanIf works. **/\r
+ /** @req DCM345, this needs to be verified when connection to CanIf works. */\r
\r
if (findRxPduIdParentConfigurationLeafs(dcmRxPduId, &protocolRx, &mainConnection, &connection, &protocolRow, &runtime)) {\r
timeParams = protocolRow->DslProtocolTimeLimit;\r
// the Concurrent "Test Present" functionality.\r
state = McuE_EnterCriticalSection();\r
if (runtime->externalRxBufferStatus == PROVIDED_TO_PDUR) {\r
- if ( result == NTFRSLT_OK ) { /** @req DCM111 **/\r
+ if ( result == NTFRSLT_OK ) { /** @req DCM111 */\r
if (isTesterPresentCommand(&(protocolRow->DslProtocolRxBufferID->pduInfo))) {\r
- startS3SessionTimer(runtime, protocolRow); /** @req DCM141 **//** @req DCM112 **//** @req DCM113 **/\r
+ startS3SessionTimer(runtime, protocolRow); /** @req DCM141 *//** @req DCM112 *//** @req DCM113 */\r
runtime->externalRxBufferStatus = NOT_IN_USE;\r
protocolRow->DslProtocolRxBufferID->externalBufferRuntimeData->status = BUFFER_AVAILABLE;\r
} else {\r
if (runtime->protocolStarted == FALSE) {\r
- higherLayerResp = StartProtocolHelper(protocolRow->DslProtocolID); /** @req DCM036 **/\r
+ higherLayerResp = StartProtocolHelper(protocolRow->DslProtocolID); /** @req DCM036 */\r
if (higherLayerResp == E_OK) {\r
runtime->protocolStarted = TRUE;\r
DcmDslRunTimeData.activeProtocol = protocolRow;\r
}\r
if (runtime->protocolStarted == TRUE) {\r
if (runtime->diagnosticActiveComM == FALSE) {\r
- ComM_DCM_ActivateDiagnostic(); /* @DCM163 */\r
+#if defined(USE_COMM)\r
+ ComM_DCM_ActivateDiagnostic(); /** @req DCM163 */\r
+#endif\r
runtime->diagnosticActiveComM = TRUE;\r
}\r
timeParams = protocolRow->DslProtocolTimeLimit;\r
runtime->stateTimeoutCount = DCM_CONVERT_MS_TO_MAIN_CYCLES(timeParams->TimStrP2ServerMax); /* See 9.2.2. */\r
- runtime->externalRxBufferStatus = PROVIDED_TO_DSD; /** @req DCM241 **/\r
+ runtime->externalRxBufferStatus = PROVIDED_TO_DSD; /** @req DCM241 */\r
if (runtime->externalTxBufferStatus == NOT_IN_USE) {\r
DEBUG( DEBUG_MEDIUM, "External Tx buffer available, we can pass it to DSD.\n");\r
} else {\r
DEBUG( DEBUG_MEDIUM, "External buffer not available, a response is being transmitted?\n");\r
}\r
- runtime->externalTxBufferStatus = PROVIDED_TO_DSD; /** @req DCM241 **/\r
+ runtime->externalTxBufferStatus = PROVIDED_TO_DSD; /** @req DCM241 */\r
runtime->responsePendingCount = DCM_Config.Dsl->DslDiagResp->DslDiagRespMaxNumRespPend;\r
runtime->diagnosticResponseFromDsd.SduDataPtr = protocolRow->DslProtocolTxBufferID->pduInfo.SduDataPtr;\r
runtime->diagnosticResponseFromDsd.SduLength = protocolRow->DslProtocolTxBufferID->pduInfo.SduLength;\r
runtime->diagReqestRxPduId = dcmRxPduId;\r
DsdDslDataIndication( // qqq: We are inside a critical section.\r
&(runtime->diagnosticRequestFromTester),\r
- protocolRow->DslProtocolSIDTable,\r
+ protocolRow->DslProtocolSIDTable, /** @req DCM035 */\r
protocolRx->DslProtocolAddrType,\r
mainConnection->DslProtocolTx->DcmDslProtocolTxPduId,\r
&(runtime->diagnosticResponseFromDsd),\r
dcmRxPduId);\r
}\r
}\r
- } else { /** @req DCM344 **/\r
+ } else { /** @req DCM344 */\r
// The indication was not equal to NTFRSLT_OK, release the resources and no forward to DSD.\r
runtime->externalRxBufferStatus = NOT_IN_USE;\r
protocolRow->DslProtocolRxBufferID->externalBufferRuntimeData->status = BUFFER_AVAILABLE;\r
if (runtime->localRxBuffer.status == PROVIDED_TO_PDUR) {\r
if ( result == NTFRSLT_OK ) { // Make sure that the data in buffer is valid.\r
if (isTesterPresentCommand(&(runtime->localRxBuffer.PduInfo))) {\r
- startS3SessionTimer(runtime, protocolRow); /** @req DCM141 **//** @req DCM112 **//** @req DCM113 **/\r
+ startS3SessionTimer(runtime, protocolRow); /** @req DCM141 *//** @req DCM112 *//** @req DCM113 */\r
}\r
}\r
runtime->localRxBuffer.status = NOT_IN_USE;\r
// it has detected that the pending request has been answered by DSD\r
// (or any other module?).\r
\r
-BufReq_ReturnType DslProvideTxBuffer(PduIdType dcmTxPduId, const PduInfoType **pduInfoPtr, PduLengthType length) { /** @req DCM092 **/\r
+BufReq_ReturnType DslProvideTxBuffer(PduIdType dcmTxPduId, const PduInfoType **pduInfoPtr, PduLengthType length) {\r
BufReq_ReturnType ret = BUFREQ_NOT_OK;\r
const Dcm_DslProtocolTxType *protocolTx = NULL;\r
const Dcm_DslMainConnectionType *mainConnection = NULL;\r
const Dcm_DslProtocolRowType *protocolRow = NULL;\r
Dcm_DslRunTimeProtocolParametersType *runtime = NULL;\r
\r
+ (void)length; // Currently not used, this is only to remove compilation warnings\r
DEBUG( DEBUG_MEDIUM, "DslProvideTxBuffer=%d\n", dcmTxPduId);\r
if (findTxPduIdParentConfigurationLeafs(dcmTxPduId, &protocolTx, &mainConnection, &connection, &protocolRow, &runtime)) {\r
switch (runtime->externalTxBufferStatus) { // ### EXTERNAL TX BUFFER ###\r
case DCM_TRANSMIT_SIGNALED: {\r
- /** @req DCM346 - length verification is already done if this state is reached. **/\r
+ /** @req DCM346 */ /* Length verification is already done if this state is reached. */\r
*pduInfoPtr = &(protocolRow->DslProtocolTxBufferID->pduInfo);\r
- runtime->externalTxBufferStatus = PROVIDED_TO_PDUR; /** @req DCM349 **/\r
+ runtime->externalTxBufferStatus = PROVIDED_TO_PDUR; /** @req DCM349 */\r
ret = BUFREQ_OK;\r
break;\r
}\r
state = McuE_EnterCriticalSection();\r
switch (runtime->externalTxBufferStatus) { // ### EXTERNAL TX BUFFER ###\r
case PROVIDED_TO_PDUR: {\r
- ComM_DCM_InactivateDiagnostic();\r
- startS3SessionTimer(runtime, protocolRow); // @DCM141\r
- releaseExternalRxTxBuffers(protocolRow, runtime); /** @req DCM118 **//** @req DCM353 **//** @req DCM354 **/\r
+#if defined(USE_COMM)\r
+ ComM_DCM_InactivateDiagnostic(); /** @req DCM164 */\r
+#endif\r
+ startS3SessionTimer(runtime, protocolRow); /** @req DCM141 */\r
+ releaseExternalRxTxBuffers(protocolRow, runtime); /** @req DCM118 *//** @req DCM352 *//** @req DCM353 *//** @req DCM354 */\r
externalBufferReleased = TRUE;\r
DEBUG( DEBUG_MEDIUM, "Released external buffer OK!\n");\r
- DsdDataConfirmation(mainConnection->DslProtocolTx->DcmDslProtocolTxPduId, result); /** @req DCM117 **//** @req DCM235 **/\r
+ DsdDataConfirmation(mainConnection->DslProtocolTx->DcmDslProtocolTxPduId, result); /** @req DCM117 *//** @req DCM235 */\r
break;\r
}\r
default:\r
break;\r
}\r
- if (externalBufferReleased == FALSE) {\r
+ if (!externalBufferReleased) {\r
switch (runtime->localTxBuffer.status) { // ### LOCAL TX BUFFER ###\r
case PROVIDED_TO_PDUR:\r
DEBUG( DEBUG_MEDIUM, "Released local buffer buffer OK!\n");\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+//lint -esym(754, SID) //Structure member SID not used in udsReadDtcInfoSub_0x01_0x07_0x11_0x12() and udsReadDtcInfoSub_0x02_0x0A_0x0F_0x13_0x15()\r
\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DCM273 */ /** @req DCM272 */\r
+/** @req DCM039 */ /** @req DCM038 */ /** @req DCM269 */\r
+/** @req DCM271 */ /** @req DCM274 */ /** @req DCM275 */ /** @req DCM424 */\r
+/** @req DCM007 */\r
+\r
#include <string.h>\r
#include "Dcm.h"\r
#include "Dcm_Internal.h"\r
#include "Dem.h"\r
-#include "Det.h"\r
#include "MemMap.h"\r
+#if defined(USE_MCU)\r
#include "Mcu.h"\r
+#endif\r
\r
#define ZERO_SUB_FUNCTION 0x00\r
\r
/*\r
* Macros\r
*/\r
-#define BYTES_TO_DTC(hb, mb, lb) (((hb) << 16) | ((mb) << 8) | (lb))\r
-#define DTC_HIGH_BYTE(dtc) (((dtc)>> 16) & 0xFF)\r
-#define DTC_MID_BYTE(dtc) (((dtc)>> 8) & 0xFF)\r
-#define DTC_LOW_BYTE(dtc) ((dtc) & 0xFF)\r
+#define BYTES_TO_DTC(hb, mb, lb) (((uint32)(hb) << 16) | ((uint32)(mb) << 8) | (uint32)(lb))\r
+#define DTC_HIGH_BYTE(dtc) (((uint32)(dtc) >> 16) & 0xFFu)\r
+#define DTC_MID_BYTE(dtc) (((uint32)(dtc) >> 8) & 0xFFu)\r
+#define DTC_LOW_BYTE(dtc) ((uint32)(dtc) & 0xFFu)\r
\r
\r
typedef struct {\r
}\r
\r
\r
-boolean DspCheckSessionLevel(const Dcm_DspSessionRowType **sessionLevelRefTable)\r
+boolean DspCheckSessionLevel(Dcm_DspSessionRowType const* const* sessionLevelRefTable)\r
{\r
- boolean returnStatus = TRUE;\r
+ Std_ReturnType returnStatus;\r
+ boolean levelFound = FALSE;\r
Dcm_SesCtrlType currentSession;\r
\r
- DslGetSesCtrlType(¤tSession);\r
- while (((*sessionLevelRefTable)->DspSessionLevel != currentSession) && !(*sessionLevelRefTable)->Arc_EOL) {\r
- sessionLevelRefTable++;\r
- }\r
+ returnStatus = DslGetSesCtrlType(¤tSession);\r
+ if (returnStatus == E_OK) {\r
+ while ( ((*sessionLevelRefTable)->DspSessionLevel != currentSession) && (!(*sessionLevelRefTable)->Arc_EOL) ) {\r
+ sessionLevelRefTable++;\r
+ }\r
\r
- if ((*sessionLevelRefTable)->Arc_EOL) {\r
- returnStatus = FALSE;\r
+ if (!(*sessionLevelRefTable)->Arc_EOL) {\r
+ levelFound = TRUE;\r
+ }\r
}\r
\r
- return returnStatus;\r
+ return levelFound;\r
}\r
\r
\r
-boolean DspCheckSecurityLevel(const Dcm_DspSecurityRowType **securityLevelRefTable)\r
+boolean DspCheckSecurityLevel(Dcm_DspSecurityRowType const* const* securityLevelRefTable)\r
{\r
- boolean returnStatus = TRUE;\r
+ Std_ReturnType returnStatus;\r
+ boolean levelFound = FALSE;\r
Dcm_SecLevelType currentSecurityLevel;\r
\r
- DslGetSecurityLevel(¤tSecurityLevel);\r
- while (((*securityLevelRefTable)->DspSecurityLevel != currentSecurityLevel) && !(*securityLevelRefTable)->Arc_EOL) {\r
- securityLevelRefTable++;\r
- }\r
- if ((*securityLevelRefTable)->Arc_EOL) {\r
- returnStatus = FALSE;\r
+ returnStatus = DslGetSecurityLevel(¤tSecurityLevel);\r
+ if (returnStatus == E_OK) {\r
+ while ( ((*securityLevelRefTable)->DspSecurityLevel != currentSecurityLevel) && (!(*securityLevelRefTable)->Arc_EOL) ) {\r
+ securityLevelRefTable++;\r
+ }\r
+ if (!(*securityLevelRefTable)->Arc_EOL) {\r
+ levelFound = TRUE;\r
+ }\r
}\r
\r
- return returnStatus;\r
+ return levelFound;\r
}\r
\r
\r
Dcm_SesCtrlType currentSessionLevel;\r
Std_ReturnType result;\r
\r
- while (!sesControl->Arc_EOL && (returnCode != E_SESSION_NOT_ALLOWED)) {\r
+ while ( (!sesControl->Arc_EOL) && (returnCode != E_SESSION_NOT_ALLOWED)) {\r
if (sesControl->GetSesChgPermission != NULL) {\r
- Dcm_GetSesCtrlType(¤tSessionLevel);\r
- result = sesControl->GetSesChgPermission(currentSessionLevel ,newSessionLevel);\r
- if (result != E_OK) {\r
- returnCode = result;\r
+ result = Dcm_GetSesCtrlType(¤tSessionLevel);\r
+ if (result == E_OK) {\r
+ result = sesControl->GetSesChgPermission(currentSessionLevel ,newSessionLevel);\r
+ if (result != E_OK) {\r
+ returnCode = result;\r
+ }\r
+ } else {\r
+ returnCode = E_NOT_OK;\r
}\r
}\r
sesControl++;\r
\r
void DspUdsDiagnosticSessionControl(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
- // @req DCM250 **/\r
+ /** @req DCM250 */\r
const Dcm_DspSessionRowType *sessionRow = DCM_Config.Dsp->DspSession->DspSessionRow;\r
Dcm_SesCtrlType reqSessionType;\r
Std_ReturnType result;\r
if (pduRxData->SduLength == 2) {\r
reqSessionType = pduRxData->SduDataPtr[1];\r
// Check if type exist in session table\r
- while ((sessionRow->DspSessionLevel != reqSessionType) && !sessionRow->Arc_EOL) {\r
+ while ((sessionRow->DspSessionLevel != reqSessionType) && (!sessionRow->Arc_EOL) ) {\r
sessionRow++;\r
}\r
\r
if (!sessionRow->Arc_EOL) {\r
result = askApplicationForSessionPermission(reqSessionType);\r
if (result == E_OK) {\r
- DslSetSesCtrlType(reqSessionType); /** @req DCM311 **/\r
+ DslSetSesCtrlType(reqSessionType); /** @req DCM311 */\r
// Create positive response\r
- /** @req DCM039.2 **/\r
pduTxData->SduDataPtr[1] = reqSessionType;\r
pduTxData->SduLength = 2;\r
- DsdDspProcessingDone(DCM_E_POSITIVERESPONSE); /** @req DCM269.2 **/\r
+ DsdDspProcessingDone(DCM_E_POSITIVERESPONSE);\r
}\r
else {\r
// TODO: Add handling of special case of E_FORCE_RCRRP (Dcm138)\r
- DsdDspProcessingDone(DCM_E_CONDITIONSNOTCORRECT); /** @req DCM308 **/\r
+ DsdDspProcessingDone(DCM_E_CONDITIONSNOTCORRECT); /** @req DCM308 */\r
}\r
}\r
else {\r
- DsdDspProcessingDone(DCM_E_SUBFUNCTIONNOTSUPPORTED); /** @req DCM307 **/\r
+ DsdDspProcessingDone(DCM_E_SUBFUNCTIONNOTSUPPORTED); /** @req DCM307 */\r
}\r
}\r
else {\r
// Wrong length\r
- DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT); /** @req DCM272.1 **/\r
+ DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT);\r
}\r
}\r
\r
\r
void DspUdsEcuReset(const PduInfoType *pduRxData, PduIdType txPduId, PduInfoType *pduTxData)\r
{\r
- // @req DCM260 **/\r
+ /** @req DCM260 */\r
uint8 reqResetType;\r
\r
if (pduRxData->SduLength == 2) {\r
dspUdsEcuResetData.resetPduId = txPduId;\r
\r
// Create positive response\r
- /** @req DCM039.1 **/\r
pduTxData->SduDataPtr[1] = reqResetType;\r
pduTxData->SduLength = 2;\r
- DsdDspProcessingDone(DCM_E_POSITIVERESPONSE); /** @req DCM269.3 **/\r
+ DsdDspProcessingDone(DCM_E_POSITIVERESPONSE);\r
break;\r
\r
default:\r
- DsdDspProcessingDone(DCM_E_SUBFUNCTIONNOTSUPPORTED); /** @req DCM273.3 **/\r
+ DsdDspProcessingDone(DCM_E_SUBFUNCTIONNOTSUPPORTED);\r
break;\r
}\r
}\r
else {\r
// Wrong length\r
- DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT); /** @req DCM272.3 **/\r
+ DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT);\r
}\r
}\r
\r
\r
void DspUdsClearDiagnosticInformation(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
+ /** @req DCM247 */\r
uint32 dtc;\r
Dem_ReturnClearDTCType result;\r
\r
if (pduRxData->SduLength == 4) {\r
dtc = BYTES_TO_DTC(pduRxData->SduDataPtr[1], pduRxData->SduDataPtr[2], pduRxData->SduDataPtr[3]);\r
\r
- result = Dem_ClearDTC(dtc, DEM_DTC_KIND_ALL_DTCS, DEM_DTC_ORIGIN_PRIMARY_MEMORY);\r
+ result = Dem_ClearDTC(dtc, DEM_DTC_KIND_ALL_DTCS, DEM_DTC_ORIGIN_PRIMARY_MEMORY); /** @req DCM005 */\r
\r
switch (result)\r
{\r
case DEM_CLEAR_OK:\r
// Create positive response\r
- /** @req DCM039.1 **/\r
pduTxData->SduLength = 1;\r
- DsdDspProcessingDone(DCM_E_POSITIVERESPONSE); /** @req DCM269.4 **/\r
+ DsdDspProcessingDone(DCM_E_POSITIVERESPONSE);\r
break;\r
\r
default:\r
}\r
else {\r
// Wrong length\r
- DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT); /** @req DCM272.1 **/\r
+ DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT);\r
}\r
}\r
\r
Dem_ReturnSetDTCFilterType setDtcFilterResult;\r
\r
// Setup the DTC filter\r
- switch (pduRxData->SduDataPtr[1]) /** @reg DCM293 **/\r
+ switch (pduRxData->SduDataPtr[1]) /** @req DCM293 */\r
{\r
case 0x01: // reportNumberOfDTCByStatusMask\r
setDtcFilterResult = Dem_SetDTCFilter(pduRxData->SduDataPtr[2], DEM_DTC_KIND_ALL_DTCS, DEM_DTC_ORIGIN_PRIMARY_MEMORY, DEM_FILTER_WITH_SEVERITY_NO, VALUE_IS_NOT_USED, DEM_FILTER_FOR_FDC_NO);\r
\r
default:\r
setDtcFilterResult = DEM_WRONG_FILTER;\r
-#if (DCM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DCM, 0, DCM_UDS_READ_DTC_INFO, DCM_E_UNEXPECTED_PARAM);\r
-#endif\r
break;\r
}\r
\r
if (setDtcFilterResult == DEM_FILTER_ACCEPTED) {\r
+ Std_ReturnType result;\r
+ Dem_ReturnGetNumberOfFilteredDTCType getNumerResult;\r
uint16 numberOfFilteredDtc;\r
uint8 dtcStatusMask;\r
+ //lint --e(826) PC-Lint exception - Suspicious pointer conversion\r
+ //lint --e(927) PC-Lint exception - Pointer to pointer cast\r
TxDataType *txData = (TxDataType*)pduTxData->SduDataPtr;\r
\r
- /** @reg DCM376 **/\r
- Dem_GetNumberOfFilteredDtc(&numberOfFilteredDtc);\r
- Dem_GetDTCStatusAvailabilityMask(&dtcStatusMask);\r
-\r
- // Create positive response (ISO 14229-1 table 251)\r
- /** @req DCM039.0x19 **/\r
- txData->reportType = pduRxData->SduDataPtr[1]; // reportType\r
- txData->dtcStatusAvailabilityMask = dtcStatusMask; // DTCStatusAvailabilityMask\r
- txData->dtcFormatIdentifier = Dem_GetTranslationType(); // DTCFormatIdentifier\r
- txData->dtcCountHighByte = (numberOfFilteredDtc >> 8); // DTCCount high byte\r
- txData->dtcCountLowByte = (numberOfFilteredDtc & 0xFF); // DTCCount low byte\r
- pduTxData->SduLength = 6;\r
+ /** @req DCM376 */\r
+ getNumerResult = Dem_GetNumberOfFilteredDtc(&numberOfFilteredDtc);\r
+ if (getNumerResult == DEM_NUMBER_OK) {\r
+ result = Dem_GetDTCStatusAvailabilityMask(&dtcStatusMask);\r
+ if (result != E_OK) {\r
+ dtcStatusMask = 0;\r
+ }\r
+\r
+ // Create positive response (ISO 14229-1 table 251)\r
+ txData->reportType = pduRxData->SduDataPtr[1]; // reportType\r
+ txData->dtcStatusAvailabilityMask = dtcStatusMask; // DTCStatusAvailabilityMask\r
+ txData->dtcFormatIdentifier = Dem_GetTranslationType(); // DTCFormatIdentifier\r
+ txData->dtcCountHighByte = (numberOfFilteredDtc >> 8); // DTCCount high byte\r
+ txData->dtcCountLowByte = (numberOfFilteredDtc & 0xFFu); // DTCCount low byte\r
+ pduTxData->SduLength = 6;\r
+ } else {\r
+ // TODO: What to do?\r
+ responseCode = DCM_E_GENERALREJECT;\r
+ }\r
}\r
else {\r
responseCode = DCM_E_REQUESTOUTOFRANGE;\r
} TxDataType;\r
\r
// Setup the DTC filter\r
- switch (pduRxData->SduDataPtr[1]) /** @reg DCM378 **/\r
+ switch (pduRxData->SduDataPtr[1]) /** @req DCM378 */\r
{\r
case 0x02: // reportDTCByStatusMask\r
setDtcFilterResult = Dem_SetDTCFilter(pduRxData->SduDataPtr[2], DEM_DTC_KIND_ALL_DTCS, DEM_DTC_ORIGIN_PRIMARY_MEMORY, DEM_FILTER_WITH_SEVERITY_NO, VALUE_IS_NOT_USED, DEM_FILTER_FOR_FDC_NO);\r
\r
default:\r
setDtcFilterResult = DEM_WRONG_FILTER;\r
-#if (DCM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DCM, 0, DCM_UDS_READ_DTC_INFO, DCM_E_UNEXPECTED_PARAM);\r
-#endif\r
break;\r
}\r
\r
if (setDtcFilterResult == DEM_FILTER_ACCEPTED) {\r
uint8 dtcStatusMask;\r
+ //lint --e(826) PC-Lint exception - Suspicious pointer conversion\r
+ //lint --e(927) PC-Lint exception - Pointer to pointer cast\r
TxDataType *txData = (TxDataType*)pduTxData->SduDataPtr;\r
Dem_ReturnGetNextFilteredDTCType getNextFilteredDtcResult;\r
uint32 dtc;\r
Dem_EventStatusExtendedType dtcStatus;\r
uint16 nrOfDtcs = 0;\r
+ Std_ReturnType result;\r
\r
- /** @reg DCM377 **/\r
- Dem_GetDTCStatusAvailabilityMask(&dtcStatusMask);\r
+ /** @req DCM377 */\r
+ result = Dem_GetDTCStatusAvailabilityMask(&dtcStatusMask);\r
+ if (result != E_OK) {\r
+ dtcStatusMask = 0;\r
+ }\r
\r
// Create positive response (ISO 14229-1 table 252)\r
- /** @req DCM039.0x19 **/\r
txData->reportType = pduRxData->SduDataPtr[1];\r
txData->dtcStatusAvailabilityMask = dtcStatusMask;\r
\r
- if (dtcStatusMask != 0x00) { /** @req DCM008 **/\r
+ if (dtcStatusMask != 0x00) { /** @req DCM008 */\r
getNextFilteredDtcResult = Dem_GetNextFilteredDTC(&dtc, &dtcStatus);\r
while (getNextFilteredDtcResult == DEM_FILTERED_OK) {\r
txData->dtcAndStatusRecord[nrOfDtcs].dtcHighByte = DTC_HIGH_BYTE(dtc);\r
responseCode = DCM_E_REQUESTOUTOFRANGE;\r
}\r
}\r
- pduTxData->SduLength = 3 + nrOfDtcs * sizeof(dtcAndStatusRecordType);\r
+ pduTxData->SduLength = (PduLengthType)(3 + (nrOfDtcs * sizeof(dtcAndStatusRecordType)));\r
}\r
else {\r
responseCode = DCM_E_REQUESTOUTOFRANGE;\r
return responseCode;\r
}\r
\r
-\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715, 838, 818} Symbol not referenced, responseCode not used, txData should be const\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x08(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715, 838, 818} Symbol not referenced, responseCode not used, txData should be const\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x09(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x06_0x10(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
- Dem_DTCOriginType dtcOrigin = NULL;\r
+ Dem_DTCOriginType dtcOrigin;\r
uint8 startRecNum;\r
uint8 endRecNum;\r
\r
// Switch on sub function\r
- switch (pduRxData->SduDataPtr[1]) /** @reg DCM378 **/\r
+ switch (pduRxData->SduDataPtr[1]) /** @req DCM378 */\r
{\r
case 0x06: // reportDTCExtendedDataRecordByDTCNumber\r
dtcOrigin = DEM_DTC_ORIGIN_PRIMARY_MEMORY;\r
\r
default:\r
responseCode = DCM_E_SUBFUNCTIONNOTSUPPORTED;\r
-#if (DCM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DCM, 0, DCM_UDS_READ_DTC_INFO, DCM_E_UNEXPECTED_PARAM);\r
-#endif\r
+ dtcOrigin = 0;\r
break;\r
}\r
\r
Dem_EventStatusExtendedType statusOfDtc;\r
\r
dtc = BYTES_TO_DTC(pduRxData->SduDataPtr[2], pduRxData->SduDataPtr[3], pduRxData->SduDataPtr[4]);\r
- getStatusOfDtcResult = Dem_GetStatusOfDTC(dtc, DEM_DTC_KIND_ALL_DTCS, dtcOrigin, &statusOfDtc); /** @req DCM295 **/ /** @req DCM475 **/\r
+ getStatusOfDtcResult = Dem_GetStatusOfDTC(dtc, DEM_DTC_KIND_ALL_DTCS, dtcOrigin, &statusOfDtc); /** @req DCM295 */ /** @req DCM475 */\r
if (getStatusOfDtcResult == DEM_STATUS_OK) {\r
Dem_ReturnGetExtendedDataRecordByDTCType getExtendedDataRecordByDtcResult;\r
- uint16 recNum;\r
- uint8 recLength;\r
+ uint8 recNum;\r
+ uint16 recLength;\r
uint16 txIndex = 6;\r
\r
- /** @req DCM297 **/ /** @req DCM474 **/ /** @req DCM386 **/\r
+ /** @req DCM297 */ /** @req DCM474 */ /** @req DCM386 */\r
pduTxData->SduDataPtr[1] = pduRxData->SduDataPtr[1]; // Sub function\r
pduTxData->SduDataPtr[2] = DTC_HIGH_BYTE(dtc); // DTC high byte\r
pduTxData->SduDataPtr[3] = DTC_MID_BYTE(dtc); // DTC mid byte\r
pduTxData->SduDataPtr[4] = DTC_LOW_BYTE(dtc); // DTC low byte\r
pduTxData->SduDataPtr[5] = statusOfDtc; // DTC status\r
for (recNum = startRecNum; recNum <= endRecNum; recNum++) {\r
- recLength = pduTxData->SduLength - txIndex -1; // Calculate what's left in buffer\r
- /** @req DCM296 **/ /** @req DCM476 **/ /** @req DCM382 **/\r
+ recLength = pduTxData->SduLength - (txIndex + 1); // Calculate what's left in buffer\r
+ /** @req DCM296 */ /** @req DCM476 */ /** @req DCM382 */\r
getExtendedDataRecordByDtcResult = Dem_GetExtendedDataRecordByDTC(dtc, DEM_DTC_KIND_ALL_DTCS, dtcOrigin, recNum, &pduTxData->SduDataPtr[txIndex+1], &recLength);\r
if (getExtendedDataRecordByDtcResult == DEM_RECORD_OK) {\r
pduTxData->SduDataPtr[txIndex++] = recNum;\r
/* Instead of calling Dem_GetSizeOfExtendedDataRecordByDTC() the result from Dem_GetExtendedDataRecordByDTC() is used */\r
- /** @req DCM478 **/ /** @req DCM479 **/ /** @req DCM480 **/\r
+ /** @req DCM478 */ /** @req DCM479 */ /** @req DCM480 */\r
txIndex += recLength;\r
}\r
else {\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715, 838, 818} Symbol not referenced, responseCode not used, txData should be const\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x03(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715, 838, 818} Symbol not referenced, responseCode not used, txData should be const\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x04(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715, 838, 818} Symbol not referenced, responseCode not used, txData should be const\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x05(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715, 838, 818} Symbol not referenced, responseCode not used, txData should be const\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x0B_0x0C_0x0D_0x0E(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715, 838, 818} Symbol not referenced, responseCode not used, txData should be const\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x14(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
\r
void DspUdsReadDtcInformation(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
- /** @reg DCM248 **/\r
+ /** @req DCM248 */\r
// Sub function number 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15\r
const uint8 sduLength[0x16] = {0, 3, 3, 6, 6, 3, 6, 4, 4, 5, 2, 2, 2, 2, 2, 3, 6, 3, 3, 3, 2, 2};\r
\r
}\r
else {\r
// Wrong length\r
- responseCode = DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT; /** @req DCM272.0x19 **/\r
+ responseCode = DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT;\r
}\r
}\r
else {\r
const Dcm_DspDidType *dspDid = DCM_Config.Dsp->DspDid;\r
boolean didFound = FALSE;\r
\r
- while ((dspDid->DspDidIdentifier != didNr) && !dspDid->Arc_EOL) {\r
+ while ((dspDid->DspDidIdentifier != didNr) && (!dspDid->Arc_EOL)) {\r
dspDid++;\r
}\r
\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
\r
- if ((didPtr->DspDidInfoRef->DspDidAccess.DspDidRead != NULL) && (didPtr->DspDidConditionCheckReadFnc != NULL) && (didPtr->DspDidReadDataFnc != NULL)) { /** @req DCM433 **/\r
- if (DspCheckSessionLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidRead->DspDidReadSessionRef)) { /** @req DCM434 **/\r
- if (DspCheckSecurityLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidRead->DspDidReadSecurityLevelRef)) { /** @req DCM435 **/\r
+ if ((didPtr->DspDidInfoRef->DspDidAccess.DspDidRead != NULL) && (didPtr->DspDidConditionCheckReadFnc != NULL) && (didPtr->DspDidReadDataFnc != NULL)) { /** @req DCM433 */\r
+ if (DspCheckSessionLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidRead->DspDidReadSessionRef)) { /** @req DCM434 */\r
+ if (DspCheckSecurityLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidRead->DspDidReadSecurityLevelRef)) { /** @req DCM435 */\r
Std_ReturnType result;\r
Dcm_NegativeResponseCodeType errorCode;\r
result = didPtr->DspDidConditionCheckReadFnc(&errorCode);\r
- if ((result == E_OK) && (errorCode == DCM_E_POSITIVERESPONSE)) { /** @req DCM439 **/\r
- uint16 didLen;\r
+ if ((result == E_OK) && (errorCode == DCM_E_POSITIVERESPONSE)) { /** @req DCM439 */\r
+ uint16 didLen = 0;\r
result = E_NOT_OK;\r
- if (didPtr->DspDidInfoRef->DspDidFixedLength) { /** @req DCM436 **/\r
+ if (didPtr->DspDidInfoRef->DspDidFixedLength) { /** @req DCM436 */\r
didLen = didPtr->DspDidSize;\r
result = E_OK;\r
}\r
if (result == E_OK) {\r
// Now ready for reading the data!\r
if ((*txPos + didLen + 2) <= pduTxData->SduLength) {\r
- pduTxData->SduDataPtr[*txPos] = (didPtr->DspDidIdentifier >> 8) & 0xFF;\r
+ pduTxData->SduDataPtr[*txPos] = (didPtr->DspDidIdentifier >> 8) & 0xFFu;\r
(*txPos)++;\r
- pduTxData->SduDataPtr[*txPos] = (didPtr->DspDidIdentifier >> 0) & 0xFF;\r
+ pduTxData->SduDataPtr[*txPos] = didPtr->DspDidIdentifier & 0xFFu;\r
(*txPos)++;\r
- result = didPtr->DspDidReadDataFnc(&pduTxData->SduDataPtr[*txPos]); /** @req DCM437 **/\r
+ result = didPtr->DspDidReadDataFnc(&pduTxData->SduDataPtr[*txPos]); /** @req DCM437 */\r
*txPos += didLen;\r
\r
if (result != E_OK) {\r
}\r
\r
if (responseCode == DCM_E_POSITIVERESPONSE) {\r
- // Recurse trough the rest of the dids. /** @req DCM440 **/\r
+ // Recurse trough the rest of the dids. /** @req DCM440 */\r
uint16 i;\r
for (i=0; (!didPtr->DspDidRef[i]->Arc_EOL) && (responseCode == DCM_E_POSITIVERESPONSE); i++) {\r
responseCode = readDidData(didPtr->DspDidRef[i], pduTxData, txPos);\r
\r
void DspUdsReadDataByIdentifier(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
- /** @req DCM253 **/\r
+ /** @req DCM253 */\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
- uint8 nrOfDids;\r
+ uint16 nrOfDids;\r
uint16 didNr;\r
const Dcm_DspDidType *didPtr = NULL;\r
\r
uint16 txPos = 1;\r
uint16 i;\r
\r
- if ((pduRxData->SduLength - 1) % 2 == 0 ) {\r
+ if ( ((pduRxData->SduLength - 1) % 2) == 0 ) {\r
nrOfDids = (pduRxData->SduLength - 1) / 2;\r
\r
for (i = 0; (i < nrOfDids) && (responseCode == DCM_E_POSITIVERESPONSE); i++) {\r
- didNr = (pduRxData->SduDataPtr[1+i*2] << 8) + pduRxData->SduDataPtr[2+i*2];\r
- if (lookupDid(didNr, &didPtr)) { /** @req DCM438 **/\r
+ didNr = (uint16)((uint16)pduRxData->SduDataPtr[1+(i*2)] << 8) + pduRxData->SduDataPtr[2+(i*2)];\r
+ if (lookupDid(didNr, &didPtr)) { /** @req DCM438 */\r
responseCode = readDidData(didPtr, pduTxData, &txPos);\r
}\r
else { // DID not found\r
}\r
\r
\r
-static Dcm_NegativeResponseCodeType readDidScalingData(const Dcm_DspDidType *didPtr, PduInfoType *pduTxData, uint16 *txPos)\r
+static Dcm_NegativeResponseCodeType readDidScalingData(const Dcm_DspDidType *didPtr, const PduInfoType *pduTxData, uint16 *txPos)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
\r
Std_ReturnType result;\r
Dcm_NegativeResponseCodeType errorCode;\r
\r
- pduTxData->SduDataPtr[*txPos] = (didPtr->DspDidIdentifier >> 8) & 0xFF;\r
+ pduTxData->SduDataPtr[*txPos] = (didPtr->DspDidIdentifier >> 8) & 0xFFu;\r
(*txPos)++;\r
- pduTxData->SduDataPtr[*txPos] = (didPtr->DspDidIdentifier >> 0) & 0xFF;\r
+ pduTxData->SduDataPtr[*txPos] = didPtr->DspDidIdentifier & 0xFFu;\r
(*txPos)++;\r
- result = didPtr->DspDidGetScalingInfoFnc(&pduTxData->SduDataPtr[*txPos], &errorCode); /** @req DCM394 **/\r
+ result = didPtr->DspDidGetScalingInfoFnc(&pduTxData->SduDataPtr[*txPos], &errorCode); /** @req DCM394 */\r
*txPos += scalingInfoLen;\r
\r
if ((result != E_OK) || (errorCode != DCM_E_POSITIVERESPONSE)) {\r
\r
void DspUdsReadScalingDataByIdentifier(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
- /** @req DCM258 **/\r
+ /** @req DCM258 */\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
uint16 didNr;\r
const Dcm_DspDidType *didPtr = NULL;\r
uint16 txPos = 1;\r
\r
if (pduRxData->SduLength == 3) {\r
- didNr = (pduRxData->SduDataPtr[1] << 8) + pduRxData->SduDataPtr[2];\r
+ didNr = (uint16)((uint16)pduRxData->SduDataPtr[1] << 8) + pduRxData->SduDataPtr[2];\r
if (lookupDid(didNr, &didPtr)) {\r
responseCode = readDidScalingData(didPtr, pduTxData, &txPos);\r
}\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
\r
- if ((didPtr->DspDidInfoRef->DspDidAccess.DspDidWrite != NULL) && (didPtr->DspDidConditionCheckWriteFnc != NULL) && (didPtr->DspDidWriteDataFnc != NULL)) { /** @req DCM468 **/\r
- if (DspCheckSessionLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidWrite->DspDidWriteSessionRef)) { /** @req DCM469 **/\r
- if (DspCheckSecurityLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidWrite->DspDidWriteSecurityLevelRef)) { /** @req DCM470 **/\r
+ if ((didPtr->DspDidInfoRef->DspDidAccess.DspDidWrite != NULL) && (didPtr->DspDidConditionCheckWriteFnc != NULL) && (didPtr->DspDidWriteDataFnc != NULL)) { /** @req DCM468 */\r
+ if (DspCheckSessionLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidWrite->DspDidWriteSessionRef)) { /** @req DCM469 */\r
+ if (DspCheckSecurityLevel(didPtr->DspDidInfoRef->DspDidAccess.DspDidWrite->DspDidWriteSecurityLevelRef)) { /** @req DCM470 */\r
Std_ReturnType result;\r
Dcm_NegativeResponseCodeType errorCode;\r
- result = didPtr->DspDidConditionCheckWriteFnc(&errorCode); /** @req DCM471 **/\r
+ result = didPtr->DspDidConditionCheckWriteFnc(&errorCode); /** @req DCM471 */\r
if ((result == E_OK) && (errorCode == DCM_E_POSITIVERESPONSE)) {\r
- uint16 didLen;\r
+ uint16 didLen = 0;\r
result = E_NOT_OK;\r
- if (didPtr->DspDidInfoRef->DspDidFixedLength) { /** @req DCM472 **/\r
+ if (didPtr->DspDidInfoRef->DspDidFixedLength) { /** @req DCM472 */\r
didLen = didPtr->DspDidSize;\r
result = E_OK;\r
}\r
else {\r
if (didPtr->DspDidReadDataLengthFnc != NULL) {\r
result = didPtr->DspDidReadDataLengthFnc(&didLen);\r
- }\r
- }\r
+ } }\r
\r
if (result == E_OK) {\r
- if (didLen == writeDidLen) { /** @req DCM473 **/\r
- result = didPtr->DspDidWriteDataFnc(&pduRxData->SduDataPtr[3], didLen, &errorCode); /** @req DCM395 **/\r
+ if (didLen == writeDidLen) { /** @req DCM473 */\r
+ result = didPtr->DspDidWriteDataFnc(&pduRxData->SduDataPtr[3], (uint8)didLen, &errorCode); /** @req DCM395 */\r
if ((result != E_OK) || (errorCode != DCM_E_POSITIVERESPONSE)) {\r
responseCode = DCM_E_CONDITIONSNOTCORRECT;\r
}\r
\r
void DspUdsWriteDataByIdentifier(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
- /** @req DCM255 **/\r
+ /** @req DCM255 */\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
uint16 didNr;\r
const Dcm_DspDidType *didPtr = NULL;\r
uint16 didDataLength;\r
\r
didDataLength = pduRxData->SduLength - 3;\r
- didNr = (pduRxData->SduDataPtr[1] << 8) + pduRxData->SduDataPtr[2];\r
- if (lookupDid(didNr, &didPtr)) { /** @req DCM467 **/\r
+ didNr = (uint16)((uint16)pduRxData->SduDataPtr[1] << 8) + pduRxData->SduDataPtr[2];\r
+ if (lookupDid(didNr, &didPtr)) { /** @req DCM467 */\r
responseCode = writeDidData(didPtr, pduRxData, didDataLength);\r
}\r
else { // DID not found\r
\r
if (responseCode == DCM_E_POSITIVERESPONSE) {\r
pduTxData->SduLength = 3;\r
- pduTxData->SduDataPtr[1] = (didNr >> 8) & 0xFF;\r
- pduTxData->SduDataPtr[2] = (didNr >> 0) & 0xFF;\r
+ pduTxData->SduDataPtr[1] = (didNr >> 8) & 0xFFu;\r
+ pduTxData->SduDataPtr[2] = didNr & 0xFFu;\r
}\r
\r
DsdDspProcessingDone(responseCode);\r
\r
void DspUdsSecurityAccess(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
- /** @req DCM252 **/\r
+ /** @req DCM252 */\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
\r
// Check sub function range (0x01 to 0x42)\r
if ((pduRxData->SduDataPtr[1] >= 0x01) && (pduRxData->SduDataPtr[1] <= 0x42)) {\r
- boolean isRequestSeed = pduRxData->SduDataPtr[1] & 0x01;\r
+ boolean isRequestSeed = pduRxData->SduDataPtr[1] & 0x01u;\r
Dcm_SecLevelType requestedSecurityLevel = (pduRxData->SduDataPtr[1]-1)/2;\r
- Std_ReturnType getSeedResult;\r
Dcm_NegativeResponseCodeType getSeedErrorCode;\r
\r
if (isRequestSeed) {\r
// requestSeed message\r
// Check if type exist in security table\r
const Dcm_DspSecurityRowType *securityRow = &DCM_Config.Dsp->DspSecurity->DspSecurityRow[0];\r
- while ((securityRow->DspSecurityLevel != requestedSecurityLevel) && !securityRow->Arc_EOL) {\r
+ while ((securityRow->DspSecurityLevel != requestedSecurityLevel) && (!securityRow->Arc_EOL)) {\r
securityRow++;\r
}\r
if (!securityRow->Arc_EOL) {\r
// Check length\r
- if (pduRxData->SduLength == (2 + securityRow->DspSecurityADRSize)) { /** @req DCM321.1 **/\r
+ if (pduRxData->SduLength == (2 + securityRow->DspSecurityADRSize)) { /** @req DCM321.RequestSeed */\r
Dcm_SecLevelType activeSecLevel;\r
- Dcm_GetSecurityLevel(&activeSecLevel);\r
- if (requestedSecurityLevel == activeSecLevel) { /** @req DCM323 **/\r
- pduTxData->SduDataPtr[1] = pduRxData->SduDataPtr[1];\r
- // If same level set the seed to zeroes\r
- memset(&pduTxData->SduDataPtr[2], 0, securityRow->DspSecuritySeedSize);\r
- pduTxData->SduLength = 2 + securityRow->DspSecuritySeedSize;\r
- }\r
- else {\r
- // New security level ask for seed\r
- getSeedResult = securityRow->GetSeed(&pduRxData->SduDataPtr[2], &pduTxData->SduDataPtr[2], &getSeedErrorCode);\r
- if ((getSeedResult == E_OK) && (getSeedErrorCode == E_OK)) {\r
- // Everything ok add sub function to tx message and send it.\r
+ Std_ReturnType result;\r
+ result = Dcm_GetSecurityLevel(&activeSecLevel);\r
+ if (result == E_OK) {\r
+ if (requestedSecurityLevel == activeSecLevel) { /** @req DCM323 */\r
pduTxData->SduDataPtr[1] = pduRxData->SduDataPtr[1];\r
+ // If same level set the seed to zeroes\r
+ memset(&pduTxData->SduDataPtr[2], 0, securityRow->DspSecuritySeedSize);\r
pduTxData->SduLength = 2 + securityRow->DspSecuritySeedSize;\r
-\r
- dspUdsSecurityAccesData.reqSecLevel = requestedSecurityLevel;\r
- dspUdsSecurityAccesData.reqSecLevelRef = securityRow;\r
- dspUdsSecurityAccesData.reqInProgress = TRUE;\r
- }\r
- else {\r
- // GetSeed returned not ok\r
- responseCode = DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT;\r
+ } else {\r
+ // New security level ask for seed\r
+ if (securityRow->GetSeed != NULL) {\r
+ Std_ReturnType getSeedResult;\r
+ getSeedResult = securityRow->GetSeed(&pduRxData->SduDataPtr[2], &pduTxData->SduDataPtr[2], &getSeedErrorCode); /** @req DCM324.RequestSeed */\r
+ if ((getSeedResult == E_OK) && (getSeedErrorCode == E_OK)) {\r
+ // Everything ok add sub function to tx message and send it.\r
+ pduTxData->SduDataPtr[1] = pduRxData->SduDataPtr[1];\r
+ pduTxData->SduLength = 2 + securityRow->DspSecuritySeedSize;\r
+\r
+ dspUdsSecurityAccesData.reqSecLevel = requestedSecurityLevel;\r
+ dspUdsSecurityAccesData.reqSecLevelRef = securityRow;\r
+ dspUdsSecurityAccesData.reqInProgress = TRUE;\r
+ }\r
+ else {\r
+ // GetSeed returned not ok\r
+ responseCode = DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT;\r
+ }\r
+ } else {\r
+ responseCode = DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT;\r
+ }\r
}\r
+ } else {\r
+ // TODO: What to do?\r
+ responseCode = DCM_E_GENERALREJECT;\r
}\r
+\r
}\r
else {\r
// Length not ok\r
else {\r
// sendKey message\r
if (dspUdsSecurityAccesData.reqInProgress) {\r
- if (pduRxData->SduLength == (2 + dspUdsSecurityAccesData.reqSecLevelRef->DspSecurityKeySize)) { /** @req DCM321 **/\r
+ if (pduRxData->SduLength == (2 + dspUdsSecurityAccesData.reqSecLevelRef->DspSecurityKeySize)) { /** @req DCM321.SendKey */\r
if (requestedSecurityLevel == dspUdsSecurityAccesData.reqSecLevel) {\r
- Std_ReturnType compareKeyResult;\r
- compareKeyResult = dspUdsSecurityAccesData.reqSecLevelRef->CompareKey(&pduRxData->SduDataPtr[2]);\r
- if (compareKeyResult == E_OK) {\r
- // Request accepted\r
- // Kill timer\r
- DslSetSecurityLevel(dspUdsSecurityAccesData.reqSecLevelRef->DspSecurityLevel);\r
- dspUdsSecurityAccesData.reqInProgress = FALSE;\r
- pduTxData->SduDataPtr[1] = pduRxData->SduDataPtr[1];\r
- pduTxData->SduLength = 2;\r
- }\r
- else {\r
+ if (dspUdsSecurityAccesData.reqSecLevelRef->CompareKey != NULL) {\r
+ Std_ReturnType compareKeyResult;\r
+ compareKeyResult = dspUdsSecurityAccesData.reqSecLevelRef->CompareKey(&pduRxData->SduDataPtr[2]); /** @req DCM324.SendKey */\r
+ if (compareKeyResult == E_OK) {\r
+ // Request accepted\r
+ // Kill timer\r
+ DslSetSecurityLevel(dspUdsSecurityAccesData.reqSecLevelRef->DspSecurityLevel); /** @req DCM325 */\r
+ dspUdsSecurityAccesData.reqInProgress = FALSE;\r
+ pduTxData->SduDataPtr[1] = pduRxData->SduDataPtr[1];\r
+ pduTxData->SduLength = 2;\r
+ }\r
+ else {\r
+ responseCode = DCM_E_CONDITIONSNOTCORRECT;\r
+ }\r
+ } else {\r
responseCode = DCM_E_CONDITIONSNOTCORRECT;\r
}\r
}\r
\r
void DspUdsTesterPresent(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
+ /** @req DCM251 */\r
if (pduRxData->SduLength == 2) {\r
switch (pduRxData->SduDataPtr[1])\r
{\r
case ZERO_SUB_FUNCTION:\r
DslResetSessionTimeoutTimer();\r
// Create positive response\r
- /** @req DCM039.1 **/\r
pduTxData->SduDataPtr[1] = ZERO_SUB_FUNCTION;\r
pduTxData->SduLength = 2;\r
- DsdDspProcessingDone(DCM_E_POSITIVERESPONSE); /** @req DCM269.1 **/\r
+ DsdDspProcessingDone(DCM_E_POSITIVERESPONSE);\r
break;\r
\r
default:\r
- DsdDspProcessingDone(DCM_E_SUBFUNCTIONNOTSUPPORTED); /** @req DCM273.1 **/\r
+ DsdDspProcessingDone(DCM_E_SUBFUNCTIONNOTSUPPORTED);\r
break;\r
}\r
}\r
else {\r
// Wrong length\r
- DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT); /** @req DCM272.1 **/\r
+ DsdDspProcessingDone(DCM_E_INCORRECTMESSAGELENGTHORINVALIDFORMAT);\r
}\r
}\r
\r
\r
void DspUdsControlDtcSetting(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
+ /** @req DCM249 */\r
Dem_ReturnControlDTCStorageType resultCode;\r
\r
if (pduRxData->SduLength == 2) {\r
switch (pduRxData->SduDataPtr[1])\r
{\r
- case 0x01: // ON /** @req DCM249.1 **/\r
- resultCode = Dem_EnableDTCStorage(DEM_DTC_GROUP_ALL_DTCS, DEM_DTC_KIND_ALL_DTCS); /** @req DCM304 **/\r
+ case 0x01: // ON\r
+ resultCode = Dem_EnableDTCStorage(DEM_DTC_GROUP_ALL_DTCS, DEM_DTC_KIND_ALL_DTCS); /** @req DCM304 */\r
if (resultCode == DEM_CONTROL_DTC_STORAGE_OK) {\r
pduTxData->SduDataPtr[1] = 0x01;\r
pduTxData->SduLength = 2;\r
}\r
break;\r
\r
- case 0x02: // OFF /** @req DCM249.2 **/\r
- resultCode = Dem_DisableDTCStorage(DEM_DTC_GROUP_ALL_DTCS, DEM_DTC_KIND_ALL_DTCS); /** @req DCM406 **/\r
+ case 0x02: // OFF\r
+ resultCode = Dem_DisableDTCStorage(DEM_DTC_GROUP_ALL_DTCS, DEM_DTC_KIND_ALL_DTCS); /** @req DCM406 */\r
if (resultCode == DEM_CONTROL_DTC_STORAGE_OK) {\r
pduTxData->SduDataPtr[1] = 0x02;\r
pduTxData->SduLength = 2;\r
if (dspUdsEcuResetData.resetPending) {\r
if (confirmPduId == dspUdsEcuResetData.resetPduId) {\r
dspUdsEcuResetData.resetPending = FALSE;\r
+#if defined(USE_MCU) && ( MCU_PERFORM_RESET_API == STD_ON )\r
Mcu_PerformReset();\r
+#else\r
+ DET_REPORTERROR(MODULE_ID_DCM, 0, DCM_UDS_RESET_ID, DCM_E_NOT_SUPPORTED);\r
+#endif\r
}\r
}\r
}\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
/*\r
- * NB! This file is for DCM internal use only and may only be included from DCM C-files!
+ * NB! This file is for DCM internal use only and may only be included from DCM C-files!\r
*/\r
\r
\r
#ifndef DCM_INTERNAL_H_\r
#define DCM_INTERNAL_H_\r
\r
+\r
+#if ( DCM_DEV_ERROR_DETECT == STD_ON )\r
+#include "Det.h"\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_DCM, 0, _api, _err); \\r
+ return E_NOT_OK; \\r
+ }\r
+\r
+#define VALIDATE_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_DCM, 0, _api, _err); \\r
+ return _rv; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_DCM, 0, _api, _err); \\r
+ return; \\r
+ }\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_RV(_exp,_api,_err,_rv )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#endif\r
+\r
+\r
// SID table\r
#define SID_DIAGNOSTIC_SESSION_CONTROL 0x10\r
#define SID_ECU_RESET 0x11\r
#define SID_CONTROL_DTC_SETTING 0x85\r
\r
// Misc definitions\r
-#define SUPPRESS_POS_RESP_BIT 0x80\r
-#define SID_RESPONSE_BIT 0x40\r
-#define VALUE_IS_NOT_USED 0x00\r
+#define SUPPRESS_POS_RESP_BIT (uint8)0x80\r
+#define SID_RESPONSE_BIT (uint8)0x40\r
+#define VALUE_IS_NOT_USED (uint8)0x00\r
\r
typedef enum {\r
DSD_TX_RESPONSE_READY,\r
void DspUdsControlDtcSetting(const PduInfoType *pduRxData, PduInfoType *pduTxData);\r
void DspDcmConfirmation(PduIdType confirmPduId);\r
\r
-boolean DspCheckSessionLevel(const Dcm_DspSessionRowType **sessionLevelRefTable);\r
-boolean DspCheckSecurityLevel(const Dcm_DspSecurityRowType **securityLevelRefTable);\r
+boolean DspCheckSessionLevel(Dcm_DspSessionRowType const* const* sessionLevelRefTable);\r
+boolean DspCheckSecurityLevel(Dcm_DspSecurityRowType const* const* securityLevelRefTable);\r
\r
\r
/*\r
void DslInit(void);\r
void DslMain(void);\r
void DslHandleResponseTransmission(void);\r
-void DslDsdProcessingDone(PduIdType txPduId, DsdProcessingDoneResultType result);\r
+void DslDsdProcessingDone(PduIdType rxPduIdRef, DsdProcessingDoneResultType responseResult);\r
void DslGetCurrentServiceTable(const Dcm_DsdServiceTableType **currentServiceTable);\r
\r
BufReq_ReturnType DslProvideRxBufferToPdur(PduIdType dcmRxPduId, PduLengthType tpSduLength, const PduInfoType **pduInfoPtr);\r
Std_ReturnType DslGetActiveProtocol(Dcm_ProtocolType *protocolId);\r
void DslSetSecurityLevel(Dcm_SecLevelType secLevel);\r
Std_ReturnType DslGetSecurityLevel(Dcm_SecLevelType *secLevel);\r
-void DslSetSesCtrlType(Dcm_SesCtrlType sesCtrlType);\r
+void DslSetSesCtrlType(Dcm_SesCtrlType sesCtrl);\r
Std_ReturnType DslGetSesCtrlType(Dcm_SesCtrlType *sesCtrlType);\r
BufReq_ReturnType DslProvideTxBuffer(PduIdType dcmTxPduId, const PduInfoType **pduInfoPtr, PduLengthType length);\r
void DslTxConfirmation(PduIdType dcmTxPduId, NotifResultType result);\r
#ifndef DCM_LCFG_H_\r
#define DCM_LCFG_H_\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DCM075 */ /** @req DCM076 */\r
+\r
+\r
#include "ComStack_Types.h"\r
#include "Dcm_Types.h"\r
\r
\r
// DidServices_<DID>\r
typedef Std_ReturnType (*Dcm_CallbackReadDataFncType)(uint8 *data);\r
-typedef Std_ReturnType (*Dcm_CallbackWriteDataFncType)(uint8 *data, uint8 dataLength, Dcm_NegativeResponseCodeType *errorCode);\r
+typedef Std_ReturnType (*Dcm_CallbackWriteDataFncType)(uint8 *data, uint16 dataLength, Dcm_NegativeResponseCodeType *errorCode);\r
typedef Std_ReturnType (*Dcm_CallbackReadDataLengthFncType)(uint16 *didLength);\r
typedef Std_ReturnType (*Dcm_CallbackConditionCheckReadFncType)(Dcm_NegativeResponseCodeType *errorCode);\r
typedef Std_ReturnType (*Dcm_CallbackConditionCheckWriteFncType)(Dcm_NegativeResponseCodeType *errorCode);\r
\r
// 10.2.44\r
typedef struct {\r
- Dcm_SesCtrlType DspSessionLevel; // (1)\r
- uint16 DspSessionP2ServerMax; // (1)\r
- uint16 DspSessionP2StarServerMax; // (1)\r
- boolean Arc_EOL;\r
-} Dcm_DspSessionRowType;\r
+ Dcm_SesCtrlType DspSessionLevel; // (1)\r
+ uint16 DspSessionP2ServerMax; // (1)\r
+ uint16 DspSessionP2StarServerMax; // (1)\r
+ boolean Arc_EOL;\r
+} Dcm_DspSessionRowType; /** @req DCM072 */\r
\r
// 10.2.42\r
typedef struct {\r
- Dcm_SecLevelType DspSecurityLevel; // (1)\r
- uint16 DspSecurityDelayTimeOnBoot; // (1)\r
- uint8 DspSecurityNumAttDelay; // (1)\r
- uint16 DspSecurityDelayTime; // (1)\r
- uint8 DspSecurityNumAttLock; // (1)\r
- uint8 DspSecurityADRSize; // (0..1)\r
- uint8 DspSecuritySeedSize; // (1)\r
- uint8 DspSecurityKeySize; // (1)\r
- Dcm_CallbackGetSeedFncType GetSeed;\r
- Dcm_CallbackCompareKeyFncType CompareKey;\r
- boolean Arc_EOL;\r
-} Dcm_DspSecurityRowType;\r
+ Dcm_SecLevelType DspSecurityLevel; // (1)\r
+ uint16 DspSecurityDelayTimeOnBoot; // (1)\r
+ uint8 DspSecurityNumAttDelay; // (1)\r
+ uint16 DspSecurityDelayTime; // (1)\r
+ uint8 DspSecurityNumAttLock; // (1)\r
+ uint8 DspSecurityADRSize; // (0..1)\r
+ uint8 DspSecuritySeedSize; // (1)\r
+ uint8 DspSecurityKeySize; // (1)\r
+ Dcm_CallbackGetSeedFncType GetSeed;\r
+ Dcm_CallbackCompareKeyFncType CompareKey;\r
+ boolean Arc_EOL;\r
+} Dcm_DspSecurityRowType; /** @req DCM073 */\r
\r
// 10.2.23\r
typedef struct {\r
- uint8 DspDidControlRecordSize; // (1)\r
- uint8 DspDidControlOptionRecordSize; // (1)\r
- uint8 DspDidControlStatusRecordSize; // (1)\r
+ uint8 DspDidControlRecordSize; // (1)\r
+ uint8 DspDidControlOptionRecordSize; // (1)\r
+ uint8 DspDidControlStatusRecordSize; // (1)\r
} Dcm_DspDidControlRecordSizesType;\r
\r
// 10.2.26\r
typedef struct {\r
- const Dcm_DspSessionRowType **DspDidControlSessionRef; // (1..*)\r
- const Dcm_DspSecurityRowType **DspDidControlSecurityLevelRef; // (1..*)\r
- const Dcm_DspDidControlRecordSizesType *DspDidFreezeCurrentState; // (0..1)\r
- const Dcm_DspDidControlRecordSizesType *DspDidResetToDefault; // (0..1)\r
- const Dcm_DspDidControlRecordSizesType *DspDidReturnControlToEcu; // (0..1)\r
- const Dcm_DspDidControlRecordSizesType *DspDidShortTermAdjustment; // (0..1)\r
-} Dcm_DspDidControlType;\r
+ const Dcm_DspSessionRowType **DspDidControlSessionRef; // (1..*) /** @req DCM621 */\r
+ const Dcm_DspSecurityRowType **DspDidControlSecurityLevelRef; // (1..*) /** @req DCM620 */\r
+ const Dcm_DspDidControlRecordSizesType *DspDidFreezeCurrentState; // (0..1) /** @req DCM624 */\r
+ const Dcm_DspDidControlRecordSizesType *DspDidResetToDefault; // (0..1) /** @req DCM623 */\r
+ const Dcm_DspDidControlRecordSizesType *DspDidReturnControlToEcu; // (0..1) /** @req DCM622 */\r
+ const Dcm_DspDidControlRecordSizesType *DspDidShortTermAdjustment; // (0..1) /** @req DCM625 */\r
+} Dcm_DspDidControlType; /** @req DCM619 */\r
\r
// 10.2.27\r
typedef struct {\r
- const Dcm_DspSessionRowType **DspDidReadSessionRef; // (1..*)\r
- const Dcm_DspSecurityRowType **DspDidReadSecurityLevelRef; // (1..*)\r
-} Dcm_DspDidReadType;\r
+ const Dcm_DspSessionRowType **DspDidReadSessionRef; // (1..*) /** @req DCM615 */\r
+ const Dcm_DspSecurityRowType **DspDidReadSecurityLevelRef; // (1..*) /** @req DCM614 */\r
+} Dcm_DspDidReadType; /** @req DCM613 */\r
\r
// 10.2.28\r
typedef struct {\r
- const Dcm_DspSessionRowType **DspDidWriteSessionRef; // (1..*)\r
- const Dcm_DspSecurityRowType **DspDidWriteSecurityLevelRef; // (1..*)\r
-} Dcm_DspDidWriteType;\r
+ const Dcm_DspSessionRowType **DspDidWriteSessionRef; // (1..*) /** @req DCM618 */\r
+ const Dcm_DspSecurityRowType **DspDidWriteSecurityLevelRef; // (1..*) /** @req DCM617 */\r
+} Dcm_DspDidWriteType; /** @req DCM616 */\r
\r
// 10.2.25\r
typedef struct {\r
const Dcm_DspDidReadType *DspDidRead; // (0..1)\r
const Dcm_DspDidWriteType *DspDidWrite; // (0..1)\r
const Dcm_DspDidControlType *DspDidControl; // (0..1)\r
-} Dcm_DspDidAccessType;\r
+} Dcm_DspDidAccessType; /** @req DCM609 */\r
\r
// 10.2.24\r
typedef struct {\r
- boolean DspDidDynamicllyDefined; // (1)\r
- boolean DspDidFixedLength; // (1)\r
- uint8 DspDidScalingInfoSize; // (0..1)\r
+ boolean DspDidDynamicllyDefined; // (1) /** @req DCM612 */\r
+ boolean DspDidFixedLength; // (1) /** @req DCM608 */\r
+ uint8 DspDidScalingInfoSize; // (0..1) /** @req DCM611 */\r
// Containers\r
- Dcm_DspDidAccessType DspDidAccess; // (1)\r
-} Dcm_DspDidInfoType;\r
+ Dcm_DspDidAccessType DspDidAccess; // (1)\r
+} Dcm_DspDidInfoType; /** @req DCM607 */\r
\r
// 10.2.22\r
-typedef struct _Dcm_DspDidType {\r
+typedef struct Dcm_DspDidType {\r
boolean DspDidUsePort; // (1)\r
- uint16 DspDidIdentifier; // (1)\r
- const Dcm_DspDidInfoType *DspDidInfoRef; // (1)\r
- const struct _Dcm_DspDidType **DspDidRef; // (0..*)\r
- uint16 DspDidSize; // (1)\r
- Dcm_CallbackReadDataLengthFncType DspDidReadDataLengthFnc; // (0..1)\r
- Dcm_CallbackConditionCheckReadFncType DspDidConditionCheckReadFnc; // (0..1)\r
- Dcm_CallbackReadDataFncType DspDidReadDataFnc; // (0..1)\r
- Dcm_CallbackConditionCheckWriteFncType DspDidConditionCheckWriteFnc; // (0..1)\r
- Dcm_CallbackWriteDataFncType DspDidWriteDataFnc; // (0..1)\r
- Dcm_CallbackGetScalingInformationFncType DspDidGetScalingInfoFnc; // (0..1)\r
- Dcm_CallbackFreezeCurrentStateFncType DspDidFreezeCurrentStateFnc; // (0..1)\r
- Dcm_CallbackResetToDefaultFncType DspDidResetToDeaultFnc; // (0..1)\r
- Dcm_CallbackReturnControlToECUFncType DspDidReturnControlToEcuFnc; // (0..1)\r
- Dcm_CallbackShortTermAdjustmentFncType DspDidShortTermAdjustmentFnc; // (0..1)\r
+ uint16 DspDidIdentifier; // (1) /** @req DCM602 */\r
+ const Dcm_DspDidInfoType *DspDidInfoRef; // (1) /** @req DCM604 */\r
+ const struct Dcm_DspDidType **DspDidRef; // (0..*) /** @req DCM606 */\r
+ uint16 DspDidSize; // (1) /** @req DCM605 */\r
+ Dcm_CallbackReadDataLengthFncType DspDidReadDataLengthFnc; // (0..1) /** @req DCM671 */\r
+ Dcm_CallbackConditionCheckReadFncType DspDidConditionCheckReadFnc; // (0..1) /** @req DCM677 */\r
+ Dcm_CallbackReadDataFncType DspDidReadDataFnc; // (0..1) /** @req DCM669 */\r
+ Dcm_CallbackConditionCheckWriteFncType DspDidConditionCheckWriteFnc; // (0..1) /** @req DCM678 */\r
+ Dcm_CallbackWriteDataFncType DspDidWriteDataFnc; // (0..1) /** @req DCM670 */\r
+ Dcm_CallbackGetScalingInformationFncType DspDidGetScalingInfoFnc; // (0..1) /** @req DCM676 */\r
+ Dcm_CallbackFreezeCurrentStateFncType DspDidFreezeCurrentStateFnc; // (0..1) /** @req DCM674 */\r
+ Dcm_CallbackResetToDefaultFncType DspDidResetToDeaultFnc; // (0..1) /** @req DCM673 */\r
+ Dcm_CallbackReturnControlToECUFncType DspDidReturnControlToEcuFnc; // (0..1) /** @req DCM672 */\r
+ Dcm_CallbackShortTermAdjustmentFncType DspDidShortTermAdjustmentFnc; // (0..1) /** @req DCM675 */\r
// Containers\r
const Dcm_DspDidControlRecordSizesType *DspDidControlRecordSize; // (0..*)\r
boolean Arc_EOL;\r
-} Dcm_DspDidType;\r
+} Dcm_DspDidType; /** @req DCM601 */\r
\r
// 10.2.30\r
typedef struct {\r
- const Dcm_DspSessionRowType **DspEcuResetSessionRef; // (1..*)\r
- const Dcm_DspSecurityRowType **DspEcuResetSecurityLevelRef; // (1..*)\r
-\r
-} Dcm_DspEcuResetType;\r
+ const Dcm_DspSessionRowType **DspEcuResetSessionRef; // (1..*)\r
+ const Dcm_DspSecurityRowType **DspEcuResetSecurityLevelRef; // (1..*)\r
+} Dcm_DspEcuResetType; /** @req DCM657 */\r
\r
// 10.2.31\r
typedef struct {\r
- boolean DspPidUsePort; // (1)\r
- uint8 DspPidIdentifier; // (1)\r
- uint8 DspPidSize; // (1)\r
- Dcm_CallbackGetPIDValueFncType DspGetPidValFnc; // (1)\r
-} Dcm_DspPidType;\r
+ boolean DspPidUsePort; // (1)\r
+ uint8 DspPidIdentifier; // (1) /** @req DCM627 */\r
+ uint8 DspPidSize; // (1) /** @req DCM628 */\r
+ Dcm_CallbackGetPIDValueFncType DspGetPidValFnc; // (1) /** @req DCM629 */\r
+} Dcm_DspPidType; /** @req DCM626 */\r
\r
// 10.2.33\r
typedef struct {\r
- boolean DspDTCInfoSubFuncSupp; // (1)\r
- uint8 DspDTCInfoSubFuncLevel; // (1)\r
- const Dcm_DspSecurityRowType **DspDTCInfoSecLevelRef; // (1..*)\r
-} Dcm_DspReadDTCRowType;\r
+ boolean DspDTCInfoSubFuncSupp; // (1)\r
+ uint8 DspDTCInfoSubFuncLevel; // (1)\r
+ const Dcm_DspSecurityRowType **DspDTCInfoSecLevelRef; // (1..*)\r
+} Dcm_DspReadDTCRowType; /** @req DCM073 */\r
\r
// 10.2.32\r
typedef struct {\r
// Containers\r
Dcm_DspReadDTCRowType *DspReadDTCRow; // (0..*)\r
-} Dcm_DspReadDTCType;\r
+} Dcm_DspReadDTCType; /** @req DCM074 */\r
\r
// 10.2.34\r
typedef struct {\r
- uint8 DspRequestControl; // (1)\r
- uint8 DspRequestControlOutBufferSize; // (1)\r
- uint8 DspRequestControlTestId; // (1)\r
-} Dcm_DspRequestControlType;\r
+ uint8 DspRequestControl; // (1)\r
+ uint8 DspRequestControlOutBufferSize; // (1)\r
+ uint8 DspRequestControlTestId; // (1) /** @req DCM656 */\r
+} Dcm_DspRequestControlType; /** @req DCM637 */\r
\r
// 10.2.37\r
typedef struct {\r
- const Dcm_DspSessionRowType *DspRoutineSessionRef; // (1..*)\r
- const Dcm_DspSecurityRowType *DspRoutineSecurityLevelRef; // (1..*)\r
-} Dcm_DspRoutineAuthorizationType;\r
+ const Dcm_DspSessionRowType *DspRoutineSessionRef; // (1..*) /** @req DCM649 */\r
+ const Dcm_DspSecurityRowType *DspRoutineSecurityLevelRef; // (1..*) /** @req DCM648 */\r
+} Dcm_DspRoutineAuthorizationType; /** @req DCM644 */\r
\r
// 10.2.38\r
typedef struct {\r
- uint8 DspReqResRtnCtrlOptRecSize; // (1)\r
-} Dcm_DspRoutineRequestResType;\r
+ uint8 DspReqResRtnCtrlOptRecSize; // (1) /** @req DCM652 */\r
+} Dcm_DspRoutineRequestResType; /** @req DCM646 */\r
\r
// 10.2.39\r
typedef struct {\r
- uint8 DspStopRoutineCtrlOptRecSize; // (1)\r
- uint8 DspStopRoutineStsOptRecSize; // (1)\r
-} Dcm_DspRoutineStopType;\r
+ uint8 DspStopRoutineCtrlOptRecSize; // (1) /** @req DCM650 */\r
+ uint8 DspStopRoutineStsOptRecSize; // (1) /** @req DCM651 */\r
+} Dcm_DspRoutineStopType; /** @req DCM645 */\r
\r
// 10.2.40\r
typedef struct {\r
- uint8 DspStartRoutineCtrlOptRecSize; // (1)\r
- uint8 DspStartRoutineStsOptRecSize; // (1)\r
-} Dcm_DspStartRoutineType;\r
+ uint8 DspStartRoutineCtrlOptRecSize; // (1) /** @req DCM654 */\r
+ uint8 DspStartRoutineStsOptRecSize; // (1) /** @req DCM655 */\r
+} Dcm_DspStartRoutineType; /** @req DCM647 */\r
\r
// 10.2.36\r
typedef struct {\r
// Containers\r
- const Dcm_DspRoutineAuthorizationType *DspRoutineAuthorization; // (1)\r
- const Dcm_DspRoutineRequestResType *DspRoutineRequestRes; // (0..1)\r
- const Dcm_DspRoutineStopType *DspRoutineStop; // (0..1)\r
- const Dcm_DspStartRoutineType *DspStartRoutine; // (1)\r
-} Dcm_DspRoutineInfoType;\r
+ const Dcm_DspRoutineAuthorizationType *DspRoutineAuthorization; // (1)\r
+ const Dcm_DspRoutineRequestResType *DspRoutineRequestRes; // (0..1)\r
+ const Dcm_DspRoutineStopType *DspRoutineStop; // (0..1)\r
+ const Dcm_DspStartRoutineType *DspStartRoutine; // (1)\r
+} Dcm_DspRoutineInfoType; /** @req DCM643 */\r
\r
// 10.2.35\r
typedef struct {\r
- boolean DspRoutineUsePort; // (1)\r
- uint16 DspRoutineIdentifier; // (1)\r
- const Dcm_DspRoutineInfoType *DspRoutineInfoRef; // (1)\r
- Dcm_CallbackStartFncType DspStartRoutineFnc; // (0..1)\r
- Dcm_CallbackStopFncType DspStopRoutineFnc; // (0..1)\r
- Dcm_CallbackRequestResultFncType DspRequestResultRoutineFnc; // (0..1)\r
-} Dcm_DspRoutineType;\r
+ boolean DspRoutineUsePort; // (1)\r
+ uint16 DspRoutineIdentifier; // (1) /** @req DCM641 */\r
+ const Dcm_DspRoutineInfoType *DspRoutineInfoRef; // (1) /** @req DCM642 */\r
+ Dcm_CallbackStartFncType DspStartRoutineFnc; // (0..1) /** @req DCM664 */\r
+ Dcm_CallbackStopFncType DspStopRoutineFnc; // (0..1) /** @req DCM665 */\r
+ Dcm_CallbackRequestResultFncType DspRequestResultRoutineFnc; // (0..1) /** @req DCM665 */\r
+} Dcm_DspRoutineType; /** @req DCM640 */\r
\r
// 10.2.41\r
typedef struct {\r
// Containers\r
const Dcm_DspSecurityRowType *DspSecurityRow; // (0..31)\r
-} Dcm_DspSecurityType;\r
+} Dcm_DspSecurityType; /** @req DCM073 */\r
\r
// 10.2.43\r
typedef struct {\r
// Containers\r
const Dcm_DspSessionRowType *DspSessionRow; // (0..31)\r
-} Dcm_DspSessionType;\r
+} Dcm_DspSessionType; /** @req DCM072 */\r
\r
// 10.2.47\r
typedef struct {\r
- uint8 DspTestResultTestId; // (1)\r
- uint8 DspTestResultUaSid; // (1)\r
-} Dcm_DspTestResultTidType;\r
+ uint8 DspTestResultTestId; // (1) /** @req DCM635 */\r
+ uint8 DspTestResultUaSid; // (1) /** @req DCM686 */\r
+} Dcm_DspTestResultTidType; /** @req DCM634 */\r
\r
// 10.2.46\r
typedef struct {\r
- uint8 DspTestResultObdmid; // (1)\r
- const Dcm_DspTestResultTidType **DspTestResultObdmidTidRef; // (1..*)\r
-} Dcm_DspTestResultObdmidTidType;\r
+ uint8 DspTestResultObdmid; // (1) /** @req DCM684 */\r
+ const Dcm_DspTestResultTidType **DspTestResultObdmidTidRef; // (1..*) /** @req DCM685 */\r
+} Dcm_DspTestResultObdmidTidType; /** @req DCM683 */\r
\r
// 10.2.45\r
typedef struct {\r
// Containers\r
- const Dcm_DspTestResultObdmidTidType *DspTestResultObdmidTid; // (0..*)\r
- const Dcm_DspTestResultTidType *DspTestResultTid; // (0..*)\r
-} Dcm_DspTestResultByObdmidType;\r
+ const Dcm_DspTestResultObdmidTidType *DspTestResultObdmidTid; // (0..*)\r
+ const Dcm_DspTestResultTidType *DspTestResultTid; // (0..*)\r
+} Dcm_DspTestResultByObdmidType; /** @req DCM682 */\r
\r
// 10.2.48\r
typedef struct {\r
- boolean DspVehInfoUsePort; // (1)\r
- uint8 DspVehInfoType; // (1)\r
- uint8 DspVehInfoSize; // (1)\r
- Dcm_CallbackGetInfoTypeValueFncType DspGetVehInfoTypeFnc; // (1)\r
-} Dcm_DspVehInfoType;\r
+ boolean DspVehInfoUsePort; // (1)\r
+ uint8 DspVehInfoType; // (1) /** @req DCM631 */\r
+ uint8 DspVehInfoSize; // (1) /** @req DCM632 */\r
+ Dcm_CallbackGetInfoTypeValueFncType DspGetVehInfoTypeFnc; // (1) /** @req DCM633 */\r
+} Dcm_DspVehInfoType; /** @req DCM630 */\r
\r
// 10.2.21\r
typedef struct {\r
- uint8 DspMaxDidToRead; // (0..1)\r
+ uint8 DspMaxDidToRead; // (0..1) /** @req DCM638 */\r
// Containers\r
- const Dcm_DspDidType *DspDid; // (0..*)\r
- const Dcm_DspDidInfoType *DspDidInfo; // (0..*)\r
- const Dcm_DspEcuResetType *DspEcuReset; // (0..*)\r
- const Dcm_DspPidType *DspPid; // (0..*)\r
- const Dcm_DspReadDTCType *DspReadDTC; // (1)\r
- const Dcm_DspRequestControlType *DspRequestControl; // (0..*)\r
- const Dcm_DspRoutineType *DspRoutine; // (0..*)\r
- const Dcm_DspRoutineInfoType *DspRoutineInfo; // (0..*)\r
- const Dcm_DspSecurityType *DspSecurity; // (0..*)\r
- const Dcm_DspSessionType *DspSession; // (1)\r
- const Dcm_DspTestResultByObdmidType *DspTestResultByObdmid; // (0..*)\r
- const Dcm_DspVehInfoType *DspVehInfo;\r
+ const Dcm_DspDidType *DspDid; // (0..*)\r
+ const Dcm_DspDidInfoType *DspDidInfo; // (0..*)\r
+ const Dcm_DspEcuResetType *DspEcuReset; // (0..*)\r
+ const Dcm_DspPidType *DspPid; // (0..*)\r
+ const Dcm_DspReadDTCType *DspReadDTC; // (1)\r
+ const Dcm_DspRequestControlType *DspRequestControl; // (0..*)\r
+ const Dcm_DspRoutineType *DspRoutine; // (0..*)\r
+ const Dcm_DspRoutineInfoType *DspRoutineInfo; // (0..*)\r
+ const Dcm_DspSecurityType *DspSecurity; // (0..*)\r
+ const Dcm_DspSessionType *DspSession; // (1)\r
+ const Dcm_DspTestResultByObdmidType *DspTestResultByObdmid; // (0..*)\r
+ const Dcm_DspVehInfoType *DspVehInfo;\r
} Dcm_DspType;\r
\r
/*******\r
*******/\r
// 10.2.4 DcmDsdService\r
typedef struct {\r
- uint8 DsdSidTabServiceId; // (1)\r
- boolean DsdSidTabSubfuncAvail; // (1)\r
- const Dcm_DspSecurityRowType **DsdSidTabSecurityLevelRef; // (1..*)\r
- const Dcm_DspSessionRowType **DsdSidTabSessionLevelRef; // (1..*)\r
+ uint8 DsdSidTabServiceId; // (1)\r
+ boolean DsdSidTabSubfuncAvail; // (1)\r
+ const Dcm_DspSecurityRowType **DsdSidTabSecurityLevelRef; // (1..*)\r
+ const Dcm_DspSessionRowType **DsdSidTabSessionLevelRef; // (1..*)\r
// Containers\r
- boolean Arc_EOL;\r
+ boolean Arc_EOL;\r
} Dcm_DsdServiceType;\r
\r
// 10.2.3 DcmDsdServiceTable\r
typedef struct {\r
- uint8 DsdSidTabId; // (1)\r
+ uint8 DsdSidTabId; // (1)\r
// Containers\r
- const Dcm_DsdServiceType *DsdService; // (1..*)\r
- boolean Arc_EOL;\r
-} Dcm_DsdServiceTableType;\r
+ const Dcm_DsdServiceType *DsdService; // (1..*)\r
+ boolean Arc_EOL;\r
+} Dcm_DsdServiceTableType; /** @req DCM071 */\r
\r
// 10.2.2 DcmDsd\r
typedef struct {\r
typedef enum\r
{\r
BUFFER_AVAILABLE,\r
- BUFFER_BUSY,\r
+ BUFFER_BUSY\r
}Dcm_DslBufferStatusType;\r
\r
\r
\r
typedef struct {\r
Dcm_DslBufferStatusType status; // Flag for buffer in use.\r
-\r
} Dcm_DslBufferRuntimeType;\r
\r
// 10.2.6\r
typedef struct {\r
- uint8 DslBufferID; // (1) // Kept for reference, will be removed (polite calls will be made).\r
- uint16 DslBufferSize; // (1)\r
- PduInfoType pduInfo;\r
- Dcm_DslBufferRuntimeType *externalBufferRuntimeData;\r
-} Dcm_DslBufferType;\r
+ uint8 DslBufferID; // (1) // Kept for reference, will be removed (polite calls will be made).\r
+ uint16 DslBufferSize; // (1)\r
+ PduInfoType pduInfo;\r
+ Dcm_DslBufferRuntimeType *externalBufferRuntimeData;\r
+} Dcm_DslBufferType; /** @req DCM032 */\r
\r
// 10.2.7\r
typedef struct {\r
- Dcm_CallbackStartProtocolFncType StartProtocol;\r
- Dcm_CallbackStopProtocolFncType StopProtocol;\r
- boolean Arc_EOL;\r
-} Dcm_DslCallbackDCMRequestServiceType;\r
+ Dcm_CallbackStartProtocolFncType StartProtocol;\r
+ Dcm_CallbackStopProtocolFncType StopProtocol;\r
+ boolean Arc_EOL;\r
+} Dcm_DslCallbackDCMRequestServiceType; /** @req DCM679 */\r
\r
// 10.2.8\r
typedef struct {\r
- boolean DslDiagRespForceRespPendEn; // (1)\r
- uint8 DslDiagRespMaxNumRespPend; // (1)\r
+ boolean DslDiagRespForceRespPendEn; // (1)\r
+ uint8 DslDiagRespMaxNumRespPend; // (1)\r
} Dcm_DslDiagRespType;\r
\r
// 10.2.18\r
typedef struct {\r
- uint16 TimStrP2ServerMax; // (1)\r
- uint16 TimStrP2ServerMin; // (1)\r
- uint16 TimStrP2StarServerMax; // (1)\r
- uint16 TimStrP2StarServerMin; // (1)\r
- uint16 TimStrS3Server; // (1)\r
- const boolean Arc_EOL;\r
+ uint16 TimStrP2ServerMax; // (1)\r
+ uint16 TimStrP2ServerMin; // (1)\r
+ uint16 TimStrP2StarServerMax; // (1)\r
+ uint16 TimStrP2StarServerMin; // (1)\r
+ uint16 TimStrS3Server; // (1)\r
+ const boolean Arc_EOL;\r
} Dcm_DslProtocolTimingRowType;\r
\r
// 10.2.17\r
typedef struct {\r
const Dcm_DslProtocolTimingRowType *DslProtocolTimingRow; // (0..*)\r
-} Dcm_DslProtocolTimingType;\r
+} Dcm_DslProtocolTimingType; /** @req DCM031 */\r
\r
// 10.2.15\r
typedef struct {\r
\r
// 10.2.13\r
struct Dcm_DslProtocolRxType_t {\r
- const Dcm_DslMainConnectionType *DslMainConnectionParent; // (1) /* Cross reference. */\r
- const Dcm_ProtocolAddrTypeType DslProtocolAddrType; // (1)\r
- const uint32 DcmDslProtocolRxPduId; // (1)\r
- const uint32 DcmDslProtocolRxTesterSourceAddr_v4; // (1)\r
- const uint8 DcmDslProtocolRxChannelId_v4; // (1)\r
- const boolean Arc_EOL;\r
+ const Dcm_DslMainConnectionType *DslMainConnectionParent; // (1) /* Cross reference. */\r
+ const Dcm_ProtocolAddrTypeType DslProtocolAddrType; // (1)\r
+ const PduIdType DcmDslProtocolRxPduId; // (1)\r
+ const uint32 DcmDslProtocolRxTesterSourceAddr_v4; // (1)\r
+ const uint8 DcmDslProtocolRxChannelId_v4; // (1)\r
+ const boolean Arc_EOL;\r
};\r
\r
/* Makes it possible to cross-reference structures. */\r
\r
// 10.2.14\r
struct Dcm_DslProtocolTxType_t {\r
- const Dcm_DslMainConnectionType *DslMainConnectionParent; // (1) /* Cross reference. */\r
- const uint32 DcmDslProtocolTxPduId; // (1) /* Will be removed (polite), kept for reference. */\r
- const boolean Arc_EOL;\r
+ const Dcm_DslMainConnectionType *DslMainConnectionParent; // (1) /* Cross reference. */\r
+ const PduIdType DcmDslProtocolTxPduId; // (1) /* Will be removed (polite), kept for reference. */\r
+ const boolean Arc_EOL;\r
};\r
\r
// -- UH\r
\r
// 10.2.12\r
struct Dcm_DslMainConnectionType_t { // Cross referenced from Dcm_DslProtocolRxType_t.\r
- const Dcm_DslConnectionType *DslConnectionParent; // Cross reference.\r
- const Dcm_DslPeriodicTransmissionType *DslPeriodicTransmissionConRef; // (0..1)\r
- const Dcm_DslResponseOnEventType *DslROEConnectionRef; // (0..*)\r
+ const Dcm_DslConnectionType *DslConnectionParent; // Cross reference.\r
+ const Dcm_DslPeriodicTransmissionType *DslPeriodicTransmissionConRef; // (0..1)\r
+ const Dcm_DslResponseOnEventType *DslROEConnectionRef; // (0..*)\r
// Containers\r
- const Dcm_DslProtocolRxType *DslProtocolRx; // (1..*) Remove?\r
- const Dcm_DslProtocolTxType *DslProtocolTx; // (1)\r
+ const Dcm_DslProtocolRxType *DslProtocolRx; // (1..*) Remove?\r
+ const Dcm_DslProtocolTxType *DslProtocolTx; // (1)\r
};\r
\r
/* Make it possible to cross reference. */\r
// 10.2.11\r
struct Dcm_DslConnectionType_t {\r
// Containers\r
- const Dcm_DslProtocolRowType *DslProtocolRow; // Cross reference.\r
- const Dcm_DslMainConnectionType *DslMainConnection; // (1)\r
- const Dcm_DslPeriodicTransmissionType *DslPeriodicTransmission; // (0..1)\r
- const Dcm_DslResponseOnEventType *DslResponseOnEvent; // (0..1)\r
- boolean Arc_EOL;\r
+ const Dcm_DslProtocolRowType *DslProtocolRow; // Cross reference.\r
+ const Dcm_DslMainConnectionType *DslMainConnection; // (1)\r
+ const Dcm_DslPeriodicTransmissionType *DslPeriodicTransmission; // (0..1)\r
+ const Dcm_DslResponseOnEventType *DslResponseOnEvent; // (0..1)\r
+ boolean Arc_EOL;\r
};\r
\r
typedef enum {\r
#define DCM_DSL_LOCAL_BUFFER_LENGTH 8\r
\r
typedef struct {\r
- Dcm_DslBufferUserType status;\r
- uint8 buffer[DCM_DSL_LOCAL_BUFFER_LENGTH];\r
- PduLengthType messageLenght;\r
- PduInfoType PduInfo;\r
+ Dcm_DslBufferUserType status;\r
+ uint8 buffer[DCM_DSL_LOCAL_BUFFER_LENGTH];\r
+ PduLengthType messageLenght;\r
+ PduInfoType PduInfo;\r
} Dcm_DslLocalBufferType;\r
\r
\r
typedef struct {\r
- PduIdType diagReqestRxPduId; // Tester request PduId.\r
- uint32 stateTimeoutCount; // Counter for timeout.\r
- Dcm_DslBufferUserType externalRxBufferStatus;\r
- PduInfoType diagnosticRequestFromTester;\r
- PduInfoType diagnosticResponseFromDsd;\r
- Dcm_DslBufferUserType externalTxBufferStatus;\r
- boolean protocolStarted; // Has the protocol been started?\r
- Dcm_DslLocalBufferType localRxBuffer;\r
- Dcm_DslLocalBufferType localTxBuffer;\r
- boolean diagnosticActiveComM; //\r
- uint16 S3ServerTimeoutCount;\r
- uint8 responsePendingCount;\r
- Dcm_SecLevelType securityLevel;\r
- Dcm_SesCtrlType sessionControl;\r
+ PduIdType diagReqestRxPduId; // Tester request PduId.\r
+ uint32 stateTimeoutCount; // Counter for timeout.\r
+ Dcm_DslBufferUserType externalRxBufferStatus;\r
+ PduInfoType diagnosticRequestFromTester;\r
+ PduInfoType diagnosticResponseFromDsd;\r
+ Dcm_DslBufferUserType externalTxBufferStatus;\r
+ boolean protocolStarted; // Has the protocol been started?\r
+ Dcm_DslLocalBufferType localRxBuffer;\r
+ Dcm_DslLocalBufferType localTxBuffer;\r
+ boolean diagnosticActiveComM; //\r
+ uint16 S3ServerTimeoutCount;\r
+ uint8 responsePendingCount;\r
+ Dcm_SecLevelType securityLevel;\r
+ Dcm_SesCtrlType sessionControl;\r
} Dcm_DslRunTimeProtocolParametersType;\r
\r
// 10.2.10\r
struct Dcm_DslProtocolRowType_t { // Cross referenced from Dcm_DslConnectionType_t.\r
- Dcm_ProtocolType DslProtocolID; // (1)\r
- boolean DslProtocolIsParallelExecutab; // (1)\r
- uint16 DslProtocolPreemptTimeout; // (1)\r
- uint8 DslProtocolPriority; // (1)\r
- Dcm_ProtocolTransTypeType DslProtocolTransType; // (1)\r
- const Dcm_DslBufferType *DslProtocolRxBufferID; // (1)\r
- const Dcm_DslBufferType *DslProtocolTxBufferID; // (1)\r
- const Dcm_DsdServiceTableType *DslProtocolSIDTable; // (1)\r
- const Dcm_DslProtocolTimingRowType *DslProtocolTimeLimit; // (0..1)\r
+ Dcm_ProtocolType DslProtocolID; // (1)\r
+ boolean DslProtocolIsParallelExecutab; // (1)\r
+ uint16 DslProtocolPreemptTimeout; // (1)\r
+ uint8 DslProtocolPriority; // (1)\r
+ Dcm_ProtocolTransTypeType DslProtocolTransType; // (1)\r
+ const Dcm_DslBufferType *DslProtocolRxBufferID; // (1)\r
+ const Dcm_DslBufferType *DslProtocolTxBufferID; // (1)\r
+ const Dcm_DsdServiceTableType *DslProtocolSIDTable; // (1)\r
+ const Dcm_DslProtocolTimingRowType *DslProtocolTimeLimit; // (0..1)\r
// Containers\r
- const Dcm_DslConnectionType *DslConnection; // (1..*)\r
+ const Dcm_DslConnectionType *DslConnection; // (1..*)\r
// Reference to runtime parameters to this protocol.\r
- Dcm_DslRunTimeProtocolParametersType *DslRunTimeProtocolParameters; // Maybe this needs to change to index.\r
- boolean Arc_EOL;\r
+ Dcm_DslRunTimeProtocolParametersType *DslRunTimeProtocolParameters; // Maybe this needs to change to index.\r
+ boolean Arc_EOL;\r
};\r
\r
// 10.2.9\r
typedef struct {\r
-// Containers\r
- const Dcm_DslProtocolRxType *DslProtocolRxGlobalList; // (1..*) A polite list for all RX protocol configurations.\r
- const Dcm_DslProtocolTxType *DslProtocolTxGlobalList; // (1..*) A polite list for all TX protocol configurations.\r
-const Dcm_DslProtocolRowType *DslProtocolRowList; // (1..*)\r
+ // Containers\r
+ const Dcm_DslProtocolRxType *DslProtocolRxGlobalList; // (1..*) A polite list for all RX protocol configurations.\r
+ const Dcm_DslProtocolTxType *DslProtocolTxGlobalList; // (1..*) A polite list for all TX protocol configurations.\r
+ const Dcm_DslProtocolRowType *DslProtocolRowList; // (1..*)\r
} Dcm_DslProtocolType;\r
\r
// 10.2.19\r
typedef struct {\r
-Dcm_CallbackIndicationFncType Indication;\r
-boolean Arc_EOL;\r
-} Dcm_DslServiceRequestIndicationType;\r
+ Dcm_CallbackIndicationFncType Indication;\r
+ boolean Arc_EOL;\r
+} Dcm_DslServiceRequestIndicationType; /** @req DCM681 */\r
\r
// 10.2.20\r
typedef struct {\r
-Dcm_CallbackGetSesChgPermissionFncType GetSesChgPermission;\r
-Dcm_CallbackChangeIndicationFncType ChangeIndication;\r
-Dcm_CallbackConfirmationRespPendFncType ConfirmationRespPend;\r
-boolean Arc_EOL;\r
-} Dcm_DslSessionControlType;\r
+ Dcm_CallbackGetSesChgPermissionFncType GetSesChgPermission;\r
+ Dcm_CallbackChangeIndicationFncType ChangeIndication;\r
+ Dcm_CallbackConfirmationRespPendFncType ConfirmationRespPend;\r
+ boolean Arc_EOL;\r
+} Dcm_DslSessionControlType; /** @req DCM680 */\r
\r
// 10.2.5\r
typedef struct {\r
-// Containers\r
-const Dcm_DslBufferType *DslBuffer; // (1..256)\r
-const Dcm_DslCallbackDCMRequestServiceType *DslCallbackDCMRequestService; // (1..*)\r
-const Dcm_DslDiagRespType *DslDiagResp; // (1)\r
-const Dcm_DslProtocolType *DslProtocol; // (1)\r
-const Dcm_DslProtocolTimingType *DslProtocolTiming; // (1)\r
-const Dcm_DslServiceRequestIndicationType *DslServiceRequestIndication; // (0..*)\r
-const Dcm_DslSessionControlType *DslSessionControl; // (1..*)\r
+ // Containers\r
+ const Dcm_DslBufferType *DslBuffer; // (1..256)\r
+ const Dcm_DslCallbackDCMRequestServiceType *DslCallbackDCMRequestService; // (1..*)\r
+ const Dcm_DslDiagRespType *DslDiagResp; // (1)\r
+ const Dcm_DslProtocolType *DslProtocol; // (1)\r
+ const Dcm_DslProtocolTimingType *DslProtocolTiming; // (1)\r
+ const Dcm_DslServiceRequestIndicationType *DslServiceRequestIndication; // (0..*)\r
+ const Dcm_DslSessionControlType *DslSessionControl; // (1..*)\r
} Dcm_DslType;\r
\r
// 10.2.1 Dcm\r
typedef struct {\r
-// Containers\r
-const Dcm_DspType *Dsp; // (1)\r
-const Dcm_DsdType *Dsd; // (1)\r
-const Dcm_DslType *Dsl; // (1)\r
+ // Containers\r
+ const Dcm_DspType *Dsp; // (1)\r
+ const Dcm_DsdType *Dsd; // (1)\r
+ const Dcm_DslType *Dsl; // (1)\r
} Dcm_ConfigType;\r
\r
/*\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+// 904 PC-Lint MISRA 14.7: OK. Allow VALIDATE, VALIDATE_RV and VALIDATE_NO_RV to return value.\r
+//lint -emacro(904,VALIDATE_RV,VALIDATE_NO_RV,VALIDATE)\r
+// 522 PC-Lint exception for empty functions\r
+//lint -esym(522,storeFreezeFrameDataEvtMem)\r
+//lint -esym(522,deleteFreezeFrameDataPriMem)\r
+//lint -esym(522,storeFreezeFrameDataPreInit)\r
+//lint -esym(522,storeFreezeFrameDataPriMem)\r
+//lint -esym(522,updateFreezeFrameOccurrencePreInit)\r
\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DEM126 */\r
+/** @req DEM151.partially */\r
+/** @req DEM152 */\r
+/** @req DEM013.14229-1 */\r
+/** @req DEM277 */\r
+/** @req DEM363 */\r
+/** @req DEM113 */ /** @req DEM174 */\r
+/** @req DEM286 */\r
+/** @req DEM267 */\r
+/** @req DEM364 */\r
+/** @req DEM114 */\r
+/** @req DEM124 */\r
+/** @req DEM370 */\r
+\r
\r
\r
#include <string.h>\r
#include "Dem.h"\r
-#include "Det.h"\r
//#include "Fim.h"\r
//#include "Nvm.h"\r
//#include "SchM_Dem.h"\r
#include "MemMap.h"\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
\r
/*\r
* Local defines\r
#define DEBOUNCE_FDC_TEST_FAILED 127\r
#define DEBOUNCE_FDC_TEST_PASSED -128\r
\r
+#if ( DEM_DEV_ERROR_DETECT == STD_ON )\r
+#include "Det.h"\r
+/** @req DEM117 */\r
+#define VALIDATE_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_DEM, 0, _api, _err); \\r
+ return _rv; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_DEM, 0, _api, _err); \\r
+ return; \\r
+ }\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
+\r
+#else\r
+#define VALIDATE_RV(_exp,_api,_err,_rv )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#endif\r
+\r
+#if (DEM_OBD_SUPPORT == STD_ON)\r
+#error "DEM_OBD_SUPPORT is set to STD_ON, this is not supported by the code."\r
+#endif\r
+\r
+#if (DEM_PTO_SUPPORT == STD_ON)\r
+#error "DEM_PTO_SUPPORT is set to STD_ON, this is not supported by the code."\r
+#endif\r
+\r
+#if (DEM_TYPE_OF_DTC_SUPPORTED != 0x01)\r
+#error "DEM_TYPE_OF_DTC_SUPPORTED is not set to 1 (ISO14229-1), only ISO14229-1 is currently supported by the code."\r
+#endif\r
+\r
+\r
/*\r
* Local types\r
*/\r
Dem_EventIdType eventId;\r
const Dem_EventParameterType *eventParamRef;\r
sint8 faultDetectionCounter;\r
- uint16 occurrence;\r
- Dem_EventStatusExtendedType eventStatusExtended;\r
+ uint16 occurrence; /** @req DEM011 */\r
+ Dem_EventStatusExtendedType eventStatusExtended; /** @req DEM006 */\r
boolean errorStatusChanged;\r
} EventStatusRecType;\r
\r
DEM_UNINITIALIZED = 0,\r
DEM_PREINITIALIZED,\r
DEM_INITIALIZED\r
-} Dem_StateType;\r
+} Dem_StateType; /** @req DEM169 */\r
\r
\r
static Dem_StateType demState = DEM_UNINITIALIZED;\r
// Help pointer to configuration set\r
static const Dem_ConfigSetType *configSet;\r
\r
-#if (DEM_VERSION_INFO_API == STD_ON)\r
-static Std_VersionInfoType _Dem_VersionInfo =\r
-{\r
- .vendorID = (uint16)1,\r
- .moduleID = (uint16)1,\r
- .instanceID = (uint8)1,\r
- .sw_major_version = (uint8)DEM_SW_MAJOR_VERSION,\r
- .sw_minor_version = (uint8)DEM_SW_MINOR_VERSION,\r
- .sw_patch_version = (uint8)DEM_SW_PATCH_VERSION,\r
- .ar_major_version = (uint8)DEM_AR_MAJOR_VERSION,\r
- .ar_minor_version = (uint8)DEM_AR_MINOR_VERSION,\r
- .ar_patch_version = (uint8)DEM_AR_PATCH_VERSION,\r
-};\r
-#endif /* DEM_VERSION_INFO_API */\r
-\r
/*\r
* Allocation of DTC filter parameters\r
*/\r
/*\r
* Allocation of pre-init event memory (used between pre-init and init)\r
*/\r
+/** @req DEM207 */\r
static FreezeFrameRecType preInitFreezeFrameBuffer[DEM_MAX_NUMBER_FF_DATA_PRE_INIT];\r
static ExtDataRecType preInitExtDataBuffer[DEM_MAX_NUMBER_EXT_DATA_PRE_INIT];\r
\r
/*\r
* Allocation of primary event memory ramlog (after init) in uninitialized memory\r
*/\r
+/** @req DEM162 */\r
static EventRecType priMemEventBuffer[DEM_MAX_NUMBER_EVENT_PRI_MEM] __attribute__ ((section (".dem_eventmemory_pri")));\r
static FreezeFrameRecType priMemFreezeFrameBuffer[DEM_MAX_NUMBER_FF_DATA_PRI_MEM] __attribute__ ((section (".dem_eventmemory_pri")));\r
static ExtDataRecType priMemExtDataBuffer[DEM_MAX_NUMBER_EXT_DATA_PRI_MEM] __attribute__ ((section (".dem_eventmemory_pri")));\r
* Procedure: zeroPriMemBuffers\r
* Description: Fill the primary buffers with zeroes\r
*/\r
+//lint -e957 PC-Lint exception - Used only by DemTest\r
void demZeroPriMemBuffers(void)\r
{\r
memset(priMemEventBuffer, 0, sizeof(priMemEventBuffer));\r
static ChecksumType calcChecksum(void *data, uint16 nrOfBytes)\r
{\r
uint16 i;\r
- uint8 *ptr = (uint8*)data;\r
+ uint8 *byte = (uint8*)data;\r
ChecksumType sum = 0;\r
\r
- for (i = 0; i < nrOfBytes; i++)\r
- sum += *ptr++;\r
- sum ^= 0xaaaa;\r
+ for (i = 0; i < nrOfBytes; i++) {\r
+ sum += byte[i];\r
+ }\r
+ sum ^= 0xaaaau;\r
return sum;\r
}\r
\r
static boolean checkDtcOrigin(Dem_DTCOriginType dtcOrigin, const Dem_EventParameterType *eventParam)\r
{\r
boolean result = FALSE;\r
+ boolean dtcOriginFound = FALSE;\r
uint16 i;\r
\r
- for (i = 0; (eventParam->EventClass->EventDestination[i] != dtcOrigin) && (i < DEM_MAX_NR_OF_EVENT_DESTINATION); i++);\r
+ for (i = 0;(i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (!dtcOriginFound); i++){\r
+ dtcOriginFound = (eventParam->EventClass->EventDestination[i] == dtcOrigin);\r
+ }\r
\r
- if (i < DEM_MAX_NR_OF_EVENT_DESTINATION) {\r
+ if (dtcOriginFound) {\r
result = TRUE;\r
}\r
\r
return result;\r
}\r
\r
-\r
/*\r
* Procedure: checkDtcSeverityMask\r
* Description: Return TRUE if "dtcSeverityMask" match any of the events DTC severity otherwise FALSE.\r
*/\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715} Symbol not referenced\r
static boolean checkDtcSeverityMask(Dem_DTCSeverityType dtcSeverityMask, const Dem_EventParameterType *eventParam)\r
{\r
boolean result = TRUE;\r
* Procedure: checkDtcFaultDetectionCounterMask\r
* Description: TBD.\r
*/\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715} Symbol not referenced\r
static boolean checkDtcFaultDetectionCounter(const Dem_EventParameterType *eventParam)\r
{\r
boolean result = TRUE;\r
*/\r
static void lookupEventStatusRec(Dem_EventIdType eventId, EventStatusRecType **const eventStatusRec)\r
{\r
- EventStatusRecType *eventStatusRecPtr = eventStatusBuffer;\r
+ uint8 i;\r
+ boolean eventIdFound = FALSE;\r
\r
- while ((eventStatusRecPtr->eventId != eventId) && (eventStatusRecPtr < &eventStatusBuffer[DEM_MAX_NUMBER_EVENT])) {\r
- eventStatusRecPtr++;\r
+ for (i = 0; (i < DEM_MAX_NUMBER_EVENT) && (!eventIdFound); i++) {\r
+ eventIdFound = (eventStatusBuffer[i].eventId == eventId);\r
}\r
\r
- if (eventStatusRecPtr < &eventStatusBuffer[DEM_MAX_NUMBER_EVENT]) {\r
- *eventStatusRec = eventStatusRecPtr;\r
+ if (eventIdFound) {\r
+ *eventStatusRec = &eventStatusBuffer[i-1];\r
} else {\r
*eventStatusRec = NULL;\r
}\r
*/\r
static void lookupEventIdParameter(Dem_EventIdType eventId, const Dem_EventParameterType **const eventIdParam)\r
{\r
- const Dem_EventParameterType *EventIdParamPtr = configSet->EventParameter;\r
+ const Dem_EventParameterType *EventIdParamList = configSet->EventParameter;\r
\r
// Lookup the correct event id parameters\r
- while ((EventIdParamPtr->EventID != eventId) && !EventIdParamPtr->Arc_EOL) {\r
- EventIdParamPtr++;\r
+ uint16 i=0;\r
+ while ((EventIdParamList[i].EventID != eventId) && (!EventIdParamList[i].Arc_EOL)) {\r
+ i++;\r
}\r
\r
- if (!EventIdParamPtr->Arc_EOL) {\r
- *eventIdParam = EventIdParamPtr;\r
+ if (!EventIdParamList[i].Arc_EOL) {\r
+ *eventIdParam = &EventIdParamList[i];\r
} else {\r
*eventIdParam = NULL;\r
}\r
* Procedure: preDebounceNone\r
* Description: Returns the result of the debouncing.\r
*/\r
-static Dem_EventStatusType preDebounceNone(Dem_EventStatusType reportedStatus, EventStatusRecType* statusRecord) {\r
+static Dem_EventStatusType preDebounceNone(const Dem_EventStatusType reportedStatus, const EventStatusRecType* statusRecord) {\r
Dem_EventStatusType returnCode;\r
+ (void)statusRecord; // Just to get rid of PC-Lint warnings\r
\r
switch (reportedStatus) {\r
- case DEM_EVENT_STATUS_FAILED:\r
- case DEM_EVENT_STATUS_PASSED:\r
+ case DEM_EVENT_STATUS_FAILED: /** @req DEM091.NoneFailed */\r
+ case DEM_EVENT_STATUS_PASSED: /** @req DEM091.NonePassed */\r
// Already debounced, do nothing.\r
break;\r
\r
default:\r
// TODO: What to do with PREFAIL and PREPASSED on no debouncing?\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_PREDEBOUNCE_NONE_ID, DEM_E_PARAM_DATA);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_PREDEBOUNCE_NONE_ID, DEM_E_PARAM_DATA);\r
break;\r
}\r
\r
switch (reportedStatus) {\r
case DEM_EVENT_STATUS_PREFAILED:\r
if (statusRecord->faultDetectionCounter < DEBOUNCE_FDC_TEST_FAILED) {\r
- if (pdVars->JumpUp && (statusRecord->faultDetectionCounter < 0)) {\r
+ if ((pdVars->JumpUp) && (statusRecord->faultDetectionCounter < 0)) {\r
statusRecord->faultDetectionCounter = 0;\r
} else {\r
- if (((sint16)statusRecord->faultDetectionCounter + pdVars->CountInStepSize) < DEBOUNCE_FDC_TEST_FAILED) {\r
- statusRecord->faultDetectionCounter += pdVars->CountInStepSize;\r
+ if (((sint16)statusRecord->faultDetectionCounter + (sint8)pdVars->CountInStepSize) < DEBOUNCE_FDC_TEST_FAILED) {\r
+ statusRecord->faultDetectionCounter += (sint8)pdVars->CountInStepSize;\r
} else {\r
statusRecord->faultDetectionCounter = DEBOUNCE_FDC_TEST_FAILED;\r
}\r
\r
case DEM_EVENT_STATUS_PREPASSED:\r
if (statusRecord->faultDetectionCounter > DEBOUNCE_FDC_TEST_PASSED) {\r
- if (pdVars->JumpDown && (statusRecord->faultDetectionCounter > 0)) {\r
+ if ((pdVars->JumpDown) && (statusRecord->faultDetectionCounter > 0)) {\r
statusRecord->faultDetectionCounter = 0;\r
} else {\r
- if (((sint16)statusRecord->faultDetectionCounter - pdVars->CountOutStepSize) > DEBOUNCE_FDC_TEST_PASSED) {\r
- statusRecord->faultDetectionCounter -= pdVars->CountOutStepSize;\r
+ if (((sint16)statusRecord->faultDetectionCounter - (sint8)pdVars->CountOutStepSize) > DEBOUNCE_FDC_TEST_PASSED) {\r
+ statusRecord->faultDetectionCounter -= (sint8)pdVars->CountOutStepSize;\r
} else {\r
statusRecord->faultDetectionCounter = DEBOUNCE_FDC_TEST_PASSED;\r
}\r
break;\r
\r
case DEM_EVENT_STATUS_FAILED:\r
- statusRecord->faultDetectionCounter = DEBOUNCE_FDC_TEST_FAILED;\r
+ statusRecord->faultDetectionCounter = DEBOUNCE_FDC_TEST_FAILED; /** @req DEM091.CounterFailed */\r
break;\r
\r
case DEM_EVENT_STATUS_PASSED:\r
- statusRecord->faultDetectionCounter = DEBOUNCE_FDC_TEST_PASSED;\r
+ statusRecord->faultDetectionCounter = DEBOUNCE_FDC_TEST_PASSED; /** @req DEM091.CounterPassed */\r
break;\r
\r
default:\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_PREDEBOUNCE_COUNTER_BASED_ID, DEM_E_PARAM_DATA);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_PREDEBOUNCE_COUNTER_BASED_ID, DEM_E_PARAM_DATA);\r
break;\r
\r
}\r
}\r
else {\r
// Error: Event status buffer full\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_EVENT_STATUS_BUFF_FULL);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_EVENT_STATUS_BUFF_FULL);\r
}\r
}\r
\r
\r
if (eventStatusRecPtr != NULL) {\r
// Handle debouncing\r
- switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) {\r
- case DEM_NO_PRE_DEBOUNCE:\r
- eventStatus = preDebounceNone(eventStatus, eventStatusRecPtr);\r
- break;\r
+ if (eventParam->EventClass->PreDebounceAlgorithmClass != NULL) {\r
+ switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) { /** @req DEM004 */ /** @req DEM342 */\r
+ case DEM_NO_PRE_DEBOUNCE:\r
+ eventStatus = preDebounceNone(eventStatus, eventStatusRecPtr);\r
+ break;\r
\r
- case DEM_PRE_DEBOUNCE_COUNTER_BASED:\r
- eventStatus = preDebounceCounterBased(eventStatus, eventStatusRecPtr);\r
- break;\r
+ case DEM_PRE_DEBOUNCE_COUNTER_BASED:\r
+ eventStatus = preDebounceCounterBased(eventStatus, eventStatusRecPtr);\r
+ break;\r
\r
- default:\r
- // Don't know how to handle this.\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
-#endif\r
- break;\r
+ default:\r
+ // Don't know how to handle this.\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
+ break;\r
+ }\r
}\r
\r
-\r
eventStatusRecPtr->errorStatusChanged = FALSE;\r
\r
// Check test failed\r
eventStatusRecPtr->occurrence++;\r
eventStatusRecPtr->errorStatusChanged = TRUE;\r
}\r
+ /** @req DEM036 */ /** @req DEM379.PendingSet */\r
eventStatusRecPtr->eventStatusExtended |= (DEM_TEST_FAILED | DEM_TEST_FAILED_THIS_OPERATION_CYCLE | DEM_TEST_FAILED_SINCE_LAST_CLEAR | DEM_PENDING_DTC);\r
- eventStatusRecPtr->eventStatusExtended &= ~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE);\r
+ eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE);\r
}\r
\r
// Check test passed\r
if (eventStatusRecPtr->eventStatusExtended & DEM_TEST_FAILED) {\r
eventStatusRecPtr->errorStatusChanged = TRUE;\r
}\r
- eventStatusRecPtr->eventStatusExtended &= ~DEM_TEST_FAILED;\r
- eventStatusRecPtr->eventStatusExtended &= ~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE);\r
+ /** @req DEM036 */\r
+ eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_TEST_FAILED;\r
+ eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~(DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR | DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE);\r
}\r
\r
// Copy the record\r
else {\r
// Copy an empty record to return data\r
eventStatusRec->eventId = DEM_EVENT_ID_NULL;\r
- eventStatusRecPtr->faultDetectionCounter = 0;\r
+ eventStatusRec->faultDetectionCounter = 0;\r
eventStatusRec->occurrence = 0;\r
eventStatusRec->eventStatusExtended = DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE | DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR;\r
eventStatusRec->errorStatusChanged = FALSE;\r
* Procedure: mergeEventStatusRec\r
* Description: Update the occurrence counter of status, if not exist a new record is created\r
*/\r
-static void mergeEventStatusRec(EventRecType *eventRec)\r
+static void mergeEventStatusRec(const EventRecType *eventRec)\r
{\r
EventStatusRecType *eventStatusRecPtr;\r
imask_t state = McuE_EnterCriticalSection();\r
}\r
else {\r
// Error: Event status buffer full\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_MERGE_EVENT_STATUS_ID, DEM_E_EVENT_STATUS_BUFF_FULL);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_MERGE_EVENT_STATUS_ID, DEM_E_EVENT_STATUS_BUFF_FULL);\r
}\r
}\r
\r
\r
*eventStatusRec = NULL;\r
\r
- for (i = 0; (i < DEM_MAX_NUMBER_EVENT) && !dtcFound; i++) {\r
+ for (i = 0; (i < DEM_MAX_NUMBER_EVENT) && (!dtcFound); i++) {\r
if (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) {\r
if (eventStatusBuffer[i].eventParamRef->DTCClassRef != NULL) {\r
\r
\r
// Check severity\r
if ((dtcFilter.filterWithSeverity == DEM_FILTER_WITH_SEVERITY_NO)\r
- || ((dtcFilter.filterWithSeverity == DEM_FILTER_WITH_SEVERITY_YES) && checkDtcSeverityMask(dtcFilter.dtcSeverityMask, eventRec->eventParamRef))) {\r
+ || ((dtcFilter.filterWithSeverity == DEM_FILTER_WITH_SEVERITY_YES) && (checkDtcSeverityMask(dtcFilter.dtcSeverityMask, eventRec->eventParamRef)))) {\r
\r
// Check fault detection counter\r
if ((dtcFilter.filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_NO)\r
- || ((dtcFilter.filterWithSeverity == DEM_FILTER_FOR_FDC_YES) && checkDtcFaultDetectionCounter(eventRec->eventParamRef))) {\r
+ || ((dtcFilter.filterWithSeverity == DEM_FILTER_FOR_FDC_YES) && (checkDtcFaultDetectionCounter(eventRec->eventParamRef)))) {\r
dtcMatch = TRUE;\r
}\r
}\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715} Symbol not referenced\r
static void getFreezeFrameData(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)\r
{\r
// TODO: Fill out\r
}\r
\r
\r
-static void storeFreezeFrameDataPreInit(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715} Symbol not referenced\r
+static void storeFreezeFrameDataPreInit(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame)\r
{\r
// TODO: Fill out\r
}\r
\r
\r
-static void updateFreezeFrameOccurrencePreInit(EventRecType *EventBuffer)\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715} Symbol not referenced\r
+static void updateFreezeFrameOccurrencePreInit(const EventRecType *EventBuffer)\r
{\r
// TODO: Fill out\r
}\r
for (i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA) && (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i] != NULL); i++) {\r
recordSize = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->DataSize;\r
if ((storeIndex + recordSize) <= DEM_MAX_SIZE_EXT_DATA) {\r
- callbackReturnCode = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->CallbackGetExtDataRecord(&extData->data[storeIndex]);\r
+ callbackReturnCode = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->CallbackGetExtDataRecord(&extData->data[storeIndex]); /** @req DEM282 */\r
if (callbackReturnCode != E_OK) {\r
// Callback data currently not available, clear space.\r
memset(&extData->data[storeIndex], 0xFF, recordSize);\r
}\r
else {\r
// Error: Size of extended data record is bigger than reserved space.\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GET_EXTENDED_DATA_ID, DEM_E_EXT_DATA_TOO_BIG);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GET_EXTENDED_DATA_ID, DEM_E_EXT_DATA_TOO_BIG);\r
break; // Break the loop\r
}\r
}\r
* Description: Store the extended data pointed by "extendedData" to the "preInitExtDataBuffer",\r
* if non existent a new entry is created.\r
*/\r
-static void storeExtendedDataPreInit(const Dem_EventParameterType *eventParam, ExtDataRecType *extendedData)\r
+static void storeExtendedDataPreInit(const Dem_EventParameterType *eventParam, const ExtDataRecType *extendedData)\r
{\r
+ boolean eventIdFound = FALSE;\r
+ boolean eventIdFreePositionFound=FALSE;\r
uint16 i;\r
imask_t state = McuE_EnterCriticalSection();\r
\r
// Check if already stored\r
- for (i = 0; (preInitExtDataBuffer[i].eventId != eventParam->EventID) && (i<DEM_MAX_NUMBER_EXT_DATA_PRE_INIT); i++);\r
+ for (i = 0; (i<DEM_MAX_NUMBER_EXT_DATA_PRE_INIT) && (!eventIdFound); i++){\r
+ eventIdFound = (preInitExtDataBuffer[i].eventId == eventParam->EventID);\r
+ }\r
\r
- if (i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT) {\r
+ if(eventIdFound){\r
// Yes, overwrite existing\r
- memcpy(&preInitExtDataBuffer[i], extendedData, sizeof(ExtDataRecType));\r
+ memcpy(&preInitExtDataBuffer[i-1], extendedData, sizeof(ExtDataRecType));\r
}\r
- else {\r
+ else{\r
// No, lookup first free position\r
- for (i = 0; (preInitExtDataBuffer[i].eventId !=0) && (i<DEM_MAX_NUMBER_EXT_DATA_PRE_INIT); i++);\r
+ for (i = 0; (i<DEM_MAX_NUMBER_EXT_DATA_PRE_INIT) && (!eventIdFreePositionFound); i++){\r
+ if(preInitExtDataBuffer[i].eventId ==0){\r
+ eventIdFreePositionFound=TRUE;\r
+ }\r
+ }\r
\r
- if (i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT) {\r
- memcpy(&preInitExtDataBuffer[i], extendedData, sizeof(ExtDataRecType));\r
+ if (eventIdFreePositionFound) {\r
+ memcpy(&preInitExtDataBuffer[i-1], extendedData, sizeof(ExtDataRecType));\r
}\r
else {\r
// Error: Pre init extended data buffer full\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_PRE_INIT_ID, DEM_E_PRE_INIT_EXT_DATA_BUFF_FULL);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_PRE_INIT_ID, DEM_E_PRE_INIT_EXT_DATA_BUFF_FULL);\r
}\r
}\r
\r
McuE_ExitCriticalSection(state);\r
}\r
\r
-\r
/*\r
* Procedure: storeEventPriMem\r
* Description: Store the event data of "eventStatus->eventId" in "priMemEventBuffer",\r
* if non existent a new entry is created.\r
*/\r
-static void storeEventPriMem(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatus)\r
+static void storeEventPriMem(const Dem_EventParameterType *eventParam, const EventStatusRecType *eventStatus)\r
{\r
+ boolean eventIdFound = FALSE;\r
+ boolean eventIdFreePositionFound=FALSE;\r
uint16 i;\r
imask_t state = McuE_EnterCriticalSection();\r
\r
+ (void)*eventParam; // Currently not used, do this to avoid warning\r
\r
// Lookup event ID\r
- for (i = 0; (priMemEventBuffer[i].eventId != eventStatus->eventId) && (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI); i++);\r
+ for (i = 0; (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) && (!eventIdFound); i++){\r
+ eventIdFound = (priMemEventBuffer[i].eventId == eventStatus->eventId);\r
+ }\r
\r
- if (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) {\r
+ if (eventIdFound) {\r
// Update event found\r
- priMemEventBuffer[i].occurrence = eventStatus->occurrence;\r
- priMemEventBuffer[i].checksum = calcChecksum(&priMemEventBuffer[i], sizeof(EventRecType)-sizeof(ChecksumType));\r
+ priMemEventBuffer[i-1].occurrence = eventStatus->occurrence;\r
+ priMemEventBuffer[i-1].checksum = calcChecksum(&priMemEventBuffer[i-1], sizeof(EventRecType)-sizeof(ChecksumType));\r
}\r
else {\r
// Search for free position\r
- for (i=0; (priMemEventBuffer[i].eventId != DEM_EVENT_ID_NULL) && (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI); i++);\r
+ for (i=0; (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) && (!eventIdFreePositionFound); i++){\r
+ eventIdFreePositionFound = (priMemEventBuffer[i].eventId == DEM_EVENT_ID_NULL);\r
+ }\r
+\r
\r
- if (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) {\r
- priMemEventBuffer[i].eventId = eventStatus->eventId;\r
- priMemEventBuffer[i].occurrence = eventStatus->occurrence;\r
- priMemEventBuffer[i].checksum = calcChecksum(&priMemEventBuffer[i], sizeof(EventRecType)-sizeof(ChecksumType));\r
+ if (eventIdFreePositionFound) {\r
+ priMemEventBuffer[i-1].eventId = eventStatus->eventId;\r
+ priMemEventBuffer[i-1].occurrence = eventStatus->occurrence;\r
+ priMemEventBuffer[i-1].checksum = calcChecksum(&priMemEventBuffer[i-1], sizeof(EventRecType)-sizeof(ChecksumType));\r
}\r
else {\r
// Error: Pri mem event buffer full\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_STORE_EVENT_PRI_MEM_ID, DEM_E_PRI_MEM_EVENT_BUFF_FULL);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_EVENT_PRI_MEM_ID, DEM_E_PRI_MEM_EVENT_BUFF_FULL);\r
}\r
}\r
\r
McuE_ExitCriticalSection(state);\r
}\r
\r
-\r
/*\r
* Procedure: deleteEventPriMem\r
* Description: Delete the event data of "eventParam->eventId" from "priMemEventBuffer".\r
*/\r
static void deleteEventPriMem(const Dem_EventParameterType *eventParam)\r
{\r
+ boolean eventIdFound = FALSE;\r
uint16 i;\r
imask_t state = McuE_EnterCriticalSection();\r
\r
\r
// Lookup event ID\r
- for (i = 0; (priMemEventBuffer[i].eventId != eventParam->EventID) && (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI); i++);\r
+ for (i = 0; (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) && (!eventIdFound); i++){\r
+ eventIdFound = (priMemEventBuffer[i].eventId == eventParam->EventID);\r
+ }\r
\r
- if (i < DEM_MAX_NUMBER_EVENT_ENTRY_PRI) {\r
+ if (eventIdFound) {\r
// Delete event found\r
- memset(&priMemEventBuffer[i], 0, sizeof(EventRecType));\r
+ memset(&priMemEventBuffer[i-1], 0, sizeof(EventRecType));\r
}\r
\r
McuE_ExitCriticalSection(state);\r
}\r
\r
-\r
/*\r
* Procedure: storeEventEvtMem\r
* Description: Store the event data of "eventStatus->eventId" in event memory according to\r
* "eventParam" destination option.\r
*/\r
-static void storeEventEvtMem(const Dem_EventParameterType *eventParam, EventStatusRecType *eventStatus)\r
+static void storeEventEvtMem(const Dem_EventParameterType *eventParam, const EventStatusRecType *eventStatus)\r
{\r
uint16 i;\r
\r
- for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {\r
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION)\r
+ && (eventParam->EventClass->EventDestination[i] != DEM_EVENT_DESTINATION_END_OF_LIST); i++) {\r
switch (eventParam->EventClass->EventDestination[i])\r
{\r
case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
- storeEventPriMem(eventParam, eventStatus);\r
+ storeEventPriMem(eventParam, eventStatus); /** @req DEM010 */\r
break;\r
\r
case DEM_DTC_ORIGIN_SECONDARY_MEMORY:\r
case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
// Not yet supported\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
break;\r
default:\r
break;\r
* Description: Store the extended data pointed by "extendedData" to the "priMemExtDataBuffer",\r
* if non existent a new entry is created.\r
*/\r
-static void storeExtendedDataPriMem(const Dem_EventParameterType *eventParam, ExtDataRecType *extendedData)\r
+static void storeExtendedDataPriMem(const Dem_EventParameterType *eventParam, const ExtDataRecType *extendedData) /** @req DEM041 */\r
{\r
+ boolean eventIdFound = FALSE;\r
+ boolean eventIdFreePositionFound=FALSE;\r
uint16 i;\r
imask_t state = McuE_EnterCriticalSection();\r
\r
// Check if already stored\r
- for (i = 0; (priMemExtDataBuffer[i].eventId != eventParam->EventID) && (i<DEM_MAX_NUMBER_EXT_DATA_PRI_MEM); i++);\r
+ for (i = 0; (i<DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) && (!eventIdFound); i++){\r
+ eventIdFound = (priMemExtDataBuffer[i].eventId == eventParam->EventID);\r
+ }\r
\r
- if (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) {\r
+ if (eventIdFound) {\r
// Yes, overwrite existing\r
- memcpy(&priMemExtDataBuffer[i], extendedData, sizeof(ExtDataRecType));\r
+ memcpy(&priMemExtDataBuffer[i-1], extendedData, sizeof(ExtDataRecType));\r
}\r
else {\r
// No, lookup first free position\r
- for (i = 0; (priMemExtDataBuffer[i].eventId != DEM_EVENT_ID_NULL) && (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM); i++);\r
- if (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) {\r
- memcpy(&priMemExtDataBuffer[i], extendedData, sizeof(ExtDataRecType));\r
+ for (i = 0; (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) && (!eventIdFreePositionFound); i++){\r
+ eventIdFreePositionFound = (priMemExtDataBuffer[i].eventId == DEM_EVENT_ID_NULL);\r
+ }\r
+ if (eventIdFreePositionFound) {\r
+ memcpy(&priMemExtDataBuffer[i-1], extendedData, sizeof(ExtDataRecType));\r
}\r
else {\r
// Error: Pri mem extended data buffer full\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_PRI_MEM_ID, DEM_E_PRI_MEM_EXT_DATA_BUFF_FULL);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_STORE_EXT_DATA_PRI_MEM_ID, DEM_E_PRI_MEM_EXT_DATA_BUFF_FULL);\r
}\r
}\r
\r
McuE_ExitCriticalSection(state);\r
}\r
\r
-\r
/*\r
* Procedure: deleteExtendedDataPriMem\r
* Description: Delete the extended data of "eventParam->eventId" from "priMemExtDataBuffer".\r
*/\r
static void deleteExtendedDataPriMem(const Dem_EventParameterType *eventParam)\r
{\r
+ boolean eventIdFound = FALSE;\r
uint16 i;\r
imask_t state = McuE_EnterCriticalSection();\r
\r
// Check if already stored\r
- for (i = 0; (priMemExtDataBuffer[i].eventId != eventParam->EventID) && (i<DEM_MAX_NUMBER_EXT_DATA_PRI_MEM); i++);\r
+ for (i = 0;(i<DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) && (!eventIdFound); i++){\r
+ eventIdFound = (priMemExtDataBuffer[i].eventId == eventParam->EventID);\r
+ }\r
\r
- if (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) {\r
+ if (eventIdFound) {\r
// Yes, clear record\r
- memset(&priMemExtDataBuffer[i], 0, sizeof(ExtDataRecType));\r
+ memset(&priMemExtDataBuffer[i-1], 0, sizeof(ExtDataRecType));\r
}\r
\r
McuE_ExitCriticalSection(state);\r
}\r
\r
-\r
/*\r
* Procedure: storeExtendedDataEvtMem\r
* Description: Store the extended data in event memory according to\r
* "eventParam" destination option\r
*/\r
-static void storeExtendedDataEvtMem(const Dem_EventParameterType *eventParam, ExtDataRecType *extendedData)\r
+static void storeExtendedDataEvtMem(const Dem_EventParameterType *eventParam, const ExtDataRecType *extendedData)\r
{\r
uint16 i;\r
\r
- for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {\r
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != DEM_EVENT_DESTINATION_END_OF_LIST); i++) {\r
switch (eventParam->EventClass->EventDestination[i])\r
{\r
case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
// Not yet supported\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
break;\r
\r
default:\r
* Description: Returns TRUE if the requested extended data number was found among the configured records for the event.\r
* "extDataRecClassPtr" returns a pointer to the record class, "posInExtData" returns the position in stored extended data.\r
*/\r
-static boolean lookupExtendedDataRecNumParam(uint8 extendedDataNumber, const Dem_EventParameterType *eventParam, Dem_ExtendedDataRecordClassType const **extDataRecClassPtr, uint8 *posInExtData)\r
+static boolean lookupExtendedDataRecNumParam(uint8 extendedDataNumber, const Dem_EventParameterType *eventParam, Dem_ExtendedDataRecordClassType const **extDataRecClassPtr, uint16 *posInExtData)\r
{\r
boolean recNumFound = FALSE;\r
\r
if (eventParam->ExtendedDataClassRef != NULL) {\r
- Dem_ExtendedDataRecordClassType const* const* extDataRecClassRefList = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef;\r
uint16 byteCnt = 0;\r
uint16 i;\r
\r
// Request extended data and copy it to the buffer\r
- for (i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA) && (extDataRecClassRefList[i] != NULL) && !recNumFound; i++) {\r
- if (extDataRecClassRefList[i]->RecordNumber == extendedDataNumber) {\r
- *extDataRecClassPtr = extDataRecClassRefList[i];\r
+ for (i = 0; (i < DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA) && (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i] != NULL) && (!recNumFound); i++) {\r
+ if (eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->RecordNumber == extendedDataNumber) {\r
+ *extDataRecClassPtr = eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i];\r
*posInExtData = byteCnt;\r
recNumFound = TRUE;\r
}\r
- byteCnt += extDataRecClassRefList[i]->DataSize;\r
+ byteCnt += eventParam->ExtendedDataClassRef->ExtendedDataRecordClassRef[i]->DataSize;\r
}\r
}\r
\r
static boolean lookupExtendedDataPriMem(Dem_EventIdType eventId, ExtDataRecType **extData)\r
{\r
boolean eventIdFound = FALSE;\r
- uint16 i;\r
+ sint16 i;\r
\r
// Lookup corresponding extended data\r
- for (i = 0; (priMemExtDataBuffer[i].eventId != eventId) && (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM); i++);\r
+ for (i = 0; (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) && (!eventIdFound); i++) {\r
+ eventIdFound = (priMemExtDataBuffer[i].eventId == eventId);\r
+ }\r
\r
- if (i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM) {\r
+ if (eventIdFound) {\r
// Yes, return pointer\r
- *extData = &priMemExtDataBuffer[i];\r
- eventIdFound = TRUE;\r
+ *extData = &priMemExtDataBuffer[i-1];\r
}\r
\r
return eventIdFound;\r
}\r
\r
-\r
-static void storeFreezeFrameDataPriMem(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715} Symbol not referenced\r
+static void storeFreezeFrameDataPriMem(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame)\r
{\r
// TODO: Fill out\r
}\r
\r
\r
+// PC-Lint (715 etc): Remove errors until function is filled.\r
+//lint -e{715} Symbol not referenced\r
static void deleteFreezeFrameDataPriMem(const Dem_EventParameterType *eventParam)\r
{\r
// TODO: Fill out\r
* Description: Store the freeze frame data in event memory according to\r
* "eventParam" destination option\r
*/\r
-static void storeFreezeFrameDataEvtMem(const Dem_EventParameterType *eventParam, FreezeFrameRecType *freezeFrame)\r
+static void storeFreezeFrameDataEvtMem(const Dem_EventParameterType *eventParam, const FreezeFrameRecType *freezeFrame)\r
{\r
uint16 i;\r
\r
- for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {\r
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != DEM_EVENT_DESTINATION_END_OF_LIST); i++) {\r
switch (eventParam->EventClass->EventDestination[i])\r
{\r
case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
// Not yet supported\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GLOBAL_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
break;\r
+\r
default:\r
break;\r
}\r
if (eventParam != NULL) {\r
if (eventParam->EventClass->OperationCycleRef < DEM_OPERATION_CYCLE_ID_ENDMARK) {\r
if (operationCycleStateList[eventParam->EventClass->OperationCycleRef] == DEM_CYCLE_STATE_START) {\r
- if (!(disableDtcStorage.storageDisabled && checkDtcGroup(disableDtcStorage.dtcGroup, eventParam) && checkDtcKind(disableDtcStorage.dtcKind, eventParam))) {\r
+ if ((!((disableDtcStorage.storageDisabled) && (checkDtcGroup(disableDtcStorage.dtcGroup, eventParam)) && (checkDtcKind(disableDtcStorage.dtcKind, eventParam))))) {\r
updateEventStatusRec(eventParam, eventStatus, TRUE, &eventStatusLocal);\r
if (eventStatusLocal.errorStatusChanged) {\r
if (eventStatusLocal.eventStatusExtended & DEM_TEST_FAILED) {\r
- storeEventEvtMem(eventParam, &eventStatusLocal);\r
+ storeEventEvtMem(eventParam, &eventStatusLocal); /** @req DEM184 */\r
// Collect freeze frame data\r
getFreezeFrameData(eventParam, &freezeFrameLocal);\r
if (freezeFrameLocal.eventId != DEM_EVENT_ID_NULL) {\r
- storeFreezeFrameDataEvtMem(eventParam, &freezeFrameLocal);\r
+ storeFreezeFrameDataEvtMem(eventParam, &freezeFrameLocal); /** @req DEM190 */\r
}\r
\r
// Collect extended data\r
\r
lookupEventStatusRec(eventId, &eventStatusRecPtr);\r
if (eventStatusRecPtr != NULL) {\r
- eventStatusRecPtr->eventStatusExtended &= ~DEM_TEST_FAILED;\r
+ eventStatusRecPtr->eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_TEST_FAILED; /** @req DEM187 */\r
}\r
\r
McuE_ExitCriticalSection(state);\r
// Get recorded status\r
getEventStatusRec(eventId, &eventStatusLocal);\r
if (eventStatusLocal.eventId == eventId) {\r
- *eventStatusExtended = eventStatusLocal.eventStatusExtended;\r
+ *eventStatusExtended = eventStatusLocal.eventStatusExtended; /** @req DEM051 */\r
}\r
else {\r
// Event Id not found, no report received.\r
// Get recorded status\r
getEventStatusRec(eventId, &eventStatusLocal);\r
if (eventStatusLocal.eventId == eventId) {\r
- if (eventStatusLocal.eventStatusExtended & DEM_TEST_FAILED) {\r
+ if (eventStatusLocal.eventStatusExtended & DEM_TEST_FAILED) { /** @req DEM052 */\r
*eventFailed = TRUE;\r
}\r
else {\r
// Get recorded status\r
getEventStatusRec(eventId, &eventStatusLocal);\r
if (eventStatusLocal.eventId == eventId) {\r
- if ( !(eventStatusLocal.eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE)) {\r
+ if ( !(eventStatusLocal.eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE)) { /** @req DEM053 */\r
*eventTested = TRUE;\r
}\r
else {\r
case DEM_NO_PRE_DEBOUNCE:\r
if (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal != NULL) {\r
if (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal->CallbackGetFDCntFnc != NULL) {\r
- returnCode = eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal->CallbackGetFDCntFnc(counter);\r
+ returnCode = eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceAlgorithm.PreDebounceMonitorInternal->CallbackGetFDCntFnc(counter); /** @req DEM204.None */ /** @req DEM264 */ /** @req DEM265 */\r
}\r
}\r
break;\r
\r
lookupEventStatusRec(eventId, &eventStatusRec);\r
if (eventStatusRec != NULL) {\r
- *counter = eventStatusRec->faultDetectionCounter;\r
+ *counter = eventStatusRec->faultDetectionCounter; /** @req DEM204.Counter */\r
} else {\r
*counter = 0;\r
}\r
\r
case DEM_PRE_DEBOUNCE_FREQUENCY_BASED:\r
case DEM_PRE_DEBOUNCE_TIME_BASED:\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
break;\r
\r
default:\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_PARAM_DATA);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_PARAM_DATA);\r
break;\r
}\r
}\r
* event connected to this cycle id.\r
* Returns E_OK if operation was successful else E_NOT_OK.\r
*/\r
-static Std_ReturnType setOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState)\r
+static Std_ReturnType setOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState) /** @req DEM338 */\r
{\r
uint16 i;\r
Std_ReturnType returnCode = E_OK;\r
// Lookup event ID\r
for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {\r
if ((eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (eventStatusBuffer[i].eventParamRef->EventClass->OperationCycleRef == operationCycleId)) {\r
- eventStatusBuffer[i].eventStatusExtended &= ~DEM_TEST_FAILED_THIS_OPERATION_CYCLE;\r
+ eventStatusBuffer[i].eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_TEST_FAILED_THIS_OPERATION_CYCLE;\r
eventStatusBuffer[i].eventStatusExtended |= DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE;\r
}\r
}\r
// Lookup event ID\r
for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {\r
if ((eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) && (eventStatusBuffer[i].eventParamRef->EventClass->OperationCycleRef == operationCycleId)) {\r
- if (!(eventStatusBuffer[i].eventStatusExtended & DEM_TEST_FAILED_THIS_OPERATION_CYCLE) && !(eventStatusBuffer[i].eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE)) {\r
- eventStatusBuffer[i].eventStatusExtended &= ~DEM_PENDING_DTC; // Clear pendingDTC bit\r
+ if ((!(eventStatusBuffer[i].eventStatusExtended & DEM_TEST_FAILED_THIS_OPERATION_CYCLE)) && (!(eventStatusBuffer[i].eventStatusExtended & DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE))) {\r
+ eventStatusBuffer[i].eventStatusExtended &= (Dem_EventStatusExtendedType)~DEM_PENDING_DTC; // Clear pendingDTC bit /** @req DEM379.PendingClear\r
}\r
}\r
}\r
break;\r
default:\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA);\r
returnCode = E_NOT_OK;\r
break;\r
}\r
}\r
else {\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_PARAM_DATA);\r
returnCode = E_NOT_OK;\r
}\r
\r
* Procedure: Dem_GetVersionInfo\r
* Reentrant: Yes\r
*/\r
-#if (DEM_VERSION_INFO_API == STD_ON)\r
-void Dem_GetVersionInfo(Std_VersionInfoType *versionInfo) {\r
- memcpy(versionInfo, &_Dem_VersionInfo, sizeof(Std_VersionInfoType));\r
-}\r
-#endif /* DEM_VERSION_INFO_API */\r
+// Defined in Dem.h\r
\r
\r
/***********************************************\r
*/\r
void Dem_PreInit(void)\r
{\r
- int i, j;\r
+ /** @req DEM180 */\r
+ uint16 i, j;\r
\r
- if (DEM_Config.ConfigSet == NULL) {\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_PREINIT_ID, DEM_E_CONFIG_PTR_INVALID);\r
-#endif\r
- return;\r
- } else {\r
- configSet = DEM_Config.ConfigSet;\r
- }\r
+ VALIDATE_NO_RV(DEM_Config.ConfigSet != NULL, DEM_PREINIT_ID, DEM_E_CONFIG_PTR_INVALID);\r
+\r
+ configSet = DEM_Config.ConfigSet;\r
\r
// Initializion of operation cycle states.\r
for (i = 0; i < DEM_OPERATION_CYCLE_ID_ENDMARK; i++) {\r
preInitFreezeFrameBuffer[i].eventId = DEM_EVENT_ID_NULL;\r
preInitFreezeFrameBuffer[i].occurrence = 0;\r
preInitFreezeFrameBuffer[i].dataSize = 0;\r
- for (j = 0; j < DEM_MAX_SIZE_FF_DATA;j++)\r
+ for (j = 0; j < DEM_MAX_SIZE_FF_DATA;j++){\r
preInitFreezeFrameBuffer[i].data[j] = 0;\r
+ }\r
}\r
\r
for (i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRE_INIT; i++) {\r
preInitExtDataBuffer[i].checksum = 0;\r
preInitExtDataBuffer[i].eventId = DEM_EVENT_ID_NULL;\r
preInitExtDataBuffer[i].dataSize = 0;\r
- for (j = 0; j < DEM_MAX_SIZE_EXT_DATA;j++)\r
+ for (j = 0; j < DEM_MAX_SIZE_EXT_DATA;j++){\r
preInitExtDataBuffer[i].data[j] = 0;\r
+ }\r
}\r
\r
disableDtcStorage.storageDisabled = FALSE;\r
\r
- setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_START);\r
+ (void)setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_START); /** @req DEM047 */\r
\r
demState = DEM_PREINITIALIZED;\r
}\r
// Validate event records stored in primary memory\r
for (i = 0; i < DEM_MAX_NUMBER_EVENT_PRI_MEM; i++) {\r
cSum = calcChecksum(&priMemEventBuffer[i], sizeof(EventRecType)-sizeof(ChecksumType));\r
- if ((cSum != priMemEventBuffer[i].checksum) || priMemEventBuffer[i].eventId == DEM_EVENT_ID_NULL) {\r
+ if ((cSum != priMemEventBuffer[i].checksum) || (priMemEventBuffer[i].eventId == DEM_EVENT_ID_NULL)) {\r
// Unlegal record, clear the record\r
memset(&priMemEventBuffer[i], 0, sizeof(EventRecType));\r
}\r
// Validate extended data records stored in primary memory\r
for (i = 0; i < DEM_MAX_NUMBER_EXT_DATA_PRI_MEM; i++) {\r
cSum = calcChecksum(&priMemExtDataBuffer[i], sizeof(ExtDataRecType)-sizeof(ChecksumType));\r
- if ((cSum != priMemExtDataBuffer[i].checksum) || priMemExtDataBuffer[i].eventId == DEM_EVENT_ID_NULL) {\r
+ if ((cSum != priMemExtDataBuffer[i].checksum) || (priMemExtDataBuffer[i].eventId == DEM_EVENT_ID_NULL)) {\r
// Unlegal record, clear the record\r
memset(&priMemExtDataBuffer[i], 0, sizeof(ExtDataRecType));\r
}\r
*/\r
void Dem_Shutdown(void)\r
{\r
- setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_END);\r
+ (void)setOperationCycleState(DEM_ACTIVE, DEM_CYCLE_STATE_END); /** @req DEM047 */\r
\r
- demState = DEM_UNINITIALIZED;\r
+ demState = DEM_UNINITIALIZED; /** @req DEM368 */\r
}\r
\r
\r
*/\r
void Dem_MainFunction(void)\r
{\r
+ /** @req DEM125 */\r
\r
}\r
\r
* Procedure: Dem_SetEventStatus\r
* Reentrant: Yes\r
*/\r
-Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, Dem_EventStatusType eventStatus)\r
+Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, Dem_EventStatusType eventStatus) /** @req DEM330 */\r
{\r
Std_ReturnType returnCode = E_OK;\r
\r
}\r
else\r
{\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_SETEVENTSTATUS_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETEVENTSTATUS_ID, DEM_E_UNINIT);\r
returnCode = E_NOT_OK;\r
}\r
\r
* Procedure: Dem_ResetEventStatus\r
* Reentrant: Yes\r
*/\r
-Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId)\r
+Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId) /** @req DEM331 */\r
{\r
Std_ReturnType returnCode = E_OK;\r
\r
if (demState == DEM_INITIALIZED) // No action is taken if the module is not started\r
{\r
- resetEventStatus(eventId);\r
+ resetEventStatus(eventId); /** @req DEM186 */\r
}\r
else\r
{\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_RESETEVENTSTATUS_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_RESETEVENTSTATUS_ID, DEM_E_UNINIT);\r
returnCode = E_NOT_OK;\r
}\r
\r
* Procedure: Dem_GetEventStatus\r
* Reentrant: Yes\r
*/\r
-Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended)\r
+Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended) /** @req DEM332 */\r
{\r
Std_ReturnType returnCode = E_OK;\r
\r
}\r
else\r
{\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GETEVENTSTATUS_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEVENTSTATUS_ID, DEM_E_UNINIT);\r
returnCode = E_NOT_OK;\r
}\r
\r
* Procedure: Dem_GetEventFailed\r
* Reentrant: Yes\r
*/\r
-Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed)\r
+Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed) /** @req DEM333 */\r
{\r
Std_ReturnType returnCode = E_OK;\r
\r
}\r
else\r
{\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GETEVENTFAILED_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEVENTFAILED_ID, DEM_E_UNINIT);\r
returnCode = E_NOT_OK;\r
}\r
\r
}\r
else\r
{\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GETEVENTTESTED_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEVENTTESTED_ID, DEM_E_UNINIT);\r
returnCode = E_NOT_OK;\r
}\r
\r
}\r
else\r
{\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETFAULTDETECTIONCOUNTER_ID, DEM_E_UNINIT);\r
returnCode = E_NOT_OK;\r
}\r
\r
}\r
else\r
{\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETOPERATIONCYCLESTATE_ID, DEM_E_UNINIT);\r
returnCode = E_NOT_OK;\r
}\r
\r
Std_ReturnType returnCode = E_NO_DTC_AVAILABLE;\r
const Dem_EventParameterType *eventParam;\r
\r
- lookupEventIdParameter(eventId, &eventParam);\r
+ if (demState == DEM_INITIALIZED) // No action is taken if the module is not started\r
+ {\r
+ lookupEventIdParameter(eventId, &eventParam);\r
\r
- if (eventParam != NULL) {\r
- if (checkDtcKind(dtcKind, eventParam)) {\r
- if (eventParam->DTCClassRef != NULL) {\r
- *dtcOfEvent = eventParam->DTCClassRef->DTC;\r
- returnCode = E_OK;\r
+ if (eventParam != NULL) {\r
+ if (checkDtcKind(dtcKind, eventParam)) {\r
+ if (eventParam->DTCClassRef != NULL) {\r
+ *dtcOfEvent = eventParam->DTCClassRef->DTC; /** @req DEM269 */\r
+ returnCode = E_OK;\r
+ }\r
}\r
}\r
+ else {\r
+ // Event Id not found\r
+ returnCode = E_NOT_OK;\r
+ }\r
}\r
- else {\r
- // Event Id not found\r
+ else\r
+ {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETDTCOFEVENT_ID, DEM_UNINITIALIZED);\r
returnCode = E_NOT_OK;\r
}\r
\r
* Procedure: Dem_ReportErrorStatus\r
* Reentrant: Yes\r
*/\r
-void Dem_ReportErrorStatus( Dem_EventIdType eventId, Dem_EventStatusType eventStatus )\r
+void Dem_ReportErrorStatus( Dem_EventIdType eventId, Dem_EventStatusType eventStatus ) /** @req DEM107 */\r
{\r
\r
switch (demState) {\r
case DEM_PREINITIALIZED:\r
// Update status and check if is to be stored\r
if ((eventStatus == DEM_EVENT_STATUS_PASSED) || (eventStatus == DEM_EVENT_STATUS_FAILED)) {\r
- handlePreInitEvent(eventId, eventStatus);\r
+ handlePreInitEvent(eventId, eventStatus); /** @req DEM168 */\r
}\r
break;\r
\r
case DEM_INITIALIZED:\r
- (void)handleEvent(eventId, eventStatus);\r
+ (void)handleEvent(eventId, eventStatus); /** @req DEM167 */\r
break;\r
\r
case DEM_UNINITIALIZED:\r
default:\r
// Uninitialized can not do anything\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_REPORTERRORSTATUS_ID, DEM_E_UNINIT);\r
-#endif\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_REPORTERRORSTATUS_ID, DEM_E_UNINIT);\r
+\r
break;\r
\r
} // switch (demState)\r
* Procedure: Dem_GetDTCStatusAvailabilityMask\r
* Reentrant: No\r
*/\r
-Std_ReturnType Dem_GetDTCStatusAvailabilityMask(uint8 *dtcStatusMask)\r
+Std_ReturnType Dem_GetDTCStatusAvailabilityMask(uint8 *dtcStatusMask) /** @req DEM014 */\r
{\r
*dtcStatusMask = DEM_DTC_STATUS_AVAILABILITY_MASK; // User configuration mask\r
- *dtcStatusMask &= DEM_TEST_FAILED // Mask with supported bits\r
+ *dtcStatusMask &= DEM_TEST_FAILED // Mask with supported bits /** @req DEM060 */\r
| DEM_TEST_FAILED_THIS_OPERATION_CYCLE\r
| DEM_PENDING_DTC\r
// | DEM_CONFIRMED_DTC TODO: Add support for this bit\r
Dem_DTCOriginType dtcOrigin,\r
Dem_FilterWithSeverityType filterWithSeverity,\r
Dem_DTCSeverityType dtcSeverityMask,\r
- Dem_FilterForFDCType filterForFaultDetectionCounter) {\r
-\r
- Dem_ReturnSetDTCFilterType returnCode = DEM_WRONG_FILTER;\r
+ Dem_FilterForFDCType filterForFaultDetectionCounter)\r
+{\r
+ Dem_ReturnSetDTCFilterType returnCode = DEM_FILTER_ACCEPTED;\r
\r
- // Check dtcKind parameter\r
- if ((dtcKind == DEM_DTC_KIND_ALL_DTCS) || (dtcKind == DEM_DTC_KIND_EMISSION_REL_DTCS)) {\r
+ if (demState == DEM_INITIALIZED) {\r
+ // Check dtcKind parameter\r
+ VALIDATE_RV((dtcKind == DEM_DTC_KIND_ALL_DTCS) || (dtcKind == DEM_DTC_KIND_EMISSION_REL_DTCS), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER);\r
\r
// Check dtcOrigin parameter\r
- if ((dtcOrigin == DEM_DTC_ORIGIN_SECONDARY_MEMORY) || (dtcOrigin == DEM_DTC_ORIGIN_PRIMARY_MEMORY)\r
- || (dtcOrigin == DEM_DTC_ORIGIN_PERMANENT_MEMORY) || (dtcOrigin == DEM_DTC_ORIGIN_MIRROR_MEMORY)) {\r
-\r
- // Check filterWithSeverity and dtcSeverityMask parameter\r
- if ((filterWithSeverity == DEM_FILTER_WITH_SEVERITY_NO)\r
- || ((filterWithSeverity == DEM_FILTER_WITH_SEVERITY_YES) && !(dtcSeverityMask & ~(DEM_SEVERITY_MAINTENANCE_ONLY | DEM_SEVERITY_CHECK_AT_NEXT_FALT | DEM_SEVERITY_CHECK_IMMEDIATELY)))){\r
-\r
- // Check filterForFaultDetectionCounter parameter\r
- if ((filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_YES) || (filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_NO)) {\r
- // Yes all parameters correct, set the new filters.\r
- dtcFilter.dtcStatusMask = dtcStatusMask;\r
- dtcFilter.dtcKind = dtcKind;\r
- dtcFilter.dtcOrigin = dtcOrigin;\r
- dtcFilter.filterWithSeverity = filterWithSeverity;\r
- dtcFilter.dtcSeverityMask = dtcSeverityMask;\r
- dtcFilter.filterForFaultDetectionCounter = filterForFaultDetectionCounter;\r
- dtcFilter.faultIndex = DEM_MAX_NUMBER_EVENT;\r
- returnCode = DEM_FILTER_ACCEPTED;\r
- }\r
- }\r
- }\r
+ VALIDATE_RV((dtcOrigin == DEM_DTC_ORIGIN_SECONDARY_MEMORY) || (dtcOrigin == DEM_DTC_ORIGIN_PRIMARY_MEMORY)\r
+ || (dtcOrigin == DEM_DTC_ORIGIN_PERMANENT_MEMORY) || (dtcOrigin == DEM_DTC_ORIGIN_MIRROR_MEMORY), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER);\r
+\r
+ // Check filterWithSeverity and dtcSeverityMask parameter\r
+ VALIDATE_RV(((filterWithSeverity == DEM_FILTER_WITH_SEVERITY_NO)\r
+ || ((filterWithSeverity == DEM_FILTER_WITH_SEVERITY_YES)\r
+ && (!(dtcSeverityMask & (Dem_DTCSeverityType)~(DEM_SEVERITY_MAINTENANCE_ONLY | DEM_SEVERITY_CHECK_AT_NEXT_FALT | DEM_SEVERITY_CHECK_IMMEDIATELY))))), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER);\r
+\r
+ // Check filterForFaultDetectionCounter parameter\r
+ VALIDATE_RV((filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_YES) || (filterForFaultDetectionCounter == DEM_FILTER_FOR_FDC_NO), DEM_SETDTCFILTER_ID, DEM_E_PARAM_DATA, DEM_WRONG_FILTER);\r
+\r
+ // Yes all parameters correct, set the new filters. /** @req DEM057 */\r
+ dtcFilter.dtcStatusMask = dtcStatusMask;\r
+ dtcFilter.dtcKind = dtcKind;\r
+ dtcFilter.dtcOrigin = dtcOrigin;\r
+ dtcFilter.filterWithSeverity = filterWithSeverity;\r
+ dtcFilter.dtcSeverityMask = dtcSeverityMask;\r
+ dtcFilter.filterForFaultDetectionCounter = filterForFaultDetectionCounter;\r
+ dtcFilter.faultIndex = DEM_MAX_NUMBER_EVENT;\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_SETDTCFILTER_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_WRONG_FILTER;\r
}\r
\r
return returnCode;\r
Dem_ReturnGetStatusOfDTCType returnCode = DEM_STATUS_FAILED;\r
EventStatusRecType *eventRec;\r
\r
- if (lookupDtcEvent(dtc, &eventRec)) {\r
- if (checkDtcKind(dtcKind, eventRec->eventParamRef)) {\r
- if (checkDtcOrigin(dtcOrigin,eventRec->eventParamRef)) {\r
- *status = eventRec->eventStatusExtended;\r
- returnCode = DEM_STATUS_OK;\r
+ if (demState == DEM_INITIALIZED) {\r
+ if (lookupDtcEvent(dtc, &eventRec)) {\r
+ if (checkDtcKind(dtcKind, eventRec->eventParamRef)) {\r
+ if (checkDtcOrigin(dtcOrigin,eventRec->eventParamRef)) {\r
+ *status = eventRec->eventStatusExtended; /** @req DEM059 */\r
+ returnCode = DEM_STATUS_OK;\r
+ }\r
+ else {\r
+ returnCode = DEM_STATUS_WRONG_DTCORIGIN; /** @req DEM171 */\r
+ }\r
}\r
else {\r
- returnCode = DEM_STATUS_WRONG_DTCORIGIN;\r
+ returnCode = DEM_STATUS_WRONG_DTCKIND;\r
}\r
}\r
else {\r
- returnCode = DEM_STATUS_WRONG_DTCKIND;\r
+ returnCode = DEM_STATUS_WRONG_DTC; /** @req DEM172 */\r
}\r
- }\r
- else {\r
- returnCode = DEM_STATUS_WRONG_DTC;\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETSTATUSOFDTC_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_STATUS_FAILED;\r
}\r
\r
return returnCode;\r
Dem_ReturnGetNumberOfFilteredDTCType Dem_GetNumberOfFilteredDtc(uint16 *numberOfFilteredDTC) {\r
uint16 i;\r
uint16 numberOfFaults = 0;\r
+ Dem_ReturnGetNumberOfFilteredDTCType returnCode = DEM_NUMBER_OK;\r
\r
- //Dem_DisableEventStatusUpdate();\r
+ if (demState == DEM_INITIALIZED) {\r
+ //Dem_DisableEventStatusUpdate();\r
\r
- for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {\r
- if (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) {\r
- if (matchEventWithDtcFilter(&eventStatusBuffer[i])) {\r
- if (eventStatusBuffer[i].eventParamRef->DTCClassRef != NULL) {\r
- numberOfFaults++;\r
+ for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {\r
+ if (eventStatusBuffer[i].eventId != DEM_EVENT_ID_NULL) {\r
+ if (matchEventWithDtcFilter(&eventStatusBuffer[i])) {\r
+ if (eventStatusBuffer[i].eventParamRef->DTCClassRef != NULL) {\r
+ numberOfFaults++;\r
+ }\r
}\r
}\r
}\r
- }\r
\r
- //Dem_EnableEventStatusUpdate();\r
+ //Dem_EnableEventStatusUpdate();\r
\r
- *numberOfFilteredDTC = numberOfFaults;\r
+ *numberOfFilteredDTC = numberOfFaults; /** @req DEM061 */\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETNUMBEROFFILTEREDDTC_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_NUMBER_FAILED;\r
+ }\r
\r
- return DEM_NUMBER_OK;\r
+ return returnCode;\r
}\r
\r
\r
Dem_ReturnGetNextFilteredDTCType returnCode = DEM_FILTERED_OK;\r
boolean dtcFound = FALSE;\r
\r
- // TODO: This job should be done in an more advanced way according to Dem288\r
- while (!dtcFound && (dtcFilter.faultIndex != 0)) {\r
- dtcFilter.faultIndex--;\r
- if (eventStatusBuffer[dtcFilter.faultIndex].eventId != DEM_EVENT_ID_NULL) {\r
- if (matchEventWithDtcFilter(&eventStatusBuffer[dtcFilter.faultIndex])) {\r
- if (eventStatusBuffer[dtcFilter.faultIndex].eventParamRef->DTCClassRef != NULL) {\r
- *dtc = eventStatusBuffer[dtcFilter.faultIndex].eventParamRef->DTCClassRef->DTC;\r
- *dtcStatus = eventStatusBuffer[dtcFilter.faultIndex].eventStatusExtended;\r
- dtcFound = TRUE;\r
+ if (demState == DEM_INITIALIZED) {\r
+ // TODO: This job should be done in an more advanced way according to Dem217\r
+ while ((!dtcFound) && (dtcFilter.faultIndex != 0)) {\r
+ dtcFilter.faultIndex--;\r
+ if (eventStatusBuffer[dtcFilter.faultIndex].eventId != DEM_EVENT_ID_NULL) {\r
+ if (matchEventWithDtcFilter(&eventStatusBuffer[dtcFilter.faultIndex])) {\r
+ if (eventStatusBuffer[dtcFilter.faultIndex].eventParamRef->DTCClassRef != NULL) {\r
+ *dtc = eventStatusBuffer[dtcFilter.faultIndex].eventParamRef->DTCClassRef->DTC; /** @req DEM216 */\r
+ *dtcStatus = eventStatusBuffer[dtcFilter.faultIndex].eventStatusExtended;\r
+ dtcFound = TRUE;\r
+ }\r
}\r
}\r
}\r
- }\r
\r
- if (!dtcFound) {\r
- dtcFilter.faultIndex = DEM_MAX_NUMBER_EVENT;\r
+ if (!dtcFound) {\r
+ dtcFilter.faultIndex = DEM_MAX_NUMBER_EVENT;\r
+ returnCode = DEM_FILTERED_NO_MATCHING_DTC;\r
+ }\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETNEXTFILTEREDDTC_ID, DEM_E_UNINIT);\r
returnCode = DEM_FILTERED_NO_MATCHING_DTC;\r
}\r
\r
*/\r
Dem_ReturnTypeOfDtcSupportedType Dem_GetTranslationType(void)\r
{\r
- return DEM_TYPE_OF_DTC_SUPPORTED;\r
+ return DEM_TYPE_OF_DTC_SUPPORTED; /** @req DEM231 */\r
}\r
\r
\r
* Procedure: Dem_ClearDTC\r
* Reentrant: No\r
*/\r
-Dem_ReturnClearDTCType Dem_ClearDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin)\r
+Dem_ReturnClearDTCType Dem_ClearDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin) /** @req DEM009 */\r
{\r
Dem_ReturnClearDTCType returnCode = DEM_CLEAR_OK;\r
Dem_EventIdType eventId;\r
const Dem_EventParameterType *eventParam;\r
uint16 i, j;\r
\r
- // Loop through the event buffer\r
- for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {\r
- eventId = eventStatusBuffer[i].eventId;\r
- if (eventId != DEM_EVENT_ID_NULL) {\r
- eventParam = eventStatusBuffer[i].eventParamRef;\r
- if (eventParam != NULL) {\r
- if (DEM_CLEAR_ALL_EVENTS | (eventParam->DTCClassRef != NULL)) {\r
- if (checkDtcKind(dtcKind, eventParam)) {\r
- if (checkDtcGroup(dtc, eventParam)) {\r
- for (j = 0; (j < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[j] != dtcOrigin); j++);\r
- if (j < DEM_MAX_NR_OF_EVENT_DESTINATION) {\r
- // Yes! All conditions met.\r
- switch (dtcOrigin)\r
- {\r
- case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
- deleteEventPriMem(eventParam);\r
- deleteFreezeFrameDataPriMem(eventParam);\r
- deleteExtendedDataPriMem(eventParam);\r
- deleteEventStatusRec(eventParam); // TODO: Shall this be done or just resetting the status?\r
- break;\r
-\r
- case DEM_DTC_ORIGIN_SECONDARY_MEMORY:\r
- case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
- case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
- // Not yet supported\r
- returnCode = DEM_CLEAR_WRONG_DTCORIGIN;\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_CLEARDTC_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
-#endif\r
- break;\r
- default:\r
- returnCode = DEM_CLEAR_WRONG_DTCORIGIN;\r
- break;\r
+ if (demState == DEM_INITIALIZED) {\r
+ // Loop through the event buffer\r
+ for (i = 0; i < DEM_MAX_NUMBER_EVENT; i++) {\r
+ eventId = eventStatusBuffer[i].eventId;\r
+ if (eventId != DEM_EVENT_ID_NULL) {\r
+ eventParam = eventStatusBuffer[i].eventParamRef;\r
+ if (eventParam != NULL) {\r
+ //lint --e(506) PC-Lint exception Misra 13.7, 14.1 Allow configuration variables in boolean expression\r
+ //lint --e(774) PC-Lint exception Related to MISRA 13.7\r
+ if ((DEM_CLEAR_ALL_EVENTS == STD_ON) || (eventParam->DTCClassRef != NULL)) {\r
+ if (checkDtcKind(dtcKind, eventParam)) {\r
+ if (checkDtcGroup(dtc, eventParam)) {\r
+ boolean dtcOriginFound = FALSE;\r
+ for (j = 0; (j < DEM_MAX_NR_OF_EVENT_DESTINATION) && (!dtcOriginFound) ; j++){\r
+ dtcOriginFound =(eventParam->EventClass->EventDestination[j] == dtcOrigin);\r
+ }\r
+ //if (j-1 < DEM_MAX_NR_OF_EVENT_DESTINATION) {\r
+ if (dtcOriginFound) {\r
+ // Yes! All conditions met.\r
+ switch (dtcOrigin)\r
+ {\r
+ case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
+ /** @req DEM077 */\r
+ deleteEventPriMem(eventParam);\r
+ deleteFreezeFrameDataPriMem(eventParam);\r
+ deleteExtendedDataPriMem(eventParam);\r
+ deleteEventStatusRec(eventParam); // TODO: Shall this be done or just resetting the status?\r
+ break;\r
+\r
+ case DEM_DTC_ORIGIN_SECONDARY_MEMORY:\r
+ case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
+ case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
+ // Not yet supported\r
+ returnCode = DEM_CLEAR_WRONG_DTCORIGIN;\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_CLEARDTC_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
+ break;\r
+ default:\r
+ returnCode = DEM_CLEAR_WRONG_DTCORIGIN;\r
+ break;\r
+ }\r
}\r
}\r
}\r
}\r
}\r
- }\r
- else {\r
- // Fatal error, no event parameters found for the stored event!\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_CLEARDTC_ID, DEM_E_UNEXPECTED_EXECUTION);\r
-#endif\r
+ else {\r
+ // Fatal error, no event parameters found for the stored event!\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_CLEARDTC_ID, DEM_E_UNEXPECTED_EXECUTION);\r
+ }\r
}\r
}\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_CLEARDTC_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_CLEAR_FAILED;\r
}\r
\r
return returnCode;\r
* Procedure: Dem_DisableDTCStorage\r
* Reentrant: No\r
*/\r
-Dem_ReturnControlDTCStorageType Dem_DisableDTCStorage(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind)\r
+Dem_ReturnControlDTCStorageType Dem_DisableDTCStorage(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind) /** @req DEM035 */\r
{\r
- Dem_ReturnControlDTCStorageType returnCode = DEM_CONTROL_DTC_STORAGE_N_OK;\r
-\r
- // Check dtcGroup parameter\r
- if (dtcGroup == DEM_DTC_GROUP_ALL_DTCS) {\r
- // Check dtcKind parameter\r
- if ((dtcKind == DEM_DTC_KIND_ALL_DTCS) || (dtcKind == DEM_DTC_KIND_EMISSION_REL_DTCS)) {\r
- disableDtcStorage.dtcGroup = dtcGroup;\r
- disableDtcStorage.dtcKind = dtcKind;\r
- disableDtcStorage.storageDisabled = TRUE;\r
-\r
- returnCode = DEM_CONTROL_DTC_STORAGE_OK;\r
+ Dem_ReturnControlDTCStorageType returnCode = DEM_CONTROL_DTC_STORAGE_OK;\r
+\r
+ if (demState == DEM_INITIALIZED) {\r
+ // Check dtcGroup parameter\r
+ if (dtcGroup == DEM_DTC_GROUP_ALL_DTCS) {\r
+ // Check dtcKind parameter\r
+ if ((dtcKind == DEM_DTC_KIND_ALL_DTCS) || (dtcKind == DEM_DTC_KIND_EMISSION_REL_DTCS)) {\r
+ /** @req DEM079 */\r
+ disableDtcStorage.dtcGroup = dtcGroup;\r
+ disableDtcStorage.dtcKind = dtcKind;\r
+ disableDtcStorage.storageDisabled = TRUE;\r
+ } else {\r
+ returnCode = DEM_CONTROL_DTC_STORAGE_N_OK;\r
+ }\r
+ } else {\r
+ returnCode = DEM_CONTROL_DTC_WRONG_DTCGROUP;\r
}\r
- }\r
- else {\r
- returnCode = DEM_CONTROL_DTC_WRONG_DTCGROUP;\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_DISABLEDTCSTORAGE_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_CONTROL_DTC_STORAGE_N_OK;\r
}\r
\r
return returnCode;\r
*/\r
Dem_ReturnControlDTCStorageType Dem_EnableDTCStorage(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind)\r
{\r
- // TODO: Behavior is not defined if group or kind do not match active settings, therefore the filter is just switched off.\r
- disableDtcStorage.storageDisabled = FALSE;\r
+ Dem_ReturnControlDTCStorageType returnCode = DEM_CONTROL_DTC_STORAGE_OK;\r
+\r
+ if (demState == DEM_INITIALIZED) {\r
+ // TODO: Behavior is not defined if group or kind do not match active settings, therefore the filter is just switched off.\r
+ (void)dtcGroup; (void)dtcKind; // Just to make get rid of PC-Lint warnings\r
+ disableDtcStorage.storageDisabled = FALSE; /** @req DEM080 */\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_ENABLEDTCSTORAGE_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_CONTROL_DTC_STORAGE_N_OK;\r
+ }\r
\r
- return DEM_CONTROL_DTC_STORAGE_OK;\r
+ return returnCode;\r
}\r
\r
/*\r
* Procedure: Dem_GetExtendedDataRecordByDTC\r
* Reentrant: No\r
*/\r
-Dem_ReturnGetExtendedDataRecordByDTCType Dem_GetExtendedDataRecordByDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint8 *destBuffer, uint8 *bufSize)\r
+Dem_ReturnGetExtendedDataRecordByDTCType Dem_GetExtendedDataRecordByDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint8 *destBuffer, uint16 *bufSize)\r
{\r
Dem_ReturnGetExtendedDataRecordByDTCType returnCode = DEM_RECORD_WRONG_DTC;\r
EventStatusRecType *eventRec;\r
Dem_ExtendedDataRecordClassType const *extendedDataRecordClass = NULL;\r
ExtDataRecType *extData;\r
- uint8 posInExtData = 0;\r
-\r
- if (lookupDtcEvent(dtc, &eventRec)) {\r
- if (checkDtcKind(dtcKind, eventRec->eventParamRef)) {\r
- if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)) {\r
- if (lookupExtendedDataRecNumParam(extendedDataNumber, eventRec->eventParamRef, &extendedDataRecordClass, &posInExtData)) {\r
- if (*bufSize >= extendedDataRecordClass->DataSize) {\r
- switch (dtcOrigin)\r
- {\r
- case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
- if (lookupExtendedDataPriMem(eventRec->eventId, &extData)) {\r
- // Yes all conditions met, copy the extended data record to destination buffer.\r
- memcpy(destBuffer, &extData->data[posInExtData], extendedDataRecordClass->DataSize);\r
- *bufSize = extendedDataRecordClass->DataSize;\r
- returnCode = DEM_RECORD_OK;\r
- }\r
- else {\r
- // The record number is legal but no record was found for the DTC\r
- *bufSize = 0;\r
- returnCode = DEM_RECORD_OK;\r
+ uint16 posInExtData = 0;\r
+\r
+ if (demState == DEM_INITIALIZED) {\r
+ if (lookupDtcEvent(dtc, &eventRec)) {\r
+ if (checkDtcKind(dtcKind, eventRec->eventParamRef)) {\r
+ if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)) {\r
+ if (lookupExtendedDataRecNumParam(extendedDataNumber, eventRec->eventParamRef, &extendedDataRecordClass, &posInExtData)) {\r
+ if (*bufSize >= extendedDataRecordClass->DataSize) {\r
+ switch (dtcOrigin)\r
+ {\r
+ case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
+ if (lookupExtendedDataPriMem(eventRec->eventId, &extData)) {\r
+ // Yes all conditions met, copy the extended data record to destination buffer.\r
+ memcpy(destBuffer, &extData->data[posInExtData], extendedDataRecordClass->DataSize); /** @req DEM075 */\r
+ *bufSize = extendedDataRecordClass->DataSize;\r
+ returnCode = DEM_RECORD_OK;\r
+ }\r
+ else {\r
+ // The record number is legal but no record was found for the DTC\r
+ *bufSize = 0;\r
+ returnCode = DEM_RECORD_OK;\r
+ }\r
+ break;\r
+\r
+ case DEM_DTC_ORIGIN_SECONDARY_MEMORY:\r
+ case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
+ case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
+ // Not yet supported\r
+ returnCode = DEM_RECORD_WRONG_DTCORIGIN;\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
+ break;\r
+ default:\r
+ returnCode = DEM_RECORD_WRONG_DTCORIGIN;\r
+ break;\r
}\r
- break;\r
-\r
- case DEM_DTC_ORIGIN_SECONDARY_MEMORY:\r
- case DEM_DTC_ORIGIN_PERMANENT_MEMORY:\r
- case DEM_DTC_ORIGIN_MIRROR_MEMORY:\r
- // Not yet supported\r
- returnCode = DEM_RECORD_WRONG_DTCORIGIN;\r
-#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
- Det_ReportError(MODULE_ID_DEM, 0, DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
-#endif\r
- break;\r
- default:\r
- returnCode = DEM_RECORD_WRONG_DTCORIGIN;\r
- break;\r
+ }\r
+ else {\r
+ returnCode = DEM_RECORD_BUFFERSIZE;\r
}\r
}\r
else {\r
- returnCode = DEM_RECORD_BUFFERSIZE;\r
+ returnCode = DEM_RECORD_NUMBER;\r
}\r
}\r
else {\r
- returnCode = DEM_RECORD_NUMBER;\r
+ returnCode = DEM_RECORD_WRONG_DTCORIGIN;\r
}\r
}\r
else {\r
- returnCode = DEM_RECORD_WRONG_DTCORIGIN;\r
+ returnCode = DEM_RECORD_DTCKIND;\r
}\r
}\r
- else {\r
- returnCode = DEM_RECORD_DTCKIND;\r
- }\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETEXTENDEDDATARECORDBYDTC_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_RECORD_WRONG_DTC;\r
}\r
\r
return returnCode;\r
Dem_ReturnGetExtendedDataRecordByDTCType returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTC;\r
EventStatusRecType *eventRec;\r
Dem_ExtendedDataRecordClassType const *extendedDataRecordClass = NULL;\r
- uint8 posInExtData;\r
-\r
- if (lookupDtcEvent(dtc, &eventRec)) {\r
- if (checkDtcKind(dtcKind, eventRec->eventParamRef)) {\r
- if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)) {\r
- if (lookupExtendedDataRecNumParam(extendedDataNumber, eventRec->eventParamRef, &extendedDataRecordClass, &posInExtData)) {\r
- *sizeOfExtendedDataRecord = extendedDataRecordClass->DataSize;\r
- returnCode = DEM_GET_SIZEOFEDRBYDTC_OK;\r
+ uint16 posInExtData;\r
+\r
+ if (demState == DEM_INITIALIZED) {\r
+ if (lookupDtcEvent(dtc, &eventRec)) {\r
+ if (checkDtcKind(dtcKind, eventRec->eventParamRef)) {\r
+ if (checkDtcOrigin(dtcOrigin, eventRec->eventParamRef)) {\r
+ if (lookupExtendedDataRecNumParam(extendedDataNumber, eventRec->eventParamRef, &extendedDataRecordClass, &posInExtData)) {\r
+ *sizeOfExtendedDataRecord = extendedDataRecordClass->DataSize; /** @req DEM076 */\r
+ returnCode = DEM_GET_SIZEOFEDRBYDTC_OK;\r
+ }\r
+ else {\r
+ returnCode = DEM_GET_SIZEOFEDRBYDTC_W_RNUM;\r
+ }\r
}\r
else {\r
- returnCode = DEM_GET_SIZEOFEDRBYDTC_W_RNUM;\r
+ returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTCOR;\r
}\r
}\r
else {\r
- returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTCOR;\r
+ returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTCKI;\r
}\r
}\r
- else {\r
- returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTCKI;\r
- }\r
+ } else {\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_GETSIZEOFEXTENDEDDATARECORDBYDTC_ID, DEM_E_UNINIT);\r
+ returnCode = DEM_GET_SIZEOFEDRBYDTC_W_DTC;\r
}\r
\r
return returnCode;\r
\r
\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DEM128 */\r
+\r
+\r
+\r
#ifndef DEM_LCFG_H_\r
#define DEM_LCFG_H_\r
\r
#include "Dem_Types.h"\r
#if defined(USE_DCM)\r
-#include "Dcm_Types.h"\r
+#include "Dcm_Types.h" /** @req DEM176.Dcm */\r
#endif\r
\r
\r
*/\r
\r
// InitMonitorForEvent\r
-typedef Std_ReturnType (*Dem_CallbackInitMonitorForEventFncType)(Dem_InitMonitorKindType InitMonitorKind);\r
+typedef Std_ReturnType (*Dem_CallbackInitMonitorForEventFncType)(Dem_InitMonitorKindType InitMonitorKind); /** @req DEM256 */\r
\r
// InitMonitorForFunction\r
-typedef Std_ReturnType (*Dem_CallbackInitMonitorForFunctionFncType)(void);\r
+typedef Std_ReturnType (*Dem_CallbackInitMonitorForFunctionFncType)(void); /** @req DEM258 */\r
\r
// EventStatusChanged\r
-typedef Std_ReturnType (*Dem_CallbackEventStatusChangedFncType)(Dem_EventStatusExtendedType EventStatusOld, Dem_EventStatusExtendedType EventStatusNew);\r
+typedef Std_ReturnType (*Dem_CallbackEventStatusChangedFncType)(Dem_EventStatusExtendedType EventStatusOld, Dem_EventStatusExtendedType EventStatusNew); /** @req DEM259 */\r
\r
// DTCStatusChanged\r
-typedef Std_ReturnType (*Dem_CallbackDTCStatusChangedFncType)(uint8 DTCStatusOld, uint8 DTCStatusNew);\r
+typedef Std_ReturnType (*Dem_CallbackDTCStatusChangedFncType)(uint8 DTCStatusOld, uint8 DTCStatusNew); /** @req DEM260 */\r
\r
-// DIDServices\r
+// DIDServices /** @req DEM261 */\r
#if defined(USE_DCM)\r
typedef Std_ReturnType (*Dem_CallbackConditionCheckReadFncType)(Dcm_NegativeResponseCodeType *Nrc);\r
typedef Std_ReturnType (*Dem_CallbackReadDataFncType)(uint8 *Data);\r
#endif\r
\r
// GetExtendedDataRecord\r
-typedef Std_ReturnType (*Dem_CallbackGetExtDataRecordFncType)(uint8 *ExtendedDataRecord);\r
+typedef Std_ReturnType (*Dem_CallbackGetExtDataRecordFncType)(uint8 *ExtendedDataRecord); /** @req DEM262 */\r
\r
// GetFaultDetectionCounter\r
-typedef Std_ReturnType (*Dem_CallbackGetFaultDetectionCounterFncType)(sint8 *EventIdFaultDetectionCounter);\r
+typedef Std_ReturnType (*Dem_CallbackGetFaultDetectionCounterFncType)(sint8 *EventIdFaultDetectionCounter); /** @req DEM263 */\r
\r
// GetPIDValue\r
-typedef Std_ReturnType (*Dem_CallbackGetPIDValueFncType)(uint8 *DataValueBuffer);\r
+typedef Std_ReturnType (*Dem_CallbackGetPIDValueFncType)(uint8 *DataValueBuffer); /** @req DEM326 */\r
\r
/*\r
* DemGeneral types\r
*/\r
+/** @req DEM128 */\r
\r
// 10.2.25 DemEnableCondition\r
typedef struct {\r
typedef struct {\r
uint16 RecordNumber; // (1)\r
uint16 DataSize; // (1)\r
- Dem_CallbackGetExtDataRecordFncType CallbackGetExtDataRecord;// (1)\r
-} Dem_ExtendedDataRecordClassType;\r
+ Dem_CallbackGetExtDataRecordFncType CallbackGetExtDataRecord;// (1) /** @req DEM139 */\r
+} Dem_ExtendedDataRecordClassType; /** @req DEM135 */\r
\r
// 10.2.13 DemExtendedDataClass\r
typedef struct {\r
const Dem_ExtendedDataRecordClassType *const ExtendedDataRecordClassRef[DEM_MAX_NR_OF_RECORDS_IN_EXTENDED_DATA+1]; // (1..253)\r
-} Dem_ExtendedDataClassType;\r
+} Dem_ExtendedDataClassType; /** @req DEM135 */\r
\r
// 10.2.8 DemPidOrDid\r
typedef struct {\r
const uint8 *PidIndentifier; // (0..1)\r
Dem_CallbackGetPIDValueFncType PidReadFnc; // (0..1)\r
boolean Arc_EOL;\r
-} Dem_PidOrDidType;\r
+} Dem_PidOrDidType; /** @req DEM136 */\r
\r
// 10.2.18 DemFreezeFrameClass\r
typedef struct {\r
Dem_FreezeFrameKindType FFKind; // (1)\r
uint8 FFRecordNumber; // (1)\r
const Dem_PidOrDidType *FFIdClassRef; // (1..255)\r
-} Dem_FreezeFrameClassType;\r
+} Dem_FreezeFrameClassType; /** @req DEM136 */\r
\r
// 10.2.4 DemIndicator\r
typedef struct {\r
uint16 Indicator; // (1)\r
-} Dem_IndicatorType;\r
+} Dem_IndicatorType; /** @req DEM129 */\r
\r
// 10.2.28 DemNvramBlockId\r
typedef struct {\r
// 10.2.6 DemCallbackDTCStatusChanged\r
typedef struct {\r
Dem_CallbackDTCStatusChangedFncType CallbackDTCStatusChangedFnc; // (0..1)\r
-} Dem_CallbackDTCStatusChangedType;\r
+} Dem_CallbackDTCStatusChangedType; /** @req DEM140 */\r
\r
// 10.2.26 DemCallbackInitMForF\r
typedef struct {\r
const Dem_CallbackInitMForFType *CallbackInitMForF; // (0..*)\r
// Dem_DTCSeverityType DTCSeverity // (0..1) Optional\r
boolean Arc_EOL;\r
-} Dem_DTCClassType;\r
+} Dem_DTCClassType; /** @req DEM132 */\r
\r
// 10.2.5 DemCallbackEventStatusChanged\r
typedef struct {\r
Dem_CallbackEventStatusChangedFncType CallbackEventStatusChangedFnc; // (0..1)\r
-} Dem_CallbackEventStatusChangedType;\r
+} Dem_CallbackEventStatusChangedType; /** @req DEM140 */\r
\r
// 10.2.27 DemCallbackInitMForE\r
typedef struct {\r
Dem_CallbackInitMonitorForEventFncType CallbackInitMForEFnc; // (0..1)\r
-} Dem_CallbackInitMforEType;\r
+} Dem_CallbackInitMforEType; /** @req DEM130 */\r
\r
+// 10.2.15\r
typedef struct {\r
Dem_IndicatorStatusType IndicatorBehaviour; // (1)\r
Dem_IndicatorType *LinkedIndicator; // (1)\r
-} Dem_IndicatorAttributeType;\r
+} Dem_IndicatorAttributeType; /** @req DEM133 */\r
\r
// 10.2.23 DemPreDebounceMonitorInternal\r
typedef struct {\r
Dem_CallbackGetFaultDetectionCounterFncType CallbackGetFDCntFnc; // (1)\r
-} Dem_PreDebounceMonitorInternalType;\r
+} Dem_PreDebounceMonitorInternalType; /** @req DEM146 */\r
\r
// 10.2.21 DemPreDebounceCounterBased\r
typedef struct {\r
boolean JumpDown;\r
uint8 CountInStepSize;\r
uint8 CountOutStepSize;\r
-} Dem_PreDebounceCounterBasedType;\r
+} Dem_PreDebounceCounterBasedType; /** @req DEM144 */\r
\r
// 10.2.22 DemPreDebounceFrequencyBased\r
typedef struct {\r
// TODO: Fill out\r
} Dem_PreDebounceTimeBasedType;\r
\r
+// 10.2.20\r
typedef struct {\r
Dem_PreDebounceNameType PreDebounceName; // (1)\r
union {\r
const Dem_PreDebounceAlgorithmClassType *PreDebounceAlgorithmClass; // (0..255) (Only 0..1 supported)\r
const Dem_IndicatorAttributeType *IndicatorAttribute; // (0..255)\r
// Dem_OEMSPecific\r
-} Dem_EventClassType;\r
+} Dem_EventClassType; /** @req DEM131 */\r
\r
// 10.2.12 DemEventParameter\r
typedef struct {\r
const Dem_CallbackEventStatusChangedType *CallbackEventStatusChanged;// (0..*)\r
const Dem_DTCClassType *DTCClassRef; // (0..1)\r
boolean Arc_EOL;\r
-} Dem_EventParameterType;\r
+} Dem_EventParameterType; /** @req DEM130 */\r
\r
// 10.2.19 DemGroupOfDTC\r
typedef struct {\r
\r
// 10.2.10 DemOemIdClass\r
typedef struct {\r
- uint8 OemID; // (Pre+Post)\r
-} Dem_OemIdClassType;\r
+ uint8 OemID;\r
+} Dem_OemIdClassType; /** @req DEM141 */\r
\r
// 10.2.9 DemConfigSet\r
typedef struct {\r
const Dem_DTCClassType *DTCClass; // (1..16777214)\r
const Dem_GroupOfDtcType *GroupOfDtc; // (1.16777214)\r
const Dem_OemIdClassType *OemIdClass; // (0..*)\r
-} Dem_ConfigSetType;\r
+} Dem_ConfigSetType; /** @req DEM130 */\r
\r
// 10.2.2 Dem\r
typedef struct {\r
\r
#ifndef DEM_TYPES_H_\r
#define DEM_TYPES_H_\r
-#include "Std_Types.h"\r
+#include "Std_Types.h" /** @req DEM176.Std */\r
+#include "Rte_Dem.h"\r
+#define DEM_EVENT_DESTINATION_END_OF_LIST 0\r
\r
/*\r
* DTC storage types\r
#define DEM_SAEJ1939_73 0x02\r
#define DEM_ISO_11992_4 0x03\r
\r
-/*\r
- * Dem_EventIdType\r
- */\r
-typedef uint16 Dem_EventIdType;\r
-\r
/*\r
* Dem_DTCGroupType\r
*/\r
typedef uint32 Dem_DTCGroupType;\r
-#define DEM_DTC_GROUP_ALL_DTCS 0xffffff\r
+#define DEM_DTC_GROUP_ALL_DTCS (Dem_DTCGroupType)0xffffff\r
\r
/*\r
* Dem status type\r
*/\r
-#define DEM_DTC_STATUS_MASK_ALL 0x00\r
+#define DEM_DTC_STATUS_MASK_ALL (uint8)0x00\r
\r
\r
/*\r
* DemDTCKindType\r
*/\r
-typedef uint8 Dem_DTCKindType;\r
-#define DEM_DTC_KIND_ALL_DTCS 0x01\r
-#define DEM_DTC_KIND_EMISSION_REL_DTCS 0x02\r
+#define DEM_DTC_KIND_ALL_DTCS (Dem_DTCKindType)0x01\r
+#define DEM_DTC_KIND_EMISSION_REL_DTCS (Dem_DTCKindType)0x02\r
\r
/*\r
* DemDTCOriginType\r
*/\r
typedef uint8 Dem_DTCOriginType;\r
-#define DEM_DTC_ORIGIN_SECONDARY_MEMORY 0x01\r
-#define DEM_DTC_ORIGIN_PRIMARY_MEMORY 0x02\r
-#define DEM_DTC_ORIGIN_PERMANENT_MEMORY 0x03\r
-#define DEM_DTC_ORIGIN_MIRROR_MEMORY 0x04\r
-\r
-/*\r
- * DemEventStatusExtendedType\r
- */\r
-typedef uint8 Dem_EventStatusExtendedType;\r
-#define DEM_TEST_FAILED 0x01\r
-#define DEM_TEST_FAILED_THIS_OPERATION_CYCLE 0x02\r
-#define DEM_PENDING_DTC 0x04\r
-#define DEM_CONFIRMED_DTC 0x08\r
-#define DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR 0x10\r
-#define DEM_TEST_FAILED_SINCE_LAST_CLEAR 0x20\r
-#define DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE 0x40\r
-#define DEM_WARNING_INDICATOR_REQUESTED 0x80\r
+#define DEM_DTC_ORIGIN_SECONDARY_MEMORY (Dem_DTCOriginType)0x01\r
+#define DEM_DTC_ORIGIN_PRIMARY_MEMORY (Dem_DTCOriginType)0x02\r
+#define DEM_DTC_ORIGIN_PERMANENT_MEMORY (Dem_DTCOriginType)0x03\r
+#define DEM_DTC_ORIGIN_MIRROR_MEMORY (Dem_DTCOriginType)0x04\r
+\r
+#define DEM_TEST_FAILED (Dem_EventStatusExtendedType)0x01\r
+#define DEM_TEST_FAILED_THIS_OPERATION_CYCLE (Dem_EventStatusExtendedType)0x02\r
+#define DEM_PENDING_DTC (Dem_EventStatusExtendedType)0x04\r
+#define DEM_CONFIRMED_DTC (Dem_EventStatusExtendedType)0x08\r
+#define DEM_TEST_NOT_COMPLETED_SINCE_LAST_CLEAR (Dem_EventStatusExtendedType)0x10\r
+#define DEM_TEST_FAILED_SINCE_LAST_CLEAR (Dem_EventStatusExtendedType)0x20\r
+#define DEM_TEST_NOT_COMPLETED_THIS_OPERATION_CYCLE (Dem_EventStatusExtendedType)0x40\r
+#define DEM_WARNING_INDICATOR_REQUESTED (Dem_EventStatusExtendedType)0x80\r
\r
-/*\r
- * DemOperationCycleType\r
- */\r
-typedef uint8 Dem_OperationCycleIdType; // TODO: Check type and values\r
enum {\r
DEM_ACTIVE, // Started by DEM on Dem_PreInit and stopped on Dem_Shutdown\r
\r
DEM_OBD_DCY, // OBD Driving Cycle\r
\r
DEM_OPERATION_CYCLE_ID_ENDMARK\r
-};\r
+}; /** @req DEM142 */\r
\r
-/*\r
- * Dem_OperationCycleStateType\r
- */\r
-typedef uint8 Dem_OperationCycleStateType;\r
-#define DEM_CYCLE_STATE_START 1\r
-#define DEM_CYCLE_STATE_END 2\r
+#define DEM_CYCLE_STATE_START (Dem_OperationCycleStateType)1\r
+#define DEM_CYCLE_STATE_END (Dem_OperationCycleStateType)2\r
\r
/*\r
* Dem_FreezeFrameKindType\r
*/\r
typedef uint8 Dem_FreezeFrameKindType; // TODO: Check type and values\r
-#define DEM_FREEZE_FRAME_NON_OBD 0x01\r
-#define DEM_FREEZE_FRAME_OBD 0x02\r
+#define DEM_FREEZE_FRAME_NON_OBD (Dem_FreezeFrameKindType)0x01\r
+#define DEM_FREEZE_FRAME_OBD (Dem_FreezeFrameKindType)0x02\r
\r
/*\r
* Dem_EventKindType\r
*/\r
typedef uint8 Dem_EventKindType; // TODO: Check type and values\r
-#define DEM_EVENT_KIND_BSW 0x01\r
-#define DEM_EVENT_KIND_SWC 0x02\r
+#define DEM_EVENT_KIND_BSW (Dem_EventKindType)0x01\r
+#define DEM_EVENT_KIND_SWC (Dem_EventKindType)0x02\r
\r
/*\r
* Dem_EventStatusType\r
*/\r
typedef uint8 Dem_EventStatusType;\r
-#define DEM_EVENT_STATUS_PASSED 0\r
-#define DEM_EVENT_STATUS_FAILED 1\r
-#define DEM_EVENT_STATUS_PREPASSED 2\r
-#define DEM_EVENT_STATUS_PREFAILED 3\r
+#define DEM_EVENT_STATUS_PASSED (Dem_EventStatusType)0\r
+#define DEM_EVENT_STATUS_FAILED (Dem_EventStatusType)1\r
+#define DEM_EVENT_STATUS_PREPASSED (Dem_EventStatusType)2\r
+#define DEM_EVENT_STATUS_PREFAILED (Dem_EventStatusType)3\r
\r
-/*\r
- * Dem_DTCType\r
- */\r
-typedef uint32 Dem_DTCType;\r
-\r
-/*\r
- * Dem_InitMonitorKindType\r
- */\r
-typedef uint8 Dem_InitMonitorKindType;\r
-#define DEM_INIT_MONITOR_CLEAR 1\r
-#define DEM_INIT_MONITOR_RESTART 2\r
+#define DEM_INIT_MONITOR_CLEAR (Dem_InitMonitorKindType)1\r
+#define DEM_INIT_MONITOR_RESTART (Dem_InitMonitorKindType)2\r
\r
-/*\r
- * Dem_IndicatorStatusType\r
- */\r
-typedef uint8 Dem_IndicatorStatusType;\r
-#define DEM_INDICATOR_OFF 0\r
-#define DEM_INDICATOR_CONTINUOUS 1\r
-#define DEM_INDICATOR_BLINKING 2\r
-#define DEM_INDICATOR_BLINK_CONT 3\r
\r
-/*\r
- * Dem_FaultDetectionCpunterType\r
- */\r
-typedef sint8 Dem_FaultDetectionCounterType;\r
+#define DEM_INDICATOR_OFF (Dem_IndicatorStatusType)0\r
+#define DEM_INDICATOR_CONTINUOUS (Dem_IndicatorStatusType)1\r
+#define DEM_INDICATOR_BLINKING (Dem_IndicatorStatusType)2\r
+#define DEM_INDICATOR_BLINK_CONT (Dem_IndicatorStatusType)3\r
\r
/*\r
* Dem_PreDebounceNameType\r
* Dem_FilterWithSeverityType\r
*/\r
typedef uint8 Dem_FilterWithSeverityType;\r
-#define DEM_FILTER_WITH_SEVERITY_YES 0x00\r
-#define DEM_FILTER_WITH_SEVERITY_NO 0x01\r
+#define DEM_FILTER_WITH_SEVERITY_YES (Dem_FilterWithSeverityType)0x00\r
+#define DEM_FILTER_WITH_SEVERITY_NO (Dem_FilterWithSeverityType)0x01\r
\r
/*\r
* Dem_FilterForFDCType\r
*/\r
typedef uint8 Dem_FilterForFDCType;\r
-#define DEM_FILTER_FOR_FDC_YES 0x00\r
-#define DEM_FILTER_FOR_FDC_NO 0x01\r
+#define DEM_FILTER_FOR_FDC_YES (Dem_FilterForFDCType)0x00\r
+#define DEM_FILTER_FOR_FDC_NO (Dem_FilterForFDCType)0x01\r
\r
/*\r
* Dem_DTCSeverityType\r
*/\r
typedef uint8 Dem_DTCSeverityType;\r
-#define DEM_SEVERITY_NO_SEVERITY 0x00 // No severity information available\r
-#define DEM_SEVERITY_MAINTENANCE_ONLY 0x20\r
-#define DEM_SEVERITY_CHECK_AT_NEXT_FALT 0x40\r
-#define DEM_SEVERITY_CHECK_IMMEDIATELY 0x80\r
+#define DEM_SEVERITY_NO_SEVERITY (Dem_DTCSeverityType)0x00 // No severity information available\r
+#define DEM_SEVERITY_MAINTENANCE_ONLY (Dem_DTCSeverityType)0x20\r
+#define DEM_SEVERITY_CHECK_AT_NEXT_FALT (Dem_DTCSeverityType)0x40\r
+#define DEM_SEVERITY_CHECK_IMMEDIATELY (Dem_DTCSeverityType)0x80\r
\r
/*\r
* Dem_ReturnSetDTCFilterType\r
*/\r
typedef uint8 Dem_ReturnSetDTCFilterType;\r
-#define DEM_FILTER_ACCEPTED 0x00\r
-#define DEM_WRONG_FILTER 0x01\r
+#define DEM_FILTER_ACCEPTED (Dem_ReturnSetDTCFilterType)0x00\r
+#define DEM_WRONG_FILTER (Dem_ReturnSetDTCFilterType)0x01\r
\r
/*\r
* Dem_ReturnGetStatusOfDTCType\r
*/\r
typedef uint8 Dem_ReturnGetStatusOfDTCType;\r
-#define DEM_STATUS_OK 0x00\r
-#define DEM_STATUS_WRONG_DTC 0x01\r
-#define DEM_STATUS_WRONG_DTCORIGIN 0x02\r
-#define DEM_STATUS_FAILED 0x04\r
-#define DEM_STATUS_WRONG_DTCKIND 0x03\r
+#define DEM_STATUS_OK (Dem_ReturnGetStatusOfDTCType)0x00\r
+#define DEM_STATUS_WRONG_DTC (Dem_ReturnGetStatusOfDTCType)0x01\r
+#define DEM_STATUS_WRONG_DTCORIGIN (Dem_ReturnGetStatusOfDTCType)0x02\r
+#define DEM_STATUS_FAILED (Dem_ReturnGetStatusOfDTCType)0x04\r
+#define DEM_STATUS_WRONG_DTCKIND (Dem_ReturnGetStatusOfDTCType)0x03\r
\r
/*\r
* Dem_ReturnGetNextFilteredDTCType\r
*/\r
typedef uint8 Dem_ReturnGetNextFilteredDTCType;\r
-#define DEM_FILTERED_OK 0x00\r
-#define DEM_FILTERED_NO_MATCHING_DTC 0x01\r
-#define DEM_FILTERED_WRONG_DTCKIND 0x02\r
-#define DEM_FILTERED_PENDING 0x03\r
+#define DEM_FILTERED_OK (Dem_ReturnGetNextFilteredDTCType)0x00\r
+#define DEM_FILTERED_NO_MATCHING_DTC (Dem_ReturnGetNextFilteredDTCType)0x01\r
+#define DEM_FILTERED_WRONG_DTCKIND (Dem_ReturnGetNextFilteredDTCType)0x02\r
+#define DEM_FILTERED_PENDING (Dem_ReturnGetNextFilteredDTCType)0x03\r
\r
/*\r
* Dem_ReturnGetNumberOfFilteredDTCType\r
*/\r
typedef uint8 Dem_ReturnGetNumberOfFilteredDTCType;\r
-#define DEM_NUMBER_OK 0x00\r
-#define DEM_NUMBER_FAILED 0x01\r
-#define DEM_NUMBER_PENDING 0x02\r
+#define DEM_NUMBER_OK (Dem_ReturnGetNumberOfFilteredDTCType)0x00\r
+#define DEM_NUMBER_FAILED (Dem_ReturnGetNumberOfFilteredDTCType)0x01\r
+#define DEM_NUMBER_PENDING (Dem_ReturnGetNumberOfFilteredDTCType)0x02\r
\r
/*\r
* Dem_ReturnClearDTCType\r
*/\r
typedef uint8 Dem_ReturnClearDTCType;\r
-#define DEM_CLEAR_OK 0x00\r
-#define DEM_CLEAR_WRONG_DTC 0x01\r
-#define DEM_CLEAR_WRONG_DTCORIGIN 0x02\r
-#define DEM_CLEAR_WRONG_DTCKIND 0x03\r
-#define DEM_CLEAR_FAILED 0x04\r
-#define DEM_DTC_PENDING 0x05\r
+#define DEM_CLEAR_OK (Dem_ReturnClearDTCType)0x00\r
+#define DEM_CLEAR_WRONG_DTC (Dem_ReturnClearDTCType)0x01\r
+#define DEM_CLEAR_WRONG_DTCORIGIN (Dem_ReturnClearDTCType)0x02\r
+#define DEM_CLEAR_WRONG_DTCKIND (Dem_ReturnClearDTCType)0x03\r
+#define DEM_CLEAR_FAILED (Dem_ReturnClearDTCType)0x04\r
+#define DEM_DTC_PENDING (Dem_ReturnClearDTCType)0x05\r
\r
/*\r
* Dem_ReturnControlDTCStorageType\r
*/\r
typedef uint8 Dem_ReturnControlDTCStorageType;\r
-#define DEM_CONTROL_DTC_STORAGE_OK 0x00\r
-#define DEM_CONTROL_DTC_STORAGE_N_OK 0x01\r
-#define DEM_CONTROL_DTC_WRONG_DTCGROUP 0x02\r
+#define DEM_CONTROL_DTC_STORAGE_OK (Dem_ReturnControlDTCStorageType)0x00\r
+#define DEM_CONTROL_DTC_STORAGE_N_OK (Dem_ReturnControlDTCStorageType)0x01\r
+#define DEM_CONTROL_DTC_WRONG_DTCGROUP (Dem_ReturnControlDTCStorageType)0x02\r
\r
/*\r
* Dem_ReturnControlEventUpdateType\r
*/\r
typedef uint8 Dem_ReturnControlEventUpdateType;\r
-#define DEM_CONTROL_EVENT_UPDATE_OK 0x00\r
-#define DEM_CONTROL_EVENT_N_OK 0x01\r
-#define DEM_CONTROL_EVENT_WRONG_DTCGROUP 0x02\r
+#define DEM_CONTROL_EVENT_UPDATE_OK (Dem_ReturnControlEventUpdateType)0x00\r
+#define DEM_CONTROL_EVENT_N_OK (Dem_ReturnControlEventUpdateType)0x01\r
+#define DEM_CONTROL_EVENT_WRONG_DTCGROUP (Dem_ReturnControlEventUpdateType)0x02\r
\r
/*\r
* Dem_ReturnGetDTCOfFreezeframeRecordType\r
*/\r
typedef uint8 Dem_ReturnGetDTCOfFreezeframeRecordType;\r
-#define DEM_GET_DTCOFFF_OK 0x00\r
-#define DEM_GET_DTCOFFF_WRONG_RECORD 0x01\r
-#define DEM_GET_DTCOFFF_NO_DTC_FOR_RECORD 0x02\r
-#define DEM_GET_DTCOFFF_WRONG_DTCKIND 0x03\r
+#define DEM_GET_DTCOFFF_OK (Dem_ReturnGetDTCOfFreezeframeRecordType)0x00\r
+#define DEM_GET_DTCOFFF_WRONG_RECORD (Dem_ReturnGetDTCOfFreezeframeRecordType)0x01\r
+#define DEM_GET_DTCOFFF_NO_DTC_FOR_RECORD (Dem_ReturnGetDTCOfFreezeframeRecordType)0x02\r
+#define DEM_GET_DTCOFFF_WRONG_DTCKIND (Dem_ReturnGetDTCOfFreezeframeRecordType)0x03\r
\r
/*\r
* Dem_GetFreezeFameDataIdentifierByDTCType\r
*/\r
typedef uint8 Dem_GetFreezeFameDataIdentifierByDTCType;\r
-#define DEM_GET_ID_OK 0x00\r
-#define DEM_GET_ID_WRONG_DTC 0x01\r
-#define DEM_GET_ID_WRONG_DTCORIGIN 0x02\r
-#define DEM_GET_ID_WRONG_DTCKIND 0x03\r
-#define DEM_GET_ID_WRONG_FF_TYPE 0x04\r
+#define DEM_GET_ID_OK (Dem_GetFreezeFameDataIdentifierByDTCType)0x00\r
+#define DEM_GET_ID_WRONG_DTC (Dem_GetFreezeFameDataIdentifierByDTCType)0x01\r
+#define DEM_GET_ID_WRONG_DTCORIGIN (Dem_GetFreezeFameDataIdentifierByDTCType)0x02\r
+#define DEM_GET_ID_WRONG_DTCKIND (Dem_GetFreezeFameDataIdentifierByDTCType)0x03\r
+#define DEM_GET_ID_WRONG_FF_TYPE (Dem_GetFreezeFameDataIdentifierByDTCType)0x04\r
\r
/*\r
* Dem_ReturnGetExtendedDataRecordByDTCType\r
*/\r
typedef uint8 Dem_ReturnGetExtendedDataRecordByDTCType;\r
-#define DEM_RECORD_OK 0x00\r
-#define DEM_RECORD_WRONG_DTC 0x01\r
-#define DEM_RECORD_WRONG_DTCORIGIN 0x02\r
-#define DEM_RECORD_DTCKIND 0x03\r
-#define DEM_RECORD_NUMBER 0x04\r
-#define DEM_RECORD_BUFFERSIZE 0x05\r
-#define DEM_RECORD_PENDING 0x06\r
+#define DEM_RECORD_OK (Dem_ReturnGetExtendedDataRecordByDTCType)0x00\r
+#define DEM_RECORD_WRONG_DTC (Dem_ReturnGetExtendedDataRecordByDTCType)0x01\r
+#define DEM_RECORD_WRONG_DTCORIGIN (Dem_ReturnGetExtendedDataRecordByDTCType)0x02\r
+#define DEM_RECORD_DTCKIND (Dem_ReturnGetExtendedDataRecordByDTCType)0x03\r
+#define DEM_RECORD_NUMBER (Dem_ReturnGetExtendedDataRecordByDTCType)0x04\r
+#define DEM_RECORD_BUFFERSIZE (Dem_ReturnGetExtendedDataRecordByDTCType)0x05\r
+#define DEM_RECORD_PENDING (Dem_ReturnGetExtendedDataRecordByDTCType)0x06\r
\r
/*\r
* Dem_ReturnGetDTCByOccurenceTimeType\r
*/\r
typedef uint8 Dem_ReturnGetDTCByOccurenceTimeType;\r
-#define DEM_OCCURR_OK 0x00\r
-#define DEM_OCCURR_WRONG_DTCKIND 0x01\r
-#define DEM_OCCURR_FAILED 0x02\r
+#define DEM_OCCURR_OK (Dem_ReturnGetDTCByOccurenceTimeType)0x00\r
+#define DEM_OCCURR_WRONG_DTCKIND (Dem_ReturnGetDTCByOccurenceTimeType)0x01\r
+#define DEM_OCCURR_FAILED (Dem_ReturnGetDTCByOccurenceTimeType)0x02\r
\r
/*\r
* Dem_ReturnGetFreezeFrameDataByDTCType\r
*/\r
typedef uint8 Dem_ReturnGetFreezeFrameDataByDTCType;\r
-#define DEM_GET_FFDATABYDTC_OK 0x00\r
-#define DEM_GET_FFDATABYDTC_WRONG_DTC 0x01\r
-#define DEM_GET_FFDATABYDTC_WRONG_DTCORIGIN 0x02\r
-#define DEM_GET_FFDATABYDTC_WRONG_DTCKIND 0x03\r
-#define DEM_GET_FFDATABYDTC_RECORDNUMBER 0x04\r
-#define DEM_GET_FFDATABYDTC_WRONG_DATAID 0x05\r
-#define DEM_GET_FFDATABYDTC_BUFFERSIZE 0x06\r
-#define DEM_GET_ID_PENDING 0x07\r
+#define DEM_GET_FFDATABYDTC_OK (Dem_ReturnGetFreezeFrameDataByDTCType)0x00\r
+#define DEM_GET_FFDATABYDTC_WRONG_DTC (Dem_ReturnGetFreezeFrameDataByDTCType)0x01\r
+#define DEM_GET_FFDATABYDTC_WRONG_DTCORIGIN (Dem_ReturnGetFreezeFrameDataByDTCType)0x02\r
+#define DEM_GET_FFDATABYDTC_WRONG_DTCKIND (Dem_ReturnGetFreezeFrameDataByDTCType)0x03\r
+#define DEM_GET_FFDATABYDTC_RECORDNUMBER (Dem_ReturnGetFreezeFrameDataByDTCType)0x04\r
+#define DEM_GET_FFDATABYDTC_WRONG_DATAID (Dem_ReturnGetFreezeFrameDataByDTCType)0x05\r
+#define DEM_GET_FFDATABYDTC_BUFFERSIZE (Dem_ReturnGetFreezeFrameDataByDTCType)0x06\r
+#define DEM_GET_ID_PENDING (Dem_ReturnGetFreezeFrameDataByDTCType)0x07\r
\r
/*\r
* Dem_ReturnGetSizeOfExtendedDataRecordByDTCType\r
*/\r
typedef uint8 Dem_ReturnGetSizeOfExtendedDataRecordByDTCType;\r
-#define DEM_GET_SIZEOFEDRBYDTC_OK 0x00\r
-#define DEM_GET_SIZEOFEDRBYDTC_W_DTC 0x01\r
-#define DEM_GET_SIZEOFEDRBYDTC_W_DTCOR 0x02\r
-#define DEM_GET_SIZEOFEDRBYDTC_W_DTCKI 0x03\r
-#define DEM_GET_SIZEOFEDRBYDTC_W_RNUM 0x04\r
-#define DEM_GET_SIZEOFEDRBYDTC_PENDING 0x05\r
+#define DEM_GET_SIZEOFEDRBYDTC_OK (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x00\r
+#define DEM_GET_SIZEOFEDRBYDTC_W_DTC (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x01\r
+#define DEM_GET_SIZEOFEDRBYDTC_W_DTCOR (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x02\r
+#define DEM_GET_SIZEOFEDRBYDTC_W_DTCKI (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x03\r
+#define DEM_GET_SIZEOFEDRBYDTC_W_RNUM (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x04\r
+#define DEM_GET_SIZEOFEDRBYDTC_PENDING (Dem_ReturnGetSizeOfExtendedDataRecordByDTCType)0x05\r
\r
/*\r
* Dem_ReturnGetSizeOfFreezeFrameType\r
*/\r
typedef uint8 Dem_ReturnGetSizeOfFreezeFrameType;\r
-#define DEM_GET_SIZEOFFF_OK 0x00\r
-#define DEM_GET_SIZEOFFF_WRONG_DTC 0x01\r
-#define DEM_GET_SIZEOFFF_WRONG_DTCOR 0x02\r
-#define DEM_GET_SIZEOFFF_WRONG_DTCKIND 0x03\r
-#define DEM_GET_SIZEOFFF_WRONG_RNUM 0x04\r
-#define DEM_GET_SIZEOFFF_PENDING 0x05\r
+#define DEM_GET_SIZEOFFF_OK (Dem_ReturnGetSizeOfFreezeFrameType)0x00\r
+#define DEM_GET_SIZEOFFF_WRONG_DTC (Dem_ReturnGetSizeOfFreezeFrameType)0x01\r
+#define DEM_GET_SIZEOFFF_WRONG_DTCOR (Dem_ReturnGetSizeOfFreezeFrameType)0x02\r
+#define DEM_GET_SIZEOFFF_WRONG_DTCKIND (Dem_ReturnGetSizeOfFreezeFrameType)0x03\r
+#define DEM_GET_SIZEOFFF_WRONG_RNUM (Dem_ReturnGetSizeOfFreezeFrameType)0x04\r
+#define DEM_GET_SIZEOFFF_PENDING (Dem_ReturnGetSizeOfFreezeFrameType)0x05\r
\r
/*\r
* Dem_ReturnGetSeverityOfDTCType\r
*/\r
typedef uint8 Dem_ReturnGetSeverityOfDTCType;\r
-#define DEM_GET_SEVERITYOFDTC_OK 0x00\r
-#define DEM_GET_SEVERITYOFDTC_WRONG_DTC 0x01\r
-#define DEM_GET_SEVERITYOFDTC_WRONG_ORIGIN 0x02\r
-#define DEM_GET_SEVERITYOFDTC_NOSEVERITY 0x03\r
+#define DEM_GET_SEVERITYOFDTC_OK (Dem_ReturnGetSeverityOfDTCType)0x00\r
+#define DEM_GET_SEVERITYOFDTC_WRONG_DTC (Dem_ReturnGetSeverityOfDTCType)0x01\r
+#define DEM_GET_SEVERITYOFDTC_WRONG_ORIGIN (Dem_ReturnGetSeverityOfDTCType)0x02\r
+#define DEM_GET_SEVERITYOFDTC_NOSEVERITY (Dem_ReturnGetSeverityOfDTCType)0x03\r
\r
\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef RTE_DEM_H_\r
+#define RTE_DEM_H_\r
+\r
+typedef uint8 Dem_DTCKindType;\r
+typedef uint32 Dem_DTCType;\r
+typedef uint16 Dem_EventIdType;\r
+typedef uint8 Dem_EventStatusExtendedType;\r
+typedef sint8 Dem_FaultDetectionCounterType;\r
+typedef uint8 Dem_IndicatorStatusType;\r
+typedef uint8 Dem_InitMonitorKindType;\r
+typedef uint8 Dem_OperationCycleIdType;\r
+typedef uint8 Dem_OperationCycleStateType;\r
+\r
+#endif /* RTE_DEM_H_ */\r
*\r
*/\r
\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DET001 */\r
+/** @req DET002 */\r
+\r
+\r
#include "Std_Types.h"\r
#include "Det.h"\r
#include "Cpu.h"\r
+#include "MemMap.h" /** @req DET006 */\r
\r
#define DEBUG_LVL 1\r
#include "debug.h"\r
DET_STARTED\r
} Det_StateType;\r
\r
-static Det_StateType _detState = DET_UNINITIALIZED;\r
+static Det_StateType detState = DET_UNINITIALIZED;\r
\r
#if ( DET_USE_RAMLOG == STD_ON )\r
// Ram log variables in uninitialized memory\r
uint32 Det_RamlogIndex __attribute__ ((section (".ramlog")));\r
+/*lint -esym(552,Det_RamLog)*/ /* PC-Lint OK. supress lintwarning about Det_Ramlog not being accessed */\r
Det_EntryType Det_RamLog[DET_RAMLOG_SIZE] __attribute__ ((section (".ramlog")));\r
#endif\r
\r
\r
uint8 Det_AddCbk(detCbk_t detCbk)\r
{\r
- if (_detState != DET_UNINITIALIZED)\r
+ uint8 rv = DET_CBK_REGISTRATION_FAILED_INDEX; // Return DET_CBK_REGISTRATION_FAILED_INDEX if the registration fails\r
+\r
+ if (detState != DET_UNINITIALIZED)\r
{\r
- for (uint32 i=0; i<DET_NUMBER_OF_CALLBACKS; i++)\r
+ for (uint8 i = 0; i < DET_NUMBER_OF_CALLBACKS; i++)\r
{\r
- if (NULL==detCbk_List[i])\r
+ if (NULL == detCbk_List[i])\r
{\r
- detCbk_List[i]=detCbk;\r
- return i;\r
+ detCbk_List[i] = detCbk;\r
+ rv = i;\r
+ break;\r
}\r
}\r
}\r
\r
- Det_ReportError(DET_MODULE_ID, 0, DET_CALLBACK_API, DET_E_CBK_REGISTRATION_FAILED);\r
- return (0xFF); // Return 0xff to indicate that the registration failed\r
+ if (rv == DET_CBK_REGISTRATION_FAILED_INDEX)\r
+ {\r
+ Det_ReportError(DET_MODULE_ID, 0, DET_CALLBACK_API, DET_E_CBK_REGISTRATION_FAILED);\r
+ }\r
+\r
+ return rv;\r
}\r
\r
+\r
void Det_RemoveCbk(uint8 detCbkIndex)\r
{\r
// Validate the index\r
if (detCbkIndex >= DET_NUMBER_OF_CALLBACKS)\r
+ {\r
Det_ReportError(DET_MODULE_ID, 0, DET_CALLBACK_API, DET_E_INDEX_OUT_OF_RANGE);\r
-\r
- detCbk_List[detCbkIndex]=NULL;\r
+ }\r
+ else\r
+ {\r
+ detCbk_List[detCbkIndex]=NULL;\r
+ }\r
}\r
#endif\r
\r
\r
void Det_Init(void)\r
{\r
- // Implements DET000\r
+\r
#if ( DET_ENABLE_CALLBACKS == STD_ON )\r
for (uint32 i=0; i<DET_NUMBER_OF_CALLBACKS; i++)\r
{\r
}\r
#endif\r
\r
- // Implements DET000\r
+ /** @req DET000 */\r
#if ( DET_USE_RAMLOG == STD_ON )\r
for(uint32 i=0; i < DET_RAMLOG_SIZE; i++)\r
{\r
Det_RamlogIndex = 0;\r
#endif\r
\r
- _detState = DET_INITIALIZED;\r
+ detState = DET_INITIALIZED;\r
}\r
\r
#if DET_DEINIT_API == STD_ON\r
void Det_DeInit( void )\r
{\r
- _detState = DET_UNINITIALIZED;\r
+ detState = DET_UNINITIALIZED;\r
}\r
#endif\r
\r
void Det_ReportError(uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId)\r
{\r
- if (_detState == DET_STARTED) // No action is taken if the module is not started\r
+ if (detState == DET_STARTED) // No action is taken if the module is not started\r
{\r
#if ( DET_ENABLE_CALLBACKS == STD_ON )\r
- long old1;\r
+ uint32 old1; // 586 PC-Lint OK: fattar inte att den används i macrot.\r
Irq_Save(old1);\r
+\r
for (uint32 i=0; i<DET_NUMBER_OF_CALLBACKS; i++)\r
{\r
if (NULL!=detCbk_List[i])\r
Irq_Restore(old1);\r
#endif\r
\r
+\r
#if ( DET_USE_RAMLOG == STD_ON )\r
- long old2;\r
+ uint32 old2;\r
Irq_Save(old2);\r
if (Det_RamlogIndex < DET_RAMLOG_SIZE)\r
{\r
Det_RamLog[Det_RamlogIndex].errorId = ErrorId;\r
Det_RamlogIndex++;\r
#if ( DET_WRAP_RAMLOG == STD_ON )\r
- if (Det_RamlogIndex == DET_RAMLOG_SIZE)\r
+ if (Det_RamlogIndex == DET_RAMLOG_SIZE){\r
Det_RamlogIndex = 0;\r
+ }\r
#endif\r
}\r
Irq_Restore(old2);\r
\r
void Det_Start(void)\r
{\r
- _detState = DET_STARTED;\r
+ detState = DET_STARTED;\r
}\r
#include "Mcu.h"\r
#include <stdio.h>\r
#include <assert.h>\r
-#define USE_TRACE 1\r
-#include "debug.h"\r
-\r
-\r
-#if 0\r
-#ifdef USE_STARTUPHOOK\r
-#ifdef CFG_MPC55XX\r
-#if !defined(USE_SIMULATOR)\r
-// Quick fix\r
-//#include "kernel_offset.h"\r
\r
-extern uint8_t pcb_list[];\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
+#include "debug.h"\r
\r
-#endif\r
-#endif\r
-#endif\r
-#endif\r
\r
\r
\r
void StartupHook( void ) {\r
LDEBUG_PRINTF("## StartupHook\n");\r
\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
-\r
- LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
+ LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)McuE_GetSystemClock());\r
}\r
\r
void ShutdownHook( StatusType Error ) {\r
}\r
// LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
}\r
-\r
-#if 0\r
-struct OsHooks os_conf_global_hooks = {\r
- .StartupHook = StartupHook,\r
- .ProtectionHook = ProtectionHook,\r
- .ShutdownHook = ShutdownHook,\r
- .ErrorHook = ErrorHook,\r
- .PreTaskHook = PreTaskHook,\r
- .PostTaskHook = PostTaskHook\r
- };\r
-#endif\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
-\r
-\r
-\r
-/*\r
- * RTE.h\r
- *\r
- * Author: tojo\r
- */\r
-\r
#ifndef RTE_H_\r
#define RTE_H_\r
#include "RTE_blinker.h"\r
\r
// Select DIO channel\r
#if defined(CFG_BRD_MPC5516IT)\r
-#define LED_CHANNEL LEDS_LED5\r
+#define LED_CHANNEL DIO_CHANNEL_NAME_LEDS_LED5\r
\r
#elif defined(CFG_BRD_MPC5567QRTECH)\r
-#define LED_CHANNEL LED_K2\r
+#define LED_CHANNEL DIO_CHANNEL_NAME_LED_K2\r
+\r
+#elif defined(CFG_BRD_HCS12X_ELMICRO_TBOARD)\r
+#define LED_CHANNEL DIO_CHANNEL_NAME_DO_PB0\r
+\r
+#elif defined(CFG_BRD_HCS12_ELMICRO_CARD12)\r
+#define LED_CHANNEL DIO_CHANNEL_NAME_LED_CHANNEL\r
+\r
+#elif defined(CFG_BRD_STM32_STM3210C)\r
+#define LED_CHANNEL DIO_CHANNEL_NAME_LED_CHANNEL4\r
+\r
+#elif defined(CFG_BRD_STM32_MCBSTM32)\r
+#define LED_CHANNEL DIO_CHANNEL_NAME_LED_CHANNEL1\r
\r
#else\r
#warning "Unknown board or CFG_BRD_* undefined"\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
#include "Os.h"\r
-#include "os_config_macros.h"\r
\r
#include "EcuM.h"\r
-#include <stdio.h>\r
-#include <assert.h>\r
#include "blinker_main.h"\r
+\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
#include "debug.h"\r
-#include "WdgM.h"\r
\r
\r
void OsIdle( void ) {\r
\r
void bTask10( void ) {\r
\r
- WdgM_MainFunction_Trigger();\r
-\r
TerminateTask();\r
}\r
\r
*/\r
void bTask25( void ) {\r
\r
- WdgM_UpdateAliveCounter(WDBG_ALIVE_LOOP_BLINK_COMPONENT);\r
blinker_component_main();\r
\r
TerminateTask();\r
\r
void bTask100( void ) {\r
\r
- WdgM_MainFunction_AliveSupervision();\r
-\r
TerminateTask();\r
}\r
/*\r
SetRelAlarm(ALARM_ID_alarm25, 25, 25); // ADC data acquisition\r
SetRelAlarm(ALARM_ID_alarm100, 100, 100); // ADC data acquisition\r
\r
- WdgM_ActivateAliveSupervision(WDBG_ALIVE_LOOP_BLINK_COMPONENT);\r
-\r
// End of startup_task().\r
TerminateTask();\r
}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>blinker_node_arm_stm32_f103</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="69a3e35e-1874-432a-94f0-b3c74c805be3">\r
+ <SHORT-NAME>blinker_node_arm_stm32_f103</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">STM32_F103</SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/blinker_node_arm_stm32_f103/SwComposition_blinker_node_arm_stm32_f103</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_stm32_f103/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_stm32_f103/Mcu</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_stm32_f103/Det</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_stm32_f103/EcuM</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_stm32_f103/Port</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_stm32_f103/Dio</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="ed185637-4f36-4989-8584-9aade6ae3578">\r
+ <SHORT-NAME>SwComposition_blinker_node_arm_stm32_f103</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="8f496cdc-208c-4918-a887-88c86b069602">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.11</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="b55a25dd-282a-4102-bbb9-eaefcd782dad">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="62701b7c-02ab-4bd2-b5df-cf959638d61b">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b37874ef-0d10-4fdf-beee-b9470e0e7751">\r
+ <SHORT-NAME>alarm25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_stm32_f103/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="7f57c907-292e-4b2b-8d2d-0eb706bea759">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_stm32_f103/Os/bTask25</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e84dd780-f9e1-4915-878c-6ea573729f55">\r
+ <SHORT-NAME>alarm10</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_stm32_f103/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="40d56a04-b12e-4f25-ab64-97f7554de5b4">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_stm32_f103/Os/bTask10</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b2cb6a6b-de7c-49d1-b7e6-b7f32b0bc17d">\r
+ <SHORT-NAME>alarm100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_stm32_f103/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="1cf5902c-ac5d-481d-8ccd-e478b17c3600">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_stm32_f103/Os/bTask100</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="bc300672-c9c6-4205-9a6b-75644c209d9f">\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
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+ <SHORT-NAME>Mcu</SHORT-NAME>\r
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+ <ENUMERATION-VALUE>\r
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+ <VALUE>GPIOB</VALUE>\r
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+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ </STRING-VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>OUTPUT_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>OUTPUT_PUSHPULL_CNF</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5a8b80b4-e1db-4e70-8f33-50c1fffa61dd">\r
+ <SHORT-NAME>B14</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>OUTPUT_10MHz_MODE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
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+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </STRING-VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
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+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>OUTPUT_PUSHPULL_CNF</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="f25b824a-e61e-4f91-ac6a-9dc8379dc97e">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortGeneral/ArcGpioRemap</DEFINITION-REF>\r
+ <VALUE>Remap1_CAN1</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
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+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortGeneral/ArcGpioRemap</DEFINITION-REF>\r
+ <VALUE>PartialRemap2_TIM2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="98039516-0a14-4137-946a-1a1797bbc961">\r
+ <SHORT-NAME>Dio</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Dio</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="42abff38-b3e4-488c-a50d-c27e7710d8e0">\r
+ <SHORT-NAME>DioGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2b6f247f-98ce-4501-b07f-f3b5374a003a">\r
+ <SHORT-NAME>LED_PORT</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioPortId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>B</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9c7caeea-c077-409b-b7be-f18b3d949cd0">\r
+ <SHORT-NAME>LED_CHANNEL1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>29</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="469ceef0-ab55-4ec9-8884-bd9a6faf333d">\r
+ <SHORT-NAME>LED_CHANNEL2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>blinker_node_arm_cm3</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="7cf102d9-f929-4b4a-97b6-4ef11256183a">\r
+ <SHORT-NAME>blinker_node_arm_cm3_107</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">STM32_F107</SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/blinker_node_arm_cm3/SwComposition_blinker_node_arm_cm3</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_cm3/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_cm3/Dio</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_cm3/Port</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_cm3/Det</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_cm3/Mcu</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_arm_cm3/EcuM</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="bf0ee133-5ed1-418a-b260-47e171242afc">\r
+ <SHORT-NAME>SwComposition_blinker_node_arm_cm3</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="4fe46a12-0672-428f-99e3-c4ca6570a776">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="80853be9-55dc-435f-95ed-9a1c90750299">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="7f1dfe11-aeff-4131-89a9-2fbe9a87f01f">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
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+ <SHORT-NAME>alarm25</SHORT-NAME>\r
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+ <REFERENCE-VALUES>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_cm3/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
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+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
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+ </REFERENCE-VALUE>\r
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+ <SHORT-NAME>OsTick</SHORT-NAME>\r
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+ <VALUE>65535</VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <SHORT-NAME>Dio</SHORT-NAME>\r
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+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ <CONTAINER UUID="bcdf538c-c632-43f4-b5cd-044bae94bb81">\r
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+ <CONTAINER UUID="749d0ffd-c994-41a1-b4c7-80400cde05ca">\r
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+ <CONTAINER UUID="44f582a3-7fd9-4d79-b41a-08ab68858e7e">\r
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+ <SHORT-NAME>LED_CHANNEL3</SHORT-NAME>\r
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+ <SHORT-NAME>LED_CHANNEL4</SHORT-NAME>\r
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+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="c4495147-c1ed-4a19-b1e3-ab23d11e7bcf">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
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+ </ADMIN-DATA>\r
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+ <CONTAINERS>\r
+ <CONTAINER UUID="2ba230a3-f785-4514-a224-7269f37bd048">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="2d1aee91-6d16-4a68-a045-4b35ad52966e">\r
+ <SHORT-NAME>PortContainer_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="be66b280-6ace-4b1f-b8a3-a923d64569b5">\r
+ <SHORT-NAME>D3_LED3</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>OUTPUT_10MHz_MODE</VALUE>\r
+ </ENUMERATION-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <VALUE>51</VALUE>\r
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+ <VALUE></VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>OUTPUT_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>OUTPUT_PUSHPULL_CNF</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="eb64422e-85c5-4fec-964d-5916a807f1fe">\r
+ <SHORT-NAME>D4_LED4</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>OUTPUT_10MHz_MODE</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <VALUE>52</VALUE>\r
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+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>OUTPUT_HIGH</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>OUTPUT_PUSHPULL_CNF</VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="a99a1b7e-6ffa-474b-91d6-1324e60d8c7f">\r
+ <SHORT-NAME>D7_LED1</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
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+ <VALUE>OUTPUT_10MHz_MODE</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <VALUE>55</VALUE>\r
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+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>OUTPUT_HIGH</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>OUTPUT_PUSHPULL_CNF</VALUE>\r
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+ <CONTAINER UUID="c430af31-68b9-4780-8dc2-d9f09edde143">\r
+ <SHORT-NAME>D13_LED2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>OUTPUT_10MHz_MODE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <VALUE>61</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>OUTPUT_HIGH</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>OUTPUT_PUSHPULL_CNF</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
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+ <CONTAINER UUID="0ffde529-3c0f-49eb-88af-da644cb60e3e">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortGeneral/ArcGpioRemap</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
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+ <MODULE-CONFIGURATION UUID="e0b9bc68-bd05-4ae1-9ae1-7a46fc6a3f86">\r
+ <SHORT-NAME>Det</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG/>\r
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+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
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+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Det</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="42d6bd8a-d355-4e0c-be5b-02cfb3a0e8e0">\r
+ <SHORT-NAME>DetGeneral</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetEnableCallbacks</DEFINITION-REF>\r
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+ </BOOLEAN-VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetWrapRamlog</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetUseStdErr</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetDeInitAPI</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Det/DetGeneral/DetNumberOfCallbacks</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Det/DetGeneral/DetRamlogSize</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="456a6a95-5836-473d-95e1-599a735500a0">\r
+ <SHORT-NAME>Mcu</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
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+ <CONTAINER UUID="b45ffd68-b2b9-4874-9de0-5f1faae58415">\r
+ <SHORT-NAME>McuGeneralConfiguration</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <CONTAINER UUID="a43b4ed4-eed7-4a21-885f-b5ba25372099">\r
+ <SHORT-NAME>McuModuleConfiguration</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSrcFailureNotification</DEFINITION-REF>\r
+ <VALUE>DISABLED</VALUE>\r
+ </ENUMERATION-VALUE>\r
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+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuNumberOfMcuModes</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuRamSectors</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuResetSetting</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="5b150cab-d2e9-426f-b365-9ae189671851">\r
+ <SHORT-NAME>McuClockSettingConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAHBClocksEnable</DEFINITION-REF>\r
+ <VALUE>DMA1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAHBClocksEnable</DEFINITION-REF>\r
+ <VALUE>ETH_MAC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAHBClocksEnable</DEFINITION-REF>\r
+ <VALUE>ETH_MAC_Tx</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAHBClocksEnable</DEFINITION-REF>\r
+ <VALUE>ETH_MAC_Rx</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB1ClocksEnable</DEFINITION-REF>\r
+ <VALUE>TIM2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB1ClocksEnable</DEFINITION-REF>\r
+ <VALUE>CAN1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB2ClocksEnable</DEFINITION-REF>\r
+ <VALUE>ADC1</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB2ClocksEnable</DEFINITION-REF>\r
+ <VALUE>GPIOA</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB2ClocksEnable</DEFINITION-REF>\r
+ <VALUE>GPIOB</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB2ClocksEnable</DEFINITION-REF>\r
+ <VALUE>GPIOC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB2ClocksEnable</DEFINITION-REF>\r
+ <VALUE>GPIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB2ClocksEnable</DEFINITION-REF>\r
+ <VALUE>GPIOE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/ArcAPB2ClocksEnable</DEFINITION-REF>\r
+ <VALUE>AFIO</VALUE>\r
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+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuDefaultClockReference</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_arm_cm3/Mcu/McuModuleConfiguration/McuClockSettingConfig/EXT_REF_25MHZ</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="08023f7f-13d4-4ccf-902a-d0e86ccc4443">\r
+ <SHORT-NAME>EXT_REF_25MHZ</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>2.5E7</VALUE>\r
+ </FLOAT-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEprediv</DEFINITION-REF>\r
+ <VALUE>9</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEmfd</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllErfd</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ </PARAMETER-VALUES>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="179c0741-fc9d-403a-a18f-b1c76a5374f7">\r
+ <SHORT-NAME>McuModeSettingConf</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="597f7367-2870-4d20-8912-217d97d63aaa">\r
+ <SHORT-NAME>EcuM</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/EcuM</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="32e03636-768e-40a9-9de6-e94ef943afdc">\r
+ <SHORT-NAME>EcuMGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMIncludeNvramMgr</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMMainFunctionPeriod</DEFINITION-REF>\r
+ <VALUE>0.2</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="bf51604d-cca9-49b6-90da-535a5b1b5ff4">\r
+ <SHORT-NAME>EcuMConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramReadallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMRunMinimumDuration</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramWriteallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE UUID="b715bb9d-eec4-4ac5-acdb-a63c2c5c7b2f">\r
+ <SHORT-NAME>blinker_node_hcs12</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY />\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="194b9abc-510c-4b5e-8486-65c5b26772af">\r
+ <SHORT-NAME>blinker_node_hcs12</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <REVISION-LABEL>Rev 2</REVISION-LABEL>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="AUTHOR">ArcCore AB</SD>\r
+ <SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
+ <SD GID="GENDIR" />\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_hcs12/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="4fe46a12-0672-428f-99e3-c4ca6570a776">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="80853be9-55dc-435f-95ed-9a1c90750299">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
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+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="7f1dfe11-aeff-4131-89a9-2fbe9a87f01f">\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ </SUB-CONTAINERS>\r
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+ <CONTAINER UUID="77224460-9071-4c32-9ba5-5ee19d0a5be2">\r
+ <SHORT-NAME>alarm25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_hcs12/Os/OsTick</VALUE-REF>\r
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+ <CONTAINER UUID="28398b0a-02ef-4aa0-9f06-90c0683ad934">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
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+ </REFERENCE-VALUE>\r
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+ </CONTAINER>\r
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+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
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+\r
--- /dev/null
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+ <VALUE>2048</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
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+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
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+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
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+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="2e154d7d-f497-4314-ba43-4493bf64aa0d">\r
+ <SHORT-NAME>Mcu</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Mcu</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="0edd9d00-1f4a-4ea5-a22a-c45cdbcf6e13">\r
+ <SHORT-NAME>McuGeneralConfiguration</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="84e20040-0673-47e6-93b8-2408cc64eb97">\r
+ <SHORT-NAME>McuModuleConfiguration</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSrcFailureNotification</DEFINITION-REF>\r
+ <VALUE>DISABLED</VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ <INTEGER-VALUE>\r
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+ <VALUE>1</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuResetSetting</DEFINITION-REF>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="19d66b5b-4d9b-4cdf-a08e-2d24bf390a33">\r
+ <SHORT-NAME>McuClockSettingConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuDefaultClockReference</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_mpc5516/Mcu/McuModuleConfiguration/McuClockSettingConfig/EXT_REF_80MHZ</VALUE-REF>\r
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+ <CONTAINER UUID="8c6f2066-f999-492f-8599-71a0d3aab0de">\r
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+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>8000000.0</VALUE>\r
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+ <VALUE>1</VALUE>\r
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+ <VALUE>104</VALUE>\r
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+ <VALUE>5</VALUE>\r
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+ <CONTAINER UUID="8a989167-768f-47cd-86c8-ce9619b47d85">\r
+ <SHORT-NAME>EXT_REF_66MHZ</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
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+ <VALUE>1.6E7</VALUE>\r
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+ <VALUE>3</VALUE>\r
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+ <VALUE>83</VALUE>\r
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+ <VALUE>5</VALUE>\r
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+ <CONTAINER UUID="734a50e2-70db-4cf9-856c-afd74514d902">\r
+ <SHORT-NAME>McuModeSettingConf</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
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+ <VALUE>0</VALUE>\r
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+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="99dd2932-f344-424c-88cb-0b0e6e005662">\r
+ <SHORT-NAME>Det</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
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+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Det</DEFINITION-REF>\r
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+ <CONTAINER UUID="7d8226d8-a4c9-4d6d-85b5-833eb68ad0e8">\r
+ <SHORT-NAME>DetGeneral</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetEnableCallbacks</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetUseRamlog</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetWrapRamlog</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetUseStdErr</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetDeInitAPI</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <VALUE>5</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Det/DetGeneral/DetRamlogSize</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
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+ </PARAMETER-VALUES>\r
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+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="36b47e2e-64a8-4e14-89f9-eca2a49722c2">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
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+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="60a1cceb-9bde-468c-8a66-a5590fbbc647">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="d745e13a-91e8-424c-8038-0a1e3bec9f84">\r
+ <SHORT-NAME>LED_PORT</SHORT-NAME>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="2a51b050-1fc1-41c7-8c1c-5c6d3933bf6c">\r
+ <SHORT-NAME>PD[4]</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <VALUE>52</VALUE>\r
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+ <VALUE>SLEW_RATE_MIN</VALUE>\r
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+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
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+ <CONTAINER UUID="c3d466db-9737-425a-a299-a7c781b4b172">\r
+ <SHORT-NAME>PD[5]</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <VALUE>53</VALUE>\r
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+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
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+ <CONTAINER UUID="8d698577-d736-4761-a645-99c113994342">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
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+ <BOOLEAN-VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
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+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
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+ </REFERENCE-VALUE>\r
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+ <CONTAINER UUID="89f89e91-5691-49cd-833b-4e9d14117a98">\r
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+ <VALUE-REF DEST="CONTAINER">/blinker_node_mpc5567/Os/bTask100</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
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+ <SHORT-NAME>Det</SHORT-NAME>\r
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+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Det</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="7d8226d8-a4c9-4d6d-85b5-833eb68ad0e8">\r
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+ <BOOLEAN-VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetUseRamlog</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetWrapRamlog</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetUseStdErr</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Det/DetGeneral/DetDeInitAPI</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Det/DetGeneral/DetNumberOfCallbacks</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Det/DetGeneral/DetRamlogSize</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="198876eb-33cf-4cbf-a37c-06d8a9670fe9">\r
+ <SHORT-NAME>EcuM</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/EcuM</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="576fbc52-a01f-44d3-9519-8e4116800610">\r
+ <SHORT-NAME>EcuMGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMIncludeNvramMgr</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMMainFunctionPeriod</DEFINITION-REF>\r
+ <VALUE>0.2</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="fa5bd3d6-0951-43a5-8529-7140d9689037">\r
+ <SHORT-NAME>EcuMConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramReadallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMRunMinimumDuration</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramWriteallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="cfa529c2-e3f7-422c-a12b-3271f42cb27d">\r
+ <SHORT-NAME>Mcu</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ <SD GID="GENERATE_AND_VALIDATE">false</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Mcu</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="72eda2b7-cb7d-4873-b5e9-79daed917de9">\r
+ <SHORT-NAME>McuGeneralConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuGeneralConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuPerformResetApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Mcu/McuGeneralConfiguration/McuVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d8f198d5-8901-4cfa-ba6b-06b5fa32fe84">\r
+ <SHORT-NAME>McuModuleConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSrcFailureNotification</DEFINITION-REF>\r
+ <VALUE>DISABLED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuNumberOfMcuModes</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="DERIVED-INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuRamSectors</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuResetSetting</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b4a7ace7-9dc0-489b-b545-a813bc08b327">\r
+ <SHORT-NAME>McuClockSettingConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuDefaultClockReference</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/blinker_node_mpc5567/Mcu/McuModuleConfiguration/McuClockSettingConfig/EXT_REF_80MHZ</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="72e293da-ad58-40a3-bb0a-07b9010c05fb">\r
+ <SHORT-NAME>EXT_REF_80MHZ</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointFrequency</DEFINITION-REF>\r
+ <VALUE>1.6E7</VALUE>\r
+ </FLOAT-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEprediv</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllEmfd</DEFINITION-REF>\r
+ <VALUE>11</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuClockSettingConfig/McuClockReferencePoint/McuClockReferencePointPllErfd</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="bb62035a-69d0-4503-8ce8-7b7adb6b845a">\r
+ <SHORT-NAME>McuModeSettingConf</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Mcu/McuModuleConfiguration/McuModeSettingConf/McuMode</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="8254a509-e508-4280-8ec0-0817ef68495b">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ <SD GID="GENERATE_AND_VALIDATE">false</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="496e8330-5da6-48f8-9e21-f6d4fed81187">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="0f17c271-bfae-4d07-8283-9ce8a8118f1b">\r
+ <SHORT-NAME>PortContainer_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="0c45b12c-496e-4f6a-9949-5e224a9adf33">\r
+ <SHORT-NAME>GPIO[125]</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>125</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_DIO</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="105ccb0c-0a5c-4930-a423-09e2b0730514">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="70ab573d-bc1a-419a-8c53-86d9da6d2405">\r
+ <SHORT-NAME>Dio</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ <SD GID="GENERATE_AND_VALIDATE">false</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Dio</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="0b40745e-f0ce-4aee-9499-b05e16e2241f">\r
+ <SHORT-NAME>DioGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Dio/DioGeneral/DioVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ba82bde5-69dc-4c1d-8fc0-2539f1e7e105">\r
+ <SHORT-NAME>DioPort_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioPortId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Dio/DioPort/ArcCoreDioPhysicalPort</DEFINITION-REF>\r
+ <VALUE>DIO_MPC5567_GENERIC_PORT</VALUE>\r
+ </STRING-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="19f14a77-d8e8-40cb-99dd-6b6e751b916a">\r
+ <SHORT-NAME>LED_K2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Dio/DioPort/DioChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Dio/DioPort/DioChannel/DioChannelId</DEFINITION-REF>\r
+ <VALUE>125</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="b715bb9d-eec4-4ac5-acdb-a63c2c5c7b2f">\r
<SHORT-NAME>blinker_node_ppc</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/blinker_node_ppc/SwComposition_blinker_node_ppc</ECU-SW-COMPOSITION-REF>\r
<MODULE-REFS>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/blinker_node_ppc/Os</MODULE-REF>\r
</MODULE-REFS>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
</INTEGER-VALUE>\r
<BOOLEAN-VALUE>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
- <VALUE>true</VALUE>\r
+ <VALUE>false</VALUE>\r
</BOOLEAN-VALUE>\r
<BOOLEAN-VALUE>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
</CONTAINER>\r
</CONTAINERS>\r
</MODULE-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="b217f781-83a1-42b7-938f-4b0823016aac">\r
+ <SHORT-NAME>SwComposition_blinker_node_ppc</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
+-include ../config/*.mk\r
+-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU WDG WDGM PORT DIO\r
+MOD_USE+=ECUM KERNEL MCU PORT DIO DET\r
\r
SELECT_CONSOLE = RAMLOG\r
SELECT_OS_CONSOLE = RAMLOG\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#include "WdgM_Cfg.h"\r
-\r
-Wdgm_SupervisionType Wdgm_Supervision[WDBG_NBR_OF_ALIVE_SIGNALS];\r
-\r
-\r
-const WdgM_SupervisedEntityType WdgM_SupervisedEntity [WDBG_NBR_OF_ALIVE_SIGNALS] =\r
-{\r
- {\r
- .WdgM_SupervisedEntityID = WDBG_ALIVE_LOOP_BLINK_COMPONENT,\r
- .WdgM_ActivationStatus = WDBG_SUPERVISION_DISABLED,\r
- .WdgM_ExpectedAliveIndications = 4,\r
- .WdgM_SupervisionReferenceCycle = 1,\r
- .WdgM_FailedSupervisionReferenceCycleTolerance = 1,\r
- .WdgM_MinMargin = 1,\r
- .WdgM_MaxMargin = 1\r
- },\r
-};\r
-\r
-const WdgM_ConfigType WdgMAliveSupervision =\r
-{\r
- .WdgM_SupervisionCycle = 1,\r
- .WdgM_NumberOfSupervisedEntities = WDBG_NBR_OF_ALIVE_SIGNALS,\r
- .WdgM_ExpiredSupervisionCycleTolerance = 1,\r
- .WdgM_SupervisedEntityPtr = WdgM_SupervisedEntity,\r
- .Wdgm_SupervisionPtr = Wdgm_Supervision\r
-};\r
-\r
-\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 11:40:48 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,256);\r
+DECLARE_STACK(bTask10,512);\r
+DECLARE_STACK(bTask100,512);\r
+DECLARE_STACK(bTask25,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 11:40:48 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:10:48 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,256);\r
+DECLARE_STACK(bTask10,512);\r
+DECLARE_STACK(bTask100,512);\r
+DECLARE_STACK(bTask25,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:10:48 CET 2011\r
+ */\r
+\r
+
+#if ((OS_SW_MAJOR_VERSION != 2))
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
--- /dev/null
+/*\r
+ * Configuration of module Det (Det_cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+
+#if !(((DET_SW_MAJOR_VERSION == 1) && (DET_SW_MINOR_VERSION == 0)) )
+#error "Det: Configuration file version differs from BSW version."
+#endif
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H \r
+\r
+#define DET_ENABLE_CALLBACKS STD_OFF // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+#define DET_DEINIT_API STD_OFF // Enable/Disable the Det_DeInit function\r
+#define DET_RAMLOG_SIZE (16) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /* DET_CFG_H */\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+
+#if !(((DIO_SW_MAJOR_VERSION == 1) && (DIO_SW_MINOR_VERSION == 0)) )
+#error "Dio: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ DIO_PORT_A = 0,\r
+ DIO_PORT_B = 1,\r
+ DIO_PORT_C = 2,\r
+ DIO_PORT_D = 3,\r
+ DIO_PORT_E = 4,\r
+ DIO_PORT_F = 5,\r
+ DIO_PORT_G = 6,\r
+ DIO_PORT_H = 7,\r
+ DIO_PORT_I = 8,\r
+ DIO_PORT_J = 9,\r
+ DIO_PORT_K = 10,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_LEDS_LED4 52\r
+#define DIO_CHANNEL_NAME_LEDS_LED5 53\r
+\r
+// Channel group\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_LED_PORT (DIO_PORT_D)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+\r
+ \r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_LEDS_LED4,\r
+ DIO_CHANNEL_NAME_LEDS_LED5,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_LED_PORT, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = {\r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = DIO_END_OF_LIST, \r
+ .mask = DIO_END_OF_LIST, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+\r
+MOD_USE += MCU PORT DIO \r
+\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Callout_template.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 24 11:07:49 CET 2011\r
+ */\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Cbk.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+#if defined(USE_NVM)\r
+#include "NvM.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+\r
+void EcuM_AL_DriverInitZero(void)\r
+{\r
+ Det_Init();\r
+ Det_Start();\r
+}\r
+\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void)\r
+{\r
+ return &EcuMConfig;\r
+}\r
+\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_MCU)\r
+ Mcu_Init(ConfigPtr->McuConfig);\r
+\r
+ // Set up default clock (Mcu_InitClock requires initRun==1)\r
+ // Ignoring return value\r
+ (void) Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+ // Preinitialize DEM\r
+ Dem_PreInit();\r
+#endif\r
+\r
+#if defined(USE_PORT)\r
+ // Setup Port\r
+ Port_Init(ConfigPtr->PortConfig);\r
+#endif\r
+\r
+\r
+#if defined(USE_GPT)\r
+ // Setup the GPT\r
+ Gpt_Init(ConfigPtr->GptConfig);\r
+#endif\r
+\r
+ // Setup watchdog\r
+ // TODO\r
+\r
+#if defined(USE_DMA)\r
+ // Setup DMA\r
+ Dma_Init(ConfigPtr->DmaConfig);\r
+#endif\r
+\r
+#if defined(USE_ADC)\r
+ // Setup ADC\r
+ Adc_Init(ConfigPtr->AdcConfig);\r
+#endif\r
+\r
+ // Setup ICU\r
+ // TODO\r
+\r
+ // Setup PWM\r
+#if defined(USE_PWM)\r
+ // Setup PWM\r
+ Pwm_Init(ConfigPtr->PwmConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_SPI)\r
+ // Setup SPI\r
+ Spi_Init(ConfigPtr->SpiConfig);\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+ // Setup EEP\r
+ Eep_Init(ConfigPtr->EEpConfig);\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+ // Setup Flash\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+#if defined(USE_FEE)\r
+ // Setup FEE\r
+ Fee_Init();\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+ // Setup EA\r
+ Ea_init();\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+ // Setup NVRAM Manager and start the read all job\r
+ NvM_Init();\r
+ NvM_ReadAll();\r
+#endif\r
+\r
+ // Setup CAN tranceiver\r
+ // TODO\r
+\r
+#if defined(USE_CAN)\r
+ // Setup Can driver\r
+ Can_Init(ConfigPtr->CanConfig);\r
+#endif\r
+\r
+#if defined(USE_CANIF)\r
+ // Setup CanIf\r
+ CanIf_Init(ConfigPtr->CanIfConfig);\r
+#endif\r
+\r
+#if defined(USE_CANTP)\r
+ // Setup CAN TP\r
+ CanTp_Init();\r
+#endif\r
+\r
+#if defined(USE_CANSM)\r
+ CanSM_Init(ConfigPtr->CanSMConfig);\r
+#endif\r
+\r
+ // Setup LIN\r
+ // TODO\r
+\r
+#if defined(USE_PDUR)\r
+ // Setup PDU Router\r
+ PduR_Init(ConfigPtr->PduRConfig);\r
+#endif\r
+\r
+#if defined(USE_CANNM)\r
+ // Setup Can Network Manager\r
+ CanNm_Init(ConfigPtr->CanNmConfig);\r
+#endif\r
+\r
+#if defined(USE_NM)\r
+ // Setup Network Management Interface\r
+ Nm_Init(ConfigPtr->NmConfig);\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+ // Setup COM layer\r
+ Com_Init(ConfigPtr->ComConfig);\r
+#endif\r
+\r
+#if defined(USE_DCM)\r
+ // Setup DCM\r
+ Dcm_Init();\r
+#endif\r
+\r
+#if defined(USE_IOHWAB)\r
+ // Setup IO hardware abstraction layer\r
+ IoHwAb_Init();\r
+#endif\r
+\r
+}\r
+\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_DEM)\r
+ // Setup DEM\r
+ Dem_Init();\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+ // Setup Communication Manager\r
+ ComM_Init(ConfigPtr->ComMConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_OnEnterRUN(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitPostRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnPrepShutdown(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoSleep(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffOne(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffTwo(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff(void)\r
+{\r
+\r
+}\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 24 11:07:49 CET 2011\r
+ */\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultShutdownMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,\r
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,\r
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)\r
+ .FlashConfig = FlsConfigSet,\r
+#endif\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Generated_Types.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 24 11:07:49 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultShutdownMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;\r
+ uint32 EcuMNvramReadAllTimeout;\r
+ uint32 EcuMNvramWriteAllTimeout;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_CANSM)\r
+ const CanSM_ConfigType* CanSMConfig;\r
+#endif\r
+#if defined(USE_NM)\r
+ const Nm_ConfigType* NmConfig;\r
+#endif\r
+#if defined(USE_CANNM)\r
+ const CanNm_ConfigType* CanNmConfig;\r
+#endif\r
+#if defined(USE_COMM)\r
+ const ComM_ConfigType* ComMConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)\r
+ const Fls_ConfigType* FlashConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 8000000UL,\r
+ .Pll1 = 1,\r
+ .Pll2 = 104,\r
+ .Pll3 = 5,\r
+ },\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 3,\r
+ .Pll2 = 83,\r
+ .Pll3 = 5,\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 2,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+
+#if !(((MCU_SW_MAJOR_VERSION == 2) && (MCU_SW_MINOR_VERSION == 0)) )
+#error "Mcu: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON \r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_CLOCKTYPE_EXT_REF_66MHZ = 1,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,2048);\r
+DECLARE_STACK(bTask10,2048);\r
+DECLARE_STACK(bTask100,2048);\r
+DECLARE_STACK(bTask25,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+ \r
+// File generated on Wed Jan 26 12:40:30 CET 2011\r
+// File generated by com.arccore.bswbuilder.modules.port.mpc5516\r
+\r
+#include "Port.h"\r
+#include "Port_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PORT_PCR_RESET, /* PCR 0 */\r
+ PORT_PCR_RESET, /* PCR 1 */\r
+ PORT_PCR_RESET, /* PCR 2 */\r
+ PORT_PCR_RESET, /* PCR 3 */\r
+ PORT_PCR_RESET, /* PCR 4 */\r
+ PORT_PCR_RESET, /* PCR 5 */\r
+ PORT_PCR_RESET, /* PCR 6 */\r
+ PORT_PCR_RESET, /* PCR 7 */\r
+ PORT_PCR_RESET, /* PCR 8 */\r
+ PORT_PCR_RESET, /* PCR 9 */\r
+ PORT_PCR_RESET, /* PCR 10 */\r
+ PORT_PCR_RESET, /* PCR 11 */\r
+ PORT_PCR_RESET, /* PCR 12 */\r
+ PORT_PCR_RESET, /* PCR 13 */\r
+ PORT_PCR_RESET, /* PCR 14 */\r
+ PORT_PCR_RESET, /* PCR 15 */\r
+ PORT_PCR_RESET, /* PCR 16 */\r
+ PORT_PCR_RESET, /* PCR 17 */\r
+ PORT_PCR_RESET, /* PCR 18 */\r
+ PORT_PCR_RESET, /* PCR 19 */\r
+ PORT_PCR_RESET, /* PCR 20 */\r
+ PORT_PCR_RESET, /* PCR 21 */\r
+ PORT_PCR_RESET, /* PCR 22 */\r
+ PORT_PCR_RESET, /* PCR 23 */\r
+ PORT_PCR_RESET, /* PCR 24 */\r
+ PORT_PCR_RESET, /* PCR 25 */\r
+ PORT_PCR_RESET, /* PCR 26 */\r
+ PORT_PCR_RESET, /* PCR 27 */\r
+ PORT_PCR_RESET, /* PCR 28 */\r
+ PORT_PCR_RESET, /* PCR 29 */\r
+ PORT_PCR_RESET, /* PCR 30 */\r
+ PORT_PCR_RESET, /* PCR 31 */\r
+ PORT_PCR_RESET, /* PCR 32 */\r
+ PORT_PCR_RESET, /* PCR 33 */\r
+ PORT_PCR_RESET, /* PCR 34 */\r
+ PORT_PCR_RESET, /* PCR 35 */\r
+ PORT_PCR_RESET, /* PCR 36 */\r
+ PORT_PCR_RESET, /* PCR 37 */\r
+ PORT_PCR_RESET, /* PCR 38 */\r
+ PORT_PCR_RESET, /* PCR 39 */\r
+ PORT_PCR_RESET, /* PCR 40 */\r
+ PORT_PCR_RESET, /* PCR 41 */\r
+ PORT_PCR_RESET, /* PCR 42 */\r
+ PORT_PCR_RESET, /* PCR 43 */\r
+ PORT_PCR_RESET, /* PCR 44 */\r
+ PORT_PCR_RESET, /* PCR 45 */\r
+ PORT_PCR_RESET, /* PCR 46 */\r
+ PORT_PCR_RESET, /* PCR 47 */\r
+ PORT_PCR_RESET, /* PCR 48 */\r
+ PORT_PCR_RESET, /* PCR 49 */\r
+ PORT_PCR_RESET, /* PCR 50 */\r
+ PORT_PCR_RESET, /* PCR 51 */\r
+ ( PORT_FUNC0 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 52 : PORT_PIN_MODE_DIO */\r
+ ( PORT_FUNC0 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 53 : PORT_PIN_MODE_DIO */\r
+ PORT_PCR_RESET, /* PCR 54 */\r
+ PORT_PCR_RESET, /* PCR 55 */\r
+ PORT_PCR_RESET, /* PCR 56 */\r
+ PORT_PCR_RESET, /* PCR 57 */\r
+ PORT_PCR_RESET, /* PCR 58 */\r
+ PORT_PCR_RESET, /* PCR 59 */\r
+ PORT_PCR_RESET, /* PCR 60 */\r
+ PORT_PCR_RESET, /* PCR 61 */\r
+ PORT_PCR_RESET, /* PCR 62 */\r
+ PORT_PCR_RESET, /* PCR 63 */\r
+ PORT_PCR_RESET, /* PCR 64 */\r
+ PORT_PCR_RESET, /* PCR 65 */\r
+ PORT_PCR_RESET, /* PCR 66 */\r
+ PORT_PCR_RESET, /* PCR 67 */\r
+ PORT_PCR_RESET, /* PCR 68 */\r
+ PORT_PCR_RESET, /* PCR 69 */\r
+ PORT_PCR_RESET, /* PCR 70 */\r
+ PORT_PCR_RESET, /* PCR 71 */\r
+ PORT_PCR_RESET, /* PCR 72 */\r
+ PORT_PCR_RESET, /* PCR 73 */\r
+ PORT_PCR_RESET, /* PCR 74 */\r
+ PORT_PCR_RESET, /* PCR 75 */\r
+ PORT_PCR_RESET, /* PCR 76 */\r
+ PORT_PCR_RESET, /* PCR 77 */\r
+ PORT_PCR_RESET, /* PCR 78 */\r
+ PORT_PCR_RESET, /* PCR 79 */\r
+ PORT_PCR_RESET, /* PCR 80 */\r
+ PORT_PCR_RESET, /* PCR 81 */\r
+ PORT_PCR_RESET, /* PCR 82 */\r
+ PORT_PCR_RESET, /* PCR 83 */\r
+ PORT_PCR_RESET, /* PCR 84 */\r
+ PORT_PCR_RESET, /* PCR 85 */\r
+ PORT_PCR_RESET, /* PCR 86 */\r
+ PORT_PCR_RESET, /* PCR 87 */\r
+ PORT_PCR_RESET, /* PCR 88 */\r
+ PORT_PCR_RESET, /* PCR 89 */\r
+ PORT_PCR_RESET, /* PCR 90 */\r
+ PORT_PCR_RESET, /* PCR 91 */\r
+ PORT_PCR_RESET, /* PCR 92 */\r
+ PORT_PCR_RESET, /* PCR 93 */\r
+ PORT_PCR_RESET, /* PCR 94 */\r
+ PORT_PCR_RESET, /* PCR 95 */\r
+ PORT_PCR_RESET, /* PCR 96 */\r
+ PORT_PCR_RESET, /* PCR 97 */\r
+ PORT_PCR_RESET, /* PCR 98 */\r
+ PORT_PCR_RESET, /* PCR 99 */\r
+ PORT_PCR_RESET, /* PCR 100 */\r
+ PORT_PCR_RESET, /* PCR 101 */\r
+ PORT_PCR_RESET, /* PCR 102 */\r
+ PORT_PCR_RESET, /* PCR 103 */\r
+ PORT_PCR_RESET, /* PCR 104 */\r
+ PORT_PCR_RESET, /* PCR 105 */\r
+ PORT_PCR_RESET, /* PCR 106 */\r
+ PORT_PCR_RESET, /* PCR 107 */\r
+ PORT_PCR_RESET, /* PCR 108 */\r
+ PORT_PCR_RESET, /* PCR 109 */\r
+ PORT_PCR_RESET, /* PCR 110 */\r
+ PORT_PCR_RESET, /* PCR 111 */\r
+ PORT_PCR_RESET, /* PCR 112 */\r
+ PORT_PCR_RESET, /* PCR 113 */\r
+ PORT_PCR_RESET, /* PCR 114 */\r
+ PORT_PCR_RESET, /* PCR 115 */\r
+ PORT_PCR_RESET, /* PCR 116 */\r
+ PORT_PCR_RESET, /* PCR 117 */\r
+ PORT_PCR_RESET, /* PCR 118 */\r
+ PORT_PCR_RESET, /* PCR 119 */\r
+ PORT_PCR_RESET, /* PCR 120 */\r
+ PORT_PCR_RESET, /* PCR 121 */\r
+ PORT_PCR_RESET, /* PCR 122 */\r
+ PORT_PCR_RESET, /* PCR 123 */\r
+ PORT_PCR_RESET, /* PCR 124 */\r
+ PORT_PCR_RESET, /* PCR 125 */\r
+ PORT_PCR_RESET, /* PCR 126 */\r
+ PORT_PCR_RESET, /* PCR 127 */\r
+ PORT_PCR_RESET, /* PCR 128 */\r
+ PORT_PCR_RESET, /* PCR 129 */\r
+ PORT_PCR_RESET, /* PCR 130 */\r
+ PORT_PCR_RESET, /* PCR 131 */\r
+ PORT_PCR_RESET, /* PCR 132 */\r
+ PORT_PCR_RESET, /* PCR 133 */\r
+ PORT_PCR_RESET, /* PCR 134 */\r
+ PORT_PCR_RESET, /* PCR 135 */\r
+ PORT_PCR_RESET, /* PCR 136 */\r
+ PORT_PCR_RESET, /* PCR 137 */\r
+ PORT_PCR_RESET, /* PCR 138 */\r
+ PORT_PCR_RESET, /* PCR 139 */\r
+ PORT_PCR_RESET, /* PCR 140 */\r
+ PORT_PCR_RESET, /* PCR 141 */\r
+ PORT_PCR_RESET, /* PCR 142 */\r
+ PORT_PCR_RESET, /* PCR 143 */\r
+ PORT_PCR_RESET, /* PCR 144 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ PORT_GPDO_RESET, /* GPDO 0 */\r
+ PORT_GPDO_RESET, /* GPDO 1 */\r
+ PORT_GPDO_RESET, /* GPDO 2 */\r
+ PORT_GPDO_RESET, /* GPDO 3 */\r
+ PORT_GPDO_RESET, /* GPDO 4 */\r
+ PORT_GPDO_RESET, /* GPDO 5 */\r
+ PORT_GPDO_RESET, /* GPDO 6 */\r
+ PORT_GPDO_RESET, /* GPDO 7 */\r
+ PORT_GPDO_RESET, /* GPDO 8 */\r
+ PORT_GPDO_RESET, /* GPDO 9 */\r
+ PORT_GPDO_RESET, /* GPDO 10 */\r
+ PORT_GPDO_RESET, /* GPDO 11 */\r
+ PORT_GPDO_RESET, /* GPDO 12 */\r
+ PORT_GPDO_RESET, /* GPDO 13 */\r
+ PORT_GPDO_RESET, /* GPDO 14 */\r
+ PORT_GPDO_RESET, /* GPDO 15 */\r
+ PORT_GPDO_RESET, /* GPDO 16 */\r
+ PORT_GPDO_RESET, /* GPDO 17 */\r
+ PORT_GPDO_RESET, /* GPDO 18 */\r
+ PORT_GPDO_RESET, /* GPDO 19 */\r
+ PORT_GPDO_RESET, /* GPDO 20 */\r
+ PORT_GPDO_RESET, /* GPDO 21 */\r
+ PORT_GPDO_RESET, /* GPDO 22 */\r
+ PORT_GPDO_RESET, /* GPDO 23 */\r
+ PORT_GPDO_RESET, /* GPDO 24 */\r
+ PORT_GPDO_RESET, /* GPDO 25 */\r
+ PORT_GPDO_RESET, /* GPDO 26 */\r
+ PORT_GPDO_RESET, /* GPDO 27 */\r
+ PORT_GPDO_RESET, /* GPDO 28 */\r
+ PORT_GPDO_RESET, /* GPDO 29 */\r
+ PORT_GPDO_RESET, /* GPDO 30 */\r
+ PORT_GPDO_RESET, /* GPDO 31 */\r
+ PORT_GPDO_RESET, /* GPDO 32 */\r
+ PORT_GPDO_RESET, /* GPDO 33 */\r
+ PORT_GPDO_RESET, /* GPDO 34 */\r
+ PORT_GPDO_RESET, /* GPDO 35 */\r
+ PORT_GPDO_RESET, /* GPDO 36 */\r
+ PORT_GPDO_RESET, /* GPDO 37 */\r
+ PORT_GPDO_RESET, /* GPDO 38 */\r
+ PORT_GPDO_RESET, /* GPDO 39 */\r
+ PORT_GPDO_RESET, /* GPDO 40 */\r
+ PORT_GPDO_RESET, /* GPDO 41 */\r
+ PORT_GPDO_RESET, /* GPDO 42 */\r
+ PORT_GPDO_RESET, /* GPDO 43 */\r
+ PORT_GPDO_RESET, /* GPDO 44 */\r
+ PORT_GPDO_RESET, /* GPDO 45 */\r
+ PORT_GPDO_RESET, /* GPDO 46 */\r
+ PORT_GPDO_RESET, /* GPDO 47 */\r
+ PORT_GPDO_RESET, /* GPDO 48 */\r
+ PORT_GPDO_RESET, /* GPDO 49 */\r
+ PORT_GPDO_RESET, /* GPDO 50 */\r
+ PORT_GPDO_RESET, /* GPDO 51 */\r
+ PORT_GPDO_RESET, /* GPDO 52 */\r
+ PORT_GPDO_RESET, /* GPDO 53 */\r
+ PORT_GPDO_RESET, /* GPDO 54 */\r
+ PORT_GPDO_RESET, /* GPDO 55 */\r
+ PORT_GPDO_RESET, /* GPDO 56 */\r
+ PORT_GPDO_RESET, /* GPDO 57 */\r
+ PORT_GPDO_RESET, /* GPDO 58 */\r
+ PORT_GPDO_RESET, /* GPDO 59 */\r
+ PORT_GPDO_RESET, /* GPDO 60 */\r
+ PORT_GPDO_RESET, /* GPDO 61 */\r
+ PORT_GPDO_RESET, /* GPDO 62 */\r
+ PORT_GPDO_RESET, /* GPDO 63 */\r
+ PORT_GPDO_RESET, /* GPDO 64 */\r
+ PORT_GPDO_RESET, /* GPDO 65 */\r
+ PORT_GPDO_RESET, /* GPDO 66 */\r
+ PORT_GPDO_RESET, /* GPDO 67 */\r
+ PORT_GPDO_RESET, /* GPDO 68 */\r
+ PORT_GPDO_RESET, /* GPDO 69 */\r
+ PORT_GPDO_RESET, /* GPDO 70 */\r
+ PORT_GPDO_RESET, /* GPDO 71 */\r
+ PORT_GPDO_RESET, /* GPDO 72 */\r
+ PORT_GPDO_RESET, /* GPDO 73 */\r
+ PORT_GPDO_RESET, /* GPDO 74 */\r
+ PORT_GPDO_RESET, /* GPDO 75 */\r
+ PORT_GPDO_RESET, /* GPDO 76 */\r
+ PORT_GPDO_RESET, /* GPDO 77 */\r
+ PORT_GPDO_RESET, /* GPDO 78 */\r
+ PORT_GPDO_RESET, /* GPDO 79 */\r
+ PORT_GPDO_RESET, /* GPDO 80 */\r
+ PORT_GPDO_RESET, /* GPDO 81 */\r
+ PORT_GPDO_RESET, /* GPDO 82 */\r
+ PORT_GPDO_RESET, /* GPDO 83 */\r
+ PORT_GPDO_RESET, /* GPDO 84 */\r
+ PORT_GPDO_RESET, /* GPDO 85 */\r
+ PORT_GPDO_RESET, /* GPDO 86 */\r
+ PORT_GPDO_RESET, /* GPDO 87 */\r
+ PORT_GPDO_RESET, /* GPDO 88 */\r
+ PORT_GPDO_RESET, /* GPDO 89 */\r
+ PORT_GPDO_RESET, /* GPDO 90 */\r
+ PORT_GPDO_RESET, /* GPDO 91 */\r
+ PORT_GPDO_RESET, /* GPDO 92 */\r
+ PORT_GPDO_RESET, /* GPDO 93 */\r
+ PORT_GPDO_RESET, /* GPDO 94 */\r
+ PORT_GPDO_RESET, /* GPDO 95 */\r
+ PORT_GPDO_RESET, /* GPDO 96 */\r
+ PORT_GPDO_RESET, /* GPDO 97 */\r
+ PORT_GPDO_RESET, /* GPDO 98 */\r
+ PORT_GPDO_RESET, /* GPDO 99 */\r
+ PORT_GPDO_RESET, /* GPDO 100 */\r
+ PORT_GPDO_RESET, /* GPDO 101 */\r
+ PORT_GPDO_RESET, /* GPDO 102 */\r
+ PORT_GPDO_RESET, /* GPDO 103 */\r
+ PORT_GPDO_RESET, /* GPDO 104 */\r
+ PORT_GPDO_RESET, /* GPDO 105 */\r
+ PORT_GPDO_RESET, /* GPDO 106 */\r
+ PORT_GPDO_RESET, /* GPDO 107 */\r
+ PORT_GPDO_RESET, /* GPDO 108 */\r
+ PORT_GPDO_RESET, /* GPDO 109 */\r
+ PORT_GPDO_RESET, /* GPDO 110 */\r
+ PORT_GPDO_RESET, /* GPDO 111 */\r
+ PORT_GPDO_RESET, /* GPDO 112 */\r
+ PORT_GPDO_RESET, /* GPDO 113 */\r
+ PORT_GPDO_RESET, /* GPDO 114 */\r
+ PORT_GPDO_RESET, /* GPDO 115 */\r
+ PORT_GPDO_RESET, /* GPDO 116 */\r
+ PORT_GPDO_RESET, /* GPDO 117 */\r
+ PORT_GPDO_RESET, /* GPDO 118 */\r
+ PORT_GPDO_RESET, /* GPDO 119 */\r
+ PORT_GPDO_RESET, /* GPDO 120 */\r
+ PORT_GPDO_RESET, /* GPDO 121 */\r
+ PORT_GPDO_RESET, /* GPDO 122 */\r
+ PORT_GPDO_RESET, /* GPDO 123 */\r
+ PORT_GPDO_RESET, /* GPDO 124 */\r
+ PORT_GPDO_RESET, /* GPDO 125 */\r
+ PORT_GPDO_RESET, /* GPDO 126 */\r
+ PORT_GPDO_RESET, /* GPDO 127 */\r
+ PORT_GPDO_RESET, /* GPDO 128 */\r
+ PORT_GPDO_RESET, /* GPDO 129 */\r
+ PORT_GPDO_RESET, /* GPDO 130 */\r
+ PORT_GPDO_RESET, /* GPDO 131 */\r
+ PORT_GPDO_RESET, /* GPDO 132 */\r
+ PORT_GPDO_RESET, /* GPDO 133 */\r
+ PORT_GPDO_RESET, /* GPDO 134 */\r
+ PORT_GPDO_RESET, /* GPDO 135 */\r
+ PORT_GPDO_RESET, /* GPDO 136 */\r
+ PORT_GPDO_RESET, /* GPDO 137 */\r
+ PORT_GPDO_RESET, /* GPDO 138 */\r
+ PORT_GPDO_RESET, /* GPDO 139 */\r
+ PORT_GPDO_RESET, /* GPDO 140 */\r
+ PORT_GPDO_RESET, /* GPDO 141 */\r
+ PORT_GPDO_RESET, /* GPDO 142 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:40:30 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
+\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_IO (0)\r
+#define PORT_FUNC0 (0)\r
+#define PORT_FUNC1 (PORT_BIT5)\r
+#define PORT_FUNC2 (PORT_BIT4)\r
+#define PORT_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+#define PORT_FUNC4 (PORT_BIT3)\r
+\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_GPDO_RESET (0)\r
+\r
+#define PORT_GPDO_HIGH (1)\r
+\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_PD4 52 \r
+#define PORT_PIN_NAME_PD5 53 \r
+\r
+#endif /* PORT_CFG_H_ */\r
--- /dev/null
+/*\r
+ * Configuration of module Det (Det_cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+
+#if !(((DET_SW_MAJOR_VERSION == 1) && (DET_SW_MINOR_VERSION == 0)) )
+#error "Det: Configuration file version differs from BSW version."
+#endif
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H \r
+\r
+#define DET_ENABLE_CALLBACKS STD_OFF // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+#define DET_DEINIT_API STD_OFF // Enable/Disable the Det_DeInit function\r
+#define DET_RAMLOG_SIZE (16) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /* DET_CFG_H */\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+
+#if !(((DIO_SW_MAJOR_VERSION == 1) && (DIO_SW_MINOR_VERSION == 0)) )
+#error "Dio: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ DIO_MPC5567_GENERIC_PORT = 0,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_LED_K2 125\r
+\r
+// Channel group\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_DioPort_1 (DIO_MPC5567_GENERIC_PORT)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+\r
+ \r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_LED_K2,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_DioPort_1, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = {\r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = DIO_END_OF_LIST, \r
+ .mask = DIO_END_OF_LIST, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+\r
+MOD_USE += MCU PORT DIO \r
+\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Callout_template.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:14:21 CET 2011\r
+ */\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Cbk.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+#if defined(USE_NVM)\r
+#include "NvM.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+\r
+void EcuM_AL_DriverInitZero(void)\r
+{\r
+ Det_Init();\r
+ Det_Start();\r
+}\r
+\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void)\r
+{\r
+ return &EcuMConfig;\r
+}\r
+\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_MCU)\r
+ Mcu_Init(ConfigPtr->McuConfig);\r
+\r
+ // Set up default clock (Mcu_InitClock requires initRun==1)\r
+ // Ignoring return value\r
+ (void) Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+ // Preinitialize DEM\r
+ Dem_PreInit();\r
+#endif\r
+\r
+#if defined(USE_PORT)\r
+ // Setup Port\r
+ Port_Init(ConfigPtr->PortConfig);\r
+#endif\r
+\r
+\r
+#if defined(USE_GPT)\r
+ // Setup the GPT\r
+ Gpt_Init(ConfigPtr->GptConfig);\r
+#endif\r
+\r
+ // Setup watchdog\r
+ // TODO\r
+\r
+#if defined(USE_DMA)\r
+ // Setup DMA\r
+ Dma_Init(ConfigPtr->DmaConfig);\r
+#endif\r
+\r
+#if defined(USE_ADC)\r
+ // Setup ADC\r
+ Adc_Init(ConfigPtr->AdcConfig);\r
+#endif\r
+\r
+ // Setup ICU\r
+ // TODO\r
+\r
+ // Setup PWM\r
+#if defined(USE_PWM)\r
+ // Setup PWM\r
+ Pwm_Init(ConfigPtr->PwmConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_SPI)\r
+ // Setup SPI\r
+ Spi_Init(ConfigPtr->SpiConfig);\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+ // Setup EEP\r
+ Eep_Init(ConfigPtr->EEpConfig);\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+ // Setup Flash\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+#if defined(USE_FEE)\r
+ // Setup FEE\r
+ Fee_Init();\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+ // Setup EA\r
+ Ea_init();\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+ // Setup NVRAM Manager and start the read all job\r
+ NvM_Init();\r
+ NvM_ReadAll();\r
+#endif\r
+\r
+ // Setup CAN tranceiver\r
+ // TODO\r
+\r
+#if defined(USE_CAN)\r
+ // Setup Can driver\r
+ Can_Init(ConfigPtr->CanConfig);\r
+#endif\r
+\r
+#if defined(USE_CANIF)\r
+ // Setup CanIf\r
+ CanIf_Init(ConfigPtr->CanIfConfig);\r
+#endif\r
+\r
+#if defined(USE_CANTP)\r
+ // Setup CAN TP\r
+ CanTp_Init();\r
+#endif\r
+\r
+#if defined(USE_CANSM)\r
+ CanSM_Init(ConfigPtr->CanSMConfig);\r
+#endif\r
+\r
+ // Setup LIN\r
+ // TODO\r
+\r
+#if defined(USE_PDUR)\r
+ // Setup PDU Router\r
+ PduR_Init(ConfigPtr->PduRConfig);\r
+#endif\r
+\r
+#if defined(USE_CANNM)\r
+ // Setup Can Network Manager\r
+ CanNm_Init(ConfigPtr->CanNmConfig);\r
+#endif\r
+\r
+#if defined(USE_NM)\r
+ // Setup Network Management Interface\r
+ Nm_Init(ConfigPtr->NmConfig);\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+ // Setup COM layer\r
+ Com_Init(ConfigPtr->ComConfig);\r
+#endif\r
+\r
+#if defined(USE_DCM)\r
+ // Setup DCM\r
+ Dcm_Init();\r
+#endif\r
+\r
+#if defined(USE_IOHWAB)\r
+ // Setup IO hardware abstraction layer\r
+ IoHwAb_Init();\r
+#endif\r
+\r
+}\r
+\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_DEM)\r
+ // Setup DEM\r
+ Dem_Init();\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+ // Setup Communication Manager\r
+ ComM_Init(ConfigPtr->ComMConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_OnEnterRUN(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitPostRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnPrepShutdown(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoSleep(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffOne(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffTwo(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff(void)\r
+{\r
+\r
+}\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:14:21 CET 2011\r
+ */\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultShutdownMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,\r
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,\r
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)\r
+ .FlashConfig = FlsConfigSet,\r
+#endif\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Generated_Types.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:14:21 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultShutdownMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;\r
+ uint32 EcuMNvramReadAllTimeout;\r
+ uint32 EcuMNvramWriteAllTimeout;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_CANSM)\r
+ const CanSM_ConfigType* CanSMConfig;\r
+#endif\r
+#if defined(USE_NM)\r
+ const Nm_ConfigType* NmConfig;\r
+#endif\r
+#if defined(USE_CANNM)\r
+ const CanNm_ConfigType* CanNmConfig;\r
+#endif\r
+#if defined(USE_COMM)\r
+ const ComM_ConfigType* ComMConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)\r
+ const Fls_ConfigType* FlashConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 16000000UL,\r
+ .Pll1 = 2,\r
+ .Pll2 = 11,\r
+ .Pll3 = 0,\r
+ },\r
+};\r
+\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+
+#if !(((MCU_SW_MAJOR_VERSION == 2) && (MCU_SW_MINOR_VERSION == 0)) )
+#error "Mcu: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "mpc55xx.h"\r
+\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON \r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,2048);\r
+DECLARE_STACK(bTask10,2048);\r
+DECLARE_STACK(bTask100,2048);\r
+DECLARE_STACK(bTask25,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:04 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+ \r
+// File generated on Wed Jan 26 14:18:05 CET 2011\r
+// File generated by com.arccore.bswbuilder.modules.port.mpc5567\r
+\r
+#include "Port.h"\r
+#include "Port_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PORT_PCR_RESET, /* PCR 0 */\r
+ PORT_PCR_RESET, /* PCR 1 */\r
+ PORT_PCR_RESET, /* PCR 2 */\r
+ PORT_PCR_RESET, /* PCR 3 */\r
+ PORT_PCR_RESET, /* PCR 4 */\r
+ PORT_PCR_RESET, /* PCR 5 */\r
+ PORT_PCR_RESET, /* PCR 6 */\r
+ PORT_PCR_RESET, /* PCR 7 */\r
+ PORT_PCR_RESET, /* PCR 8 */\r
+ PORT_PCR_RESET, /* PCR 9 */\r
+ PORT_PCR_RESET, /* PCR 10 */\r
+ PORT_PCR_RESET, /* PCR 11 */\r
+ PORT_PCR_RESET, /* PCR 12 */\r
+ PORT_PCR_RESET, /* PCR 13 */\r
+ PORT_PCR_RESET, /* PCR 14 */\r
+ PORT_PCR_RESET, /* PCR 15 */\r
+ PORT_PCR_RESET, /* PCR 16 */\r
+ PORT_PCR_RESET, /* PCR 17 */\r
+ PORT_PCR_RESET, /* PCR 18 */\r
+ PORT_PCR_RESET, /* PCR 19 */\r
+ PORT_PCR_RESET, /* PCR 20 */\r
+ PORT_PCR_RESET, /* PCR 21 */\r
+ PORT_PCR_RESET, /* PCR 22 */\r
+ PORT_PCR_RESET, /* PCR 23 */\r
+ PORT_PCR_RESET, /* PCR 24 */\r
+ PORT_PCR_RESET, /* PCR 25 */\r
+ PORT_PCR_RESET, /* PCR 26 */\r
+ PORT_PCR_RESET, /* PCR 27 */\r
+ PORT_PCR_RESET, /* PCR 28 */\r
+ PORT_PCR_RESET, /* PCR 29 */\r
+ PORT_PCR_RESET, /* PCR 30 */\r
+ PORT_PCR_RESET, /* PCR 31 */\r
+ PORT_PCR_RESET, /* PCR 32 */\r
+ PORT_PCR_RESET, /* PCR 33 */\r
+ PORT_PCR_RESET, /* PCR 34 */\r
+ PORT_PCR_RESET, /* PCR 35 */\r
+ PORT_PCR_RESET, /* PCR 36 */\r
+ PORT_PCR_RESET, /* PCR 37 */\r
+ PORT_PCR_RESET, /* PCR 38 */\r
+ PORT_PCR_RESET, /* PCR 39 */\r
+ PORT_PCR_RESET, /* PCR 40 */\r
+ PORT_PCR_RESET, /* PCR 41 */\r
+ PORT_PCR_RESET, /* PCR 42 */\r
+ PORT_PCR_RESET, /* PCR 43 */\r
+ PORT_PCR_RESET, /* PCR 44 */\r
+ PORT_PCR_RESET, /* PCR 45 */\r
+ PORT_PCR_RESET, /* PCR 46 */\r
+ PORT_PCR_RESET, /* PCR 47 */\r
+ PORT_PCR_RESET, /* PCR 48 */\r
+ PORT_PCR_RESET, /* PCR 49 */\r
+ PORT_PCR_RESET, /* PCR 50 */\r
+ PORT_PCR_RESET, /* PCR 51 */\r
+ PORT_PCR_RESET, /* PCR 52 */\r
+ PORT_PCR_RESET, /* PCR 53 */\r
+ PORT_PCR_RESET, /* PCR 54 */\r
+ PORT_PCR_RESET, /* PCR 55 */\r
+ PORT_PCR_RESET, /* PCR 56 */\r
+ PORT_PCR_RESET, /* PCR 57 */\r
+ PORT_PCR_RESET, /* PCR 58 */\r
+ PORT_PCR_RESET, /* PCR 59 */\r
+ PORT_PCR_RESET, /* PCR 60 */\r
+ PORT_PCR_RESET, /* PCR 61 */\r
+ PORT_PCR_RESET, /* PCR 62 */\r
+ PORT_PCR_RESET, /* PCR 63 */\r
+ PORT_PCR_RESET, /* PCR 64 */\r
+ PORT_PCR_RESET, /* PCR 65 */\r
+ PORT_PCR_RESET, /* PCR 66 */\r
+ PORT_PCR_RESET, /* PCR 67 */\r
+ PORT_PCR_RESET, /* PCR 68 */\r
+ PORT_PCR_RESET, /* PCR 69 */\r
+ PORT_PCR_RESET, /* PCR 70 */\r
+ PORT_PCR_RESET, /* PCR 71 */\r
+ PORT_PCR_RESET, /* PCR 72 */\r
+ PORT_PCR_RESET, /* PCR 73 */\r
+ PORT_PCR_RESET, /* PCR 74 */\r
+ PORT_PCR_RESET, /* PCR 75 */\r
+ PORT_PCR_RESET, /* PCR 76 */\r
+ PORT_PCR_RESET, /* PCR 77 */\r
+ PORT_PCR_RESET, /* PCR 78 */\r
+ PORT_PCR_RESET, /* PCR 79 */\r
+ PORT_PCR_RESET, /* PCR 80 */\r
+ PORT_PCR_RESET, /* PCR 81 */\r
+ PORT_PCR_RESET, /* PCR 82 */\r
+ PORT_PCR_RESET, /* PCR 83 */\r
+ PORT_PCR_RESET, /* PCR 84 */\r
+ PORT_PCR_RESET, /* PCR 85 */\r
+ PORT_PCR_RESET, /* PCR 86 */\r
+ PORT_PCR_RESET, /* PCR 87 */\r
+ PORT_PCR_RESET, /* PCR 88 */\r
+ PORT_PCR_RESET, /* PCR 89 */\r
+ PORT_PCR_RESET, /* PCR 90 */\r
+ PORT_PCR_RESET, /* PCR 91 */\r
+ PORT_PCR_RESET, /* PCR 92 */\r
+ PORT_PCR_RESET, /* PCR 93 */\r
+ PORT_PCR_RESET, /* PCR 94 */\r
+ PORT_PCR_RESET, /* PCR 95 */\r
+ PORT_PCR_RESET, /* PCR 96 */\r
+ PORT_PCR_RESET, /* PCR 97 */\r
+ PORT_PCR_RESET, /* PCR 98 */\r
+ PORT_PCR_RESET, /* PCR 99 */\r
+ PORT_PCR_RESET, /* PCR 100 */\r
+ PORT_PCR_RESET, /* PCR 101 */\r
+ PORT_PCR_RESET, /* PCR 102 */\r
+ PORT_PCR_RESET, /* PCR 103 */\r
+ PORT_PCR_RESET, /* PCR 104 */\r
+ PORT_PCR_RESET, /* PCR 105 */\r
+ PORT_PCR_RESET, /* PCR 106 */\r
+ PORT_PCR_RESET, /* PCR 107 */\r
+ PORT_PCR_RESET, /* PCR 108 */\r
+ PORT_PCR_RESET, /* PCR 109 */\r
+ PORT_PCR_RESET, /* PCR 110 */\r
+ PORT_PCR_RESET, /* PCR 111 */\r
+ PORT_PCR_RESET, /* PCR 112 */\r
+ PORT_PCR_RESET, /* PCR 113 */\r
+ PORT_PCR_RESET, /* PCR 114 */\r
+ PORT_PCR_RESET, /* PCR 115 */\r
+ PORT_PCR_RESET, /* PCR 116 */\r
+ PORT_PCR_RESET, /* PCR 117 */\r
+ PORT_PCR_RESET, /* PCR 118 */\r
+ PORT_PCR_RESET, /* PCR 119 */\r
+ PORT_PCR_RESET, /* PCR 120 */\r
+ PORT_PCR_RESET, /* PCR 121 */\r
+ PORT_PCR_RESET, /* PCR 122 */\r
+ PORT_PCR_RESET, /* PCR 123 */\r
+ PORT_PCR_RESET, /* PCR 124 */\r
+ ( PORT_FUNC0 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 125 : PORT_PIN_MODE_DIO */\r
+ PORT_PCR_RESET, /* PCR 126 */\r
+ PORT_PCR_RESET, /* PCR 127 */\r
+ PORT_PCR_RESET, /* PCR 128 */\r
+ PORT_PCR_RESET, /* PCR 129 */\r
+ PORT_PCR_RESET, /* PCR 130 */\r
+ PORT_PCR_RESET, /* PCR 131 */\r
+ PORT_PCR_RESET, /* PCR 132 */\r
+ PORT_PCR_RESET, /* PCR 133 */\r
+ PORT_PCR_RESET, /* PCR 134 */\r
+ PORT_PCR_RESET, /* PCR 135 */\r
+ PORT_PCR_RESET, /* PCR 136 */\r
+ PORT_PCR_RESET, /* PCR 137 */\r
+ PORT_PCR_RESET, /* PCR 138 */\r
+ PORT_PCR_RESET, /* PCR 139 */\r
+ PORT_PCR_RESET, /* PCR 140 */\r
+ PORT_PCR_RESET, /* PCR 141 */\r
+ PORT_PCR_RESET, /* PCR 142 */\r
+ PORT_PCR_RESET, /* PCR 143 */\r
+ PORT_PCR_RESET, /* PCR 144 */\r
+ PORT_PCR_RESET, /* PCR 145 */\r
+ PORT_PCR_RESET, /* PCR 146 */\r
+ PORT_PCR_RESET, /* PCR 147 */\r
+ PORT_PCR_RESET, /* PCR 148 */\r
+ PORT_PCR_RESET, /* PCR 149 */\r
+ PORT_PCR_RESET, /* PCR 150 */\r
+ PORT_PCR_RESET, /* PCR 151 */\r
+ PORT_PCR_RESET, /* PCR 152 */\r
+ PORT_PCR_RESET, /* PCR 153 */\r
+ PORT_PCR_RESET, /* PCR 154 */\r
+ PORT_PCR_RESET, /* PCR 155 */\r
+ PORT_PCR_RESET, /* PCR 156 */\r
+ PORT_PCR_RESET, /* PCR 157 */\r
+ PORT_PCR_RESET, /* PCR 158 */\r
+ PORT_PCR_RESET, /* PCR 159 */\r
+ PORT_PCR_RESET, /* PCR 160 */\r
+ PORT_PCR_RESET, /* PCR 161 */\r
+ PORT_PCR_RESET, /* PCR 162 */\r
+ PORT_PCR_RESET, /* PCR 163 */\r
+ PORT_PCR_RESET, /* PCR 164 */\r
+ PORT_PCR_RESET, /* PCR 165 */\r
+ PORT_PCR_RESET, /* PCR 166 */\r
+ PORT_PCR_RESET, /* PCR 167 */\r
+ PORT_PCR_RESET, /* PCR 168 */\r
+ PORT_PCR_RESET, /* PCR 169 */\r
+ PORT_PCR_RESET, /* PCR 170 */\r
+ PORT_PCR_RESET, /* PCR 171 */\r
+ PORT_PCR_RESET, /* PCR 172 */\r
+ PORT_PCR_RESET, /* PCR 173 */\r
+ PORT_PCR_RESET, /* PCR 174 */\r
+ PORT_PCR_RESET, /* PCR 175 */\r
+ PORT_PCR_RESET, /* PCR 176 */\r
+ PORT_PCR_RESET, /* PCR 177 */\r
+ PORT_PCR_RESET, /* PCR 178 */\r
+ PORT_PCR_RESET, /* PCR 179 */\r
+ PORT_PCR_RESET, /* PCR 180 */\r
+ PORT_PCR_RESET, /* PCR 181 */\r
+ PORT_PCR_RESET, /* PCR 182 */\r
+ PORT_PCR_RESET, /* PCR 183 */\r
+ PORT_PCR_RESET, /* PCR 184 */\r
+ PORT_PCR_RESET, /* PCR 185 */\r
+ PORT_PCR_RESET, /* PCR 186 */\r
+ PORT_PCR_RESET, /* PCR 187 */\r
+ PORT_PCR_RESET, /* PCR 188 */\r
+ PORT_PCR_RESET, /* PCR 189 */\r
+ PORT_PCR_RESET, /* PCR 190 */\r
+ PORT_PCR_RESET, /* PCR 191 */\r
+ PORT_PCR_RESET, /* PCR 192 */\r
+ PORT_PCR_RESET, /* PCR 193 */\r
+ PORT_PCR_RESET, /* PCR 194 */\r
+ PORT_PCR_RESET, /* PCR 195 */\r
+ PORT_PCR_RESET, /* PCR 196 */\r
+ PORT_PCR_RESET, /* PCR 197 */\r
+ PORT_PCR_RESET, /* PCR 198 */\r
+ PORT_PCR_RESET, /* PCR 199 */\r
+ PORT_PCR_RESET, /* PCR 200 */\r
+ PORT_PCR_RESET, /* PCR 201 */\r
+ PORT_PCR_RESET, /* PCR 202 */\r
+ PORT_PCR_RESET, /* PCR 203 */\r
+ PORT_PCR_RESET, /* PCR 204 */\r
+ PORT_PCR_RESET, /* PCR 205 */\r
+ PORT_PCR_RESET, /* PCR 206 */\r
+ PORT_PCR_RESET, /* PCR 207 */\r
+ PORT_PCR_RESET, /* PCR 208 */\r
+ PORT_PCR_RESET, /* PCR 209 */\r
+ PORT_PCR_RESET, /* PCR 210 */\r
+ PORT_PCR_RESET, /* PCR 211 */\r
+ PORT_PCR_RESET, /* PCR 212 */\r
+ PORT_PCR_RESET, /* PCR 213 */\r
+ PORT_PCR_RESET, /* PCR 214 */\r
+ PORT_PCR_RESET, /* PCR 215 */\r
+ PORT_PCR_RESET, /* PCR 216 */\r
+ PORT_PCR_RESET, /* PCR 217 */\r
+ PORT_PCR_RESET, /* PCR 218 */\r
+ PORT_PCR_RESET, /* PCR 219 */\r
+ PORT_PCR_RESET, /* PCR 220 */\r
+ PORT_PCR_RESET, /* PCR 221 */\r
+ PORT_PCR_RESET, /* PCR 222 */\r
+ PORT_PCR_RESET, /* PCR 223 */\r
+ PORT_PCR_RESET, /* PCR 224 */\r
+ PORT_PCR_RESET, /* PCR 225 */\r
+ PORT_PCR_RESET, /* PCR 226 */\r
+ PORT_PCR_RESET, /* PCR 227 */\r
+ PORT_PCR_RESET, /* PCR 228 */\r
+ PORT_PCR_RESET, /* PCR 229 */\r
+ PORT_PCR_RESET, /* PCR 230 */\r
+ PORT_PCR_RESET, /* PCR 231 */\r
+ PORT_PCR_RESET, /* PCR 232 */\r
+ PORT_PCR_RESET, /* PCR 233 */\r
+ PORT_PCR_RESET, /* PCR 234 */\r
+ PORT_PCR_RESET, /* PCR 235 */\r
+ PORT_PCR_RESET, /* PCR 236 */\r
+ PORT_PCR_RESET, /* PCR 237 */\r
+ PORT_PCR_RESET, /* PCR 238 */\r
+ PORT_PCR_RESET, /* PCR 239 */\r
+ PORT_PCR_RESET, /* PCR 240 */\r
+ PORT_PCR_RESET, /* PCR 241 */\r
+ PORT_PCR_RESET, /* PCR 242 */\r
+ PORT_PCR_RESET, /* PCR 243 */\r
+ PORT_PCR_RESET, /* PCR 244 */\r
+ PORT_PCR_RESET, /* PCR 245 */\r
+ PORT_PCR_RESET, /* PCR 246 */\r
+ PORT_PCR_RESET, /* PCR 247 */\r
+ PORT_PCR_RESET, /* PCR 248 */\r
+ PORT_PCR_RESET, /* PCR 249 */\r
+ PORT_PCR_RESET, /* PCR 250 */\r
+ PORT_PCR_RESET, /* PCR 251 */\r
+ PORT_PCR_RESET, /* PCR 252 */\r
+ PORT_PCR_RESET, /* PCR 253 */\r
+ PORT_PCR_RESET, /* PCR 254 */\r
+ PORT_PCR_RESET, /* PCR 255 */\r
+ PORT_PCR_RESET, /* PCR 256 */\r
+ PORT_PCR_RESET, /* PCR 257 */\r
+ PORT_PCR_RESET, /* PCR 258 */\r
+ PORT_PCR_RESET, /* PCR 259 */\r
+ PORT_PCR_RESET, /* PCR 260 */\r
+ PORT_PCR_RESET, /* PCR 261 */\r
+ PORT_PCR_RESET, /* PCR 262 */\r
+ PORT_PCR_RESET, /* PCR 263 */\r
+ PORT_PCR_RESET, /* PCR 264 */\r
+ PORT_PCR_RESET, /* PCR 265 */\r
+ PORT_PCR_RESET, /* PCR 266 */\r
+ PORT_PCR_RESET, /* PCR 267 */\r
+ PORT_PCR_RESET, /* PCR 268 */\r
+ PORT_PCR_RESET, /* PCR 269 */\r
+ PORT_PCR_RESET, /* PCR 270 */\r
+ PORT_PCR_RESET, /* PCR 271 */\r
+ PORT_PCR_RESET, /* PCR 272 */\r
+ PORT_PCR_RESET, /* PCR 273 */\r
+ PORT_PCR_RESET, /* PCR 274 */\r
+ PORT_PCR_RESET, /* PCR 275 */\r
+ PORT_PCR_RESET, /* PCR 276 */\r
+ PORT_PCR_RESET, /* PCR 277 */\r
+ PORT_PCR_RESET, /* PCR 278 */\r
+ PORT_PCR_RESET, /* PCR 279 */\r
+ PORT_PCR_RESET, /* PCR 280 */\r
+ PORT_PCR_RESET, /* PCR 281 */\r
+ PORT_PCR_RESET, /* PCR 282 */\r
+ PORT_PCR_RESET, /* PCR 283 */\r
+ PORT_PCR_RESET, /* PCR 284 */\r
+ PORT_PCR_RESET, /* PCR 285 */\r
+ PORT_PCR_RESET, /* PCR 286 */\r
+ PORT_PCR_RESET, /* PCR 287 */\r
+ PORT_PCR_RESET, /* PCR 288 */\r
+ PORT_PCR_RESET, /* PCR 289 */\r
+ PORT_PCR_RESET, /* PCR 290 */\r
+ PORT_PCR_RESET, /* PCR 291 */\r
+ PORT_PCR_RESET, /* PCR 292 */\r
+ PORT_PCR_RESET, /* PCR 293 */\r
+ PORT_PCR_RESET, /* PCR 294 */\r
+ PORT_PCR_RESET, /* PCR 295 */\r
+ PORT_PCR_RESET, /* PCR 296 */\r
+ PORT_PCR_RESET, /* PCR 297 */\r
+ PORT_PCR_RESET, /* PCR 298 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ PORT_GPDO_RESET, /* GPDO 0 */\r
+ PORT_GPDO_RESET, /* GPDO 1 */\r
+ PORT_GPDO_RESET, /* GPDO 2 */\r
+ PORT_GPDO_RESET, /* GPDO 3 */\r
+ PORT_GPDO_RESET, /* GPDO 4 */\r
+ PORT_GPDO_RESET, /* GPDO 5 */\r
+ PORT_GPDO_RESET, /* GPDO 6 */\r
+ PORT_GPDO_RESET, /* GPDO 7 */\r
+ PORT_GPDO_RESET, /* GPDO 8 */\r
+ PORT_GPDO_RESET, /* GPDO 9 */\r
+ PORT_GPDO_RESET, /* GPDO 10 */\r
+ PORT_GPDO_RESET, /* GPDO 11 */\r
+ PORT_GPDO_RESET, /* GPDO 12 */\r
+ PORT_GPDO_RESET, /* GPDO 13 */\r
+ PORT_GPDO_RESET, /* GPDO 14 */\r
+ PORT_GPDO_RESET, /* GPDO 15 */\r
+ PORT_GPDO_RESET, /* GPDO 16 */\r
+ PORT_GPDO_RESET, /* GPDO 17 */\r
+ PORT_GPDO_RESET, /* GPDO 18 */\r
+ PORT_GPDO_RESET, /* GPDO 19 */\r
+ PORT_GPDO_RESET, /* GPDO 20 */\r
+ PORT_GPDO_RESET, /* GPDO 21 */\r
+ PORT_GPDO_RESET, /* GPDO 22 */\r
+ PORT_GPDO_RESET, /* GPDO 23 */\r
+ PORT_GPDO_RESET, /* GPDO 24 */\r
+ PORT_GPDO_RESET, /* GPDO 25 */\r
+ PORT_GPDO_RESET, /* GPDO 26 */\r
+ PORT_GPDO_RESET, /* GPDO 27 */\r
+ PORT_GPDO_RESET, /* GPDO 28 */\r
+ PORT_GPDO_RESET, /* GPDO 29 */\r
+ PORT_GPDO_RESET, /* GPDO 30 */\r
+ PORT_GPDO_RESET, /* GPDO 31 */\r
+ PORT_GPDO_RESET, /* GPDO 32 */\r
+ PORT_GPDO_RESET, /* GPDO 33 */\r
+ PORT_GPDO_RESET, /* GPDO 34 */\r
+ PORT_GPDO_RESET, /* GPDO 35 */\r
+ PORT_GPDO_RESET, /* GPDO 36 */\r
+ PORT_GPDO_RESET, /* GPDO 37 */\r
+ PORT_GPDO_RESET, /* GPDO 38 */\r
+ PORT_GPDO_RESET, /* GPDO 39 */\r
+ PORT_GPDO_RESET, /* GPDO 40 */\r
+ PORT_GPDO_RESET, /* GPDO 41 */\r
+ PORT_GPDO_RESET, /* GPDO 42 */\r
+ PORT_GPDO_RESET, /* GPDO 43 */\r
+ PORT_GPDO_RESET, /* GPDO 44 */\r
+ PORT_GPDO_RESET, /* GPDO 45 */\r
+ PORT_GPDO_RESET, /* GPDO 46 */\r
+ PORT_GPDO_RESET, /* GPDO 47 */\r
+ PORT_GPDO_RESET, /* GPDO 48 */\r
+ PORT_GPDO_RESET, /* GPDO 49 */\r
+ PORT_GPDO_RESET, /* GPDO 50 */\r
+ PORT_GPDO_RESET, /* GPDO 51 */\r
+ PORT_GPDO_RESET, /* GPDO 52 */\r
+ PORT_GPDO_RESET, /* GPDO 53 */\r
+ PORT_GPDO_RESET, /* GPDO 54 */\r
+ PORT_GPDO_RESET, /* GPDO 55 */\r
+ PORT_GPDO_RESET, /* GPDO 56 */\r
+ PORT_GPDO_RESET, /* GPDO 57 */\r
+ PORT_GPDO_RESET, /* GPDO 58 */\r
+ PORT_GPDO_RESET, /* GPDO 59 */\r
+ PORT_GPDO_RESET, /* GPDO 60 */\r
+ PORT_GPDO_RESET, /* GPDO 61 */\r
+ PORT_GPDO_RESET, /* GPDO 62 */\r
+ PORT_GPDO_RESET, /* GPDO 63 */\r
+ PORT_GPDO_RESET, /* GPDO 64 */\r
+ PORT_GPDO_RESET, /* GPDO 65 */\r
+ PORT_GPDO_RESET, /* GPDO 66 */\r
+ PORT_GPDO_RESET, /* GPDO 67 */\r
+ PORT_GPDO_RESET, /* GPDO 68 */\r
+ PORT_GPDO_RESET, /* GPDO 69 */\r
+ PORT_GPDO_RESET, /* GPDO 70 */\r
+ PORT_GPDO_RESET, /* GPDO 71 */\r
+ PORT_GPDO_RESET, /* GPDO 72 */\r
+ PORT_GPDO_RESET, /* GPDO 73 */\r
+ PORT_GPDO_RESET, /* GPDO 74 */\r
+ PORT_GPDO_RESET, /* GPDO 75 */\r
+ PORT_GPDO_RESET, /* GPDO 76 */\r
+ PORT_GPDO_RESET, /* GPDO 77 */\r
+ PORT_GPDO_RESET, /* GPDO 78 */\r
+ PORT_GPDO_RESET, /* GPDO 79 */\r
+ PORT_GPDO_RESET, /* GPDO 80 */\r
+ PORT_GPDO_RESET, /* GPDO 81 */\r
+ PORT_GPDO_RESET, /* GPDO 82 */\r
+ PORT_GPDO_RESET, /* GPDO 83 */\r
+ PORT_GPDO_RESET, /* GPDO 84 */\r
+ PORT_GPDO_RESET, /* GPDO 85 */\r
+ PORT_GPDO_RESET, /* GPDO 86 */\r
+ PORT_GPDO_RESET, /* GPDO 87 */\r
+ PORT_GPDO_RESET, /* GPDO 88 */\r
+ PORT_GPDO_RESET, /* GPDO 89 */\r
+ PORT_GPDO_RESET, /* GPDO 90 */\r
+ PORT_GPDO_RESET, /* GPDO 91 */\r
+ PORT_GPDO_RESET, /* GPDO 92 */\r
+ PORT_GPDO_RESET, /* GPDO 93 */\r
+ PORT_GPDO_RESET, /* GPDO 94 */\r
+ PORT_GPDO_RESET, /* GPDO 95 */\r
+ PORT_GPDO_RESET, /* GPDO 96 */\r
+ PORT_GPDO_RESET, /* GPDO 97 */\r
+ PORT_GPDO_RESET, /* GPDO 98 */\r
+ PORT_GPDO_RESET, /* GPDO 99 */\r
+ PORT_GPDO_RESET, /* GPDO 100 */\r
+ PORT_GPDO_RESET, /* GPDO 101 */\r
+ PORT_GPDO_RESET, /* GPDO 102 */\r
+ PORT_GPDO_RESET, /* GPDO 103 */\r
+ PORT_GPDO_RESET, /* GPDO 104 */\r
+ PORT_GPDO_RESET, /* GPDO 105 */\r
+ PORT_GPDO_RESET, /* GPDO 106 */\r
+ PORT_GPDO_RESET, /* GPDO 107 */\r
+ PORT_GPDO_RESET, /* GPDO 108 */\r
+ PORT_GPDO_RESET, /* GPDO 109 */\r
+ PORT_GPDO_RESET, /* GPDO 110 */\r
+ PORT_GPDO_RESET, /* GPDO 111 */\r
+ PORT_GPDO_RESET, /* GPDO 112 */\r
+ PORT_GPDO_RESET, /* GPDO 113 */\r
+ PORT_GPDO_RESET, /* GPDO 114 */\r
+ PORT_GPDO_RESET, /* GPDO 115 */\r
+ PORT_GPDO_RESET, /* GPDO 116 */\r
+ PORT_GPDO_RESET, /* GPDO 117 */\r
+ PORT_GPDO_RESET, /* GPDO 118 */\r
+ PORT_GPDO_RESET, /* GPDO 119 */\r
+ PORT_GPDO_RESET, /* GPDO 120 */\r
+ PORT_GPDO_RESET, /* GPDO 121 */\r
+ PORT_GPDO_RESET, /* GPDO 122 */\r
+ PORT_GPDO_RESET, /* GPDO 123 */\r
+ PORT_GPDO_RESET, /* GPDO 124 */\r
+ PORT_GPDO_RESET, /* GPDO 125 */\r
+ PORT_GPDO_RESET, /* GPDO 126 */\r
+ PORT_GPDO_RESET, /* GPDO 127 */\r
+ PORT_GPDO_RESET, /* GPDO 128 */\r
+ PORT_GPDO_RESET, /* GPDO 129 */\r
+ PORT_GPDO_RESET, /* GPDO 130 */\r
+ PORT_GPDO_RESET, /* GPDO 131 */\r
+ PORT_GPDO_RESET, /* GPDO 132 */\r
+ PORT_GPDO_RESET, /* GPDO 133 */\r
+ PORT_GPDO_RESET, /* GPDO 134 */\r
+ PORT_GPDO_RESET, /* GPDO 135 */\r
+ PORT_GPDO_RESET, /* GPDO 136 */\r
+ PORT_GPDO_RESET, /* GPDO 137 */\r
+ PORT_GPDO_RESET, /* GPDO 138 */\r
+ PORT_GPDO_RESET, /* GPDO 139 */\r
+ PORT_GPDO_RESET, /* GPDO 140 */\r
+ PORT_GPDO_RESET, /* GPDO 141 */\r
+ PORT_GPDO_RESET, /* GPDO 142 */\r
+ PORT_GPDO_RESET, /* GPDO 143 */\r
+ PORT_GPDO_RESET, /* GPDO 144 */\r
+ PORT_GPDO_RESET, /* GPDO 145 */\r
+ PORT_GPDO_RESET, /* GPDO 146 */\r
+ PORT_GPDO_RESET, /* GPDO 147 */\r
+ PORT_GPDO_RESET, /* GPDO 148 */\r
+ PORT_GPDO_RESET, /* GPDO 149 */\r
+ PORT_GPDO_RESET, /* GPDO 150 */\r
+ PORT_GPDO_RESET, /* GPDO 151 */\r
+ PORT_GPDO_RESET, /* GPDO 152 */\r
+ PORT_GPDO_RESET, /* GPDO 153 */\r
+ PORT_GPDO_RESET, /* GPDO 154 */\r
+ PORT_GPDO_RESET, /* GPDO 155 */\r
+ PORT_GPDO_RESET, /* GPDO 156 */\r
+ PORT_GPDO_RESET, /* GPDO 157 */\r
+ PORT_GPDO_RESET, /* GPDO 158 */\r
+ PORT_GPDO_RESET, /* GPDO 159 */\r
+ PORT_GPDO_RESET, /* GPDO 160 */\r
+ PORT_GPDO_RESET, /* GPDO 161 */\r
+ PORT_GPDO_RESET, /* GPDO 162 */\r
+ PORT_GPDO_RESET, /* GPDO 163 */\r
+ PORT_GPDO_RESET, /* GPDO 164 */\r
+ PORT_GPDO_RESET, /* GPDO 165 */\r
+ PORT_GPDO_RESET, /* GPDO 166 */\r
+ PORT_GPDO_RESET, /* GPDO 167 */\r
+ PORT_GPDO_RESET, /* GPDO 168 */\r
+ PORT_GPDO_RESET, /* GPDO 169 */\r
+ PORT_GPDO_RESET, /* GPDO 170 */\r
+ PORT_GPDO_RESET, /* GPDO 171 */\r
+ PORT_GPDO_RESET, /* GPDO 172 */\r
+ PORT_GPDO_RESET, /* GPDO 173 */\r
+ PORT_GPDO_RESET, /* GPDO 174 */\r
+ PORT_GPDO_RESET, /* GPDO 175 */\r
+ PORT_GPDO_RESET, /* GPDO 176 */\r
+ PORT_GPDO_RESET, /* GPDO 177 */\r
+ PORT_GPDO_RESET, /* GPDO 178 */\r
+ PORT_GPDO_RESET, /* GPDO 179 */\r
+ PORT_GPDO_RESET, /* GPDO 180 */\r
+ PORT_GPDO_RESET, /* GPDO 181 */\r
+ PORT_GPDO_RESET, /* GPDO 182 */\r
+ PORT_GPDO_RESET, /* GPDO 183 */\r
+ PORT_GPDO_RESET, /* GPDO 184 */\r
+ PORT_GPDO_RESET, /* GPDO 185 */\r
+ PORT_GPDO_RESET, /* GPDO 186 */\r
+ PORT_GPDO_RESET, /* GPDO 187 */\r
+ PORT_GPDO_RESET, /* GPDO 188 */\r
+ PORT_GPDO_RESET, /* GPDO 189 */\r
+ PORT_GPDO_RESET, /* GPDO 190 */\r
+ PORT_GPDO_RESET, /* GPDO 191 */\r
+ PORT_GPDO_RESET, /* GPDO 192 */\r
+ PORT_GPDO_RESET, /* GPDO 193 */\r
+ PORT_GPDO_RESET, /* GPDO 194 */\r
+ PORT_GPDO_RESET, /* GPDO 195 */\r
+ PORT_GPDO_RESET, /* GPDO 196 */\r
+ PORT_GPDO_RESET, /* GPDO 197 */\r
+ PORT_GPDO_RESET, /* GPDO 198 */\r
+ PORT_GPDO_RESET, /* GPDO 199 */\r
+ PORT_GPDO_RESET, /* GPDO 200 */\r
+ PORT_GPDO_RESET, /* GPDO 201 */\r
+ PORT_GPDO_RESET, /* GPDO 202 */\r
+ PORT_GPDO_RESET, /* GPDO 203 */\r
+ PORT_GPDO_RESET, /* GPDO 204 */\r
+ PORT_GPDO_RESET, /* GPDO 205 */\r
+ PORT_GPDO_RESET, /* GPDO 206 */\r
+ PORT_GPDO_RESET, /* GPDO 207 */\r
+ PORT_GPDO_RESET, /* GPDO 208 */\r
+ PORT_GPDO_RESET, /* GPDO 209 */\r
+ PORT_GPDO_RESET, /* GPDO 210 */\r
+ PORT_GPDO_RESET, /* GPDO 211 */\r
+ PORT_GPDO_RESET, /* GPDO 212 */\r
+ PORT_GPDO_RESET, /* GPDO 213 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:18:05 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
+\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_IO (0)\r
+#define PORT_FUNC0 (0)\r
+#define PORT_FUNC1 (PORT_BIT5)\r
+#define PORT_FUNC2 (PORT_BIT4)\r
+#define PORT_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+#define PORT_FUNC4 (PORT_BIT3)\r
+\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_GPDO_RESET (0)\r
+\r
+#define PORT_GPDO_HIGH (1)\r
+\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_GPIO125 125 \r
+\r
+#endif /* PORT_CFG_H_ */\r
--- /dev/null
+/*\r
+ * Configuration of module Det (Det_cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+
+#if !(((DET_SW_MAJOR_VERSION == 1) && (DET_SW_MINOR_VERSION == 0)) )
+#error "Det: Configuration file version differs from BSW version."
+#endif
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H \r
+\r
+#define DET_ENABLE_CALLBACKS STD_OFF // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+#define DET_DEINIT_API STD_OFF // Enable/Disable the Det_DeInit function\r
+#define DET_RAMLOG_SIZE (16) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /* DET_CFG_H */\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+
+#if !(((DIO_SW_MAJOR_VERSION == 1) && (DIO_SW_MINOR_VERSION == 0)) )
+#error "Dio: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ A = 0,\r
+ B = 1,\r
+ C = 2,\r
+ D = 3,\r
+ E = 4,\r
+ F = 5,\r
+ G = 6,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_LED_CHANNEL1 29\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL2 30\r
+\r
+// Channel group\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_LED_PORT (B)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+\r
+ \r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_LED_CHANNEL1,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL2,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_LED_PORT, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = {\r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = DIO_END_OF_LIST, \r
+ .mask = DIO_END_OF_LIST, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+\r
+MOD_USE += PORT DIO \r
+\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Callout_template.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 24 13:05:28 CET 2011\r
+ */\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Cbk.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+#if defined(USE_NVM)\r
+#include "NvM.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+\r
+void EcuM_AL_DriverInitZero(void)\r
+{\r
+ Det_Init();\r
+ Det_Start();\r
+}\r
+\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void)\r
+{\r
+ return &EcuMConfig;\r
+}\r
+\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_MCU)\r
+ Mcu_Init(ConfigPtr->McuConfig);\r
+\r
+ // Set up default clock (Mcu_InitClock requires initRun==1)\r
+ // Ignoring return value\r
+ (void) Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+ // Preinitialize DEM\r
+ Dem_PreInit();\r
+#endif\r
+\r
+#if defined(USE_PORT)\r
+ // Setup Port\r
+ Port_Init(ConfigPtr->PortConfig);\r
+#endif\r
+\r
+\r
+#if defined(USE_GPT)\r
+ // Setup the GPT\r
+ Gpt_Init(ConfigPtr->GptConfig);\r
+#endif\r
+\r
+ // Setup watchdog\r
+ // TODO\r
+\r
+#if defined(USE_DMA)\r
+ // Setup DMA\r
+ Dma_Init(ConfigPtr->DmaConfig);\r
+#endif\r
+\r
+#if defined(USE_ADC)\r
+ // Setup ADC\r
+ Adc_Init(ConfigPtr->AdcConfig);\r
+#endif\r
+\r
+ // Setup ICU\r
+ // TODO\r
+\r
+ // Setup PWM\r
+#if defined(USE_PWM)\r
+ // Setup PWM\r
+ Pwm_Init(ConfigPtr->PwmConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_SPI)\r
+ // Setup SPI\r
+ Spi_Init(ConfigPtr->SpiConfig);\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+ // Setup EEP\r
+ Eep_Init(ConfigPtr->EEpConfig);\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+ // Setup Flash\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+#if defined(USE_FEE)\r
+ // Setup FEE\r
+ Fee_Init();\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+ // Setup EA\r
+ Ea_init();\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+ // Setup NVRAM Manager and start the read all job\r
+ NvM_Init();\r
+ NvM_ReadAll();\r
+#endif\r
+\r
+ // Setup CAN tranceiver\r
+ // TODO\r
+\r
+#if defined(USE_CAN)\r
+ // Setup Can driver\r
+ Can_Init(ConfigPtr->CanConfig);\r
+#endif\r
+\r
+#if defined(USE_CANIF)\r
+ // Setup CanIf\r
+ CanIf_Init(ConfigPtr->CanIfConfig);\r
+#endif\r
+\r
+#if defined(USE_CANTP)\r
+ // Setup CAN TP\r
+ CanTp_Init();\r
+#endif\r
+\r
+#if defined(USE_CANSM)\r
+ CanSM_Init(ConfigPtr->CanSMConfig);\r
+#endif\r
+\r
+ // Setup LIN\r
+ // TODO\r
+\r
+#if defined(USE_PDUR)\r
+ // Setup PDU Router\r
+ PduR_Init(ConfigPtr->PduRConfig);\r
+#endif\r
+\r
+#if defined(USE_CANNM)\r
+ // Setup Can Network Manager\r
+ CanNm_Init(ConfigPtr->CanNmConfig);\r
+#endif\r
+\r
+#if defined(USE_NM)\r
+ // Setup Network Management Interface\r
+ Nm_Init(ConfigPtr->NmConfig);\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+ // Setup COM layer\r
+ Com_Init(ConfigPtr->ComConfig);\r
+#endif\r
+\r
+#if defined(USE_DCM)\r
+ // Setup DCM\r
+ Dcm_Init();\r
+#endif\r
+\r
+#if defined(USE_IOHWAB)\r
+ // Setup IO hardware abstraction layer\r
+ IoHwAb_Init();\r
+#endif\r
+\r
+}\r
+\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_DEM)\r
+ // Setup DEM\r
+ Dem_Init();\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+ // Setup Communication Manager\r
+ ComM_Init(ConfigPtr->ComMConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_OnEnterRUN(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitPostRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnPrepShutdown(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoSleep(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffOne(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffTwo(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff(void)\r
+{\r
+\r
+}\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 24 13:05:28 CET 2011\r
+ */\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultShutdownMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,\r
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,\r
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)\r
+ .FlashConfig = FlsConfigSet,\r
+#endif\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_DEV_ERROR_DETECT STD_ON\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Generated_Types.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 24 13:05:28 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultShutdownMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;\r
+ uint32 EcuMNvramReadAllTimeout;\r
+ uint32 EcuMNvramWriteAllTimeout;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_CANSM)\r
+ const CanSM_ConfigType* CanSMConfig;\r
+#endif\r
+#if defined(USE_NM)\r
+ const Nm_ConfigType* NmConfig;\r
+#endif\r
+#if defined(USE_CANNM)\r
+ const CanNm_ConfigType* CanNmConfig;\r
+#endif\r
+#if defined(USE_COMM)\r
+ const ComM_ConfigType* ComMConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)\r
+ const Fls_ConfigType* FlashConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:22:38 CET 2011\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 8000000UL,\r
+ .Pll1 = 9,\r
+ .Pll2 = 0,\r
+ .Pll3 = 0,\r
+ },\r
+};\r
+\r
+const Mcu_PerClockConfigType McuPerClockConfigData =\r
+{ \r
+ .AHBClocksEnable = RCC_AHBPeriph_DMA1,\r
+ .APB1ClocksEnable = RCC_APB1Periph_TIM2 | RCC_APB1Periph_CAN1,\r
+ .APB2ClocksEnable = RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO\r
+};\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 14:22:38 CET 2011\r
+ */\r
+\r
+
+#if !(((MCU_SW_MAJOR_VERSION == 2) && (MCU_SW_MINOR_VERSION == 0)) )
+#error "Mcu: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Mcu_ConfigTypes.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON \r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_8MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_alarm10,\r
+ "alarm10",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask10,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm100,\r
+ "alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_alarm25,\r
+ "alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,2048);\r
+DECLARE_STACK(bTask10,2048);\r
+DECLARE_STACK(bTask100,2048);\r
+DECLARE_STACK(bTask25,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask10,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_alarm10 0\r
+#define ALARM_ID_alarm100 1\r
+#define ALARM_ID_alarm25 2\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask10 2\r
+#define TASK_ID_bTask100 3\r
+#define TASK_ID_bTask25 4\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask10( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 3 \r
+#define OS_TASK_CNT 5\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+ \r
+#include "stm32f10x_gpio.h"\r
+#include "port.h"\r
+\r
+const uint32 remaps[] = {\r
+ GPIO_Remap1_CAN1,\r
+ GPIO_PartialRemap2_TIM2,\r
+};\r
+\r
+const GpioPinCnfMode_Type GPIOConf[] =\r
+{\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF, \r
+ .GpioPinCnfMode_14 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+};\r
+\r
+\r
+const GpioPinOutLevel_Type GPIOOutConf[] =\r
+{\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_HIGH, \r
+ .GpioPinOutLevel_14 = GPIO_OUTPUT_HIGH, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = 7,\r
+ .padConfig = GPIOConf,\r
+ .outConfig = GPIOOutConf,\r
+\r
+ .remapCount = sizeof(remaps) / sizeof(uint32),\r
+ .remaps = &remaps[0]\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Jan 26 12:28:57 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Port_ConfigTypes.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /* PORT_CFG_H_ */\r
--- /dev/null
+/*\r
+ * Configuration of module Det (Det_cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+
+#if !(((DET_SW_MAJOR_VERSION == 1) && (DET_SW_MINOR_VERSION == 0)) )
+#error "Det: Configuration file version differs from BSW version."
+#endif
+
+/*\r
+ * Development Error Tracer driver\r
+ *\r
+ * Specification: Autosar v2.0.1, Final\r
+ *\r
+ */\r
+#ifndef DET_CFG_H\r
+#define DET_CFG_H \r
+\r
+#define DET_ENABLE_CALLBACKS STD_OFF // Enable to use callback on errors\r
+#define DET_USE_RAMLOG STD_ON // Enable to log DET errors to ramlog\r
+#define DET_WRAP_RAMLOG STD_ON // The ramlog wraps around when reaching the end\r
+#define DET_USE_STDERR STD_OFF // Enable to get DET errors on stderr\r
+#define DET_DEINIT_API STD_OFF // Enable/Disable the Det_DeInit function\r
+#define DET_RAMLOG_SIZE (16) // Number of entries in ramlog\r
+#define DET_NUMBER_OF_CALLBACKS (5) // Number of callbacks\r
+\r
+#endif /* DET_CFG_H */\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+
+#if !(((DIO_SW_MAJOR_VERSION == 1) && (DIO_SW_MINOR_VERSION == 0)) )
+#error "Dio: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+\r
+#define DIO_END_OF_LIST -1\r
+\r
+// Physical ports\r
+typedef enum\r
+{\r
+ A = 0,\r
+ B = 1,\r
+ C = 2,\r
+ D = 3,\r
+ E = 4,\r
+ F = 5,\r
+ G = 6,\r
+} Dio_PortTypesType;\r
+\r
+\r
+// Channels \r
+#define DIO_CHANNEL_NAME_LED_CHANNEL1 55\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL2 61\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL3 51\r
+#define DIO_CHANNEL_NAME_LED_CHANNEL4 52\r
+\r
+// Channel group\r
+\r
+// Ports\r
+#define DIO_PORT_NAME_LED_PORT (D)\r
+\r
+\r
+\r
+\r
+// Pointers for convenience.\r
+// Channels \r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+\r
+#endif /*DIO_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Dio (Dio_Lcfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.0\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+\r
+ \r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] = { \r
+ DIO_CHANNEL_NAME_LED_CHANNEL1,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL2,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL3,\r
+ DIO_CHANNEL_NAME_LED_CHANNEL4,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] = { \r
+ DIO_PORT_NAME_LED_PORT, \r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] = {\r
+ { \r
+ .port = DIO_END_OF_LIST, \r
+ .offset = DIO_END_OF_LIST, \r
+ .mask = DIO_END_OF_LIST, \r
+ }\r
+};\r
+\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+\r
+MOD_USE += DIO PORT MCU \r
+\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Callout_template.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:28:13 CET 2011\r
+ */\r
+\r
+\r
+#include "EcuM.h"\r
+#include "EcuM_Cbk.h"\r
+#include "Det.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_IOHWAB)\r
+#include "IoHwAb.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+#if defined(USE_EEP)\r
+#include "Eep.h"\r
+#endif\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+#if defined(USE_NVM)\r
+#include "NvM.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+\r
+void EcuM_AL_DriverInitZero(void)\r
+{\r
+ Det_Init();\r
+ Det_Start();\r
+}\r
+\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void)\r
+{\r
+ return &EcuMConfig;\r
+}\r
+\r
+void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_MCU)\r
+ Mcu_Init(ConfigPtr->McuConfig);\r
+\r
+ // Set up default clock (Mcu_InitClock requires initRun==1)\r
+ // Ignoring return value\r
+ (void) Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
+\r
+ // Wait for PLL to sync.\r
+ while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
+ {\r
+ ;\r
+ }\r
+#endif\r
+\r
+#if defined(USE_DEM)\r
+ // Preinitialize DEM\r
+ Dem_PreInit();\r
+#endif\r
+\r
+#if defined(USE_PORT)\r
+ // Setup Port\r
+ Port_Init(ConfigPtr->PortConfig);\r
+#endif\r
+\r
+\r
+#if defined(USE_GPT)\r
+ // Setup the GPT\r
+ Gpt_Init(ConfigPtr->GptConfig);\r
+#endif\r
+\r
+ // Setup watchdog\r
+ // TODO\r
+\r
+#if defined(USE_DMA)\r
+ // Setup DMA\r
+ Dma_Init(ConfigPtr->DmaConfig);\r
+#endif\r
+\r
+#if defined(USE_ADC)\r
+ // Setup ADC\r
+ Adc_Init(ConfigPtr->AdcConfig);\r
+#endif\r
+\r
+ // Setup ICU\r
+ // TODO\r
+\r
+ // Setup PWM\r
+#if defined(USE_PWM)\r
+ // Setup PWM\r
+ Pwm_Init(ConfigPtr->PwmConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_SPI)\r
+ // Setup SPI\r
+ Spi_Init(ConfigPtr->SpiConfig);\r
+#endif\r
+\r
+#if defined(USE_EEP)\r
+ // Setup EEP\r
+ Eep_Init(ConfigPtr->EEpConfig);\r
+#endif\r
+\r
+#if defined(USE_FLS)\r
+ // Setup Flash\r
+ Fls_Init(ConfigPtr->FlashConfig);\r
+#endif\r
+\r
+#if defined(USE_FEE)\r
+ // Setup FEE\r
+ Fee_Init();\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+ // Setup EA\r
+ Ea_init();\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+ // Setup NVRAM Manager and start the read all job\r
+ NvM_Init();\r
+ NvM_ReadAll();\r
+#endif\r
+\r
+ // Setup CAN tranceiver\r
+ // TODO\r
+\r
+#if defined(USE_CAN)\r
+ // Setup Can driver\r
+ Can_Init(ConfigPtr->CanConfig);\r
+#endif\r
+\r
+#if defined(USE_CANIF)\r
+ // Setup CanIf\r
+ CanIf_Init(ConfigPtr->CanIfConfig);\r
+#endif\r
+\r
+#if defined(USE_CANTP)\r
+ // Setup CAN TP\r
+ CanTp_Init();\r
+#endif\r
+\r
+#if defined(USE_CANSM)\r
+ CanSM_Init(ConfigPtr->CanSMConfig);\r
+#endif\r
+\r
+ // Setup LIN\r
+ // TODO\r
+\r
+#if defined(USE_PDUR)\r
+ // Setup PDU Router\r
+ PduR_Init(ConfigPtr->PduRConfig);\r
+#endif\r
+\r
+#if defined(USE_CANNM)\r
+ // Setup Can Network Manager\r
+ CanNm_Init(ConfigPtr->CanNmConfig);\r
+#endif\r
+\r
+#if defined(USE_NM)\r
+ // Setup Network Management Interface\r
+ Nm_Init(ConfigPtr->NmConfig);\r
+#endif\r
+\r
+#if defined(USE_COM)\r
+ // Setup COM layer\r
+ Com_Init(ConfigPtr->ComConfig);\r
+#endif\r
+\r
+#if defined(USE_DCM)\r
+ // Setup DCM\r
+ Dcm_Init();\r
+#endif\r
+\r
+#if defined(USE_IOHWAB)\r
+ // Setup IO hardware abstraction layer\r
+ IoHwAb_Init();\r
+#endif\r
+\r
+}\r
+\r
+void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr)\r
+{\r
+ //lint --e{715} PC-Lint (715) - ConfigPtr usage depends on configuration of modules\r
+\r
+#if defined(USE_DEM)\r
+ // Setup DEM\r
+ Dem_Init();\r
+#endif\r
+\r
+#if defined(USE_COMM)\r
+ // Setup Communication Manager\r
+ ComM_Init(ConfigPtr->ComMConfig);\r
+#endif\r
+}\r
+\r
+void EcuM_OnEnterRUN(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnExitPostRun(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnPrepShutdown(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoSleep(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffOne(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_OnGoOffTwo(void)\r
+{\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff(void)\r
+{\r
+\r
+}\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:28:13 CET 2011\r
+ */\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultShutdownMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+ .EcuMNvramReadAllTimeout = ECUM_NVRAM_READALL_TIMEOUT,\r
+ .EcuMNvramWriteAllTimeout = ECUM_NVRAM_WRITEALL_TIMEOUT,\r
+ .EcuMRunMinimumDuration = ECUM_NVRAM_MIN_RUN_DURATION,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+#if defined(USE_FLS)\r
+ .FlashConfig = FlsConfigSet,\r
+#endif\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_ON\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Generated_Types.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:28:13 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef _ECUM_GENERATED_TYPES_H_\r
+#define _ECUM_GENERATED_TYPES_H_\r
+\r
+#if defined(USE_MCU)\r
+#include "Mcu.h"\r
+#endif\r
+#if defined(USE_PORT)\r
+#include "Port.h"\r
+#endif\r
+#if defined(USE_CAN)\r
+#include "Can.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_PWM)\r
+#include "Pwm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_DMA)\r
+#include "Dma.h"\r
+#endif\r
+#if defined(USE_ADC)\r
+#include "Adc.h"\r
+#endif\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+#if defined(USE_COMM)\r
+#include "ComM.h"\r
+#endif\r
+#if defined(USE_NM)\r
+#include "Nm.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm.h"\r
+#endif\r
+#if defined(USE_CANSM)\r
+#include "CanSM.h"\r
+#endif\r
+#if defined(USE_LINSM)\r
+#include "LinSM.h"\r
+#endif\r
+#if defined(USE_FLS)\r
+#include "Fls.h"\r
+#endif\r
+\r
+typedef struct\r
+{\r
+ EcuM_StateType EcuMDefaultShutdownTarget;\r
+ uint8 EcuMDefaultShutdownMode;\r
+ AppModeType EcuMDefaultAppMode;\r
+ uint32 EcuMRunMinimumDuration;\r
+ uint32 EcuMNvramReadAllTimeout;\r
+ uint32 EcuMNvramWriteAllTimeout;\r
+\r
+#if defined(USE_MCU)\r
+ const Mcu_ConfigType* McuConfig;\r
+#endif\r
+#if defined(USE_PORT)\r
+ const Port_ConfigType* PortConfig;\r
+#endif\r
+#if defined(USE_CAN)\r
+ const Can_ConfigType* CanConfig;\r
+#endif\r
+#if defined(USE_CANIF)\r
+ const CanIf_ConfigType* CanIfConfig;\r
+#endif\r
+#if defined(USE_CANSM)\r
+ const CanSM_ConfigType* CanSMConfig;\r
+#endif\r
+#if defined(USE_NM)\r
+ const Nm_ConfigType* NmConfig;\r
+#endif\r
+#if defined(USE_CANNM)\r
+ const CanNm_ConfigType* CanNmConfig;\r
+#endif\r
+#if defined(USE_COMM)\r
+ const ComM_ConfigType* ComMConfig;\r
+#endif\r
+#if defined(USE_COM)\r
+ const Com_ConfigType* ComConfig;\r
+#endif\r
+#if defined(USE_PDUR)\r
+ const PduR_PBConfigType* PduRConfig;\r
+#endif\r
+#if defined(USE_PWM)\r
+ const Pwm_ConfigType* PwmConfig;\r
+#endif\r
+#if defined(USE_DMA)\r
+ const Dma_ConfigType* DmaConfig;\r
+#endif\r
+#if defined(USE_ADC)\r
+ const Adc_ConfigType* AdcConfig;\r
+#endif\r
+#if defined(USE_GPT)\r
+ const Gpt_ConfigType* GptConfig;\r
+#endif\r
+#if defined(USE_FLS)\r
+ const Fls_ConfigType* FlashConfig;\r
+#endif\r
+} EcuM_ConfigType;\r
+\r
+#endif /*_ECUM_GENERATED_TYPES_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+\r
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ .McuRamDefaultValue = 0,\r
+ .McuRamSectionBaseAddress = 0,\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 25000000UL,\r
+ .Pll1 = 9,\r
+ .Pll2 = 8,\r
+ .Pll3 = 0,\r
+ },\r
+};\r
+\r
+const Mcu_PerClockConfigType McuPerClockConfigData =\r
+{ \r
+ .AHBClocksEnable = RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_ETH_MAC | RCC_AHBPeriph_ETH_MAC_Tx | RCC_AHBPeriph_ETH_MAC_Rx,\r
+ .APB1ClocksEnable = RCC_APB1Periph_TIM2 | RCC_APB1Periph_CAN1,\r
+ .APB2ClocksEnable = RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO\r
+};\r
+\r
+const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ .McuClockSrcFailureNotification = 0,\r
+ .McuRamSectors = 1,\r
+ .McuClockSettings = 1,\r
+ .McuDefaultClockSettings = 0,\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ }\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Mcu (Mcu_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+
+#if !(((MCU_SW_MAJOR_VERSION == 2) && (MCU_SW_MINOR_VERSION == 0)) )
+#error "Mcu: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Mcu_ConfigTypes.h"\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_OFF \r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_25MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 10:51:58 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 10:51:58 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+ \r
+#include "stm32f10x_gpio.h"\r
+#include "port.h"\r
+\r
+const uint32 remaps[] = {\r
+};\r
+\r
+const GpioPinCnfMode_Type GPIOConf[] =\r
+{\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF, \r
+ .GpioPinCnfMode_4 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = GPIO_OUTPUT_10MHz_MODE | GPIO_OUTPUT_PUSHPULL_CNF, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinCnfMode_0 = 0, \r
+ .GpioPinCnfMode_1 = 0, \r
+ .GpioPinCnfMode_2 = 0, \r
+ .GpioPinCnfMode_3 = 0, \r
+ .GpioPinCnfMode_4 = 0, \r
+ .GpioPinCnfMode_5 = 0, \r
+ .GpioPinCnfMode_6 = 0, \r
+ .GpioPinCnfMode_7 = 0, \r
+ .GpioPinCnfMode_8 = 0, \r
+ .GpioPinCnfMode_9 = 0, \r
+ .GpioPinCnfMode_10 = 0, \r
+ .GpioPinCnfMode_11 = 0, \r
+ .GpioPinCnfMode_12 = 0, \r
+ .GpioPinCnfMode_13 = 0, \r
+ .GpioPinCnfMode_14 = 0, \r
+ .GpioPinCnfMode_15 = 0, \r
+ },\r
+};\r
+\r
+\r
+const GpioPinOutLevel_Type GPIOOutConf[] =\r
+{\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = GPIO_OUTPUT_HIGH, \r
+ .GpioPinOutLevel_4 = GPIO_OUTPUT_HIGH, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = GPIO_OUTPUT_HIGH, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = GPIO_OUTPUT_HIGH, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+ {\r
+ .GpioPinOutLevel_0 = 0, \r
+ .GpioPinOutLevel_1 = 0, \r
+ .GpioPinOutLevel_2 = 0, \r
+ .GpioPinOutLevel_3 = 0, \r
+ .GpioPinOutLevel_4 = 0, \r
+ .GpioPinOutLevel_5 = 0, \r
+ .GpioPinOutLevel_6 = 0, \r
+ .GpioPinOutLevel_7 = 0, \r
+ .GpioPinOutLevel_8 = 0, \r
+ .GpioPinOutLevel_9 = 0, \r
+ .GpioPinOutLevel_10 = 0, \r
+ .GpioPinOutLevel_11 = 0, \r
+ .GpioPinOutLevel_12 = 0, \r
+ .GpioPinOutLevel_13 = 0, \r
+ .GpioPinOutLevel_14 = 0, \r
+ .GpioPinOutLevel_15 = 0, \r
+ },\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = 7,\r
+ .padConfig = GPIOConf,\r
+ .outConfig = GPIOOutConf,\r
+\r
+ .remapCount = sizeof(remaps) / sizeof(uint32),\r
+ .remaps = &remaps[0]\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 21 11:32:26 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "Port_ConfigTypes.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_ON\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /* PORT_CFG_H_ */\r
obj-y += Hooks.o\r
obj-y += Rte.o\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
+VPATH += ../\r
+\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
inc-y += $(ROOTDIR)/system/kernel/include\r
\r
#TODO: Remove?, Build other way?\r
-VPATH += $(ROOTDIR)/$(SUBDIR)/Rte\r
-inc-y += $(ROOTDIR)/$(SUBDIR)/Rte\r
+VPATH += ../Rte\r
+inc-y += ../Rte\r
VPATH += $(ROOTDIR)/components/blinker\r
inc-y += $(ROOTDIR)/components/blinker\r
\r
\r
# libs needed by us \r
-libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+#libitem-y +=\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = blinker_node.elf\r
\r
\r
#include "Os.h"\r
+#include "Mcu.h"\r
#include "Pwm.h"\r
#include <stdio.h>\r
#include <assert.h>\r
-#define USE_TRACE 1\r
-#define USE_LDEBUG_PRINTF 1\r
+\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
#include "debug.h"\r
\r
/* Notification callback from channel 0 */\r
\r
/* Global hooks */\r
ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
- LDEBUG_PRINTF("## ProtectionHook\n");\r
+ LDEBUG_FPUTS("## ProtectionHook\n");\r
return PRO_KILLAPPL;\r
}\r
\r
void StartupHook( void ) {\r
- LDEBUG_PRINTF("## StartupHook\n");\r
-\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
+ LDEBUG_FPUTS("## StartupHook\n");\r
\r
- LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
+ LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)McuE_GetSystemClock());\r
}\r
\r
void ShutdownHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ShutdownHook\n");\r
+ LDEBUG_FPUTS("## ShutdownHook\n");\r
while(1);\r
}\r
\r
}\r
// LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
}\r
-\r
-#if 0\r
-struct OsHooks os_conf_global_hooks = {\r
- .StartupHook = StartupHook,\r
- .ProtectionHook = ProtectionHook,\r
- .ShutdownHook = ShutdownHook,\r
- .ErrorHook = ErrorHook,\r
- .PreTaskHook = PreTaskHook,\r
- .PostTaskHook = PostTaskHook\r
- };\r
-#endif\r
\r
\r
void RTE_pwm_enable_notifications(Pwm_ChannelType channel, Pwm_EdgeNotificationType type) {\r
+#if (PWM_NOTIFICATION_SUPPORTED == STD_ON)\r
Pwm_EnableNotification(channel, type);\r
+#endif\r
}\r
#include <stdio.h>\r
#include <assert.h>\r
#include "pwm_sine_main.h"\r
+\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
#include "debug.h"\r
-//#include "WdgM.h"\r
\r
\r
void OsIdle( void ) {\r
+-include ../config/*.mk\r
+-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU PORT PWM\r
-\r
-SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+MOD_USE+=KERNEL MCU ECUM DET PORT PWM RAMLOG\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:54:45 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm100,\r
+ "Alarm100",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask100,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_Alarm25,\r
+ "Alarm25",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_bTask25,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Startup,512);\r
+DECLARE_STACK(bTask100,512);\r
+DECLARE_STACK(bTask25,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ Startup,\r
+ 3,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask100,\r
+ 2,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ bTask25,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:54:45 CET 2011\r
+ */\r
+\r
+
+#if ((OS_SW_MAJOR_VERSION != 2))
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm100 0\r
+#define ALARM_ID_Alarm25 1\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Startup 1\r
+#define TASK_ID_bTask100 2\r
+#define TASK_ID_bTask25 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Startup( void );\r
+void bTask100( void );\r
+void bTask25( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 2 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:54:45 CET 2011\r
+ */\r
+\r
+ \r
+\r
+\r
+#include "Port.h"\r
+\r
+#define PORT_UNDEFINED 0x00\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .corePullUpRegister = 0x90,\r
+ .coreReducedDriveRegister = 0x00,\r
+ .modeRoutingRegister = 0x00,\r
+\r
+ #if ( PORTA_CONFIGURABLE == STD_ON )\r
+ .portADirection = PORT_UNDEFINED,\r
+ .portAOutValue = PORT_UNDEFINED,\r
+ .portAMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTB_CONFIGURABLE == STD_ON )\r
+ .portBDirection = 0xFF,\r
+ .portBOutValue = PORT_UNDEFINED,\r
+ .portBMask = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTE_CONFIGURABLE == STD_ON )\r
+ .portEDirection = PORT_UNDEFINED,\r
+ .portEOutValue = PORT_UNDEFINED,\r
+ .portEMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTK_CONFIGURABLE == STD_ON )\r
+ .portKDirection = PORT_UNDEFINED,\r
+ .portKOutValue = PORT_UNDEFINED,\r
+ .portKMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTH_CONFIGURABLE == STD_ON )\r
+ .portHDirection = 0x0,\r
+ .portHOutValue = 0x0,\r
+ .portHMask = 0x0,\r
+ .portHPullEnableRegister = 0xFF,\r
+ .portHPullPolarityRegsiter = 0x0,\r
+ .portHReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ .portJDirection = 0x80,\r
+ .portJOutValue = 0xC0,\r
+ .portJMask = 0x40,\r
+ .portJPullEnableRegister = 0x0,\r
+ .portJPullPolarityRegsiter 0x0,\r
+ .portJReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTM_CONFIGURABLE == STD_ON )\r
+ .portMDirection = 0x0,\r
+ .portMOutValue = 0xC3,\r
+ .portMMask = 0x0,\r
+ .portMPullEnableRegister = 0x0,\r
+ .portMPullPolarityRegsiter = 0x0,\r
+ .portMWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portMReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTP_CONFIGURABLE == STD_ON )\r
+ .portPDirection = 0x3,\r
+ .portPOutValue = 0x0,\r
+ .portPMask = 0x0,\r
+ .portPPullEnableRegister = 0x0,\r
+ .portPPullPolarityRegsiter = 0x0,\r
+ .portPReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTS_CONFIGURABLE == STD_ON )\r
+ .portSDirection = 0x0,\r
+ .portSOutValue = 0xF,\r
+ .portSMask = 0x0,\r
+ .portSPullEnableRegister = 0x5,\r
+ .portSPullPolarityRegsiter = 0x0,\r
+ .portSWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portSReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTT_CONFIGURABLE == STD_ON )\r
+ .portTDirection = 0x4,\r
+ .portTOutValue = 0x3,\r
+ .portTMask = 0x0,\r
+ .portTPullEnableRegister = 0x0,\r
+ .portTPullPolarityRegsiter = 0x0,\r
+ .portTReducedDriveRegister = 0x0,\r
+ #endif\r
+};\r
+\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:54:45 CET 2011\r
+ */\r
+\r
+
+#if ((PORT_SW_MAJOR_VERSION != 1))
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+\r
+/** Parameter to enable/disable configuration on a port */\r
+#define PORTA_CONFIGURABLE STD_OFF\r
+#define PORTB_CONFIGURABLE STD_ON\r
+#define PORTE_CONFIGURABLE STD_OFF\r
+#define PORTK_CONFIGURABLE STD_OFF\r
+#define PORTH_CONFIGURABLE STD_ON\r
+#define PORTJ_CONFIGURABLE STD_ON\r
+#define PORTM_CONFIGURABLE STD_ON\r
+#define PORTP_CONFIGURABLE STD_ON\r
+#define PORTS_CONFIGURABLE STD_ON\r
+#define PORTT_CONFIGURABLE STD_ON\r
+\r
+#define PORT_A_BASE 0x0100\r
+#define PORT_B_BASE 0x0200\r
+#define PORT_E_BASE 0x0300\r
+#define PORT_K_BASE 0x0400\r
+#define PORT_H_BASE 0x0500\r
+#define PORT_J_BASE 0x0600\r
+#define PORT_M_BASE 0x0700\r
+#define PORT_P_BASE 0x0800\r
+#define PORT_S_BASE 0x0900\r
+#define PORT_T_BASE 0x0A00\r
+#define PORT_BITMASK 0x00FF\r
+#define PORT_BASEMASK 0xFF00;\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum\r
+{\r
+ PORT_PA0 = PORT_A_BASE,\r
+ PORT_PA1,\r
+ PORT_PA2,\r
+ PORT_PA3,\r
+ PORT_PA4,\r
+ PORT_PA5,\r
+ PORT_PA6,\r
+ PORT_PA7,\r
+ PORT_PB0 = PORT_B_BASE,\r
+ PORT_PB1,\r
+ PORT_PB2,\r
+ PORT_PB3,\r
+ PORT_PB4,\r
+ PORT_PB5,\r
+ PORT_PB6,\r
+ PORT_PB7,\r
+ PORT_PE0 = PORT_E_BASE,\r
+ PORT_PE1,\r
+ PORT_PE2,\r
+ PORT_PE3,\r
+ PORT_PE4,\r
+ PORT_PE5,\r
+ PORT_PE6,\r
+ PORT_PE7,\r
+ PORT_PH0 = PORT_H_BASE,\r
+ PORT_PH1,\r
+ PORT_PH2,\r
+ PORT_PH3,\r
+ PORT_PH4,\r
+ PORT_PH5,\r
+ PORT_PH6,\r
+ PORT_PH7,\r
+ PORT_PJ0 = PORT_J_BASE,\r
+ PORT_PJ1,\r
+ PORT_PJ2,\r
+ PORT_PJ3,\r
+ PORT_PJ4,\r
+ PORT_PJ5,\r
+ PORT_PJ6,\r
+ PORT_PJ7,\r
+ PORT_PK0 = PORT_K_BASE,\r
+ PORT_PK1,\r
+ PORT_PK2,\r
+ PORT_PK3,\r
+ PORT_PK4,\r
+ PORT_PK5,\r
+ PORT_PK6,\r
+ PORT_PK7,\r
+ PORT_PM0 = PORT_M_BASE,\r
+ PORT_PM1,\r
+ PORT_PM2,\r
+ PORT_PM3,\r
+ PORT_PM4,\r
+ PORT_PM5,\r
+ PORT_PM6,\r
+ PORT_PM7,\r
+ PORT_PP0 = PORT_P_BASE,\r
+ PORT_PP1,\r
+ PORT_PP2,\r
+ PORT_PP3,\r
+ PORT_PP4,\r
+ PORT_PP5,\r
+ PORT_PP6,\r
+ PORT_PP7,\r
+ PORT_PS0 = PORT_S_BASE,\r
+ PORT_PS1,\r
+ PORT_PS2,\r
+ PORT_PS3,\r
+ PORT_PS4,\r
+ PORT_PS5,\r
+ PORT_PS6,\r
+ PORT_PS7,\r
+ PORT_PT0 = PORT_T_BASE,\r
+ PORT_PT1,\r
+ PORT_PT2,\r
+ PORT_PT3,\r
+ PORT_PT4,\r
+ PORT_PT5,\r
+ PORT_PT6,\r
+ PORT_PT7,\r
+} Port_PinType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct\r
+{\r
+ const uint8_t corePullUpRegister; // PUCR\r
+ const uint8_t coreReducedDriveRegister; // RDRIV\r
+ const uint8_t modeRoutingRegister; // MODRR\r
+\r
+ /**\r
+ * Every port has:\r
+ * a direction (input or output)\r
+ * a default out value\r
+ * a mask that is 0 if the direction is allowed to change during runtime\r
+ *\r
+ * Some ports have:\r
+ * a reduced drive conf (power saving)\r
+ * a pull enable conf (enable pull-up/pull-down\r
+ * a pull direction conf (pull-up or pull-down)\r
+ * a wired mode (enable open drain outputs)\r
+ */\r
+#if ( PORTA_CONFIGURABLE == STD_ON )\r
+ const uint8_t portADirection;\r
+ const uint8_t portAOutValue;\r
+ const uint8_t portAMask;\r
+#endif\r
+\r
+#if ( PORTB_CONFIGURABLE == STD_ON )\r
+ const uint8_t portBDirection;\r
+ const uint8_t portBOutValue;\r
+ const uint8_t portBMask;\r
+#endif\r
+\r
+#if ( PORTE_CONFIGURABLE == STD_ON )\r
+ const uint8_t portEDirection;\r
+ const uint8_t portEOutValue;\r
+ const uint8_t portEMask;\r
+#endif\r
+\r
+#if ( PORTK_CONFIGURABLE == STD_ON )\r
+ const uint8_t portKDirection;\r
+ const uint8_t portKOutValue;\r
+ const uint8_t portKMask;\r
+#endif\r
+\r
+#if ( PORTH_CONFIGURABLE == STD_ON )\r
+ const uint8_t portHDirection;\r
+ const uint8_t portHOutValue;\r
+ const uint8_t portHMask;\r
+ const uint8_t portHPullEnableRegister;\r
+ const uint8_t portHPullPolarityRegsiter;\r
+ const uint8_t portHReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ const uint8_t portJDirection;\r
+ const uint8_t portJOutValue;\r
+ const uint8_t portJMask;\r
+ const uint8_t portJPullEnableRegister;\r
+ const uint8_t portJPullPolarityRegsiter;\r
+ const uint8_t portJReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTM_CONFIGURABLE == STD_ON )\r
+ const uint8_t portMDirection;\r
+ const uint8_t portMOutValue;\r
+ const uint8_t portMMask;\r
+ const uint8_t portMPullEnableRegister;\r
+ const uint8_t portMPullPolarityRegsiter;\r
+ const uint8_t portMWiredModeRegsiter;\r
+ const uint8_t portMReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTP_CONFIGURABLE == STD_ON )\r
+ const uint8_t portPDirection;\r
+ const uint8_t portPOutValue;\r
+ const uint8_t portPMask;\r
+ const uint8_t portPPullEnableRegister;\r
+ const uint8_t portPPullPolarityRegsiter;\r
+ const uint8_t portPReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTS_CONFIGURABLE == STD_ON )\r
+ const uint8_t portSDirection;\r
+ const uint8_t portSOutValue;\r
+ const uint8_t portSMask;\r
+ const uint8_t portSPullEnableRegister;\r
+ const uint8_t portSPullPolarityRegsiter;\r
+ const uint8_t portSWiredModeRegsiter;\r
+ const uint8_t portSReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTT_CONFIGURABLE == STD_ON )\r
+ const uint8_t portTDirection;\r
+ const uint8_t portTOutValue;\r
+ const uint8_t portTMask;\r
+ const uint8_t portTPullEnableRegister;\r
+ const uint8_t portTPullPolarityRegsiter;\r
+ const uint8_t portTReducedDriveRegister;\r
+#endif\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_SDA PORT_PJ6 \r
+#define PORT_PIN_NAME_SCL PORT_PJ7 \r
+#define PORT_PIN_NAME_TXD PORT_PM1 \r
+#define PORT_PIN_NAME_RXD PORT_PM0 \r
+#define PORT_PIN_NAME_PB0 PORT_PB0 \r
+#define PORT_PIN_NAME_PB1 PORT_PB1 \r
+#define PORT_PIN_NAME_PB2 PORT_PB2 \r
+#define PORT_PIN_NAME_PB3 PORT_PB3 \r
+#define PORT_PIN_NAME_PB4 PORT_PB4 \r
+#define PORT_PIN_NAME_PB5 PORT_PB5 \r
+#define PORT_PIN_NAME_PB6 PORT_PB6 \r
+#define PORT_PIN_NAME_PB7 PORT_PB7 \r
+#define PORT_PIN_NAME_PH0 PORT_PH0 \r
+#define PORT_PIN_NAME_PH1 PORT_PH1 \r
+#define PORT_PIN_NAME_PH2 PORT_PH2 \r
+#define PORT_PIN_NAME_PH3 PORT_PH3 \r
+#define PORT_PIN_NAME_PH4 PORT_PH4 \r
+#define PORT_PIN_NAME_PH5 PORT_PH5 \r
+#define PORT_PIN_NAME_PH6 PORT_PH6 \r
+#define PORT_PIN_NAME_PH7 PORT_PH7 \r
+#define PORT_PIN_NAME_PT0 PORT_PT0 \r
+#define PORT_PIN_NAME_PT1 PORT_PT1 \r
+#define PORT_PIN_NAME_BEEPER PORT_PT2 \r
+#define PORT_PIN_NAME_PP0 PORT_PP0 \r
+#define PORT_PIN_NAME_PP1 PORT_PP1 \r
+#define PORT_PIN_NAME_RXD0 PORT_PS0 \r
+#define PORT_PIN_NAME_TXD0 PORT_PS1 \r
+#define PORT_PIN_NAME_RXD1 PORT_PS2 \r
+#define PORT_PIN_NAME_TXD1 PORT_PS3 \r
+#define PORT_PIN_NAME_PM6 PORT_PM6 \r
+#define PORT_PIN_NAME_PM7 PORT_PM7 \r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:54:45 CET 2011\r
+ */\r
+\r
+\r
+#include "Pwm.h"\r
+\r
+const Pwm_ConfigType PwmConfig =\r
+{\r
+ .channels = { \r
+ {\r
+ .channel = PWM_CHANNEL_1,\r
+ DUTY_AND_PERIOD(24576,188.0),\r
+ .centerAlign = STD_OFF,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = STD_ON,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD\r
+ }, \r
+ {\r
+ .channel = PWM_CHANNEL_2,\r
+ DUTY_AND_PERIOD(0,188.0),\r
+ .centerAlign = STD_OFF,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = STD_ON,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD\r
+ },\r
+ },\r
+ .busPrescalerA = PRESCALER_128,\r
+ .busPrescalerB = PRESCALER_2,\r
+ .prescalerA = 1,\r
+ .prescalerB = 1,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 16:54:45 CET 2011\r
+ */\r
+\r
+
+#if ((PWM_SW_MAJOR_VERSION != 1))
+#error "Pwm: Configuration file version differs from BSW version."
+#endif
+
+ \r
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+#define PWM_DEV_ERROR_DETECT STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_OFF\r
+#define PWM_FREEZE_ENABLE STD_OFF\r
+\r
+// Define what API functions to enable.\r
+#define PWM_GET_OUTPUT_STATE STD_ON\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+#define PWM_DEINIT STD_OFF\r
+#define PWM_DUTYCYCLE STD_ON\r
+#define PWM_SET_OUTPUT_TO_IDLE STD_OFF\r
+#define PWM_VERSION_INFO_API STD_OFF\r
+\r
+\r
+\r
+/**\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/**\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == channel id.\r
+ */\r
+typedef uint8 Pwm_ChannelType;\r
+\r
+/**\r
+ * PWM070: All time units used within the API services of the PWM module shall\r
+ * be of the unit ticks.\r
+ */\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_1 = 1 ,\r
+ PWM_CHANNEL_2 = 0 ,\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+/* 1 =PWMchannel output is high at the beginning of the period, then goes low when the duty count\r
+is reached. */\r
+#define POLARITY_NORMAL 1\r
+#define POLARITY_INVERSED 0\r
+\r
+/**\r
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,\r
+ * the following macro can be used to convert between that format and the\r
+ * driver format.\r
+ */\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (uint8)((uint32)((uint32)_duty*(uint32)_period)>>15), .period = _period\r
+\r
+\r
+typedef struct {\r
+ /** Number of duty ticks */\r
+ uint8_t duty;\r
+ /** Length of period, in ticks */\r
+ uint8_t period;\r
+ /** Center or left align */\r
+ uint8_t centerAlign:1;\r
+ /** Polarity of the channel */\r
+ uint8_t polarity:1;\r
+ /** Scaled clock enabled */\r
+ uint8_t scaledClockEnable:1;\r
+ /** idle state */\r
+ uint8_t idleState:1;\r
+\r
+ uint8_t reserved:4;\r
+\r
+ Pwm_ChannelClassType class;\r
+\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+typedef enum{\r
+ PRESCALER_1 = 0,\r
+ PRESCALER_2 = 1,\r
+ PRESCALER_4 = 2,\r
+ PRESCALER_8 = 3,\r
+ PRESCALER_16 = 4,\r
+ PRESCALER_32 = 5,\r
+ PRESCALER_64 = 6,\r
+ PRESCALER_128 = 7,\r
+}Pwm_PrescalerType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType channels[PWM_NUMBER_OF_CHANNELS];\r
+ Pwm_PrescalerType busPrescalerA;\r
+ Pwm_PrescalerType busPrescalerB;\r
+ uint8_t prescalerA;\r
+ uint8_t prescalerB;\r
+} Pwm_ConfigType;\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
*/\r
\r
\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )\r
#error "Os: Configuration file version differs from BSW version."\r
#endif\r
\r
\r
\r
\r
+#include "Port.h"\r
#include "Port_Cfg.h"\r
\r
// All: PA,OBE,IBE,ODE,HYS,SRC,WPE,WPS\r
// Input: PA,OBE,IBE,HYS,WPE,WPS\r
// Output: PA,OBE,IBE,ODE,SRC,(WPE,WPS)\r
\r
-#define PCR_PWM PCR_BOOTCFG\r
+#define PCR_PWM PORT_PCR_BOOTCFG\r
#define PCR_ADC (0)\r
-#define PCR_IO_INPUT PCR_BOOTCFG\r
-#define PCR_IO_OUTPUT OBE_ENABLE\r
-#define PCR_CAN (0)\r
-#define PCR_SPI PCR_BOOTCFG\r
-#define PCR_I2C PCR_BOOTCFG\r
+#define PCR_IO_INPUT PORT_PCR_BOOTCFG\r
+#define PCR_IO_OUTPUT PORT_OBE_ENABLE\r
+#define PCR_CAN (0)\r
+#define PCR_SPI PORT_PCR_BOOTCFG\r
+#define PCR_I2C PORT_PCR_BOOTCFG\r
\r
const uint16_t PortPadConfigData[] =\r
{\r
// pad 0-15\r
- PCR_RESET, /* PA0, AN0 */\r
- PCR_RESET, /* PA1 */\r
- PCR_RESET, /* PA2 */\r
- PCR_RESET, /* PA3 */\r
- PCR_RESET, /* PA4 */\r
- PCR_RESET, /* PA5 */\r
- PCR_RESET, /* PA6, */\r
- PCR_RESET, /* PA7(input only) */\r
- PCR_RESET, /* PA8(input only) */\r
- PCR_RESET, /* PA9(input only) */\r
- PCR_RESET, /* PA10(input only) */\r
- PCR_RESET, /* PA11(input only) */\r
- PCR_RESET, /* PA12(input only) */\r
- PCR_RESET, /* PA13(input only) */\r
- PCR_RESET, /* PA14(input only) */\r
- PCR_RESET, /* PA15(input only) */\r
+ PORT_PCR_RESET, /* PA0, AN0 */\r
+ PORT_PCR_RESET, /* PA1 */\r
+ PORT_PCR_RESET, /* PA2 */\r
+ PORT_PCR_RESET, /* PA3 */\r
+ PORT_PCR_RESET, /* PA4 */\r
+ PORT_PCR_RESET, /* PA5 */\r
+ PORT_PCR_RESET, /* PA6, */\r
+ PORT_PCR_RESET, /* PA7(input only) */\r
+ PORT_PCR_RESET, /* PA8(input only) */\r
+ PORT_PCR_RESET, /* PA9(input only) */\r
+ PORT_PCR_RESET, /* PA10(input only) */\r
+ PORT_PCR_RESET, /* PA11(input only) */\r
+ PORT_PCR_RESET, /* PA12(input only) */\r
+ PORT_PCR_RESET, /* PA13(input only) */\r
+ PORT_PCR_RESET, /* PA14(input only) */\r
+ PORT_PCR_RESET, /* PA15(input only) */\r
\r
// pad 16-31\r
- PCR_RESET, /* PB0 */\r
- PCR_RESET, /* PB1 */\r
- PCR_RESET, /* PB2 */\r
- PCR_RESET, /* PB3 */\r
- PCR_RESET, /* PB4 */\r
- PCR_RESET, /* PB5 */\r
- PCR_RESET, /* PB6 */\r
- PCR_RESET, /* PB7 */\r
- PCR_RESET, /* PB8 */\r
- PCR_RESET, /* PB9 */\r
- PCR_RESET, /* PB10 */\r
- PCR_RESET, /* PB11 */\r
- PCR_RESET, /* PB12 */\r
- PCR_RESET, /* PB13 */\r
- PCR_RESET, /* PB14 */\r
- PCR_RESET, /* PB15 */\r
+ PORT_PCR_RESET, /* PB0 */\r
+ PORT_PCR_RESET, /* PB1 */\r
+ PORT_PCR_RESET, /* PB2 */\r
+ PORT_PCR_RESET, /* PB3 */\r
+ PORT_PCR_RESET, /* PB4 */\r
+ PORT_PCR_RESET, /* PB5 */\r
+ PORT_PCR_RESET, /* PB6 */\r
+ PORT_PCR_RESET, /* PB7 */\r
+ PORT_PCR_RESET, /* PB8 */\r
+ PORT_PCR_RESET, /* PB9 */\r
+ PORT_PCR_RESET, /* PB10 */\r
+ PORT_PCR_RESET, /* PB11 */\r
+ PORT_PCR_RESET, /* PB12 */\r
+ PORT_PCR_RESET, /* PB13 */\r
+ PORT_PCR_RESET, /* PB14 */\r
+ PORT_PCR_RESET, /* PB15 */\r
\r
// pad 32-47\r
- PA_FUNC1|OBE_ENABLE, /* PC0/emios0 */\r
- PCR_RESET, // PC1\r
- PCR_RESET, // PC2\r
- PA_FUNC1|OBE_ENABLE, /* PC3 emios3, pin 117 */\r
- PCR_RESET, /* PC4 */\r
- PCR_RESET, /* PC5 */\r
- PCR_RESET, /* PC6 */\r
- PCR_RESET, /* PC7 */\r
- PCR_RESET, /* PC8 */\r
- PCR_RESET, /* PC9 */\r
- PCR_RESET, /* PC10 */\r
- PCR_RESET, /* PC11 */\r
- PCR_RESET, /* PC12 */\r
- PCR_RESET, /* PC13 */\r
- PCR_RESET, /* PC14 */\r
- PCR_RESET, /* PC15 */\r
+ PORT_PA_FUNC1|PORT_OBE_ENABLE, /* PC0/emios0 */\r
+ PORT_PCR_RESET, // PC1\r
+ PORT_PCR_RESET, // PC2\r
+ PORT_PA_FUNC1|PORT_OBE_ENABLE, /* PC3 emios3, pin 117 */\r
+ PORT_PCR_RESET, /* PC4 */\r
+ PORT_PCR_RESET, /* PC5 */\r
+ PORT_PCR_RESET, /* PC6 */\r
+ PORT_PCR_RESET, /* PC7 */\r
+ PORT_PCR_RESET, /* PC8 */\r
+ PORT_PCR_RESET, /* PC9 */\r
+ PORT_PCR_RESET, /* PC10 */\r
+ PORT_PCR_RESET, /* PC11 */\r
+ PORT_PCR_RESET, /* PC12 */\r
+ PORT_PCR_RESET, /* PC13 */\r
+ PORT_PCR_RESET, /* PC14 */\r
+ PORT_PCR_RESET, /* PC15 */\r
\r
// pad 48-63\r
- PCR_RESET, /* PD0, CAN_A, Tx */\r
- PCR_RESET, /* PD1, CAN_A, Rx */\r
- PCR_BOOTCFG, /* PD2 */\r
- PCR_RESET, /* PD3 */\r
- PA_FUNC2|OBE_ENABLE, /* PD4, LED */\r
- PA_FUNC2|OBE_ENABLE, /* PD5, LED */\r
- PCR_RESET, /* PD6 , SCI_RS232??*/\r
- PCR_RESET, /* PD7 , SCI_RS232??*/\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD8 LIN TX */\r
- (PA_FUNC1 | IBE_ENABLE), /* PD9 LIN RX */\r
- PCR_RESET, /* PD10 */\r
- PCR_RESET, /* PD11 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD12 SPIB_CS0 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD13 SPIB_CLK*/\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PD14 SPIB_SO*/\r
- (PA_FUNC1 | IBE_ENABLE), /* PD15 SPIB_SI*/\r
+ PORT_PCR_RESET, /* PD0, CAN_A, Tx */\r
+ PORT_PCR_RESET, /* PD1, CAN_A, Rx */\r
+ PORT_PCR_BOOTCFG, /* PD2 */\r
+ PORT_PCR_RESET, /* PD3 */\r
+ PORT_PA_FUNC2|PORT_OBE_ENABLE, /* PD4, LED */\r
+ PORT_PA_FUNC2|PORT_OBE_ENABLE, /* PD5, LED */\r
+ PORT_PCR_RESET, /* PD6 , SCI_RS232??*/\r
+ PORT_PCR_RESET, /* PD7 , SCI_RS232??*/\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD8 LIN TX */\r
+ (PORT_PA_FUNC1 | PORT_IBE_ENABLE), /* PD9 LIN RX */\r
+ PORT_PCR_RESET, /* PD10 */\r
+ PORT_PCR_RESET, /* PD11 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD12 SPIB_CS0 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD13 SPIB_CLK*/\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PD14 SPIB_SO*/\r
+ (PORT_PA_FUNC1 | PORT_IBE_ENABLE), /* PD15 SPIB_SI*/\r
\r
// pad 64-79\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE0 SPIA_CS1 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE1 SPIA_CS2*/\r
- PCR_RESET, /* PE2 */\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE3 SPIA_CLK*/\r
- (PA_FUNC1 | OBE_ENABLE | SLEW_RATE_MAX), /* PE4 SPIA_SO*/\r
- (PA_FUNC1 | IBE_ENABLE), /* PE5 SPIA_SI*/\r
- PCR_RESET, /* PE6 */\r
- PCR_RESET, /* PE7 */\r
- PCR_RESET, /* PE8 */\r
- PCR_RESET, /* PE9 */\r
- PCR_RESET, /* PE10 */\r
- PCR_RESET, /* PE11 */\r
- PCR_RESET, /* PE12 */\r
- PCR_RESET, /* PE13 */\r
- PCR_RESET, /* PE14 */\r
- PCR_RESET, /* PE15 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE0 SPIA_CS1 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE1 SPIA_CS2*/\r
+ PORT_PCR_RESET, /* PE2 */\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE3 SPIA_CLK*/\r
+ (PORT_PA_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MAX), /* PE4 SPIA_SO*/\r
+ (PORT_PA_FUNC1 | PORT_IBE_ENABLE), /* PE5 SPIA_SI*/\r
+ PORT_PCR_RESET, /* PE6 */\r
+ PORT_PCR_RESET, /* PE7 */\r
+ PORT_PCR_RESET, /* PE8 */\r
+ PORT_PCR_RESET, /* PE9 */\r
+ PORT_PCR_RESET, /* PE10 */\r
+ PORT_PCR_RESET, /* PE11 */\r
+ PORT_PCR_RESET, /* PE12 */\r
+ PORT_PCR_RESET, /* PE13 */\r
+ PORT_PCR_RESET, /* PE14 */\r
+ PORT_PCR_RESET, /* PE15 */\r
\r
// pad 80-95\r
- PCR_RESET, /* PF0 */\r
- PCR_RESET, /* PF1 */\r
- PCR_RESET, /* PF2 */\r
- PCR_RESET, /* PF3 */\r
- PCR_RESET, /* PF4 */\r
- PCR_RESET, /* PF5 */\r
- PCR_RESET, /* PF6 */\r
- PCR_RESET, /* PF7 */\r
- PCR_RESET, /* PF8 */\r
- PCR_RESET, /* PF9 */\r
- PCR_RESET, /* PF10 */\r
- PCR_RESET, /* PF11 */\r
- PA_FUNC2|OBE_ENABLE|PULL_UP, /* PF12 SCI_D Transmit, J1708 Tx*/\r
- PA_FUNC2|IBE_ENABLE|PULL_UP, /* PF13 SCI_D Receive, J1708 Rx*/\r
- PCR_RESET, /* PF14 */\r
- PCR_RESET, /* PF15 */\r
+ PORT_PCR_RESET, /* PF0 */\r
+ PORT_PCR_RESET, /* PF1 */\r
+ PORT_PCR_RESET, /* PF2 */\r
+ PORT_PCR_RESET, /* PF3 */\r
+ PORT_PCR_RESET, /* PF4 */\r
+ PORT_PCR_RESET, /* PF5 */\r
+ PORT_PCR_RESET, /* PF6 */\r
+ PORT_PCR_RESET, /* PF7 */\r
+ PORT_PCR_RESET, /* PF8 */\r
+ PORT_PCR_RESET, /* PF9 */\r
+ PORT_PCR_RESET, /* PF10 */\r
+ PORT_PCR_RESET, /* PF11 */\r
+ PORT_PA_FUNC2|PORT_OBE_ENABLE|PORT_PULL_UP, /* PF12 SCI_D Transmit, J1708 Tx*/\r
+ PORT_PA_FUNC2|PORT_IBE_ENABLE|PORT_PULL_UP, /* PF13 SCI_D Receive, J1708 Rx*/\r
+ PORT_PCR_RESET, /* PF14 */\r
+ PORT_PCR_RESET, /* PF15 */\r
\r
// pad 96-111\r
- PCR_RESET, /* PG0 */\r
- PA_FUNC2|IBE_ENABLE|PULL_UP, /* PG1 eMIOS[17], J1708 Edgedetect*/\r
- PCR_RESET, /* PG2 */\r
- PCR_RESET, /* PG3 */\r
- PCR_RESET, /* PG4 */\r
- PCR_RESET, /* PG5 */\r
- PCR_RESET, /* PG6 */\r
- PCR_RESET, /* PG7 */\r
- PCR_RESET, /* PG8 */\r
- PCR_RESET, /* PG9 */\r
- PCR_RESET, /* PG10 */\r
- PCR_RESET, /* PG11 */\r
- PCR_RESET, /* PG12 */\r
- PCR_RESET, /* PG13 */\r
- PCR_RESET, /* PG14 */\r
- PCR_RESET, /* PG15 */\r
+ PORT_PCR_RESET, /* PG0 */\r
+ PORT_PA_FUNC2|PORT_IBE_ENABLE|PORT_PULL_UP, /* PG1 eMIOS[17], J1708 Edgedetect*/\r
+ PORT_PCR_RESET, /* PG2 */\r
+ PORT_PCR_RESET, /* PG3 */\r
+ PORT_PCR_RESET, /* PG4 */\r
+ PORT_PCR_RESET, /* PG5 */\r
+ PORT_PCR_RESET, /* PG6 */\r
+ PORT_PCR_RESET, /* PG7 */\r
+ PORT_PCR_RESET, /* PG8 */\r
+ PORT_PCR_RESET, /* PG9 */\r
+ PORT_PCR_RESET, /* PG10 */\r
+ PORT_PCR_RESET, /* PG11 */\r
+ PORT_PCR_RESET, /* PG12 */\r
+ PORT_PCR_RESET, /* PG13 */\r
+ PORT_PCR_RESET, /* PG14 */\r
+ PORT_PCR_RESET, /* PG15 */\r
\r
// pad 112-127\r
- PCR_RESET, /* PH0 */\r
- PCR_RESET, /* PH1 */\r
- PCR_RESET, /* PH2 */\r
- PCR_RESET, /* PH3 */\r
- PCR_RESET, /* PH4 */\r
- PCR_RESET, /* PH5 */\r
- PCR_RESET, /* PH6 */\r
- PCR_RESET, /* PH7 */\r
- PCR_RESET, /* PH8 */\r
- PCR_RESET, /* PH9 */\r
- PCR_RESET, /* PH10 */\r
- PCR_RESET, /* PH11 */\r
- PCR_RESET, /* PH12 */\r
- PCR_RESET, /* PH13 */\r
- PCR_RESET, /* PH14 */\r
- PCR_RESET, /* PH15 */\r
+ PORT_PCR_RESET, /* PH0 */\r
+ PORT_PCR_RESET, /* PH1 */\r
+ PORT_PCR_RESET, /* PH2 */\r
+ PORT_PCR_RESET, /* PH3 */\r
+ PORT_PCR_RESET, /* PH4 */\r
+ PORT_PCR_RESET, /* PH5 */\r
+ PORT_PCR_RESET, /* PH6 */\r
+ PORT_PCR_RESET, /* PH7 */\r
+ PORT_PCR_RESET, /* PH8 */\r
+ PORT_PCR_RESET, /* PH9 */\r
+ PORT_PCR_RESET, /* PH10 */\r
+ PORT_PCR_RESET, /* PH11 */\r
+ PORT_PCR_RESET, /* PH12 */\r
+ PORT_PCR_RESET, /* PH13 */\r
+ PORT_PCR_RESET, /* PH14 */\r
+ PORT_PCR_RESET, /* PH15 */\r
\r
// pad 128-143\r
- PCR_RESET, /* PJ0 */\r
- PCR_RESET, /* PJ1 */\r
- PCR_RESET, /* PJ2 */\r
- PCR_RESET, /* PJ3 */\r
- PCR_RESET, /* PJ4 */\r
- PCR_RESET, /* PJ5 */\r
- PCR_RESET, /* PJ6 */\r
- PCR_RESET, /* PJ7 */\r
- PCR_RESET, /* PJ8 */\r
- PCR_RESET, /* PJ9 */\r
- PCR_RESET, /* PJ10 */\r
- PCR_RESET, /* PJ11 */\r
- PCR_RESET, /* PJ12 */\r
- PCR_RESET, /* PJ13 */\r
- PCR_RESET, /* PJ14 */\r
- PCR_RESET, /* PJ15 */\r
+ PORT_PCR_RESET, /* PJ0 */\r
+ PORT_PCR_RESET, /* PJ1 */\r
+ PORT_PCR_RESET, /* PJ2 */\r
+ PORT_PCR_RESET, /* PJ3 */\r
+ PORT_PCR_RESET, /* PJ4 */\r
+ PORT_PCR_RESET, /* PJ5 */\r
+ PORT_PCR_RESET, /* PJ6 */\r
+ PORT_PCR_RESET, /* PJ7 */\r
+ PORT_PCR_RESET, /* PJ8 */\r
+ PORT_PCR_RESET, /* PJ9 */\r
+ PORT_PCR_RESET, /* PJ10 */\r
+ PORT_PCR_RESET, /* PJ11 */\r
+ PORT_PCR_RESET, /* PJ12 */\r
+ PORT_PCR_RESET, /* PJ13 */\r
+ PORT_PCR_RESET, /* PJ14 */\r
+ PORT_PCR_RESET, /* PJ15 */\r
\r
// pad 144-145\r
- PCR_RESET, /* PK0 (input only) */\r
- PCR_RESET, /* PK1 (input only)*/\r
+ PORT_PCR_RESET, /* PK0 (input only) */\r
+ PORT_PCR_RESET, /* PK1 (input only)*/\r
};\r
\r
-#define GPDO_RESET 0\r
+#define PORT_GPDO_RESET 0\r
\r
const uint8_t PortOutConfigData[] =\r
{\r
// pad 16-31\r
- GPDO_RESET, /* PB0 */\r
- GPDO_RESET, /* PB1 */\r
- GPDO_RESET, /* PB2 */\r
- GPDO_RESET, /* PB3 */\r
- GPDO_RESET, /* PB4 */\r
- GPDO_RESET, /* PB5 */\r
- GPDO_RESET, /* PB6 */\r
- GPDO_RESET, /* PB7 */\r
- GPDO_RESET, /* PB8 */\r
- GPDO_RESET, /* PB9 */\r
- GPDO_RESET, /* PB10 */\r
- GPDO_RESET, /* PB11 */\r
- GPDO_RESET, /* PB12 */\r
- GPDO_RESET, /* PB13 */\r
- GPDO_RESET, /* PB14 */\r
- GPDO_RESET, /* PB15 */\r
+ PORT_GPDO_RESET, /* PB0 */\r
+ PORT_GPDO_RESET, /* PB1 */\r
+ PORT_GPDO_RESET, /* PB2 */\r
+ PORT_GPDO_RESET, /* PB3 */\r
+ PORT_GPDO_RESET, /* PB4 */\r
+ PORT_GPDO_RESET, /* PB5 */\r
+ PORT_GPDO_RESET, /* PB6 */\r
+ PORT_GPDO_RESET, /* PB7 */\r
+ PORT_GPDO_RESET, /* PB8 */\r
+ PORT_GPDO_RESET, /* PB9 */\r
+ PORT_GPDO_RESET, /* PB10 */\r
+ PORT_GPDO_RESET, /* PB11 */\r
+ PORT_GPDO_RESET, /* PB12 */\r
+ PORT_GPDO_RESET, /* PB13 */\r
+ PORT_GPDO_RESET, /* PB14 */\r
+ PORT_GPDO_RESET, /* PB15 */\r
\r
// pad 32-47\r
- GPDO_RESET, /* PC0 */\r
- GPDO_RESET, /* PC1 */\r
- GPDO_RESET, /* PC2 */\r
- GPDO_RESET, /* PC3 */\r
- GPDO_RESET, /* PC4 */\r
- GPDO_RESET, /* PC5 */\r
- GPDO_RESET, /* PC6 */\r
- GPDO_RESET, /* PC7 */\r
- GPDO_RESET, /* PC8 */\r
- GPDO_RESET, /* PC9 */\r
- GPDO_RESET, /* PC10 */\r
- GPDO_RESET, /* PC11 */\r
- GPDO_RESET, /* PC12 */\r
- GPDO_RESET, /* PC13 */\r
- GPDO_RESET, /* PC14 */\r
- GPDO_RESET, /* PC15 */\r
+ PORT_GPDO_RESET, /* PC0 */\r
+ PORT_GPDO_RESET, /* PC1 */\r
+ PORT_GPDO_RESET, /* PC2 */\r
+ PORT_GPDO_RESET, /* PC3 */\r
+ PORT_GPDO_RESET, /* PC4 */\r
+ PORT_GPDO_RESET, /* PC5 */\r
+ PORT_GPDO_RESET, /* PC6 */\r
+ PORT_GPDO_RESET, /* PC7 */\r
+ PORT_GPDO_RESET, /* PC8 */\r
+ PORT_GPDO_RESET, /* PC9 */\r
+ PORT_GPDO_RESET, /* PC10 */\r
+ PORT_GPDO_RESET, /* PC11 */\r
+ PORT_GPDO_RESET, /* PC12 */\r
+ PORT_GPDO_RESET, /* PC13 */\r
+ PORT_GPDO_RESET, /* PC14 */\r
+ PORT_GPDO_RESET, /* PC15 */\r
\r
// pad 48-63\r
- GPDO_RESET, /* PD0 */\r
- GPDO_RESET, /* PD1 */\r
- GPDO_RESET, /* PD2 */\r
- GPDO_RESET, /* PD3 */\r
- GPDO_RESET, /* PD4 */\r
- GPDO_RESET, /* PD5 */\r
- GPDO_RESET, /* PD6 */\r
- GPDO_RESET, /* PD7 */\r
- GPDO_RESET, /* PD8 */\r
- GPDO_RESET, /* PD9 */\r
- GPDO_RESET, /* PD10 */\r
- GPDO_RESET, /* PD11 */\r
- GPDO_RESET, /* PD12 */\r
- GPDO_RESET, /* PD13 */\r
- GPDO_RESET, /* PD14 */\r
- GPDO_RESET, /* PD15 */\r
+ PORT_GPDO_RESET, /* PD0 */\r
+ PORT_GPDO_RESET, /* PD1 */\r
+ PORT_GPDO_RESET, /* PD2 */\r
+ PORT_GPDO_RESET, /* PD3 */\r
+ PORT_GPDO_RESET, /* PD4 */\r
+ PORT_GPDO_RESET, /* PD5 */\r
+ PORT_GPDO_RESET, /* PD6 */\r
+ PORT_GPDO_RESET, /* PD7 */\r
+ PORT_GPDO_RESET, /* PD8 */\r
+ PORT_GPDO_RESET, /* PD9 */\r
+ PORT_GPDO_RESET, /* PD10 */\r
+ PORT_GPDO_RESET, /* PD11 */\r
+ PORT_GPDO_RESET, /* PD12 */\r
+ PORT_GPDO_RESET, /* PD13 */\r
+ PORT_GPDO_RESET, /* PD14 */\r
+ PORT_GPDO_RESET, /* PD15 */\r
\r
// pad 64-79\r
- GPDO_RESET, /* PE0 */\r
- GPDO_RESET, /* PE1 */\r
- GPDO_RESET, /* PE2 */\r
- GPDO_RESET, /* PE3 */\r
- GPDO_RESET, /* PE4 */\r
- GPDO_RESET, /* PE5 */\r
- GPDO_RESET, /* PE6 */\r
- GPDO_RESET, /* PE7 */\r
- GPDO_RESET, /* PE8 */\r
- GPDO_RESET, /* PE9 */\r
- GPDO_RESET, /* PE10 */\r
- GPDO_RESET, /* PE11 */\r
- GPDO_RESET, /* PE12 */\r
- GPDO_RESET, /* PE13 */\r
- GPDO_RESET, /* PE14 */\r
- GPDO_RESET, /* PE15 */\r
+ PORT_GPDO_RESET, /* PE0 */\r
+ PORT_GPDO_RESET, /* PE1 */\r
+ PORT_GPDO_RESET, /* PE2 */\r
+ PORT_GPDO_RESET, /* PE3 */\r
+ PORT_GPDO_RESET, /* PE4 */\r
+ PORT_GPDO_RESET, /* PE5 */\r
+ PORT_GPDO_RESET, /* PE6 */\r
+ PORT_GPDO_RESET, /* PE7 */\r
+ PORT_GPDO_RESET, /* PE8 */\r
+ PORT_GPDO_RESET, /* PE9 */\r
+ PORT_GPDO_RESET, /* PE10 */\r
+ PORT_GPDO_RESET, /* PE11 */\r
+ PORT_GPDO_RESET, /* PE12 */\r
+ PORT_GPDO_RESET, /* PE13 */\r
+ PORT_GPDO_RESET, /* PE14 */\r
+ PORT_GPDO_RESET, /* PE15 */\r
\r
// pad 80-95\r
- GPDO_RESET, /* PF0 */\r
- GPDO_RESET, /* PF1 */\r
- GPDO_RESET, /* PF2 */\r
- GPDO_RESET, /* PF3 */\r
- GPDO_RESET, /* PF4 */\r
- GPDO_RESET, /* PF5 */\r
- GPDO_RESET, /* PF6 */\r
- GPDO_RESET, /* PF7 */\r
- GPDO_RESET, /* PF8 */\r
- GPDO_RESET, /* PF9 */\r
- GPDO_RESET, /* PF10 */\r
- GPDO_RESET, /* PF11 */\r
- GPDO_RESET, /* PF12 */\r
- GPDO_RESET, /* PF13 */\r
- GPDO_RESET, /* PF14 */\r
- GPDO_RESET, /* PF15 */\r
+ PORT_GPDO_RESET, /* PF0 */\r
+ PORT_GPDO_RESET, /* PF1 */\r
+ PORT_GPDO_RESET, /* PF2 */\r
+ PORT_GPDO_RESET, /* PF3 */\r
+ PORT_GPDO_RESET, /* PF4 */\r
+ PORT_GPDO_RESET, /* PF5 */\r
+ PORT_GPDO_RESET, /* PF6 */\r
+ PORT_GPDO_RESET, /* PF7 */\r
+ PORT_GPDO_RESET, /* PF8 */\r
+ PORT_GPDO_RESET, /* PF9 */\r
+ PORT_GPDO_RESET, /* PF10 */\r
+ PORT_GPDO_RESET, /* PF11 */\r
+ PORT_GPDO_RESET, /* PF12 */\r
+ PORT_GPDO_RESET, /* PF13 */\r
+ PORT_GPDO_RESET, /* PF14 */\r
+ PORT_GPDO_RESET, /* PF15 */\r
\r
// pad 96-111\r
- GPDO_RESET, /* PG0 */\r
- GPDO_RESET, /* PG1 */\r
- GPDO_RESET, /* PG2 */\r
- GPDO_RESET, /* PG3 */\r
- GPDO_RESET, /* PG4 */\r
- GPDO_RESET, /* PG5 */\r
- GPDO_RESET, /* PG6 */\r
- GPDO_RESET, /* PG7 */\r
- GPDO_RESET, /* PG8 */\r
- GPDO_RESET, /* PG9 */\r
- GPDO_RESET, /* PG10 */\r
- GPDO_RESET, /* PG11 */\r
- GPDO_RESET, /* PG12 */\r
- GPDO_RESET, /* PG13 */\r
- GPDO_RESET, /* PG14 */\r
- GPDO_RESET, /* PG15 */\r
+ PORT_GPDO_RESET, /* PG0 */\r
+ PORT_GPDO_RESET, /* PG1 */\r
+ PORT_GPDO_RESET, /* PG2 */\r
+ PORT_GPDO_RESET, /* PG3 */\r
+ PORT_GPDO_RESET, /* PG4 */\r
+ PORT_GPDO_RESET, /* PG5 */\r
+ PORT_GPDO_RESET, /* PG6 */\r
+ PORT_GPDO_RESET, /* PG7 */\r
+ PORT_GPDO_RESET, /* PG8 */\r
+ PORT_GPDO_RESET, /* PG9 */\r
+ PORT_GPDO_RESET, /* PG10 */\r
+ PORT_GPDO_RESET, /* PG11 */\r
+ PORT_GPDO_RESET, /* PG12 */\r
+ PORT_GPDO_RESET, /* PG13 */\r
+ PORT_GPDO_RESET, /* PG14 */\r
+ PORT_GPDO_RESET, /* PG15 */\r
\r
// pad 112-127\r
- GPDO_RESET, /* PH0 */\r
- GPDO_RESET, /* PH1 */\r
- GPDO_RESET, /* PH2 */\r
- GPDO_RESET, /* PH3 */\r
- GPDO_RESET, /* PH4 */\r
- GPDO_RESET, /* PH5 */\r
- GPDO_RESET, /* PH6 */\r
- GPDO_RESET, /* PH7 */\r
- GPDO_RESET, /* PH8 */\r
- GPDO_RESET, /* PH9 */\r
- GPDO_RESET, /* PH10 */\r
- GPDO_RESET, /* PH11 */\r
- GPDO_RESET, /* PH12 */\r
- GPDO_RESET, /* PH13 */\r
- GPDO_RESET, /* PH14 */\r
- GPDO_RESET, /* PH15 */\r
+ PORT_GPDO_RESET, /* PH0 */\r
+ PORT_GPDO_RESET, /* PH1 */\r
+ PORT_GPDO_RESET, /* PH2 */\r
+ PORT_GPDO_RESET, /* PH3 */\r
+ PORT_GPDO_RESET, /* PH4 */\r
+ PORT_GPDO_RESET, /* PH5 */\r
+ PORT_GPDO_RESET, /* PH6 */\r
+ PORT_GPDO_RESET, /* PH7 */\r
+ PORT_GPDO_RESET, /* PH8 */\r
+ PORT_GPDO_RESET, /* PH9 */\r
+ PORT_GPDO_RESET, /* PH10 */\r
+ PORT_GPDO_RESET, /* PH11 */\r
+ PORT_GPDO_RESET, /* PH12 */\r
+ PORT_GPDO_RESET, /* PH13 */\r
+ PORT_GPDO_RESET, /* PH14 */\r
+ PORT_GPDO_RESET, /* PH15 */\r
\r
// pad 128-143\r
- GPDO_RESET, /* PJ0 */\r
- GPDO_RESET, /* PJ1 */\r
- GPDO_RESET, /* PJ2 */\r
- GPDO_RESET, /* PJ3 */\r
- GPDO_RESET, /* PJ4 */\r
- GPDO_RESET, /* PJ5 */\r
- GPDO_RESET, /* PJ6 */\r
- GPDO_RESET, /* PJ7 */\r
- GPDO_RESET, /* PJ8 */\r
- GPDO_RESET, /* PJ9 */\r
- GPDO_RESET, /* PJ10 */\r
- GPDO_RESET, /* PJ11 */\r
- GPDO_RESET, /* PJ12 */\r
- GPDO_RESET, /* PJ13 */\r
- GPDO_RESET, /* PJ14 */\r
- GPDO_RESET, /* PJ15 */\r
+ PORT_GPDO_RESET, /* PJ0 */\r
+ PORT_GPDO_RESET, /* PJ1 */\r
+ PORT_GPDO_RESET, /* PJ2 */\r
+ PORT_GPDO_RESET, /* PJ3 */\r
+ PORT_GPDO_RESET, /* PJ4 */\r
+ PORT_GPDO_RESET, /* PJ5 */\r
+ PORT_GPDO_RESET, /* PJ6 */\r
+ PORT_GPDO_RESET, /* PJ7 */\r
+ PORT_GPDO_RESET, /* PJ8 */\r
+ PORT_GPDO_RESET, /* PJ9 */\r
+ PORT_GPDO_RESET, /* PJ10 */\r
+ PORT_GPDO_RESET, /* PJ11 */\r
+ PORT_GPDO_RESET, /* PJ12 */\r
+ PORT_GPDO_RESET, /* PJ13 */\r
+ PORT_GPDO_RESET, /* PJ14 */\r
+ PORT_GPDO_RESET, /* PJ15 */\r
};\r
\r
//#define GPDI_RESET 0\r
\r
\r
\r
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )\r
+#error "Port: Configuration file version differs from BSW version."\r
+#endif\r
\r
\r
#ifndef PORT_CFG_H_\r
\r
#define PORT_VERSION_INFO_API STD_ON\r
#define PORT_DEV_ERROR_DETECT STD_ON\r
-#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_ON\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
\r
typedef enum\r
{\r
- PA0,\r
- PA1,\r
- PA2,\r
- PA3,\r
- PA4,\r
- PA5,\r
- PA6,\r
- PA7,\r
- PA8,\r
- PA9,\r
- PA10,\r
- PA11,\r
- PA12,\r
- PA13,\r
- PA14,\r
- PA15,\r
- PB0,\r
- PB1,\r
- PB2,\r
- PB3,\r
- PB4,\r
- PB5,\r
- PB6,\r
- PB7,\r
- PB8,\r
- PB9,\r
- PB10,\r
- PB11,\r
- PB12,\r
- PB13,\r
- PB14,\r
- PB15,\r
- PC0,\r
- PC1,\r
- PC2,\r
- PC3,\r
- PC4,\r
- PC5,\r
- PC6,\r
- PC7,\r
- PC8,\r
- PC9,\r
- PC10,\r
- PC11,\r
- PC12,\r
- PC13,\r
- PC14,\r
- PC15,\r
- PD0,\r
- PD1,\r
- PD2,\r
- PD3,\r
- PD4,\r
- PD5,\r
- PD6,\r
- PD7,\r
- PD8,\r
- PD9,\r
- PD10,\r
- PD11,\r
- PD12,\r
- PD13,\r
- PD14,\r
- PD15,\r
- PE0,\r
- PE1,\r
- PE2,\r
- PE3,\r
- PE4,\r
- PE5,\r
- PE6,\r
- PE7,\r
- PE8,\r
- PE9,\r
- PE10,\r
- PE11,\r
- PE12,\r
- PE13,\r
- PE14,\r
- PE15,\r
- PF0,\r
- PF1,\r
- PF2,\r
- PF3,\r
- PF4,\r
- PF5,\r
- PF6,\r
- PF7,\r
- PF8,\r
- PF9,\r
- PF10,\r
- PF11,\r
- PF12,\r
- PF13,\r
- PF14,\r
- PF15,\r
- PG0,\r
- PG1,\r
- PG2,\r
- PG3,\r
- PG4,\r
- PG5,\r
- PG6,\r
- PG7,\r
- PG8,\r
- PG9,\r
- PG10,\r
- PG11,\r
- PG12,\r
- PG13,\r
- PG14,\r
- PG15,\r
- PH0,\r
- PH1,\r
- PH2,\r
- PH3,\r
- PH4,\r
- PH5,\r
- PH6,\r
- PH7,\r
- PH8,\r
- PH9,\r
- PH10,\r
- PH11,\r
- PH12,\r
- PH13,\r
- PH14,\r
- PH15,\r
- PJ0,\r
- PJ1,\r
- PJ2,\r
- PJ3,\r
- PJ4,\r
- PJ5,\r
- PJ6,\r
- PJ7,\r
- PJ8,\r
- PJ9,\r
- PJ10,\r
- PJ11,\r
- PJ12,\r
- PJ13,\r
- PJ14,\r
- PJ15,\r
- PK0,\r
- PK1\r
+ PORT_PA0,\r
+ PORT_PA1,\r
+ PORT_PA2,\r
+ PORT_PA3,\r
+ PORT_PA4,\r
+ PORT_PA5,\r
+ PORT_PA6,\r
+ PORT_PA7,\r
+ PORT_PA8,\r
+ PORT_PA9,\r
+ PORT_PA10,\r
+ PORT_PA11,\r
+ PORT_PA12,\r
+ PORT_PA13,\r
+ PORT_PA14,\r
+ PORT_PA15,\r
+ PORT_PB0,\r
+ PORT_PB1,\r
+ PORT_PB2,\r
+ PORT_PB3,\r
+ PORT_PB4,\r
+ PORT_PB5,\r
+ PORT_PB6,\r
+ PORT_PB7,\r
+ PORT_PB8,\r
+ PORT_PB9,\r
+ PORT_PB10,\r
+ PORT_PB11,\r
+ PORT_PB12,\r
+ PORT_PB13,\r
+ PORT_PB14,\r
+ PORT_PB15,\r
+ PORT_PC0,\r
+ PORT_PC1,\r
+ PORT_PC2,\r
+ PORT_PC3,\r
+ PORT_PC4,\r
+ PORT_PC5,\r
+ PORT_PC6,\r
+ PORT_PC7,\r
+ PORT_PC8,\r
+ PORT_PC9,\r
+ PORT_PC10,\r
+ PORT_PC11,\r
+ PORT_PC12,\r
+ PORT_PC13,\r
+ PORT_PC14,\r
+ PORT_PC15,\r
+ PORT_PD0,\r
+ PORT_PD1,\r
+ PORT_PD2,\r
+ PORT_PD3,\r
+ PORT_PD4,\r
+ PORT_PD5,\r
+ PORT_PD6,\r
+ PORT_PD7,\r
+ PORT_PD8,\r
+ PORT_PD9,\r
+ PORT_PD10,\r
+ PORT_PD11,\r
+ PORT_PD12,\r
+ PORT_PD13,\r
+ PORT_PD14,\r
+ PORT_PD15,\r
+ PORT_PE0,\r
+ PORT_PE1,\r
+ PORT_PE2,\r
+ PORT_PE3,\r
+ PORT_PE4,\r
+ PORT_PE5,\r
+ PORT_PE6,\r
+ PORT_PE7,\r
+ PORT_PE8,\r
+ PORT_PE9,\r
+ PORT_PE10,\r
+ PORT_PE11,\r
+ PORT_PE12,\r
+ PORT_PE13,\r
+ PORT_PE14,\r
+ PORT_PE15,\r
+ PORT_PF0,\r
+ PORT_PF1,\r
+ PORT_PF2,\r
+ PORT_PF3,\r
+ PORT_PF4,\r
+ PORT_PF5,\r
+ PORT_PF6,\r
+ PORT_PF7,\r
+ PORT_PF8,\r
+ PORT_PF9,\r
+ PORT_PF10,\r
+ PORT_PF11,\r
+ PORT_PF12,\r
+ PORT_PF13,\r
+ PORT_PF14,\r
+ PORT_PF15,\r
+ PORT_PG0,\r
+ PORT_PG1,\r
+ PORT_PG2,\r
+ PORT_PG3,\r
+ PORT_PG4,\r
+ PORT_PG5,\r
+ PORT_PG6,\r
+ PORT_PG7,\r
+ PORT_PG8,\r
+ PORT_PG9,\r
+ PORT_PG10,\r
+ PORT_PG11,\r
+ PORT_PG12,\r
+ PORT_PG13,\r
+ PORT_PG14,\r
+ PORT_PG15,\r
+ PORT_PH0,\r
+ PORT_PH1,\r
+ PORT_PH2,\r
+ PORT_PH3,\r
+ PORT_PH4,\r
+ PORT_PH5,\r
+ PORT_PH6,\r
+ PORT_PH7,\r
+ PORT_PH8,\r
+ PORT_PH9,\r
+ PORT_PH10,\r
+ PORT_PH11,\r
+ PORT_PH12,\r
+ PORT_PH13,\r
+ PORT_PH14,\r
+ PORT_PH15,\r
+ PORT_PJ0,\r
+ PORT_PJ1,\r
+ PORT_PJ2,\r
+ PORT_PJ3,\r
+ PORT_PJ4,\r
+ PORT_PJ5,\r
+ PORT_PJ6,\r
+ PORT_PJ7,\r
+ PORT_PJ8,\r
+ PORT_PJ9,\r
+ PORT_PJ10,\r
+ PORT_PJ11,\r
+ PORT_PJ12,\r
+ PORT_PJ13,\r
+ PORT_PJ14,\r
+ PORT_PJ15,\r
+ PORT_PK0,\r
+ PORT_PK1\r
} Port_PinType;\r
\r
-#define BIT0 (1<<15)\r
-#define BIT1 (1<<14)\r
-#define BIT2 (1<<13)\r
-#define BIT3 (1<<12)\r
-#define BIT4 (1<<11)\r
-#define BIT5 (1<<10)\r
-#define BIT6 (1<<9)\r
-#define BIT7 (1<<8)\r
-#define BIT8 (1<<7)\r
-#define BIT9 (1<<6)\r
-#define BIT10 (1<<5)\r
-#define BIT11 (1<<4)\r
-#define BIT12 (1<<3)\r
-#define BIT13 (1<<2)\r
-#define BIT14 (1<<1)\r
-#define BIT15 (1<<0)\r
-\r
-#define WPE_BIT BIT14\r
-#define WPS_BIT BIT15\r
-#define SRC0 BIT12\r
-#define SRC1 BIT13\r
-\r
-#define PULL_UP (WPE_BIT|WPS_BIT)\r
-#define PULL_DOWN (WPE_BIT)\r
-#define PULL_NONE 0\r
-#define SLEW_RATE_MIN 0\r
-#define SLEW_RATE_MED BIT13\r
-#define SLEW_RATE_MAX (BIT12|BIT13)\r
-#define HYS_ENABLE BIT11\r
-#define ODE_ENABLE BIT10\r
-#define IBE_ENABLE BIT7\r
-#define OBE_ENABLE BIT6\r
-#define PA_IO 0\r
-#define PA_FUNC1 (BIT5)\r
-#define PA_FUNC2 (BIT4)\r
-#define PA_FUNC3 (BIT4|BIT5)\r
-\r
-#define NORMAL_INPUT (BIT15)\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_PA_IO 0\r
+#define PORT_PA_FUNC1 (PORT_BIT5)\r
+#define PORT_PA_FUNC2 (PORT_BIT4)\r
+#define PORT_PA_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+\r
+#define PORT_NORMAL_INPUT (PORT_BIT15)\r
\r
// Should be this out of reset\r
-#define PCR_RESET (0)\r
-#define PCR_BOOTCFG (IBE_ENABLE|PULL_DOWN)\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_PCR_BOOTCFG (PORT_IBE_ENABLE|PORT_PULL_DOWN)\r
\r
-#define EVB_TEST_CONFIG (&PortConfigData)\r
+#define PORT_EVB_TEST_CONFIG (&PortConfigData)\r
\r
typedef struct\r
{\r
*/\r
\r
\r
-#if (PWM_SW_MAJOR_VERSION != 1) \r
+#if !(((PWM_SW_MAJOR_VERSION == 1) && (PWM_SW_MINOR_VERSION == 0)) )\r
#error "Pwm: Configuration file version differs from BSW version."\r
#endif\r
\r
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC5567\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:16:23 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:50:59 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC5567\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:16:23 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:50:59 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
-/* \r
-* Configuration of module Port (Port_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC5567\r
-* \r
-* Module vendor: ArcCore\r
-* Module version: 1.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 09 13:44:55 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:50:58 CET 2011\r
+ */\r
\r
\r
-// File generated on Fri Apr 09 13:44:55 CEST 2010\r
+// File generated on Fri Jan 14 10:50:58 CET 2011\r
// File generated by com.arccore.bswbuilder.modules.port.mpc5567\r
\r
#include "Port.h"\r
#include "Port_Cfg.h"\r
-#include "stdlib.h"\r
+#include <stdlib.h>\r
\r
const uint16_t PortPadConfigData[] = {\r
- PCR_RESET, /* PCR 0 */\r
- PCR_RESET, /* PCR 1 */\r
- PCR_RESET, /* PCR 2 */\r
- PCR_RESET, /* PCR 3 */\r
- PCR_RESET, /* PCR 4 */\r
- PCR_RESET, /* PCR 5 */\r
- PCR_RESET, /* PCR 6 */\r
- PCR_RESET, /* PCR 7 */\r
- PCR_RESET, /* PCR 8 */\r
- PCR_RESET, /* PCR 9 */\r
- PCR_RESET, /* PCR 10 */\r
- PCR_RESET, /* PCR 11 */\r
- PCR_RESET, /* PCR 12 */\r
- PCR_RESET, /* PCR 13 */\r
- PCR_RESET, /* PCR 14 */\r
- PCR_RESET, /* PCR 15 */\r
- PCR_RESET, /* PCR 16 */\r
- PCR_RESET, /* PCR 17 */\r
- PCR_RESET, /* PCR 18 */\r
- PCR_RESET, /* PCR 19 */\r
- PCR_RESET, /* PCR 20 */\r
- PCR_RESET, /* PCR 21 */\r
- PCR_RESET, /* PCR 22 */\r
- PCR_RESET, /* PCR 23 */\r
- PCR_RESET, /* PCR 24 */\r
- PCR_RESET, /* PCR 25 */\r
- PCR_RESET, /* PCR 26 */\r
- PCR_RESET, /* PCR 27 */\r
- PCR_RESET, /* PCR 28 */\r
- PCR_RESET, /* PCR 29 */\r
- PCR_RESET, /* PCR 30 */\r
- PCR_RESET, /* PCR 31 */\r
- PCR_RESET, /* PCR 32 */\r
- PCR_RESET, /* PCR 33 */\r
- PCR_RESET, /* PCR 34 */\r
- PCR_RESET, /* PCR 35 */\r
- PCR_RESET, /* PCR 36 */\r
- PCR_RESET, /* PCR 37 */\r
- PCR_RESET, /* PCR 38 */\r
- PCR_RESET, /* PCR 39 */\r
- PCR_RESET, /* PCR 40 */\r
- PCR_RESET, /* PCR 41 */\r
- PCR_RESET, /* PCR 42 */\r
- PCR_RESET, /* PCR 43 */\r
- PCR_RESET, /* PCR 44 */\r
- PCR_RESET, /* PCR 45 */\r
- PCR_RESET, /* PCR 46 */\r
- PCR_RESET, /* PCR 47 */\r
- PCR_RESET, /* PCR 48 */\r
- PCR_RESET, /* PCR 49 */\r
- PCR_RESET, /* PCR 50 */\r
- PCR_RESET, /* PCR 51 */\r
- PCR_RESET, /* PCR 52 */\r
- PCR_RESET, /* PCR 53 */\r
- PCR_RESET, /* PCR 54 */\r
- PCR_RESET, /* PCR 55 */\r
- PCR_RESET, /* PCR 56 */\r
- PCR_RESET, /* PCR 57 */\r
- PCR_RESET, /* PCR 58 */\r
- PCR_RESET, /* PCR 59 */\r
- PCR_RESET, /* PCR 60 */\r
- PCR_RESET, /* PCR 61 */\r
- PCR_RESET, /* PCR 62 */\r
- PCR_RESET, /* PCR 63 */\r
- PCR_RESET, /* PCR 64 */\r
- PCR_RESET, /* PCR 65 */\r
- PCR_RESET, /* PCR 66 */\r
- PCR_RESET, /* PCR 67 */\r
- PCR_RESET, /* PCR 68 */\r
- PCR_RESET, /* PCR 69 */\r
- PCR_RESET, /* PCR 70 */\r
- PCR_RESET, /* PCR 71 */\r
- PCR_RESET, /* PCR 72 */\r
- PCR_RESET, /* PCR 73 */\r
- PCR_RESET, /* PCR 74 */\r
- PCR_RESET, /* PCR 75 */\r
- PCR_RESET, /* PCR 76 */\r
- PCR_RESET, /* PCR 77 */\r
- PCR_RESET, /* PCR 78 */\r
- PCR_RESET, /* PCR 79 */\r
- PCR_RESET, /* PCR 80 */\r
- PCR_RESET, /* PCR 81 */\r
- PCR_RESET, /* PCR 82 */\r
- PCR_RESET, /* PCR 83 */\r
- PCR_RESET, /* PCR 84 */\r
- PCR_RESET, /* PCR 85 */\r
- PCR_RESET, /* PCR 86 */\r
- PCR_RESET, /* PCR 87 */\r
- PCR_RESET, /* PCR 88 */\r
- PCR_RESET, /* PCR 89 */\r
- PCR_RESET, /* PCR 90 */\r
- PCR_RESET, /* PCR 91 */\r
- PCR_RESET, /* PCR 92 */\r
- PCR_RESET, /* PCR 93 */\r
- PCR_RESET, /* PCR 94 */\r
- PCR_RESET, /* PCR 95 */\r
- PCR_RESET, /* PCR 96 */\r
- PCR_RESET, /* PCR 97 */\r
- PCR_RESET, /* PCR 98 */\r
- PCR_RESET, /* PCR 99 */\r
- PCR_RESET, /* PCR 100 */\r
- PCR_RESET, /* PCR 101 */\r
- PCR_RESET, /* PCR 102 */\r
- PCR_RESET, /* PCR 103 */\r
- PCR_RESET, /* PCR 104 */\r
- PCR_RESET, /* PCR 105 */\r
- PCR_RESET, /* PCR 106 */\r
- PCR_RESET, /* PCR 107 */\r
- PCR_RESET, /* PCR 108 */\r
- PCR_RESET, /* PCR 109 */\r
- PCR_RESET, /* PCR 110 */\r
- PCR_RESET, /* PCR 111 */\r
- PCR_RESET, /* PCR 112 */\r
- PCR_RESET, /* PCR 113 */\r
- PCR_RESET, /* PCR 114 */\r
- PCR_RESET, /* PCR 115 */\r
- PCR_RESET, /* PCR 116 */\r
- PCR_RESET, /* PCR 117 */\r
- PCR_RESET, /* PCR 118 */\r
- PCR_RESET, /* PCR 119 */\r
- PCR_RESET, /* PCR 120 */\r
- PCR_RESET, /* PCR 121 */\r
- PCR_RESET, /* PCR 122 */\r
- PCR_RESET, /* PCR 123 */\r
- PCR_RESET, /* PCR 124 */\r
- PCR_RESET, /* PCR 125 */\r
- PCR_RESET, /* PCR 126 */\r
- PCR_RESET, /* PCR 127 */\r
- PCR_RESET, /* PCR 128 */\r
- PCR_RESET, /* PCR 129 */\r
- PCR_RESET, /* PCR 130 */\r
- PCR_RESET, /* PCR 131 */\r
- PCR_RESET, /* PCR 132 */\r
- PCR_RESET, /* PCR 133 */\r
- PCR_RESET, /* PCR 134 */\r
- PCR_RESET, /* PCR 135 */\r
- PCR_RESET, /* PCR 136 */\r
- PCR_RESET, /* PCR 137 */\r
- PCR_RESET, /* PCR 138 */\r
- PCR_RESET, /* PCR 139 */\r
- PCR_RESET, /* PCR 140 */\r
- PCR_RESET, /* PCR 141 */\r
- PCR_RESET, /* PCR 142 */\r
- PCR_RESET, /* PCR 143 */\r
- PCR_RESET, /* PCR 144 */\r
- PCR_RESET, /* PCR 145 */\r
- PCR_RESET, /* PCR 146 */\r
- PCR_RESET, /* PCR 147 */\r
- PCR_RESET, /* PCR 148 */\r
- PCR_RESET, /* PCR 149 */\r
- PCR_RESET, /* PCR 150 */\r
- PCR_RESET, /* PCR 151 */\r
- PCR_RESET, /* PCR 152 */\r
- PCR_RESET, /* PCR 153 */\r
- PCR_RESET, /* PCR 154 */\r
- PCR_RESET, /* PCR 155 */\r
- PCR_RESET, /* PCR 156 */\r
- PCR_RESET, /* PCR 157 */\r
- PCR_RESET, /* PCR 158 */\r
- PCR_RESET, /* PCR 159 */\r
- PCR_RESET, /* PCR 160 */\r
- PCR_RESET, /* PCR 161 */\r
- PCR_RESET, /* PCR 162 */\r
- PCR_RESET, /* PCR 163 */\r
- PCR_RESET, /* PCR 164 */\r
- PCR_RESET, /* PCR 165 */\r
- PCR_RESET, /* PCR 166 */\r
- PCR_RESET, /* PCR 167 */\r
- PCR_RESET, /* PCR 168 */\r
- PCR_RESET, /* PCR 169 */\r
- PCR_RESET, /* PCR 170 */\r
- PCR_RESET, /* PCR 171 */\r
- PCR_RESET, /* PCR 172 */\r
- PCR_RESET, /* PCR 173 */\r
- PCR_RESET, /* PCR 174 */\r
- PCR_RESET, /* PCR 175 */\r
- PCR_RESET, /* PCR 176 */\r
- PCR_RESET, /* PCR 177 */\r
- PCR_RESET, /* PCR 178 */\r
- PCR_RESET, /* PCR 179 */\r
- PCR_RESET, /* PCR 180 */\r
- PCR_RESET, /* PCR 181 */\r
- PCR_RESET, /* PCR 182 */\r
- PCR_RESET, /* PCR 183 */\r
- PCR_RESET, /* PCR 184 */\r
- PCR_RESET, /* PCR 185 */\r
- PCR_RESET, /* PCR 186 */\r
- PCR_RESET, /* PCR 187 */\r
- PCR_RESET, /* PCR 188 */\r
- ( FUNC1 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 189 : PORT_PIN_MODE_PWM */\r
- PCR_RESET, /* PCR 190 */\r
- ( FUNC1 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 191 : PORT_PIN_MODE_PWM */\r
- PCR_RESET, /* PCR 192 */\r
- PCR_RESET, /* PCR 193 */\r
- PCR_RESET, /* PCR 194 */\r
- PCR_RESET, /* PCR 195 */\r
- PCR_RESET, /* PCR 196 */\r
- PCR_RESET, /* PCR 197 */\r
- PCR_RESET, /* PCR 198 */\r
- PCR_RESET, /* PCR 199 */\r
- PCR_RESET, /* PCR 200 */\r
- PCR_RESET, /* PCR 201 */\r
- PCR_RESET, /* PCR 202 */\r
- PCR_RESET, /* PCR 203 */\r
- PCR_RESET, /* PCR 204 */\r
- PCR_RESET, /* PCR 205 */\r
- PCR_RESET, /* PCR 206 */\r
- PCR_RESET, /* PCR 207 */\r
- PCR_RESET, /* PCR 208 */\r
- PCR_RESET, /* PCR 209 */\r
- PCR_RESET, /* PCR 210 */\r
- PCR_RESET, /* PCR 211 */\r
- PCR_RESET, /* PCR 212 */\r
- PCR_RESET, /* PCR 213 */\r
- PCR_RESET, /* PCR 214 */\r
- PCR_RESET, /* PCR 215 */\r
- PCR_RESET, /* PCR 216 */\r
- PCR_RESET, /* PCR 217 */\r
- PCR_RESET, /* PCR 218 */\r
- PCR_RESET, /* PCR 219 */\r
- PCR_RESET, /* PCR 220 */\r
- PCR_RESET, /* PCR 221 */\r
- PCR_RESET, /* PCR 222 */\r
- PCR_RESET, /* PCR 223 */\r
- PCR_RESET, /* PCR 224 */\r
- PCR_RESET, /* PCR 225 */\r
- PCR_RESET, /* PCR 226 */\r
- PCR_RESET, /* PCR 227 */\r
- PCR_RESET, /* PCR 228 */\r
- PCR_RESET, /* PCR 229 */\r
- PCR_RESET, /* PCR 230 */\r
- PCR_RESET, /* PCR 231 */\r
- PCR_RESET, /* PCR 232 */\r
- PCR_RESET, /* PCR 233 */\r
- PCR_RESET, /* PCR 234 */\r
- PCR_RESET, /* PCR 235 */\r
- PCR_RESET, /* PCR 236 */\r
- PCR_RESET, /* PCR 237 */\r
- PCR_RESET, /* PCR 238 */\r
- PCR_RESET, /* PCR 239 */\r
- PCR_RESET, /* PCR 240 */\r
- PCR_RESET, /* PCR 241 */\r
- PCR_RESET, /* PCR 242 */\r
- PCR_RESET, /* PCR 243 */\r
- PCR_RESET, /* PCR 244 */\r
- PCR_RESET, /* PCR 245 */\r
- PCR_RESET, /* PCR 246 */\r
- PCR_RESET, /* PCR 247 */\r
- PCR_RESET, /* PCR 248 */\r
- PCR_RESET, /* PCR 249 */\r
- PCR_RESET, /* PCR 250 */\r
- PCR_RESET, /* PCR 251 */\r
- PCR_RESET, /* PCR 252 */\r
- PCR_RESET, /* PCR 253 */\r
- PCR_RESET, /* PCR 254 */\r
- PCR_RESET, /* PCR 255 */\r
- PCR_RESET, /* PCR 256 */\r
- PCR_RESET, /* PCR 257 */\r
- PCR_RESET, /* PCR 258 */\r
- PCR_RESET, /* PCR 259 */\r
- PCR_RESET, /* PCR 260 */\r
- PCR_RESET, /* PCR 261 */\r
- PCR_RESET, /* PCR 262 */\r
- PCR_RESET, /* PCR 263 */\r
- PCR_RESET, /* PCR 264 */\r
- PCR_RESET, /* PCR 265 */\r
- PCR_RESET, /* PCR 266 */\r
- PCR_RESET, /* PCR 267 */\r
- PCR_RESET, /* PCR 268 */\r
- PCR_RESET, /* PCR 269 */\r
- PCR_RESET, /* PCR 270 */\r
- PCR_RESET, /* PCR 271 */\r
- PCR_RESET, /* PCR 272 */\r
- PCR_RESET, /* PCR 273 */\r
- PCR_RESET, /* PCR 274 */\r
- PCR_RESET, /* PCR 275 */\r
- PCR_RESET, /* PCR 276 */\r
- PCR_RESET, /* PCR 277 */\r
- PCR_RESET, /* PCR 278 */\r
- PCR_RESET, /* PCR 279 */\r
- PCR_RESET, /* PCR 280 */\r
- PCR_RESET, /* PCR 281 */\r
- PCR_RESET, /* PCR 282 */\r
- PCR_RESET, /* PCR 283 */\r
- PCR_RESET, /* PCR 284 */\r
- PCR_RESET, /* PCR 285 */\r
- PCR_RESET, /* PCR 286 */\r
- PCR_RESET, /* PCR 287 */\r
- PCR_RESET, /* PCR 288 */\r
- PCR_RESET, /* PCR 289 */\r
- PCR_RESET, /* PCR 290 */\r
- PCR_RESET, /* PCR 291 */\r
- PCR_RESET, /* PCR 292 */\r
- PCR_RESET, /* PCR 293 */\r
- PCR_RESET, /* PCR 294 */\r
- PCR_RESET, /* PCR 295 */\r
- PCR_RESET, /* PCR 296 */\r
- PCR_RESET, /* PCR 297 */\r
- PCR_RESET, /* PCR 298 */\r
+ PORT_PCR_RESET, /* PCR 0 */\r
+ PORT_PCR_RESET, /* PCR 1 */\r
+ PORT_PCR_RESET, /* PCR 2 */\r
+ PORT_PCR_RESET, /* PCR 3 */\r
+ PORT_PCR_RESET, /* PCR 4 */\r
+ PORT_PCR_RESET, /* PCR 5 */\r
+ PORT_PCR_RESET, /* PCR 6 */\r
+ PORT_PCR_RESET, /* PCR 7 */\r
+ PORT_PCR_RESET, /* PCR 8 */\r
+ PORT_PCR_RESET, /* PCR 9 */\r
+ PORT_PCR_RESET, /* PCR 10 */\r
+ PORT_PCR_RESET, /* PCR 11 */\r
+ PORT_PCR_RESET, /* PCR 12 */\r
+ PORT_PCR_RESET, /* PCR 13 */\r
+ PORT_PCR_RESET, /* PCR 14 */\r
+ PORT_PCR_RESET, /* PCR 15 */\r
+ PORT_PCR_RESET, /* PCR 16 */\r
+ PORT_PCR_RESET, /* PCR 17 */\r
+ PORT_PCR_RESET, /* PCR 18 */\r
+ PORT_PCR_RESET, /* PCR 19 */\r
+ PORT_PCR_RESET, /* PCR 20 */\r
+ PORT_PCR_RESET, /* PCR 21 */\r
+ PORT_PCR_RESET, /* PCR 22 */\r
+ PORT_PCR_RESET, /* PCR 23 */\r
+ PORT_PCR_RESET, /* PCR 24 */\r
+ PORT_PCR_RESET, /* PCR 25 */\r
+ PORT_PCR_RESET, /* PCR 26 */\r
+ PORT_PCR_RESET, /* PCR 27 */\r
+ PORT_PCR_RESET, /* PCR 28 */\r
+ PORT_PCR_RESET, /* PCR 29 */\r
+ PORT_PCR_RESET, /* PCR 30 */\r
+ PORT_PCR_RESET, /* PCR 31 */\r
+ PORT_PCR_RESET, /* PCR 32 */\r
+ PORT_PCR_RESET, /* PCR 33 */\r
+ PORT_PCR_RESET, /* PCR 34 */\r
+ PORT_PCR_RESET, /* PCR 35 */\r
+ PORT_PCR_RESET, /* PCR 36 */\r
+ PORT_PCR_RESET, /* PCR 37 */\r
+ PORT_PCR_RESET, /* PCR 38 */\r
+ PORT_PCR_RESET, /* PCR 39 */\r
+ PORT_PCR_RESET, /* PCR 40 */\r
+ PORT_PCR_RESET, /* PCR 41 */\r
+ PORT_PCR_RESET, /* PCR 42 */\r
+ PORT_PCR_RESET, /* PCR 43 */\r
+ PORT_PCR_RESET, /* PCR 44 */\r
+ PORT_PCR_RESET, /* PCR 45 */\r
+ PORT_PCR_RESET, /* PCR 46 */\r
+ PORT_PCR_RESET, /* PCR 47 */\r
+ PORT_PCR_RESET, /* PCR 48 */\r
+ PORT_PCR_RESET, /* PCR 49 */\r
+ PORT_PCR_RESET, /* PCR 50 */\r
+ PORT_PCR_RESET, /* PCR 51 */\r
+ PORT_PCR_RESET, /* PCR 52 */\r
+ PORT_PCR_RESET, /* PCR 53 */\r
+ PORT_PCR_RESET, /* PCR 54 */\r
+ PORT_PCR_RESET, /* PCR 55 */\r
+ PORT_PCR_RESET, /* PCR 56 */\r
+ PORT_PCR_RESET, /* PCR 57 */\r
+ PORT_PCR_RESET, /* PCR 58 */\r
+ PORT_PCR_RESET, /* PCR 59 */\r
+ PORT_PCR_RESET, /* PCR 60 */\r
+ PORT_PCR_RESET, /* PCR 61 */\r
+ PORT_PCR_RESET, /* PCR 62 */\r
+ PORT_PCR_RESET, /* PCR 63 */\r
+ PORT_PCR_RESET, /* PCR 64 */\r
+ PORT_PCR_RESET, /* PCR 65 */\r
+ PORT_PCR_RESET, /* PCR 66 */\r
+ PORT_PCR_RESET, /* PCR 67 */\r
+ PORT_PCR_RESET, /* PCR 68 */\r
+ PORT_PCR_RESET, /* PCR 69 */\r
+ PORT_PCR_RESET, /* PCR 70 */\r
+ PORT_PCR_RESET, /* PCR 71 */\r
+ PORT_PCR_RESET, /* PCR 72 */\r
+ PORT_PCR_RESET, /* PCR 73 */\r
+ PORT_PCR_RESET, /* PCR 74 */\r
+ PORT_PCR_RESET, /* PCR 75 */\r
+ PORT_PCR_RESET, /* PCR 76 */\r
+ PORT_PCR_RESET, /* PCR 77 */\r
+ PORT_PCR_RESET, /* PCR 78 */\r
+ PORT_PCR_RESET, /* PCR 79 */\r
+ PORT_PCR_RESET, /* PCR 80 */\r
+ PORT_PCR_RESET, /* PCR 81 */\r
+ PORT_PCR_RESET, /* PCR 82 */\r
+ PORT_PCR_RESET, /* PCR 83 */\r
+ PORT_PCR_RESET, /* PCR 84 */\r
+ PORT_PCR_RESET, /* PCR 85 */\r
+ PORT_PCR_RESET, /* PCR 86 */\r
+ PORT_PCR_RESET, /* PCR 87 */\r
+ PORT_PCR_RESET, /* PCR 88 */\r
+ PORT_PCR_RESET, /* PCR 89 */\r
+ PORT_PCR_RESET, /* PCR 90 */\r
+ PORT_PCR_RESET, /* PCR 91 */\r
+ PORT_PCR_RESET, /* PCR 92 */\r
+ PORT_PCR_RESET, /* PCR 93 */\r
+ PORT_PCR_RESET, /* PCR 94 */\r
+ PORT_PCR_RESET, /* PCR 95 */\r
+ PORT_PCR_RESET, /* PCR 96 */\r
+ PORT_PCR_RESET, /* PCR 97 */\r
+ PORT_PCR_RESET, /* PCR 98 */\r
+ PORT_PCR_RESET, /* PCR 99 */\r
+ PORT_PCR_RESET, /* PCR 100 */\r
+ PORT_PCR_RESET, /* PCR 101 */\r
+ PORT_PCR_RESET, /* PCR 102 */\r
+ PORT_PCR_RESET, /* PCR 103 */\r
+ PORT_PCR_RESET, /* PCR 104 */\r
+ PORT_PCR_RESET, /* PCR 105 */\r
+ PORT_PCR_RESET, /* PCR 106 */\r
+ PORT_PCR_RESET, /* PCR 107 */\r
+ PORT_PCR_RESET, /* PCR 108 */\r
+ PORT_PCR_RESET, /* PCR 109 */\r
+ PORT_PCR_RESET, /* PCR 110 */\r
+ PORT_PCR_RESET, /* PCR 111 */\r
+ PORT_PCR_RESET, /* PCR 112 */\r
+ PORT_PCR_RESET, /* PCR 113 */\r
+ PORT_PCR_RESET, /* PCR 114 */\r
+ PORT_PCR_RESET, /* PCR 115 */\r
+ PORT_PCR_RESET, /* PCR 116 */\r
+ PORT_PCR_RESET, /* PCR 117 */\r
+ PORT_PCR_RESET, /* PCR 118 */\r
+ PORT_PCR_RESET, /* PCR 119 */\r
+ PORT_PCR_RESET, /* PCR 120 */\r
+ PORT_PCR_RESET, /* PCR 121 */\r
+ PORT_PCR_RESET, /* PCR 122 */\r
+ PORT_PCR_RESET, /* PCR 123 */\r
+ PORT_PCR_RESET, /* PCR 124 */\r
+ PORT_PCR_RESET, /* PCR 125 */\r
+ PORT_PCR_RESET, /* PCR 126 */\r
+ PORT_PCR_RESET, /* PCR 127 */\r
+ PORT_PCR_RESET, /* PCR 128 */\r
+ PORT_PCR_RESET, /* PCR 129 */\r
+ PORT_PCR_RESET, /* PCR 130 */\r
+ PORT_PCR_RESET, /* PCR 131 */\r
+ PORT_PCR_RESET, /* PCR 132 */\r
+ PORT_PCR_RESET, /* PCR 133 */\r
+ PORT_PCR_RESET, /* PCR 134 */\r
+ PORT_PCR_RESET, /* PCR 135 */\r
+ PORT_PCR_RESET, /* PCR 136 */\r
+ PORT_PCR_RESET, /* PCR 137 */\r
+ PORT_PCR_RESET, /* PCR 138 */\r
+ PORT_PCR_RESET, /* PCR 139 */\r
+ PORT_PCR_RESET, /* PCR 140 */\r
+ PORT_PCR_RESET, /* PCR 141 */\r
+ PORT_PCR_RESET, /* PCR 142 */\r
+ PORT_PCR_RESET, /* PCR 143 */\r
+ PORT_PCR_RESET, /* PCR 144 */\r
+ PORT_PCR_RESET, /* PCR 145 */\r
+ PORT_PCR_RESET, /* PCR 146 */\r
+ PORT_PCR_RESET, /* PCR 147 */\r
+ PORT_PCR_RESET, /* PCR 148 */\r
+ PORT_PCR_RESET, /* PCR 149 */\r
+ PORT_PCR_RESET, /* PCR 150 */\r
+ PORT_PCR_RESET, /* PCR 151 */\r
+ PORT_PCR_RESET, /* PCR 152 */\r
+ PORT_PCR_RESET, /* PCR 153 */\r
+ PORT_PCR_RESET, /* PCR 154 */\r
+ PORT_PCR_RESET, /* PCR 155 */\r
+ PORT_PCR_RESET, /* PCR 156 */\r
+ PORT_PCR_RESET, /* PCR 157 */\r
+ PORT_PCR_RESET, /* PCR 158 */\r
+ PORT_PCR_RESET, /* PCR 159 */\r
+ PORT_PCR_RESET, /* PCR 160 */\r
+ PORT_PCR_RESET, /* PCR 161 */\r
+ PORT_PCR_RESET, /* PCR 162 */\r
+ PORT_PCR_RESET, /* PCR 163 */\r
+ PORT_PCR_RESET, /* PCR 164 */\r
+ PORT_PCR_RESET, /* PCR 165 */\r
+ PORT_PCR_RESET, /* PCR 166 */\r
+ PORT_PCR_RESET, /* PCR 167 */\r
+ PORT_PCR_RESET, /* PCR 168 */\r
+ PORT_PCR_RESET, /* PCR 169 */\r
+ PORT_PCR_RESET, /* PCR 170 */\r
+ PORT_PCR_RESET, /* PCR 171 */\r
+ PORT_PCR_RESET, /* PCR 172 */\r
+ PORT_PCR_RESET, /* PCR 173 */\r
+ PORT_PCR_RESET, /* PCR 174 */\r
+ PORT_PCR_RESET, /* PCR 175 */\r
+ PORT_PCR_RESET, /* PCR 176 */\r
+ PORT_PCR_RESET, /* PCR 177 */\r
+ PORT_PCR_RESET, /* PCR 178 */\r
+ PORT_PCR_RESET, /* PCR 179 */\r
+ PORT_PCR_RESET, /* PCR 180 */\r
+ PORT_PCR_RESET, /* PCR 181 */\r
+ PORT_PCR_RESET, /* PCR 182 */\r
+ PORT_PCR_RESET, /* PCR 183 */\r
+ PORT_PCR_RESET, /* PCR 184 */\r
+ PORT_PCR_RESET, /* PCR 185 */\r
+ PORT_PCR_RESET, /* PCR 186 */\r
+ PORT_PCR_RESET, /* PCR 187 */\r
+ PORT_PCR_RESET, /* PCR 188 */\r
+ ( PORT_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 189 : PORT_PIN_MODE_PWM */\r
+ PORT_PCR_RESET, /* PCR 190 */\r
+ ( PORT_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 191 : PORT_PIN_MODE_PWM */\r
+ PORT_PCR_RESET, /* PCR 192 */\r
+ PORT_PCR_RESET, /* PCR 193 */\r
+ PORT_PCR_RESET, /* PCR 194 */\r
+ PORT_PCR_RESET, /* PCR 195 */\r
+ PORT_PCR_RESET, /* PCR 196 */\r
+ PORT_PCR_RESET, /* PCR 197 */\r
+ PORT_PCR_RESET, /* PCR 198 */\r
+ PORT_PCR_RESET, /* PCR 199 */\r
+ PORT_PCR_RESET, /* PCR 200 */\r
+ PORT_PCR_RESET, /* PCR 201 */\r
+ PORT_PCR_RESET, /* PCR 202 */\r
+ PORT_PCR_RESET, /* PCR 203 */\r
+ PORT_PCR_RESET, /* PCR 204 */\r
+ PORT_PCR_RESET, /* PCR 205 */\r
+ PORT_PCR_RESET, /* PCR 206 */\r
+ PORT_PCR_RESET, /* PCR 207 */\r
+ PORT_PCR_RESET, /* PCR 208 */\r
+ PORT_PCR_RESET, /* PCR 209 */\r
+ PORT_PCR_RESET, /* PCR 210 */\r
+ PORT_PCR_RESET, /* PCR 211 */\r
+ PORT_PCR_RESET, /* PCR 212 */\r
+ PORT_PCR_RESET, /* PCR 213 */\r
+ PORT_PCR_RESET, /* PCR 214 */\r
+ PORT_PCR_RESET, /* PCR 215 */\r
+ PORT_PCR_RESET, /* PCR 216 */\r
+ PORT_PCR_RESET, /* PCR 217 */\r
+ PORT_PCR_RESET, /* PCR 218 */\r
+ PORT_PCR_RESET, /* PCR 219 */\r
+ PORT_PCR_RESET, /* PCR 220 */\r
+ PORT_PCR_RESET, /* PCR 221 */\r
+ PORT_PCR_RESET, /* PCR 222 */\r
+ PORT_PCR_RESET, /* PCR 223 */\r
+ PORT_PCR_RESET, /* PCR 224 */\r
+ PORT_PCR_RESET, /* PCR 225 */\r
+ PORT_PCR_RESET, /* PCR 226 */\r
+ PORT_PCR_RESET, /* PCR 227 */\r
+ PORT_PCR_RESET, /* PCR 228 */\r
+ PORT_PCR_RESET, /* PCR 229 */\r
+ PORT_PCR_RESET, /* PCR 230 */\r
+ PORT_PCR_RESET, /* PCR 231 */\r
+ PORT_PCR_RESET, /* PCR 232 */\r
+ PORT_PCR_RESET, /* PCR 233 */\r
+ PORT_PCR_RESET, /* PCR 234 */\r
+ PORT_PCR_RESET, /* PCR 235 */\r
+ PORT_PCR_RESET, /* PCR 236 */\r
+ PORT_PCR_RESET, /* PCR 237 */\r
+ PORT_PCR_RESET, /* PCR 238 */\r
+ PORT_PCR_RESET, /* PCR 239 */\r
+ PORT_PCR_RESET, /* PCR 240 */\r
+ PORT_PCR_RESET, /* PCR 241 */\r
+ PORT_PCR_RESET, /* PCR 242 */\r
+ PORT_PCR_RESET, /* PCR 243 */\r
+ PORT_PCR_RESET, /* PCR 244 */\r
+ PORT_PCR_RESET, /* PCR 245 */\r
+ PORT_PCR_RESET, /* PCR 246 */\r
+ PORT_PCR_RESET, /* PCR 247 */\r
+ PORT_PCR_RESET, /* PCR 248 */\r
+ PORT_PCR_RESET, /* PCR 249 */\r
+ PORT_PCR_RESET, /* PCR 250 */\r
+ PORT_PCR_RESET, /* PCR 251 */\r
+ PORT_PCR_RESET, /* PCR 252 */\r
+ PORT_PCR_RESET, /* PCR 253 */\r
+ PORT_PCR_RESET, /* PCR 254 */\r
+ PORT_PCR_RESET, /* PCR 255 */\r
+ PORT_PCR_RESET, /* PCR 256 */\r
+ PORT_PCR_RESET, /* PCR 257 */\r
+ PORT_PCR_RESET, /* PCR 258 */\r
+ PORT_PCR_RESET, /* PCR 259 */\r
+ PORT_PCR_RESET, /* PCR 260 */\r
+ PORT_PCR_RESET, /* PCR 261 */\r
+ PORT_PCR_RESET, /* PCR 262 */\r
+ PORT_PCR_RESET, /* PCR 263 */\r
+ PORT_PCR_RESET, /* PCR 264 */\r
+ PORT_PCR_RESET, /* PCR 265 */\r
+ PORT_PCR_RESET, /* PCR 266 */\r
+ PORT_PCR_RESET, /* PCR 267 */\r
+ PORT_PCR_RESET, /* PCR 268 */\r
+ PORT_PCR_RESET, /* PCR 269 */\r
+ PORT_PCR_RESET, /* PCR 270 */\r
+ PORT_PCR_RESET, /* PCR 271 */\r
+ PORT_PCR_RESET, /* PCR 272 */\r
+ PORT_PCR_RESET, /* PCR 273 */\r
+ PORT_PCR_RESET, /* PCR 274 */\r
+ PORT_PCR_RESET, /* PCR 275 */\r
+ PORT_PCR_RESET, /* PCR 276 */\r
+ PORT_PCR_RESET, /* PCR 277 */\r
+ PORT_PCR_RESET, /* PCR 278 */\r
+ PORT_PCR_RESET, /* PCR 279 */\r
+ PORT_PCR_RESET, /* PCR 280 */\r
+ PORT_PCR_RESET, /* PCR 281 */\r
+ PORT_PCR_RESET, /* PCR 282 */\r
+ PORT_PCR_RESET, /* PCR 283 */\r
+ PORT_PCR_RESET, /* PCR 284 */\r
+ PORT_PCR_RESET, /* PCR 285 */\r
+ PORT_PCR_RESET, /* PCR 286 */\r
+ PORT_PCR_RESET, /* PCR 287 */\r
+ PORT_PCR_RESET, /* PCR 288 */\r
+ PORT_PCR_RESET, /* PCR 289 */\r
+ PORT_PCR_RESET, /* PCR 290 */\r
+ PORT_PCR_RESET, /* PCR 291 */\r
+ PORT_PCR_RESET, /* PCR 292 */\r
+ PORT_PCR_RESET, /* PCR 293 */\r
+ PORT_PCR_RESET, /* PCR 294 */\r
+ PORT_PCR_RESET, /* PCR 295 */\r
+ PORT_PCR_RESET, /* PCR 296 */\r
+ PORT_PCR_RESET, /* PCR 297 */\r
+ PORT_PCR_RESET, /* PCR 298 */\r
};\r
\r
const uint8_t PortOutConfigData[] = {\r
- GPDO_RESET, /* GPDO 0 */\r
- GPDO_RESET, /* GPDO 1 */\r
- GPDO_RESET, /* GPDO 2 */\r
- GPDO_RESET, /* GPDO 3 */\r
- GPDO_RESET, /* GPDO 4 */\r
- GPDO_RESET, /* GPDO 5 */\r
- GPDO_RESET, /* GPDO 6 */\r
- GPDO_RESET, /* GPDO 7 */\r
- GPDO_RESET, /* GPDO 8 */\r
- GPDO_RESET, /* GPDO 9 */\r
- GPDO_RESET, /* GPDO 10 */\r
- GPDO_RESET, /* GPDO 11 */\r
- GPDO_RESET, /* GPDO 12 */\r
- GPDO_RESET, /* GPDO 13 */\r
- GPDO_RESET, /* GPDO 14 */\r
- GPDO_RESET, /* GPDO 15 */\r
- GPDO_RESET, /* GPDO 16 */\r
- GPDO_RESET, /* GPDO 17 */\r
- GPDO_RESET, /* GPDO 18 */\r
- GPDO_RESET, /* GPDO 19 */\r
- GPDO_RESET, /* GPDO 20 */\r
- GPDO_RESET, /* GPDO 21 */\r
- GPDO_RESET, /* GPDO 22 */\r
- GPDO_RESET, /* GPDO 23 */\r
- GPDO_RESET, /* GPDO 24 */\r
- GPDO_RESET, /* GPDO 25 */\r
- GPDO_RESET, /* GPDO 26 */\r
- GPDO_RESET, /* GPDO 27 */\r
- GPDO_RESET, /* GPDO 28 */\r
- GPDO_RESET, /* GPDO 29 */\r
- GPDO_RESET, /* GPDO 30 */\r
- GPDO_RESET, /* GPDO 31 */\r
- GPDO_RESET, /* GPDO 32 */\r
- GPDO_RESET, /* GPDO 33 */\r
- GPDO_RESET, /* GPDO 34 */\r
- GPDO_RESET, /* GPDO 35 */\r
- GPDO_RESET, /* GPDO 36 */\r
- GPDO_RESET, /* GPDO 37 */\r
- GPDO_RESET, /* GPDO 38 */\r
- GPDO_RESET, /* GPDO 39 */\r
- GPDO_RESET, /* GPDO 40 */\r
- GPDO_RESET, /* GPDO 41 */\r
- GPDO_RESET, /* GPDO 42 */\r
- GPDO_RESET, /* GPDO 43 */\r
- GPDO_RESET, /* GPDO 44 */\r
- GPDO_RESET, /* GPDO 45 */\r
- GPDO_RESET, /* GPDO 46 */\r
- GPDO_RESET, /* GPDO 47 */\r
- GPDO_RESET, /* GPDO 48 */\r
- GPDO_RESET, /* GPDO 49 */\r
- GPDO_RESET, /* GPDO 50 */\r
- GPDO_RESET, /* GPDO 51 */\r
- GPDO_RESET, /* GPDO 52 */\r
- GPDO_RESET, /* GPDO 53 */\r
- GPDO_RESET, /* GPDO 54 */\r
- GPDO_RESET, /* GPDO 55 */\r
- GPDO_RESET, /* GPDO 56 */\r
- GPDO_RESET, /* GPDO 57 */\r
- GPDO_RESET, /* GPDO 58 */\r
- GPDO_RESET, /* GPDO 59 */\r
- GPDO_RESET, /* GPDO 60 */\r
- GPDO_RESET, /* GPDO 61 */\r
- GPDO_RESET, /* GPDO 62 */\r
- GPDO_RESET, /* GPDO 63 */\r
- GPDO_RESET, /* GPDO 64 */\r
- GPDO_RESET, /* GPDO 65 */\r
- GPDO_RESET, /* GPDO 66 */\r
- GPDO_RESET, /* GPDO 67 */\r
- GPDO_RESET, /* GPDO 68 */\r
- GPDO_RESET, /* GPDO 69 */\r
- GPDO_RESET, /* GPDO 70 */\r
- GPDO_RESET, /* GPDO 71 */\r
- GPDO_RESET, /* GPDO 72 */\r
- GPDO_RESET, /* GPDO 73 */\r
- GPDO_RESET, /* GPDO 74 */\r
- GPDO_RESET, /* GPDO 75 */\r
- GPDO_RESET, /* GPDO 76 */\r
- GPDO_RESET, /* GPDO 77 */\r
- GPDO_RESET, /* GPDO 78 */\r
- GPDO_RESET, /* GPDO 79 */\r
- GPDO_RESET, /* GPDO 80 */\r
- GPDO_RESET, /* GPDO 81 */\r
- GPDO_RESET, /* GPDO 82 */\r
- GPDO_RESET, /* GPDO 83 */\r
- GPDO_RESET, /* GPDO 84 */\r
- GPDO_RESET, /* GPDO 85 */\r
- GPDO_RESET, /* GPDO 86 */\r
- GPDO_RESET, /* GPDO 87 */\r
- GPDO_RESET, /* GPDO 88 */\r
- GPDO_RESET, /* GPDO 89 */\r
- GPDO_RESET, /* GPDO 90 */\r
- GPDO_RESET, /* GPDO 91 */\r
- GPDO_RESET, /* GPDO 92 */\r
- GPDO_RESET, /* GPDO 93 */\r
- GPDO_RESET, /* GPDO 94 */\r
- GPDO_RESET, /* GPDO 95 */\r
- GPDO_RESET, /* GPDO 96 */\r
- GPDO_RESET, /* GPDO 97 */\r
- GPDO_RESET, /* GPDO 98 */\r
- GPDO_RESET, /* GPDO 99 */\r
- GPDO_RESET, /* GPDO 100 */\r
- GPDO_RESET, /* GPDO 101 */\r
- GPDO_RESET, /* GPDO 102 */\r
- GPDO_RESET, /* GPDO 103 */\r
- GPDO_RESET, /* GPDO 104 */\r
- GPDO_RESET, /* GPDO 105 */\r
- GPDO_RESET, /* GPDO 106 */\r
- GPDO_RESET, /* GPDO 107 */\r
- GPDO_RESET, /* GPDO 108 */\r
- GPDO_RESET, /* GPDO 109 */\r
- GPDO_RESET, /* GPDO 110 */\r
- GPDO_RESET, /* GPDO 111 */\r
- GPDO_RESET, /* GPDO 112 */\r
- GPDO_RESET, /* GPDO 113 */\r
- GPDO_RESET, /* GPDO 114 */\r
- GPDO_RESET, /* GPDO 115 */\r
- GPDO_RESET, /* GPDO 116 */\r
- GPDO_RESET, /* GPDO 117 */\r
- GPDO_RESET, /* GPDO 118 */\r
- GPDO_RESET, /* GPDO 119 */\r
- GPDO_RESET, /* GPDO 120 */\r
- GPDO_RESET, /* GPDO 121 */\r
- GPDO_RESET, /* GPDO 122 */\r
- GPDO_RESET, /* GPDO 123 */\r
- GPDO_RESET, /* GPDO 124 */\r
- GPDO_RESET, /* GPDO 125 */\r
- GPDO_RESET, /* GPDO 126 */\r
- GPDO_RESET, /* GPDO 127 */\r
- GPDO_RESET, /* GPDO 128 */\r
- GPDO_RESET, /* GPDO 129 */\r
- GPDO_RESET, /* GPDO 130 */\r
- GPDO_RESET, /* GPDO 131 */\r
- GPDO_RESET, /* GPDO 132 */\r
- GPDO_RESET, /* GPDO 133 */\r
- GPDO_RESET, /* GPDO 134 */\r
- GPDO_RESET, /* GPDO 135 */\r
- GPDO_RESET, /* GPDO 136 */\r
- GPDO_RESET, /* GPDO 137 */\r
- GPDO_RESET, /* GPDO 138 */\r
- GPDO_RESET, /* GPDO 139 */\r
- GPDO_RESET, /* GPDO 140 */\r
- GPDO_RESET, /* GPDO 141 */\r
- GPDO_RESET, /* GPDO 142 */\r
- GPDO_RESET, /* GPDO 143 */\r
- GPDO_RESET, /* GPDO 144 */\r
- GPDO_RESET, /* GPDO 145 */\r
- GPDO_RESET, /* GPDO 146 */\r
- GPDO_RESET, /* GPDO 147 */\r
- GPDO_RESET, /* GPDO 148 */\r
- GPDO_RESET, /* GPDO 149 */\r
- GPDO_RESET, /* GPDO 150 */\r
- GPDO_RESET, /* GPDO 151 */\r
- GPDO_RESET, /* GPDO 152 */\r
- GPDO_RESET, /* GPDO 153 */\r
- GPDO_RESET, /* GPDO 154 */\r
- GPDO_RESET, /* GPDO 155 */\r
- GPDO_RESET, /* GPDO 156 */\r
- GPDO_RESET, /* GPDO 157 */\r
- GPDO_RESET, /* GPDO 158 */\r
- GPDO_RESET, /* GPDO 159 */\r
- GPDO_RESET, /* GPDO 160 */\r
- GPDO_RESET, /* GPDO 161 */\r
- GPDO_RESET, /* GPDO 162 */\r
- GPDO_RESET, /* GPDO 163 */\r
- GPDO_RESET, /* GPDO 164 */\r
- GPDO_RESET, /* GPDO 165 */\r
- GPDO_RESET, /* GPDO 166 */\r
- GPDO_RESET, /* GPDO 167 */\r
- GPDO_RESET, /* GPDO 168 */\r
- GPDO_RESET, /* GPDO 169 */\r
- GPDO_RESET, /* GPDO 170 */\r
- GPDO_RESET, /* GPDO 171 */\r
- GPDO_RESET, /* GPDO 172 */\r
- GPDO_RESET, /* GPDO 173 */\r
- GPDO_RESET, /* GPDO 174 */\r
- GPDO_RESET, /* GPDO 175 */\r
- GPDO_RESET, /* GPDO 176 */\r
- GPDO_RESET, /* GPDO 177 */\r
- GPDO_RESET, /* GPDO 178 */\r
- GPDO_RESET, /* GPDO 179 */\r
- GPDO_RESET, /* GPDO 180 */\r
- GPDO_RESET, /* GPDO 181 */\r
- GPDO_RESET, /* GPDO 182 */\r
- GPDO_RESET, /* GPDO 183 */\r
- GPDO_RESET, /* GPDO 184 */\r
- GPDO_RESET, /* GPDO 185 */\r
- GPDO_RESET, /* GPDO 186 */\r
- GPDO_RESET, /* GPDO 187 */\r
- GPDO_RESET, /* GPDO 188 */\r
- GPDO_RESET, /* GPDO 189 */\r
- GPDO_RESET, /* GPDO 190 */\r
- GPDO_RESET, /* GPDO 191 */\r
- GPDO_RESET, /* GPDO 192 */\r
- GPDO_RESET, /* GPDO 193 */\r
- GPDO_RESET, /* GPDO 194 */\r
- GPDO_RESET, /* GPDO 195 */\r
- GPDO_RESET, /* GPDO 196 */\r
- GPDO_RESET, /* GPDO 197 */\r
- GPDO_RESET, /* GPDO 198 */\r
- GPDO_RESET, /* GPDO 199 */\r
- GPDO_RESET, /* GPDO 200 */\r
- GPDO_RESET, /* GPDO 201 */\r
- GPDO_RESET, /* GPDO 202 */\r
- GPDO_RESET, /* GPDO 203 */\r
- GPDO_RESET, /* GPDO 204 */\r
- GPDO_RESET, /* GPDO 205 */\r
- GPDO_RESET, /* GPDO 206 */\r
- GPDO_RESET, /* GPDO 207 */\r
- GPDO_RESET, /* GPDO 208 */\r
- GPDO_RESET, /* GPDO 209 */\r
- GPDO_RESET, /* GPDO 210 */\r
- GPDO_RESET, /* GPDO 211 */\r
- GPDO_RESET, /* GPDO 212 */\r
- GPDO_RESET, /* GPDO 213 */\r
+ PORT_GPDO_RESET, /* GPDO 0 */\r
+ PORT_GPDO_RESET, /* GPDO 1 */\r
+ PORT_GPDO_RESET, /* GPDO 2 */\r
+ PORT_GPDO_RESET, /* GPDO 3 */\r
+ PORT_GPDO_RESET, /* GPDO 4 */\r
+ PORT_GPDO_RESET, /* GPDO 5 */\r
+ PORT_GPDO_RESET, /* GPDO 6 */\r
+ PORT_GPDO_RESET, /* GPDO 7 */\r
+ PORT_GPDO_RESET, /* GPDO 8 */\r
+ PORT_GPDO_RESET, /* GPDO 9 */\r
+ PORT_GPDO_RESET, /* GPDO 10 */\r
+ PORT_GPDO_RESET, /* GPDO 11 */\r
+ PORT_GPDO_RESET, /* GPDO 12 */\r
+ PORT_GPDO_RESET, /* GPDO 13 */\r
+ PORT_GPDO_RESET, /* GPDO 14 */\r
+ PORT_GPDO_RESET, /* GPDO 15 */\r
+ PORT_GPDO_RESET, /* GPDO 16 */\r
+ PORT_GPDO_RESET, /* GPDO 17 */\r
+ PORT_GPDO_RESET, /* GPDO 18 */\r
+ PORT_GPDO_RESET, /* GPDO 19 */\r
+ PORT_GPDO_RESET, /* GPDO 20 */\r
+ PORT_GPDO_RESET, /* GPDO 21 */\r
+ PORT_GPDO_RESET, /* GPDO 22 */\r
+ PORT_GPDO_RESET, /* GPDO 23 */\r
+ PORT_GPDO_RESET, /* GPDO 24 */\r
+ PORT_GPDO_RESET, /* GPDO 25 */\r
+ PORT_GPDO_RESET, /* GPDO 26 */\r
+ PORT_GPDO_RESET, /* GPDO 27 */\r
+ PORT_GPDO_RESET, /* GPDO 28 */\r
+ PORT_GPDO_RESET, /* GPDO 29 */\r
+ PORT_GPDO_RESET, /* GPDO 30 */\r
+ PORT_GPDO_RESET, /* GPDO 31 */\r
+ PORT_GPDO_RESET, /* GPDO 32 */\r
+ PORT_GPDO_RESET, /* GPDO 33 */\r
+ PORT_GPDO_RESET, /* GPDO 34 */\r
+ PORT_GPDO_RESET, /* GPDO 35 */\r
+ PORT_GPDO_RESET, /* GPDO 36 */\r
+ PORT_GPDO_RESET, /* GPDO 37 */\r
+ PORT_GPDO_RESET, /* GPDO 38 */\r
+ PORT_GPDO_RESET, /* GPDO 39 */\r
+ PORT_GPDO_RESET, /* GPDO 40 */\r
+ PORT_GPDO_RESET, /* GPDO 41 */\r
+ PORT_GPDO_RESET, /* GPDO 42 */\r
+ PORT_GPDO_RESET, /* GPDO 43 */\r
+ PORT_GPDO_RESET, /* GPDO 44 */\r
+ PORT_GPDO_RESET, /* GPDO 45 */\r
+ PORT_GPDO_RESET, /* GPDO 46 */\r
+ PORT_GPDO_RESET, /* GPDO 47 */\r
+ PORT_GPDO_RESET, /* GPDO 48 */\r
+ PORT_GPDO_RESET, /* GPDO 49 */\r
+ PORT_GPDO_RESET, /* GPDO 50 */\r
+ PORT_GPDO_RESET, /* GPDO 51 */\r
+ PORT_GPDO_RESET, /* GPDO 52 */\r
+ PORT_GPDO_RESET, /* GPDO 53 */\r
+ PORT_GPDO_RESET, /* GPDO 54 */\r
+ PORT_GPDO_RESET, /* GPDO 55 */\r
+ PORT_GPDO_RESET, /* GPDO 56 */\r
+ PORT_GPDO_RESET, /* GPDO 57 */\r
+ PORT_GPDO_RESET, /* GPDO 58 */\r
+ PORT_GPDO_RESET, /* GPDO 59 */\r
+ PORT_GPDO_RESET, /* GPDO 60 */\r
+ PORT_GPDO_RESET, /* GPDO 61 */\r
+ PORT_GPDO_RESET, /* GPDO 62 */\r
+ PORT_GPDO_RESET, /* GPDO 63 */\r
+ PORT_GPDO_RESET, /* GPDO 64 */\r
+ PORT_GPDO_RESET, /* GPDO 65 */\r
+ PORT_GPDO_RESET, /* GPDO 66 */\r
+ PORT_GPDO_RESET, /* GPDO 67 */\r
+ PORT_GPDO_RESET, /* GPDO 68 */\r
+ PORT_GPDO_RESET, /* GPDO 69 */\r
+ PORT_GPDO_RESET, /* GPDO 70 */\r
+ PORT_GPDO_RESET, /* GPDO 71 */\r
+ PORT_GPDO_RESET, /* GPDO 72 */\r
+ PORT_GPDO_RESET, /* GPDO 73 */\r
+ PORT_GPDO_RESET, /* GPDO 74 */\r
+ PORT_GPDO_RESET, /* GPDO 75 */\r
+ PORT_GPDO_RESET, /* GPDO 76 */\r
+ PORT_GPDO_RESET, /* GPDO 77 */\r
+ PORT_GPDO_RESET, /* GPDO 78 */\r
+ PORT_GPDO_RESET, /* GPDO 79 */\r
+ PORT_GPDO_RESET, /* GPDO 80 */\r
+ PORT_GPDO_RESET, /* GPDO 81 */\r
+ PORT_GPDO_RESET, /* GPDO 82 */\r
+ PORT_GPDO_RESET, /* GPDO 83 */\r
+ PORT_GPDO_RESET, /* GPDO 84 */\r
+ PORT_GPDO_RESET, /* GPDO 85 */\r
+ PORT_GPDO_RESET, /* GPDO 86 */\r
+ PORT_GPDO_RESET, /* GPDO 87 */\r
+ PORT_GPDO_RESET, /* GPDO 88 */\r
+ PORT_GPDO_RESET, /* GPDO 89 */\r
+ PORT_GPDO_RESET, /* GPDO 90 */\r
+ PORT_GPDO_RESET, /* GPDO 91 */\r
+ PORT_GPDO_RESET, /* GPDO 92 */\r
+ PORT_GPDO_RESET, /* GPDO 93 */\r
+ PORT_GPDO_RESET, /* GPDO 94 */\r
+ PORT_GPDO_RESET, /* GPDO 95 */\r
+ PORT_GPDO_RESET, /* GPDO 96 */\r
+ PORT_GPDO_RESET, /* GPDO 97 */\r
+ PORT_GPDO_RESET, /* GPDO 98 */\r
+ PORT_GPDO_RESET, /* GPDO 99 */\r
+ PORT_GPDO_RESET, /* GPDO 100 */\r
+ PORT_GPDO_RESET, /* GPDO 101 */\r
+ PORT_GPDO_RESET, /* GPDO 102 */\r
+ PORT_GPDO_RESET, /* GPDO 103 */\r
+ PORT_GPDO_RESET, /* GPDO 104 */\r
+ PORT_GPDO_RESET, /* GPDO 105 */\r
+ PORT_GPDO_RESET, /* GPDO 106 */\r
+ PORT_GPDO_RESET, /* GPDO 107 */\r
+ PORT_GPDO_RESET, /* GPDO 108 */\r
+ PORT_GPDO_RESET, /* GPDO 109 */\r
+ PORT_GPDO_RESET, /* GPDO 110 */\r
+ PORT_GPDO_RESET, /* GPDO 111 */\r
+ PORT_GPDO_RESET, /* GPDO 112 */\r
+ PORT_GPDO_RESET, /* GPDO 113 */\r
+ PORT_GPDO_RESET, /* GPDO 114 */\r
+ PORT_GPDO_RESET, /* GPDO 115 */\r
+ PORT_GPDO_RESET, /* GPDO 116 */\r
+ PORT_GPDO_RESET, /* GPDO 117 */\r
+ PORT_GPDO_RESET, /* GPDO 118 */\r
+ PORT_GPDO_RESET, /* GPDO 119 */\r
+ PORT_GPDO_RESET, /* GPDO 120 */\r
+ PORT_GPDO_RESET, /* GPDO 121 */\r
+ PORT_GPDO_RESET, /* GPDO 122 */\r
+ PORT_GPDO_RESET, /* GPDO 123 */\r
+ PORT_GPDO_RESET, /* GPDO 124 */\r
+ PORT_GPDO_RESET, /* GPDO 125 */\r
+ PORT_GPDO_RESET, /* GPDO 126 */\r
+ PORT_GPDO_RESET, /* GPDO 127 */\r
+ PORT_GPDO_RESET, /* GPDO 128 */\r
+ PORT_GPDO_RESET, /* GPDO 129 */\r
+ PORT_GPDO_RESET, /* GPDO 130 */\r
+ PORT_GPDO_RESET, /* GPDO 131 */\r
+ PORT_GPDO_RESET, /* GPDO 132 */\r
+ PORT_GPDO_RESET, /* GPDO 133 */\r
+ PORT_GPDO_RESET, /* GPDO 134 */\r
+ PORT_GPDO_RESET, /* GPDO 135 */\r
+ PORT_GPDO_RESET, /* GPDO 136 */\r
+ PORT_GPDO_RESET, /* GPDO 137 */\r
+ PORT_GPDO_RESET, /* GPDO 138 */\r
+ PORT_GPDO_RESET, /* GPDO 139 */\r
+ PORT_GPDO_RESET, /* GPDO 140 */\r
+ PORT_GPDO_RESET, /* GPDO 141 */\r
+ PORT_GPDO_RESET, /* GPDO 142 */\r
+ PORT_GPDO_RESET, /* GPDO 143 */\r
+ PORT_GPDO_RESET, /* GPDO 144 */\r
+ PORT_GPDO_RESET, /* GPDO 145 */\r
+ PORT_GPDO_RESET, /* GPDO 146 */\r
+ PORT_GPDO_RESET, /* GPDO 147 */\r
+ PORT_GPDO_RESET, /* GPDO 148 */\r
+ PORT_GPDO_RESET, /* GPDO 149 */\r
+ PORT_GPDO_RESET, /* GPDO 150 */\r
+ PORT_GPDO_RESET, /* GPDO 151 */\r
+ PORT_GPDO_RESET, /* GPDO 152 */\r
+ PORT_GPDO_RESET, /* GPDO 153 */\r
+ PORT_GPDO_RESET, /* GPDO 154 */\r
+ PORT_GPDO_RESET, /* GPDO 155 */\r
+ PORT_GPDO_RESET, /* GPDO 156 */\r
+ PORT_GPDO_RESET, /* GPDO 157 */\r
+ PORT_GPDO_RESET, /* GPDO 158 */\r
+ PORT_GPDO_RESET, /* GPDO 159 */\r
+ PORT_GPDO_RESET, /* GPDO 160 */\r
+ PORT_GPDO_RESET, /* GPDO 161 */\r
+ PORT_GPDO_RESET, /* GPDO 162 */\r
+ PORT_GPDO_RESET, /* GPDO 163 */\r
+ PORT_GPDO_RESET, /* GPDO 164 */\r
+ PORT_GPDO_RESET, /* GPDO 165 */\r
+ PORT_GPDO_RESET, /* GPDO 166 */\r
+ PORT_GPDO_RESET, /* GPDO 167 */\r
+ PORT_GPDO_RESET, /* GPDO 168 */\r
+ PORT_GPDO_RESET, /* GPDO 169 */\r
+ PORT_GPDO_RESET, /* GPDO 170 */\r
+ PORT_GPDO_RESET, /* GPDO 171 */\r
+ PORT_GPDO_RESET, /* GPDO 172 */\r
+ PORT_GPDO_RESET, /* GPDO 173 */\r
+ PORT_GPDO_RESET, /* GPDO 174 */\r
+ PORT_GPDO_RESET, /* GPDO 175 */\r
+ PORT_GPDO_RESET, /* GPDO 176 */\r
+ PORT_GPDO_RESET, /* GPDO 177 */\r
+ PORT_GPDO_RESET, /* GPDO 178 */\r
+ PORT_GPDO_RESET, /* GPDO 179 */\r
+ PORT_GPDO_RESET, /* GPDO 180 */\r
+ PORT_GPDO_RESET, /* GPDO 181 */\r
+ PORT_GPDO_RESET, /* GPDO 182 */\r
+ PORT_GPDO_RESET, /* GPDO 183 */\r
+ PORT_GPDO_RESET, /* GPDO 184 */\r
+ PORT_GPDO_RESET, /* GPDO 185 */\r
+ PORT_GPDO_RESET, /* GPDO 186 */\r
+ PORT_GPDO_RESET, /* GPDO 187 */\r
+ PORT_GPDO_RESET, /* GPDO 188 */\r
+ PORT_GPDO_RESET, /* GPDO 189 */\r
+ PORT_GPDO_RESET, /* GPDO 190 */\r
+ PORT_GPDO_RESET, /* GPDO 191 */\r
+ PORT_GPDO_RESET, /* GPDO 192 */\r
+ PORT_GPDO_RESET, /* GPDO 193 */\r
+ PORT_GPDO_RESET, /* GPDO 194 */\r
+ PORT_GPDO_RESET, /* GPDO 195 */\r
+ PORT_GPDO_RESET, /* GPDO 196 */\r
+ PORT_GPDO_RESET, /* GPDO 197 */\r
+ PORT_GPDO_RESET, /* GPDO 198 */\r
+ PORT_GPDO_RESET, /* GPDO 199 */\r
+ PORT_GPDO_RESET, /* GPDO 200 */\r
+ PORT_GPDO_RESET, /* GPDO 201 */\r
+ PORT_GPDO_RESET, /* GPDO 202 */\r
+ PORT_GPDO_RESET, /* GPDO 203 */\r
+ PORT_GPDO_RESET, /* GPDO 204 */\r
+ PORT_GPDO_RESET, /* GPDO 205 */\r
+ PORT_GPDO_RESET, /* GPDO 206 */\r
+ PORT_GPDO_RESET, /* GPDO 207 */\r
+ PORT_GPDO_RESET, /* GPDO 208 */\r
+ PORT_GPDO_RESET, /* GPDO 209 */\r
+ PORT_GPDO_RESET, /* GPDO 210 */\r
+ PORT_GPDO_RESET, /* GPDO 211 */\r
+ PORT_GPDO_RESET, /* GPDO 212 */\r
+ PORT_GPDO_RESET, /* GPDO 213 */\r
};\r
\r
const Port_ConfigType PortConfigData =\r
.padConfig = PortPadConfigData,\r
.outCnt = sizeof(PortOutConfigData),\r
.outConfig = PortOutConfigData,\r
-};
\ No newline at end of file
+};\r
-/* \r
-* Configuration of module Port (Port_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC5567\r
-* \r
-* Module vendor: ArcCore\r
-* Module version: 1.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 09 13:44:55 CEST 2010\r
-*/\r
-\r
-\r
-#if (PORT_SW_MAJOR_VERSION != 1) \r
-#error "Port: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:50:58 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef PORT_CFG_H_\r
#define PORT_CFG_H_\r
\r
#define PORT_VERSION_INFO_API STD_OFF\r
#define PORT_DEV_ERROR_DETECT STD_ON\r
-#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_OFF\r
-\r
-#define BIT0 (1<<15)\r
-#define BIT1 (1<<14)\r
-#define BIT2 (1<<13)\r
-#define BIT3 (1<<12)\r
-#define BIT4 (1<<11)\r
-#define BIT5 (1<<10)\r
-#define BIT6 (1<<9)\r
-#define BIT7 (1<<8)\r
-#define BIT8 (1<<7)\r
-#define BIT9 (1<<6)\r
-#define BIT10 (1<<5)\r
-#define BIT11 (1<<4)\r
-#define BIT12 (1<<3)\r
-#define BIT13 (1<<2)\r
-#define BIT14 (1<<1)\r
-#define BIT15 (1<<0)\r
-\r
-#define WPE_BIT BIT14\r
-#define WPS_BIT BIT15\r
-#define SRC0 BIT12\r
-#define SRC1 BIT13\r
-\r
-#define PULL_UP (WPE_BIT|WPS_BIT)\r
-#define PULL_DOWN (WPE_BIT)\r
-#define PULL_NONE 0\r
-#define SLEW_RATE_MIN 0\r
-#define SLEW_RATE_MED BIT13\r
-#define SLEW_RATE_MAX (BIT12|BIT13)\r
-#define HYS_ENABLE BIT11\r
-#define ODE_ENABLE BIT10\r
-#define IBE_ENABLE BIT7\r
-#define OBE_ENABLE BIT6\r
-#define IO (0)\r
-#define FUNC0 (0)\r
-#define FUNC1 (BIT5)\r
-#define FUNC2 (BIT4)\r
-#define FUNC3 (BIT4|BIT5)\r
-#define FUNC4 (BIT3)\r
-\r
-#define PCR_RESET (0)\r
-#define GPDO_RESET (0)\r
-\r
-#define GPDO_HIGH (1)\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_IO (0)\r
+#define PORT_FUNC0 (0)\r
+#define PORT_FUNC1 (PORT_BIT5)\r
+#define PORT_FUNC2 (PORT_BIT4)\r
+#define PORT_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+#define PORT_FUNC4 (PORT_BIT3)\r
+\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_GPDO_RESET (0)\r
+\r
+#define PORT_GPDO_HIGH (1)\r
\r
\r
typedef uint16 Port_PinType;\r
\r
extern const Port_ConfigType PortConfigData;\r
\r
+#define PORT_PIN_NAME_EMIOS10 189 \r
+#define PORT_PIN_NAME_EMIOS12 191 \r
+\r
#endif /* PORT_CFG_H_ */\r
-/* \r
-* Configuration of module Pwm (Pwm_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC5567\r
-* \r
-* Module vendor: ArcCore\r
-* Module version: 1.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 09 15:05:32 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:50:59 CET 2011\r
+ */\r
\r
/*\r
* Pwm_Cfg.c\r
},\r
#if PWM_NOTIFICATION_SUPPORTED==ON\r
.NotificationHandlers = {\r
- // Notification routine for PWM_CHANNEL_1\r
- MyPwmNotificationRoutine,\r
- \r
- // Notification routine for PWM_CHANNEL_2\r
- NULL,\r
- \r
+// Notification routine for PWM_CHANNEL_1\r
+ MyPwmNotificationRoutine, \r
+// Notification routine for PWM_CHANNEL_2\r
+ NULL, \r
}\r
#endif\r
};\r
- \r
-/* \r
-* Configuration of module Pwm (Pwm_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC5567\r
-* \r
-* Module vendor: ArcCore\r
-* Module version: 1.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 09 15:05:32 CEST 2010\r
-*/\r
-\r
-\r
-#if (PWM_SW_MAJOR_VERSION != 1) \r
-#error "Pwm: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:50:59 CET 2011\r
+ */\r
\r
+
+#if !(((PWM_SW_MAJOR_VERSION == 1) && (PWM_SW_MINOR_VERSION == 0)) )
+#error "Pwm: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef PWM_CFG_H_\r
#define PWM_CFG_H_\r
}\r
\r
#endif /* PWM_CFG_H_ */\r
-
\ No newline at end of file
obj-y += Hooks.o\r
obj-y += Rte.o\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
+VPATH += ../\r
+\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
inc-y += $(ROOTDIR)/system/kernel/include\r
\r
#TODO: Remove?, Build other way?\r
-VPATH += $(ROOTDIR)/$(SUBDIR)/Rte\r
-inc-y += $(ROOTDIR)/$(SUBDIR)/Rte\r
+VPATH += ../Rte\r
+inc-y += ../Rte\r
VPATH += $(ROOTDIR)/components/pwm_sine\r
inc-y += $(ROOTDIR)/components/pwm_sine\r
\r
\r
# libs needed by us \r
-libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+#libitem-y +=\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = pwm_node.elf\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>pwm_node_hcs12</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="a1b3a0d6-0216-40cc-81df-752fcd91de29">\r
+ <SHORT-NAME>pwm_node_hcs12</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <REVISION-LABEL>Rev1</REVISION-LABEL>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">HCS12</SD>\r
+ <SD GID="AUTHOR">Arccore AB</SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/pwm_node_hcs12/SwComposition_pwm_node_hcs12</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_hcs12/Port</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_hcs12/Pwm</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_hcs12/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="2ec29ad6-98e5-4f7a-b293-6d56e92a0fe8">\r
+ <SHORT-NAME>SwComposition_pwm_node_hcs12</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="a06e6eca-b8f3-40ee-b70a-526e9d07d86d">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="256a7c74-3a97-4041-a4f6-fdab77196a48">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fe36d864-a9cf-47e9-99f4-179f339fea26">\r
+ <SHORT-NAME>II2C</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="13de6916-4779-4cf9-aa84-6423f24b5c75">\r
+ <SHORT-NAME>SDA</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>38</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d40af306-47db-4163-866b-ed234f4d54aa">\r
+ <SHORT-NAME>SCL</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>39</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c9118c42-7541-4c3e-aee5-9b33fb38e7de">\r
+ <SHORT-NAME>CAN0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="48995106-5317-492c-a8be-9dc90f86dce9">\r
+ <SHORT-NAME>TXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>49</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f355a281-9d29-4662-bd38-93b45a67b181">\r
+ <SHORT-NAME>RXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="970071df-1367-4fa6-b8ba-d12184ac9016">\r
+ <SHORT-NAME>LEDBAR</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="e75826c4-11e9-4c78-a62e-f64155f4d104">\r
+ <SHORT-NAME>PB0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f13211c5-d930-4315-88ac-f7baf7a013e1">\r
+ <SHORT-NAME>PB1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>17</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1bc00010-6ebe-436f-92e1-2d6c0895aa46">\r
+ <SHORT-NAME>PB2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>18</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0009d8fa-ebd5-451b-83f7-8a7e7fcc0ced">\r
+ <SHORT-NAME>PB3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>19</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="68143d0f-27ba-4bae-ad00-b8ca9392392d">\r
+ <SHORT-NAME>PB4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6367f310-133b-4b10-9275-5519396b82ff">\r
+ <SHORT-NAME>PB5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>21</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="59aa2eb4-ebde-472b-b5c1-ceecfce4336d">\r
+ <SHORT-NAME>PB6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>22</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4a169d18-36d5-40a7-8831-faf22622a866">\r
+ <SHORT-NAME>PB7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>23</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a0e9802a-f4ed-4ad3-b495-49157e822336">\r
+ <SHORT-NAME>DIPSW</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="27cbd4e4-129a-4364-be2b-a0054fb86cbe">\r
+ <SHORT-NAME>PH0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>24</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="30a97936-de39-42de-a3a9-d1e30f12af4d">\r
+ <SHORT-NAME>PH1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>25</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="084b83ee-4c09-4111-b19d-276dab9070ae">\r
+ <SHORT-NAME>PH2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>26</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7f90b11-a909-451c-a93e-b0bbe01df46a">\r
+ <SHORT-NAME>PH3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>27</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="417bb21d-caf2-48c2-a198-814203dc94da">\r
+ <SHORT-NAME>PH4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>28</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6e4f5953-9390-42fd-b33d-86736b010307">\r
+ <SHORT-NAME>PH5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>29</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="02660e29-0e6a-4781-98c8-74a3c9b908ef">\r
+ <SHORT-NAME>PH6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d85861f9-9523-45ad-aa84-44647733487b">\r
+ <SHORT-NAME>PH7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>31</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="103ee4c6-92df-4eae-b87a-096ccf9b56e2">\r
+ <SHORT-NAME>TIMER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="18f35583-11aa-4af3-a7cb-6bf56494047e">\r
+ <SHORT-NAME>PT0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>72</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="58635cff-b40b-41d7-879a-ea79efc33e06">\r
+ <SHORT-NAME>PT1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>73</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="99e5f077-39d8-48c6-8085-6b0764b0c48d">\r
+ <SHORT-NAME>BEEPER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>74</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="95d6d2f4-2db4-4495-84ed-fa8032997f5b">\r
+ <SHORT-NAME>PWM</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="89bf9c10-ceb3-4d60-961c-1051ed4b031d">\r
+ <SHORT-NAME>PP0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="182cd6da-fc4c-4b21-8ad3-57e3e8c3568a">\r
+ <SHORT-NAME>PP1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a1fa03c0-2470-4914-aabd-17c992c74a92">\r
+ <SHORT-NAME>SCI0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9b4e54e6-bc5b-4ccb-b5d9-33670baae41c">\r
+ <SHORT-NAME>RXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1ae13d69-adf7-481a-929d-0c916d37daee">\r
+ <SHORT-NAME>TXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1d78b7b3-38f6-486c-89b2-3369eab9e7df">\r
+ <SHORT-NAME>SCI1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="19e08fdf-14d6-4cfe-aa28-969f9479fde7">\r
+ <SHORT-NAME>RXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>58</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="580e6d9e-8812-438d-9b01-94f8b2cda75f">\r
+ <SHORT-NAME>TXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>59</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="218ea307-52d6-4837-abfb-080872edd058">\r
+ <SHORT-NAME>PM6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>54</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ac024e84-9ae2-4303-a186-6a93ffc0902b">\r
+ <SHORT-NAME>PM7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>55</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="19e54a5c-c778-4d34-88ae-80eaf1fff9d8">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="17747ce9-57d3-476c-8203-8c93cd2a5dcc">\r
+ <SHORT-NAME>Pwm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Pwm</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="ecc119e4-7869-41cc-af30-3792813737cf">\r
+ <SHORT-NAME>PwmChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="0d1ebc17-ef4d-4193-a492-7d8291ed2dca">\r
+ <SHORT-NAME>PWM_CHANNEL_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmCenterAlign</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmScaledClockEnable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>24576</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>188.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>POLARITY_NORMAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a05dbf4b-56e8-4e6b-8139-4864371f67c2">\r
+ <SHORT-NAME>PWM_CHANNEL_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmCenterAlign</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmScaledClockEnable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>188.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>POLARITY_NORMAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c2a3ced7-5cde-4ca0-804f-9adeb4730fc4">\r
+ <SHORT-NAME>PwmConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmGetOutputState</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetDutyCycle</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetOutputToIdle</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetPeriodAndDuty</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b4c0e419-333e-4370-8f36-28034d382f59">\r
+ <SHORT-NAME>PwmGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmFreezeEnable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDevErorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDutycycleUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmIndex</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmNotificationSupported</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmPeriodUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerA</DEFINITION-REF>\r
+ <VALUE>PRESCALER_128</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerB</DEFINITION-REF>\r
+ <VALUE>PRESCALER_2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerA</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerB</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="69109d4c-3493-478e-be8d-aff53b32a590">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="68ccafa9-c2b1-43e1-93c9-3fd1c8f4fff9">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="5862f0c9-1e5a-4f23-b2c4-8e051b6d948b">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a7cff35b-d536-41ef-a65a-40242e4f63f8">\r
+ <SHORT-NAME>bTask25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4cad9ed3-b331-4bb9-bbd8-11181c7e9e0b">\r
+ <SHORT-NAME>bTask100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="39e56da8-cecd-4bee-81b7-273a13d65515">\r
+ <SHORT-NAME>Startup</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="d520590f-1abd-49c6-943b-ab880a36ff0f">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="363499a7-ab29-4eaf-9c73-718a6404395d">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="71c16123-17bc-4752-9536-120eaf67e681">\r
+ <SHORT-NAME>Alarm25</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node_hcs12/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fd442fa2-11a4-41ca-a016-a41ce867ca9f">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node_hcs12/Os/bTask25</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="775e10d2-a210-4b79-bbfc-5cb3a3a1adf7">\r
+ <SHORT-NAME>Alarm100</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node_hcs12/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="63e7ab95-16cd-4565-9cc9-f2f9dd2e1df3">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node_hcs12/Os/bTask100</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="55d13f76-fbd7-4f4f-894f-6e893bb4af68">\r
<SHORT-NAME>pwm_node_mpc5567</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SD GID="MCU">MPC5567</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/pwm_node_mpc5567/SwComposition_pwm_node_mpc5567</ECU-SW-COMPOSITION-REF>\r
<MODULE-REFS>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc5567/Port</MODULE-REF>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node_mpc5567/Pwm</MODULE-REF>\r
<SHORT-NAME>Port</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
<SHORT-NAME>Pwm</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">1.0.0</SD>\r
</ENUMERATION-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FLOAT-VALUE>\r
<DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
</CONTAINER>\r
</CONTAINERS>\r
</MODULE-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="11a49707-21e6-4cba-b31c-dccc09708eed">\r
+ <SHORT-NAME>SwComposition_pwm_node_mpc5567</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
\r
\r
#include "Os.h"\r
+#include "Mcu.h"\r
#include <stdio.h>\r
#include <assert.h>\r
-#define USE_TRACE 1\r
-#include "debug.h"\r
-#include "Mcu.h"\r
-\r
-\r
-#if 0\r
-#ifdef USE_STARTUPHOOK\r
-#ifdef CFG_MPC55XX\r
-#if !defined(USE_SIMULATOR)\r
-// Quick fix\r
-//#include "Kernel_Offset.h"\r
\r
-extern uint8_t pcb_list[];\r
-\r
-#endif\r
-#endif\r
-#endif\r
-#endif\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
+#include "debug.h"\r
\r
\r
\r
/* Global hooks */\r
ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
- LDEBUG_PRINTF("## ProtectionHook\n");\r
+ LDEBUG_FPUTS("## ProtectionHook\n");\r
return PRO_KILLAPPL;\r
}\r
\r
void StartupHook( void ) {\r
- LDEBUG_PRINTF("## StartupHook\n");\r
+ LDEBUG_FPUTS("## StartupHook\n");\r
\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
-\r
- LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
+ LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)McuE_GetSystemClock());\r
}\r
\r
void ShutdownHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ShutdownHook\n");\r
+ LDEBUG_FPUTS("## ShutdownHook\n");\r
while(1);\r
}\r
\r
void PostTaskHook( void ) {\r
// LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
}\r
-\r
-#if 0\r
-struct OsHooks os_conf_global_hooks = {\r
- .StartupHook = StartupHook,\r
- .ProtectionHook = ProtectionHook,\r
- .ShutdownHook = ShutdownHook,\r
- .ErrorHook = ErrorHook,\r
- .PreTaskHook = PreTaskHook,\r
- .PostTaskHook = PostTaskHook\r
- };\r
-#endif\r
#include "EcuM.h"\r
#include <stdio.h>\r
#include <assert.h>\r
-#include "debug.h"\r
#include "Com.h"\r
#include "pwm_node2_helpers.h"\r
\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
+#include "debug.h"\r
+\r
void OsIdle( void ) {\r
for(;;);\r
}\r
// Call second phase of startup sequence.\r
EcuM_StartupTwo();\r
\r
+ // Startup CanIf due to ComM is missing in this example\r
+ CanIf_InitController(CANIF_CHANNEL_0, CANIF_CHANNEL_0_CONFIG_0);\r
+ CanIf_SetControllerMode(CANIF_CHANNEL_0, CANIF_CS_STARTED);\r
+\r
// Make sure that the right PDU-groups are ready for communication.\r
Com_IpduGroupStart(RxGroup, 0);\r
\r
+\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU\r
-\r
-SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+MOD_USE+=KERNEL MCU ECUM DET PORT COM CAN CANIF PWM RAMLOG\r
+++ /dev/null
-/* \r
-* Configuration of module Com (Com_PbCfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#include "Com.h"\r
-#include "stdlib.h"\r
-#if defined(USE_PDUR)\r
-#include "PduR.h"\r
-#endif\r
-\r
-\r
-\r
-\r
-\r
-/*\r
- * Signal init values.\r
- */\r
-const uint16 Com_SignalInitValue_SetLedLevelRx = 0;\r
- \r
-\r
-/*\r
- * Group signal definitions\r
- */\r
-const ComGroupSignal_type ComGroupSignal[] = {\r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-\r
-/* SignalGroup GroupSignals lists. */\r
-\r
-/*\r
- * Signal definitions\r
- */\r
-const ComSignal_type ComSignal[] = {\r
- {\r
- .ComHandleId = SetLedLevelRx,\r
- .ComFirstTimeoutFactor = 0,\r
- .ComNotification = NULL,\r
- .ComTimeoutFactor = 0,\r
- .ComTimeoutNotification = NULL,\r
- .ComTransferProperty = TRIGGERED,\r
- \r
- \r
- .ComSignalInitValue = &Com_SignalInitValue_SetLedLevelRx,\r
- .ComBitPosition = 7,\r
- .ComBitSize = 16,\r
- .ComSignalEndianess = BIG_ENDIAN,\r
- .ComSignalType = UINT16,\r
- .ComGroupSignal = NULL,\r
- \r
- },\r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-\r
-/*\r
- * I-PDU group definitions\r
- */\r
-const ComIPduGroup_type ComIPduGroup[] = {\r
- {\r
- .ComIPduGroupHandleId = RxGroup\r
- },\r
- \r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-/* IPdu signal lists. */\r
-const ComSignal_type *ComIPduSignalRefs_LedCommandRx[] = {\r
- &ComSignal[ SetLedLevelRx ], \r
- NULL,\r
-};\r
-\r
-/*\r
- * I-PDU definitions\r
- */\r
-const ComIPdu_type ComIPdu[] = { \r
- \r
- { // LedCommandRx\r
- .ArcIPduOutgoingId = PDUR_SOURCE_PDU_ID_LedCommandRx,\r
- .ComIPduCallout = NULL,\r
- .ComIPduSignalProcessing = DEFERRED,\r
- .ComIPduSize = 8,\r
- .ComIPduDirection = RECEIVE,\r
- .ComIPduGroupRef = RxGroup,\r
- \r
- .ComIPduSignalRef = ComIPduSignalRefs_LedCommandRx,\r
- }, \r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-const Com_ConfigType ComConfiguration = {\r
- .ComConfigurationId = 1,\r
- .ComIPdu = ComIPdu,\r
- .ComIPduGroup = ComIPduGroup,\r
- .ComSignal = ComSignal,\r
- .ComGroupSignal = ComGroupSignal\r
-};\r
-\r
-\r
+++ /dev/null
-/* \r
-* Configuration of module Com (Com_PbCfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (COM_SW_MAJOR_VERSION != 1) \r
-#error "Com: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-#ifndef COM_PBCFG_H_\r
-#define COM_PBCFG_H_\r
-\r
-#include "Com_Types.h"\r
-\r
-extern const Com_ConfigType ComConfiguration;\r
-\r
-// COM Polite Defines.\r
-#define COM_PDU_ID_LedCommandRx 0\r
-\r
-\r
-\r
-// PDU group definitions\r
-enum {\r
- RxGroup = 0,\r
-};\r
-\r
-// Signal definitions\r
-enum {\r
- SetLedLevelRx = 0,\r
-};\r
-\r
-\r
-\r
-\r
-#endif /* COM_PBCFG_H_ */\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Callout_template.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 14:42:38 CEST 2010\r
-*/\r
-\r
-\r
-#include "EcuM.h"\r
-#include "Det.h"\r
-#if defined(USE_DEM)\r
-#include "Dem.h"\r
-#endif\r
-#if defined(USE_MCU)\r
-#include "Mcu.h"\r
-#endif\r
-#if defined(USE_GPT)\r
-#include "Gpt.h"\r
-#endif\r
-#if defined(USE_CAN)\r
-#include "Can.h"\r
-#endif\r
-#if defined(USE_CANIF)\r
-#include "CanIf.h"\r
-#endif\r
-#if defined(USE_PDUR)\r
-#include "PduR.h"\r
-#endif\r
-#if defined(USE_COM)\r
-#include "Com.h"\r
-#endif\r
-#if defined(USE_CANTP)\r
-#include "CanTp.h"\r
-#endif\r
-#if defined(USE_DCM)\r
-#include "Dcm.h"\r
-#endif\r
-#if defined(USE_PWM)\r
-#include "Pwm.h"\r
-#endif\r
-#if defined(USE_IOHWAB)\r
-#include "IoHwAb.h"\r
-#endif\r
-\r
-void EcuM_AL_DriverInitZero()\r
-{\r
- Det_Init();\r
- Det_Start();\r
-}\r
-\r
-EcuM_ConfigType* EcuM_DeterminePbConfiguration()\r
-{\r
- return &EcuMConfig;\r
-}\r
-\r
-void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
-{\r
-#if defined(USE_MCU)\r
- Mcu_Init(ConfigPtr->McuConfig);\r
-\r
- // Set up default clock (Mcu_InitClock requires initRun==1)\r
- Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
-\r
- // Wait for PLL to sync.\r
- while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
- ;\r
-#endif\r
-\r
-#if defined(USE_DEM)\r
- // Preinitialize DEM\r
- Dem_PreInit();\r
-#endif\r
-\r
-#if defined(USE_PORT)\r
- // Setup Port\r
- Port_Init(ConfigPtr->PortConfig);\r
-#endif\r
-\r
-\r
-#if defined(USE_GPT)\r
- // Setup the GPT\r
- Gpt_Init(ConfigPtr->GptConfig);\r
-#endif\r
-\r
- // Setup watchdog\r
- // TODO\r
-\r
-#if defined(USE_DMA)\r
- // Setup DMA\r
- Dma_Init(ConfigPtr->DmaConfig);\r
-#endif\r
-\r
-#if defined(USE_ADC)\r
- // Setup ADC\r
- Adc_Init(ConfigPtr->AdcConfig);\r
-#endif\r
-\r
- // Setup ICU\r
- // TODO\r
-\r
- // Setup PWM\r
-#if defined(USE_PWM)\r
- // Setup PWM\r
- Pwm_Init(ConfigPtr->PwmConfig);\r
-#endif\r
-}\r
-\r
-void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
-{\r
-#if defined(USE_SPI)\r
- // Setup SPI\r
- Spi_Init(ConfigPtr->SpiConfig);\r
-#endif\r
-\r
-#if defined(USE_EEP)\r
- // Setup EEP\r
- Eep_Init(ConfigPtr->EEpConfig);\r
-#endif\r
-\r
-#if defined(USE_FLS)\r
- // Setup Flash\r
- FlashInit(ConfigPtr->FlashConfig);\r
-#endif\r
-\r
- // Setup NVRAM Manaager\r
- // TODO\r
-\r
- // Setup CAN tranceiver\r
- // TODO\r
-\r
-#if defined(USE_CAN)\r
- // Setup Can driver\r
- Can_Init(ConfigPtr->CanConfig);\r
-#endif\r
-\r
-#if defined(USE_CANIF)\r
- // Setup CanIf\r
- CanIf_Init(ConfigPtr->CanIfConfig);\r
-#endif\r
-\r
-#if defined(USE_CANTP)\r
- // Setup CAN TP\r
- CanTp_Init();\r
-#endif\r
- // Setup LIN\r
- // TODO\r
-\r
-#if defined(USE_PDUR)\r
- // Setup PDU Router\r
- PduR_Init(ConfigPtr->PduRConfig);\r
-#endif\r
-\r
-#if defined(USE_COM)\r
- // Setup COM layer\r
- Com_Init(ConfigPtr->ComConfig);\r
-#endif\r
-\r
-#if defined(USE_DCM)\r
- // Setup DCM\r
- Dcm_Init();\r
-#endif\r
-\r
-#if defined(USE_IOHWAB)\r
- // Setup IO hardware abstraction layer\r
- IoHwAb_Init();\r
-#endif\r
-\r
-}\r
-\r
-void EcuM_AL_DriverInitThree(const EcuM_ConfigType ConfigPtr)\r
-{\r
-#if defined(USE_DEM)\r
- // Setup DEM\r
- Dem_Init();\r
-#endif\r
-\r
-#if defined(USE_CANIF)\r
- // Startup the CAN interafce; due to the missing COM manager\r
- CanIf_InitController(CANIF_CHANNEL_0, CANIF_CHANNEL_0_CONFIG_0);\r
- CanIf_SetControllerMode(CANIF_CHANNEL_0, CANIF_CS_STARTED);\r
-#endif\r
-}\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 14:42:38 CEST 2010\r
-*/\r
-\r
-\r
-\r
-#include "EcuM.h"\r
-\r
-EcuM_ConfigType EcuMConfig =\r
-{\r
- .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
- .EcuMDefaultShutdownMode = 0, // Don't care\r
- .EcuMDefaultAppMode = 0, // Don't care\r
-\r
-#if defined(USE_MCU)\r
- .McuConfig = McuConfigData,\r
-#endif\r
-#if defined(USE_PORT)\r
- .PortConfig = &PortConfigData,\r
-#endif\r
-#if defined(USE_CAN)\r
- .CanConfig = &CanConfigData,\r
-#endif\r
-#if defined(USE_CANIF)\r
- .CanIfConfig = &CanIf_Config,\r
-#endif\r
-#if defined(USE_COM)\r
- .ComConfig = &ComConfiguration,\r
-#endif\r
-#if defined(USE_PDUR)\r
- .PduRConfig = &PduR_Config,\r
-#endif\r
-#if defined(USE_DMA)\r
- .DmaConfig = DmaConfig,\r
-#endif\r
-#if defined(USE_ADC)\r
- .AdcConfig = AdcConfig,\r
-#endif\r
-#if defined(USE_PWM)\r
- .PwmConfig = &PwmConfig,\r
-#endif\r
-#if defined(USE_GPT)\r
- .GptConfig = GptConfigData,\r
-#endif\r
-};\r
-\r
-void EcuM_OnGoOffTwo( void ) {\r
-\r
-}\r
-\r
-void EcuM_AL_SwitchOff( void ) {\r
-\r
-}\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (ECUM_SW_MAJOR_VERSION != 1) \r
-#error "EcuM: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
-\r
-#define ECUM_VERSION_INFO_API STD_OFF\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-#define ECUM_DEV_ERROR_DETECT STD_OFF\r
-\r
-#include "EcuM_Generated_Types.h"\r
-\r
-extern EcuM_ConfigType EcuMConfig;\r
-\r
-#endif /*ECUM_CFG_H_*/\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Generated_Types.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 14:42:38 CEST 2010\r
-*/\r
-\r
-\r
-#if (ECUM_SW_MAJOR_VERSION != 1) \r
-#error "EcuM: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-#ifndef _ECUM_GENERATED_TYPES_H_\r
-#define _ECUM_GENERATED_TYPES_H_\r
-\r
-#if defined(USE_MCU)\r
-#include "Mcu.h"\r
-#endif\r
-#if defined(USE_PORT)\r
-#include "Port.h"\r
-#endif\r
-#if defined(USE_CAN)\r
-#include "Can.h"\r
-#endif\r
-#if defined(USE_CANIF)\r
-#include "CanIf.h"\r
-#endif\r
-#if defined(USE_PWM)\r
-#include "Pwm.h"\r
-#endif\r
-#if defined(USE_COM)\r
-#include "Com.h"\r
-#endif\r
-#if defined(USE_PDUR)\r
-#include "PduR.h"\r
-#endif\r
-#if defined(USE_DMA)\r
-#include "Dma.h"\r
-#endif\r
-#if defined(USE_ADC)\r
-#include "Adc.h"\r
-#endif\r
-#if defined(USE_GPT)\r
-#include "Gpt.h"\r
-#endif\r
-\r
-\r
-typedef struct\r
-{\r
- EcuM_StateType EcuMDefaultShutdownTarget;\r
- uint8 EcuMDefaultShutdownMode;\r
- AppModeType EcuMDefaultAppMode;\r
-\r
-#if defined(USE_MCU)\r
- const Mcu_ConfigType* McuConfig;\r
-#endif\r
-#if defined(USE_PORT)\r
- const Port_ConfigType* PortConfig;\r
-#endif\r
-#if defined(USE_CAN)\r
- const Can_ConfigType* CanConfig;\r
-#endif\r
-#if defined(USE_CANIF)\r
- const CanIf_ConfigType* CanIfConfig;\r
-#endif\r
-#if defined(USE_COM)\r
- const Com_ConfigType* ComConfig;\r
-#endif\r
-#if defined(USE_PDUR)\r
- const PduR_PBConfigType* PduRConfig;\r
-#endif\r
-#if defined(USE_PWM)\r
- const Pwm_ConfigType* PwmConfig;\r
-#endif\r
-#if defined(USE_DMA)\r
- const Dma_ConfigType* DmaConfig;\r
-#endif\r
-#if defined(USE_ADC)\r
- const Adc_ConfigType* AdcConfig;\r
-#endif\r
-#if defined(USE_GPT)\r
- const Gpt_ConfigType* GptConfig;\r
-#endif\r
-} EcuM_ConfigType;\r
-\r
-#endif /*_ECUM_GENERATED_TYPES_H_*/\r
+++ /dev/null
-/* \r
-* Configuration of module Port (Port_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:34 CEST 2010\r
-*/\r
-\r
- \r
-// File generated on Fri Apr 30 15:56:34 CEST 2010\r
-// File generated by com.arccore.bswbuilder.modules.port.mpc5516\r
-\r
-#include "Port.h"\r
-#include "Port_Cfg.h"\r
-#include "stdlib.h"\r
-\r
-const uint16_t PortPadConfigData[] = {\r
- PCR_RESET, /* PCR 0 */\r
- PCR_RESET, /* PCR 1 */\r
- PCR_RESET, /* PCR 2 */\r
- PCR_RESET, /* PCR 3 */\r
- PCR_RESET, /* PCR 4 */\r
- PCR_RESET, /* PCR 5 */\r
- PCR_RESET, /* PCR 6 */\r
- PCR_RESET, /* PCR 7 */\r
- PCR_RESET, /* PCR 8 */\r
- PCR_RESET, /* PCR 9 */\r
- PCR_RESET, /* PCR 10 */\r
- PCR_RESET, /* PCR 11 */\r
- PCR_RESET, /* PCR 12 */\r
- PCR_RESET, /* PCR 13 */\r
- PCR_RESET, /* PCR 14 */\r
- PCR_RESET, /* PCR 15 */\r
- PCR_RESET, /* PCR 16 */\r
- PCR_RESET, /* PCR 17 */\r
- PCR_RESET, /* PCR 18 */\r
- PCR_RESET, /* PCR 19 */\r
- PCR_RESET, /* PCR 20 */\r
- PCR_RESET, /* PCR 21 */\r
- PCR_RESET, /* PCR 22 */\r
- PCR_RESET, /* PCR 23 */\r
- PCR_RESET, /* PCR 24 */\r
- PCR_RESET, /* PCR 25 */\r
- PCR_RESET, /* PCR 26 */\r
- PCR_RESET, /* PCR 27 */\r
- PCR_RESET, /* PCR 28 */\r
- PCR_RESET, /* PCR 29 */\r
- PCR_RESET, /* PCR 30 */\r
- PCR_RESET, /* PCR 31 */\r
- PCR_RESET, /* PCR 32 */\r
- PCR_RESET, /* PCR 33 */\r
- PCR_RESET, /* PCR 34 */\r
- PCR_RESET, /* PCR 35 */\r
- PCR_RESET, /* PCR 36 */\r
- PCR_RESET, /* PCR 37 */\r
- PCR_RESET, /* PCR 38 */\r
- PCR_RESET, /* PCR 39 */\r
- PCR_RESET, /* PCR 40 */\r
- PCR_RESET, /* PCR 41 */\r
- PCR_RESET, /* PCR 42 */\r
- PCR_RESET, /* PCR 43 */\r
- PCR_RESET, /* PCR 44 */\r
- ( FUNC1 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 45 : PORT_PIN_MODE_PWM */\r
- PCR_RESET, /* PCR 46 */\r
- PCR_RESET, /* PCR 47 */\r
- ( FUNC1 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 48 : PORT_PIN_MODE_CAN */\r
- ( FUNC1 | IBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 49 : PORT_PIN_MODE_CAN */\r
- PCR_RESET, /* PCR 50 */\r
- PCR_RESET, /* PCR 51 */\r
- PCR_RESET, /* PCR 52 */\r
- PCR_RESET, /* PCR 53 */\r
- PCR_RESET, /* PCR 54 */\r
- PCR_RESET, /* PCR 55 */\r
- PCR_RESET, /* PCR 56 */\r
- PCR_RESET, /* PCR 57 */\r
- PCR_RESET, /* PCR 58 */\r
- PCR_RESET, /* PCR 59 */\r
- PCR_RESET, /* PCR 60 */\r
- PCR_RESET, /* PCR 61 */\r
- PCR_RESET, /* PCR 62 */\r
- PCR_RESET, /* PCR 63 */\r
- PCR_RESET, /* PCR 64 */\r
- PCR_RESET, /* PCR 65 */\r
- PCR_RESET, /* PCR 66 */\r
- PCR_RESET, /* PCR 67 */\r
- PCR_RESET, /* PCR 68 */\r
- PCR_RESET, /* PCR 69 */\r
- PCR_RESET, /* PCR 70 */\r
- PCR_RESET, /* PCR 71 */\r
- PCR_RESET, /* PCR 72 */\r
- PCR_RESET, /* PCR 73 */\r
- PCR_RESET, /* PCR 74 */\r
- PCR_RESET, /* PCR 75 */\r
- PCR_RESET, /* PCR 76 */\r
- PCR_RESET, /* PCR 77 */\r
- PCR_RESET, /* PCR 78 */\r
- PCR_RESET, /* PCR 79 */\r
- PCR_RESET, /* PCR 80 */\r
- PCR_RESET, /* PCR 81 */\r
- PCR_RESET, /* PCR 82 */\r
- PCR_RESET, /* PCR 83 */\r
- PCR_RESET, /* PCR 84 */\r
- PCR_RESET, /* PCR 85 */\r
- PCR_RESET, /* PCR 86 */\r
- PCR_RESET, /* PCR 87 */\r
- PCR_RESET, /* PCR 88 */\r
- PCR_RESET, /* PCR 89 */\r
- PCR_RESET, /* PCR 90 */\r
- PCR_RESET, /* PCR 91 */\r
- PCR_RESET, /* PCR 92 */\r
- PCR_RESET, /* PCR 93 */\r
- PCR_RESET, /* PCR 94 */\r
- PCR_RESET, /* PCR 95 */\r
- PCR_RESET, /* PCR 96 */\r
- PCR_RESET, /* PCR 97 */\r
- PCR_RESET, /* PCR 98 */\r
- PCR_RESET, /* PCR 99 */\r
- PCR_RESET, /* PCR 100 */\r
- PCR_RESET, /* PCR 101 */\r
- PCR_RESET, /* PCR 102 */\r
- PCR_RESET, /* PCR 103 */\r
- PCR_RESET, /* PCR 104 */\r
- PCR_RESET, /* PCR 105 */\r
- PCR_RESET, /* PCR 106 */\r
- PCR_RESET, /* PCR 107 */\r
- PCR_RESET, /* PCR 108 */\r
- PCR_RESET, /* PCR 109 */\r
- PCR_RESET, /* PCR 110 */\r
- PCR_RESET, /* PCR 111 */\r
- PCR_RESET, /* PCR 112 */\r
- PCR_RESET, /* PCR 113 */\r
- PCR_RESET, /* PCR 114 */\r
- PCR_RESET, /* PCR 115 */\r
- PCR_RESET, /* PCR 116 */\r
- PCR_RESET, /* PCR 117 */\r
- PCR_RESET, /* PCR 118 */\r
- PCR_RESET, /* PCR 119 */\r
- PCR_RESET, /* PCR 120 */\r
- PCR_RESET, /* PCR 121 */\r
- PCR_RESET, /* PCR 122 */\r
- PCR_RESET, /* PCR 123 */\r
- PCR_RESET, /* PCR 124 */\r
- PCR_RESET, /* PCR 125 */\r
- PCR_RESET, /* PCR 126 */\r
- PCR_RESET, /* PCR 127 */\r
- PCR_RESET, /* PCR 128 */\r
- PCR_RESET, /* PCR 129 */\r
- PCR_RESET, /* PCR 130 */\r
- PCR_RESET, /* PCR 131 */\r
- PCR_RESET, /* PCR 132 */\r
- PCR_RESET, /* PCR 133 */\r
- PCR_RESET, /* PCR 134 */\r
- PCR_RESET, /* PCR 135 */\r
- PCR_RESET, /* PCR 136 */\r
- PCR_RESET, /* PCR 137 */\r
- PCR_RESET, /* PCR 138 */\r
- PCR_RESET, /* PCR 139 */\r
- PCR_RESET, /* PCR 140 */\r
- PCR_RESET, /* PCR 141 */\r
- PCR_RESET, /* PCR 142 */\r
- PCR_RESET, /* PCR 143 */\r
- PCR_RESET, /* PCR 144 */\r
-};\r
-\r
-const uint8_t PortOutConfigData[] = {\r
- GPDO_RESET, /* GPDO 0 */\r
- GPDO_RESET, /* GPDO 1 */\r
- GPDO_RESET, /* GPDO 2 */\r
- GPDO_RESET, /* GPDO 3 */\r
- GPDO_RESET, /* GPDO 4 */\r
- GPDO_RESET, /* GPDO 5 */\r
- GPDO_RESET, /* GPDO 6 */\r
- GPDO_RESET, /* GPDO 7 */\r
- GPDO_RESET, /* GPDO 8 */\r
- GPDO_RESET, /* GPDO 9 */\r
- GPDO_RESET, /* GPDO 10 */\r
- GPDO_RESET, /* GPDO 11 */\r
- GPDO_RESET, /* GPDO 12 */\r
- GPDO_RESET, /* GPDO 13 */\r
- GPDO_RESET, /* GPDO 14 */\r
- GPDO_RESET, /* GPDO 15 */\r
- GPDO_RESET, /* GPDO 16 */\r
- GPDO_RESET, /* GPDO 17 */\r
- GPDO_RESET, /* GPDO 18 */\r
- GPDO_RESET, /* GPDO 19 */\r
- GPDO_RESET, /* GPDO 20 */\r
- GPDO_RESET, /* GPDO 21 */\r
- GPDO_RESET, /* GPDO 22 */\r
- GPDO_RESET, /* GPDO 23 */\r
- GPDO_RESET, /* GPDO 24 */\r
- GPDO_RESET, /* GPDO 25 */\r
- GPDO_RESET, /* GPDO 26 */\r
- GPDO_RESET, /* GPDO 27 */\r
- GPDO_RESET, /* GPDO 28 */\r
- GPDO_RESET, /* GPDO 29 */\r
- GPDO_RESET, /* GPDO 30 */\r
- GPDO_RESET, /* GPDO 31 */\r
- GPDO_RESET, /* GPDO 32 */\r
- GPDO_RESET, /* GPDO 33 */\r
- GPDO_RESET, /* GPDO 34 */\r
- GPDO_RESET, /* GPDO 35 */\r
- GPDO_RESET, /* GPDO 36 */\r
- GPDO_RESET, /* GPDO 37 */\r
- GPDO_RESET, /* GPDO 38 */\r
- GPDO_RESET, /* GPDO 39 */\r
- GPDO_RESET, /* GPDO 40 */\r
- GPDO_RESET, /* GPDO 41 */\r
- GPDO_RESET, /* GPDO 42 */\r
- GPDO_RESET, /* GPDO 43 */\r
- GPDO_RESET, /* GPDO 44 */\r
- GPDO_RESET, /* GPDO 45 */\r
- GPDO_RESET, /* GPDO 46 */\r
- GPDO_RESET, /* GPDO 47 */\r
- GPDO_RESET, /* GPDO 48 */\r
- GPDO_RESET, /* GPDO 49 */\r
- GPDO_RESET, /* GPDO 50 */\r
- GPDO_RESET, /* GPDO 51 */\r
- GPDO_RESET, /* GPDO 52 */\r
- GPDO_RESET, /* GPDO 53 */\r
- GPDO_RESET, /* GPDO 54 */\r
- GPDO_RESET, /* GPDO 55 */\r
- GPDO_RESET, /* GPDO 56 */\r
- GPDO_RESET, /* GPDO 57 */\r
- GPDO_RESET, /* GPDO 58 */\r
- GPDO_RESET, /* GPDO 59 */\r
- GPDO_RESET, /* GPDO 60 */\r
- GPDO_RESET, /* GPDO 61 */\r
- GPDO_RESET, /* GPDO 62 */\r
- GPDO_RESET, /* GPDO 63 */\r
- GPDO_RESET, /* GPDO 64 */\r
- GPDO_RESET, /* GPDO 65 */\r
- GPDO_RESET, /* GPDO 66 */\r
- GPDO_RESET, /* GPDO 67 */\r
- GPDO_RESET, /* GPDO 68 */\r
- GPDO_RESET, /* GPDO 69 */\r
- GPDO_RESET, /* GPDO 70 */\r
- GPDO_RESET, /* GPDO 71 */\r
- GPDO_RESET, /* GPDO 72 */\r
- GPDO_RESET, /* GPDO 73 */\r
- GPDO_RESET, /* GPDO 74 */\r
- GPDO_RESET, /* GPDO 75 */\r
- GPDO_RESET, /* GPDO 76 */\r
- GPDO_RESET, /* GPDO 77 */\r
- GPDO_RESET, /* GPDO 78 */\r
- GPDO_RESET, /* GPDO 79 */\r
- GPDO_RESET, /* GPDO 80 */\r
- GPDO_RESET, /* GPDO 81 */\r
- GPDO_RESET, /* GPDO 82 */\r
- GPDO_RESET, /* GPDO 83 */\r
- GPDO_RESET, /* GPDO 84 */\r
- GPDO_RESET, /* GPDO 85 */\r
- GPDO_RESET, /* GPDO 86 */\r
- GPDO_RESET, /* GPDO 87 */\r
- GPDO_RESET, /* GPDO 88 */\r
- GPDO_RESET, /* GPDO 89 */\r
- GPDO_RESET, /* GPDO 90 */\r
- GPDO_RESET, /* GPDO 91 */\r
- GPDO_RESET, /* GPDO 92 */\r
- GPDO_RESET, /* GPDO 93 */\r
- GPDO_RESET, /* GPDO 94 */\r
- GPDO_RESET, /* GPDO 95 */\r
- GPDO_RESET, /* GPDO 96 */\r
- GPDO_RESET, /* GPDO 97 */\r
- GPDO_RESET, /* GPDO 98 */\r
- GPDO_RESET, /* GPDO 99 */\r
- GPDO_RESET, /* GPDO 100 */\r
- GPDO_RESET, /* GPDO 101 */\r
- GPDO_RESET, /* GPDO 102 */\r
- GPDO_RESET, /* GPDO 103 */\r
- GPDO_RESET, /* GPDO 104 */\r
- GPDO_RESET, /* GPDO 105 */\r
- GPDO_RESET, /* GPDO 106 */\r
- GPDO_RESET, /* GPDO 107 */\r
- GPDO_RESET, /* GPDO 108 */\r
- GPDO_RESET, /* GPDO 109 */\r
- GPDO_RESET, /* GPDO 110 */\r
- GPDO_RESET, /* GPDO 111 */\r
- GPDO_RESET, /* GPDO 112 */\r
- GPDO_RESET, /* GPDO 113 */\r
- GPDO_RESET, /* GPDO 114 */\r
- GPDO_RESET, /* GPDO 115 */\r
- GPDO_RESET, /* GPDO 116 */\r
- GPDO_RESET, /* GPDO 117 */\r
- GPDO_RESET, /* GPDO 118 */\r
- GPDO_RESET, /* GPDO 119 */\r
- GPDO_RESET, /* GPDO 120 */\r
- GPDO_RESET, /* GPDO 121 */\r
- GPDO_RESET, /* GPDO 122 */\r
- GPDO_RESET, /* GPDO 123 */\r
- GPDO_RESET, /* GPDO 124 */\r
- GPDO_RESET, /* GPDO 125 */\r
- GPDO_RESET, /* GPDO 126 */\r
- GPDO_RESET, /* GPDO 127 */\r
- GPDO_RESET, /* GPDO 128 */\r
- GPDO_RESET, /* GPDO 129 */\r
- GPDO_RESET, /* GPDO 130 */\r
- GPDO_RESET, /* GPDO 131 */\r
- GPDO_RESET, /* GPDO 132 */\r
- GPDO_RESET, /* GPDO 133 */\r
- GPDO_RESET, /* GPDO 134 */\r
- GPDO_RESET, /* GPDO 135 */\r
- GPDO_RESET, /* GPDO 136 */\r
- GPDO_RESET, /* GPDO 137 */\r
- GPDO_RESET, /* GPDO 138 */\r
- GPDO_RESET, /* GPDO 139 */\r
- GPDO_RESET, /* GPDO 140 */\r
- GPDO_RESET, /* GPDO 141 */\r
- GPDO_RESET, /* GPDO 142 */\r
-};\r
-\r
-const Port_ConfigType PortConfigData =\r
-{\r
- .padCnt = sizeof(PortPadConfigData),\r
- .padConfig = PortPadConfigData,\r
- .outCnt = sizeof(PortOutConfigData),\r
- .outConfig = PortOutConfigData,\r
-};\r
+++ /dev/null
-/* \r
-* Configuration of module Port (Port_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:34 CEST 2010\r
-*/\r
-\r
-\r
-#if (PORT_SW_MAJOR_VERSION != 1) \r
-#error "Port: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-#ifndef PORT_CFG_H_\r
-#define PORT_CFG_H_\r
-\r
-#include "Std_Types.h"\r
-\r
-#define PORT_VERSION_INFO_API STD_OFF\r
-#define PORT_DEV_ERROR_DETECT STD_OFF\r
-#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_OFF\r
-\r
-#define BIT0 (1<<15)\r
-#define BIT1 (1<<14)\r
-#define BIT2 (1<<13)\r
-#define BIT3 (1<<12)\r
-#define BIT4 (1<<11)\r
-#define BIT5 (1<<10)\r
-#define BIT6 (1<<9)\r
-#define BIT7 (1<<8)\r
-#define BIT8 (1<<7)\r
-#define BIT9 (1<<6)\r
-#define BIT10 (1<<5)\r
-#define BIT11 (1<<4)\r
-#define BIT12 (1<<3)\r
-#define BIT13 (1<<2)\r
-#define BIT14 (1<<1)\r
-#define BIT15 (1<<0)\r
-\r
-#define WPE_BIT BIT14\r
-#define WPS_BIT BIT15\r
-#define SRC0 BIT12\r
-#define SRC1 BIT13\r
-\r
-#define PULL_UP (WPE_BIT|WPS_BIT)\r
-#define PULL_DOWN (WPE_BIT)\r
-#define PULL_NONE 0\r
-#define SLEW_RATE_MIN 0\r
-#define SLEW_RATE_MED BIT13\r
-#define SLEW_RATE_MAX (BIT12|BIT13)\r
-#define HYS_ENABLE BIT11\r
-#define ODE_ENABLE BIT10\r
-#define IBE_ENABLE BIT7\r
-#define OBE_ENABLE BIT6\r
-#define IO (0)\r
-#define FUNC0 (0)\r
-#define FUNC1 (BIT5)\r
-#define FUNC2 (BIT4)\r
-#define FUNC3 (BIT4|BIT5)\r
-#define FUNC4 (BIT3)\r
-\r
-#define PCR_RESET (0)\r
-#define GPDO_RESET (0)\r
-\r
-#define GPDO_HIGH (1)\r
-\r
-\r
-typedef uint16 Port_PinType;\r
-\r
-typedef struct\r
-{\r
- uint16_t padCnt;\r
- const uint16_t *padConfig;\r
- uint16_t outCnt;\r
- const uint8_t *outConfig;\r
-// uint16_t inCnt;\r
-// const uint8_t *inConfig;\r
-} Port_ConfigType;\r
-\r
-extern const Port_ConfigType PortConfigData;\r
-\r
-#endif /* PORT_CFG_H_ */\r
--- /dev/null
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+\r
+ \r
+#include "CanIf.h"\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#include "CanTp_Cbk.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm_Cbk.h"\r
+#endif\r
+#include <stdlib.h>\r
+\r
+\r
+// Imported structs from Can_Lcfg.c\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType CanConfigSetData;\r
+\r
+\r
+\r
+// Contains the mapping from CanIf-specific Channels to Can Controllers\r
+const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {\r
+ CAN_CTRL_0, // CHANNEL_0\r
+};\r
+\r
+const uint8 CanIf_Arc_ChannelDefaultConfIndex[CANIF_CHANNEL_CNT] = {\r
+ CANIF_CHANNEL_0_CONFIG_0,\r
+};\r
+\r
+// Container that gets slamed into CanIf_InitController()\r
+// Inits ALL controllers\r
+// Multiplicity 1..*\r
+const CanIf_ControllerConfigType CanIfControllerConfig[] = {\r
+ // This is the ConfigurationIndex in CanIf_InitController()\r
+ \r
+ \r
+ { \r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CANIF_CHANNEL_0,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[1],\r
+ },\r
+ \r
+};\r
+\r
+// Function callbacks for higher layers\r
+const CanIf_DispatchConfigType CanIfDispatchConfig =\r
+{\r
+ .CanIfBusOffNotification = NULL,\r
+ .CanIfWakeUpNotification = NULL, // Not used\r
+ .CanIfWakeupValidNotification = NULL, // Not used\r
+ .CanIfErrorNotificaton = NULL,\r
+};\r
+\r
+\r
+// Data for init configuration CanIfInitConfiguration\r
+\r
+ \r
+\r
+const CanIf_HthConfigType CanIfHthConfigData_Hoh_1[] =\r
+{\r
+};\r
+\r
+const CanIf_HrhConfigType CanIfHrhConfigData_Hoh_1[] =\r
+{\r
+ \r
+ {\r
+ .CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfSoftwareFilterHrh = TRUE,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_0,\r
+ .CanIfHrhIdSymRef = RxBox,\r
+ .CanIf_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] = { \r
+ \r
+ {\r
+ .CanConfigSet = &CanConfigSetData,\r
+ .CanIfHrhConfig = CanIfHrhConfigData_Hoh_1,\r
+ .CanIfHthConfig = CanIfHthConfigData_Hoh_1,\r
+ .CanIf_Arc_EOL = 1,\r
+ },\r
+};\r
+ \r
+const CanIf_TxPduConfigType CanIfTxPduConfigData[] = { \r
+};\r
+\r
+const CanIf_RxPduConfigType CanIfRxPduConfigData[] = { \r
+ {\r
+ .CanIfCanRxPduId = PDUR_DEST_PDU_ID_LedCommandRx,\r
+ .CanIfCanRxPduCanId = 291,\r
+ .CanIfCanRxPduDlc = 8,\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON ) \r
+ .CanIfReadRxPduData = false,\r
+#endif \r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadRxPduNotifyStatus = false, \r
+#endif\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfRxUserType = CANIF_USER_TYPE_CAN_PDUR,\r
+ .CanIfCanRxPduHrhRef = &CanIfHrhConfigData_Hoh_1[0],\r
+ .CanIfRxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserRxIndication = NULL,\r
+ .CanIfSoftwareFilterType = CANIF_SOFTFILTER_TYPE_MASK,\r
+ .CanIfCanRxPduCanIdMask = 0xFFF,\r
+ .PduIdRef = NULL,\r
+ }, \r
+};\r
+\r
+// This container contains the init parameters of the CAN\r
+// Multiplicity 1..*\r
+const CanIf_InitConfigType CanIfInitConfig =\r
+{\r
+ .CanIfConfigSet = 0, // Not used\r
+ .CanIfNumberOfCanRxPduIds = sizeof(CanIfRxPduConfigData)/sizeof(CanIf_RxPduConfigType),\r
+ .CanIfNumberOfCanTXPduIds = sizeof(CanIfTxPduConfigData)/sizeof(CanIf_TxPduConfigType),\r
+ .CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
+\r
+ // Containers\r
+ .CanIfHohConfigPtr = CanIfHohConfigData,\r
+ .CanIfRxPduConfigPtr = CanIfRxPduConfigData,\r
+ .CanIfTxPduConfigPtr = CanIfTxPduConfigData,\r
+};\r
+\r
+ // This container includes all necessary configuration sub-containers\r
+// according the CAN Interface configuration structure.\r
+CanIf_ConfigType CanIf_Config =\r
+{\r
+ .ControllerConfig = CanIfControllerConfig,\r
+ .DispatchConfig = &CanIfDispatchConfig,\r
+ .InitConfig = &CanIfInitConfig,\r
+ .TransceiverConfig = NULL, // Not used\r
+ .Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap, \r
+ .Arc_ChannelDefaultConfIndex = CanIf_Arc_ChannelDefaultConfIndex,\r
+};\r
+\r
-/* \r
-* Configuration of module CanIf (CanIf_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (CANIF_SW_MAJOR_VERSION != 1 && CANIF_SW_MINOR_VERSION != 1) \r
-#error "CanIf: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
\r
+
+#if !(((CANIF_SW_MAJOR_VERSION == 1) && (CANIF_SW_MINOR_VERSION == 1)) )
+#error "CanIf: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef CANIF_CFG_H_\r
#define CANIF_CFG_H_\r
CANIF_CHANNEL_CNT\r
} CanIf_Arc_ChannelIdType;\r
\r
+#define CANIF_CONTROLLER_ID_CAN0 CANIF_CHANNEL_0\r
+\r
typedef enum {\r
CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
- CANIF_SOFTFILTER_TYPE_MASK, // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+ CANIF_SOFTFILTER_TYPE_MASK // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
} CanIf_SoftwareFilterTypeType;\r
\r
typedef enum {\r
CANIF_USER_TYPE_CAN_NM,\r
CANIF_USER_TYPE_CAN_TP,\r
CANIF_USER_TYPE_CAN_PDUR,\r
- CANIF_USER_TYPE_CAN_SPECIAL,\r
+ CANIF_USER_TYPE_CAN_SPECIAL\r
} CanIf_UserTypeType;\r
\r
\r
#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
\r
-//-------------------------------------------------------------------\r
-\r
-typedef struct {\r
- void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
- void (*RxIndication)(void *); //(const Can_PduType *);\r
- void (*ControllerBusOff)(uint8);\r
- void (*ControllerWakeup)(uint8);\r
- void (*Arc_Error)(uint8,uint32);\r
-} CanIf_CallbackType;\r
-\r
-\r
-\r
//-------------------------------------------------------------------\r
/*\r
* CanIfHrhRangeConfig container\r
typedef enum {\r
CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- CANIF_WAKEUP_SUPPORT_TRANSCEIVER,\r
+ CANIF_WAKEUP_SUPPORT_TRANSCEIVER\r
} CanIf_WakeupSupportType;\r
\r
\r
// CanIf-specific id of the controller\r
CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
\r
- const char CanIfDriverNameRef[8]; // Not used\r
+ const uint8 CanIfDriverNameRef[8]; // Not used\r
\r
const Can_ControllerConfigType *CanIfInitControllerRef;\r
} CanIf_ControllerConfigType;\r
\r
// ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers\r
const CanControllerIdType *Arc_ChannelToControllerMap;\r
+ \r
+ const uint8 *Arc_ChannelDefaultConfIndex;\r
} CanIf_ConfigType;\r
\r
\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+
+#if !(((CAN_SW_MAJOR_VERSION == 1) && (CAN_SW_MINOR_VERSION == 0)) )
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+ \r
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF // Not supported\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+typedef enum {\r
+ CAN_CTRL_0 = 0,\r
+ CAN_CTRL_1 = 1,\r
+ CAN_CTRL_2 = 2,\r
+ CAN_CTRL_3 = 3,\r
+ CAN_CTRL_4 = 4,\r
+ CAN_CONTROLLER_CNT = 5\r
+}CanControllerIdType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD\r
+} Can_IdTypeType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ TxBox,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ RxBox,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ uint8 CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+typedef struct\r
+{\r
+ uint8 idmr[8]; // Identifier Mask Register, 1 = ignore corresponding acceptance code register bit\r
+ uint8 idar[8]; // Identifier Acceptance Register\r
+ Can_Arc_IDAMType idam;\r
+} Can_FilterMaskType;\r
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask; \r
+ \r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING\r
+} Can_Arc_ProcessType;\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Lcfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:48 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_CAN0_Mask_1 = {\r
+ {0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF},\r
+ {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0},\r
+ CAN_ARC_IDAM_2_32BIT\r
+};\r
+\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_CAN0[] = {\r
+ {\r
+ .CanObjectId = RxBox,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_CAN0_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = TxBox,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_CAN0_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_0,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_CAN0[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
-/* \r
-* Configuration of module Com (Com_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (COM_SW_MAJOR_VERSION != 1) \r
-#error "Com: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module Com (Com_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
\r
-#ifndef COM_CFG_H_\r
-#define COM_CFG_H_\r
+#ifndef COM_CFG_H\r
+#define COM_CFG_H\r
\r
#define COM_MODULE_ID 20\r
#define COM_INSTANCE_ID 1\r
\r
-#define COM_DEV_ERROR_DETECT\r
+//#define COM_DEV_ERROR_DETECT\r
\r
#define COM_N_IPDUS 1\r
#define COM_N_SIGNALS 1\r
#define COM_INVALID_PDU_ID 104\r
#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
\r
-\r
-#define COM_MAX_NR_IPDU 999999999\r
-\r
#define COM_E_TOO_MANY_IPDU 106\r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
-/*\r
- * ComGeneral pre-compile time configuration parameters.\r
- */\r
#define ComConfigurationTimeBase 0.0\r
#define ComVersionInfoApi\r
\r
-#endif /*COM_CFG_H_*/\r
+#endif /*COM_CFG_H*/\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
+#include <stdlib.h>\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Signal init values.\r
+ */\r
+const uint16 Com_SignalInitValue_SetLedLevelRx = 0;\r
+ \r
+\r
+/*\r
+ * Group signal definitions\r
+ */\r
+const ComGroupSignal_type ComGroupSignal[] = {\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/* SignalGroup GroupSignals lists. */\r
+\r
+/*\r
+ * Signal definitions\r
+ */\r
+const ComSignal_type ComSignal[] = {\r
+ {\r
+ .ComHandleId = SetLedLevelRx,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_SetLedLevelRx,\r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 16,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT16,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU group definitions\r
+ */\r
+const ComIPduGroup_type ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = RxGroup,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+/* IPdu signal lists. */\r
+const ComSignal_type * const ComIPduSignalRefs_LedCommandRx[] = {\r
+ &ComSignal[ SetLedLevelRx ], \r
+ NULL,\r
+};\r
+\r
+/*\r
+ * I-PDU definitions\r
+ */\r
+const ComIPdu_type ComIPdu[] = { \r
+ \r
+ { // LedCommandRx\r
+ .ArcIPduOutgoingId = PDUR_SOURCE_PDU_ID_LedCommandRx,\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = RxGroup,\r
+ \r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = NONE,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduSignalRef = ComIPduSignalRefs_LedCommandRx,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+const Com_ConfigType ComConfiguration = {\r
+ .ComConfigurationId = 1,\r
+ .ComIPdu = ComIPdu,\r
+ .ComIPduGroup = ComIPduGroup,\r
+ .ComSignal = ComSignal,\r
+ .ComGroupSignal = ComGroupSignal\r
+};\r
+\r
+/* IPdu buffers and signal group buffers */\r
+uint8 ComArcIPduBuffer_LedCommandRx[8];\r
+ \r
+\r
+Com_Arc_IPdu_type Com_Arc_IPdu[] = {\r
+ { // LedCommandRx\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ },\r
+ .ComIPduDataPtr = ComArcIPduBuffer_LedCommandRx,\r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+};\r
+\r
+Com_Arc_Signal_type Com_Arc_Signal[] = {\r
+ { // SetLedLevelRx\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComTimeoutFactor = 0,\r
+ .ComIPduHandleId = 0,\r
+ .ComSignalUpdated = 0,\r
+ .ComIPduDataPtr = NULL,\r
+ \r
+ .Com_Arc_ShadowBuffer = NULL\r
+ \r
+ },\r
+ \r
+};\r
+\r
+Com_Arc_GroupSignal_type Com_Arc_GroupSignal[COM_N_GROUP_SIGNALS];\r
+\r
+uint8 outgoingSduPtr[8];\r
+\r
+Com_Arc_Config_type Com_Arc_Config = {\r
+ .ComIPdu = Com_Arc_IPdu,\r
+ .ComSignal = Com_Arc_Signal,\r
+ .ComGroupSignal = Com_Arc_GroupSignal,\r
+ .OutgoingPdu = {\r
+ .SduDataPtr = outgoingSduPtr,\r
+ .SduLength = 0\r
+ }\r
+};\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
+#ifndef COM_PBCFG_H\r
+#define COM_PBCFG_H\r
+\r
+#include "Com_Types.h"\r
+\r
+extern const Com_ConfigType ComConfiguration;\r
+\r
+// COM Polite Defines.\r
+#define COM_PDU_ID_LedCommandRx 0\r
+\r
+\r
+\r
+// PDU group definitions\r
+#define RxGroup 0\r
+\r
+\r
+// Signal definitions\r
+#define SetLedLevelRx 0\r
+\r
+\r
+\r
+\r
+#endif /* COM_PBCFG_H */\r
--- /dev/null
+\r
+MOD_USE += CANIF COM PDUR PORT PWM CAN \r
+\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_ComAlarm, ALARM_AUTOSTART_ABSOLUTE, 5, 20, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_ComAlarm,\r
+ "ComAlarm",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_ComAlarm),\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_ComTask,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(ComTask,512);\r
+DECLARE_STACK(StartupTask,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ ComTask,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ StartupTask,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_ComAlarm 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_ComTask 1\r
+#define TASK_ID_StartupTask 2\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void ComTask( void );\r
+void StartupTask( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 3\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_OFF\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
-/* \r
-* Configuration of module PduR (PduR_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (PDUR_SW_MAJOR_VERSION != 1) \r
-#error "PduR: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module PduR (PduR_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
\r
\r
#ifndef PDUR_CFG_H_\r
-/* \r
-* Configuration of module PduR (PduR_PbCfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:34 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
\r
\r
#include "PduR.h"\r
-/* \r
-* Configuration of module PduR (PduR_PbCfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (PDUR_SW_MAJOR_VERSION != 1) \r
-#error "PduR: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
\r
#if defined(USE_DCM)\r
#include "Dcm.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+ \r
+\r
+\r
+#include "Port.h"\r
+\r
+#define PORT_UNDEFINED 0x00\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .corePullUpRegister = 0x90,\r
+ .coreReducedDriveRegister = 0x00,\r
+ .modeRoutingRegister = 0x00,\r
+\r
+ #if ( PORTA_CONFIGURABLE == STD_ON )\r
+ .portADirection = PORT_UNDEFINED,\r
+ .portAOutValue = PORT_UNDEFINED,\r
+ .portAMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTB_CONFIGURABLE == STD_ON )\r
+ .portBDirection = 0xFF,\r
+ .portBOutValue = PORT_UNDEFINED,\r
+ .portBMask = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTE_CONFIGURABLE == STD_ON )\r
+ .portEDirection = PORT_UNDEFINED,\r
+ .portEOutValue = PORT_UNDEFINED,\r
+ .portEMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTK_CONFIGURABLE == STD_ON )\r
+ .portKDirection = PORT_UNDEFINED,\r
+ .portKOutValue = PORT_UNDEFINED,\r
+ .portKMask = PORT_UNDEFINED,\r
+ #endif\r
+\r
+ #if ( PORTH_CONFIGURABLE == STD_ON )\r
+ .portHDirection = 0x0,\r
+ .portHOutValue = 0x0,\r
+ .portHMask = 0x0,\r
+ .portHPullEnableRegister = 0xFF,\r
+ .portHPullPolarityRegsiter = 0x0,\r
+ .portHReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ .portJDirection = 0x80,\r
+ .portJOutValue = 0xC0,\r
+ .portJMask = 0x40,\r
+ .portJPullEnableRegister = 0x0,\r
+ .portJPullPolarityRegsiter 0x0,\r
+ .portJReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTM_CONFIGURABLE == STD_ON )\r
+ .portMDirection = 0x0,\r
+ .portMOutValue = 0xC3,\r
+ .portMMask = 0x0,\r
+ .portMPullEnableRegister = 0x0,\r
+ .portMPullPolarityRegsiter = 0x0,\r
+ .portMWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portMReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTP_CONFIGURABLE == STD_ON )\r
+ .portPDirection = 0x3,\r
+ .portPOutValue = 0x0,\r
+ .portPMask = 0x0,\r
+ .portPPullEnableRegister = 0x0,\r
+ .portPPullPolarityRegsiter = 0x0,\r
+ .portPReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTS_CONFIGURABLE == STD_ON )\r
+ .portSDirection = 0x0,\r
+ .portSOutValue = 0xF,\r
+ .portSMask = 0x0,\r
+ .portSPullEnableRegister = 0x5,\r
+ .portSPullPolarityRegsiter = 0x0,\r
+ .portSWiredModeRegsiter = PORT_UNDEFINED,\r
+ .portSReducedDriveRegister = 0x0,\r
+ #endif\r
+\r
+ #if ( PORTT_CONFIGURABLE == STD_ON )\r
+ .portTDirection = 0x4,\r
+ .portTOutValue = 0x3,\r
+ .portTMask = 0x0,\r
+ .portTPullEnableRegister = 0x0,\r
+ .portTPullPolarityRegsiter = 0x0,\r
+ .portTReducedDriveRegister = 0x0,\r
+ #endif\r
+};\r
+\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+\r
+/** Parameter to enable/disable configuration on a port */\r
+#define PORTA_CONFIGURABLE STD_OFF\r
+#define PORTB_CONFIGURABLE STD_ON\r
+#define PORTE_CONFIGURABLE STD_OFF\r
+#define PORTK_CONFIGURABLE STD_OFF\r
+#define PORTH_CONFIGURABLE STD_ON\r
+#define PORTJ_CONFIGURABLE STD_ON\r
+#define PORTM_CONFIGURABLE STD_ON\r
+#define PORTP_CONFIGURABLE STD_ON\r
+#define PORTS_CONFIGURABLE STD_ON\r
+#define PORTT_CONFIGURABLE STD_ON\r
+\r
+#define PORT_A_BASE 0x0100\r
+#define PORT_B_BASE 0x0200\r
+#define PORT_E_BASE 0x0300\r
+#define PORT_K_BASE 0x0400\r
+#define PORT_H_BASE 0x0500\r
+#define PORT_J_BASE 0x0600\r
+#define PORT_M_BASE 0x0700\r
+#define PORT_P_BASE 0x0800\r
+#define PORT_S_BASE 0x0900\r
+#define PORT_T_BASE 0x0A00\r
+#define PORT_BITMASK 0x00FF\r
+#define PORT_BASEMASK 0xFF00;\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum\r
+{\r
+ PORT_PA0 = PORT_A_BASE,\r
+ PORT_PA1,\r
+ PORT_PA2,\r
+ PORT_PA3,\r
+ PORT_PA4,\r
+ PORT_PA5,\r
+ PORT_PA6,\r
+ PORT_PA7,\r
+ PORT_PB0 = PORT_B_BASE,\r
+ PORT_PB1,\r
+ PORT_PB2,\r
+ PORT_PB3,\r
+ PORT_PB4,\r
+ PORT_PB5,\r
+ PORT_PB6,\r
+ PORT_PB7,\r
+ PORT_PE0 = PORT_E_BASE,\r
+ PORT_PE1,\r
+ PORT_PE2,\r
+ PORT_PE3,\r
+ PORT_PE4,\r
+ PORT_PE5,\r
+ PORT_PE6,\r
+ PORT_PE7,\r
+ PORT_PH0 = PORT_H_BASE,\r
+ PORT_PH1,\r
+ PORT_PH2,\r
+ PORT_PH3,\r
+ PORT_PH4,\r
+ PORT_PH5,\r
+ PORT_PH6,\r
+ PORT_PH7,\r
+ PORT_PJ0 = PORT_J_BASE,\r
+ PORT_PJ1,\r
+ PORT_PJ2,\r
+ PORT_PJ3,\r
+ PORT_PJ4,\r
+ PORT_PJ5,\r
+ PORT_PJ6,\r
+ PORT_PJ7,\r
+ PORT_PK0 = PORT_K_BASE,\r
+ PORT_PK1,\r
+ PORT_PK2,\r
+ PORT_PK3,\r
+ PORT_PK4,\r
+ PORT_PK5,\r
+ PORT_PK6,\r
+ PORT_PK7,\r
+ PORT_PM0 = PORT_M_BASE,\r
+ PORT_PM1,\r
+ PORT_PM2,\r
+ PORT_PM3,\r
+ PORT_PM4,\r
+ PORT_PM5,\r
+ PORT_PM6,\r
+ PORT_PM7,\r
+ PORT_PP0 = PORT_P_BASE,\r
+ PORT_PP1,\r
+ PORT_PP2,\r
+ PORT_PP3,\r
+ PORT_PP4,\r
+ PORT_PP5,\r
+ PORT_PP6,\r
+ PORT_PP7,\r
+ PORT_PS0 = PORT_S_BASE,\r
+ PORT_PS1,\r
+ PORT_PS2,\r
+ PORT_PS3,\r
+ PORT_PS4,\r
+ PORT_PS5,\r
+ PORT_PS6,\r
+ PORT_PS7,\r
+ PORT_PT0 = PORT_T_BASE,\r
+ PORT_PT1,\r
+ PORT_PT2,\r
+ PORT_PT3,\r
+ PORT_PT4,\r
+ PORT_PT5,\r
+ PORT_PT6,\r
+ PORT_PT7,\r
+} Port_PinType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct\r
+{\r
+ const uint8_t corePullUpRegister; // PUCR\r
+ const uint8_t coreReducedDriveRegister; // RDRIV\r
+ const uint8_t modeRoutingRegister; // MODRR\r
+\r
+ /**\r
+ * Every port has:\r
+ * a direction (input or output)\r
+ * a default out value\r
+ * a mask that is 0 if the direction is allowed to change during runtime\r
+ *\r
+ * Some ports have:\r
+ * a reduced drive conf (power saving)\r
+ * a pull enable conf (enable pull-up/pull-down\r
+ * a pull direction conf (pull-up or pull-down)\r
+ * a wired mode (enable open drain outputs)\r
+ */\r
+#if ( PORTA_CONFIGURABLE == STD_ON )\r
+ const uint8_t portADirection;\r
+ const uint8_t portAOutValue;\r
+ const uint8_t portAMask;\r
+#endif\r
+\r
+#if ( PORTB_CONFIGURABLE == STD_ON )\r
+ const uint8_t portBDirection;\r
+ const uint8_t portBOutValue;\r
+ const uint8_t portBMask;\r
+#endif\r
+\r
+#if ( PORTE_CONFIGURABLE == STD_ON )\r
+ const uint8_t portEDirection;\r
+ const uint8_t portEOutValue;\r
+ const uint8_t portEMask;\r
+#endif\r
+\r
+#if ( PORTK_CONFIGURABLE == STD_ON )\r
+ const uint8_t portKDirection;\r
+ const uint8_t portKOutValue;\r
+ const uint8_t portKMask;\r
+#endif\r
+\r
+#if ( PORTH_CONFIGURABLE == STD_ON )\r
+ const uint8_t portHDirection;\r
+ const uint8_t portHOutValue;\r
+ const uint8_t portHMask;\r
+ const uint8_t portHPullEnableRegister;\r
+ const uint8_t portHPullPolarityRegsiter;\r
+ const uint8_t portHReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTJ_CONFIGURABLE == STD_ON )\r
+ const uint8_t portJDirection;\r
+ const uint8_t portJOutValue;\r
+ const uint8_t portJMask;\r
+ const uint8_t portJPullEnableRegister;\r
+ const uint8_t portJPullPolarityRegsiter;\r
+ const uint8_t portJReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTM_CONFIGURABLE == STD_ON )\r
+ const uint8_t portMDirection;\r
+ const uint8_t portMOutValue;\r
+ const uint8_t portMMask;\r
+ const uint8_t portMPullEnableRegister;\r
+ const uint8_t portMPullPolarityRegsiter;\r
+ const uint8_t portMWiredModeRegsiter;\r
+ const uint8_t portMReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTP_CONFIGURABLE == STD_ON )\r
+ const uint8_t portPDirection;\r
+ const uint8_t portPOutValue;\r
+ const uint8_t portPMask;\r
+ const uint8_t portPPullEnableRegister;\r
+ const uint8_t portPPullPolarityRegsiter;\r
+ const uint8_t portPReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTS_CONFIGURABLE == STD_ON )\r
+ const uint8_t portSDirection;\r
+ const uint8_t portSOutValue;\r
+ const uint8_t portSMask;\r
+ const uint8_t portSPullEnableRegister;\r
+ const uint8_t portSPullPolarityRegsiter;\r
+ const uint8_t portSWiredModeRegsiter;\r
+ const uint8_t portSReducedDriveRegister;\r
+#endif\r
+\r
+#if ( PORTT_CONFIGURABLE == STD_ON )\r
+ const uint8_t portTDirection;\r
+ const uint8_t portTOutValue;\r
+ const uint8_t portTMask;\r
+ const uint8_t portTPullEnableRegister;\r
+ const uint8_t portTPullPolarityRegsiter;\r
+ const uint8_t portTReducedDriveRegister;\r
+#endif\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_SDA PORT_PJ6 \r
+#define PORT_PIN_NAME_SCL PORT_PJ7 \r
+#define PORT_PIN_NAME_TXD PORT_PM1 \r
+#define PORT_PIN_NAME_RXD PORT_PM0 \r
+#define PORT_PIN_NAME_PB0 PORT_PB0 \r
+#define PORT_PIN_NAME_PB1 PORT_PB1 \r
+#define PORT_PIN_NAME_PB2 PORT_PB2 \r
+#define PORT_PIN_NAME_PB3 PORT_PB3 \r
+#define PORT_PIN_NAME_PB4 PORT_PB4 \r
+#define PORT_PIN_NAME_PB5 PORT_PB5 \r
+#define PORT_PIN_NAME_PB6 PORT_PB6 \r
+#define PORT_PIN_NAME_PB7 PORT_PB7 \r
+#define PORT_PIN_NAME_PH0 PORT_PH0 \r
+#define PORT_PIN_NAME_PH1 PORT_PH1 \r
+#define PORT_PIN_NAME_PH2 PORT_PH2 \r
+#define PORT_PIN_NAME_PH3 PORT_PH3 \r
+#define PORT_PIN_NAME_PH4 PORT_PH4 \r
+#define PORT_PIN_NAME_PH5 PORT_PH5 \r
+#define PORT_PIN_NAME_PH6 PORT_PH6 \r
+#define PORT_PIN_NAME_PH7 PORT_PH7 \r
+#define PORT_PIN_NAME_PT0 PORT_PT0 \r
+#define PORT_PIN_NAME_PT1 PORT_PT1 \r
+#define PORT_PIN_NAME_BEEPER PORT_PT2 \r
+#define PORT_PIN_NAME_PP0 PORT_PP0 \r
+#define PORT_PIN_NAME_PP1 PORT_PP1 \r
+#define PORT_PIN_NAME_RXD0 PORT_PS0 \r
+#define PORT_PIN_NAME_TXD0 PORT_PS1 \r
+#define PORT_PIN_NAME_RXD1 PORT_PS2 \r
+#define PORT_PIN_NAME_TXD1 PORT_PS3 \r
+#define PORT_PIN_NAME_PM6 PORT_PM6 \r
+#define PORT_PIN_NAME_PM7 PORT_PM7 \r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+\r
+#include "Pwm.h"\r
+\r
+const Pwm_ConfigType PwmConfig =\r
+{\r
+ .channels = { \r
+ {\r
+ .channel = PWM_CHANNEL_1,\r
+ DUTY_AND_PERIOD(24576,188.0),\r
+ .centerAlign = STD_OFF,\r
+ .polarity = POLARITY_NORMAL,\r
+ .scaledClockEnable = STD_ON,\r
+ .idleState = PWM_LOW,\r
+ .class = PWM_VARIABLE_PERIOD\r
+ },\r
+ },\r
+ .busPrescalerA = PRESCALER_128,\r
+ .busPrescalerB = PRESCALER_2,\r
+ .prescalerA = 1,\r
+ .prescalerB = 1,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): HCS12\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:38:47 CET 2011\r
+ */\r
+\r
+
+#if !(((PWM_SW_MAJOR_VERSION == 1) && (PWM_SW_MINOR_VERSION == 0)) )
+#error "Pwm: Configuration file version differs from BSW version."
+#endif
+
+ \r
+\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+#define PWM_DEV_ERROR_DETECT STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_OFF\r
+#define PWM_FREEZE_ENABLE STD_OFF\r
+\r
+// Define what API functions to enable.\r
+#define PWM_GET_OUTPUT_STATE STD_OFF\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+#define PWM_DEINIT STD_OFF\r
+#define PWM_DUTYCYCLE STD_ON\r
+#define PWM_SET_OUTPUT_TO_IDLE STD_OFF\r
+#define PWM_VERSION_INFO_API STD_OFF\r
+\r
+\r
+\r
+/**\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/**\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == channel id.\r
+ */\r
+typedef uint8 Pwm_ChannelType;\r
+\r
+/**\r
+ * PWM070: All time units used within the API services of the PWM module shall\r
+ * be of the unit ticks.\r
+ */\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_1 = 0 ,\r
+ PWM_NUMBER_OF_CHANNELS = 1\r
+} Pwm_NamedChannelsType;\r
+\r
+/* 1 =PWMchannel output is high at the beginning of the period, then goes low when the duty count\r
+is reached. */\r
+#define POLARITY_NORMAL 1\r
+#define POLARITY_INVERSED 0\r
+\r
+/**\r
+ * Since the AUTOSAR PWM specification uses a different unit for the duty,\r
+ * the following macro can be used to convert between that format and the\r
+ * driver format.\r
+ */\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (uint8)((uint32)((uint32)_duty*(uint32)_period)>>15), .period = _period\r
+\r
+\r
+typedef struct {\r
+ /** Number of duty ticks */\r
+ uint8_t duty;\r
+ /** Length of period, in ticks */\r
+ uint8_t period;\r
+ /** Center or left align */\r
+ uint8_t centerAlign:1;\r
+ /** Polarity of the channel */\r
+ uint8_t polarity:1;\r
+ /** Scaled clock enabled */\r
+ uint8_t scaledClockEnable:1;\r
+ /** idle state */\r
+ uint8_t idleState:1;\r
+\r
+ uint8_t reserved:4;\r
+\r
+ Pwm_ChannelClassType class;\r
+\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+typedef enum{\r
+ PRESCALER_1 = 0,\r
+ PRESCALER_2 = 1,\r
+ PRESCALER_4 = 2,\r
+ PRESCALER_8 = 3,\r
+ PRESCALER_16 = 4,\r
+ PRESCALER_32 = 5,\r
+ PRESCALER_64 = 6,\r
+ PRESCALER_128 = 7,\r
+}Pwm_PrescalerType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType channels[PWM_NUMBER_OF_CHANNELS];\r
+ Pwm_PrescalerType busPrescalerA;\r
+ Pwm_PrescalerType busPrescalerB;\r
+ uint8_t prescalerA;\r
+ uint8_t prescalerB;\r
+} Pwm_ConfigType;\r
+\r
+#endif\r
+\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
-/* \r
-* Configuration of module CanIf (CanIf_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:29 CET 2011\r
+ */\r
\r
\r
\r
#if defined(USE_PDUR)\r
#include "PduR.h"\r
#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm_Cbk.h"\r
+#endif\r
#include <stdlib.h>\r
\r
\r
FLEXCAN_A, // CHANNEL_0\r
};\r
\r
+const uint8 CanIf_Arc_ChannelDefaultConfIndex[CANIF_CHANNEL_CNT] = {\r
+ CANIF_CHANNEL_0_CONFIG_0,\r
+};\r
+\r
// Container that gets slamed into CanIf_InitController()\r
// Inits ALL controllers\r
// Multiplicity 1..*\r
{\r
.CanIfHrhType = CAN_ARC_HANDLE_TYPE_BASIC,\r
.CanIfSoftwareFilterHrh = TRUE,\r
- .CanIfCanControllerHrhIdRef = FLEXCAN_A,\r
+ .CanIfCanControllerHrhIdRef = CANIF_CHANNEL_0,\r
.CanIfHrhIdSymRef = RxMailboxes,\r
.CanIf_Arc_EOL = 1,\r
},\r
};\r
\r
\r
-const CanIf_InitHohConfigType CanIfHohConfigData[] = {\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] = { \r
\r
{\r
.CanConfigSet = &CanConfigSetData,\r
.InitConfig = &CanIfInitConfig,\r
.TransceiverConfig = NULL, // Not used\r
.Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap, \r
+ .Arc_ChannelDefaultConfIndex = CanIf_Arc_ChannelDefaultConfIndex,\r
};\r
\r
--- /dev/null
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:29 CET 2011\r
+ */\r
+\r
+
+#if !(((CANIF_SW_MAJOR_VERSION == 1) && (CANIF_SW_MINOR_VERSION == 1)) )
+#error "CanIf: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef CANIF_CFG_H_\r
+#define CANIF_CFG_H_\r
+\r
+#include "Can.h"\r
+\r
+#define CANIF_PDU_ID_LedCommandRx 0\r
+\r
+\r
+// Identifiers for the elements in CanIfControllerConfig[]\r
+// This is the ConfigurationIndex in CanIf_InitController()\r
+typedef enum {\r
+ CANIF_CHANNEL_0_CONFIG_0,\r
+ CANIF_CHANNEL_CONFIGURATION_CNT\r
+} CanIf_Arc_ConfigurationIndexType;\r
+\r
+typedef enum {\r
+ CANIF_CHANNEL_0,\r
+ CANIF_CHANNEL_CNT\r
+} CanIf_Arc_ChannelIdType;\r
+\r
+#define CANIF_CONTROLLER_ID_Can_A CANIF_CHANNEL_0\r
+\r
+typedef enum {\r
+ CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_MASK // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+} CanIf_SoftwareFilterTypeType;\r
+\r
+typedef enum {\r
+ CANIF_USER_TYPE_CAN_NM,\r
+ CANIF_USER_TYPE_CAN_TP,\r
+ CANIF_USER_TYPE_CAN_PDUR,\r
+ CANIF_USER_TYPE_CAN_SPECIAL\r
+} CanIf_UserTypeType;\r
+\r
+\r
+typedef void (*CanIf_FuncTypeCanSpecial)(PduIdType, const uint8 *, uint8, Can_IdType);\r
+\r
+typedef enum {\r
+ CANIF_PDU_TYPE_STATIC = 0,\r
+ CANIF_PDU_TYPE_DYNAMIC // Not supported\r
+} CanIf_PduTypeType;\r
+\r
+typedef enum {\r
+ CANIF_CAN_ID_TYPE_29 = 0,\r
+ CANIF_CAN_ID_TYPE_11\r
+} CanIf_CanIdTypeType;\r
+\r
+/*\r
+ * Public container\r
+ */\r
+#define CANIF_VERSION_INFO_API STD_ON\r
+#define CANIF_DEV_ERROR_DETECT STD_ON\r
+#define CANIF_DLC_CHECK STD_ON\r
+#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF // Not supported\r
+#define CANIF_READRXPDU_DATA_API STD_OFF // Not supported\r
+#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_SETDYNAMICTXID_API STD_OFF // Not supported\r
+#define CANIF_WAKEUP_EVENT_API STD_OFF // Not supported\r
+#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
+#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfHrhRangeConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Lower CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduLowerCanId;\r
+\r
+ // Upper CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduUpperCanId;\r
+} CanIf_HrhRangeConfigType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHrhConfig container\r
+ */\r
+typedef struct {\r
+ // Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
+ // configured, software filtering is enabled.\r
+ Can_Arc_HohType CanIfHrhType;\r
+\r
+ // Selects the hardware receive objects by using the HRH range/list from\r
+ // CAN Driver configuration to define, for which HRH a software filtering has\r
+ // to be performed at during receive processing. True: Software filtering is\r
+ // enabled False: Software filtering is disabled\r
+ boolean CanIfSoftwareFilterHrh;\r
+\r
+ // Reference to controller Id to which the HRH belongs to. A controller can\r
+ // contain one or more HRHs.\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerHrhIdRef;\r
+\r
+ // The parameter refers to a particular HRH object in the CAN Driver Module\r
+ // configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_Arc_HRHType CanIfHrhIdSymRef ;\r
+\r
+ // Defines the parameters required for configuraing multiple\r
+ // CANID ranges for a given same HRH.\r
+ const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIf_Arc_EOL;\r
+} CanIf_HrhConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHthConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
+ Can_Arc_HohType CanIfHthType;\r
+\r
+ // Reference to controller Id to which the HTH belongs to. A controller\r
+ // can contain one or more HTHs\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerIdRef;\r
+\r
+ // The parameter refers to a particular HTH object in the CAN Driver Module\r
+ // configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_Arc_HTHType CanIfHthIdSymRef ;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIf_Arc_EOL;\r
+} CanIf_HthConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHohConfig container\r
+ */\r
+typedef struct {\r
+ // Selects the CAN interface specific configuration setup. This type of external\r
+ // data structure shall contain the post build initialization data for the\r
+ // CAN interface for all underlying CAN Drivers.\r
+ const Can_ConfigSetType *CanConfigSet;\r
+\r
+ // This container contains contiguration parameters for each hardware receive object.\r
+ const CanIf_HrhConfigType *CanIfHrhConfig;\r
+\r
+ // This container contains parameters releated to each HTH\r
+ const CanIf_HthConfigType *CanIfHthConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIf_Arc_EOL;\r
+} CanIf_InitHohConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTxPduConfig container\r
+ */\r
+\r
+// This container contains the configuration (parameters) of each transmit\r
+// CAN L-PDU. The SHORT-NAME of "CanIfTxPduConfig" container\r
+// represents the symolic name of Transmit L-PDU.\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for transmit CAN L-PDU. The\r
+ // CanIfCanTxPduId is configurable at pre-compile and post-built time.\r
+ // Range: 0..max. number of CantTxPduIds PduIdType CanTxPduId;\r
+ PduIdType CanIfTxPduId;\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanTxPduIdCanId;\r
+\r
+ // Data length code (in bytes) of transmit CAN L-PDUs used by the CAN\r
+ // Driver for CAN L-PDU transmission. The data area size of a CAN L-Pdu\r
+ // can have a range from 0 to 8 bytes.\r
+ uint8 CanIfCanTxPduIdDlc;\r
+\r
+ // Defines the type of each transmit CAN L-PDU.\r
+ // DYNAMIC CAN ID is defined at runtime.\r
+ // STATIC CAN ID is defined at compile-time.\r
+ CanIf_PduTypeType CanIfCanTxPduType;\r
+\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ // Enables and disables transmit confirmation for each transmit CAN L-PDU\r
+ // for reading its notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadTxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfTxPduIdCanIdType;\r
+\r
+ // Name of target confirmation services to target upper layers (PduR, CanNm\r
+ // and CanTp. If parameter is not configured then no call-out function is\r
+ // provided by the upper layer for this Tx L-PDU.\r
+ void (*CanIfUserTxConfirmation)(PduIdType); /* CANIF 109 */\r
+\r
+ // Handle, that defines the hardware object or the pool of hardware objects\r
+ // configured for transmission. The parameter refers HTH Id, to which the L-\r
+ // PDU belongs to.\r
+ const CanIf_HthConfigType *CanIfCanTxPduHthRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack. ..\r
+ void *PduIdRef;\r
+} CanIf_TxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfRxPduConfig container\r
+ */\r
+\r
+\r
+// This container contains the configuration (parameters) of each receive\r
+// CAN L-PDU. The SHORT-NAME of "CanIfRxPduConfig" container itself\r
+// represents the symolic name of Receive L-PDU.\r
+\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for receive CAN L-PDU. The\r
+ // CanRxPduId is configurable at pre-compile and post-built time. It shall fulfill\r
+ // ANSI/AUTOSAR definitions for constant defines. Range: 0..max. number\r
+ // of defined CanRxPduIds\r
+ PduIdType CanIfCanRxPduId;\r
+\r
+ // CAN Identifier of Receive CAN L-PDUs used by the CAN Interface. Exa:\r
+ // Software Filtering. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanRxPduCanId;\r
+\r
+ // Data Length code of received CAN L-PDUs used by the CAN Interface.\r
+ // Exa: DLC check. The data area size of a CAN L-PDU can have a range\r
+ // from 0 to 8 bytes. uint8 CanIfCanRxPduDlc;\r
+ uint8 CanIfCanRxPduDlc;\r
+\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ // Enables and disables the Rx buffering for reading of received L-PDU data.\r
+ // True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduData;\r
+#endif\r
+\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ // CanIfReadRxPduNotifyStatus {CANIF_READRXPDU_NOTIFY_STATUS}\r
+ // Enables and disables receive indication for each receive CAN L-PDU for\r
+ // reading its' notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of receive CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfRxPduIdCanIdType;\r
+\r
+ // This parameter defines the type of the receive indication call-outs called to\r
+ // the corresponding upper layer the used TargetRxPduId belongs to.\r
+ CanIf_UserTypeType CanIfRxUserType;\r
+\r
+ // Name of target indication services to target upper layers (PduRouter,\r
+ // CanNm, CanTp and ComplexDeviceDrivers). If parameter is 0 no call-out\r
+ // function is configured.\r
+ void *CanIfUserRxIndication;\r
+\r
+ // The HRH to which Rx L-PDU belongs to, is referred through this\r
+ // parameter.\r
+ const CanIf_HrhConfigType *CanIfCanRxPduHrhRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack.\r
+ void *PduIdRef;\r
+\r
+ // Defines the type of software filtering that should be used\r
+ // for this receive object.\r
+ CanIf_SoftwareFilterTypeType CanIfSoftwareFilterType;\r
+\r
+ // Acceptance filters, 1 - care, 0 - don't care.\r
+ // Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
+ // ArcCore exension\r
+ uint32 CanIfCanRxPduCanIdMask;\r
+\r
+} CanIf_RxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * CanIfControllerConfig container\r
+ */\r
+\r
+typedef enum {\r
+ CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
+ CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ CANIF_WAKEUP_SUPPORT_TRANSCEIVER\r
+} CanIf_WakeupSupportType;\r
+\r
+\r
+// This is the type supplied to CanIf_InitController()\r
+typedef struct {\r
+ CanIf_WakeupSupportType WakeupSupport; // Not used\r
+\r
+ // CanIf-specific id of the controller\r
+ CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
+\r
+ const uint8 CanIfDriverNameRef[8]; // Not used\r
+\r
+ const Can_ControllerConfigType *CanIfInitControllerRef;\r
+} CanIf_ControllerConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTransceiverDrvConfig container\r
+ */\r
+\r
+typedef struct {\r
+ boolean TrcvWakeupNotification;\r
+ uint8 TrcvIdRef;\r
+} CanIf_TransceiverDrvConfigType;\r
+\r
+\r
+typedef struct {\r
+ uint32 todo;\r
+} CanIf_TransceiverConfigType;\r
+\r
+// Callout functions with respect to the upper layers. This callout functions\r
+// defined in this container are common to all configured underlying CAN\r
+// Drivers / CAN Transceiver Drivers.\r
+typedef struct {\r
+ // Name of target BusOff notification services to target upper layers\r
+ // (PduRouter, CanNm, CanTp and ComplexDeviceDrivers).\r
+ // Multiplicity: 1\r
+ void (*CanIfBusOffNotification)(uint8 Controller);\r
+\r
+ // Name of target wakeup notification services to target upper layers\r
+ // e.g Ecu_StateManager. If parameter is 0\r
+ // no call-out function is configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeUpNotification)();\r
+\r
+ // Name of target wakeup validation notification services to target upper\r
+ // layers (ECU State Manager). If parameter is 0 no call-out function is\r
+ // configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeupValidNotification)();\r
+\r
+ // ArcCore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_Arc_ErrorType);\r
+\r
+} CanIf_DispatchConfigType;\r
+\r
+// This container contains the references to the configuration setup of each\r
+// underlying CAN driver.\r
+\r
+typedef struct {\r
+ // Selects the CAN Interface specific configuration setup. This type of the\r
+ // external data structure shall contain the post build initialization data for the\r
+ // CAN Interface for all underlying CAN Dirvers. constant to CanIf_ConfigType\r
+ uint32 CanIfConfigSet;\r
+\r
+ uint32 CanIfNumberOfCanRxPduIds;\r
+ uint32 CanIfNumberOfCanTXPduIds;\r
+ uint32 CanIfNumberOfDynamicCanTXPduIds;\r
+\r
+ //\r
+ // Containers\r
+ //\r
+\r
+ // This container contains the reference to the configuration\r
+ // setup of each underlying CAN driver.\r
+ // Multiplicity: 0..*\r
+ const CanIf_InitHohConfigType *CanIfHohConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // receive CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfRxPduConfig" container itself represents the symolic\r
+ // name of Receive L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_RxPduConfigType *CanIfRxPduConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // transmit CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfTxPduConfig" container represents the symolic name of\r
+ // Transmit L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_TxPduConfigType *CanIfTxPduConfigPtr;\r
+\r
+} CanIf_InitConfigType;\r
+\r
+\r
+typedef struct {\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN controllers by each underlying CAN driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_ControllerConfigType *ControllerConfig;\r
+\r
+ // Callout functions with respect to the upper layers. This callout\r
+ // functions defined in this container are common to all\r
+ // configured underlying CAN Drivers / CAN Transceiver Drivers\r
+ const CanIf_DispatchConfigType *DispatchConfig;\r
+\r
+ // This container contains the init parameters of the CAN\r
+ // Interface.\r
+ // Multiplicity: 1..*\r
+ const CanIf_InitConfigType *InitConfig;\r
+\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN transceivers by each underlying CAN\r
+ // Transceiver Driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;\r
+ \r
+ // ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers\r
+ const CanControllerIdType *Arc_ChannelToControllerMap;\r
+ \r
+ const uint8 *Arc_ChannelDefaultConfIndex;\r
+} CanIf_ConfigType;\r
+\r
+\r
+extern CanIf_ConfigType CanIf_Config;\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:29 CET 2011\r
+ */\r
+\r
+
+#if !(((CAN_SW_MAJOR_VERSION == 1) && (CAN_SW_MINOR_VERSION == 0)) )
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+ \r
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF // Not supported\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+typedef enum {\r
+ FLEXCAN_A = 0,\r
+ CAN_CTRL_A = 0,\r
+ FLEXCAN_B = 1,\r
+ CAN_CTRL_B = 1,\r
+ FLEXCAN_C = 2,\r
+ CAN_CTRL_C = 2,\r
+ FLEXCAN_D = 3,\r
+ CAN_CTRL_D = 3,\r
+ FLEXCAN_E = 4,\r
+ CAN_CTRL_E = 4,\r
+ FLEXCAN_F = 5,\r
+ CAN_CTRL_F = 5,\r
+ CAN_CONTROLLER_CNT = 6\r
+}CanControllerIdType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD\r
+} Can_IdTypeType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ RxMailboxes,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ uint8 CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+typedef uint32 Can_FilterMaskType;\r
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask; \r
+ \r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING\r
+} Can_Arc_ProcessType;\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
-/* \r
-* Configuration of module Can (Can_Lcfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Can (Can_Lcfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:29 CET 2011\r
+ */\r
\r
\r
\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef COM_CFG_H\r
+#define COM_CFG_H\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+//#define COM_DEV_ERROR_DETECT\r
+\r
+#define COM_N_IPDUS 1\r
+#define COM_N_SIGNALS 1\r
+#define COM_N_GROUP_SIGNALS 0\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
+\r
+#define ComConfigurationTimeBase 0.0\r
+#define ComVersionInfoApi\r
+\r
+#endif /*COM_CFG_H*/\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
+#include <stdlib.h>\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Signal init values.\r
+ */\r
+const uint16 Com_SignalInitValue_SetLedLevelRx = 0;\r
+ \r
+\r
+/*\r
+ * Group signal definitions\r
+ */\r
+const ComGroupSignal_type ComGroupSignal[] = {\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/* SignalGroup GroupSignals lists. */\r
+\r
+/*\r
+ * Signal definitions\r
+ */\r
+const ComSignal_type ComSignal[] = {\r
+ {\r
+ .ComHandleId = SetLedLevelRx,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_SetLedLevelRx,\r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 16,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT16,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU group definitions\r
+ */\r
+const ComIPduGroup_type ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = RxGroup,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+/* IPdu signal lists. */\r
+const ComSignal_type * const ComIPduSignalRefs_LedCommandRx[] = {\r
+ &ComSignal[ SetLedLevelRx ], \r
+ NULL,\r
+};\r
+\r
+/*\r
+ * I-PDU definitions\r
+ */\r
+const ComIPdu_type ComIPdu[] = { \r
+ \r
+ { // LedCommandRx\r
+ .ArcIPduOutgoingId = PDUR_SOURCE_PDU_ID_LedCommandRx,\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = RECEIVE,\r
+ .ComIPduGroupRef = RxGroup,\r
+ \r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = NONE,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduSignalRef = ComIPduSignalRefs_LedCommandRx,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+const Com_ConfigType ComConfiguration = {\r
+ .ComConfigurationId = 1,\r
+ .ComIPdu = ComIPdu,\r
+ .ComIPduGroup = ComIPduGroup,\r
+ .ComSignal = ComSignal,\r
+ .ComGroupSignal = ComGroupSignal\r
+};\r
+\r
+/* IPdu buffers and signal group buffers */\r
+uint8 ComArcIPduBuffer_LedCommandRx[8];\r
+ \r
+\r
+Com_Arc_IPdu_type Com_Arc_IPdu[] = {\r
+ { // LedCommandRx\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ },\r
+ .ComIPduDataPtr = ComArcIPduBuffer_LedCommandRx,\r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+};\r
+\r
+Com_Arc_Signal_type Com_Arc_Signal[] = {\r
+ { // SetLedLevelRx\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComTimeoutFactor = 0,\r
+ .ComIPduHandleId = 0,\r
+ .ComSignalUpdated = 0,\r
+ .ComIPduDataPtr = NULL,\r
+ \r
+ .Com_Arc_ShadowBuffer = NULL\r
+ \r
+ },\r
+ \r
+};\r
+\r
+Com_Arc_GroupSignal_type Com_Arc_GroupSignal[COM_N_GROUP_SIGNALS];\r
+\r
+uint8 outgoingSduPtr[8];\r
+\r
+Com_Arc_Config_type Com_Arc_Config = {\r
+ .ComIPdu = Com_Arc_IPdu,\r
+ .ComSignal = Com_Arc_Signal,\r
+ .ComGroupSignal = Com_Arc_GroupSignal,\r
+ .OutgoingPdu = {\r
+ .SduDataPtr = outgoingSduPtr,\r
+ .SduLength = 0\r
+ }\r
+};\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
+#ifndef COM_PBCFG_H\r
+#define COM_PBCFG_H\r
+\r
+#include "Com_Types.h"\r
+\r
+extern const Com_ConfigType ComConfiguration;\r
+\r
+// COM Polite Defines.\r
+#define COM_PDU_ID_LedCommandRx 0\r
+\r
+\r
+\r
+// PDU group definitions\r
+#define RxGroup 0\r
+\r
+\r
+// Signal definitions\r
+#define SetLedLevelRx 0\r
+\r
+\r
+\r
+\r
+#endif /* COM_PBCFG_H */\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 16:39:13 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 16:39:13 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
-/* \r
-* Configuration of module PduR (PduR_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (PDUR_SW_MAJOR_VERSION != 1) \r
-#error "PduR: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module PduR (PduR_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
\r
\r
#ifndef PDUR_CFG_H_\r
-/* \r
-* Configuration of module PduR (PduR_PbCfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
\r
\r
#include "PduR.h"\r
--- /dev/null
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
+\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+\r
+extern PduR_PBConfigType PduR_Config;\r
+\r
+// PduR Polite Defines.\r
+\r
+#define PDUR_SOURCE_PDU_ID_LedCommandRx CANIF_PDU_ID_LedCommandRx\r
+#define PDUR_DEST_PDU_ID_LedCommandRx COM_PDU_ID_LedCommandRx\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+ \r
+// File generated on Mon Jan 17 11:45:30 CET 2011\r
+// File generated by com.arccore.bswbuilder.modules.port.mpc5516\r
+\r
+#include "Port.h"\r
+#include "Port_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PORT_PCR_RESET, /* PCR 0 */\r
+ PORT_PCR_RESET, /* PCR 1 */\r
+ PORT_PCR_RESET, /* PCR 2 */\r
+ PORT_PCR_RESET, /* PCR 3 */\r
+ PORT_PCR_RESET, /* PCR 4 */\r
+ PORT_PCR_RESET, /* PCR 5 */\r
+ PORT_PCR_RESET, /* PCR 6 */\r
+ PORT_PCR_RESET, /* PCR 7 */\r
+ PORT_PCR_RESET, /* PCR 8 */\r
+ PORT_PCR_RESET, /* PCR 9 */\r
+ PORT_PCR_RESET, /* PCR 10 */\r
+ PORT_PCR_RESET, /* PCR 11 */\r
+ PORT_PCR_RESET, /* PCR 12 */\r
+ PORT_PCR_RESET, /* PCR 13 */\r
+ PORT_PCR_RESET, /* PCR 14 */\r
+ PORT_PCR_RESET, /* PCR 15 */\r
+ PORT_PCR_RESET, /* PCR 16 */\r
+ PORT_PCR_RESET, /* PCR 17 */\r
+ PORT_PCR_RESET, /* PCR 18 */\r
+ PORT_PCR_RESET, /* PCR 19 */\r
+ PORT_PCR_RESET, /* PCR 20 */\r
+ PORT_PCR_RESET, /* PCR 21 */\r
+ PORT_PCR_RESET, /* PCR 22 */\r
+ PORT_PCR_RESET, /* PCR 23 */\r
+ PORT_PCR_RESET, /* PCR 24 */\r
+ PORT_PCR_RESET, /* PCR 25 */\r
+ PORT_PCR_RESET, /* PCR 26 */\r
+ PORT_PCR_RESET, /* PCR 27 */\r
+ PORT_PCR_RESET, /* PCR 28 */\r
+ PORT_PCR_RESET, /* PCR 29 */\r
+ PORT_PCR_RESET, /* PCR 30 */\r
+ PORT_PCR_RESET, /* PCR 31 */\r
+ PORT_PCR_RESET, /* PCR 32 */\r
+ PORT_PCR_RESET, /* PCR 33 */\r
+ PORT_PCR_RESET, /* PCR 34 */\r
+ PORT_PCR_RESET, /* PCR 35 */\r
+ PORT_PCR_RESET, /* PCR 36 */\r
+ PORT_PCR_RESET, /* PCR 37 */\r
+ PORT_PCR_RESET, /* PCR 38 */\r
+ PORT_PCR_RESET, /* PCR 39 */\r
+ PORT_PCR_RESET, /* PCR 40 */\r
+ PORT_PCR_RESET, /* PCR 41 */\r
+ PORT_PCR_RESET, /* PCR 42 */\r
+ PORT_PCR_RESET, /* PCR 43 */\r
+ PORT_PCR_RESET, /* PCR 44 */\r
+ PORT_PCR_RESET, /* PCR 45 */\r
+ PORT_PCR_RESET, /* PCR 46 */\r
+ PORT_PCR_RESET, /* PCR 47 */\r
+ ( PORT_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 48 : PORT_PIN_MODE_CAN */\r
+ ( PORT_FUNC1 | PORT_IBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 49 : PORT_PIN_MODE_CAN */\r
+ PORT_PCR_RESET, /* PCR 50 */\r
+ PORT_PCR_RESET, /* PCR 51 */\r
+ PORT_PCR_RESET, /* PCR 52 */\r
+ ( PORT_FUNC2 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 53 : PORT_PIN_MODE_PWM */\r
+ PORT_PCR_RESET, /* PCR 54 */\r
+ PORT_PCR_RESET, /* PCR 55 */\r
+ PORT_PCR_RESET, /* PCR 56 */\r
+ PORT_PCR_RESET, /* PCR 57 */\r
+ PORT_PCR_RESET, /* PCR 58 */\r
+ PORT_PCR_RESET, /* PCR 59 */\r
+ PORT_PCR_RESET, /* PCR 60 */\r
+ PORT_PCR_RESET, /* PCR 61 */\r
+ PORT_PCR_RESET, /* PCR 62 */\r
+ PORT_PCR_RESET, /* PCR 63 */\r
+ PORT_PCR_RESET, /* PCR 64 */\r
+ PORT_PCR_RESET, /* PCR 65 */\r
+ PORT_PCR_RESET, /* PCR 66 */\r
+ PORT_PCR_RESET, /* PCR 67 */\r
+ PORT_PCR_RESET, /* PCR 68 */\r
+ PORT_PCR_RESET, /* PCR 69 */\r
+ PORT_PCR_RESET, /* PCR 70 */\r
+ PORT_PCR_RESET, /* PCR 71 */\r
+ PORT_PCR_RESET, /* PCR 72 */\r
+ PORT_PCR_RESET, /* PCR 73 */\r
+ PORT_PCR_RESET, /* PCR 74 */\r
+ PORT_PCR_RESET, /* PCR 75 */\r
+ PORT_PCR_RESET, /* PCR 76 */\r
+ PORT_PCR_RESET, /* PCR 77 */\r
+ PORT_PCR_RESET, /* PCR 78 */\r
+ PORT_PCR_RESET, /* PCR 79 */\r
+ PORT_PCR_RESET, /* PCR 80 */\r
+ PORT_PCR_RESET, /* PCR 81 */\r
+ PORT_PCR_RESET, /* PCR 82 */\r
+ PORT_PCR_RESET, /* PCR 83 */\r
+ PORT_PCR_RESET, /* PCR 84 */\r
+ PORT_PCR_RESET, /* PCR 85 */\r
+ PORT_PCR_RESET, /* PCR 86 */\r
+ PORT_PCR_RESET, /* PCR 87 */\r
+ PORT_PCR_RESET, /* PCR 88 */\r
+ PORT_PCR_RESET, /* PCR 89 */\r
+ PORT_PCR_RESET, /* PCR 90 */\r
+ PORT_PCR_RESET, /* PCR 91 */\r
+ PORT_PCR_RESET, /* PCR 92 */\r
+ PORT_PCR_RESET, /* PCR 93 */\r
+ PORT_PCR_RESET, /* PCR 94 */\r
+ PORT_PCR_RESET, /* PCR 95 */\r
+ PORT_PCR_RESET, /* PCR 96 */\r
+ PORT_PCR_RESET, /* PCR 97 */\r
+ PORT_PCR_RESET, /* PCR 98 */\r
+ PORT_PCR_RESET, /* PCR 99 */\r
+ PORT_PCR_RESET, /* PCR 100 */\r
+ PORT_PCR_RESET, /* PCR 101 */\r
+ PORT_PCR_RESET, /* PCR 102 */\r
+ PORT_PCR_RESET, /* PCR 103 */\r
+ PORT_PCR_RESET, /* PCR 104 */\r
+ PORT_PCR_RESET, /* PCR 105 */\r
+ PORT_PCR_RESET, /* PCR 106 */\r
+ PORT_PCR_RESET, /* PCR 107 */\r
+ PORT_PCR_RESET, /* PCR 108 */\r
+ PORT_PCR_RESET, /* PCR 109 */\r
+ PORT_PCR_RESET, /* PCR 110 */\r
+ PORT_PCR_RESET, /* PCR 111 */\r
+ PORT_PCR_RESET, /* PCR 112 */\r
+ PORT_PCR_RESET, /* PCR 113 */\r
+ PORT_PCR_RESET, /* PCR 114 */\r
+ PORT_PCR_RESET, /* PCR 115 */\r
+ PORT_PCR_RESET, /* PCR 116 */\r
+ PORT_PCR_RESET, /* PCR 117 */\r
+ PORT_PCR_RESET, /* PCR 118 */\r
+ PORT_PCR_RESET, /* PCR 119 */\r
+ PORT_PCR_RESET, /* PCR 120 */\r
+ PORT_PCR_RESET, /* PCR 121 */\r
+ PORT_PCR_RESET, /* PCR 122 */\r
+ PORT_PCR_RESET, /* PCR 123 */\r
+ PORT_PCR_RESET, /* PCR 124 */\r
+ PORT_PCR_RESET, /* PCR 125 */\r
+ PORT_PCR_RESET, /* PCR 126 */\r
+ PORT_PCR_RESET, /* PCR 127 */\r
+ PORT_PCR_RESET, /* PCR 128 */\r
+ PORT_PCR_RESET, /* PCR 129 */\r
+ PORT_PCR_RESET, /* PCR 130 */\r
+ PORT_PCR_RESET, /* PCR 131 */\r
+ PORT_PCR_RESET, /* PCR 132 */\r
+ PORT_PCR_RESET, /* PCR 133 */\r
+ PORT_PCR_RESET, /* PCR 134 */\r
+ PORT_PCR_RESET, /* PCR 135 */\r
+ PORT_PCR_RESET, /* PCR 136 */\r
+ PORT_PCR_RESET, /* PCR 137 */\r
+ PORT_PCR_RESET, /* PCR 138 */\r
+ PORT_PCR_RESET, /* PCR 139 */\r
+ PORT_PCR_RESET, /* PCR 140 */\r
+ PORT_PCR_RESET, /* PCR 141 */\r
+ PORT_PCR_RESET, /* PCR 142 */\r
+ PORT_PCR_RESET, /* PCR 143 */\r
+ PORT_PCR_RESET, /* PCR 144 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ PORT_GPDO_RESET, /* GPDO 0 */\r
+ PORT_GPDO_RESET, /* GPDO 1 */\r
+ PORT_GPDO_RESET, /* GPDO 2 */\r
+ PORT_GPDO_RESET, /* GPDO 3 */\r
+ PORT_GPDO_RESET, /* GPDO 4 */\r
+ PORT_GPDO_RESET, /* GPDO 5 */\r
+ PORT_GPDO_RESET, /* GPDO 6 */\r
+ PORT_GPDO_RESET, /* GPDO 7 */\r
+ PORT_GPDO_RESET, /* GPDO 8 */\r
+ PORT_GPDO_RESET, /* GPDO 9 */\r
+ PORT_GPDO_RESET, /* GPDO 10 */\r
+ PORT_GPDO_RESET, /* GPDO 11 */\r
+ PORT_GPDO_RESET, /* GPDO 12 */\r
+ PORT_GPDO_RESET, /* GPDO 13 */\r
+ PORT_GPDO_RESET, /* GPDO 14 */\r
+ PORT_GPDO_RESET, /* GPDO 15 */\r
+ PORT_GPDO_RESET, /* GPDO 16 */\r
+ PORT_GPDO_RESET, /* GPDO 17 */\r
+ PORT_GPDO_RESET, /* GPDO 18 */\r
+ PORT_GPDO_RESET, /* GPDO 19 */\r
+ PORT_GPDO_RESET, /* GPDO 20 */\r
+ PORT_GPDO_RESET, /* GPDO 21 */\r
+ PORT_GPDO_RESET, /* GPDO 22 */\r
+ PORT_GPDO_RESET, /* GPDO 23 */\r
+ PORT_GPDO_RESET, /* GPDO 24 */\r
+ PORT_GPDO_RESET, /* GPDO 25 */\r
+ PORT_GPDO_RESET, /* GPDO 26 */\r
+ PORT_GPDO_RESET, /* GPDO 27 */\r
+ PORT_GPDO_RESET, /* GPDO 28 */\r
+ PORT_GPDO_RESET, /* GPDO 29 */\r
+ PORT_GPDO_RESET, /* GPDO 30 */\r
+ PORT_GPDO_RESET, /* GPDO 31 */\r
+ PORT_GPDO_RESET, /* GPDO 32 */\r
+ PORT_GPDO_RESET, /* GPDO 33 */\r
+ PORT_GPDO_RESET, /* GPDO 34 */\r
+ PORT_GPDO_RESET, /* GPDO 35 */\r
+ PORT_GPDO_RESET, /* GPDO 36 */\r
+ PORT_GPDO_RESET, /* GPDO 37 */\r
+ PORT_GPDO_RESET, /* GPDO 38 */\r
+ PORT_GPDO_RESET, /* GPDO 39 */\r
+ PORT_GPDO_RESET, /* GPDO 40 */\r
+ PORT_GPDO_RESET, /* GPDO 41 */\r
+ PORT_GPDO_RESET, /* GPDO 42 */\r
+ PORT_GPDO_RESET, /* GPDO 43 */\r
+ PORT_GPDO_RESET, /* GPDO 44 */\r
+ PORT_GPDO_RESET, /* GPDO 45 */\r
+ PORT_GPDO_RESET, /* GPDO 46 */\r
+ PORT_GPDO_RESET, /* GPDO 47 */\r
+ PORT_GPDO_RESET, /* GPDO 48 */\r
+ PORT_GPDO_RESET, /* GPDO 49 */\r
+ PORT_GPDO_RESET, /* GPDO 50 */\r
+ PORT_GPDO_RESET, /* GPDO 51 */\r
+ PORT_GPDO_RESET, /* GPDO 52 */\r
+ PORT_GPDO_RESET, /* GPDO 53 */\r
+ PORT_GPDO_RESET, /* GPDO 54 */\r
+ PORT_GPDO_RESET, /* GPDO 55 */\r
+ PORT_GPDO_RESET, /* GPDO 56 */\r
+ PORT_GPDO_RESET, /* GPDO 57 */\r
+ PORT_GPDO_RESET, /* GPDO 58 */\r
+ PORT_GPDO_RESET, /* GPDO 59 */\r
+ PORT_GPDO_RESET, /* GPDO 60 */\r
+ PORT_GPDO_RESET, /* GPDO 61 */\r
+ PORT_GPDO_RESET, /* GPDO 62 */\r
+ PORT_GPDO_RESET, /* GPDO 63 */\r
+ PORT_GPDO_RESET, /* GPDO 64 */\r
+ PORT_GPDO_RESET, /* GPDO 65 */\r
+ PORT_GPDO_RESET, /* GPDO 66 */\r
+ PORT_GPDO_RESET, /* GPDO 67 */\r
+ PORT_GPDO_RESET, /* GPDO 68 */\r
+ PORT_GPDO_RESET, /* GPDO 69 */\r
+ PORT_GPDO_RESET, /* GPDO 70 */\r
+ PORT_GPDO_RESET, /* GPDO 71 */\r
+ PORT_GPDO_RESET, /* GPDO 72 */\r
+ PORT_GPDO_RESET, /* GPDO 73 */\r
+ PORT_GPDO_RESET, /* GPDO 74 */\r
+ PORT_GPDO_RESET, /* GPDO 75 */\r
+ PORT_GPDO_RESET, /* GPDO 76 */\r
+ PORT_GPDO_RESET, /* GPDO 77 */\r
+ PORT_GPDO_RESET, /* GPDO 78 */\r
+ PORT_GPDO_RESET, /* GPDO 79 */\r
+ PORT_GPDO_RESET, /* GPDO 80 */\r
+ PORT_GPDO_RESET, /* GPDO 81 */\r
+ PORT_GPDO_RESET, /* GPDO 82 */\r
+ PORT_GPDO_RESET, /* GPDO 83 */\r
+ PORT_GPDO_RESET, /* GPDO 84 */\r
+ PORT_GPDO_RESET, /* GPDO 85 */\r
+ PORT_GPDO_RESET, /* GPDO 86 */\r
+ PORT_GPDO_RESET, /* GPDO 87 */\r
+ PORT_GPDO_RESET, /* GPDO 88 */\r
+ PORT_GPDO_RESET, /* GPDO 89 */\r
+ PORT_GPDO_RESET, /* GPDO 90 */\r
+ PORT_GPDO_RESET, /* GPDO 91 */\r
+ PORT_GPDO_RESET, /* GPDO 92 */\r
+ PORT_GPDO_RESET, /* GPDO 93 */\r
+ PORT_GPDO_RESET, /* GPDO 94 */\r
+ PORT_GPDO_RESET, /* GPDO 95 */\r
+ PORT_GPDO_RESET, /* GPDO 96 */\r
+ PORT_GPDO_RESET, /* GPDO 97 */\r
+ PORT_GPDO_RESET, /* GPDO 98 */\r
+ PORT_GPDO_RESET, /* GPDO 99 */\r
+ PORT_GPDO_RESET, /* GPDO 100 */\r
+ PORT_GPDO_RESET, /* GPDO 101 */\r
+ PORT_GPDO_RESET, /* GPDO 102 */\r
+ PORT_GPDO_RESET, /* GPDO 103 */\r
+ PORT_GPDO_RESET, /* GPDO 104 */\r
+ PORT_GPDO_RESET, /* GPDO 105 */\r
+ PORT_GPDO_RESET, /* GPDO 106 */\r
+ PORT_GPDO_RESET, /* GPDO 107 */\r
+ PORT_GPDO_RESET, /* GPDO 108 */\r
+ PORT_GPDO_RESET, /* GPDO 109 */\r
+ PORT_GPDO_RESET, /* GPDO 110 */\r
+ PORT_GPDO_RESET, /* GPDO 111 */\r
+ PORT_GPDO_RESET, /* GPDO 112 */\r
+ PORT_GPDO_RESET, /* GPDO 113 */\r
+ PORT_GPDO_RESET, /* GPDO 114 */\r
+ PORT_GPDO_RESET, /* GPDO 115 */\r
+ PORT_GPDO_RESET, /* GPDO 116 */\r
+ PORT_GPDO_RESET, /* GPDO 117 */\r
+ PORT_GPDO_RESET, /* GPDO 118 */\r
+ PORT_GPDO_RESET, /* GPDO 119 */\r
+ PORT_GPDO_RESET, /* GPDO 120 */\r
+ PORT_GPDO_RESET, /* GPDO 121 */\r
+ PORT_GPDO_RESET, /* GPDO 122 */\r
+ PORT_GPDO_RESET, /* GPDO 123 */\r
+ PORT_GPDO_RESET, /* GPDO 124 */\r
+ PORT_GPDO_RESET, /* GPDO 125 */\r
+ PORT_GPDO_RESET, /* GPDO 126 */\r
+ PORT_GPDO_RESET, /* GPDO 127 */\r
+ PORT_GPDO_RESET, /* GPDO 128 */\r
+ PORT_GPDO_RESET, /* GPDO 129 */\r
+ PORT_GPDO_RESET, /* GPDO 130 */\r
+ PORT_GPDO_RESET, /* GPDO 131 */\r
+ PORT_GPDO_RESET, /* GPDO 132 */\r
+ PORT_GPDO_RESET, /* GPDO 133 */\r
+ PORT_GPDO_RESET, /* GPDO 134 */\r
+ PORT_GPDO_RESET, /* GPDO 135 */\r
+ PORT_GPDO_RESET, /* GPDO 136 */\r
+ PORT_GPDO_RESET, /* GPDO 137 */\r
+ PORT_GPDO_RESET, /* GPDO 138 */\r
+ PORT_GPDO_RESET, /* GPDO 139 */\r
+ PORT_GPDO_RESET, /* GPDO 140 */\r
+ PORT_GPDO_RESET, /* GPDO 141 */\r
+ PORT_GPDO_RESET, /* GPDO 142 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_OFF\r
+#define PORT_DEV_ERROR_DETECT STD_OFF\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_IO (0)\r
+#define PORT_FUNC0 (0)\r
+#define PORT_FUNC1 (PORT_BIT5)\r
+#define PORT_FUNC2 (PORT_BIT4)\r
+#define PORT_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+#define PORT_FUNC4 (PORT_BIT3)\r
+\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_GPDO_RESET (0)\r
+\r
+#define PORT_GPDO_HIGH (1)\r
+\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_eMIOS13 53 \r
+#define PORT_PIN_NAME_CNTX_A 48 \r
+#define PORT_PIN_NAME_CNRX_A 49 \r
+\r
+#endif /* PORT_CFG_H_ */\r
-/* \r
-* Configuration of module Pwm (Pwm_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:34 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
\r
/*\r
* Pwm_Cfg.c\r
},\r
#if PWM_NOTIFICATION_SUPPORTED==ON\r
.NotificationHandlers = {\r
- // Notification routine for PWM_CHANNEL_1\r
- ,\r
- \r
+// Notification routine for PWM_CHANNEL_1\r
+ NULL, \r
}\r
#endif\r
};\r
-
\ No newline at end of file
-/* \r
-* Configuration of module Pwm (Pwm_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:34 CEST 2010\r
-*/\r
-\r
-\r
-#if (PWM_SW_MAJOR_VERSION != 1) \r
-#error "Pwm: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module Pwm (Pwm_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:45:30 CET 2011\r
+ */\r
\r
+
+#if !(((PWM_SW_MAJOR_VERSION == 1) && (PWM_SW_MINOR_VERSION == 0)) )
+#error "Pwm: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef PWM_CFG_H_\r
#define PWM_CFG_H_\r
}\r
\r
#endif /* PWM_CFG_H_ */\r
-
\ No newline at end of file
inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
inc-y += $(ROOTDIR)/system/kernel/include\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
+VPATH += ../\r
+\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
\r
#TODO: Remove?, Build other way?\r
-VPATH += $(ROOTDIR)/$(SUBDIR)/Rte\r
-inc-y += $(ROOTDIR)/$(SUBDIR)/Rte\r
+VPATH += ../Rte\r
+inc-y += ../Rte\r
VPATH += $(ROOTDIR)/components/fading_led\r
inc-y += $(ROOTDIR)/components/fading_led\r
\r
\r
# libs needed by us \r
-libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+#libitem-y +=\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = pwm_node2.elf\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>pwm_node2_hcs12</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="bddc6ed9-5ca3-4816-bd60-f6a036d3bdc3">\r
+ <SHORT-NAME>pwm_node2_hcs12</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <REVISION-LABEL>Rev1</REVISION-LABEL>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">HCS12</SD>\r
+ <SD GID="AUTHOR">Arccore AB</SD>\r
+ <SD GID="GENDIR">/pwm_hcs12/config/hcs12x_elmicro_tboard</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/pwm_node2_hcs12/SwComposition_pwm_node2_hcs12</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/CanIf</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/Com</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/EcuC</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/EcuM</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/PduR</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/Port</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/Pwm</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_hcs12/Can</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="15a040bb-d8f3-4f87-a9f2-ba5bfe960fa1">\r
+ <SHORT-NAME>SwComposition_pwm_node2_hcs12</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="a02d0d3c-139e-43ba-a34f-6b2b356c0795">\r
+ <SHORT-NAME>CanIf</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/CanIf</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="5c1fc120-c759-4d63-87d2-a79160c3ad97">\r
+ <SHORT-NAME>CanIfDispatchConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDispatchConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfBusOffNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfErrorNotificaton</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupValidNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4e097a93-96bb-48ee-b4ea-404d07816fd1">\r
+ <SHORT-NAME>CanIfDriverConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDriverConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfBusoffNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfReceiveIndication</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTransmitCancellation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTxConfirmation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f7f3926a-0cf6-420a-8cd4-0587a1ac6c90">\r
+ <SHORT-NAME>CanIfInitConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfConfigSet</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanRxPduIds</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanTXPduIds</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfDynamicCanTXPduIds</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="1a375926-db73-4c4d-8e08-0f5e140b121e">\r
+ <SHORT-NAME>Hoh_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="6445c297-04d0-4e6f-beef-8aa463d2e12a">\r
+ <SHORT-NAME>RxHandler</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfHrhType</DEFINITION-REF>\r
+ <VALUE>BASIC_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfSoftwareFilterHrh</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfCanControllerHrhIdRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/CanIf/CHANNEL_0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="SYMBOLIC-NAME-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHrhConfig/CanIfHrhIdSymRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/Can/CanConfigSet/RxBox</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0cf91a50-aaa2-4ced-8a7a-cdbbfcf5c51c">\r
+ <SHORT-NAME>Rx_PDU_1</SHORT-NAME>\r
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+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="303041a0-dfae-4cb2-9231-9cd5159f0823">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="c0b83121-410d-4746-8c2b-e4a7522148d6">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f6bec2cf-7c37-4700-85f8-fc34f708b1a7">\r
+ <SHORT-NAME>ComTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f9afa00b-b8c6-49c1-9269-dc405aadc22b">\r
+ <SHORT-NAME>StartupTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="31f6edb0-9f6c-4de7-9442-fa8dc4f2315b">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="056d0fc9-4dbf-44cf-a8a1-6d41f71ded33">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a55ec12a-b16e-441b-a0b5-6ad00c35acd3">\r
+ <SHORT-NAME>ComAlarm</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="c1fc0ddd-4d7f-43af-8f57-c14d506f1bed">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/Os/ComTask</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2a49f11b-f258-4e4d-87e7-2f869242afd8">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="0c71cbf4-191b-4ff9-8d34-af29067dd8f1">\r
+ <SHORT-NAME>PduR</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/PduR</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="d02f4168-e3f2-44f1-a72f-b2c540006908">\r
+ <SHORT-NAME>PduRGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/PduR/PduRGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRCanIfSupport</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRCanTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRComSupport</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRDcmSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRFifoTxBufferSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRFrIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRFrTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRGatewayOperation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRIPduMSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRLinIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRLinTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMemorySize</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoModule</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoRxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoTxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpModule</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpRxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpTxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastFromIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastFromTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastToIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastToTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRSbTxBufferSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRSingleIf</DEFINITION-REF>\r
+ <VALUE>CAN_IF</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRSingleTp</DEFINITION-REF>\r
+ <VALUE>CAN_TP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRZeroCostOperation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8abbebb8-783c-4f97-ac28-3b78ea52e4ed">\r
+ <SHORT-NAME>PduRGlobalConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/PduR/PduRGlobalConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGlobalConfig/PduRConfigurationId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="f38c60fe-f11f-4b6b-a694-2bdebeb7fbff">\r
+ <SHORT-NAME>PduRRoutingTable</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/PduR/PduRGlobalConfig/PduRRoutingTable</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="a06e6eca-b8f3-40ee-b70a-526e9d07d86d">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="256a7c74-3a97-4041-a4f6-fdab77196a48">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fe36d864-a9cf-47e9-99f4-179f339fea26">\r
+ <SHORT-NAME>II2C</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="13de6916-4779-4cf9-aa84-6423f24b5c75">\r
+ <SHORT-NAME>SDA</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>38</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d40af306-47db-4163-866b-ed234f4d54aa">\r
+ <SHORT-NAME>SCL</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PJ7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>39</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c9118c42-7541-4c3e-aee5-9b33fb38e7de">\r
+ <SHORT-NAME>CAN0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="48995106-5317-492c-a8be-9dc90f86dce9">\r
+ <SHORT-NAME>TXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>49</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f355a281-9d29-4662-bd38-93b45a67b181">\r
+ <SHORT-NAME>RXD</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>48</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="970071df-1367-4fa6-b8ba-d12184ac9016">\r
+ <SHORT-NAME>LEDBAR</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="e75826c4-11e9-4c78-a62e-f64155f4d104">\r
+ <SHORT-NAME>PB0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f13211c5-d930-4315-88ac-f7baf7a013e1">\r
+ <SHORT-NAME>PB1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>17</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1bc00010-6ebe-436f-92e1-2d6c0895aa46">\r
+ <SHORT-NAME>PB2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>18</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0009d8fa-ebd5-451b-83f7-8a7e7fcc0ced">\r
+ <SHORT-NAME>PB3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>19</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="68143d0f-27ba-4bae-ad00-b8ca9392392d">\r
+ <SHORT-NAME>PB4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6367f310-133b-4b10-9275-5519396b82ff">\r
+ <SHORT-NAME>PB5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>21</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="59aa2eb4-ebde-472b-b5c1-ceecfce4336d">\r
+ <SHORT-NAME>PB6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>22</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4a169d18-36d5-40a7-8831-faf22622a866">\r
+ <SHORT-NAME>PB7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PB7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>23</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a0e9802a-f4ed-4ad3-b495-49157e822336">\r
+ <SHORT-NAME>DIPSW</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="27cbd4e4-129a-4364-be2b-a0054fb86cbe">\r
+ <SHORT-NAME>PH0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>24</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="30a97936-de39-42de-a3a9-d1e30f12af4d">\r
+ <SHORT-NAME>PH1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>25</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="084b83ee-4c09-4111-b19d-276dab9070ae">\r
+ <SHORT-NAME>PH2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>26</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7f90b11-a909-451c-a93e-b0bbe01df46a">\r
+ <SHORT-NAME>PH3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>27</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="417bb21d-caf2-48c2-a198-814203dc94da">\r
+ <SHORT-NAME>PH4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH4</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>28</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6e4f5953-9390-42fd-b33d-86736b010307">\r
+ <SHORT-NAME>PH5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH5</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>29</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="02660e29-0e6a-4781-98c8-74a3c9b908ef">\r
+ <SHORT-NAME>PH6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d85861f9-9523-45ad-aa84-44647733487b">\r
+ <SHORT-NAME>PH7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PH7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>31</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="103ee4c6-92df-4eae-b87a-096ccf9b56e2">\r
+ <SHORT-NAME>TIMER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="18f35583-11aa-4af3-a7cb-6bf56494047e">\r
+ <SHORT-NAME>PT0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>72</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="58635cff-b40b-41d7-879a-ea79efc33e06">\r
+ <SHORT-NAME>PT1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>73</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="99e5f077-39d8-48c6-8085-6b0764b0c48d">\r
+ <SHORT-NAME>BEEPER</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PT2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>74</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="95d6d2f4-2db4-4495-84ed-fa8032997f5b">\r
+ <SHORT-NAME>PWM</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="89bf9c10-ceb3-4d60-961c-1051ed4b031d">\r
+ <SHORT-NAME>PP0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="182cd6da-fc4c-4b21-8ad3-57e3e8c3568a">\r
+ <SHORT-NAME>PP1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PP1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a1fa03c0-2470-4914-aabd-17c992c74a92">\r
+ <SHORT-NAME>SCI0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9b4e54e6-bc5b-4ccb-b5d9-33670baae41c">\r
+ <SHORT-NAME>RXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS0</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>56</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1ae13d69-adf7-481a-929d-0c916d37daee">\r
+ <SHORT-NAME>TXD0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS1</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>57</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1d78b7b3-38f6-486c-89b2-3369eab9e7df">\r
+ <SHORT-NAME>SCI1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="19e08fdf-14d6-4cfe-aa28-969f9479fde7">\r
+ <SHORT-NAME>RXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_UP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS2</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>58</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="580e6d9e-8812-438d-9b01-94f8b2cda75f">\r
+ <SHORT-NAME>TXD1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PS3</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>59</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="218ea307-52d6-4837-abfb-080872edd058">\r
+ <SHORT-NAME>PM6</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM6</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>54</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ac024e84-9ae2-4303-a186-6a93ffc0902b">\r
+ <SHORT-NAME>PM7</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcReducedDrive</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <STRING-VALUE>\r
+ <DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/ArcPortPinName</DEFINITION-REF>\r
+ <VALUE>PM7</VALUE>\r
+ </STRING-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>55</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_HIGH</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="19e54a5c-c778-4d34-88ae-80eaf1fff9d8">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="17747ce9-57d3-476c-8203-8c93cd2a5dcc">\r
+ <SHORT-NAME>Pwm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Pwm</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="ecc119e4-7869-41cc-af30-3792813737cf">\r
+ <SHORT-NAME>PwmChannelConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a05dbf4b-56e8-4e6b-8139-4864371f67c2">\r
+ <SHORT-NAME>PWM_CHANNEL_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmCenterAlign</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/ArcPwmScaledClockEnable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelClass</DEFINITION-REF>\r
+ <VALUE>PWM_VARIABLE_PERIOD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmChannelId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmDutycycleDefault</DEFINITION-REF>\r
+ <VALUE>24576</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmIdleState</DEFINITION-REF>\r
+ <VALUE>PWM_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
+ <VALUE></VALUE>\r
+ </FUNCTION-NAME-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
+ <VALUE>188.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPolarity</DEFINITION-REF>\r
+ <VALUE>POLARITY_NORMAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c2a3ced7-5cde-4ca0-804f-9adeb4730fc4">\r
+ <SHORT-NAME>PwmConfigurationOfOptApiServices</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmDeInitApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmGetOutputState</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetDutyCycle</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetOutputToIdle</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmSetPeriodAndDuty</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmConfigurationOfOptApiServices/PwmVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b4c0e419-333e-4370-8f36-28034d382f59">\r
+ <SHORT-NAME>PwmGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Pwm/PwmGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmFreezeEnable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDevErorDetect</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmDutycycleUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmIndex</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmNotificationSupported</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/PwmPeriodUpdatedEndperiod</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerA</DEFINITION-REF>\r
+ <VALUE>PRESCALER_128</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelBusPrescalerB</DEFINITION-REF>\r
+ <VALUE>PRESCALER_2</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerA</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Pwm/PwmGeneral/ArcPwmChannelPrescalerB</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="84bdd5be-ae8f-4920-8123-425502312b34">\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Can</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="bba8d9ee-ff87-446d-853b-536a783c874f">\r
+ <SHORT-NAME>CanConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a5208169-71d2-4f2e-b5fd-766509996c65">\r
+ <SHORT-NAME>CAN0</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerActivation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerBaudRate</DEFINITION-REF>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanHWControllerId</DEFINITION-REF>\r
+ <VALUE>CAN_CTRL_0</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerPropSeg</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg1</DEFINITION-REF>\r
+ <VALUE>12</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg2</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="cd47453b-40ae-4958-bdb2-2c96b17c7952">\r
+ <SHORT-NAME>Mask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12IdamMaskType</DEFINITION-REF>\r
+ <VALUE>CAN_ARC_IDAM_2_32BIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12ArcIdmrValue</DEFINITION-REF>\r
+ <VALUE>18446744073709551615</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/ArcCanHcs12ArcIdarValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ </PARAMETER-VALUES>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="a77c39d5-4ea7-4321-83c5-bbe27d61c01b">\r
+ <SHORT-NAME>RxBox</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>RECEIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/Can/CanConfigSet/CAN0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/Can/CanConfigSet/CAN0/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ef1a36b6-b037-4177-99f8-3ae349f6157c">\r
+ <SHORT-NAME>TxBox</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>TRANSMIT</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/Can/CanConfigSet/CAN0</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/pwm_node2_hcs12/Can/CanConfigSet/CAN0/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
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+ <CONTAINER UUID="b5becc71-8e43-478d-aee9-bde788df0dad">\r
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+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanDevErrorDetection</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanMultiplexedTransmission</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE UUID="e78065d1-ae68-444e-8f2d-5898e52152c4">\r
+ <SHORT-NAME>GeneratedSystemSignals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <SYSTEM-SIGNAL UUID="a2a703d9-170c-47b5-9267-bd089053d069">\r
+ <SHORT-NAME>SetLedLevelRx</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::ParallelModelOptions">\r
+ <SD GID="PARALLEL_MODEL_GENERATED">TRUE</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <INIT-VALUE-REF DEST="INTEGER-LITERAL">/pwm_node2_hcs12/GeneratedSystemSignals/Data/IntegerLiterals/SetLedLevelRxInitValue/SetLedLevelRxInitValueLiteral</INIT-VALUE-REF>\r
+ <LENGTH>16</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>Data</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS/>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">255</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS/>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">65535</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS/>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">4294967295</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS/>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-128</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">127</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS/>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-32768</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">32767</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS/>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-2147483648</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">2147483647</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>IntegerLiterals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <CONSTANT-SPECIFICATION>\r
+ <SHORT-NAME>SetLedLevelRxInitValue</SHORT-NAME>\r
+ <VALUE>\r
+ <INTEGER-LITERAL UUID="2dbf7209-f911-48ab-846b-8d1343178e38">\r
+ <SHORT-NAME>SetLedLevelRxInitValueLiteral</SHORT-NAME>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-LITERAL>\r
+ </VALUE>\r
+ </CONSTANT-SPECIFICATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="7a138641-e1da-4ab5-9618-7bfdbc46ffa9">\r
<SHORT-NAME>pwm_node2_mpc551x</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SHORT-NAME>pwm_node2_mpc551x</SHORT-NAME>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
- <DOC-REVISION/>\r
+ <DOC-REVISION>\r
+ <REVISION-LABEL>Rev 1</REVISION-LABEL>\r
+ </DOC-REVISION>\r
</DOC-REVISIONS>\r
<SDGS>\r
<SDG GID="Arccore::EcuOptions">\r
<SD GID="MCU">MPC551x</SD>\r
- <SD GID="GENDIR">/pwm_node2_2/config</SD>\r
+ <SD GID="AUTHOR">Arccore AB</SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/pwm_node2_mpc551x/SwComposition_pwm_node2_mpc551x</ECU-SW-COMPOSITION-REF>\r
<MODULE-REFS>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_mpc551x/Can</MODULE-REF>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/pwm_node2_mpc551x/CanIf</MODULE-REF>\r
<SHORT-NAME>Can</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<SHORT-NAME>CanIf</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
<PARAMETER-VALUES>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfBusOffNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfErrorNotificaton</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupValidNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
<PARAMETER-VALUES>\r
<STRING-VALUE>\r
<DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfConfigSet</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</STRING-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanRxPduIds</DEFINITION-REF>\r
</ENUMERATION-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfRxPduConfig/CanIfUserRxIndication</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
</PARAMETER-VALUES>\r
<REFERENCE-VALUES>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfSoftwareFilterType</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
<SHORT-NAME>Com</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<PARAMETER-VALUES>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduCallout</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduRxHandleId</DEFINITION-REF>\r
</INTEGER-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Com/ComConfig/ComSignal/ComNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalEndianess</DEFINITION-REF>\r
</INTEGER-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTimeoutNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
<SHORT-NAME>EcuC</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<SHORT-NAME>EcuM</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMVersionInfoApi</DEFINITION-REF>\r
<VALUE>false</VALUE>\r
</BOOLEAN-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMMainFunctionPeriod</DEFINITION-REF>\r
+ <VALUE>0.2</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0969990f-6520-46e5-a6c5-68fac284e6d2">\r
+ <SHORT-NAME>EcuMConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramReadallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMRunMinimumDuration</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramWriteallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
</CONTAINERS>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
<SHORT-NAME>PduR</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoModule</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoRxPduId</DEFINITION-REF>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpModule</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpRxPduId</DEFINITION-REF>\r
<SHORT-NAME>Port</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<SHORT-NAME>Pwm</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
<SUB-CONTAINERS>\r
- <CONTAINER UUID="aad28c1c-ef39-4003-8782-cc280dfa1a23">\r
+ <CONTAINER UUID="2f95dcba-6a3d-49e0-9094-cec839c6cf59">\r
<SHORT-NAME>eMIOS[13]</SHORT-NAME>\r
<DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
<PARAMETER-VALUES>\r
</BOOLEAN-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
- <VALUE>45</VALUE>\r
+ <VALUE>53</VALUE>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
<SHORT-NAME>Pwm</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
</ENUMERATION-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FLOAT-VALUE>\r
<DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/Pwm/PwmChannelConfigSet/PwmChannel/PwmPeriodDefault</DEFINITION-REF>\r
</CONTAINER>\r
</CONTAINERS>\r
</MODULE-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="b7204398-6dcc-46ff-810a-8386273a3b42">\r
+ <SHORT-NAME>SwComposition_pwm_node2_mpc551x</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
</ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE UUID="a9260709-8342-4b59-bf9b-dbfcbaa9b787">\r
+ <SHORT-NAME>GeneratedSystemSignals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <SYSTEM-SIGNAL UUID="8da5bafc-7bf3-4870-9ab9-86f2c0d9fb73">\r
+ <SHORT-NAME>SetLedLevelRx</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::ParallelModelOptions">\r
+ <SD GID="PARALLEL_MODEL_GENERATED">TRUE</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <INIT-VALUE-REF DEST="INTEGER-LITERAL">/pwm_node2_mpc551x/GeneratedSystemSignals/Data/IntegerLiterals/SetLedLevelRxInitValue/SetLedLevelRxInitValueLiteral</INIT-VALUE-REF>\r
+ <LENGTH>16</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>Data</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">255</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">65535</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">4294967295</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-128</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">127</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-32768</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">32767</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-2147483648</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">2147483647</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>IntegerLiterals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <CONSTANT-SPECIFICATION>\r
+ <SHORT-NAME>SetLedLevelRxInitValue</SHORT-NAME>\r
+ <VALUE>\r
+ <INTEGER-LITERAL UUID="ce069300-3769-41f8-916d-f1c73a9a5ebd">\r
+ <SHORT-NAME>SetLedLevelRxInitValueLiteral</SHORT-NAME>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-LITERAL>\r
+ </VALUE>\r
+ </CONSTANT-SPECIFICATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
\r
-MOD_USE+=KERNEL MCU\r
+-include ../config/*.mk\r
+-include ../config/$(BOARDDIR)/*.mk\r
\r
-SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+MOD_USE+= DET ECUM MCU KERNEL RAMLOG \r
\r
-def-y += CFG_RAMLOG_SIZE=1024\r
-def-y += HEAPSIZE=1400
\ No newline at end of file
+#def-y += NDEBUG\r
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:25:22 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 14:52:25 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:25:22 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 14:52:25 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
\r
// Stack size\r
#define OS_INTERRUPT_STACK_SIZE 512\r
-#define OS_OSIDLE_STACK_SIZE 200\r
+#define OS_OSIDLE_STACK_SIZE 512\r
\r
#define OS_ALARM_CNT 1 \r
#define OS_TASK_CNT 4\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 10:42:01 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,512);\r
+DECLARE_STACK(etask_1,512);\r
+DECLARE_STACK(etask_2,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 10:42:01 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:26:09 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:21:12 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:26:09 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:21:12 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 21:46:57 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 21:46:57 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 21:46:57 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 21:46:57 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:26:34 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:52:54 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:26:34 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:52:54 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:49:22 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:49:22 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 09:13:21 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 09:13:21 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 16:25:07 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): TMS570\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 16:25:07 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
\r
# Our object files\r
obj-y += simple_main.o\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
\r
VPATH += ..\r
VPATH += ../config\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
# libs needed by us \r
-libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+#libitem-y += \r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+#ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldp\r
\r
# What I want to build\r
build-exe-y = simple.elf\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>simple_arm_cr4</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="ce8f4c18-6e54-4275-b9be-ee7e6f731690">\r
+ <SHORT-NAME>simple_arm_cr4</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">TMS570</SD>\r
+ <SD GID="GENDIR">/simple/config/ti_tms570ls</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/simple_arm_cr4/SwComposition_simple_arm_cr4</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/simple_arm_cr4/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="41962514-d10a-4c2b-9bbd-2bf759446c16">\r
+ <SHORT-NAME>SwComposition_simple_arm_cr4</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="29b23c16-ee7a-4b40-afaf-6c4117db16d3">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="92c5a2e3-81e3-4e1f-9137-174435a92b41">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="6578a055-00a4-4de2-8e87-3b7758f9caf7">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="67722c4e-130a-4dac-8aeb-72ed94e3e7e9">\r
+ <SHORT-NAME>Alarm1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cr4/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="78d0ecea-4ed3-4503-b0c8-4ad0b400d6ab">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6de53f9-2026-4621-887f-556572f825be">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cr4/Os/EVENT_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cr4/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9c54b7bd-b0c1-4733-a6a4-b77b22b8df12">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="170cda57-b4ad-4c67-8384-97736003af20">\r
+ <SHORT-NAME>etask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9254b1b9-6b3d-4e1a-b294-871e853d8ae0">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8c0b5497-cc95-4e9b-b102-99f3f7e637bb">\r
+ <SHORT-NAME>etask_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b5d30e9f-ae64-42ba-861e-7dd525761722">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="72dc534e-fc28-4883-b1d7-5e1162314494">\r
+ <SHORT-NAME>btask_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5f7216e5-bed0-4a95-bf07-26b1c54be1c0">\r
+ <SHORT-NAME>EVENT_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="896fdbc9-ed9a-4f24-9366-257760788019">\r
+ <SHORT-NAME>EVENT_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d681023d-1f60-4239-b9a2-7889a00bdaa4">\r
+ <SHORT-NAME>EVENT_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>simple_arm_cm3</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="4ab03f0b-f00d-4eb3-8406-006c42d20f4d">\r
+ <SHORT-NAME>simple_arm_cm3</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">STM32_F103</SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/simple_arm_cm3/SwComposition_simple_arm_cm3</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/simple_arm_cm3/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="a5ac45c0-0dd8-4e11-8f33-bcc59510e846">\r
+ <SHORT-NAME>SwComposition_simple_arm_cm3</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="29b23c16-ee7a-4b40-afaf-6c4117db16d3">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="92c5a2e3-81e3-4e1f-9137-174435a92b41">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="6578a055-00a4-4de2-8e87-3b7758f9caf7">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="67722c4e-130a-4dac-8aeb-72ed94e3e7e9">\r
+ <SHORT-NAME>Alarm1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cm3/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="78d0ecea-4ed3-4503-b0c8-4ad0b400d6ab">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6de53f9-2026-4621-887f-556572f825be">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cm3/Os/EVENT_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cm3/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9c54b7bd-b0c1-4733-a6a4-b77b22b8df12">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="170cda57-b4ad-4c67-8384-97736003af20">\r
+ <SHORT-NAME>etask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9254b1b9-6b3d-4e1a-b294-871e853d8ae0">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8c0b5497-cc95-4e9b-b102-99f3f7e637bb">\r
+ <SHORT-NAME>etask_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b5d30e9f-ae64-42ba-861e-7dd525761722">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="72dc534e-fc28-4883-b1d7-5e1162314494">\r
+ <SHORT-NAME>btask_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5f7216e5-bed0-4a95-bf07-26b1c54be1c0">\r
+ <SHORT-NAME>EVENT_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="896fdbc9-ed9a-4f24-9366-257760788019">\r
+ <SHORT-NAME>EVENT_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d681023d-1f60-4239-b9a2-7889a00bdaa4">\r
+ <SHORT-NAME>EVENT_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>simple_arm_cm3</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="4ab03f0b-f00d-4eb3-8406-006c42d20f4d">\r
+ <SHORT-NAME>simple_arm_cm3</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">STM32_F107</SD>\r
+ <SD GID="GENDIR">/simple/config/stm32_stm3210c</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/simple_arm_cm3/SwComposition_simple_arm_cm3</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/simple_arm_cm3/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="a5ac45c0-0dd8-4e11-8f33-bcc59510e846">\r
+ <SHORT-NAME>SwComposition_simple_arm_cm3</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="29b23c16-ee7a-4b40-afaf-6c4117db16d3">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="92c5a2e3-81e3-4e1f-9137-174435a92b41">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="6578a055-00a4-4de2-8e87-3b7758f9caf7">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="67722c4e-130a-4dac-8aeb-72ed94e3e7e9">\r
+ <SHORT-NAME>Alarm1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cm3/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="78d0ecea-4ed3-4503-b0c8-4ad0b400d6ab">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6de53f9-2026-4621-887f-556572f825be">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cm3/Os/EVENT_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/simple_arm_cm3/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9c54b7bd-b0c1-4733-a6a4-b77b22b8df12">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="170cda57-b4ad-4c67-8384-97736003af20">\r
+ <SHORT-NAME>etask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="9254b1b9-6b3d-4e1a-b294-871e853d8ae0">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8c0b5497-cc95-4e9b-b102-99f3f7e637bb">\r
+ <SHORT-NAME>etask_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b5d30e9f-ae64-42ba-861e-7dd525761722">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="72dc534e-fc28-4883-b1d7-5e1162314494">\r
+ <SHORT-NAME>btask_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5f7216e5-bed0-4a95-bf07-26b1c54be1c0">\r
+ <SHORT-NAME>EVENT_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="896fdbc9-ed9a-4f24-9366-257760788019">\r
+ <SHORT-NAME>EVENT_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d681023d-1f60-4239-b9a2-7889a00bdaa4">\r
+ <SHORT-NAME>EVENT_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="0d59ee12-95ec-49af-8852-d0a411bc3657">\r
<SHORT-NAME>simple_hcs12</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
</INTEGER-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
- <VALUE>200</VALUE>\r
+ <VALUE>512</VALUE>\r
</INTEGER-VALUE>\r
<BOOLEAN-VALUE>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
</MODULE-CONFIGURATION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-#include "Os.h"\r
-#include "Mcu.h"\r
-#include "arc.h"\r
-\r
-#define USE_LDEBUG_PRINTF\r
-#include "debug.h"\r
-\r
-// How many errors to keep in error log.\r
-#define ERROR_LOG_SIZE 20\r
-\r
-\r
-/**\r
- * Just an example of a basic task.\r
- */\r
-\r
-void btask_3( void ) {\r
- StackInfoType si;\r
- TaskType currTask;\r
- LDEBUG_PRINTF("[%08d] btask_3 start\n", GetOsTick() );\r
-\r
- GetTaskID(&currTask);\r
- Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("btask_3: Stack usage %d%%\n",OS_STACK_USAGE(&si));\r
-\r
- TerminateTask();\r
-}\r
-\r
-/**\r
- * An extended task is auto-started and is also triggered by an alarm\r
- * that sets event 2.\r
- */\r
-\r
-void etask_1( void ) {\r
- volatile float tryFloatingPoint = 0.0F;\r
- StackInfoType si;\r
- TaskType currTask;\r
-\r
-\r
- LDEBUG_PRINTF("etask_1 start\n");\r
- for(;;) {\r
- SetEvent(TASK_ID_etask_2,1);\r
- WaitEvent(2);\r
- ClearEvent(2);\r
- tryFloatingPoint += 1.0F;\r
- GetTaskID(&currTask);\r
- Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("etask_1: Stack usage %d%% \n",OS_STACK_USAGE(&si));\r
-\r
- }\r
-}\r
-\r
-/**\r
- * An extended task that receives events from someone\r
- * and activates task: btask_3.\r
- */\r
-void etask_2( void ) {\r
- LDEBUG_PRINTF("etask_2 start\n");\r
-\r
- for(;;) {\r
- WaitEvent(1);\r
- ClearEvent(1);\r
- ActivateTask(TASK_ID_btask_3);\r
- {\r
- StackInfoType si;\r
- TaskType currTask;\r
- GetTaskID(&currTask);\r
- Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("etask_1: Stack usage %d%% \n",OS_STACK_USAGE(&si));\r
- }\r
- }\r
-}\r
-\r
-\r
-/*\r
- * Functions that must be supplied by the example\r
- */\r
-\r
-void OsIdle( void ) {\r
- for(;;);\r
-}\r
-\r
-\r
-/* Global hooks */\r
-ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
- LDEBUG_PRINTF("## ProtectionHook\n");\r
- return PRO_KILLAPPL;\r
-}\r
-\r
-void StartupHook( void ) {\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
-\r
- LDEBUG_PRINTF("## StartupHook\n");\r
-\r
- LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
-}\r
-\r
-void ShutdownHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ShutdownHook\n");\r
- while(1);\r
-}\r
-\r
-struct LogBad_s {\r
- uint32_t param1;\r
- uint32_t param2;\r
- uint32_t param3;\r
- TaskType taskId;\r
- OsServiceIdType serviceId;\r
- StatusType error;\r
-};\r
-\r
-void ErrorHook( StatusType Error ) {\r
-\r
- TaskType task;\r
- static struct LogBad_s LogBad[ERROR_LOG_SIZE];\r
- static uint8_t ErrorCount = 0;\r
-\r
- GetTaskID(&task);\r
-\r
-\r
- OsServiceIdType service = OSErrorGetServiceId();\r
-\r
- /* Grab the arguments to the functions\r
- * This is the standard way, see 11.2 in OSEK spec\r
- */\r
- switch(service) {\r
- case OSServiceId_SetRelAlarm:\r
- {\r
- // Read the arguments to the faulty functions...\r
- /* (Commented to remove warnings)\r
- AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;\r
- TickType increment = OSError_SetRelAlarm_Increment;\r
- TickType cycle = OSError_SetRelAlarm_Cycle; */\r
- // ... Handle this some way.\r
- break;\r
- }\r
- /*\r
- * The same pattern as above applies for all other OS functions.\r
- * See Os.h for names and definitions.\r
- */\r
-\r
- default:\r
- break;\r
- }\r
-\r
- LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);\r
-\r
- /* Log the errors in a buffer for later review */\r
- LogBad[ErrorCount].param1 = os_error.param1;\r
- LogBad[ErrorCount].param2 = os_error.param2;\r
- LogBad[ErrorCount].param3 = os_error.param3;\r
- LogBad[ErrorCount].serviceId = service;\r
- LogBad[ErrorCount].taskId = task;\r
- LogBad[ErrorCount].error = Error;\r
-\r
- ErrorCount++;\r
-\r
- // Stall if buffer is full.\r
- while(ErrorCount >= ERROR_LOG_SIZE);\r
-}\r
-\r
-void PreTaskHook( void ) {\r
- TaskType task;\r
- GetTaskID(&task);\r
-// LDEBUG_PRINTF("## PreTaskHook, taskid=%d\n",task);\r
-}\r
-\r
-void PostTaskHook( void ) {\r
- TaskType task;\r
- GetTaskID(&task);\r
-// LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
-}\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include "Os.h"
+#include "Mcu.h"
+#include "arc.h"
+
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.
+#include "debug.h"
+
+// How many errors to keep in error log.
+#define ERROR_LOG_SIZE 20
+
+
+/**
+ * Just an example of a basic task.
+ */
+
+void btask_3( void ) {
+ StackInfoType si;
+ TaskType currTask;
+ LDEBUG_PRINTF("[%08u] btask_3 start\n", (unsigned)GetOsTick() );
+
+ GetTaskID(&currTask);
+ Os_Arc_GetStackInfo(currTask,&si);
+ LDEBUG_PRINTF("btask_3: %u%% stack usage\n",
+ (unsigned)OS_STACK_USAGE(&si));
+
+ TerminateTask();
+}
+
+/**
+ * An extended task is auto-started and is also triggered by an alarm
+ * that sets event 2.
+ */
+
+void etask_1( void ) {
+ volatile float tryFloatingPoint = 0.0F;
+ StackInfoType si;
+ TaskType currTask;
+
+ LDEBUG_FPUTS("etask_1 start\n");
+ for(;;) {
+ SetEvent(TASK_ID_etask_2,EVENT_MASK_EVENT_1);
+ WaitEvent(EVENT_MASK_EVENT_2);
+ ClearEvent(EVENT_MASK_EVENT_2);
+ tryFloatingPoint += 1.0F;
+ GetTaskID(&currTask);
+ Os_Arc_GetStackInfo(currTask,&si);
+ LDEBUG_PRINTF("etask_1: %u%% stack usage\n",
+ (unsigned)OS_STACK_USAGE(&si));
+
+ }
+}
+
+/**
+ * An extended task that receives events from someone
+ * and activates task: btask_3.
+ */
+void etask_2( void ) {
+ LDEBUG_FPUTS("etask_2 start\n");
+
+ for(;;) {
+ WaitEvent(EVENT_MASK_EVENT_1);
+ ClearEvent(EVENT_MASK_EVENT_1);
+ ActivateTask(TASK_ID_btask_3);
+ {
+ StackInfoType si;
+ TaskType currTask;
+ GetTaskID(&currTask);
+ Os_Arc_GetStackInfo(currTask,&si);
+ LDEBUG_PRINTF("etask_2: %u%% stack usage\n",
+ (unsigned)OS_STACK_USAGE(&si));
+ }
+ }
+}
+
+
+/*
+ * Functions that must be supplied by the example
+ */
+
+void OsIdle( void ) {
+ for(;;);
+}
+
+
+/* Global hooks */
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {
+ LDEBUG_FPUTS("## ProtectionHook\n");
+ return PRO_KILLAPPL;
+}
+
+void StartupHook( void ) {
+ LDEBUG_FPUTS("## StartupHook\n");
+
+ LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)McuE_GetSystemClock());
+}
+
+void ShutdownHook( StatusType Error ) {
+ LDEBUG_FPUTS("## ShutdownHook\n");
+ while(1);
+}
+
+struct LogBad_s {
+ uint32_t param1;
+ uint32_t param2;
+ uint32_t param3;
+ TaskType taskId;
+ OsServiceIdType serviceId;
+ StatusType error;
+};
+
+void ErrorHook( StatusType Error ) {
+
+ TaskType task;
+ static struct LogBad_s LogBad[ERROR_LOG_SIZE];
+ static uint8_t ErrorCount = 0;
+
+ GetTaskID(&task);
+
+
+ OsServiceIdType service = OSErrorGetServiceId();
+
+ /* Grab the arguments to the functions
+ * This is the standard way, see 11.2 in OSEK spec
+ */
+ switch(service) {
+ case OSServiceId_SetRelAlarm:
+ {
+ // Read the arguments to the faulty functions...
+ AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;
+ TickType increment = OSError_SetRelAlarm_Increment;
+ TickType cycle = OSError_SetRelAlarm_Cycle;
+ (void)alarm_id;
+ (void)increment;
+ (void)cycle;
+
+ // ... Handle this some way.
+ break;
+ }
+ /*
+ * The same pattern as above applies for all other OS functions.
+ * See Os.h for names and definitions.
+ */
+
+ default:
+ break;
+ }
+
+ LDEBUG_PRINTF("## ErrorHook err=%u\n",Error);
+
+ /* Log the errors in a buffer for later review */
+ LogBad[ErrorCount].param1 = os_error.param1;
+ LogBad[ErrorCount].param2 = os_error.param2;
+ LogBad[ErrorCount].param3 = os_error.param3;
+ LogBad[ErrorCount].serviceId = service;
+ LogBad[ErrorCount].taskId = task;
+ LogBad[ErrorCount].error = Error;
+
+ ErrorCount++;
+
+ // Stall if buffer is full.
+ while(ErrorCount >= ERROR_LOG_SIZE);
+}
+
+void PreTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+// LDEBUG_PRINTF("## PreTaskHook, taskid=%u\n",task);
+}
+
+void PostTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+// LDEBUG_PRINTF("## PostTaskHook, taskid=%u\n",task);
+}
+
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="0d59ee12-95ec-49af-8852-d0a411bc3657">\r
<SHORT-NAME>simple_ppc</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/simple_ppc/SwComposition_simple_ppc</ECU-SW-COMPOSITION-REF>\r
<MODULE-REFS>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/simple_ppc/Os</MODULE-REF>\r
</MODULE-REFS>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
</CONTAINER>\r
</CONTAINERS>\r
</MODULE-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="b992cfe3-fc89-47e3-bc02-d1674260aac3">\r
+ <SHORT-NAME>SwComposition_simple_ppc</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
\r
\r
#include "Os.h"\r
+#include "Mcu.h"\r
#include <stdio.h>\r
#include <assert.h>\r
\r
-#define USE_LDEBUG_PRINTF\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
#include "debug.h"\r
\r
-#include "Mcu.h"\r
-\r
-\r
-#if 0\r
-#ifdef USE_STARTUPHOOK\r
-#ifdef CFG_MPC55XX\r
-#if !defined(USE_SIMULATOR)\r
-// Quick fix\r
-//#include "Kernel_Offset.h"\r
-\r
-extern uint8_t pcb_list[];\r
-\r
-#endif\r
-#endif\r
-#endif\r
-#endif\r
\r
\r
\r
void StartupHook( void ) {\r
LDEBUG_PRINTF("## StartupHook\n");\r
\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
-\r
- LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
+ LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)McuE_GetSystemClock());\r
}\r
\r
void ShutdownHook( StatusType Error ) {\r
void PostTaskHook( void ) {\r
// dbg_printf("## PostTaskHook, taskid=%d\n",task);\r
}\r
-\r
-#if 0\r
-struct OsHooks os_conf_global_hooks = {\r
- .StartupHook = StartupHook,\r
- .ProtectionHook = ProtectionHook,\r
- .ShutdownHook = ShutdownHook,\r
- .ErrorHook = ErrorHook,\r
- .PreTaskHook = PreTaskHook,\r
- .PostTaskHook = PostTaskHook\r
- };\r
-#endif\r
#include "EcuM.h"\r
#include <stdio.h>\r
#include <assert.h>\r
-#include "debug.h"\r
#include "Com.h"\r
#include "Adc.h"\r
\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
+#include "debug.h"\r
+\r
void OsIdle( void ) {\r
for(;;);\r
}\r
// Call second phase of startup sequence.\r
EcuM_StartupTwo();\r
\r
+ // Startup CanIf due to ComM is missing in this example\r
+ CanIf_InitController(CANIF_CHANNEL_0, CANIF_CHANNEL_0_CONFIG_0);\r
+ CanIf_SetControllerMode(CANIF_CHANNEL_0, CANIF_CS_STARTED);\r
+\r
// Make sure that the right PDU-groups are ready for communication.\r
Com_IpduGroupStart(TxGroup, 0);\r
\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU ADC DMA \r
+MOD_USE+=ADC DET ECUM DMA KERNEL MCU \r
\r
SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+SELECT_OS_CONSOLE = RAMLOG
\ No newline at end of file
+++ /dev/null
-/* \r
-* Configuration of module Com (Com_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (COM_SW_MAJOR_VERSION != 1) \r
-#error "Com: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-#ifndef COM_CFG_H_\r
-#define COM_CFG_H_\r
-\r
-#define COM_MODULE_ID 20\r
-#define COM_INSTANCE_ID 1\r
-\r
-#define COM_DEV_ERROR_DETECT\r
-\r
-#define COM_N_IPDUS 1\r
-#define COM_N_SIGNALS 1\r
-#define COM_N_GROUP_SIGNALS 0\r
-\r
-#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
-#define COM_E_INITIALIZATION_FAILED 102\r
-#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
-#define COM_INVALID_PDU_ID 104\r
-#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
-\r
-\r
-#define COM_MAX_NR_IPDU 999999999\r
-\r
-#define COM_E_TOO_MANY_IPDU 106\r
-#define COM_E_TOO_MANY_SIGNAL 107\r
-#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
-\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
-\r
-/*\r
- * ComGeneral pre-compile time configuration parameters.\r
- */\r
-#define ComConfigurationTimeBase 0.0\r
-#define ComVersionInfoApi\r
-\r
-#endif /*COM_CFG_H_*/\r
+++ /dev/null
-/* \r
-* Configuration of module Com (Com_PbCfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#include "Com.h"\r
-#include "stdlib.h"\r
-#if defined(USE_PDUR)\r
-#include "PduR.h"\r
-#endif\r
-\r
-\r
-\r
-\r
-\r
-/*\r
- * Signal init values.\r
- */\r
-const uint16 Com_SignalInitValue_SetLedLevelTx = 0;\r
- \r
-\r
-/*\r
- * Group signal definitions\r
- */\r
-const ComGroupSignal_type ComGroupSignal[] = {\r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-\r
-/* SignalGroup GroupSignals lists. */\r
-\r
-/*\r
- * Signal definitions\r
- */\r
-const ComSignal_type ComSignal[] = {\r
- {\r
- .ComHandleId = SetLedLevelTx,\r
- .ComFirstTimeoutFactor = 0,\r
- .ComNotification = NULL,\r
- .ComTimeoutFactor = 0,\r
- .ComTimeoutNotification = NULL,\r
- .ComTransferProperty = TRIGGERED,\r
- \r
- \r
- .ComSignalInitValue = &Com_SignalInitValue_SetLedLevelTx,\r
- .ComBitPosition = 7,\r
- .ComBitSize = 16,\r
- .ComSignalEndianess = BIG_ENDIAN,\r
- .ComSignalType = UINT16,\r
- .ComGroupSignal = NULL,\r
- \r
- },\r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-\r
-/*\r
- * I-PDU group definitions\r
- */\r
-const ComIPduGroup_type ComIPduGroup[] = {\r
- {\r
- .ComIPduGroupHandleId = TxGroup\r
- },\r
- \r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-/* IPdu signal lists. */\r
-const ComSignal_type *ComIPduSignalRefs_LedCommandTx[] = {\r
- &ComSignal[ SetLedLevelTx ], \r
- NULL,\r
-};\r
-\r
-/*\r
- * I-PDU definitions\r
- */\r
-const ComIPdu_type ComIPdu[] = { \r
- \r
- { // LedCommandTx\r
- .ArcIPduOutgoingId = PDUR_DEST_PDU_ID_LedCommandTx,\r
- .ComIPduCallout = NULL,\r
- .ComIPduSignalProcessing = DEFERRED,\r
- .ComIPduSize = 8,\r
- .ComIPduDirection = SEND,\r
- .ComIPduGroupRef = TxGroup,\r
- \r
- .ComTxIPdu = {\r
- .ComTxIPduMinimumDelayFactor = 0,\r
- .ComTxIPduUnusedAreasDefault = 0,\r
- .ComTxModeTrue = {\r
- .ComTxModeMode = DIRECT,\r
- .ComTxModeNumberOfRepetitions = 0,\r
- .ComTxModeRepetitionPeriodFactor = 0,\r
- .ComTxModeTimeOffsetFactor = 0,\r
- .ComTxModeTimePeriodFactor = 0,\r
- },\r
- },\r
- \r
- .ComIPduSignalRef = ComIPduSignalRefs_LedCommandTx,\r
- }, \r
- {\r
- .Com_Arc_EOL = 1\r
- }\r
-};\r
-\r
-const Com_ConfigType ComConfiguration = {\r
- .ComConfigurationId = 1,\r
- .ComIPdu = ComIPdu,\r
- .ComIPduGroup = ComIPduGroup,\r
- .ComSignal = ComSignal,\r
- .ComGroupSignal = ComGroupSignal\r
-};\r
-\r
-\r
+++ /dev/null
-/* \r
-* Configuration of module Com (Com_PbCfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (COM_SW_MAJOR_VERSION != 1) \r
-#error "Com: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-#ifndef COM_PBCFG_H_\r
-#define COM_PBCFG_H_\r
-\r
-#include "Com_Types.h"\r
-\r
-extern const Com_ConfigType ComConfiguration;\r
-\r
-// COM Polite Defines.\r
-#define COM_PDU_ID_LedCommandTx 0\r
-\r
-\r
-\r
-// PDU group definitions\r
-enum {\r
- TxGroup = 0,\r
-};\r
-\r
-// Signal definitions\r
-enum {\r
- SetLedLevelTx = 0,\r
-};\r
-\r
-\r
-\r
-\r
-#endif /* COM_PBCFG_H_ */\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Callout_template.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:43:38 CEST 2010\r
-*/\r
-\r
-\r
-#include "EcuM.h"\r
-#include "Det.h"\r
-#if defined(USE_DEM)\r
-#include "Dem.h"\r
-#endif\r
-#if defined(USE_MCU)\r
-#include "Mcu.h"\r
-#endif\r
-#if defined(USE_GPT)\r
-#include "Gpt.h"\r
-#endif\r
-#if defined(USE_CAN)\r
-#include "Can.h"\r
-#endif\r
-#if defined(USE_CANIF)\r
-#include "CanIf.h"\r
-#endif\r
-#if defined(USE_PDUR)\r
-#include "PduR.h"\r
-#endif\r
-#if defined(USE_COM)\r
-#include "Com.h"\r
-#endif\r
-#if defined(USE_CANTP)\r
-#include "CanTp.h"\r
-#endif\r
-#if defined(USE_DCM)\r
-#include "Dcm.h"\r
-#endif\r
-#if defined(USE_PWM)\r
-#include "Pwm.h"\r
-#endif\r
-#if defined(USE_IOHWAB)\r
-#include "IoHwAb.h"\r
-#endif\r
-\r
-void EcuM_AL_DriverInitZero()\r
-{\r
- Det_Init();\r
- Det_Start();\r
-}\r
-\r
-EcuM_ConfigType* EcuM_DeterminePbConfiguration()\r
-{\r
- return &EcuMConfig;\r
-}\r
-\r
-void EcuM_AL_DriverInitOne(const EcuM_ConfigType *ConfigPtr)\r
-{\r
-#if defined(USE_MCU)\r
- Mcu_Init(ConfigPtr->McuConfig);\r
-\r
- // Set up default clock (Mcu_InitClock requires initRun==1)\r
- Mcu_InitClock( ConfigPtr->McuConfig->McuDefaultClockSettings );\r
-\r
- // Wait for PLL to sync.\r
- while (Mcu_GetPllStatus() != MCU_PLL_LOCKED)\r
- ;\r
-#endif\r
-\r
-#if defined(USE_DEM)\r
- // Preinitialize DEM\r
- Dem_PreInit();\r
-#endif\r
-\r
-#if defined(USE_PORT)\r
- // Setup Port\r
- Port_Init(ConfigPtr->PortConfig);\r
-#endif\r
-\r
-\r
-#if defined(USE_GPT)\r
- // Setup the GPT\r
- Gpt_Init(ConfigPtr->GptConfig);\r
-#endif\r
-\r
- // Setup watchdog\r
- // TODO\r
-\r
-#if defined(USE_DMA)\r
- // Setup DMA\r
- Dma_Init(ConfigPtr->DmaConfig);\r
-#endif\r
-\r
-#if defined(USE_ADC)\r
- // Setup ADC\r
- Adc_Init(ConfigPtr->AdcConfig);\r
-#endif\r
-\r
- // Setup ICU\r
- // TODO\r
-\r
- // Setup PWM\r
-#if defined(USE_PWM)\r
- // Setup PWM\r
- Pwm_Init(ConfigPtr->PwmConfig);\r
-#endif\r
-}\r
-\r
-void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr)\r
-{\r
-#if defined(USE_SPI)\r
- // Setup SPI\r
- Spi_Init(ConfigPtr->SpiConfig);\r
-#endif\r
-\r
-#if defined(USE_EEP)\r
- // Setup EEP\r
- Eep_Init(ConfigPtr->EEpConfig);\r
-#endif\r
-\r
-#if defined(USE_FLS)\r
- // Setup Flash\r
- FlashInit(ConfigPtr->FlashConfig);\r
-#endif\r
-\r
- // Setup NVRAM Manaager\r
- // TODO\r
-\r
- // Setup CAN tranceiver\r
- // TODO\r
-\r
-#if defined(USE_CAN)\r
- // Setup Can driver\r
- Can_Init(ConfigPtr->CanConfig);\r
-#endif\r
-\r
-#if defined(USE_CANIF)\r
- // Setup CanIf\r
- CanIf_Init(ConfigPtr->CanIfConfig);\r
-#endif\r
-\r
-#if defined(USE_CANTP)\r
- // Setup CAN TP\r
- CanTp_Init();\r
-#endif\r
- // Setup LIN\r
- // TODO\r
-\r
-#if defined(USE_PDUR)\r
- // Setup PDU Router\r
- PduR_Init(ConfigPtr->PduRConfig);\r
-#endif\r
-\r
-#if defined(USE_COM)\r
- // Setup COM layer\r
- Com_Init(ConfigPtr->ComConfig);\r
-#endif\r
-\r
-#if defined(USE_DCM)\r
- // Setup DCM\r
- Dcm_Init();\r
-#endif\r
-\r
-#if defined(USE_IOHWAB)\r
- // Setup IO hardware abstraction layer\r
- IoHwAb_Init();\r
-#endif\r
-\r
-}\r
-\r
-void EcuM_AL_DriverInitThree(const EcuM_ConfigType ConfigPtr)\r
-{\r
-#if defined(USE_DEM)\r
- // Setup DEM\r
- Dem_Init();\r
-#endif\r
-\r
-#if defined(USE_CANIF)\r
- // Startup the CAN interafce; due to the missing COM manager\r
- CanIf_InitController(CANIF_CHANNEL_0, CANIF_CHANNEL_0_CONFIG_0);\r
- CanIf_SetControllerMode(CANIF_CHANNEL_0, CANIF_CS_STARTED);\r
-#endif\r
-}\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:43:38 CEST 2010\r
-*/\r
-\r
-\r
-\r
-#include "EcuM.h"\r
-\r
-EcuM_ConfigType EcuMConfig =\r
-{\r
- .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
- .EcuMDefaultShutdownMode = 0, // Don't care\r
- .EcuMDefaultAppMode = 0, // Don't care\r
-\r
-#if defined(USE_MCU)\r
- .McuConfig = McuConfigData,\r
-#endif\r
-#if defined(USE_PORT)\r
- .PortConfig = &PortConfigData,\r
-#endif\r
-#if defined(USE_CAN)\r
- .CanConfig = &CanConfigData,\r
-#endif\r
-#if defined(USE_CANIF)\r
- .CanIfConfig = &CanIf_Config,\r
-#endif\r
-#if defined(USE_COM)\r
- .ComConfig = &ComConfiguration,\r
-#endif\r
-#if defined(USE_PDUR)\r
- .PduRConfig = &PduR_Config,\r
-#endif\r
-#if defined(USE_DMA)\r
- .DmaConfig = DmaConfig,\r
-#endif\r
-#if defined(USE_ADC)\r
- .AdcConfig = AdcConfig,\r
-#endif\r
-#if defined(USE_PWM)\r
- .PwmConfig = &PwmConfig,\r
-#endif\r
-#if defined(USE_GPT)\r
- .GptConfig = GptConfigData,\r
-#endif\r
-};\r
-\r
-void EcuM_OnGoOffTwo( void ) {\r
-\r
-}\r
-\r
-void EcuM_AL_SwitchOff( void ) {\r
-\r
-}\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (ECUM_SW_MAJOR_VERSION != 1) \r
-#error "EcuM: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
-\r
-#define ECUM_VERSION_INFO_API STD_OFF\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-#define ECUM_DEV_ERROR_DETECT STD_OFF\r
-\r
-#include "EcuM_Generated_Types.h"\r
-\r
-extern EcuM_ConfigType EcuMConfig;\r
-\r
-#endif /*ECUM_CFG_H_*/\r
+++ /dev/null
-/* \r
-* Configuration of module EcuM (EcuM_Generated_Types.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:43:38 CEST 2010\r
-*/\r
-\r
-\r
-#if (ECUM_SW_MAJOR_VERSION != 1) \r
-#error "EcuM: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-#ifndef _ECUM_GENERATED_TYPES_H_\r
-#define _ECUM_GENERATED_TYPES_H_\r
-\r
-#if defined(USE_MCU)\r
-#include "Mcu.h"\r
-#endif\r
-#if defined(USE_PORT)\r
-#include "Port.h"\r
-#endif\r
-#if defined(USE_CAN)\r
-#include "Can.h"\r
-#endif\r
-#if defined(USE_CANIF)\r
-#include "CanIf.h"\r
-#endif\r
-#if defined(USE_PWM)\r
-#include "Pwm.h"\r
-#endif\r
-#if defined(USE_COM)\r
-#include "Com.h"\r
-#endif\r
-#if defined(USE_PDUR)\r
-#include "PduR.h"\r
-#endif\r
-#if defined(USE_DMA)\r
-#include "Dma.h"\r
-#endif\r
-#if defined(USE_ADC)\r
-#include "Adc.h"\r
-#endif\r
-#if defined(USE_GPT)\r
-#include "Gpt.h"\r
-#endif\r
-\r
-\r
-typedef struct\r
-{\r
- EcuM_StateType EcuMDefaultShutdownTarget;\r
- uint8 EcuMDefaultShutdownMode;\r
- AppModeType EcuMDefaultAppMode;\r
-\r
-#if defined(USE_MCU)\r
- const Mcu_ConfigType* McuConfig;\r
-#endif\r
-#if defined(USE_PORT)\r
- const Port_ConfigType* PortConfig;\r
-#endif\r
-#if defined(USE_CAN)\r
- const Can_ConfigType* CanConfig;\r
-#endif\r
-#if defined(USE_CANIF)\r
- const CanIf_ConfigType* CanIfConfig;\r
-#endif\r
-#if defined(USE_COM)\r
- const Com_ConfigType* ComConfig;\r
-#endif\r
-#if defined(USE_PDUR)\r
- const PduR_PBConfigType* PduRConfig;\r
-#endif\r
-#if defined(USE_PWM)\r
- const Pwm_ConfigType* PwmConfig;\r
-#endif\r
-#if defined(USE_DMA)\r
- const Dma_ConfigType* DmaConfig;\r
-#endif\r
-#if defined(USE_ADC)\r
- const Adc_ConfigType* AdcConfig;\r
-#endif\r
-#if defined(USE_GPT)\r
- const Gpt_ConfigType* GptConfig;\r
-#endif\r
-} EcuM_ConfigType;\r
-\r
-#endif /*_ECUM_GENERATED_TYPES_H_*/\r
+++ /dev/null
-/* \r
-* Configuration of module Port (Port_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
- \r
-// File generated on Fri Apr 30 15:54:06 CEST 2010\r
-// File generated by com.arccore.bswbuilder.modules.port.mpc5516\r
-\r
-#include "Port.h"\r
-#include "Port_Cfg.h"\r
-#include "stdlib.h"\r
-\r
-const uint16_t PortPadConfigData[] = {\r
- PCR_RESET, /* PCR 0 */\r
- PCR_RESET, /* PCR 1 */\r
- PCR_RESET, /* PCR 2 */\r
- PCR_RESET, /* PCR 3 */\r
- PCR_RESET, /* PCR 4 */\r
- PCR_RESET, /* PCR 5 */\r
- PCR_RESET, /* PCR 6 */\r
- PCR_RESET, /* PCR 7 */\r
- PCR_RESET, /* PCR 8 */\r
- PCR_RESET, /* PCR 9 */\r
- PCR_RESET, /* PCR 10 */\r
- PCR_RESET, /* PCR 11 */\r
- PCR_RESET, /* PCR 12 */\r
- PCR_RESET, /* PCR 13 */\r
- PCR_RESET, /* PCR 14 */\r
- PCR_RESET, /* PCR 15 */\r
- PCR_RESET, /* PCR 16 */\r
- PCR_RESET, /* PCR 17 */\r
- PCR_RESET, /* PCR 18 */\r
- PCR_RESET, /* PCR 19 */\r
- PCR_RESET, /* PCR 20 */\r
- PCR_RESET, /* PCR 21 */\r
- PCR_RESET, /* PCR 22 */\r
- PCR_RESET, /* PCR 23 */\r
- PCR_RESET, /* PCR 24 */\r
- PCR_RESET, /* PCR 25 */\r
- PCR_RESET, /* PCR 26 */\r
- PCR_RESET, /* PCR 27 */\r
- PCR_RESET, /* PCR 28 */\r
- PCR_RESET, /* PCR 29 */\r
- PCR_RESET, /* PCR 30 */\r
- PCR_RESET, /* PCR 31 */\r
- PCR_RESET, /* PCR 32 */\r
- PCR_RESET, /* PCR 33 */\r
- PCR_RESET, /* PCR 34 */\r
- PCR_RESET, /* PCR 35 */\r
- PCR_RESET, /* PCR 36 */\r
- PCR_RESET, /* PCR 37 */\r
- PCR_RESET, /* PCR 38 */\r
- PCR_RESET, /* PCR 39 */\r
- PCR_RESET, /* PCR 40 */\r
- PCR_RESET, /* PCR 41 */\r
- PCR_RESET, /* PCR 42 */\r
- PCR_RESET, /* PCR 43 */\r
- PCR_RESET, /* PCR 44 */\r
- PCR_RESET, /* PCR 45 */\r
- PCR_RESET, /* PCR 46 */\r
- PCR_RESET, /* PCR 47 */\r
- ( FUNC1 | OBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 48 : PORT_PIN_MODE_CAN */\r
- ( FUNC1 | IBE_ENABLE | SLEW_RATE_MIN | PULL_NONE ), /* PCR 49 : PORT_PIN_MODE_CAN */\r
- PCR_RESET, /* PCR 50 */\r
- PCR_RESET, /* PCR 51 */\r
- PCR_RESET, /* PCR 52 */\r
- PCR_RESET, /* PCR 53 */\r
- PCR_RESET, /* PCR 54 */\r
- PCR_RESET, /* PCR 55 */\r
- PCR_RESET, /* PCR 56 */\r
- PCR_RESET, /* PCR 57 */\r
- PCR_RESET, /* PCR 58 */\r
- PCR_RESET, /* PCR 59 */\r
- PCR_RESET, /* PCR 60 */\r
- PCR_RESET, /* PCR 61 */\r
- PCR_RESET, /* PCR 62 */\r
- PCR_RESET, /* PCR 63 */\r
- PCR_RESET, /* PCR 64 */\r
- PCR_RESET, /* PCR 65 */\r
- PCR_RESET, /* PCR 66 */\r
- PCR_RESET, /* PCR 67 */\r
- PCR_RESET, /* PCR 68 */\r
- PCR_RESET, /* PCR 69 */\r
- PCR_RESET, /* PCR 70 */\r
- PCR_RESET, /* PCR 71 */\r
- PCR_RESET, /* PCR 72 */\r
- PCR_RESET, /* PCR 73 */\r
- PCR_RESET, /* PCR 74 */\r
- PCR_RESET, /* PCR 75 */\r
- PCR_RESET, /* PCR 76 */\r
- PCR_RESET, /* PCR 77 */\r
- PCR_RESET, /* PCR 78 */\r
- PCR_RESET, /* PCR 79 */\r
- PCR_RESET, /* PCR 80 */\r
- PCR_RESET, /* PCR 81 */\r
- PCR_RESET, /* PCR 82 */\r
- PCR_RESET, /* PCR 83 */\r
- PCR_RESET, /* PCR 84 */\r
- PCR_RESET, /* PCR 85 */\r
- PCR_RESET, /* PCR 86 */\r
- PCR_RESET, /* PCR 87 */\r
- PCR_RESET, /* PCR 88 */\r
- PCR_RESET, /* PCR 89 */\r
- PCR_RESET, /* PCR 90 */\r
- PCR_RESET, /* PCR 91 */\r
- PCR_RESET, /* PCR 92 */\r
- PCR_RESET, /* PCR 93 */\r
- PCR_RESET, /* PCR 94 */\r
- PCR_RESET, /* PCR 95 */\r
- PCR_RESET, /* PCR 96 */\r
- PCR_RESET, /* PCR 97 */\r
- PCR_RESET, /* PCR 98 */\r
- PCR_RESET, /* PCR 99 */\r
- PCR_RESET, /* PCR 100 */\r
- PCR_RESET, /* PCR 101 */\r
- PCR_RESET, /* PCR 102 */\r
- PCR_RESET, /* PCR 103 */\r
- PCR_RESET, /* PCR 104 */\r
- PCR_RESET, /* PCR 105 */\r
- PCR_RESET, /* PCR 106 */\r
- PCR_RESET, /* PCR 107 */\r
- PCR_RESET, /* PCR 108 */\r
- PCR_RESET, /* PCR 109 */\r
- PCR_RESET, /* PCR 110 */\r
- PCR_RESET, /* PCR 111 */\r
- PCR_RESET, /* PCR 112 */\r
- PCR_RESET, /* PCR 113 */\r
- PCR_RESET, /* PCR 114 */\r
- PCR_RESET, /* PCR 115 */\r
- PCR_RESET, /* PCR 116 */\r
- PCR_RESET, /* PCR 117 */\r
- PCR_RESET, /* PCR 118 */\r
- PCR_RESET, /* PCR 119 */\r
- PCR_RESET, /* PCR 120 */\r
- PCR_RESET, /* PCR 121 */\r
- PCR_RESET, /* PCR 122 */\r
- PCR_RESET, /* PCR 123 */\r
- PCR_RESET, /* PCR 124 */\r
- PCR_RESET, /* PCR 125 */\r
- PCR_RESET, /* PCR 126 */\r
- PCR_RESET, /* PCR 127 */\r
- PCR_RESET, /* PCR 128 */\r
- PCR_RESET, /* PCR 129 */\r
- PCR_RESET, /* PCR 130 */\r
- PCR_RESET, /* PCR 131 */\r
- PCR_RESET, /* PCR 132 */\r
- PCR_RESET, /* PCR 133 */\r
- PCR_RESET, /* PCR 134 */\r
- PCR_RESET, /* PCR 135 */\r
- PCR_RESET, /* PCR 136 */\r
- PCR_RESET, /* PCR 137 */\r
- PCR_RESET, /* PCR 138 */\r
- PCR_RESET, /* PCR 139 */\r
- PCR_RESET, /* PCR 140 */\r
- PCR_RESET, /* PCR 141 */\r
- PCR_RESET, /* PCR 142 */\r
- PCR_RESET, /* PCR 143 */\r
- PCR_RESET, /* PCR 144 */\r
-};\r
-\r
-const uint8_t PortOutConfigData[] = {\r
- GPDO_RESET, /* GPDO 0 */\r
- GPDO_RESET, /* GPDO 1 */\r
- GPDO_RESET, /* GPDO 2 */\r
- GPDO_RESET, /* GPDO 3 */\r
- GPDO_RESET, /* GPDO 4 */\r
- GPDO_RESET, /* GPDO 5 */\r
- GPDO_RESET, /* GPDO 6 */\r
- GPDO_RESET, /* GPDO 7 */\r
- GPDO_RESET, /* GPDO 8 */\r
- GPDO_RESET, /* GPDO 9 */\r
- GPDO_RESET, /* GPDO 10 */\r
- GPDO_RESET, /* GPDO 11 */\r
- GPDO_RESET, /* GPDO 12 */\r
- GPDO_RESET, /* GPDO 13 */\r
- GPDO_RESET, /* GPDO 14 */\r
- GPDO_RESET, /* GPDO 15 */\r
- GPDO_RESET, /* GPDO 16 */\r
- GPDO_RESET, /* GPDO 17 */\r
- GPDO_RESET, /* GPDO 18 */\r
- GPDO_RESET, /* GPDO 19 */\r
- GPDO_RESET, /* GPDO 20 */\r
- GPDO_RESET, /* GPDO 21 */\r
- GPDO_RESET, /* GPDO 22 */\r
- GPDO_RESET, /* GPDO 23 */\r
- GPDO_RESET, /* GPDO 24 */\r
- GPDO_RESET, /* GPDO 25 */\r
- GPDO_RESET, /* GPDO 26 */\r
- GPDO_RESET, /* GPDO 27 */\r
- GPDO_RESET, /* GPDO 28 */\r
- GPDO_RESET, /* GPDO 29 */\r
- GPDO_RESET, /* GPDO 30 */\r
- GPDO_RESET, /* GPDO 31 */\r
- GPDO_RESET, /* GPDO 32 */\r
- GPDO_RESET, /* GPDO 33 */\r
- GPDO_RESET, /* GPDO 34 */\r
- GPDO_RESET, /* GPDO 35 */\r
- GPDO_RESET, /* GPDO 36 */\r
- GPDO_RESET, /* GPDO 37 */\r
- GPDO_RESET, /* GPDO 38 */\r
- GPDO_RESET, /* GPDO 39 */\r
- GPDO_RESET, /* GPDO 40 */\r
- GPDO_RESET, /* GPDO 41 */\r
- GPDO_RESET, /* GPDO 42 */\r
- GPDO_RESET, /* GPDO 43 */\r
- GPDO_RESET, /* GPDO 44 */\r
- GPDO_RESET, /* GPDO 45 */\r
- GPDO_RESET, /* GPDO 46 */\r
- GPDO_RESET, /* GPDO 47 */\r
- GPDO_RESET, /* GPDO 48 */\r
- GPDO_RESET, /* GPDO 49 */\r
- GPDO_RESET, /* GPDO 50 */\r
- GPDO_RESET, /* GPDO 51 */\r
- GPDO_RESET, /* GPDO 52 */\r
- GPDO_RESET, /* GPDO 53 */\r
- GPDO_RESET, /* GPDO 54 */\r
- GPDO_RESET, /* GPDO 55 */\r
- GPDO_RESET, /* GPDO 56 */\r
- GPDO_RESET, /* GPDO 57 */\r
- GPDO_RESET, /* GPDO 58 */\r
- GPDO_RESET, /* GPDO 59 */\r
- GPDO_RESET, /* GPDO 60 */\r
- GPDO_RESET, /* GPDO 61 */\r
- GPDO_RESET, /* GPDO 62 */\r
- GPDO_RESET, /* GPDO 63 */\r
- GPDO_RESET, /* GPDO 64 */\r
- GPDO_RESET, /* GPDO 65 */\r
- GPDO_RESET, /* GPDO 66 */\r
- GPDO_RESET, /* GPDO 67 */\r
- GPDO_RESET, /* GPDO 68 */\r
- GPDO_RESET, /* GPDO 69 */\r
- GPDO_RESET, /* GPDO 70 */\r
- GPDO_RESET, /* GPDO 71 */\r
- GPDO_RESET, /* GPDO 72 */\r
- GPDO_RESET, /* GPDO 73 */\r
- GPDO_RESET, /* GPDO 74 */\r
- GPDO_RESET, /* GPDO 75 */\r
- GPDO_RESET, /* GPDO 76 */\r
- GPDO_RESET, /* GPDO 77 */\r
- GPDO_RESET, /* GPDO 78 */\r
- GPDO_RESET, /* GPDO 79 */\r
- GPDO_RESET, /* GPDO 80 */\r
- GPDO_RESET, /* GPDO 81 */\r
- GPDO_RESET, /* GPDO 82 */\r
- GPDO_RESET, /* GPDO 83 */\r
- GPDO_RESET, /* GPDO 84 */\r
- GPDO_RESET, /* GPDO 85 */\r
- GPDO_RESET, /* GPDO 86 */\r
- GPDO_RESET, /* GPDO 87 */\r
- GPDO_RESET, /* GPDO 88 */\r
- GPDO_RESET, /* GPDO 89 */\r
- GPDO_RESET, /* GPDO 90 */\r
- GPDO_RESET, /* GPDO 91 */\r
- GPDO_RESET, /* GPDO 92 */\r
- GPDO_RESET, /* GPDO 93 */\r
- GPDO_RESET, /* GPDO 94 */\r
- GPDO_RESET, /* GPDO 95 */\r
- GPDO_RESET, /* GPDO 96 */\r
- GPDO_RESET, /* GPDO 97 */\r
- GPDO_RESET, /* GPDO 98 */\r
- GPDO_RESET, /* GPDO 99 */\r
- GPDO_RESET, /* GPDO 100 */\r
- GPDO_RESET, /* GPDO 101 */\r
- GPDO_RESET, /* GPDO 102 */\r
- GPDO_RESET, /* GPDO 103 */\r
- GPDO_RESET, /* GPDO 104 */\r
- GPDO_RESET, /* GPDO 105 */\r
- GPDO_RESET, /* GPDO 106 */\r
- GPDO_RESET, /* GPDO 107 */\r
- GPDO_RESET, /* GPDO 108 */\r
- GPDO_RESET, /* GPDO 109 */\r
- GPDO_RESET, /* GPDO 110 */\r
- GPDO_RESET, /* GPDO 111 */\r
- GPDO_RESET, /* GPDO 112 */\r
- GPDO_RESET, /* GPDO 113 */\r
- GPDO_RESET, /* GPDO 114 */\r
- GPDO_RESET, /* GPDO 115 */\r
- GPDO_RESET, /* GPDO 116 */\r
- GPDO_RESET, /* GPDO 117 */\r
- GPDO_RESET, /* GPDO 118 */\r
- GPDO_RESET, /* GPDO 119 */\r
- GPDO_RESET, /* GPDO 120 */\r
- GPDO_RESET, /* GPDO 121 */\r
- GPDO_RESET, /* GPDO 122 */\r
- GPDO_RESET, /* GPDO 123 */\r
- GPDO_RESET, /* GPDO 124 */\r
- GPDO_RESET, /* GPDO 125 */\r
- GPDO_RESET, /* GPDO 126 */\r
- GPDO_RESET, /* GPDO 127 */\r
- GPDO_RESET, /* GPDO 128 */\r
- GPDO_RESET, /* GPDO 129 */\r
- GPDO_RESET, /* GPDO 130 */\r
- GPDO_RESET, /* GPDO 131 */\r
- GPDO_RESET, /* GPDO 132 */\r
- GPDO_RESET, /* GPDO 133 */\r
- GPDO_RESET, /* GPDO 134 */\r
- GPDO_RESET, /* GPDO 135 */\r
- GPDO_RESET, /* GPDO 136 */\r
- GPDO_RESET, /* GPDO 137 */\r
- GPDO_RESET, /* GPDO 138 */\r
- GPDO_RESET, /* GPDO 139 */\r
- GPDO_RESET, /* GPDO 140 */\r
- GPDO_RESET, /* GPDO 141 */\r
- GPDO_RESET, /* GPDO 142 */\r
-};\r
-\r
-const Port_ConfigType PortConfigData =\r
-{\r
- .padCnt = sizeof(PortPadConfigData),\r
- .padConfig = PortPadConfigData,\r
- .outCnt = sizeof(PortOutConfigData),\r
- .outConfig = PortOutConfigData,\r
-};\r
+++ /dev/null
-/* \r
-* Configuration of module Port (Port_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (PORT_SW_MAJOR_VERSION != 1) \r
-#error "Port: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-#ifndef PORT_CFG_H_\r
-#define PORT_CFG_H_\r
-\r
-#include "Std_Types.h"\r
-\r
-#define PORT_VERSION_INFO_API STD_OFF\r
-#define PORT_DEV_ERROR_DETECT STD_OFF\r
-#define PORT_PIN_DIRECTION_CHANGES_ALLOWED STD_OFF\r
-\r
-#define BIT0 (1<<15)\r
-#define BIT1 (1<<14)\r
-#define BIT2 (1<<13)\r
-#define BIT3 (1<<12)\r
-#define BIT4 (1<<11)\r
-#define BIT5 (1<<10)\r
-#define BIT6 (1<<9)\r
-#define BIT7 (1<<8)\r
-#define BIT8 (1<<7)\r
-#define BIT9 (1<<6)\r
-#define BIT10 (1<<5)\r
-#define BIT11 (1<<4)\r
-#define BIT12 (1<<3)\r
-#define BIT13 (1<<2)\r
-#define BIT14 (1<<1)\r
-#define BIT15 (1<<0)\r
-\r
-#define WPE_BIT BIT14\r
-#define WPS_BIT BIT15\r
-#define SRC0 BIT12\r
-#define SRC1 BIT13\r
-\r
-#define PULL_UP (WPE_BIT|WPS_BIT)\r
-#define PULL_DOWN (WPE_BIT)\r
-#define PULL_NONE 0\r
-#define SLEW_RATE_MIN 0\r
-#define SLEW_RATE_MED BIT13\r
-#define SLEW_RATE_MAX (BIT12|BIT13)\r
-#define HYS_ENABLE BIT11\r
-#define ODE_ENABLE BIT10\r
-#define IBE_ENABLE BIT7\r
-#define OBE_ENABLE BIT6\r
-#define IO (0)\r
-#define FUNC0 (0)\r
-#define FUNC1 (BIT5)\r
-#define FUNC2 (BIT4)\r
-#define FUNC3 (BIT4|BIT5)\r
-#define FUNC4 (BIT3)\r
-\r
-#define PCR_RESET (0)\r
-#define GPDO_RESET (0)\r
-\r
-#define GPDO_HIGH (1)\r
-\r
-\r
-typedef uint16 Port_PinType;\r
-\r
-typedef struct\r
-{\r
- uint16_t padCnt;\r
- const uint16_t *padConfig;\r
- uint16_t outCnt;\r
- const uint8_t *outConfig;\r
-// uint16_t inCnt;\r
-// const uint8_t *inConfig;\r
-} Port_ConfigType;\r
-\r
-extern const Port_ConfigType PortConfigData;\r
-\r
-#endif /* PORT_CFG_H_ */\r
--- /dev/null
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+\r
+ \r
+#include "CanIf.h"\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#include "CanTp_Cbk.h"\r
+#endif\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm_Cbk.h"\r
+#endif\r
+#include <stdlib.h>\r
+\r
+\r
+// Imported structs from Can_Lcfg.c\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType CanConfigSetData;\r
+\r
+\r
+\r
+// Contains the mapping from CanIf-specific Channels to Can Controllers\r
+const CanControllerIdType CanIf_Arc_ChannelToControllerMap[CANIF_CHANNEL_CNT] = {\r
+ FLEXCAN_A, // CHANNEL_0\r
+};\r
+\r
+const uint8 CanIf_Arc_ChannelDefaultConfIndex[CANIF_CHANNEL_CNT] = {\r
+ CANIF_CHANNEL_0_CONFIG_0,\r
+};\r
+\r
+// Container that gets slamed into CanIf_InitController()\r
+// Inits ALL controllers\r
+// Multiplicity 1..*\r
+const CanIf_ControllerConfigType CanIfControllerConfig[] = {\r
+ // This is the ConfigurationIndex in CanIf_InitController()\r
+ \r
+ \r
+ { \r
+ .WakeupSupport = CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ .CanIfControllerIdRef = CANIF_CHANNEL_0,\r
+ .CanIfDriverNameRef = "FLEXCAN", // Not used\r
+ .CanIfInitControllerRef = &CanControllerConfigData[0],\r
+ },\r
+ \r
+};\r
+\r
+// Function callbacks for higher layers\r
+const CanIf_DispatchConfigType CanIfDispatchConfig =\r
+{\r
+ .CanIfBusOffNotification = NULL,\r
+ .CanIfWakeUpNotification = NULL, // Not used\r
+ .CanIfWakeupValidNotification = NULL, // Not used\r
+ .CanIfErrorNotificaton = NULL,\r
+};\r
+\r
+\r
+// Data for init configuration CanIfInitConfiguration\r
+\r
+ \r
+\r
+const CanIf_HthConfigType CanIfHthConfigData_Hoh_1[] =\r
+{\r
+ \r
+ { \r
+ .CanIfHthType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIfCanControllerIdRef = CANIF_CHANNEL_0,\r
+ .CanIfHthIdSymRef = HWObj_1,\r
+ .CanIf_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+const CanIf_HrhConfigType CanIfHrhConfigData_Hoh_1[] =\r
+{\r
+};\r
+\r
+\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] = { \r
+ \r
+ {\r
+ .CanConfigSet = &CanConfigSetData,\r
+ .CanIfHrhConfig = CanIfHrhConfigData_Hoh_1,\r
+ .CanIfHthConfig = CanIfHthConfigData_Hoh_1,\r
+ .CanIf_Arc_EOL = 1,\r
+ },\r
+};\r
+ \r
+const CanIf_TxPduConfigType CanIfTxPduConfigData[] = { \r
+ {\r
+ .CanIfTxPduId = PDUR_SOURCE_PDU_ID_LedCommandTx,\r
+ .CanIfCanTxPduIdCanId = 291,\r
+ .CanIfCanTxPduIdDlc = 8,\r
+ .CanIfCanTxPduType = CANIF_PDU_TYPE_STATIC,\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ .CanIfReadTxPduNotifyStatus = true, \r
+#endif\r
+ .CanIfTxPduIdCanIdType = CANIF_CAN_ID_TYPE_29,\r
+ .CanIfUserTxConfirmation = PduR_CanIfTxConfirmation,\r
+ .CanIfCanTxPduHthRef = &CanIfHthConfigData_Hoh_1[0],\r
+ .PduIdRef = NULL,\r
+ }, \r
+};\r
+\r
+const CanIf_RxPduConfigType CanIfRxPduConfigData[] = { \r
+};\r
+\r
+// This container contains the init parameters of the CAN\r
+// Multiplicity 1..*\r
+const CanIf_InitConfigType CanIfInitConfig =\r
+{\r
+ .CanIfConfigSet = 0, // Not used\r
+ .CanIfNumberOfCanRxPduIds = sizeof(CanIfRxPduConfigData)/sizeof(CanIf_RxPduConfigType),\r
+ .CanIfNumberOfCanTXPduIds = sizeof(CanIfTxPduConfigData)/sizeof(CanIf_TxPduConfigType),\r
+ .CanIfNumberOfDynamicCanTXPduIds = 0, // Not used\r
+\r
+ // Containers\r
+ .CanIfHohConfigPtr = CanIfHohConfigData,\r
+ .CanIfRxPduConfigPtr = CanIfRxPduConfigData,\r
+ .CanIfTxPduConfigPtr = CanIfTxPduConfigData,\r
+};\r
+\r
+ // This container includes all necessary configuration sub-containers\r
+// according the CAN Interface configuration structure.\r
+CanIf_ConfigType CanIf_Config =\r
+{\r
+ .ControllerConfig = CanIfControllerConfig,\r
+ .DispatchConfig = &CanIfDispatchConfig,\r
+ .InitConfig = &CanIfInitConfig,\r
+ .TransceiverConfig = NULL, // Not used\r
+ .Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap, \r
+ .Arc_ChannelDefaultConfIndex = CanIf_Arc_ChannelDefaultConfIndex,\r
+};\r
+\r
-/* \r
-* Configuration of module CanIf (CanIf_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (CANIF_SW_MAJOR_VERSION != 1 && CANIF_SW_MINOR_VERSION != 1) \r
-#error "CanIf: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
\r
+
+#if !(((CANIF_SW_MAJOR_VERSION == 1) && (CANIF_SW_MINOR_VERSION == 1)) )
+#error "CanIf: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef CANIF_CFG_H_\r
#define CANIF_CFG_H_\r
CANIF_CHANNEL_CNT\r
} CanIf_Arc_ChannelIdType;\r
\r
+#define CANIF_CONTROLLER_ID_Controller_1 CANIF_CHANNEL_0\r
+\r
typedef enum {\r
CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
- CANIF_SOFTFILTER_TYPE_MASK, // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+ CANIF_SOFTFILTER_TYPE_MASK // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
} CanIf_SoftwareFilterTypeType;\r
\r
typedef enum {\r
CANIF_USER_TYPE_CAN_NM,\r
CANIF_USER_TYPE_CAN_TP,\r
CANIF_USER_TYPE_CAN_PDUR,\r
- CANIF_USER_TYPE_CAN_SPECIAL,\r
+ CANIF_USER_TYPE_CAN_SPECIAL\r
} CanIf_UserTypeType;\r
\r
\r
#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
\r
-//-------------------------------------------------------------------\r
-\r
-typedef struct {\r
- void (*CancelTxConfirmation)( void *); // (const Can_PduType *);\r
- void (*RxIndication)(void *); //(const Can_PduType *);\r
- void (*ControllerBusOff)(uint8);\r
- void (*ControllerWakeup)(uint8);\r
- void (*Arc_Error)(uint8,uint32);\r
-} CanIf_CallbackType;\r
-\r
-\r
-\r
//-------------------------------------------------------------------\r
/*\r
* CanIfHrhRangeConfig container\r
typedef enum {\r
CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
- CANIF_WAKEUP_SUPPORT_TRANSCEIVER,\r
+ CANIF_WAKEUP_SUPPORT_TRANSCEIVER\r
} CanIf_WakeupSupportType;\r
\r
\r
// CanIf-specific id of the controller\r
CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
\r
- const char CanIfDriverNameRef[8]; // Not used\r
+ const uint8 CanIfDriverNameRef[8]; // Not used\r
\r
const Can_ControllerConfigType *CanIfInitControllerRef;\r
} CanIf_ControllerConfigType;\r
\r
// ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers\r
const CanControllerIdType *Arc_ChannelToControllerMap;\r
+ \r
+ const uint8 *Arc_ChannelDefaultConfIndex;\r
} CanIf_ConfigType;\r
\r
\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((CAN_SW_MAJOR_VERSION == 1) && (CAN_SW_MINOR_VERSION == 0)) )
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+ \r
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF // Not supported\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+typedef enum {\r
+ FLEXCAN_A = 0,\r
+ CAN_CTRL_A = 0,\r
+ FLEXCAN_B = 1,\r
+ CAN_CTRL_B = 1,\r
+ FLEXCAN_C = 2,\r
+ CAN_CTRL_C = 2,\r
+ FLEXCAN_D = 3,\r
+ CAN_CTRL_D = 3,\r
+ FLEXCAN_E = 4,\r
+ CAN_CTRL_E = 4,\r
+ FLEXCAN_F = 5,\r
+ CAN_CTRL_F = 5,\r
+ CAN_CONTROLLER_CNT = 6\r
+}CanControllerIdType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD\r
+} Can_IdTypeType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_1,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ uint8 CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+typedef uint32 Can_FilterMaskType;\r
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask; \r
+ \r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING\r
+} Can_Arc_ProcessType;\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
-/* \r
-* Configuration of module Can (Can_Lcfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Can (Can_Lcfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
\r
\r
\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef COM_CFG_H\r
+#define COM_CFG_H\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+//#define COM_DEV_ERROR_DETECT\r
+\r
+#define COM_N_IPDUS 1\r
+#define COM_N_SIGNALS 1\r
+#define COM_N_GROUP_SIGNALS 0\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
+\r
+#define ComConfigurationTimeBase 0.0\r
+#define ComVersionInfoApi\r
+\r
+#endif /*COM_CFG_H*/\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
+#include <stdlib.h>\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Signal init values.\r
+ */\r
+const uint16 Com_SignalInitValue_SetLedLevelTx = 0;\r
+ \r
+\r
+/*\r
+ * Group signal definitions\r
+ */\r
+const ComGroupSignal_type ComGroupSignal[] = {\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/* SignalGroup GroupSignals lists. */\r
+\r
+/*\r
+ * Signal definitions\r
+ */\r
+const ComSignal_type ComSignal[] = {\r
+ {\r
+ .ComHandleId = SetLedLevelTx,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_SetLedLevelTx,\r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 16,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT16,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU group definitions\r
+ */\r
+const ComIPduGroup_type ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = TxGroup,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+/* IPdu signal lists. */\r
+const ComSignal_type * const ComIPduSignalRefs_LedCommandTx[] = {\r
+ &ComSignal[ SetLedLevelTx ], \r
+ NULL,\r
+};\r
+\r
+/*\r
+ * I-PDU definitions\r
+ */\r
+const ComIPdu_type ComIPdu[] = { \r
+ \r
+ { // LedCommandTx\r
+ .ArcIPduOutgoingId = PDUR_DEST_PDU_ID_LedCommandTx,\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = TxGroup,\r
+ \r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduSignalRef = ComIPduSignalRefs_LedCommandTx,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+const Com_ConfigType ComConfiguration = {\r
+ .ComConfigurationId = 1,\r
+ .ComIPdu = ComIPdu,\r
+ .ComIPduGroup = ComIPduGroup,\r
+ .ComSignal = ComSignal,\r
+ .ComGroupSignal = ComGroupSignal\r
+};\r
+\r
+/* IPdu buffers and signal group buffers */\r
+uint8 ComArcIPduBuffer_LedCommandTx[8];\r
+ \r
+\r
+Com_Arc_IPdu_type Com_Arc_IPdu[] = {\r
+ { // LedCommandTx\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ },\r
+ .ComIPduDataPtr = ComArcIPduBuffer_LedCommandTx,\r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+};\r
+\r
+Com_Arc_Signal_type Com_Arc_Signal[] = {\r
+ { // SetLedLevelTx\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComTimeoutFactor = 0,\r
+ .ComIPduHandleId = 0,\r
+ .ComSignalUpdated = 0,\r
+ .ComIPduDataPtr = NULL,\r
+ \r
+ .Com_Arc_ShadowBuffer = NULL\r
+ \r
+ },\r
+ \r
+};\r
+\r
+Com_Arc_GroupSignal_type Com_Arc_GroupSignal[COM_N_GROUP_SIGNALS];\r
+\r
+uint8 outgoingSduPtr[8];\r
+\r
+Com_Arc_Config_type Com_Arc_Config = {\r
+ .ComIPdu = Com_Arc_IPdu,\r
+ .ComSignal = Com_Arc_Signal,\r
+ .ComGroupSignal = Com_Arc_GroupSignal,\r
+ .OutgoingPdu = {\r
+ .SduDataPtr = outgoingSduPtr,\r
+ .SduLength = 0\r
+ }\r
+};\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
+#ifndef COM_PBCFG_H\r
+#define COM_PBCFG_H\r
+\r
+#include "Com_Types.h"\r
+\r
+extern const Com_ConfigType ComConfiguration;\r
+\r
+// COM Polite Defines.\r
+#define COM_PDU_ID_LedCommandTx 0\r
+\r
+\r
+\r
+// PDU group definitions\r
+#define TxGroup 0\r
+\r
+\r
+// Signal definitions\r
+#define SetLedLevelTx 0\r
+\r
+\r
+\r
+\r
+#endif /* COM_PBCFG_H */\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
\r
// ################################## ALARMS ################################\r
-GEN_ALARM_AUTOSTART(ALARM_ID_ComAlarm, ALARM_AUTOSTART_ABSOLUTE, 5, 20, OSDEFAULTAPPMODE );\r
+GEN_ALARM_AUTOSTART(ALARM_ID_ComAlarm, ALARM_AUTOSTART_RELATIVE, 5, 20, OSDEFAULTAPPMODE );\r
\r
-GEN_ALARM_AUTOSTART(ALARM_ID_ReadSwAlarm, ALARM_AUTOSTART_ABSOLUTE, 10, 30, OSDEFAULTAPPMODE );\r
+GEN_ALARM_AUTOSTART(ALARM_ID_ReadSwAlarm, ALARM_AUTOSTART_RELATIVE, 10, 30, OSDEFAULTAPPMODE );\r
\r
\r
GEN_ALARM_HEAD {\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
--- /dev/null
+/*\r
+ * Configuration of module PduR (PduR_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef PDUR_CFG_H_\r
+#define PDUR_CFG_H_\r
+\r
+// Module support\r
+#define PDUR_CANIF_SUPPORT STD_ON\r
+#define PDUR_CANTP_SUPPORT STD_OFF\r
+#define PDUR_FRIF_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_FRTP_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_LINIF_SUPPORT STD_OFF\r
+#define PDUR_LINTP_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_COM_SUPPORT STD_ON\r
+#define PDUR_DCM_SUPPORT STD_OFF\r
+#define PDUR_IPDUM_SUPPORT STD_OFF /* Not supported */\r
+\r
+\r
+#define PDUR_DEV_ERROR_DETECT STD_OFF\r
+#define PDUR_VERSION_INFO_API STD_OFF\r
+\r
+\r
+// Zero cost operation mode\r
+#define PDUR_ZERO_COST_OPERATION STD_ON\r
+#define PDUR_SINGLE_IF CAN_IF\r
+#define PDUR_SINGLE_TP CAN_TP\r
+\r
+\r
+// Gateway operation\r
+#define PDUR_GATEWAY_OPERATION STD_OFF\r
+#define PDUR_MEMORY_SIZE 10 /* Not used */\r
+#define PDUR_SB_TX_BUFFER_SUPPORT STD_OFF\r
+#define PDUR_FIFO_TX_BUFFER_SUPPORT STD_OFF\r
+\r
+/**\r
+ * The maximum numbers of Tx buffers.\r
+ */\r
+#define PDUR_MAX_TX_BUFFER_NUMBER 10 /* Not used */\r
+\r
+\r
+\r
+\r
+\r
+// Multicast\r
+/* Not supported\r
+#define PDUR_MULTICAST_TOIF_SUPPORT STD_OFF\r
+#define PDUR_MULTICAST_FROMIF_SUPPORT STD_OFF\r
+#define PDUR_MULTICAST_TOTP_SUPPORT STD_OFF\r
+#define PDUR_MULTICAST_FROMTP_SUPPORT STD_OFF\r
+*/\r
+\r
+\r
+// Minimum routing\r
+/* Minimum routing not supported.\r
+#define PDUR_MINIMUM_ROUTING_UP_MODULE COM\r
+#define PDUR_MINIMUM_ROUTING_LO_MODULE CAN_IF\r
+#define PDUR_MINIMUM_ROUTING_UP_RXPDUID ((PduIdType)100)\r
+#define PDUR_MINIMUM_ROUTING_LO_RXPDUID ((PduIdType)255)\r
+#define PDUR_MINIMUM_ROUTING_UP_TXPDUID ((PduIdType)255)\r
+#define PDUR_MINIMUM_ROUTING_LO_TXPDUID ((PduIdType)255)\r
+*/\r
+\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+\r
+#include "PduR.h"\r
+#include "PduR_Cfg.h"\r
+#include "PduR_PbCfg.h"\r
+\r
+#if PDUR_CANIF_SUPPORT == STD_ON\r
+#include "CanIf.h"\r
+#endif\r
+#if PDUR_CANTP_SUPPORT == STD_ON\r
+#include "CanTp.h"\r
+#endif\r
+#if PDUR_LINIF_SUPPORT == STD_ON\r
+#include "LinIf.h"\r
+#endif\r
+#if PDUR_COM_SUPPORT == STD_ON\r
+#include "Com.h"\r
+#endif\r
+#if PDUR_DCM_SUPPORT == STD_ON\r
+#include "Dcm.h"\r
+#endif\r
+\r
+\r
+PduRTxBufferTable_type PduRTxBufferTable = {\r
+ .PduRMaxTxBufferNumber = 1,\r
+ .PduRTxBuffer = {\r
+ {\r
+ .Depth = 0,\r
+ },\r
+ }\r
+};\r
+\r
+\r
+PduRRoutingTable_type PduRRoutingTable = {\r
+ .PduRRoutingPath = {\r
+ { // End of routing table\r
+ .PduR_Arc_EOL = 1\r
+ }\r
+ }\r
+};\r
+\r
+\r
+\r
+\r
+PduR_PBConfigType PduR_Config = {\r
+ .PduRConfigurationId = 0,\r
+ .PduRTxBufferTable = &PduRTxBufferTable,\r
+ .PduRRoutingTable = &PduRRoutingTable,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
+\r
+#if defined(USE_DCM)\r
+#include "Dcm.h"\r
+#endif\r
+#if defined(USE_COM)\r
+#include "Com.h"\r
+#endif\r
+#if defined(USE_CANIF)\r
+#include "CanIf.h"\r
+#endif\r
+#if defined(USE_CANTP)\r
+#include "CanTp.h"\r
+#endif\r
+\r
+extern PduR_PBConfigType PduR_Config;\r
+\r
+// PduR Polite Defines.\r
+\r
+#define PDUR_SOURCE_PDU_ID_LedCommandTx COM_PDU_ID_LedCommandTx\r
+#define PDUR_DEST_PDU_ID_LedCommandTx CANIF_PDU_ID_LedCommandTx\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+ \r
+// File generated on Mon Jan 17 12:24:21 CET 2011\r
+// File generated by com.arccore.bswbuilder.modules.port.mpc5516\r
+\r
+#include "Port.h"\r
+#include "Port_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PORT_PCR_RESET, /* PCR 0 */\r
+ PORT_PCR_RESET, /* PCR 1 */\r
+ PORT_PCR_RESET, /* PCR 2 */\r
+ PORT_PCR_RESET, /* PCR 3 */\r
+ PORT_PCR_RESET, /* PCR 4 */\r
+ PORT_PCR_RESET, /* PCR 5 */\r
+ PORT_PCR_RESET, /* PCR 6 */\r
+ PORT_PCR_RESET, /* PCR 7 */\r
+ PORT_PCR_RESET, /* PCR 8 */\r
+ PORT_PCR_RESET, /* PCR 9 */\r
+ PORT_PCR_RESET, /* PCR 10 */\r
+ PORT_PCR_RESET, /* PCR 11 */\r
+ PORT_PCR_RESET, /* PCR 12 */\r
+ PORT_PCR_RESET, /* PCR 13 */\r
+ PORT_PCR_RESET, /* PCR 14 */\r
+ PORT_PCR_RESET, /* PCR 15 */\r
+ PORT_PCR_RESET, /* PCR 16 */\r
+ PORT_PCR_RESET, /* PCR 17 */\r
+ PORT_PCR_RESET, /* PCR 18 */\r
+ PORT_PCR_RESET, /* PCR 19 */\r
+ PORT_PCR_RESET, /* PCR 20 */\r
+ PORT_PCR_RESET, /* PCR 21 */\r
+ PORT_PCR_RESET, /* PCR 22 */\r
+ PORT_PCR_RESET, /* PCR 23 */\r
+ PORT_PCR_RESET, /* PCR 24 */\r
+ PORT_PCR_RESET, /* PCR 25 */\r
+ PORT_PCR_RESET, /* PCR 26 */\r
+ PORT_PCR_RESET, /* PCR 27 */\r
+ PORT_PCR_RESET, /* PCR 28 */\r
+ PORT_PCR_RESET, /* PCR 29 */\r
+ PORT_PCR_RESET, /* PCR 30 */\r
+ PORT_PCR_RESET, /* PCR 31 */\r
+ PORT_PCR_RESET, /* PCR 32 */\r
+ PORT_PCR_RESET, /* PCR 33 */\r
+ PORT_PCR_RESET, /* PCR 34 */\r
+ PORT_PCR_RESET, /* PCR 35 */\r
+ PORT_PCR_RESET, /* PCR 36 */\r
+ PORT_PCR_RESET, /* PCR 37 */\r
+ PORT_PCR_RESET, /* PCR 38 */\r
+ PORT_PCR_RESET, /* PCR 39 */\r
+ PORT_PCR_RESET, /* PCR 40 */\r
+ PORT_PCR_RESET, /* PCR 41 */\r
+ PORT_PCR_RESET, /* PCR 42 */\r
+ PORT_PCR_RESET, /* PCR 43 */\r
+ PORT_PCR_RESET, /* PCR 44 */\r
+ PORT_PCR_RESET, /* PCR 45 */\r
+ PORT_PCR_RESET, /* PCR 46 */\r
+ PORT_PCR_RESET, /* PCR 47 */\r
+ ( PORT_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 48 : PORT_PIN_MODE_CAN */\r
+ ( PORT_FUNC1 | PORT_IBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 49 : PORT_PIN_MODE_CAN */\r
+ PORT_PCR_RESET, /* PCR 50 */\r
+ PORT_PCR_RESET, /* PCR 51 */\r
+ PORT_PCR_RESET, /* PCR 52 */\r
+ PORT_PCR_RESET, /* PCR 53 */\r
+ PORT_PCR_RESET, /* PCR 54 */\r
+ PORT_PCR_RESET, /* PCR 55 */\r
+ PORT_PCR_RESET, /* PCR 56 */\r
+ PORT_PCR_RESET, /* PCR 57 */\r
+ PORT_PCR_RESET, /* PCR 58 */\r
+ PORT_PCR_RESET, /* PCR 59 */\r
+ PORT_PCR_RESET, /* PCR 60 */\r
+ PORT_PCR_RESET, /* PCR 61 */\r
+ PORT_PCR_RESET, /* PCR 62 */\r
+ PORT_PCR_RESET, /* PCR 63 */\r
+ PORT_PCR_RESET, /* PCR 64 */\r
+ PORT_PCR_RESET, /* PCR 65 */\r
+ PORT_PCR_RESET, /* PCR 66 */\r
+ PORT_PCR_RESET, /* PCR 67 */\r
+ PORT_PCR_RESET, /* PCR 68 */\r
+ PORT_PCR_RESET, /* PCR 69 */\r
+ PORT_PCR_RESET, /* PCR 70 */\r
+ PORT_PCR_RESET, /* PCR 71 */\r
+ PORT_PCR_RESET, /* PCR 72 */\r
+ PORT_PCR_RESET, /* PCR 73 */\r
+ PORT_PCR_RESET, /* PCR 74 */\r
+ PORT_PCR_RESET, /* PCR 75 */\r
+ PORT_PCR_RESET, /* PCR 76 */\r
+ PORT_PCR_RESET, /* PCR 77 */\r
+ PORT_PCR_RESET, /* PCR 78 */\r
+ PORT_PCR_RESET, /* PCR 79 */\r
+ PORT_PCR_RESET, /* PCR 80 */\r
+ PORT_PCR_RESET, /* PCR 81 */\r
+ PORT_PCR_RESET, /* PCR 82 */\r
+ PORT_PCR_RESET, /* PCR 83 */\r
+ PORT_PCR_RESET, /* PCR 84 */\r
+ PORT_PCR_RESET, /* PCR 85 */\r
+ PORT_PCR_RESET, /* PCR 86 */\r
+ PORT_PCR_RESET, /* PCR 87 */\r
+ PORT_PCR_RESET, /* PCR 88 */\r
+ PORT_PCR_RESET, /* PCR 89 */\r
+ PORT_PCR_RESET, /* PCR 90 */\r
+ PORT_PCR_RESET, /* PCR 91 */\r
+ PORT_PCR_RESET, /* PCR 92 */\r
+ PORT_PCR_RESET, /* PCR 93 */\r
+ PORT_PCR_RESET, /* PCR 94 */\r
+ PORT_PCR_RESET, /* PCR 95 */\r
+ PORT_PCR_RESET, /* PCR 96 */\r
+ PORT_PCR_RESET, /* PCR 97 */\r
+ PORT_PCR_RESET, /* PCR 98 */\r
+ PORT_PCR_RESET, /* PCR 99 */\r
+ PORT_PCR_RESET, /* PCR 100 */\r
+ PORT_PCR_RESET, /* PCR 101 */\r
+ PORT_PCR_RESET, /* PCR 102 */\r
+ PORT_PCR_RESET, /* PCR 103 */\r
+ PORT_PCR_RESET, /* PCR 104 */\r
+ PORT_PCR_RESET, /* PCR 105 */\r
+ PORT_PCR_RESET, /* PCR 106 */\r
+ PORT_PCR_RESET, /* PCR 107 */\r
+ PORT_PCR_RESET, /* PCR 108 */\r
+ PORT_PCR_RESET, /* PCR 109 */\r
+ PORT_PCR_RESET, /* PCR 110 */\r
+ PORT_PCR_RESET, /* PCR 111 */\r
+ PORT_PCR_RESET, /* PCR 112 */\r
+ PORT_PCR_RESET, /* PCR 113 */\r
+ PORT_PCR_RESET, /* PCR 114 */\r
+ PORT_PCR_RESET, /* PCR 115 */\r
+ PORT_PCR_RESET, /* PCR 116 */\r
+ PORT_PCR_RESET, /* PCR 117 */\r
+ PORT_PCR_RESET, /* PCR 118 */\r
+ PORT_PCR_RESET, /* PCR 119 */\r
+ PORT_PCR_RESET, /* PCR 120 */\r
+ PORT_PCR_RESET, /* PCR 121 */\r
+ PORT_PCR_RESET, /* PCR 122 */\r
+ PORT_PCR_RESET, /* PCR 123 */\r
+ PORT_PCR_RESET, /* PCR 124 */\r
+ PORT_PCR_RESET, /* PCR 125 */\r
+ PORT_PCR_RESET, /* PCR 126 */\r
+ PORT_PCR_RESET, /* PCR 127 */\r
+ PORT_PCR_RESET, /* PCR 128 */\r
+ PORT_PCR_RESET, /* PCR 129 */\r
+ PORT_PCR_RESET, /* PCR 130 */\r
+ PORT_PCR_RESET, /* PCR 131 */\r
+ PORT_PCR_RESET, /* PCR 132 */\r
+ PORT_PCR_RESET, /* PCR 133 */\r
+ PORT_PCR_RESET, /* PCR 134 */\r
+ PORT_PCR_RESET, /* PCR 135 */\r
+ PORT_PCR_RESET, /* PCR 136 */\r
+ PORT_PCR_RESET, /* PCR 137 */\r
+ PORT_PCR_RESET, /* PCR 138 */\r
+ PORT_PCR_RESET, /* PCR 139 */\r
+ PORT_PCR_RESET, /* PCR 140 */\r
+ PORT_PCR_RESET, /* PCR 141 */\r
+ PORT_PCR_RESET, /* PCR 142 */\r
+ PORT_PCR_RESET, /* PCR 143 */\r
+ PORT_PCR_RESET, /* PCR 144 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ PORT_GPDO_RESET, /* GPDO 0 */\r
+ PORT_GPDO_RESET, /* GPDO 1 */\r
+ PORT_GPDO_RESET, /* GPDO 2 */\r
+ PORT_GPDO_RESET, /* GPDO 3 */\r
+ PORT_GPDO_RESET, /* GPDO 4 */\r
+ PORT_GPDO_RESET, /* GPDO 5 */\r
+ PORT_GPDO_RESET, /* GPDO 6 */\r
+ PORT_GPDO_RESET, /* GPDO 7 */\r
+ PORT_GPDO_RESET, /* GPDO 8 */\r
+ PORT_GPDO_RESET, /* GPDO 9 */\r
+ PORT_GPDO_RESET, /* GPDO 10 */\r
+ PORT_GPDO_RESET, /* GPDO 11 */\r
+ PORT_GPDO_RESET, /* GPDO 12 */\r
+ PORT_GPDO_RESET, /* GPDO 13 */\r
+ PORT_GPDO_RESET, /* GPDO 14 */\r
+ PORT_GPDO_RESET, /* GPDO 15 */\r
+ PORT_GPDO_RESET, /* GPDO 16 */\r
+ PORT_GPDO_RESET, /* GPDO 17 */\r
+ PORT_GPDO_RESET, /* GPDO 18 */\r
+ PORT_GPDO_RESET, /* GPDO 19 */\r
+ PORT_GPDO_RESET, /* GPDO 20 */\r
+ PORT_GPDO_RESET, /* GPDO 21 */\r
+ PORT_GPDO_RESET, /* GPDO 22 */\r
+ PORT_GPDO_RESET, /* GPDO 23 */\r
+ PORT_GPDO_RESET, /* GPDO 24 */\r
+ PORT_GPDO_RESET, /* GPDO 25 */\r
+ PORT_GPDO_RESET, /* GPDO 26 */\r
+ PORT_GPDO_RESET, /* GPDO 27 */\r
+ PORT_GPDO_RESET, /* GPDO 28 */\r
+ PORT_GPDO_RESET, /* GPDO 29 */\r
+ PORT_GPDO_RESET, /* GPDO 30 */\r
+ PORT_GPDO_RESET, /* GPDO 31 */\r
+ PORT_GPDO_RESET, /* GPDO 32 */\r
+ PORT_GPDO_RESET, /* GPDO 33 */\r
+ PORT_GPDO_RESET, /* GPDO 34 */\r
+ PORT_GPDO_RESET, /* GPDO 35 */\r
+ PORT_GPDO_RESET, /* GPDO 36 */\r
+ PORT_GPDO_RESET, /* GPDO 37 */\r
+ PORT_GPDO_RESET, /* GPDO 38 */\r
+ PORT_GPDO_RESET, /* GPDO 39 */\r
+ PORT_GPDO_RESET, /* GPDO 40 */\r
+ PORT_GPDO_RESET, /* GPDO 41 */\r
+ PORT_GPDO_RESET, /* GPDO 42 */\r
+ PORT_GPDO_RESET, /* GPDO 43 */\r
+ PORT_GPDO_RESET, /* GPDO 44 */\r
+ PORT_GPDO_RESET, /* GPDO 45 */\r
+ PORT_GPDO_RESET, /* GPDO 46 */\r
+ PORT_GPDO_RESET, /* GPDO 47 */\r
+ PORT_GPDO_RESET, /* GPDO 48 */\r
+ PORT_GPDO_RESET, /* GPDO 49 */\r
+ PORT_GPDO_RESET, /* GPDO 50 */\r
+ PORT_GPDO_RESET, /* GPDO 51 */\r
+ PORT_GPDO_RESET, /* GPDO 52 */\r
+ PORT_GPDO_RESET, /* GPDO 53 */\r
+ PORT_GPDO_RESET, /* GPDO 54 */\r
+ PORT_GPDO_RESET, /* GPDO 55 */\r
+ PORT_GPDO_RESET, /* GPDO 56 */\r
+ PORT_GPDO_RESET, /* GPDO 57 */\r
+ PORT_GPDO_RESET, /* GPDO 58 */\r
+ PORT_GPDO_RESET, /* GPDO 59 */\r
+ PORT_GPDO_RESET, /* GPDO 60 */\r
+ PORT_GPDO_RESET, /* GPDO 61 */\r
+ PORT_GPDO_RESET, /* GPDO 62 */\r
+ PORT_GPDO_RESET, /* GPDO 63 */\r
+ PORT_GPDO_RESET, /* GPDO 64 */\r
+ PORT_GPDO_RESET, /* GPDO 65 */\r
+ PORT_GPDO_RESET, /* GPDO 66 */\r
+ PORT_GPDO_RESET, /* GPDO 67 */\r
+ PORT_GPDO_RESET, /* GPDO 68 */\r
+ PORT_GPDO_RESET, /* GPDO 69 */\r
+ PORT_GPDO_RESET, /* GPDO 70 */\r
+ PORT_GPDO_RESET, /* GPDO 71 */\r
+ PORT_GPDO_RESET, /* GPDO 72 */\r
+ PORT_GPDO_RESET, /* GPDO 73 */\r
+ PORT_GPDO_RESET, /* GPDO 74 */\r
+ PORT_GPDO_RESET, /* GPDO 75 */\r
+ PORT_GPDO_RESET, /* GPDO 76 */\r
+ PORT_GPDO_RESET, /* GPDO 77 */\r
+ PORT_GPDO_RESET, /* GPDO 78 */\r
+ PORT_GPDO_RESET, /* GPDO 79 */\r
+ PORT_GPDO_RESET, /* GPDO 80 */\r
+ PORT_GPDO_RESET, /* GPDO 81 */\r
+ PORT_GPDO_RESET, /* GPDO 82 */\r
+ PORT_GPDO_RESET, /* GPDO 83 */\r
+ PORT_GPDO_RESET, /* GPDO 84 */\r
+ PORT_GPDO_RESET, /* GPDO 85 */\r
+ PORT_GPDO_RESET, /* GPDO 86 */\r
+ PORT_GPDO_RESET, /* GPDO 87 */\r
+ PORT_GPDO_RESET, /* GPDO 88 */\r
+ PORT_GPDO_RESET, /* GPDO 89 */\r
+ PORT_GPDO_RESET, /* GPDO 90 */\r
+ PORT_GPDO_RESET, /* GPDO 91 */\r
+ PORT_GPDO_RESET, /* GPDO 92 */\r
+ PORT_GPDO_RESET, /* GPDO 93 */\r
+ PORT_GPDO_RESET, /* GPDO 94 */\r
+ PORT_GPDO_RESET, /* GPDO 95 */\r
+ PORT_GPDO_RESET, /* GPDO 96 */\r
+ PORT_GPDO_RESET, /* GPDO 97 */\r
+ PORT_GPDO_RESET, /* GPDO 98 */\r
+ PORT_GPDO_RESET, /* GPDO 99 */\r
+ PORT_GPDO_RESET, /* GPDO 100 */\r
+ PORT_GPDO_RESET, /* GPDO 101 */\r
+ PORT_GPDO_RESET, /* GPDO 102 */\r
+ PORT_GPDO_RESET, /* GPDO 103 */\r
+ PORT_GPDO_RESET, /* GPDO 104 */\r
+ PORT_GPDO_RESET, /* GPDO 105 */\r
+ PORT_GPDO_RESET, /* GPDO 106 */\r
+ PORT_GPDO_RESET, /* GPDO 107 */\r
+ PORT_GPDO_RESET, /* GPDO 108 */\r
+ PORT_GPDO_RESET, /* GPDO 109 */\r
+ PORT_GPDO_RESET, /* GPDO 110 */\r
+ PORT_GPDO_RESET, /* GPDO 111 */\r
+ PORT_GPDO_RESET, /* GPDO 112 */\r
+ PORT_GPDO_RESET, /* GPDO 113 */\r
+ PORT_GPDO_RESET, /* GPDO 114 */\r
+ PORT_GPDO_RESET, /* GPDO 115 */\r
+ PORT_GPDO_RESET, /* GPDO 116 */\r
+ PORT_GPDO_RESET, /* GPDO 117 */\r
+ PORT_GPDO_RESET, /* GPDO 118 */\r
+ PORT_GPDO_RESET, /* GPDO 119 */\r
+ PORT_GPDO_RESET, /* GPDO 120 */\r
+ PORT_GPDO_RESET, /* GPDO 121 */\r
+ PORT_GPDO_RESET, /* GPDO 122 */\r
+ PORT_GPDO_RESET, /* GPDO 123 */\r
+ PORT_GPDO_RESET, /* GPDO 124 */\r
+ PORT_GPDO_RESET, /* GPDO 125 */\r
+ PORT_GPDO_RESET, /* GPDO 126 */\r
+ PORT_GPDO_RESET, /* GPDO 127 */\r
+ PORT_GPDO_RESET, /* GPDO 128 */\r
+ PORT_GPDO_RESET, /* GPDO 129 */\r
+ PORT_GPDO_RESET, /* GPDO 130 */\r
+ PORT_GPDO_RESET, /* GPDO 131 */\r
+ PORT_GPDO_RESET, /* GPDO 132 */\r
+ PORT_GPDO_RESET, /* GPDO 133 */\r
+ PORT_GPDO_RESET, /* GPDO 134 */\r
+ PORT_GPDO_RESET, /* GPDO 135 */\r
+ PORT_GPDO_RESET, /* GPDO 136 */\r
+ PORT_GPDO_RESET, /* GPDO 137 */\r
+ PORT_GPDO_RESET, /* GPDO 138 */\r
+ PORT_GPDO_RESET, /* GPDO 139 */\r
+ PORT_GPDO_RESET, /* GPDO 140 */\r
+ PORT_GPDO_RESET, /* GPDO 141 */\r
+ PORT_GPDO_RESET, /* GPDO 142 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): MPC551x\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:24:21 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_OFF\r
+#define PORT_DEV_ERROR_DETECT STD_OFF\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_IO (0)\r
+#define PORT_FUNC0 (0)\r
+#define PORT_FUNC1 (PORT_BIT5)\r
+#define PORT_FUNC2 (PORT_BIT4)\r
+#define PORT_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+#define PORT_FUNC4 (PORT_BIT3)\r
+\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_GPDO_RESET (0)\r
+\r
+#define PORT_GPDO_HIGH (1)\r
+\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_CNTX_A 48 \r
+#define PORT_PIN_NAME_CNRX_A 49 \r
+\r
+#endif /* PORT_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "Adc.h"\r
+#include "Dma.h"\r
+#include "mpc55xx.h"\r
+\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS] = {\r
+ {\r
+ .notifictionEnable = 1,\r
+ },\r
+ {\r
+ .notifictionEnable = 1,\r
+ }\r
+};\r
+\r
+extern void switch_node_switches_callback (void);\r
+extern void switch_node_potentiometers_callback (void);\r
+\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_DISABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+ { ADC_CONVERSION_TIME_8_CLOCKS, 10, 0, ADC_RESOLUTION_12BITS, ADC_CALIBRATION_ENABLED},\r
+};\r
+\r
+/*\r
+ * The switches\r
+ */\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_SWITCH_CHANNELS] =\r
+{\r
+ ADC_CH0, ADC_CH1\r
+};\r
+\r
+\r
+/*\r
+ * The potentiometers\r
+ */\r
+const Adc_ChannelType Adc_Group1ChannelList[ADC_NBR_OF_POTENTIOMETER_CHANNELS] =\r
+{\r
+ ADC_CH8, ADC_CH9, ADC_CH10\r
+};\r
+\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+Adc_CommandType Adc_Group0Commands [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group1Buffer [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+Adc_CommandType Adc_Group1Commands [sizeof(Adc_Group1ChannelList)/sizeof(Adc_Group1ChannelList[0])];\r
+\r
+/*\r
+Adc_ValueGroupType Adc_Group2Buffer [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+Adc_CommandType Adc_Group2Commands [sizeof(Adc_Group2ChannelList)/sizeof(Adc_Group2ChannelList[0])];\r
+\r
+Adc_ValueGroupType Adc_Group3Buffer [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+Adc_CommandType Adc_Group3Commands [sizeof(Adc_Group3ChannelList)/sizeof(Adc_Group3ChannelList[0])];\r
+*/\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = switch_node_switches_callback,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .commandBuffer = Adc_Group0Commands,\r
+ .numberOfChannels = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0],\r
+ .dmaCommandChannel = DMA_ADC_GROUP0_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP0_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP0],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP0]},\r
+\r
+ { .accessMode = ADC_ACCESS_MODE_SINGLE, .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW, .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = switch_node_potentiometers_callback,\r
+ .streamBufferMode = ADC_NO_STREAMING, .streamNumSamples = 0,\r
+ .channelList = Adc_Group1ChannelList,\r
+ .resultBuffer = Adc_Group1Buffer,\r
+ .commandBuffer = Adc_Group1Commands,\r
+ .numberOfChannels = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP1],\r
+ .dmaCommandChannel = DMA_ADC_GROUP1_COMMAND_CHANNEL,\r
+ .dmaResultChannel = DMA_ADC_GROUP1_RESULT_CHANNEL,\r
+ .groupDMACommands = &AdcGroupDMACommandConfig[ADC_GROUP1],\r
+ .groupDMAResults = &AdcGroupDMAResultConfig[ADC_GROUP1]}\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+\r
+/* DMA configuration. */\r
+const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS] =\r
+{\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group0Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group0Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP0].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Commands)/sizeof(Adc_Group0Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (uint32_t)Adc_Group1Commands,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_32BITS,\r
+ .SOFF = sizeof(Adc_CommandType),\r
+ .NBYTES = sizeof(Adc_CommandType),\r
+ .SLAST = -sizeof(Adc_Group1Commands),\r
+ .DADDR = (vint32_t)&EQADC.CFPR[ADC_GROUP1].R,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .DOFF = 0,\r
+ .DLAST_SGA = 0,\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Commands)/sizeof(Adc_Group1Commands[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ }\r
+};\r
+\r
+const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS]=\r
+{\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP0].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group0Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group0Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group0Buffer)/sizeof(Adc_Group0Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+ },\r
+ {\r
+ .SADDR = (vint32_t)&EQADC.RFPR[ADC_GROUP1].R + 2,\r
+ .SMOD = 0,\r
+ .SSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .DMOD = 0,\r
+ .DSIZE = DMA_TRANSFER_SIZE_16BITS,\r
+ .SOFF = 0,\r
+ .NBYTES = sizeof(Adc_ValueGroupType),\r
+ .SLAST = 0,\r
+ .DADDR = (uint32_t)Adc_Group1Buffer,\r
+ .CITERE_LINK = 0,\r
+ .CITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .DOFF = sizeof(Adc_ValueGroupType),\r
+ .DLAST_SGA = -sizeof(Adc_Group1Buffer),\r
+ .BITERE_LINK = 0,\r
+ .BITER = sizeof(Adc_Group1Buffer)/sizeof(Adc_Group1Buffer[0]),\r
+ .BWC = 0,\r
+ .MAJORLINKCH = 0,\r
+ .DONE = 0,\r
+ .ACTIVE = 0,\r
+ .MAJORE_LINK = 0,\r
+ .E_SG = 0,\r
+ .D_REQ = 0,\r
+ .INT_HALF = 0,\r
+ .INT_MAJ = 0,\r
+ .START = 0\r
+}\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#include "Dma.h"\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+/* Group definitions. */\r
+\r
+typedef enum\r
+{\r
+ ADC_SWITCHES,\r
+ ADC_POTENTIOMETERS\r
+}Adc_GroupType_NiceNames;\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_GROUP1,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_CH16,\r
+ ADC_CH17,\r
+ ADC_CH18,\r
+ ADC_CH19,\r
+ ADC_CH20,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_SWITCH_RED,\r
+ ADC_SWITCH_BLACK,\r
+ ADC_NBR_OF_SWITCH_CHANNELS,\r
+}Adc_SwitchesSignalType;\r
+\r
+typedef enum\r
+{\r
+ ADC_POTENTIOMETER_NOT_USED,\r
+ ADC_POTENTIOMETER_0,\r
+\r
+ ADC_POTENTIOMETER_1,\r
+ ADC_NBR_OF_POTENTIOMETER_CHANNELS,\r
+}Adc_PotentiometersSignals;\r
+\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+\r
+\r
+/* Non-standard type */\r
+typedef union\r
+{\r
+ vuint32_t R;\r
+ struct\r
+ {\r
+ vuint32_t EOQ:1;\r
+ vuint32_t PAUSE:1;\r
+ vuint32_t :4;\r
+ vuint32_t BN:1;\r
+ vuint32_t CAL:1;\r
+ vuint32_t MESSAGE_TAG:4;\r
+ vuint32_t LST:2;\r
+ vuint32_t TSR:1;\r
+ vuint32_t FMT:1;\r
+ vuint32_t CHANNEL_NUMBER:8;\r
+ vuint32_t :8;\r
+ } B;\r
+}Adc_CommandType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK\r
+}Adc_ClockSourceType;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DISABLED,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ Adc_ClockSourceType clockSource;\r
+ uint8_t hwUnitId;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_REFERENCE_VOLTAGE_GROUND,\r
+ ADC_REFERENCE_VOLTAGE_5V,\r
+}Adc_VoltageSourceType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_64_CLOCKS,\r
+ ADC_CONVERSION_TIME_128_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+/* Non-standard type */\r
+typedef enum\r
+{\r
+ ADC_CALIBRATION_DISABLED,\r
+ ADC_CALIBRATION_ENABLED\r
+}Adc_CalibrationType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_RESOLUTION_12BITS\r
+}Adc_ResolutionType;\r
+\r
+/* Non-standard type */\r
+/* Channel definitions. */\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType adcChannelConvTime;\r
+ Adc_VoltageSourceType adcChannelRefVoltSrcLow;\r
+ Adc_VoltageSourceType adcChannelRefVoltSrcHigh;\r
+ Adc_ResolutionType adcChannelResolution;\r
+ Adc_CalibrationType adcChannelCalibrationEnable;\r
+}Adc_ChannelConfigurationType;\r
+\r
+\r
+/* TODO list timer sources here. */\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_NO_TIMER,\r
+}Adc_HwTriggerTimerType;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef uint16_t Adc_StreamNumSampleType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINOUS = 9,\r
+}Adc_GroupConvModeType;\r
+\r
+\r
+/* Used ?? */\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType *resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+}Adc_GroupStatus;\r
+\r
+\r
+/* Implementation specific */\r
+typedef struct\r
+{\r
+ Adc_GroupAccessModeType accessMode;\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ Adc_HwTriggerSignalType hwTriggerSignal;\r
+ Adc_HwTriggerTimerType hwTriggerTimer;\r
+ void (*groupCallback)(void);\r
+ Adc_StreamBufferModeType streamBufferMode;\r
+ Adc_StreamNumSampleType streamNumSamples;\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ Adc_CommandType *commandBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+ Dma_ChannelType dmaCommandChannel;\r
+ Dma_ChannelType dmaResultChannel;\r
+ const struct tcd_t *groupDMACommands;\r
+ const struct tcd_t *groupDMAResults;\r
+}Adc_GroupDefType;\r
+\r
+\r
+/* Impl. specific */\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_ChannelConfigurationType* channelConfigPtr;\r
+ const uint16_t nbrOfChannels;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+ const uint16_t nbrOfGroups;\r
+}Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig [];\r
+\r
+extern const struct tcd_t AdcGroupDMACommandConfig [ADC_NBR_OF_GROUPS];\r
+extern const struct tcd_t AdcGroupDMAResultConfig [ADC_NBR_OF_GROUPS];\r
+\r
+#endif /*ADC_CFG_H_*/\r
-/* \r
-* Configuration of module CanIf (CanIf_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
\r
\r
\r
#if defined(USE_PDUR)\r
#include "PduR.h"\r
#endif\r
+#if defined(USE_CANNM)\r
+#include "CanNm_Cbk.h"\r
+#endif\r
#include <stdlib.h>\r
\r
\r
FLEXCAN_A, // CHANNEL_0\r
};\r
\r
+const uint8 CanIf_Arc_ChannelDefaultConfIndex[CANIF_CHANNEL_CNT] = {\r
+ CANIF_CHANNEL_0_CONFIG_0,\r
+};\r
+\r
// Container that gets slamed into CanIf_InitController()\r
// Inits ALL controllers\r
// Multiplicity 1..*\r
};\r
\r
\r
-const CanIf_InitHohConfigType CanIfHohConfigData[] = {\r
+const CanIf_InitHohConfigType CanIfHohConfigData[] = { \r
\r
{\r
.CanConfigSet = &CanConfigSetData,\r
.InitConfig = &CanIfInitConfig,\r
.TransceiverConfig = NULL, // Not used\r
.Arc_ChannelToControllerMap = CanIf_Arc_ChannelToControllerMap, \r
+ .Arc_ChannelDefaultConfIndex = CanIf_Arc_ChannelDefaultConfIndex,\r
};\r
\r
--- /dev/null
+/*\r
+ * Configuration of module CanIf (CanIf_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.4\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((CANIF_SW_MAJOR_VERSION == 1) && (CANIF_SW_MINOR_VERSION == 1)) )
+#error "CanIf: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef CANIF_CFG_H_\r
+#define CANIF_CFG_H_\r
+\r
+#include "Can.h"\r
+\r
+\r
+#define CANIF_PDU_ID_LedCommandTx 0\r
+\r
+// Identifiers for the elements in CanIfControllerConfig[]\r
+// This is the ConfigurationIndex in CanIf_InitController()\r
+typedef enum {\r
+ CANIF_CHANNEL_0_CONFIG_0,\r
+ CANIF_CHANNEL_CONFIGURATION_CNT\r
+} CanIf_Arc_ConfigurationIndexType;\r
+\r
+typedef enum {\r
+ CANIF_CHANNEL_0,\r
+ CANIF_CHANNEL_CNT\r
+} CanIf_Arc_ChannelIdType;\r
+\r
+#define CANIF_CONTROLLER_ID_Controller_1 CANIF_CHANNEL_0\r
+\r
+typedef enum {\r
+ CANIF_SOFTFILTER_TYPE_BINARY = 0, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_INDEX, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_LINEAR, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_TABLE, // Not supported\r
+ CANIF_SOFTFILTER_TYPE_MASK // CanIfCanRxPduCanIdMask in RxPduConfig is used for filtering\r
+} CanIf_SoftwareFilterTypeType;\r
+\r
+typedef enum {\r
+ CANIF_USER_TYPE_CAN_NM,\r
+ CANIF_USER_TYPE_CAN_TP,\r
+ CANIF_USER_TYPE_CAN_PDUR,\r
+ CANIF_USER_TYPE_CAN_SPECIAL\r
+} CanIf_UserTypeType;\r
+\r
+\r
+typedef void (*CanIf_FuncTypeCanSpecial)(PduIdType, const uint8 *, uint8, Can_IdType);\r
+\r
+typedef enum {\r
+ CANIF_PDU_TYPE_STATIC = 0,\r
+ CANIF_PDU_TYPE_DYNAMIC // Not supported\r
+} CanIf_PduTypeType;\r
+\r
+typedef enum {\r
+ CANIF_CAN_ID_TYPE_29 = 0,\r
+ CANIF_CAN_ID_TYPE_11\r
+} CanIf_CanIdTypeType;\r
+\r
+/*\r
+ * Public container\r
+ */\r
+#define CANIF_VERSION_INFO_API STD_ON\r
+#define CANIF_DEV_ERROR_DETECT STD_ON\r
+#define CANIF_DLC_CHECK STD_ON\r
+#define CANIF_MULITPLE_DRIVER_SUPPORT STD_OFF // Not supported\r
+#define CANIF_READRXPDU_DATA_API STD_OFF // Not supported\r
+#define CANIF_READRXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_READTXPDU_NOTIFY_STATUS_API STD_OFF // Not supported\r
+#define CANIF_SETDYNAMICTXID_API STD_OFF // Not supported\r
+#define CANIF_WAKEUP_EVENT_API STD_OFF // Not supported\r
+#define CANIF_TRANSCEIVER_API STD_OFF // Not supported\r
+#define CANIF_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfHrhRangeConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Lower CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduLowerCanId;\r
+\r
+ // Upper CAN Identifier of a receive CAN L-PDU for identifier range\r
+ // definition, in which all CAN Ids shall pass the software filtering. Range: 11\r
+ // Bit for Standard CAN Identifier 29 Bit for Extended CAN Identifer\r
+ uint32 CanIfRxPduUpperCanId;\r
+} CanIf_HrhRangeConfigType;\r
+\r
+\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHrhConfig container\r
+ */\r
+typedef struct {\r
+ // Defines the HRH type i.e, whether its a BasicCan or FullCan. If BasicCan is\r
+ // configured, software filtering is enabled.\r
+ Can_Arc_HohType CanIfHrhType;\r
+\r
+ // Selects the hardware receive objects by using the HRH range/list from\r
+ // CAN Driver configuration to define, for which HRH a software filtering has\r
+ // to be performed at during receive processing. True: Software filtering is\r
+ // enabled False: Software filtering is disabled\r
+ boolean CanIfSoftwareFilterHrh;\r
+\r
+ // Reference to controller Id to which the HRH belongs to. A controller can\r
+ // contain one or more HRHs.\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerHrhIdRef;\r
+\r
+ // The parameter refers to a particular HRH object in the CAN Driver Module\r
+ // configuration. The HRH id is unique in a given CAN Driver. The HRH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_Arc_HRHType CanIfHrhIdSymRef ;\r
+\r
+ // Defines the parameters required for configuraing multiple\r
+ // CANID ranges for a given same HRH.\r
+ const CanIf_HrhRangeConfigType *CanIfHrhRangeConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIf_Arc_EOL;\r
+} CanIf_HrhConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHthConfig container\r
+ */\r
+\r
+typedef struct {\r
+ // Defines the HTH type i.e, whether its a BasicCan or FullCan.\r
+ Can_Arc_HohType CanIfHthType;\r
+\r
+ // Reference to controller Id to which the HTH belongs to. A controller\r
+ // can contain one or more HTHs\r
+ CanIf_Arc_ChannelIdType CanIfCanControllerIdRef;\r
+\r
+ // The parameter refers to a particular HTH object in the CAN Driver Module\r
+ // configuration. The HTH id is unique in a given CAN Driver. The HTH Ids\r
+ // are defined in the CAN Driver Module and hence it is derived from CAN\r
+ // Driver Configuration.\r
+ Can_Arc_HTHType CanIfHthIdSymRef ;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIf_Arc_EOL;\r
+} CanIf_HthConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfInitHohConfig container\r
+ */\r
+typedef struct {\r
+ // Selects the CAN interface specific configuration setup. This type of external\r
+ // data structure shall contain the post build initialization data for the\r
+ // CAN interface for all underlying CAN Drivers.\r
+ const Can_ConfigSetType *CanConfigSet;\r
+\r
+ // This container contains contiguration parameters for each hardware receive object.\r
+ const CanIf_HrhConfigType *CanIfHrhConfig;\r
+\r
+ // This container contains parameters releated to each HTH\r
+ const CanIf_HthConfigType *CanIfHthConfig;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean CanIf_Arc_EOL;\r
+} CanIf_InitHohConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTxPduConfig container\r
+ */\r
+\r
+// This container contains the configuration (parameters) of each transmit\r
+// CAN L-PDU. The SHORT-NAME of "CanIfTxPduConfig" container\r
+// represents the symolic name of Transmit L-PDU.\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for transmit CAN L-PDU. The\r
+ // CanIfCanTxPduId is configurable at pre-compile and post-built time.\r
+ // Range: 0..max. number of CantTxPduIds PduIdType CanTxPduId;\r
+ PduIdType CanIfTxPduId;\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanTxPduIdCanId;\r
+\r
+ // Data length code (in bytes) of transmit CAN L-PDUs used by the CAN\r
+ // Driver for CAN L-PDU transmission. The data area size of a CAN L-Pdu\r
+ // can have a range from 0 to 8 bytes.\r
+ uint8 CanIfCanTxPduIdDlc;\r
+\r
+ // Defines the type of each transmit CAN L-PDU.\r
+ // DYNAMIC CAN ID is defined at runtime.\r
+ // STATIC CAN ID is defined at compile-time.\r
+ CanIf_PduTypeType CanIfCanTxPduType;\r
+\r
+#if ( CANIF_READTXPDU_NOTIFY_STATUS_API == STD_ON )\r
+ // Enables and disables transmit confirmation for each transmit CAN L-PDU\r
+ // for reading its notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadTxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of transmit CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfTxPduIdCanIdType;\r
+\r
+ // Name of target confirmation services to target upper layers (PduR, CanNm\r
+ // and CanTp. If parameter is not configured then no call-out function is\r
+ // provided by the upper layer for this Tx L-PDU.\r
+ void (*CanIfUserTxConfirmation)(PduIdType); /* CANIF 109 */\r
+\r
+ // Handle, that defines the hardware object or the pool of hardware objects\r
+ // configured for transmission. The parameter refers HTH Id, to which the L-\r
+ // PDU belongs to.\r
+ const CanIf_HthConfigType *CanIfCanTxPduHthRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack. ..\r
+ void *PduIdRef;\r
+} CanIf_TxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfRxPduConfig container\r
+ */\r
+\r
+\r
+// This container contains the configuration (parameters) of each receive\r
+// CAN L-PDU. The SHORT-NAME of "CanIfRxPduConfig" container itself\r
+// represents the symolic name of Receive L-PDU.\r
+\r
+typedef struct {\r
+ // ECU wide unique, symbolic handle for receive CAN L-PDU. The\r
+ // CanRxPduId is configurable at pre-compile and post-built time. It shall fulfill\r
+ // ANSI/AUTOSAR definitions for constant defines. Range: 0..max. number\r
+ // of defined CanRxPduIds\r
+ PduIdType CanIfCanRxPduId;\r
+\r
+ // CAN Identifier of Receive CAN L-PDUs used by the CAN Interface. Exa:\r
+ // Software Filtering. Range: 11 Bit For Standard CAN Identifier ... 29 Bit For\r
+ // Extended CAN identifier\r
+ uint32 CanIfCanRxPduCanId;\r
+\r
+ // Data Length code of received CAN L-PDUs used by the CAN Interface.\r
+ // Exa: DLC check. The data area size of a CAN L-PDU can have a range\r
+ // from 0 to 8 bytes. uint8 CanIfCanRxPduDlc;\r
+ uint8 CanIfCanRxPduDlc;\r
+\r
+#if ( CANIF_CANPDUID_READDATA_API == STD_ON )\r
+ // Enables and disables the Rx buffering for reading of received L-PDU data.\r
+ // True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduData;\r
+#endif\r
+\r
+#if ( CANIF_READRXPDU_NOTIF_STATUS_API == STD_ON )\r
+ // CanIfReadRxPduNotifyStatus {CANIF_READRXPDU_NOTIFY_STATUS}\r
+ // Enables and disables receive indication for each receive CAN L-PDU for\r
+ // reading its' notification status. True: Enabled False: Disabled\r
+ boolean CanIfReadRxPduNotifyStatus;\r
+#endif\r
+\r
+ // CAN Identifier of receive CAN L-PDUs used by the CAN Driver for CAN L-\r
+ // PDU transmission.\r
+ // EXTENDED_CAN The CANID is of type Extended (29 bits)\r
+ // STANDARD_CAN The CANID is of type Standard (11 bits)\r
+ CanIf_CanIdTypeType CanIfRxPduIdCanIdType;\r
+\r
+ // This parameter defines the type of the receive indication call-outs called to\r
+ // the corresponding upper layer the used TargetRxPduId belongs to.\r
+ CanIf_UserTypeType CanIfRxUserType;\r
+\r
+ // Name of target indication services to target upper layers (PduRouter,\r
+ // CanNm, CanTp and ComplexDeviceDrivers). If parameter is 0 no call-out\r
+ // function is configured.\r
+ void *CanIfUserRxIndication;\r
+\r
+ // The HRH to which Rx L-PDU belongs to, is referred through this\r
+ // parameter.\r
+ const CanIf_HrhConfigType *CanIfCanRxPduHrhRef;\r
+\r
+ // Reference to the "global" Pdu structure to allow harmonization of handle\r
+ // IDs in the COM-Stack.\r
+ void *PduIdRef;\r
+\r
+ // Defines the type of software filtering that should be used\r
+ // for this receive object.\r
+ CanIf_SoftwareFilterTypeType CanIfSoftwareFilterType;\r
+\r
+ // Acceptance filters, 1 - care, 0 - don't care.\r
+ // Is enabled by the CanIfSoftwareFilterMask in CanIf_HrhConfigType\r
+ // ArcCore exension\r
+ uint32 CanIfCanRxPduCanIdMask;\r
+\r
+} CanIf_RxPduConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/*\r
+ * CanIfControllerConfig container\r
+ */\r
+\r
+typedef enum {\r
+ CANIF_WAKEUP_SUPPORT_CONTROLLER,\r
+ CANIF_WAKEUP_SUPPORT_NO_WAKEUP,\r
+ CANIF_WAKEUP_SUPPORT_TRANSCEIVER\r
+} CanIf_WakeupSupportType;\r
+\r
+\r
+// This is the type supplied to CanIf_InitController()\r
+typedef struct {\r
+ CanIf_WakeupSupportType WakeupSupport; // Not used\r
+\r
+ // CanIf-specific id of the controller\r
+ CanIf_Arc_ChannelIdType CanIfControllerIdRef;\r
+\r
+ const uint8 CanIfDriverNameRef[8]; // Not used\r
+\r
+ const Can_ControllerConfigType *CanIfInitControllerRef;\r
+} CanIf_ControllerConfigType;\r
+\r
+//-------------------------------------------------------------------\r
+/*\r
+ * CanIfTransceiverDrvConfig container\r
+ */\r
+\r
+typedef struct {\r
+ boolean TrcvWakeupNotification;\r
+ uint8 TrcvIdRef;\r
+} CanIf_TransceiverDrvConfigType;\r
+\r
+\r
+typedef struct {\r
+ uint32 todo;\r
+} CanIf_TransceiverConfigType;\r
+\r
+// Callout functions with respect to the upper layers. This callout functions\r
+// defined in this container are common to all configured underlying CAN\r
+// Drivers / CAN Transceiver Drivers.\r
+typedef struct {\r
+ // Name of target BusOff notification services to target upper layers\r
+ // (PduRouter, CanNm, CanTp and ComplexDeviceDrivers).\r
+ // Multiplicity: 1\r
+ void (*CanIfBusOffNotification)(uint8 Controller);\r
+\r
+ // Name of target wakeup notification services to target upper layers\r
+ // e.g Ecu_StateManager. If parameter is 0\r
+ // no call-out function is configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeUpNotification)();\r
+\r
+ // Name of target wakeup validation notification services to target upper\r
+ // layers (ECU State Manager). If parameter is 0 no call-out function is\r
+ // configured.\r
+ // Multiplicity: 0..1\r
+ void (*CanIfWakeupValidNotification)();\r
+\r
+ // ArcCore ext.\r
+ void (*CanIfErrorNotificaton)(uint8,Can_Arc_ErrorType);\r
+\r
+} CanIf_DispatchConfigType;\r
+\r
+// This container contains the references to the configuration setup of each\r
+// underlying CAN driver.\r
+\r
+typedef struct {\r
+ // Selects the CAN Interface specific configuration setup. This type of the\r
+ // external data structure shall contain the post build initialization data for the\r
+ // CAN Interface for all underlying CAN Dirvers. constant to CanIf_ConfigType\r
+ uint32 CanIfConfigSet;\r
+\r
+ uint32 CanIfNumberOfCanRxPduIds;\r
+ uint32 CanIfNumberOfCanTXPduIds;\r
+ uint32 CanIfNumberOfDynamicCanTXPduIds;\r
+\r
+ //\r
+ // Containers\r
+ //\r
+\r
+ // This container contains the reference to the configuration\r
+ // setup of each underlying CAN driver.\r
+ // Multiplicity: 0..*\r
+ const CanIf_InitHohConfigType *CanIfHohConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // receive CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfRxPduConfig" container itself represents the symolic\r
+ // name of Receive L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_RxPduConfigType *CanIfRxPduConfigPtr;\r
+\r
+ // This container contains the configuration (parameters) of each\r
+ // transmit CAN L-PDU. The SHORT-NAME of\r
+ // "CanIfTxPduConfig" container represents the symolic name of\r
+ // Transmit L-PDU.\r
+ // Multiplicity: 0..*\r
+ const CanIf_TxPduConfigType *CanIfTxPduConfigPtr;\r
+\r
+} CanIf_InitConfigType;\r
+\r
+\r
+typedef struct {\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN controllers by each underlying CAN driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_ControllerConfigType *ControllerConfig;\r
+\r
+ // Callout functions with respect to the upper layers. This callout\r
+ // functions defined in this container are common to all\r
+ // configured underlying CAN Drivers / CAN Transceiver Drivers\r
+ const CanIf_DispatchConfigType *DispatchConfig;\r
+\r
+ // This container contains the init parameters of the CAN\r
+ // Interface.\r
+ // Multiplicity: 1..*\r
+ const CanIf_InitConfigType *InitConfig;\r
+\r
+ // This container contains the configuration (parameters) of all\r
+ // addressed CAN transceivers by each underlying CAN\r
+ // Transceiver Driver.\r
+ // Multiplicity: 1..*\r
+ const CanIf_TransceiverConfigType *TransceiverConfig;\r
+ \r
+ // ArcCore: Contains the mapping from CanIf-specific Channels to Can Controllers\r
+ const CanControllerIdType *Arc_ChannelToControllerMap;\r
+ \r
+ const uint8 *Arc_ChannelDefaultConfIndex;\r
+} CanIf_ConfigType;\r
+\r
+\r
+extern CanIf_ConfigType CanIf_Config;\r
+\r
+#endif\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((CAN_SW_MAJOR_VERSION == 1) && (CAN_SW_MINOR_VERSION == 0)) )
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+ \r
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF // Not supported\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+typedef enum {\r
+ FLEXCAN_A = 0,\r
+ CAN_CTRL_A = 0,\r
+ FLEXCAN_B = 1,\r
+ CAN_CTRL_B = 1,\r
+ FLEXCAN_C = 2,\r
+ CAN_CTRL_C = 2,\r
+ FLEXCAN_D = 3,\r
+ CAN_CTRL_D = 3,\r
+ FLEXCAN_E = 4,\r
+ CAN_CTRL_E = 4,\r
+ FLEXCAN_F = 5,\r
+ CAN_CTRL_F = 5,\r
+ CAN_CONTROLLER_CNT = 6\r
+}CanControllerIdType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD\r
+} Can_IdTypeType;\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_1,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ uint8 CanIndex;\r
+} Can_GeneralType;\r
+\r
+// Start mc9s12 unique\r
+typedef enum {\r
+ CAN_ARC_IDAM_2_32BIT,\r
+ CAN_ARC_IDAM_4_16BIT,\r
+ CAN_ARC_IDAM_8_8BIT,\r
+ CAN_ARC_IDAM_FILTER_CLOSED,\r
+} Can_Arc_IDAMType;\r
+\r
+typedef uint32 Can_FilterMaskType;\r
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask; \r
+ \r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING\r
+} Can_Arc_ProcessType;\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Can (Can_Lcfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_Mask_1 = 0x0;\r
+\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
+ {\r
+ .CanObjectId = HWObj_1,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1,\r
+ \r
+ .Can_Arc_MbMask = 0xff0000,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = FLEXCAN_A,\r
+ .CanControllerPropSeg = 4,\r
+ .CanControllerSeg1 = 4,\r
+ .CanControllerSeg2 = 4,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = PERIPHERAL_CLOCK_FLEXCAN_A,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
-/* \r
-* Configuration of module EcuC (ComGlobals.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.0\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:56:33 CEST 2010\r
-*/\r
-\r
-\r
-#if (ECUC_SW_MAJOR_VERSION != 1) \r
-#error "EcuC: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*
+* Configuration of module EcuC (ComGlobals.h)
+*
+* Created by:
+* Configured for (MCU): MPC5567
+*
+* Module vendor: ArcCore
+* Module version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Thu Jun 17 15:44:15 CEST 2010
+*/
+
+
+#if (ECUC_SW_MAJOR_VERSION != 1)
+#error "EcuC: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef COMGLOBALS_H_\r
#define COMGLOBALS_H_\r
\r
// PDU handle id definitions.\r
enum {\r
- LedCommandRx = 0,\r
+ LedCommandTx = 0,\r
};\r
\r
#endif\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef COM_CFG_H\r
+#define COM_CFG_H\r
+\r
+#define COM_MODULE_ID 20\r
+#define COM_INSTANCE_ID 1\r
+\r
+//#define COM_DEV_ERROR_DETECT\r
+\r
+#define COM_N_IPDUS 1\r
+#define COM_N_SIGNALS 1\r
+#define COM_N_GROUP_SIGNALS 0\r
+\r
+#define COM_E_INVALID_FILTER_CONFIGURATION 101\r
+#define COM_E_INITIALIZATION_FAILED 102\r
+#define COM_E_INVALID_SIGNAL_CONFIGURATION 103\r
+#define COM_INVALID_PDU_ID 104\r
+#define COM_ERROR_SIGNAL_IS_SIGNALGROUP 105\r
+\r
+#define COM_E_TOO_MANY_IPDU 106\r
+#define COM_E_TOO_MANY_SIGNAL 107\r
+#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
+\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
+\r
+#define ComConfigurationTimeBase 0.0\r
+#define ComVersionInfoApi\r
+\r
+#endif /*COM_CFG_H*/\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+\r
+#include "Com.h"\r
+#include "Com_Internal.h"\r
+#include <stdlib.h>\r
+#if defined(USE_PDUR)\r
+#include "PduR.h"\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
+/*\r
+ * Signal init values.\r
+ */\r
+const uint16 Com_SignalInitValue_SetLedLevelTx = 0;\r
+ \r
+\r
+/*\r
+ * Group signal definitions\r
+ */\r
+const ComGroupSignal_type ComGroupSignal[] = {\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/* SignalGroup GroupSignals lists. */\r
+\r
+/*\r
+ * Signal definitions\r
+ */\r
+const ComSignal_type ComSignal[] = {\r
+ {\r
+ .ComHandleId = SetLedLevelTx,\r
+ .ComFirstTimeoutFactor = 0,\r
+ .ComNotification = NULL,\r
+ .ComTimeoutFactor = 0,\r
+ .ComTimeoutNotification = NULL,\r
+ .ComErrorNotification = NULL,\r
+ .ComTransferProperty = TRIGGERED,\r
+ \r
+ .ComUpdateBitPosition = 0,\r
+ .ComSignalArcUseUpdateBit = 0,\r
+ \r
+ \r
+ .ComSignalInitValue = &Com_SignalInitValue_SetLedLevelTx,\r
+ .ComBitPosition = 7,\r
+ .ComBitSize = 16,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
+ .ComSignalType = UINT16,\r
+ .Com_Arc_IsSignalGroup = 0,\r
+ .ComGroupSignal = NULL,\r
+ \r
+ .ComRxDataTimeoutAction = COM_TIMEOUT_DATA_ACTION_NONE,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+\r
+/*\r
+ * I-PDU group definitions\r
+ */\r
+const ComIPduGroup_type ComIPduGroup[] = {\r
+ {\r
+ .ComIPduGroupHandleId = TxGroup,\r
+ .Com_Arc_EOL = 0\r
+ },\r
+ \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+/* IPdu signal lists. */\r
+const ComSignal_type * const ComIPduSignalRefs_LedCommandTx[] = {\r
+ &ComSignal[ SetLedLevelTx ], \r
+ NULL,\r
+};\r
+\r
+/*\r
+ * I-PDU definitions\r
+ */\r
+const ComIPdu_type ComIPdu[] = { \r
+ \r
+ { // LedCommandTx\r
+ .ArcIPduOutgoingId = PDUR_DEST_PDU_ID_LedCommandTx,\r
+ .ComIPduCallout = NULL,\r
+ .ComIPduSignalProcessing = DEFERRED,\r
+ .ComIPduSize = 8,\r
+ .ComIPduDirection = SEND,\r
+ .ComIPduGroupRef = TxGroup,\r
+ \r
+ .ComTxIPdu = {\r
+ .ComTxIPduMinimumDelayFactor = 0,\r
+ .ComTxIPduUnusedAreasDefault = 0,\r
+ .ComTxModeTrue = {\r
+ .ComTxModeMode = DIRECT,\r
+ .ComTxModeNumberOfRepetitions = 0,\r
+ .ComTxModeRepetitionPeriodFactor = 0,\r
+ .ComTxModeTimeOffsetFactor = 0,\r
+ .ComTxModeTimePeriodFactor = 0,\r
+ },\r
+ },\r
+ \r
+ .ComIPduSignalRef = ComIPduSignalRefs_LedCommandTx,\r
+ .Com_Arc_EOL = 0\r
+ }, \r
+ {\r
+ .Com_Arc_EOL = 1\r
+ }\r
+};\r
+\r
+const Com_ConfigType ComConfiguration = {\r
+ .ComConfigurationId = 1,\r
+ .ComIPdu = ComIPdu,\r
+ .ComIPduGroup = ComIPduGroup,\r
+ .ComSignal = ComSignal,\r
+ .ComGroupSignal = ComGroupSignal\r
+};\r
+\r
+/* IPdu buffers and signal group buffers */\r
+uint8 ComArcIPduBuffer_LedCommandTx[8];\r
+ \r
+\r
+Com_Arc_IPdu_type Com_Arc_IPdu[] = {\r
+ { // LedCommandTx\r
+ .Com_Arc_TxIPduTimers = {\r
+ .ComTxIPduNumberOfRepetitionsLeft = 0,\r
+ .ComTxModeRepetitionPeriodTimer = 0,\r
+ .ComTxIPduMinimumDelayTimer = 0,\r
+ .ComTxModeTimePeriodTimer = 0\r
+ },\r
+ .ComIPduDataPtr = ComArcIPduBuffer_LedCommandTx,\r
+ .Com_Arc_IpduStarted = 0 \r
+ },\r
+};\r
+\r
+Com_Arc_Signal_type Com_Arc_Signal[] = {\r
+ { // SetLedLevelTx\r
+ .Com_Arc_DeadlineCounter = 0,\r
+ .ComTimeoutFactor = 0,\r
+ .ComIPduHandleId = 0,\r
+ .ComSignalUpdated = 0,\r
+ .ComIPduDataPtr = NULL,\r
+ \r
+ .Com_Arc_ShadowBuffer = NULL\r
+ \r
+ },\r
+ \r
+};\r
+\r
+Com_Arc_GroupSignal_type Com_Arc_GroupSignal[COM_N_GROUP_SIGNALS];\r
+\r
+uint8 outgoingSduPtr[8];\r
+\r
+Com_Arc_Config_type Com_Arc_Config = {\r
+ .ComIPdu = Com_Arc_IPdu,\r
+ .ComSignal = Com_Arc_Signal,\r
+ .ComGroupSignal = Com_Arc_GroupSignal,\r
+ .OutgoingPdu = {\r
+ .SduDataPtr = outgoingSduPtr,\r
+ .SduLength = 0\r
+ }\r
+};\r
+\r
--- /dev/null
+/*\r
+ * Configuration of module Com (Com_PbCfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.5\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((COM_SW_MAJOR_VERSION == 1) && (COM_SW_MINOR_VERSION == 1)) )
+#error "Com: Configuration file version differs from BSW version."
+#endif
+
+#ifndef COM_PBCFG_H\r
+#define COM_PBCFG_H\r
+\r
+#include "Com_Types.h"\r
+\r
+extern const Com_ConfigType ComConfiguration;\r
+\r
+// COM Polite Defines.\r
+#define COM_PDU_ID_LedCommandTx 0\r
+\r
+\r
+\r
+// PDU group definitions\r
+#define TxGroup 0\r
+\r
+\r
+// Signal definitions\r
+#define SetLedLevelTx 0\r
+\r
+\r
+\r
+\r
+#endif /* COM_PBCFG_H */\r
--- /dev/null
+\r
+MOD_USE += CANIF COM PDUR CAN PORT \r
+\r
--- /dev/null
+/*\r
+ * Configuration of module EcuM (EcuM_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.1\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((ECUM_SW_MAJOR_VERSION == 2) && (ECUM_SW_MINOR_VERSION == 0)) )
+#error "EcuM: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef ECUM_CFG_H_\r
+#define ECUM_CFG_H_\r
+\r
+#define ECUM_VERSION_INFO_API STD_OFF\r
+#define ECUM_DEV_ERROR_DETECT STD_OFF\r
+\r
+#include "EcuM_Generated_Types.h"\r
+\r
+#define ECUM_MAIN_FUNCTION_PERIOD (200)\r
+#define ECUM_NVRAM_READALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_WRITEALL_TIMEOUT (10000)\r
+#define ECUM_NVRAM_MIN_RUN_DURATION (10000)\r
+\r
+// EcuM_UserType definitions\r
+typedef enum {\r
+ ECUM_USER_SYSTEM, // Dummy user to get at least one user in system\r
+ ECUM_USER_ENDMARK // Must be the last in list!\r
+} EcuM_UserList;\r
+\r
+extern EcuM_ConfigType EcuMConfig;\r
+\r
+#endif /*ECUM_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_ComAlarm, ALARM_AUTOSTART_RELATIVE, 5, 20, OSDEFAULTAPPMODE );\r
+ \r
+GEN_ALARM_AUTOSTART(ALARM_ID_ReadSwAlarm, ALARM_AUTOSTART_RELATIVE, 10, 30, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_ComAlarm,\r
+ "ComAlarm",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_ComAlarm),\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_ComTask,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_ReadSwAlarm,\r
+ "ReadSwAlarm",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_ReadSwAlarm),\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_ReadSwitches,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(ComTask,2048);\r
+DECLARE_STACK(ReadSwitches,2048);\r
+DECLARE_STACK(StartupTask,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ ComTask,\r
+ 10,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ ReadSwitches,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ StartupTask,\r
+ 20,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_ComAlarm 0\r
+#define ALARM_ID_ReadSwAlarm 1\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_ComTask 1\r
+#define TASK_ID_ReadSwitches 2\r
+#define TASK_ID_StartupTask 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void ComTask( void );\r
+void ReadSwitches( void );\r
+void StartupTask( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 2 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 0\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module PduR (PduR_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
+\r
+\r
+#ifndef PDUR_CFG_H_\r
+#define PDUR_CFG_H_\r
+\r
+// Module support\r
+#define PDUR_CANIF_SUPPORT STD_ON\r
+#define PDUR_CANTP_SUPPORT STD_OFF\r
+#define PDUR_FRIF_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_FRTP_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_LINIF_SUPPORT STD_OFF\r
+#define PDUR_LINTP_SUPPORT STD_OFF /* Not supported */\r
+#define PDUR_COM_SUPPORT STD_ON\r
+#define PDUR_DCM_SUPPORT STD_OFF\r
+#define PDUR_IPDUM_SUPPORT STD_OFF /* Not supported */\r
+\r
+\r
+#define PDUR_DEV_ERROR_DETECT STD_OFF\r
+#define PDUR_VERSION_INFO_API STD_OFF\r
+\r
+\r
+// Zero cost operation mode\r
+#define PDUR_ZERO_COST_OPERATION STD_ON\r
+#define PDUR_SINGLE_IF CAN_IF\r
+#define PDUR_SINGLE_TP CAN_TP\r
+\r
+\r
+// Gateway operation\r
+#define PDUR_GATEWAY_OPERATION STD_OFF\r
+#define PDUR_MEMORY_SIZE 10 /* Not used */\r
+#define PDUR_SB_TX_BUFFER_SUPPORT STD_OFF\r
+#define PDUR_FIFO_TX_BUFFER_SUPPORT STD_OFF\r
+\r
+/**\r
+ * The maximum numbers of Tx buffers.\r
+ */\r
+#define PDUR_MAX_TX_BUFFER_NUMBER 10 /* Not used */\r
+\r
+\r
+\r
+\r
+\r
+// Multicast\r
+/* Not supported\r
+#define PDUR_MULTICAST_TOIF_SUPPORT STD_OFF\r
+#define PDUR_MULTICAST_FROMIF_SUPPORT STD_OFF\r
+#define PDUR_MULTICAST_TOTP_SUPPORT STD_OFF\r
+#define PDUR_MULTICAST_FROMTP_SUPPORT STD_OFF\r
+*/\r
+\r
+\r
+// Minimum routing\r
+/* Minimum routing not supported.\r
+#define PDUR_MINIMUM_ROUTING_UP_MODULE COM\r
+#define PDUR_MINIMUM_ROUTING_LO_MODULE CAN_IF\r
+#define PDUR_MINIMUM_ROUTING_UP_RXPDUID ((PduIdType)100)\r
+#define PDUR_MINIMUM_ROUTING_LO_RXPDUID ((PduIdType)255)\r
+#define PDUR_MINIMUM_ROUTING_UP_TXPDUID ((PduIdType)255)\r
+#define PDUR_MINIMUM_ROUTING_LO_TXPDUID ((PduIdType)255)\r
+*/\r
+\r
+\r
+#endif\r
--- /dev/null
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+\r
+#include "PduR.h"\r
+#include "PduR_Cfg.h"\r
+#include "PduR_PbCfg.h"\r
+\r
+#if PDUR_CANIF_SUPPORT == STD_ON\r
+#include "CanIf.h"\r
+#endif\r
+#if PDUR_CANTP_SUPPORT == STD_ON\r
+#include "CanTp.h"\r
+#endif\r
+#if PDUR_LINIF_SUPPORT == STD_ON\r
+#include "LinIf.h"\r
+#endif\r
+#if PDUR_COM_SUPPORT == STD_ON\r
+#include "Com.h"\r
+#endif\r
+#if PDUR_DCM_SUPPORT == STD_ON\r
+#include "Dcm.h"\r
+#endif\r
+\r
+\r
+PduRTxBufferTable_type PduRTxBufferTable = {\r
+ .PduRMaxTxBufferNumber = 1,\r
+ .PduRTxBuffer = {\r
+ {\r
+ .Depth = 0,\r
+ },\r
+ }\r
+};\r
+\r
+\r
+PduRRoutingTable_type PduRRoutingTable = {\r
+ .PduRRoutingPath = {\r
+ { // End of routing table\r
+ .PduR_Arc_EOL = 1\r
+ }\r
+ }\r
+};\r
+\r
+\r
+\r
+\r
+PduR_PBConfigType PduR_Config = {\r
+ .PduRConfigurationId = 0,\r
+ .PduRTxBufferTable = &PduRTxBufferTable,\r
+ .PduRRoutingTable = &PduRRoutingTable,\r
+};\r
-/* \r
-* Configuration of module PduR (PduR_PbCfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.1\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Fri Apr 30 15:54:06 CEST 2010\r
-*/\r
-\r
-\r
-#if (PDUR_SW_MAJOR_VERSION != 1) \r
-#error "PduR: Configuration file version differs from BSW version."\r
-#endif\r
+/*\r
+ * Configuration of module PduR (PduR_PbCfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
\r
+
+#if !(((PDUR_SW_MAJOR_VERSION == 1) && (PDUR_SW_MINOR_VERSION == 0)) )
+#error "PduR: Configuration file version differs from BSW version."
+#endif
+
\r
#if defined(USE_DCM)\r
#include "Dcm.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.c)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+ \r
+// File generated on Fri Jan 14 10:53:45 CET 2011\r
+// File generated by com.arccore.bswbuilder.modules.port.mpc5567\r
+\r
+#include "Port.h"\r
+#include "Port_Cfg.h"\r
+#include <stdlib.h>\r
+\r
+const uint16_t PortPadConfigData[] = {\r
+ PORT_PCR_RESET, /* PCR 0 */\r
+ PORT_PCR_RESET, /* PCR 1 */\r
+ PORT_PCR_RESET, /* PCR 2 */\r
+ PORT_PCR_RESET, /* PCR 3 */\r
+ PORT_PCR_RESET, /* PCR 4 */\r
+ PORT_PCR_RESET, /* PCR 5 */\r
+ PORT_PCR_RESET, /* PCR 6 */\r
+ PORT_PCR_RESET, /* PCR 7 */\r
+ PORT_PCR_RESET, /* PCR 8 */\r
+ PORT_PCR_RESET, /* PCR 9 */\r
+ PORT_PCR_RESET, /* PCR 10 */\r
+ PORT_PCR_RESET, /* PCR 11 */\r
+ PORT_PCR_RESET, /* PCR 12 */\r
+ PORT_PCR_RESET, /* PCR 13 */\r
+ PORT_PCR_RESET, /* PCR 14 */\r
+ PORT_PCR_RESET, /* PCR 15 */\r
+ PORT_PCR_RESET, /* PCR 16 */\r
+ PORT_PCR_RESET, /* PCR 17 */\r
+ PORT_PCR_RESET, /* PCR 18 */\r
+ PORT_PCR_RESET, /* PCR 19 */\r
+ PORT_PCR_RESET, /* PCR 20 */\r
+ PORT_PCR_RESET, /* PCR 21 */\r
+ PORT_PCR_RESET, /* PCR 22 */\r
+ PORT_PCR_RESET, /* PCR 23 */\r
+ PORT_PCR_RESET, /* PCR 24 */\r
+ PORT_PCR_RESET, /* PCR 25 */\r
+ PORT_PCR_RESET, /* PCR 26 */\r
+ PORT_PCR_RESET, /* PCR 27 */\r
+ PORT_PCR_RESET, /* PCR 28 */\r
+ PORT_PCR_RESET, /* PCR 29 */\r
+ PORT_PCR_RESET, /* PCR 30 */\r
+ PORT_PCR_RESET, /* PCR 31 */\r
+ PORT_PCR_RESET, /* PCR 32 */\r
+ PORT_PCR_RESET, /* PCR 33 */\r
+ PORT_PCR_RESET, /* PCR 34 */\r
+ PORT_PCR_RESET, /* PCR 35 */\r
+ PORT_PCR_RESET, /* PCR 36 */\r
+ PORT_PCR_RESET, /* PCR 37 */\r
+ PORT_PCR_RESET, /* PCR 38 */\r
+ PORT_PCR_RESET, /* PCR 39 */\r
+ PORT_PCR_RESET, /* PCR 40 */\r
+ PORT_PCR_RESET, /* PCR 41 */\r
+ PORT_PCR_RESET, /* PCR 42 */\r
+ PORT_PCR_RESET, /* PCR 43 */\r
+ PORT_PCR_RESET, /* PCR 44 */\r
+ PORT_PCR_RESET, /* PCR 45 */\r
+ PORT_PCR_RESET, /* PCR 46 */\r
+ PORT_PCR_RESET, /* PCR 47 */\r
+ PORT_PCR_RESET, /* PCR 48 */\r
+ PORT_PCR_RESET, /* PCR 49 */\r
+ PORT_PCR_RESET, /* PCR 50 */\r
+ PORT_PCR_RESET, /* PCR 51 */\r
+ PORT_PCR_RESET, /* PCR 52 */\r
+ PORT_PCR_RESET, /* PCR 53 */\r
+ PORT_PCR_RESET, /* PCR 54 */\r
+ PORT_PCR_RESET, /* PCR 55 */\r
+ PORT_PCR_RESET, /* PCR 56 */\r
+ PORT_PCR_RESET, /* PCR 57 */\r
+ PORT_PCR_RESET, /* PCR 58 */\r
+ PORT_PCR_RESET, /* PCR 59 */\r
+ PORT_PCR_RESET, /* PCR 60 */\r
+ PORT_PCR_RESET, /* PCR 61 */\r
+ PORT_PCR_RESET, /* PCR 62 */\r
+ PORT_PCR_RESET, /* PCR 63 */\r
+ PORT_PCR_RESET, /* PCR 64 */\r
+ PORT_PCR_RESET, /* PCR 65 */\r
+ PORT_PCR_RESET, /* PCR 66 */\r
+ PORT_PCR_RESET, /* PCR 67 */\r
+ PORT_PCR_RESET, /* PCR 68 */\r
+ PORT_PCR_RESET, /* PCR 69 */\r
+ PORT_PCR_RESET, /* PCR 70 */\r
+ PORT_PCR_RESET, /* PCR 71 */\r
+ PORT_PCR_RESET, /* PCR 72 */\r
+ PORT_PCR_RESET, /* PCR 73 */\r
+ PORT_PCR_RESET, /* PCR 74 */\r
+ PORT_PCR_RESET, /* PCR 75 */\r
+ PORT_PCR_RESET, /* PCR 76 */\r
+ PORT_PCR_RESET, /* PCR 77 */\r
+ PORT_PCR_RESET, /* PCR 78 */\r
+ PORT_PCR_RESET, /* PCR 79 */\r
+ PORT_PCR_RESET, /* PCR 80 */\r
+ PORT_PCR_RESET, /* PCR 81 */\r
+ PORT_PCR_RESET, /* PCR 82 */\r
+ ( PORT_FUNC1 | PORT_OBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 83 : PORT_PIN_MODE_CAN */\r
+ ( PORT_FUNC1 | PORT_IBE_ENABLE | PORT_SLEW_RATE_MIN | PORT_PULL_NONE ), /* PCR 84 : PORT_PIN_MODE_CAN */\r
+ PORT_PCR_RESET, /* PCR 85 */\r
+ PORT_PCR_RESET, /* PCR 86 */\r
+ PORT_PCR_RESET, /* PCR 87 */\r
+ PORT_PCR_RESET, /* PCR 88 */\r
+ PORT_PCR_RESET, /* PCR 89 */\r
+ PORT_PCR_RESET, /* PCR 90 */\r
+ PORT_PCR_RESET, /* PCR 91 */\r
+ PORT_PCR_RESET, /* PCR 92 */\r
+ PORT_PCR_RESET, /* PCR 93 */\r
+ PORT_PCR_RESET, /* PCR 94 */\r
+ PORT_PCR_RESET, /* PCR 95 */\r
+ PORT_PCR_RESET, /* PCR 96 */\r
+ PORT_PCR_RESET, /* PCR 97 */\r
+ PORT_PCR_RESET, /* PCR 98 */\r
+ PORT_PCR_RESET, /* PCR 99 */\r
+ PORT_PCR_RESET, /* PCR 100 */\r
+ PORT_PCR_RESET, /* PCR 101 */\r
+ PORT_PCR_RESET, /* PCR 102 */\r
+ PORT_PCR_RESET, /* PCR 103 */\r
+ PORT_PCR_RESET, /* PCR 104 */\r
+ PORT_PCR_RESET, /* PCR 105 */\r
+ PORT_PCR_RESET, /* PCR 106 */\r
+ PORT_PCR_RESET, /* PCR 107 */\r
+ PORT_PCR_RESET, /* PCR 108 */\r
+ PORT_PCR_RESET, /* PCR 109 */\r
+ PORT_PCR_RESET, /* PCR 110 */\r
+ PORT_PCR_RESET, /* PCR 111 */\r
+ PORT_PCR_RESET, /* PCR 112 */\r
+ PORT_PCR_RESET, /* PCR 113 */\r
+ PORT_PCR_RESET, /* PCR 114 */\r
+ PORT_PCR_RESET, /* PCR 115 */\r
+ PORT_PCR_RESET, /* PCR 116 */\r
+ PORT_PCR_RESET, /* PCR 117 */\r
+ PORT_PCR_RESET, /* PCR 118 */\r
+ PORT_PCR_RESET, /* PCR 119 */\r
+ PORT_PCR_RESET, /* PCR 120 */\r
+ PORT_PCR_RESET, /* PCR 121 */\r
+ PORT_PCR_RESET, /* PCR 122 */\r
+ PORT_PCR_RESET, /* PCR 123 */\r
+ PORT_PCR_RESET, /* PCR 124 */\r
+ PORT_PCR_RESET, /* PCR 125 */\r
+ PORT_PCR_RESET, /* PCR 126 */\r
+ PORT_PCR_RESET, /* PCR 127 */\r
+ PORT_PCR_RESET, /* PCR 128 */\r
+ PORT_PCR_RESET, /* PCR 129 */\r
+ PORT_PCR_RESET, /* PCR 130 */\r
+ PORT_PCR_RESET, /* PCR 131 */\r
+ PORT_PCR_RESET, /* PCR 132 */\r
+ PORT_PCR_RESET, /* PCR 133 */\r
+ PORT_PCR_RESET, /* PCR 134 */\r
+ PORT_PCR_RESET, /* PCR 135 */\r
+ PORT_PCR_RESET, /* PCR 136 */\r
+ PORT_PCR_RESET, /* PCR 137 */\r
+ PORT_PCR_RESET, /* PCR 138 */\r
+ PORT_PCR_RESET, /* PCR 139 */\r
+ PORT_PCR_RESET, /* PCR 140 */\r
+ PORT_PCR_RESET, /* PCR 141 */\r
+ PORT_PCR_RESET, /* PCR 142 */\r
+ PORT_PCR_RESET, /* PCR 143 */\r
+ PORT_PCR_RESET, /* PCR 144 */\r
+ PORT_PCR_RESET, /* PCR 145 */\r
+ PORT_PCR_RESET, /* PCR 146 */\r
+ PORT_PCR_RESET, /* PCR 147 */\r
+ PORT_PCR_RESET, /* PCR 148 */\r
+ PORT_PCR_RESET, /* PCR 149 */\r
+ PORT_PCR_RESET, /* PCR 150 */\r
+ PORT_PCR_RESET, /* PCR 151 */\r
+ PORT_PCR_RESET, /* PCR 152 */\r
+ PORT_PCR_RESET, /* PCR 153 */\r
+ PORT_PCR_RESET, /* PCR 154 */\r
+ PORT_PCR_RESET, /* PCR 155 */\r
+ PORT_PCR_RESET, /* PCR 156 */\r
+ PORT_PCR_RESET, /* PCR 157 */\r
+ PORT_PCR_RESET, /* PCR 158 */\r
+ PORT_PCR_RESET, /* PCR 159 */\r
+ PORT_PCR_RESET, /* PCR 160 */\r
+ PORT_PCR_RESET, /* PCR 161 */\r
+ PORT_PCR_RESET, /* PCR 162 */\r
+ PORT_PCR_RESET, /* PCR 163 */\r
+ PORT_PCR_RESET, /* PCR 164 */\r
+ PORT_PCR_RESET, /* PCR 165 */\r
+ PORT_PCR_RESET, /* PCR 166 */\r
+ PORT_PCR_RESET, /* PCR 167 */\r
+ PORT_PCR_RESET, /* PCR 168 */\r
+ PORT_PCR_RESET, /* PCR 169 */\r
+ PORT_PCR_RESET, /* PCR 170 */\r
+ PORT_PCR_RESET, /* PCR 171 */\r
+ PORT_PCR_RESET, /* PCR 172 */\r
+ PORT_PCR_RESET, /* PCR 173 */\r
+ PORT_PCR_RESET, /* PCR 174 */\r
+ PORT_PCR_RESET, /* PCR 175 */\r
+ PORT_PCR_RESET, /* PCR 176 */\r
+ PORT_PCR_RESET, /* PCR 177 */\r
+ PORT_PCR_RESET, /* PCR 178 */\r
+ PORT_PCR_RESET, /* PCR 179 */\r
+ PORT_PCR_RESET, /* PCR 180 */\r
+ PORT_PCR_RESET, /* PCR 181 */\r
+ PORT_PCR_RESET, /* PCR 182 */\r
+ PORT_PCR_RESET, /* PCR 183 */\r
+ PORT_PCR_RESET, /* PCR 184 */\r
+ PORT_PCR_RESET, /* PCR 185 */\r
+ PORT_PCR_RESET, /* PCR 186 */\r
+ PORT_PCR_RESET, /* PCR 187 */\r
+ PORT_PCR_RESET, /* PCR 188 */\r
+ PORT_PCR_RESET, /* PCR 189 */\r
+ PORT_PCR_RESET, /* PCR 190 */\r
+ PORT_PCR_RESET, /* PCR 191 */\r
+ PORT_PCR_RESET, /* PCR 192 */\r
+ PORT_PCR_RESET, /* PCR 193 */\r
+ PORT_PCR_RESET, /* PCR 194 */\r
+ PORT_PCR_RESET, /* PCR 195 */\r
+ PORT_PCR_RESET, /* PCR 196 */\r
+ PORT_PCR_RESET, /* PCR 197 */\r
+ PORT_PCR_RESET, /* PCR 198 */\r
+ PORT_PCR_RESET, /* PCR 199 */\r
+ PORT_PCR_RESET, /* PCR 200 */\r
+ PORT_PCR_RESET, /* PCR 201 */\r
+ PORT_PCR_RESET, /* PCR 202 */\r
+ PORT_PCR_RESET, /* PCR 203 */\r
+ PORT_PCR_RESET, /* PCR 204 */\r
+ PORT_PCR_RESET, /* PCR 205 */\r
+ PORT_PCR_RESET, /* PCR 206 */\r
+ PORT_PCR_RESET, /* PCR 207 */\r
+ PORT_PCR_RESET, /* PCR 208 */\r
+ PORT_PCR_RESET, /* PCR 209 */\r
+ PORT_PCR_RESET, /* PCR 210 */\r
+ PORT_PCR_RESET, /* PCR 211 */\r
+ PORT_PCR_RESET, /* PCR 212 */\r
+ PORT_PCR_RESET, /* PCR 213 */\r
+ PORT_PCR_RESET, /* PCR 214 */\r
+ PORT_PCR_RESET, /* PCR 215 */\r
+ PORT_PCR_RESET, /* PCR 216 */\r
+ PORT_PCR_RESET, /* PCR 217 */\r
+ PORT_PCR_RESET, /* PCR 218 */\r
+ PORT_PCR_RESET, /* PCR 219 */\r
+ PORT_PCR_RESET, /* PCR 220 */\r
+ PORT_PCR_RESET, /* PCR 221 */\r
+ PORT_PCR_RESET, /* PCR 222 */\r
+ PORT_PCR_RESET, /* PCR 223 */\r
+ PORT_PCR_RESET, /* PCR 224 */\r
+ PORT_PCR_RESET, /* PCR 225 */\r
+ PORT_PCR_RESET, /* PCR 226 */\r
+ PORT_PCR_RESET, /* PCR 227 */\r
+ PORT_PCR_RESET, /* PCR 228 */\r
+ PORT_PCR_RESET, /* PCR 229 */\r
+ PORT_PCR_RESET, /* PCR 230 */\r
+ PORT_PCR_RESET, /* PCR 231 */\r
+ PORT_PCR_RESET, /* PCR 232 */\r
+ PORT_PCR_RESET, /* PCR 233 */\r
+ PORT_PCR_RESET, /* PCR 234 */\r
+ PORT_PCR_RESET, /* PCR 235 */\r
+ PORT_PCR_RESET, /* PCR 236 */\r
+ PORT_PCR_RESET, /* PCR 237 */\r
+ PORT_PCR_RESET, /* PCR 238 */\r
+ PORT_PCR_RESET, /* PCR 239 */\r
+ PORT_PCR_RESET, /* PCR 240 */\r
+ PORT_PCR_RESET, /* PCR 241 */\r
+ PORT_PCR_RESET, /* PCR 242 */\r
+ PORT_PCR_RESET, /* PCR 243 */\r
+ PORT_PCR_RESET, /* PCR 244 */\r
+ PORT_PCR_RESET, /* PCR 245 */\r
+ PORT_PCR_RESET, /* PCR 246 */\r
+ PORT_PCR_RESET, /* PCR 247 */\r
+ PORT_PCR_RESET, /* PCR 248 */\r
+ PORT_PCR_RESET, /* PCR 249 */\r
+ PORT_PCR_RESET, /* PCR 250 */\r
+ PORT_PCR_RESET, /* PCR 251 */\r
+ PORT_PCR_RESET, /* PCR 252 */\r
+ PORT_PCR_RESET, /* PCR 253 */\r
+ PORT_PCR_RESET, /* PCR 254 */\r
+ PORT_PCR_RESET, /* PCR 255 */\r
+ PORT_PCR_RESET, /* PCR 256 */\r
+ PORT_PCR_RESET, /* PCR 257 */\r
+ PORT_PCR_RESET, /* PCR 258 */\r
+ PORT_PCR_RESET, /* PCR 259 */\r
+ PORT_PCR_RESET, /* PCR 260 */\r
+ PORT_PCR_RESET, /* PCR 261 */\r
+ PORT_PCR_RESET, /* PCR 262 */\r
+ PORT_PCR_RESET, /* PCR 263 */\r
+ PORT_PCR_RESET, /* PCR 264 */\r
+ PORT_PCR_RESET, /* PCR 265 */\r
+ PORT_PCR_RESET, /* PCR 266 */\r
+ PORT_PCR_RESET, /* PCR 267 */\r
+ PORT_PCR_RESET, /* PCR 268 */\r
+ PORT_PCR_RESET, /* PCR 269 */\r
+ PORT_PCR_RESET, /* PCR 270 */\r
+ PORT_PCR_RESET, /* PCR 271 */\r
+ PORT_PCR_RESET, /* PCR 272 */\r
+ PORT_PCR_RESET, /* PCR 273 */\r
+ PORT_PCR_RESET, /* PCR 274 */\r
+ PORT_PCR_RESET, /* PCR 275 */\r
+ PORT_PCR_RESET, /* PCR 276 */\r
+ PORT_PCR_RESET, /* PCR 277 */\r
+ PORT_PCR_RESET, /* PCR 278 */\r
+ PORT_PCR_RESET, /* PCR 279 */\r
+ PORT_PCR_RESET, /* PCR 280 */\r
+ PORT_PCR_RESET, /* PCR 281 */\r
+ PORT_PCR_RESET, /* PCR 282 */\r
+ PORT_PCR_RESET, /* PCR 283 */\r
+ PORT_PCR_RESET, /* PCR 284 */\r
+ PORT_PCR_RESET, /* PCR 285 */\r
+ PORT_PCR_RESET, /* PCR 286 */\r
+ PORT_PCR_RESET, /* PCR 287 */\r
+ PORT_PCR_RESET, /* PCR 288 */\r
+ PORT_PCR_RESET, /* PCR 289 */\r
+ PORT_PCR_RESET, /* PCR 290 */\r
+ PORT_PCR_RESET, /* PCR 291 */\r
+ PORT_PCR_RESET, /* PCR 292 */\r
+ PORT_PCR_RESET, /* PCR 293 */\r
+ PORT_PCR_RESET, /* PCR 294 */\r
+ PORT_PCR_RESET, /* PCR 295 */\r
+ PORT_PCR_RESET, /* PCR 296 */\r
+ PORT_PCR_RESET, /* PCR 297 */\r
+ PORT_PCR_RESET, /* PCR 298 */\r
+};\r
+\r
+const uint8_t PortOutConfigData[] = {\r
+ PORT_GPDO_RESET, /* GPDO 0 */\r
+ PORT_GPDO_RESET, /* GPDO 1 */\r
+ PORT_GPDO_RESET, /* GPDO 2 */\r
+ PORT_GPDO_RESET, /* GPDO 3 */\r
+ PORT_GPDO_RESET, /* GPDO 4 */\r
+ PORT_GPDO_RESET, /* GPDO 5 */\r
+ PORT_GPDO_RESET, /* GPDO 6 */\r
+ PORT_GPDO_RESET, /* GPDO 7 */\r
+ PORT_GPDO_RESET, /* GPDO 8 */\r
+ PORT_GPDO_RESET, /* GPDO 9 */\r
+ PORT_GPDO_RESET, /* GPDO 10 */\r
+ PORT_GPDO_RESET, /* GPDO 11 */\r
+ PORT_GPDO_RESET, /* GPDO 12 */\r
+ PORT_GPDO_RESET, /* GPDO 13 */\r
+ PORT_GPDO_RESET, /* GPDO 14 */\r
+ PORT_GPDO_RESET, /* GPDO 15 */\r
+ PORT_GPDO_RESET, /* GPDO 16 */\r
+ PORT_GPDO_RESET, /* GPDO 17 */\r
+ PORT_GPDO_RESET, /* GPDO 18 */\r
+ PORT_GPDO_RESET, /* GPDO 19 */\r
+ PORT_GPDO_RESET, /* GPDO 20 */\r
+ PORT_GPDO_RESET, /* GPDO 21 */\r
+ PORT_GPDO_RESET, /* GPDO 22 */\r
+ PORT_GPDO_RESET, /* GPDO 23 */\r
+ PORT_GPDO_RESET, /* GPDO 24 */\r
+ PORT_GPDO_RESET, /* GPDO 25 */\r
+ PORT_GPDO_RESET, /* GPDO 26 */\r
+ PORT_GPDO_RESET, /* GPDO 27 */\r
+ PORT_GPDO_RESET, /* GPDO 28 */\r
+ PORT_GPDO_RESET, /* GPDO 29 */\r
+ PORT_GPDO_RESET, /* GPDO 30 */\r
+ PORT_GPDO_RESET, /* GPDO 31 */\r
+ PORT_GPDO_RESET, /* GPDO 32 */\r
+ PORT_GPDO_RESET, /* GPDO 33 */\r
+ PORT_GPDO_RESET, /* GPDO 34 */\r
+ PORT_GPDO_RESET, /* GPDO 35 */\r
+ PORT_GPDO_RESET, /* GPDO 36 */\r
+ PORT_GPDO_RESET, /* GPDO 37 */\r
+ PORT_GPDO_RESET, /* GPDO 38 */\r
+ PORT_GPDO_RESET, /* GPDO 39 */\r
+ PORT_GPDO_RESET, /* GPDO 40 */\r
+ PORT_GPDO_RESET, /* GPDO 41 */\r
+ PORT_GPDO_RESET, /* GPDO 42 */\r
+ PORT_GPDO_RESET, /* GPDO 43 */\r
+ PORT_GPDO_RESET, /* GPDO 44 */\r
+ PORT_GPDO_RESET, /* GPDO 45 */\r
+ PORT_GPDO_RESET, /* GPDO 46 */\r
+ PORT_GPDO_RESET, /* GPDO 47 */\r
+ PORT_GPDO_RESET, /* GPDO 48 */\r
+ PORT_GPDO_RESET, /* GPDO 49 */\r
+ PORT_GPDO_RESET, /* GPDO 50 */\r
+ PORT_GPDO_RESET, /* GPDO 51 */\r
+ PORT_GPDO_RESET, /* GPDO 52 */\r
+ PORT_GPDO_RESET, /* GPDO 53 */\r
+ PORT_GPDO_RESET, /* GPDO 54 */\r
+ PORT_GPDO_RESET, /* GPDO 55 */\r
+ PORT_GPDO_RESET, /* GPDO 56 */\r
+ PORT_GPDO_RESET, /* GPDO 57 */\r
+ PORT_GPDO_RESET, /* GPDO 58 */\r
+ PORT_GPDO_RESET, /* GPDO 59 */\r
+ PORT_GPDO_RESET, /* GPDO 60 */\r
+ PORT_GPDO_RESET, /* GPDO 61 */\r
+ PORT_GPDO_RESET, /* GPDO 62 */\r
+ PORT_GPDO_RESET, /* GPDO 63 */\r
+ PORT_GPDO_RESET, /* GPDO 64 */\r
+ PORT_GPDO_RESET, /* GPDO 65 */\r
+ PORT_GPDO_RESET, /* GPDO 66 */\r
+ PORT_GPDO_RESET, /* GPDO 67 */\r
+ PORT_GPDO_RESET, /* GPDO 68 */\r
+ PORT_GPDO_RESET, /* GPDO 69 */\r
+ PORT_GPDO_RESET, /* GPDO 70 */\r
+ PORT_GPDO_RESET, /* GPDO 71 */\r
+ PORT_GPDO_RESET, /* GPDO 72 */\r
+ PORT_GPDO_RESET, /* GPDO 73 */\r
+ PORT_GPDO_RESET, /* GPDO 74 */\r
+ PORT_GPDO_RESET, /* GPDO 75 */\r
+ PORT_GPDO_RESET, /* GPDO 76 */\r
+ PORT_GPDO_RESET, /* GPDO 77 */\r
+ PORT_GPDO_RESET, /* GPDO 78 */\r
+ PORT_GPDO_RESET, /* GPDO 79 */\r
+ PORT_GPDO_RESET, /* GPDO 80 */\r
+ PORT_GPDO_RESET, /* GPDO 81 */\r
+ PORT_GPDO_RESET, /* GPDO 82 */\r
+ PORT_GPDO_RESET, /* GPDO 83 */\r
+ PORT_GPDO_RESET, /* GPDO 84 */\r
+ PORT_GPDO_RESET, /* GPDO 85 */\r
+ PORT_GPDO_RESET, /* GPDO 86 */\r
+ PORT_GPDO_RESET, /* GPDO 87 */\r
+ PORT_GPDO_RESET, /* GPDO 88 */\r
+ PORT_GPDO_RESET, /* GPDO 89 */\r
+ PORT_GPDO_RESET, /* GPDO 90 */\r
+ PORT_GPDO_RESET, /* GPDO 91 */\r
+ PORT_GPDO_RESET, /* GPDO 92 */\r
+ PORT_GPDO_RESET, /* GPDO 93 */\r
+ PORT_GPDO_RESET, /* GPDO 94 */\r
+ PORT_GPDO_RESET, /* GPDO 95 */\r
+ PORT_GPDO_RESET, /* GPDO 96 */\r
+ PORT_GPDO_RESET, /* GPDO 97 */\r
+ PORT_GPDO_RESET, /* GPDO 98 */\r
+ PORT_GPDO_RESET, /* GPDO 99 */\r
+ PORT_GPDO_RESET, /* GPDO 100 */\r
+ PORT_GPDO_RESET, /* GPDO 101 */\r
+ PORT_GPDO_RESET, /* GPDO 102 */\r
+ PORT_GPDO_RESET, /* GPDO 103 */\r
+ PORT_GPDO_RESET, /* GPDO 104 */\r
+ PORT_GPDO_RESET, /* GPDO 105 */\r
+ PORT_GPDO_RESET, /* GPDO 106 */\r
+ PORT_GPDO_RESET, /* GPDO 107 */\r
+ PORT_GPDO_RESET, /* GPDO 108 */\r
+ PORT_GPDO_RESET, /* GPDO 109 */\r
+ PORT_GPDO_RESET, /* GPDO 110 */\r
+ PORT_GPDO_RESET, /* GPDO 111 */\r
+ PORT_GPDO_RESET, /* GPDO 112 */\r
+ PORT_GPDO_RESET, /* GPDO 113 */\r
+ PORT_GPDO_RESET, /* GPDO 114 */\r
+ PORT_GPDO_RESET, /* GPDO 115 */\r
+ PORT_GPDO_RESET, /* GPDO 116 */\r
+ PORT_GPDO_RESET, /* GPDO 117 */\r
+ PORT_GPDO_RESET, /* GPDO 118 */\r
+ PORT_GPDO_RESET, /* GPDO 119 */\r
+ PORT_GPDO_RESET, /* GPDO 120 */\r
+ PORT_GPDO_RESET, /* GPDO 121 */\r
+ PORT_GPDO_RESET, /* GPDO 122 */\r
+ PORT_GPDO_RESET, /* GPDO 123 */\r
+ PORT_GPDO_RESET, /* GPDO 124 */\r
+ PORT_GPDO_RESET, /* GPDO 125 */\r
+ PORT_GPDO_RESET, /* GPDO 126 */\r
+ PORT_GPDO_RESET, /* GPDO 127 */\r
+ PORT_GPDO_RESET, /* GPDO 128 */\r
+ PORT_GPDO_RESET, /* GPDO 129 */\r
+ PORT_GPDO_RESET, /* GPDO 130 */\r
+ PORT_GPDO_RESET, /* GPDO 131 */\r
+ PORT_GPDO_RESET, /* GPDO 132 */\r
+ PORT_GPDO_RESET, /* GPDO 133 */\r
+ PORT_GPDO_RESET, /* GPDO 134 */\r
+ PORT_GPDO_RESET, /* GPDO 135 */\r
+ PORT_GPDO_RESET, /* GPDO 136 */\r
+ PORT_GPDO_RESET, /* GPDO 137 */\r
+ PORT_GPDO_RESET, /* GPDO 138 */\r
+ PORT_GPDO_RESET, /* GPDO 139 */\r
+ PORT_GPDO_RESET, /* GPDO 140 */\r
+ PORT_GPDO_RESET, /* GPDO 141 */\r
+ PORT_GPDO_RESET, /* GPDO 142 */\r
+ PORT_GPDO_RESET, /* GPDO 143 */\r
+ PORT_GPDO_RESET, /* GPDO 144 */\r
+ PORT_GPDO_RESET, /* GPDO 145 */\r
+ PORT_GPDO_RESET, /* GPDO 146 */\r
+ PORT_GPDO_RESET, /* GPDO 147 */\r
+ PORT_GPDO_RESET, /* GPDO 148 */\r
+ PORT_GPDO_RESET, /* GPDO 149 */\r
+ PORT_GPDO_RESET, /* GPDO 150 */\r
+ PORT_GPDO_RESET, /* GPDO 151 */\r
+ PORT_GPDO_RESET, /* GPDO 152 */\r
+ PORT_GPDO_RESET, /* GPDO 153 */\r
+ PORT_GPDO_RESET, /* GPDO 154 */\r
+ PORT_GPDO_RESET, /* GPDO 155 */\r
+ PORT_GPDO_RESET, /* GPDO 156 */\r
+ PORT_GPDO_RESET, /* GPDO 157 */\r
+ PORT_GPDO_RESET, /* GPDO 158 */\r
+ PORT_GPDO_RESET, /* GPDO 159 */\r
+ PORT_GPDO_RESET, /* GPDO 160 */\r
+ PORT_GPDO_RESET, /* GPDO 161 */\r
+ PORT_GPDO_RESET, /* GPDO 162 */\r
+ PORT_GPDO_RESET, /* GPDO 163 */\r
+ PORT_GPDO_RESET, /* GPDO 164 */\r
+ PORT_GPDO_RESET, /* GPDO 165 */\r
+ PORT_GPDO_RESET, /* GPDO 166 */\r
+ PORT_GPDO_RESET, /* GPDO 167 */\r
+ PORT_GPDO_RESET, /* GPDO 168 */\r
+ PORT_GPDO_RESET, /* GPDO 169 */\r
+ PORT_GPDO_RESET, /* GPDO 170 */\r
+ PORT_GPDO_RESET, /* GPDO 171 */\r
+ PORT_GPDO_RESET, /* GPDO 172 */\r
+ PORT_GPDO_RESET, /* GPDO 173 */\r
+ PORT_GPDO_RESET, /* GPDO 174 */\r
+ PORT_GPDO_RESET, /* GPDO 175 */\r
+ PORT_GPDO_RESET, /* GPDO 176 */\r
+ PORT_GPDO_RESET, /* GPDO 177 */\r
+ PORT_GPDO_RESET, /* GPDO 178 */\r
+ PORT_GPDO_RESET, /* GPDO 179 */\r
+ PORT_GPDO_RESET, /* GPDO 180 */\r
+ PORT_GPDO_RESET, /* GPDO 181 */\r
+ PORT_GPDO_RESET, /* GPDO 182 */\r
+ PORT_GPDO_RESET, /* GPDO 183 */\r
+ PORT_GPDO_RESET, /* GPDO 184 */\r
+ PORT_GPDO_RESET, /* GPDO 185 */\r
+ PORT_GPDO_RESET, /* GPDO 186 */\r
+ PORT_GPDO_RESET, /* GPDO 187 */\r
+ PORT_GPDO_RESET, /* GPDO 188 */\r
+ PORT_GPDO_RESET, /* GPDO 189 */\r
+ PORT_GPDO_RESET, /* GPDO 190 */\r
+ PORT_GPDO_RESET, /* GPDO 191 */\r
+ PORT_GPDO_RESET, /* GPDO 192 */\r
+ PORT_GPDO_RESET, /* GPDO 193 */\r
+ PORT_GPDO_RESET, /* GPDO 194 */\r
+ PORT_GPDO_RESET, /* GPDO 195 */\r
+ PORT_GPDO_RESET, /* GPDO 196 */\r
+ PORT_GPDO_RESET, /* GPDO 197 */\r
+ PORT_GPDO_RESET, /* GPDO 198 */\r
+ PORT_GPDO_RESET, /* GPDO 199 */\r
+ PORT_GPDO_RESET, /* GPDO 200 */\r
+ PORT_GPDO_RESET, /* GPDO 201 */\r
+ PORT_GPDO_RESET, /* GPDO 202 */\r
+ PORT_GPDO_RESET, /* GPDO 203 */\r
+ PORT_GPDO_RESET, /* GPDO 204 */\r
+ PORT_GPDO_RESET, /* GPDO 205 */\r
+ PORT_GPDO_RESET, /* GPDO 206 */\r
+ PORT_GPDO_RESET, /* GPDO 207 */\r
+ PORT_GPDO_RESET, /* GPDO 208 */\r
+ PORT_GPDO_RESET, /* GPDO 209 */\r
+ PORT_GPDO_RESET, /* GPDO 210 */\r
+ PORT_GPDO_RESET, /* GPDO 211 */\r
+ PORT_GPDO_RESET, /* GPDO 212 */\r
+ PORT_GPDO_RESET, /* GPDO 213 */\r
+};\r
+\r
+const Port_ConfigType PortConfigData =\r
+{\r
+ .padCnt = sizeof(PortPadConfigData),\r
+ .padConfig = PortPadConfigData,\r
+ .outCnt = sizeof(PortOutConfigData),\r
+ .outConfig = PortOutConfigData,\r
+};\r
--- /dev/null
+/*\r
+ * Configuration of module Port (Port_Cfg.h)\r
+ *\r
+ * Created by: Arccore AB\r
+ * Configured for (MCU): MPC5567\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.2\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 10:53:45 CET 2011\r
+ */\r
+\r
+
+#if !(((PORT_SW_MAJOR_VERSION == 1) && (PORT_SW_MINOR_VERSION == 0)) )
+#error "Port: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define PORT_VERSION_INFO_API STD_OFF\r
+#define PORT_DEV_ERROR_DETECT STD_OFF\r
+#define PORT_SET_PIN_MODE_API STD_OFF\r
+#define PORT_SET_PIN_DIRECTION_API STD_OFF\r
+\r
+#define PORT_BIT0 (1<<15)\r
+#define PORT_BIT1 (1<<14)\r
+#define PORT_BIT2 (1<<13)\r
+#define PORT_BIT3 (1<<12)\r
+#define PORT_BIT4 (1<<11)\r
+#define PORT_BIT5 (1<<10)\r
+#define PORT_BIT6 (1<<9)\r
+#define PORT_BIT7 (1<<8)\r
+#define PORT_BIT8 (1<<7)\r
+#define PORT_BIT9 (1<<6)\r
+#define PORT_BIT10 (1<<5)\r
+#define PORT_BIT11 (1<<4)\r
+#define PORT_BIT12 (1<<3)\r
+#define PORT_BIT13 (1<<2)\r
+#define PORT_BIT14 (1<<1)\r
+#define PORT_BIT15 (1<<0)\r
+\r
+#define PORT_WPE_BIT PORT_BIT14\r
+#define PORT_WPS_BIT PORT_BIT15\r
+#define PORT_SRC0 PORT_BIT12\r
+#define PORT_SRC1 PORT_BIT13\r
+\r
+#define PORT_PULL_UP (PORT_WPE_BIT|PORT_WPS_BIT)\r
+#define PORT_PULL_DOWN (PORT_WPE_BIT)\r
+#define PORT_PULL_NONE 0\r
+#define PORT_SLEW_RATE_MIN 0\r
+#define PORT_SLEW_RATE_MED PORT_BIT13\r
+#define PORT_SLEW_RATE_MAX (PORT_BIT12|PORT_BIT13)\r
+#define PORT_HYS_ENABLE PORT_BIT11\r
+#define PORT_ODE_ENABLE PORT_BIT10\r
+#define PORT_IBE_ENABLE PORT_BIT7\r
+#define PORT_OBE_ENABLE PORT_BIT6\r
+#define PORT_IO (0)\r
+#define PORT_FUNC0 (0)\r
+#define PORT_FUNC1 (PORT_BIT5)\r
+#define PORT_FUNC2 (PORT_BIT4)\r
+#define PORT_FUNC3 (PORT_BIT4|PORT_BIT5)\r
+#define PORT_FUNC4 (PORT_BIT3)\r
+\r
+#define PORT_PCR_RESET (0)\r
+#define PORT_GPDO_RESET (0)\r
+\r
+#define PORT_GPDO_HIGH (1)\r
+\r
+\r
+typedef uint16 Port_PinType;\r
+\r
+typedef struct\r
+{\r
+ uint16_t padCnt;\r
+ const uint16_t *padConfig;\r
+ uint16_t outCnt;\r
+ const uint8_t *outConfig;\r
+// uint16_t inCnt;\r
+// const uint8_t *inConfig;\r
+} Port_ConfigType;\r
+\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#define PORT_PIN_NAME_CNTXA 83 \r
+#define PORT_PIN_NAME_CNRXA 84 \r
+\r
+#endif /* PORT_CFG_H_ */\r
inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
inc-y += $(ROOTDIR)/system/kernel/include\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
+VPATH += ../\r
+\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
\r
#TODO: Remove?, Build other way?\r
-VPATH += $(ROOTDIR)/$(SUBDIR)/Rte\r
-inc-y += $(ROOTDIR)/$(SUBDIR)/Rte\r
+VPATH += ../Rte\r
+inc-y += ../Rte\r
VPATH += $(ROOTDIR)/components/switch\r
inc-y += $(ROOTDIR)/components/switch\r
\r
\r
# libs needed by us \r
-libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+#libitem-y +=\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
build-exe-y = switch_node.elf\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="fc563c91-212b-48aa-9b79-bd5e8f4b5ab0">\r
<SHORT-NAME>switch_node_mpc551x</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SD GID="MCU">MPC551x</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/switch_node_mpc551x/SwComposition_switch_node_mpc551x</ECU-SW-COMPOSITION-REF>\r
<MODULE-REFS>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/Can</MODULE-REF>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc551x/CanIf</MODULE-REF>\r
<SHORT-NAME>Can</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<SHORT-NAME>CanIf</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
<PARAMETER-VALUES>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfBusOffNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfErrorNotificaton</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupValidNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
<PARAMETER-VALUES>\r
<STRING-VALUE>\r
<DEFINITION-REF DEST="STRING-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfConfigSet</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</STRING-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfCanRxPduIds</DEFINITION-REF>\r
</ENUMERATION-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfTxPduConfig/CanIfUserTxConfirmation</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
</PARAMETER-VALUES>\r
<REFERENCE-VALUES>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/CanIf/CanIfPrivateConfiguration/CanIfSoftwareFilterType</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</ENUMERATION-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
</BOOLEAN-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
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- <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfTransceiverDrvConfig</DEFINITION-REF>\r
- <PARAMETER-VALUES>\r
- <BOOLEAN-VALUE>\r
- <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfTransceiverDrvConfig/CanIfTrcvWakeupNotification</DEFINITION-REF>\r
- <VALUE>false</VALUE>\r
- </BOOLEAN-VALUE>\r
- </PARAMETER-VALUES>\r
- </CONTAINER>\r
<CONTAINER UUID="d0bb0449-11b0-4815-8fc4-d98b626da887">\r
<SHORT-NAME>CHANNEL_0</SHORT-NAME>\r
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<SHORT-NAME>Com</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<PARAMETER-VALUES>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduCallout</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Com/ComConfig/ComIPdu/ComIPduRxHandleId</DEFINITION-REF>\r
</INTEGER-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Com/ComConfig/ComSignal/ComNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComSignalEndianess</DEFINITION-REF>\r
</INTEGER-VALUE>\r
<FUNCTION-NAME-VALUE>\r
<DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTimeoutNotification</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</FUNCTION-NAME-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Com/ComConfig/ComSignal/ComTransferProperty</DEFINITION-REF>\r
<SHORT-NAME>EcuC</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
<SHORT-NAME>PduR</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoModule</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoRxPduId</DEFINITION-REF>\r
</INTEGER-VALUE>\r
<ENUMERATION-VALUE>\r
<DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpModule</DEFINITION-REF>\r
- <VALUE></VALUE>\r
+ <VALUE />\r
</ENUMERATION-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpRxPduId</DEFINITION-REF>\r
<SHORT-NAME>Port</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<SHORT-NAME>EcuM</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMVersionInfoApi</DEFINITION-REF>\r
<VALUE>false</VALUE>\r
</BOOLEAN-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMMainFunctionPeriod</DEFINITION-REF>\r
+ <VALUE>0.2</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d82c22c1-1366-4a95-8b12-e9567fb3ae45">\r
+ <SHORT-NAME>EcuMConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramReadallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMRunMinimumDuration</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramWriteallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
</PARAMETER-VALUES>\r
</CONTAINER>\r
</CONTAINERS>\r
</MODULE-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="f5aff3ee-47b2-4798-906d-c72a3e6ad31e">\r
+ <SHORT-NAME>SwComposition_switch_node_mpc551x</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
</ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE UUID="a12472d5-8544-45a1-a68e-b72607912e76">\r
+ <SHORT-NAME>GeneratedSystemSignals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <SYSTEM-SIGNAL UUID="aa8d91e9-05a9-41ba-8a22-0bcb423997f9">\r
+ <SHORT-NAME>SetLedLevelTx</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::ParallelModelOptions">\r
+ <SD GID="PARALLEL_MODEL_GENERATED">TRUE</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <INIT-VALUE-REF DEST="INTEGER-LITERAL">/switch_node_mpc551x/GeneratedSystemSignals/Data/IntegerLiterals/SetLedLevelTxInitValue/SetLedLevelTxInitValueLiteral</INIT-VALUE-REF>\r
+ <LENGTH>16</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>Data</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">255</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">65535</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">4294967295</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-128</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">127</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-32768</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">32767</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-2147483648</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">2147483647</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>IntegerLiterals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <CONSTANT-SPECIFICATION>\r
+ <SHORT-NAME>SetLedLevelTxInitValue</SHORT-NAME>\r
+ <VALUE>\r
+ <INTEGER-LITERAL UUID="c12f4ad5-c594-438d-b7ef-0cc98e0e17b6">\r
+ <SHORT-NAME>SetLedLevelTxInitValueLiteral</SHORT-NAME>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-LITERAL>\r
+ </VALUE>\r
+ </CONSTANT-SPECIFICATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE UUID="78ad8a35-662e-43b4-9b0f-af912da9aa21">\r
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+ <CATEGORY>EcuConfiguration</CATEGORY>\r
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+ </ADMIN-DATA>\r
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+ <SHORT-NAME>switch_node_mpc5567</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <REVISION-LABEL>Rev 1</REVISION-LABEL>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">MPC5567</SD>\r
+ <SD GID="AUTHOR">Arccore AB</SD>\r
+ <SD GID="GENDIR" />\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/switch_node_mpc5567/SwComposition_switch_node_mpc5567</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/CanIf</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/Com</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/EcuC</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/Os</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/PduR</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/EcuM</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/Can</MODULE-REF>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/switch_node_mpc5567/Port</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="85d102ca-e755-47c5-a266-beed10ab3b57">\r
+ <SHORT-NAME>CanIf</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
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+ </ADMIN-DATA>\r
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+ <PARAMETER-VALUES>\r
+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfBusOffNotification</DEFINITION-REF>\r
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+ <FUNCTION-NAME-VALUE>\r
+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfErrorNotificaton</DEFINITION-REF>\r
+ <VALUE />\r
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+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupNotification</DEFINITION-REF>\r
+ <VALUE />\r
+ </FUNCTION-NAME-VALUE>\r
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+ <DEFINITION-REF DEST="FUNCTION-NAME-DEF">/ArcCore/CanIf/CanIfDispatchConfig/CanIfWakeupValidNotification</DEFINITION-REF>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="3b595f17-b484-400d-80d1-1c4c0feb134e">\r
+ <SHORT-NAME>CanIfDriverConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfDriverConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfBusoffNotification</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfReceiveIndication</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTransmitCancellation</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/CanIf/CanIfDriverConfig/CanIfTxConfirmation</DEFINITION-REF>\r
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+ <STRING-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfNumberOfDynamicCanTXPduIds</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
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+ <CONTAINER UUID="de0010c7-e224-4341-a27a-b88424103f34">\r
+ <SHORT-NAME>Hoh_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig</DEFINITION-REF>\r
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+ <CONTAINER UUID="5b415083-c3b5-4b5f-b4bc-e71b49e1ffe9">\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHthConfig/CanIfHthType</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHthConfig/CanIfCanControllerIdRef</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="SYMBOLIC-NAME-REFERENCE-PARAM-DEF">/ArcCore/CanIf/CanIfInitConfiguration/CanIfInitHohConfig/CanIfHthConfig/CanIfHthIdSymRef</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>RELATIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4074607e-a4c0-440e-a1cc-167c05a9ec83">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/switch_node_mpc5567/Os/ComTask</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="38528920-a11b-4e23-a952-969bdd19bc4b">\r
+ <SHORT-NAME>ReadSwAlarm</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/switch_node_mpc5567/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="802dd1d5-57ad-4ba6-a068-5c97822717e6">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>RELATIVE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>30</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="fb1d868d-8d1b-4977-a0cc-e2eea00b912b">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/switch_node_mpc5567/Os/ReadSwitches</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="299edb5c-e9bb-4cb7-99f2-96078c8ef889">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
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+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1672b97f-c474-47c9-9e3b-c4fb8f26804b">\r
+ <SHORT-NAME>ComTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7997f4d1-9b0c-4282-ba4c-5fdc1708411f">\r
+ <SHORT-NAME>ReadSwitches</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="dee9715a-4fa7-42f3-b692-a89b671c2578">\r
+ <SHORT-NAME>StartupTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>20</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="030fc701-0f8e-4d53-ad7b-8e341ef54b74">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="560e71ec-57fc-4fc4-bfaf-a07ebc650bcd">\r
+ <SHORT-NAME>PduR</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.1</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/PduR</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="c02d4309-5afc-4c03-8451-668b3b8bd8ba">\r
+ <SHORT-NAME>PduRGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/PduR/PduRGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRCanIfSupport</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRCanTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRComSupport</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRDcmSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRFifoTxBufferSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRFrIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRFrTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRGatewayOperation</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRIPduMSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRLinIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRLinTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMemorySize</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoModule</DEFINITION-REF>\r
+ <VALUE />\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoRxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingLoTxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpModule</DEFINITION-REF>\r
+ <VALUE />\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpRxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMinimumRoutingUpTxPduId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastFromIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastFromTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastToIfSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRMulticastToTpSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRSbTxBufferSupport</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRSingleIf</DEFINITION-REF>\r
+ <VALUE>CAN_IF</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRSingleTp</DEFINITION-REF>\r
+ <VALUE>CAN_TP</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/PduR/PduRGeneral/PduRZeroCostOperation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="31ab650e-b697-4204-ad91-3728915cef20">\r
+ <SHORT-NAME>PduRGlobalConfig</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/PduR/PduRGlobalConfig</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/PduR/PduRGlobalConfig/PduRConfigurationId</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="c988f2e6-82ba-4053-877e-3a973ae704e5">\r
+ <SHORT-NAME>PduRRoutingTable</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/PduR/PduRGlobalConfig/PduRRoutingTable</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="4e4b8e32-0309-4da2-86b0-2fb7d7450820">\r
+ <SHORT-NAME>EcuM</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/EcuM</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="03e49c2b-e150-484b-93c4-1805e3ca0ec7">\r
+ <SHORT-NAME>EcuMGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMIncludeNvramMgr</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/EcuM/EcuMGeneral/EcuMVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <VALUE>0.2</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7096af02-46a7-419b-9c5a-a3393c5bbb9c">\r
+ <SHORT-NAME>EcuMConfiguration</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/EcuM/EcuMConfiguration</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramReadallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMRunMinimumDuration</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ <FLOAT-VALUE>\r
+ <DEFINITION-REF DEST="FLOAT-PARAM-DEF">/ArcCore/EcuM/EcuMConfiguration/EcuMNvramWriteallTimeout</DEFINITION-REF>\r
+ <VALUE>10.0</VALUE>\r
+ </FLOAT-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="c89a47f9-0dec-4a59-a324-c03e724d6000">\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.0</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Can</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="40054b44-301c-485f-8076-ba6730e5f762">\r
+ <SHORT-NAME>CanConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="d5af655d-ba36-4474-9f27-65be24d7f2a8">\r
+ <SHORT-NAME>Controller_1</SHORT-NAME>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerActivation</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
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+ <VALUE>false</VALUE>\r
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+ <VALUE>125</VALUE>\r
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+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanHWControllerId</DEFINITION-REF>\r
+ <VALUE>FLEXCAN_A</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerPropSeg</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg1</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanControllerSeg2</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="2fe950d4-fc32-40e3-8671-abc7b9000d8a">\r
+ <SHORT-NAME>Mask_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanController/CanFilterMask/CanFilterMaskValue</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="311ed183-b070-48d0-999c-de45f7bc7018">\r
+ <SHORT-NAME>HWObj_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanIdType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanObjectType</DEFINITION-REF>\r
+ <VALUE>TRANSMIT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanMBMask</DEFINITION-REF>\r
+ <VALUE>16711680</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanControllerRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/switch_node_mpc5567/Can/CanConfigSet/Controller_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Can/CanConfigSet/CanHardwareObject/CanFilterMaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/switch_node_mpc5567/Can/CanConfigSet/Controller_1/Mask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2c60c720-b54d-40fc-b5ac-4b5fc91b5dbd">\r
+ <SHORT-NAME>CanGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Can/CanGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanDevErrorDetection</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanMultiplexedTransmission</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Can/CanGeneral/CanVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="317b7b30-da2c-4b40-8a30-7b64ead2da1a">\r
+ <SHORT-NAME>Port</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.2</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Port</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="99f76cfb-62b3-4110-b0ae-69580589849d">\r
+ <SHORT-NAME>PortConfigSet</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="168901b9-beda-4d27-8142-6057097141e9">\r
+ <SHORT-NAME>Can</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer</DEFINITION-REF>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="976cbf7c-9d76-40ad-adfb-02b51fef9117">\r
+ <SHORT-NAME>CNTXA</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_OUT</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>83</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c6e7b660-7250-4772-83e3-9ae17384f57e">\r
+ <SHORT-NAME>CNRXA</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinPullMode</DEFINITION-REF>\r
+ <VALUE>PULL_NONE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirection</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_IN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinDirectionChangeable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinHysteresisEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinOpenDrainEnabled</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinId</DEFINITION-REF>\r
+ <VALUE>84</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinSlewRate</DEFINITION-REF>\r
+ <VALUE>SLEW_RATE_MIN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinLevelValue</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_LEVEL_LOW</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Port/PortConfigSet/PortContainer/PortPin/PortPinMode</DEFINITION-REF>\r
+ <VALUE>PORT_PIN_MODE_CAN</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="041c18ac-f1bc-4b85-b494-5c09c66af23e">\r
+ <SHORT-NAME>PortGeneral</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Port/PortGeneral</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortDevErrorDetect</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinDirectionApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortSetPinModeApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Port/PortGeneral/PortVersionInfoApi</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="3f1661e4-7c0a-4801-b708-4f0be9fae2b6">\r
+ <SHORT-NAME>SwComposition_switch_node_mpc5567</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE UUID="c58cd0a6-d7b0-4b2a-817c-d0e82d4472b8">\r
+ <SHORT-NAME>GeneratedSystemSignals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <SYSTEM-SIGNAL UUID="e967256d-b5ed-4bd3-bcbd-ac4e4fe18a46">\r
+ <SHORT-NAME>SetLedLevelTx</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG GID="Arccore::ParallelModelOptions">\r
+ <SD GID="PARALLEL_MODEL_GENERATED">TRUE</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <INIT-VALUE-REF DEST="INTEGER-LITERAL">/switch_node_mpc5567/GeneratedSystemSignals/Data/IntegerLiterals/SetLedLevelTxInitValue/SetLedLevelTxInitValueLiteral</INIT-VALUE-REF>\r
+ <LENGTH>16</LENGTH>\r
+ </SYSTEM-SIGNAL>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>Data</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">255</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">65535</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">4294967295</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt8</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-128</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">127</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt16</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-32768</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">32767</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt32</SHORT-NAME>\r
+ <SW-DATA-DEF-PROPS />\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-2147483648</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">2147483647</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>IntegerLiterals</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <CONSTANT-SPECIFICATION>\r
+ <SHORT-NAME>SetLedLevelTxInitValue</SHORT-NAME>\r
+ <VALUE>\r
+ <INTEGER-LITERAL UUID="cf92ba63-3422-4555-849c-a7de2a59cf87">\r
+ <SHORT-NAME>SetLedLevelTxInitValueLiteral</SHORT-NAME>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-LITERAL>\r
+ </VALUE>\r
+ </CONSTANT-SPECIFICATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
\r
-MOD_USE+=KERNEL MCU\r
+-include ../config/*.mk\r
+-include ../config/$(BOARDDIR)/*.mk\r
+\r
+MOD_USE+=DET ECUM MCU KERNEL RAMLOG \r
\r
SELECT_CONSOLE = RAMLOG\r
SELECT_OS_CONSOLE = RAMLOG\r
\r
def-y += CFG_RAMLOG_SIZE=1024\r
-def-y += HEAPSIZE=400
\ No newline at end of file
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:28:16 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 14:53:39 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:28:16 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 14:53:39 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
\r
// Stack size\r
#define OS_INTERRUPT_STACK_SIZE 512\r
-#define OS_OSIDLE_STACK_SIZE 200\r
+#define OS_OSIDLE_STACK_SIZE 512\r
\r
#define OS_ALARM_CNT 1 \r
#define OS_TASK_CNT 4\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1400\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:00:47 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,512);\r
+DECLARE_STACK(etask_1,512);\r
+DECLARE_STACK(etask_2,512);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 11:00:47 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 512\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1400\r
+def-y += CFG_RAMLOG_SIZE=1024
\ No newline at end of file
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:28:40 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:33:23 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:28:40 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 12:33:23 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 23:08:30 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 23:08:30 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 23:08:30 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 23:08:30 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:28:54 CEST 2010\r
-*/\r
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 11:34:04 CET 2011\r
+ */\r
\r
\r
\r
COUNTER_UNIT_NANO,\r
0xffff,\r
1,\r
- 1,\r
+ 0,\r
0),\r
};\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: ArcCore AB\r
-* Configured for (MCU): Undefined MCU\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* Copyright ArcCore AB 2010\r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:28:54 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: ArcCore AB\r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * Copyright ArcCore AB 2010\r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 11:34:04 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
\r
#ifndef OS_CFG_H_\r
#define OS_CFG_H_\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:54:51 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F103\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Mon Jan 17 08:54:51 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 09:15:16 CET 2011\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): STM32_F107\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Fri Jan 14 09:15:16 CET 2011\r
+ */\r
+\r
+
+#if !(((OS_SW_MAJOR_VERSION == 2) && (OS_SW_MINOR_VERSION == 0)) )
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.c)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 15:30:44 CET 2010\r
+ */\r
+\r
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*\r
+ * Configuration of module Os (Os_Cfg.h)\r
+ *\r
+ * Created by: \r
+ * Configured for (MCU): Undefined MCU\r
+ *\r
+ * Module vendor: ArcCore\r
+ * Module version: 2.0.11\r
+ *\r
+ * \r
+ * Generated by Arctic Studio (http://arccore.com) \r
+ * on Wed Dec 01 15:30:44 CET 2010\r
+ */\r
+\r
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
-\r
+# Our object files\r
+obj-y += tiny.o\r
\r
VPATH += ..\r
VPATH += ../config\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
-# Our object files\r
-obj-y += tiny.o\r
-\r
# libs needed by us \r
-libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+#libitem-y +=\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
\r
# What I want to build\r
#build-lib-y = tiny.a\r
#include "Mcu.h"\r
#include "arc.h"\r
\r
-#define USE_LDEBUG_PRINTF\r
+//#define USE_LDEBUG_PRINTF // Uncomment this to turn debug statements on.\r
#include "debug.h"\r
\r
// How many errors to keep in error log.\r
\r
GetTaskID(&currTask);\r
Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("btask_3: Stack usage %u%%\n",\r
+ LDEBUG_PRINTF("btask_3: %u%% stack usage\n",\r
(unsigned)OS_STACK_USAGE(&si));\r
\r
TerminateTask();\r
StackInfoType si;\r
TaskType currTask;\r
\r
-\r
- LDEBUG_PRINTF("etask_1 start\n");\r
+ LDEBUG_FPUTS("etask_1 start\n");\r
for(;;) {\r
SetEvent(TASK_ID_etask_2,EVENT_MASK_EVENT_1);\r
WaitEvent(EVENT_MASK_EVENT_2);\r
tryFloatingPoint += 1.0F;\r
GetTaskID(&currTask);\r
Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("etask_1: Stack usage %u%% \n",\r
+ LDEBUG_PRINTF("etask_1: %u%% stack usage\n",\r
(unsigned)OS_STACK_USAGE(&si));\r
\r
}\r
* and activates task: btask_3.\r
*/\r
void etask_2( void ) {\r
- LDEBUG_PRINTF("etask_2 start\n");\r
+ LDEBUG_FPUTS("etask_2 start\n");\r
\r
for(;;) {\r
WaitEvent(EVENT_MASK_EVENT_1);\r
TaskType currTask;\r
GetTaskID(&currTask);\r
Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("etask_1: Stack usage %u%% \n",\r
+ LDEBUG_PRINTF("etask_2: %u%% stack usage\n",\r
(unsigned)OS_STACK_USAGE(&si));\r
}\r
}\r
\r
/* Global hooks */\r
ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
- LDEBUG_PRINTF("## ProtectionHook\n");\r
+ LDEBUG_FPUTS("## ProtectionHook\n");\r
return PRO_KILLAPPL;\r
}\r
\r
void StartupHook( void ) {\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
-\r
- LDEBUG_PRINTF("## StartupHook\n");\r
+ LDEBUG_FPUTS("## StartupHook\n");\r
\r
- LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)sys_freq);\r
+ LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)McuE_GetSystemClock());\r
}\r
\r
void ShutdownHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ShutdownHook\n");\r
+ LDEBUG_FPUTS("## ShutdownHook\n");\r
while(1);\r
}\r
\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>tiny_arm_cr4</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="7c3c165c-c7e6-458b-a18c-d0e7b89c6a2d">\r
+ <SHORT-NAME>tiny_arm_cr4</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/tiny_arm_cr4/SwComposition_tiny_arm_cr4</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tiny_arm_cr4/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="8e93c90b-a011-4edc-9f6b-a4927f5b499a">\r
+ <SHORT-NAME>SwComposition_tiny_arm_cr4</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="d9b75d00-e6eb-4671-a7cf-0abd1e1ed6a7">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="5ceca27a-71ff-4c71-bcb8-69a1f31f5d79">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="185f3281-13f7-459b-9ccd-66eb1aff52ca">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <CONTAINER UUID="4c1d9bd6-69e7-48c8-8036-35c6279f2240">\r
+ <SHORT-NAME>etask_1</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="fbcd933e-5944-44dd-ac92-f9eace6bb55c">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="41f28680-c88e-4083-bacc-40cf82ec3122">\r
+ <SHORT-NAME>etask_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="53d449ae-bdbe-49cb-bb22-141480e62565">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b5120b2f-2b4e-4e0f-8a7f-c7466b489644">\r
+ <SHORT-NAME>btask_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
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+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="759524bb-836c-4d61-b59a-cf8edfb6e162">\r
+ <SHORT-NAME>Alarm_4ms</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cr4/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="45cda08c-e07f-4670-8f14-b85acb209a6f">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5801fbe7-6b9b-4390-9341-2dd9ab4412f5">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cr4/Os/EVENT_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cr4/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f289efa7-5957-47a1-9c32-2248195ca090">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6dde7c3-6596-4a33-96ab-3a43d4ab1429">\r
+ <SHORT-NAME>EVENT_0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d93f5687-240e-465d-afb4-da563598d37a">\r
+ <SHORT-NAME>EVENT_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="94eef554-c26c-44d5-9b8f-501597b53d51">\r
+ <SHORT-NAME>EVENT_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>tiny_arm_cm3</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="2791ca0a-8e26-4388-976c-a48110927414">\r
+ <SHORT-NAME>tiny_arm_cm3</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">STM32_F103</SD>\r
+ <SD GID="GENDIR">/tiny/config/stm32_stm3210c</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/tiny_arm_cm3/SwComposition_tiny_arm_cm3</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tiny_arm_cm3/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="9aecec1e-749c-47fe-9fdb-98ed851bf12f">\r
+ <SHORT-NAME>SwComposition_tiny_arm_cm3</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="d9b75d00-e6eb-4671-a7cf-0abd1e1ed6a7">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="5ceca27a-71ff-4c71-bcb8-69a1f31f5d79">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="185f3281-13f7-459b-9ccd-66eb1aff52ca">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
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+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
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+ <CONTAINER UUID="fbcd933e-5944-44dd-ac92-f9eace6bb55c">\r
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+ <VALUE>1</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
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+ <VALUE>FULL</VALUE>\r
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+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cm3/Os/OsTick</VALUE-REF>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="45cda08c-e07f-4670-8f14-b85acb209a6f">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
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+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
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+ </CONTAINER>\r
+ <CONTAINER UUID="5801fbe7-6b9b-4390-9341-2dd9ab4412f5">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cm3/Os/EVENT_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cm3/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
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+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f289efa7-5957-47a1-9c32-2248195ca090">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6dde7c3-6596-4a33-96ab-3a43d4ab1429">\r
+ <SHORT-NAME>EVENT_0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d93f5687-240e-465d-afb4-da563598d37a">\r
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+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="94eef554-c26c-44d5-9b8f-501597b53d51">\r
+ <SHORT-NAME>EVENT_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>tiny_arm_cm3</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="2791ca0a-8e26-4388-976c-a48110927414">\r
+ <SHORT-NAME>tiny_arm_cm3</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">STM32_F107</SD>\r
+ <SD GID="GENDIR"></SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/tiny_arm_cm3/SwComposition_tiny_arm_cm3</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/tiny_arm_cm3/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="9aecec1e-749c-47fe-9fdb-98ed851bf12f">\r
+ <SHORT-NAME>SwComposition_tiny_arm_cm3</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="d9b75d00-e6eb-4671-a7cf-0abd1e1ed6a7">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="5ceca27a-71ff-4c71-bcb8-69a1f31f5d79">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
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+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="185f3281-13f7-459b-9ccd-66eb1aff52ca">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
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+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <BOOLEAN-VALUE>\r
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+ <VALUE>true</VALUE>\r
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+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
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+ <VALUE>1</VALUE>\r
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+ <VALUE>1</VALUE>\r
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+ <VALUE>2048</VALUE>\r
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+ <VALUE>FULL</VALUE>\r
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+ <CONTAINER UUID="fbcd933e-5944-44dd-ac92-f9eace6bb55c">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
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+ </CONTAINER>\r
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+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
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+ <VALUE>2048</VALUE>\r
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+ <CONTAINER UUID="759524bb-836c-4d61-b59a-cf8edfb6e162">\r
+ <SHORT-NAME>Alarm_4ms</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
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+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cm3/Os/OsTick</VALUE-REF>\r
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+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="45cda08c-e07f-4670-8f14-b85acb209a6f">\r
+ <SHORT-NAME>OsAlarmAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAlarmTime</DEFINITION-REF>\r
+ <VALUE>100</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmAutostartType</DEFINITION-REF>\r
+ <VALUE>ABSOLUTE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAutostart/OsAlarmCycleTime</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5801fbe7-6b9b-4390-9341-2dd9ab4412f5">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cm3/Os/EVENT_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/tiny_arm_cm3/Os/etask_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f289efa7-5957-47a1-9c32-2248195ca090">\r
+ <SHORT-NAME>OsTick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e6dde7c3-6596-4a33-96ab-3a43d4ab1429">\r
+ <SHORT-NAME>EVENT_0</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d93f5687-240e-465d-afb4-da563598d37a">\r
+ <SHORT-NAME>EVENT_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="94eef554-c26c-44d5-9b8f-501597b53d51">\r
+ <SHORT-NAME>EVENT_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="d3915a94-30a7-4688-a3b9-ec2496d78472">\r
<SHORT-NAME>tiny_hcs12</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
</INTEGER-VALUE>\r
<INTEGER-VALUE>\r
<DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
- <VALUE>200</VALUE>\r
+ <VALUE>512</VALUE>\r
</INTEGER-VALUE>\r
<BOOLEAN-VALUE>\r
<DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
</MODULE-CONFIGURATION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
<?xml version="1.0" encoding="UTF-8"?>\r
-<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
<AR-PACKAGE UUID="59e33e84-47d4-4613-bbcc-1aed684041be">\r
<SHORT-NAME>tiny_ppc</SHORT-NAME>\r
<CATEGORY>EcuConfiguration</CATEGORY>\r
<ADMIN-DATA>\r
<DOC-REVISIONS>\r
<DOC-REVISION>\r
- <ISSUED-BY/>\r
+ <ISSUED-BY />\r
</DOC-REVISION>\r
</DOC-REVISIONS>\r
</ADMIN-DATA>\r
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR" />\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/tiny_ppc/SwComposition_tiny_ppc</ECU-SW-COMPOSITION-REF>\r
<MODULE-REFS>\r
<MODULE-REF DEST="MODULE-CONFIGURATION">/tiny_ppc/Os</MODULE-REF>\r
</MODULE-REFS>\r
<SHORT-NAME>Os</SHORT-NAME>\r
<ADMIN-DATA>\r
<SDGS>\r
- <SDG/>\r
+ <SDG />\r
<SDG GID="Arccore::ModuleOptions">\r
<SD GID="GENERATE_AND_VALIDATE">true</SD>\r
<SD GID="ARCCORE_EDITOR_VERSION">2.0.6</SD>\r
</CONTAINER>\r
</CONTAINERS>\r
</MODULE-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="58aa50aa-74d9-422a-9410-c1fb05da153b">\r
+ <SHORT-NAME>SwComposition_tiny_ppc</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
</ELEMENTS>\r
</AR-PACKAGE>\r
- </TOP-LEVEL-PACKAGES></AUTOSAR>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
--- /dev/null
+#ifndef CALIBRATIONDATA_H_\r
+#define CALIBRATIONDATA_H_\r
+\r
+#include "Calibration_Settings.h"\r
+\r
+#ifdef CALIBRATION_ENABLED\r
+/* Section data from linker script. */\r
+extern char __CALIB_RAM_START;\r
+extern char __CALIB_RAM_END;\r
+extern char __CALIB_ROM_START;\r
+#endif /* CALIBRATION_ENABLED */\r
+#define ARC_DECLARE_CALIB(type, name) type __attribute__((section (".calibration"))) name\r
+\r
+#endif /* CALIBRATIONDATA_H_ */\r
#include "Std_Types.h"\r
#include "CanIf_Types.h"\r
#include "ComStack_Types.h"\r
+#if defined(USE_MCU)\r
#include "Mcu.h"\r
+#endif\r
+\r
\r
typedef struct {\r
uint32 txSuccessCnt;\r
typedef enum {\r
CAN_OK,\r
CAN_NOT_OK,\r
- CAN_BUSY,\r
+ CAN_BUSY\r
// CAN_WAKEUP, // Removed in 3.0\r
} Can_ReturnType;\r
\r
/* Error from CAN controller */\r
typedef union {\r
- volatile uint32_t R;\r
+ volatile uint32_t R;\r
struct {\r
- volatile uint32_t:24;\r
+ volatile uint32_t:24;\r
volatile uint32_t BIT1ERR:1;\r
volatile uint32_t BIT0ERR:1;\r
volatile uint32_t ACKERR:1;\r
#include "Can_Cfg.h"\r
\r
void Can_Init( const Can_ConfigType *Config );\r
-void Can_DeInit();\r
+void Can_DeInit(void);\r
\r
#if ( CAN_VERSION_INFO_API == STD_ON )\r
#define Can_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,CAN)\r
#ifndef CANIF_H_\r
#define CANIF_H_\r
\r
-// Added by Mattias\r
+#if defined(USE_PDUR)\r
#include "PduR.h"\r
+#endif\r
+\r
+#if defined(USE_COM)\r
#include "Com.h"\r
+#endif\r
\r
#define CANIF_VENDOR_ID 1\r
#define CANIF_MODULE_ID MODULE_ID_CANIF\r
* SLEEP mode and can be woken up by request of the\r
* CAN driver or by a network event (must be supported\r
* by CAN hardware) */\r
- CANIF_CS_SLEEP,\r
+ CANIF_CS_SLEEP\r
} CanIf_ControllerModeType;\r
\r
/** Status of the PDU channel group. Current mode of the channel defines its\r
* shall be set to the offline active mode\r
* => notifications are processed but transmit\r
* requests are blocked. */\r
- CANIF_SET_TX_OFFLINE_ACTIVE,\r
+ CANIF_SET_TX_OFFLINE_ACTIVE\r
} CanIf_ChannelSetModeType;\r
\r
\r
CANIF_NO_NOTIFICATION = 0, \r
/** The requested Rx/Tx CAN L-PDU was\r
* successfully transmitted or received. */\r
- CANIF_TX_RX_NOTIFICATION,\r
+ CANIF_TX_RX_NOTIFICATION\r
\r
} CanIf_NotifStatusType;\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CANNM_H\r
+#define CANNM_H\r
+\r
+#include "ComStack_Types.h"\r
+#include "NmStack_Types.h"\r
+#include "CanNm_ConfigTypes.h"\r
+#include "Modules.h"\r
+#include "CanNm_Cbk.h"\r
+\r
+/** @req CANNM021 */\r
+#define CANNM_VENDOR_ID 1\r
+#define CANNM_MODULE_ID MODULE_ID_CANNM\r
+\r
+#define CANNM_AR_MAJOR_VERSION 3\r
+#define CANNM_AR_MINOR_VERSION 0\r
+#define CANNM_AR_PATCH_VERSION 1\r
+\r
+#define CANNM_SW_MAJOR_VERSION 1\r
+#define CANNM_SW_MINOR_VERSION 0\r
+#define CANNM_SW_PATCH_VERSION 0\r
+\r
+/** @req CANNM200.configFiles */\r
+#include "CanNm_Cfg.h"\r
+\r
+/** @req CANNM018 */\r
+#define CANNM_E_NO_INIT 0x01u /**< API service used */\r
+#define CANNM_E_INVALID_CHANNEL 0x02u /**< API service called with wrong channel handle */\r
+/** NM-Timeout Timer has abnormally expired outside of the Ready Sleep State;\r
+it may happen: (1) because of Bus-Off state, (2) if some ECU requests bus communication or node detection shortly\r
+before the NMTimeout Timer expires so that a NM message can not be transmitted in time;\r
+this race condition applies to event-triggered systems */\r
+#define CANNM_E_DEV_NETWORK_TIMEOUT 0x11u\r
+#define NM_E_NULL_POINTER 0x12u /**< Null pointer has been passed as an argument (Does not apply to function CanNm_Init) */\r
+\r
+\r
+#define CANNM_SERVICEID_INIT 0x00u\r
+#define CANNM_SERVICEID_PASSIVESTARTUP 0x01u\r
+#define CANNM_SERVICEID_NETWORKREQUEST 0x02u\r
+#define CANNM_SERVICEID_NETWORKRELEASE 0x03u\r
+#define CANNM_SERVICEID_DISABLECOMMUNICATION 0x0Cu\r
+#define CANNM_SERVICEID_ENABLECOMMUNICATION 0x0Du\r
+#define CANNM_SERVICEID_SETUSERDATA 0x04u\r
+#define CANNM_SERVICEID_GETUSERDATA 0x05u\r
+#define CANNM_SERVICEID_GETNODEIDENTIFIER 0x06u\r
+#define CANNM_SERVICEID_GETLOCALNODEIDENTIFIER 0x07u\r
+#define CANNM_SERVICEID_REPEATMESSAGEREQUEST 0x08u\r
+#define CANNM_SERVICEID_GETPDUDATA 0x0Au\r
+#define CANNM_SERVICEID_GETSTATE 0x0Bu\r
+#define CANNM_SERVICEID_GETVERSIONINFO 0xF1u\r
+#define CANNM_SERVICEID_REQUESTBUSSYNCHRONIZATION 0xC0u\r
+#define CANNM_SERVICEID_CHECKREMOTESLEEPINDICATION 0xD0u\r
+#define CANNM_SERVICEID_TXCONFIRMATION 0x0Fu\r
+#define CANNM_SERVICEID_RXINDICATION 0x10u\r
+#define CANNM_SERVICEID_ARC_MAINFUNCTION 0x13u\r
+\r
+#define CANNM_CBV_REPEAT_MESSAGE_REQUEST 0x01u /**< @req CANNM045 */\r
+\r
+// Functions called by NM Interface\r
+// --------------------------------\r
+\r
+/** Initialize the complete CanNm module, i.e. all channels which are activated */\r
+void CanNm_Init( const CanNm_ConfigType * const cannmConfigPtr );\r
+\r
+/** Passive startup of the AUTOSAR CAN NM. It triggers the transition from Bus-\r
+ * Sleep Mode to the Network Mode in Repeat Message State.\r
+ * This service has no effect if the current state is not equal to Bus-Sleep Mode. In\r
+ * that case NM_E_NOT_EXECUTED is returned. */\r
+Nm_ReturnType CanNm_PassiveStartUp( const NetworkHandleType nmChannelHandle );\r
+\r
+/** Request the network, since ECU needs to communicate on the bus. Network\r
+ * state shall be changed to \91requested\92 */\r
+Nm_ReturnType CanNm_NetworkRequest( const NetworkHandleType nmChannelHandle );\r
+\r
+/** Release the network, since ECU doesn\92t have to communicate on the bus. Network\r
+ * state shall be changed to \91released\92. */\r
+Nm_ReturnType CanNm_NetworkRelease( const NetworkHandleType nmChannelHandle );\r
+\r
+/** Disable the NM PDU transmission ability due to a ISO14229 Communication\r
+ * Control (28hex) service */\r
+Nm_ReturnType CanNm_DisableCommunication( const NetworkHandleType nmChannelHandle );\r
+\r
+/** Enable the NM PDU transmission ability due to a ISO14229 Communication\r
+ * Control (28hex) service */\r
+Nm_ReturnType CanNm_EnableCommunication( const NetworkHandleType nmChannelHandle );\r
+\r
+/** Set user data for NM messages transmitted next on the bus. */\r
+Nm_ReturnType CanNm_SetUserData( const NetworkHandleType nmChannelHandle, const uint8* const nmUserDataPtr );\r
+\r
+/** Get user data out of the most recently received NM message. */\r
+Nm_ReturnType CanNm_GetUserData( const NetworkHandleType nmChannelHandle, uint8* const nmUserDataPtr );\r
+\r
+/** Get node identifier out of the most recently received NM PDU. */\r
+Nm_ReturnType CanNm_GetNodeIdentifier( const NetworkHandleType nmChannelHandle, uint8 * const nmNodeIdPtr );\r
+\r
+/** Get node identifier configured for the local node. */\r
+Nm_ReturnType CanNm_GetLocalNodeIdentifier( const NetworkHandleType nmChannelHandle, uint8 * const nmNodeIdPtr );\r
+\r
+/** Set Repeat Message Request Bit for NM messages transmitted next on the bus. */\r
+Nm_ReturnType CanNm_RepeatMessageRequest( const NetworkHandleType nmChannelHandle );\r
+\r
+/** Get the whole PDU data out of the most recently received NM message. */\r
+Nm_ReturnType CanNm_GetPduData( const NetworkHandleType nmChannelHandle, uint8 * const nmPduDataPtr );\r
+\r
+/** Returns the state and the mode of the network management. */\r
+Nm_ReturnType CanNm_GetState( const NetworkHandleType nmChannelHandle, Nm_StateType * const nmStatePtr, Nm_ModeType * const nmModePtr );\r
+\r
+/** This service returns the version information of this module. */\r
+#if ( CANNM_VERSION_INFO_API == STD_ON )\r
+#define CanNm_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,CANNM)\r
+#endif /* CANNM_VERSION_INFO_API */\r
+\r
+/** Request bus synchronization. */\r
+Nm_ReturnType CanNm_RequestBusSynchronization( const NetworkHandleType nmChannelHandle );\r
+\r
+/** Check if remote sleep indication takes place or not. */\r
+Nm_ReturnType CanNm_CheckRemoteSleepIndication( const NetworkHandleType nmChannelHandle, boolean * const nmRemoteSleepIndPtr );\r
+\r
+\r
+// Functions called by CAN Interface\r
+// ---------------------------------\r
+\r
+/** This service confirms a previous successfully processed CAN transmit request.\r
+ * This callback service is called by the CanIf and implemented by the CanNm. */\r
+void CanNm_TxConfirmation( PduIdType canNmTxPduId );\r
+\r
+/** This service indicates a successful reception of a received NM message to the\r
+ * CanNm after passing all filters and validation checks.\r
+ * This callback service is called by the CAN Interface and implemented by the CanNm. */\r
+void CanNm_RxIndication( PduIdType canNmRxPduId, const uint8 *canSduPtr );\r
+\r
+\r
+#endif /* CANNM_H */\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#ifndef CANNM_CBK_H_\r
+#define CANNM_CBK_H_\r
\r
+/* We need this to export pdu id's */\r
+#include "CanNm.h"\r
\r
-\r
-\r
-\r
-\r
-#ifndef MEMIF_CFG_H_\r
-#define MEMIF_CFG_H_\r
-\r
-// TODO. include FEE and EA modules\r
-\r
-\r
-\r
-#endif /*MEMIF_CFG_H_*/\r
+#endif /* CANNM_CBK_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CANNM_CONFIGTYPES_H_\r
+#define CANNM_CONFIGTYPES_H_\r
+\r
+typedef enum {\r
+ CANNM_PDU_BYTE_0 = 0x00,\r
+ CANNM_PDU_BYTE_1 = 0x01,\r
+ CANNM_PDU_OFF = 0xFF\r
+} CanNm_PduBytePositionType;\r
+\r
+/** @req CANNM202 @req CANNM203 */\r
+typedef struct {\r
+ const boolean Active;\r
+ const NetworkHandleType NmNetworkHandle;\r
+ const uint8 NodeId;\r
+ const uint32 MainFunctionPeriod;\r
+ const uint32 TimeoutTime;\r
+ const uint32 RepeatMessageTime; /**< @req CANNM148.1 */\r
+ const uint32 WaitBusSleepTime; /**< @req CANNM148.2 */\r
+ const uint32 MessageCycleTime; /**< @req CANNM148.3 */\r
+ const uint32 MessageCycleOffsetTime;\r
+ const PduIdType CanIfPduId;\r
+ const uint8 PduLength; /**< @req CANNM076 */\r
+ const CanNm_PduBytePositionType NidPosition; /**< @req CANNM074 */\r
+ const CanNm_PduBytePositionType CbvPosition; /**< @req CANNM075 */\r
+} CanNm_ChannelType;\r
+\r
+typedef struct {\r
+ const CanNm_ChannelType* Channels;\r
+} CanNm_ConfigType;\r
+\r
+#endif /* CANNM_CONFIGTYPES_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CANNM_INTERNAL_H_\r
+#define CANNM_INTERNAL_H_\r
+\r
+/** @req CANNM188 @req CANNM196 @req CANNM199 */\r
+#if (CANNM_DEV_ERROR_DETECT == STD_ON)\r
+#define CANNM_DET_REPORTERROR(serviceId, errorId, instanceId) \\r
+ Det_ReportError(MODULE_ID_CANNM, (uint8)instanceId, serviceId, errorId)\r
+\r
+#define CANNM_VALIDATE(expression, serviceId, errorId, instanceId, ...) \\r
+ if (!(expression)) { \\r
+ CANNM_DET_REPORTERROR(serviceId, errorId, instanceId); \\r
+ return __VA_ARGS__; \\r
+ }\r
+\r
+#else\r
+#define CANNM_DET_REPORTERROR(...)\r
+#define CANNM_VALIDATE(...)\r
+#endif\r
+\r
+#define CANNM_VALIDATE_INIT(serviceID, ...) \\r
+ CANNM_VALIDATE((CanNm_Internal.InitStatus == CANNM_INIT), serviceID, CANNM_E_NO_INIT, 0, __VA_ARGS__)\r
+\r
+/** @req CANNM192 */\r
+#define CANNM_VALIDATE_CHANNEL(channel, serviceID, ...) \\r
+ CANNM_VALIDATE( (channel < CANNM_CHANNEL_COUNT), serviceID, CANNM_E_INVALID_CHANNEL, channel, __VA_ARGS__)\r
+\r
+#define CANNM_VALIDATE_NOTNULL(ptr, serviceID, ...) \\r
+ CANNM_VALIDATE( (ptr != NULL), serviceID, NM_E_NULL_POINTER, 0, __VA_ARGS__)\r
+\r
+typedef enum {\r
+ CANNM_INIT,\r
+ CANNM_UNINIT\r
+} CanNm_InitStatusType;\r
+\r
+typedef struct {\r
+ Nm_ModeType Mode; /**< @req CANNM092 */\r
+ Nm_StateType State; /**< @req CANNM094 */\r
+ boolean Requested;\r
+ uint32 TimeoutTimeLeft;\r
+ uint32 RepeatMessageTimeLeft;\r
+ uint32 WaitBusSleepTimeLeft;\r
+ uint32 MessageCycleTimeLeft;\r
+ uint32 MessageCycleOffsetTimeLeft;\r
+ uint8 TxMessageSdu[8];\r
+ uint8 RxMessageSdu[8];\r
+} CanNm_Internal_ChannelType;\r
+\r
+typedef struct {\r
+ CanNm_InitStatusType InitStatus;\r
+ CanNm_Internal_ChannelType Channels[CANNM_CHANNEL_COUNT];\r
+} CanNm_InternalType;\r
+\r
+/* Timer helpers */\r
+static inline void CanNm_Internal_TickTimeoutTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_TickRepeatMessageTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_TickWaitBusSleepTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_TickMessageCycleTime( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_ClearCbv( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+\r
+/* Message helpers */\r
+static inline void CanNm_Internal_TransmitMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline uint8 CanNm_Internal_GetUserDataOffset( const CanNm_ChannelType* ChannelConf );\r
+static inline uint8* CanNm_Internal_GetUserDataPtr( const CanNm_ChannelType* ChannelConf, uint8* MessageSduPtr );\r
+static inline uint8 CanNm_Internal_GetUserDataLength( const CanNm_ChannelType* ChannelConf );\r
+\r
+/* Transition helpers */\r
+static inline void CanNm_Internal_PrepareBusSleep_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_PrepareBusSleep_to_BusSleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+\r
+static inline void CanNm_Internal_BusSleep_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_BusSleep_to_BusSleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+\r
+static inline void CanNm_Internal_RepeatMessage_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_RepeatMessage_to_ReadySleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_RepeatMessage_to_NormalOperation( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+\r
+static inline void CanNm_Internal_NormalOperation_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_NormalOperation_to_ReadySleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_NormalOperation_to_NormalOperation( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+\r
+static inline void CanNm_Internal_ReadySleep_to_NormalOperation( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_ReadySleep_to_PrepareBusSleep( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+static inline void CanNm_Internal_ReadySleep_to_RepeatMessage( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+\r
+static inline void CanNm_Internal_NetworkMode_to_NetworkMode( const CanNm_ChannelType* ChannelConf, CanNm_Internal_ChannelType* ChannelInternal );\r
+\r
+\r
+#endif /* CANNM_INTERNAL_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/** @req CANSM008 */\r
+\r
+#ifndef CANSM_H_\r
+#define CANSM_H_\r
+\r
+#include "ComStack_Types.h" /**< @req CANSM238 */\r
+#include "ComM.h"\r
+#include "CanSM_ConfigTypes.h"\r
+#include "Modules.h"\r
+\r
+#define CANSM_VENDOR_ID 1\r
+#define CANSM_MODULE_ID MODULE_ID_CANSM\r
+\r
+#define CANSM_AR_MAJOR_VERSION 1\r
+#define CANSM_AR_MINOR_VERSION 0\r
+#define CANSM_AR_PATCH_VERSION 1\r
+\r
+#define CANSM_SW_MAJOR_VERSION 1\r
+#define CANSM_SW_MINOR_VERSION 0\r
+#define CANSM_SW_PATCH_VERSION 0\r
+\r
+#include "CanSM_Cfg.h" /**< @req CANSM239 @req CANSM025.configuration */\r
+\r
+\r
+#define CANSM_E_UNINIT 0x01 /**< API service used without module initialization */\r
+#define CANSM_E_PARAM_POINTER 0x02 /**< API service called with wrong pointer */\r
+#define CANSM_E_INVALID_NETWORK_HANDLE 0x03 /**< API service called with wrong parameter */\r
+#define CANSM_E_INVALID_NETWORK_MODE 0x04 /**< API service called with wrong parameter */\r
+\r
+\r
+#define CANSM_SERVICEID_INIT 0x00\r
+#define CANSM_SERVICEID_GETVERSIONINFO 0x01\r
+#define CANSM_SERVICEID_REQUESTCOMMODE 0x02\r
+#define CANSM_SERVICEID_GETCURRENTCOMMODE 0x03\r
+#define CANSM_SERVICEID_CONTROLLERBUSOFF 0x04\r
+#define CANSM_SERVICEID_MAINFUNCTION 0x05\r
+\r
+\r
+/** This type shall define the states of the network mode state machine. */\r
+typedef enum {\r
+ CANSM_UNINITED,\r
+ CANSM_NO_COMMUNICATION,\r
+ CANSM_SILENT_COMMUNICATION,\r
+ CANSM_FULL_COMMUNICATION\r
+} CanSM_NetworkModeStateType;\r
+\r
+/** This type shall define the states of the bus-off recovery state machine. */\r
+typedef enum {\r
+ CANSM_BOR_IDLE, /**< Idle state */\r
+ CANSM_BOR_CHECK, /**< Initial bus-off check at beginning of full-communication */\r
+ CANSM_BOR_NO_BUS_OFF, /**< Regular state during full-communication without detected bus-off events */\r
+ CANSM_BOR_TXOFF_L1, /**< Bus-off recovery level 1 state, TX disabled */\r
+ CANSM_BOR_CHECK_L1, /**< Bus-off recovery level 1 state, TX enabled again */\r
+ CANSM_BOR_TXOFF_L2, /**< Bus-off recovery level 2 state, TX disabled */\r
+ CANSM_BOR_CHECK_L2 /**< Bus-off recovery level 2 state, TX enabled again */\r
+} CanSM_BusOffRecoveryStateType; /** @req CANSM169 */\r
+\r
+/** @req CANSM037 */\r
+\r
+/** This service initializes the CanSM module */\r
+/** @req CANSM023 */\r
+void CanSM_Init( const CanSM_ConfigType* ConfigPtr );\r
+\r
+/** This service puts out the version information of this module */\r
+/** @req CANSM024 @req CANSM180 */\r
+#if (CANSM_VERSION_INFO_API == STD_ON)\r
+#define CanSM_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,CANSM)\r
+#endif\r
+\r
+/** This service shall change the communication mode of a CAN network to the requested one. */\r
+/** @req CANSM062 */\r
+Std_ReturnType CanSM_RequestComMode( NetworkHandleType NetworkHandle, ComM_ModeType ComM_Mode );\r
+\r
+/** This service shall put out the current communication mode of a CAN network. */\r
+/** @req CANSM063 */\r
+Std_ReturnType CanSM_GetCurrentComMode( NetworkHandleType NetworkHandle, ComM_ModeType* ComM_ModePtr );\r
+\r
+\r
+/** Scheduled function of the CanSM */\r
+/** @req CANSM065 */\r
+void CanSM_MainFunction(void);\r
+\r
+\r
+\r
+\r
+\r
+#endif /* CANSM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CANSM_CBK_H_\r
+#define CANSM_CBK_H_\r
+\r
+/** @req CANSM011 */\r
+\r
+/** The CanSM is notified about a bus-off event on a certain CAN controller with this\r
+ * call-out function. It shall execute the bus-off recovery state machine for the\r
+ * corresponding network handle. */\r
+void CanSM_ControllerBusOff( uint8 Controller );\r
+\r
+#endif /* CANSM_CBK_H_ */\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#ifndef CANSM_COMM_H_\r
+#define CANSM_COMM_H_\r
\r
\r
-\r
-\r
-\r
-\r
-#ifndef COMM_NM_H_\r
-#define COMM_NM_H_\r
-\r
-#endif /*COMM_NM_H_*/\r
+#endif /* CANSM_COMM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef CANSM_CONFIGTYPES_H_\r
+#define CANSM_CONFIGTYPES_H_\r
+\r
+/** @req CANSM010.bswbuilder */\r
+\r
+#include "Com.h"\r
+\r
+typedef struct {\r
+ const uint8 CanIfControllerId;\r
+} CanSM_ControllerType;\r
+\r
+typedef struct {\r
+ const CanSM_ControllerType* Controllers;\r
+ const uint8 ControllerCount;\r
+ const uint8 ComMNetworkHandle;\r
+ const Com_PduGroupIdType ComRxPduGroupId; /**< @req CANSM091 */\r
+ const Com_PduGroupIdType ComTxPduGroupId;\r
+} CanSM_NetworkType;\r
+\r
+typedef struct {\r
+ const CanSM_NetworkType* Networks;\r
+} CanSM_ConfigType; /**< @req CANSM061 */\r
+\r
+#endif /* CANSM_CONFIGTYPES_H_ */\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#ifndef CANSM_ECUM_H_\r
+#define CANSM_ECUM_H_\r
\r
-#ifndef NVM_CFG_H_\r
-#define NVM_CFG_H_\r
\r
-#include "NvM_Types.h"\r
-\r
-#endif /*NVM_CFG_H_*/\r
+#endif /* CANSM_ECUM_H_ */\r
#ifndef CANTP_H_\r
#define CANTP_H_\r
\r
+#define CANTP_MODULE_ID MODULE_ID_CANTP /** @req CANTP115 */\r
+#define CANTP_VENDOR_ID 1\r
+\r
#define CANTP_SW_MAJOR_VERSION 1\r
#define CANTP_SW_MINOR_VERSION 0\r
#define CANTP_SW_PATCH_VERSION 0\r
#include "ComStack_Types.h"\r
#include "Std_Types.h"\r
#include "CanTp_Cfg.h" /** @req CANTP221 */\r
-//#include "Dem.h" // TODO: req: CanTp156\r
+//#include "Dem.h"\r
\r
/*\r
*\r
* Errors described by CanTp 7.4 Error classification.\r
*\r
****************************/\r
-\r
+/** @req CANTP101 */\r
#define CANTP_E_PARAM_CONFIG 0x01\r
#define CANTP_E_PARAM_ID 0x02\r
#define CANTP_E_PARAM_ADDRESS 0x04\r
* Implemented functions\r
****************************/\r
\r
-void CanTp_Init(); /** req : CanTp208 **/\r
+void CanTp_Init(void); /** @req CANTP208 **/\r
\r
-void CanTp_GetVersionInfo( Std_VersionInfoType* versioninfo ); /** req : CanTp210 **/\r
+#if ( CANTP_VERSION_INFO_API == STD_ON ) /** @req CANTP162 *//** @req CANTP163 */\r
+#define CanTp_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,CANTP) /** @req CANTP210 */ /* @req CANTP218 */\r
+#endif /* CANTP_VERSION_INFO_API */\r
\r
-void CanTp_Shutdown();\r
+void CanTp_Shutdown(void); /** @req CANTP211 */\r
\r
-Std_ReturnType CanTp_Transmit( PduIdType CanTpTxSduId, const PduInfoType * CanTpTxInfoPtr );\r
+Std_ReturnType CanTp_Transmit( PduIdType CanTpTxSduId, const PduInfoType * CanTpTxInfoPtr ); /** @req CANTP212 */\r
\r
-Std_ReturnType FrTp_CancelTransmitRequest( PduIdType FrTpTxPduId, FrTp_CancelReasonType FrTpCancelReason );\r
+Std_ReturnType FrTp_CancelTransmitRequest( PduIdType FrTpTxPduId, FrTp_CancelReasonType FrTpCancelReason ); /** @req CANTP246 */\r
\r
-void CanTp_MainFunction();\r
+void CanTp_MainFunction(void); /** @req CANTP213 */\r
\r
\r
#endif /* CANTP_H_ */\r
#include "ComStack_Types.h"\r
\r
\r
-void CanTp_RxIndication( PduIdType CanTpRxPduId, const PduInfoType *CanTpRxPduPtr );\r
+void CanTp_RxIndication( PduIdType CanTpRxPduId, const PduInfoType *CanTpRxPduPtr ); /** @req CANTP214 */\r
\r
-void CanTp_TxConfirmation( PduIdType CanTpTxPduId );\r
+void CanTp_TxConfirmation( PduIdType CanTpTxPduId ); /** @req CANTP215 */\r
\r
\r
#endif /* CANTP_CBK_H_ */\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+/*\r
+ * General requirements\r
+ */\r
/** @req CANTP160 */\r
\r
+/*\r
+ * Definitions generated by tools
+ */\r
+/** @req CANTP239 */\r
+/** @req CANTP242 */\r
+\r
+//lint -save -e451 //PC-Lint Wrong interpretation, "Platform_Types.h included twice without a standard include guard."\r
+\r
#ifndef CANTP_TYPES_H_\r
#define CANTP_TYPES_H_\r
\r
CANTP_OFF, CANTP_ON\r
} CanTp_StateType;\r
\r
-typedef enum { /* req: CanTp030 */\r
+typedef enum {\r
CANTP_RX_WAIT,\r
CANTP_RX_PROCESSING,\r
CANTP_TX_WAIT,\r
\r
\r
typedef struct {\r
- uint32 CanTpNSa; /** req: CanTp254 */\r
-} CanTp_NSaType; /** req: CanTp256: .. */\r
+ uint32 CanTpNSa; /** @req CANTP254 */\r
+} CanTp_NSaType; /** @req CANTP253 */\r
\r
typedef struct {\r
- uint32 CanTpNTa; /** req: CanTp255 */\r
-} CanTp_NTaType;\r
+ uint32 CanTpNTa; /** @req CANTP255 */\r
+} CanTp_NTaType; /** @req CANTP139 */\r
\r
typedef struct {\r
- const uint32 CanTpRxNPduId; /** req: CanTp258: */\r
- const uint32 CanTpRxNPduRef; /** req: CanTp257: */\r
-} CanTp_RxNPduType;\r
+ const uint32 CanTpRxNPduId; /** @req CANTP258 */\r
+ const uint32 CanTpRxNPduRef; /** @req CANTP257 */\r
+} CanTp_RxNPduType; /** @req CANTP256 */\r
\r
typedef struct {\r
- const uint32 CanTpTxNPduId; /** req: CanTp258: */\r
- const uint32 CanTpTxNPduRef; /** req: CanTp257: */\r
-} CanTp_TxNPduType;\r
+ const uint32 CanTpTxNPduId; /* TODO: Remove this? */\r
+ const uint32 CanTpTxNPduRef; /** @req CANTP275 */\r
+} CanTp_TxNPduType; /** @req CANTP274 */\r
\r
typedef struct {\r
- const uint32 CanTpTxFcNPduRef; /** req: CanTp259: Reference to a PDU in the COM stack. */\r
-} CanTp_TxFcNPduType;\r
+ const uint32 CanTpTxFcNPduRef; /** @req CANTP260 */ /* Reference to a PDU in the COM stack. */\r
+} CanTp_TxFcNPduType; /** @req CANTP259 */\r
\r
typedef struct {\r
- const uint32 CanTpRxFcNPduRef; /** req: CanTp259: Reference to a PDU in the COM stack. */\r
- const uint32 CanTpRxFcNPduId; /** req: CanTp274: */\r
-} CanTp_RxFcNPduType;\r
+ const uint32 CanTpRxFcNPduRef; /** @req CANTP272 */ /* Reference to a PDU in the COM stack. */\r
+ const uint32 CanTpRxFcNPduId; /** @req CANTP273 */\r
+} CanTp_RxFcNPduType; /** @req CANTP271 */\r
\r
\r
typedef struct {\r
- const int CanIf_FcPduId; // The polite CanIf PDU index.\r
- const int PduR_PduId; // The polite PduR index.\r
- const CanTp_AddressingFormantType CanTpAddressingFormant;\r
- const uint8 CanTpBs; /** req: CanTp243: Sets the maximum number of messages of N-PDUs before flow control. */\r
- const uint16 CanTpNar; /** req: CanTp244: Timeout for transmission of a CAN frame (ms). */\r
- const uint16 CanTpNbr; /** req: CanTp245: ?? */\r
- const uint16 CanTpNcr; /** req: CanTp246: Time out for consecutive frames (ms). */\r
- const uint8 CanTpRxChannel; /* Connection to runtime variable index, see CanTp 266. */\r
- const uint16 CanTpRxDI; /** req: CanTp248: Data length code for of this RxNsdu. */\r
- CanTp_StateType CanTpRxPaddingActivation; /** req: CanTp249: Enable use of padding. */\r
- CanTp_TaTypeType CanTpRxTaType; /** req: CanTp250: Functional or physical addressing. */\r
- const uint8 CanTpWftMax; /** req: CanTp251: Max number FC wait that can be transmitted consecutively. */\r
- const uint16 CanTpSTmin; /** req: CanTp252: Minimum time the sender shall wait between transmissions of two N-PDU. */\r
+ const PduIdType CanIf_FcPduId; // The polite CanIf PDU index.\r
+ const PduIdType PduR_PduId; // The polite PduR index.\r
+ const CanTp_AddressingFormantType CanTpAddressingFormant; /** @req CANTP242 */\r
+ const uint8 CanTpBs; /** @req CANTP243 */ /* Sets the maximum number of messages of N-PDUs before flow control. */\r
+ const uint16 CanTpNar; /** @req CANTP244 */ /* Timeout for transmission of a CAN frame (ms). */\r
+ const uint16 CanTpNbr; /** @req CANTP245 */\r
+ const uint16 CanTpNcr; /** @req CANTP246 */ /* Time out for consecutive frames (ms). */\r
+ const uint8 CanTpRxChannel; /** @req CANTP247 */ /* Connection to runtime variable index, see CanTp 266. */\r
+ const uint16 CanTpRxDI; /** @req CANTP248 */ /* Data length code for of this RxNsdu. */\r
+ CanTp_StateType CanTpRxPaddingActivation; /** @req CANTP249 */ /* Enable use of padding. */\r
+ CanTp_TaTypeType CanTpRxTaType; /** @req CANTP250 */ /* Functional or physical addressing. */\r
+ const uint8 CanTpWftMax; /** @req CANTP251 */ /* Max number FC wait that can be transmitted consecutively. */\r
+ const uint16 CanTpSTmin; /** @req CANTP252 */ /* Minimum time the sender shall wait between transmissions of two N-PDU. */\r
/*const uint32 CanTpNSduRef ** req: CanTp241. This is PDU id - typeless enum. */\r
const CanTp_NSaType *CanTpNSa;\r
const CanTp_NTaType *CanTpNTa;\r
//CanTp_TxFcNPduType *CanTpTxFcNPdu;\r
//const PduIdType CanTpRxPduId;\r
\r
-} CanTp_RxNSduType;\r
+} CanTp_RxNSduType; /** @req CANTP137 */\r
\r
typedef struct {\r
- const int CanIf_PduId; // The polite CanIf index.\r
- const int PduR_PduId; // The polite PduR index.\r
- const CanTp_AddressingFormantType CanTpAddressingMode; /** req: CanTp138: */\r
- const uint16 CanTpNas; /** req: CanTp263: N_As timeout for transmission of any CAN frame. */\r
- const uint16 CanTpNbs; /** req: CanTp264: N_Bs timeout of transmission until reception of next Flow Control. */\r
- const uint16 CanTpNcs; /** req: CanTp265: N_Bs timeout of transmission until reception of next Flow Control. */\r
- const uint8 CanTpTxChannel; /** req: CanTp266: Link to the TX connection channel (why?). */\r
- const uint16 CanTpTxDI; /** req: CanTp267: Data length code for of this TxNsdu. */\r
+ const PduIdType CanIf_PduId; // The polite CanIf index.\r
+ const PduIdType PduR_PduId; // The polite PduR index.\r
+ const CanTp_AddressingFormantType CanTpAddressingMode; /** @req CANTP262 */\r
+ const uint16 CanTpNas; /** @req CANTP263 */ /* N_As timeout for transmission of any CAN frame. */\r
+ const uint16 CanTpNbs; /** @req CANTP264 */ /* N_Bs timeout of transmission until reception of next Flow Control. */\r
+ const uint16 CanTpNcs; /** @req CANTP265 */ /* N_Bs timeout of transmission until reception of next Flow Control. */\r
+ const uint8 CanTpTxChannel; /** @req CANTP266 */ /* Link to the TX connection channel (why?). */\r
+ const uint16 CanTpTxDI; /** @req CANTP267 */ /* Data length code for of this TxNsdu. */\r
/*const uint32 CanTpTxNSduId; / ** req: CanTp268: Data length code for of this TxNsdu. */\r
- CanTp_StateType CanTpTxPaddingActivation; /** req: CanTp249: Enable use of padding. */\r
- CanTp_TaTypeType CanTpTxTaType; /** req: CanTp270: Functional or physical addressing. */\r
+ CanTp_StateType CanTpTxPaddingActivation; /** @req CANTP269 */ /* Enable use of padding. */\r
+ CanTp_TaTypeType CanTpTxTaType; /** @req CANTP270 */ /* Functional or physical addressing. */\r
/*const uint32 CanTpNSduRef ** req: CanTp261. This is PDU id - typeless enum. */\r
const CanTp_NSaType *CanTpNSa;\r
const CanTp_NTaType *CanTpNTa;\r
//CanTp_TxNPduType *CanTpTxNPdu;\r
//PduIdType CanTpTxPduId;\r
\r
-} CanTp_TxNSduType; /** req: CanTp138: */\r
+} CanTp_TxNSduType; /** @req CANTP138 */\r
\r
// - - - - - - - - - - -\r
\r
-// These constants needs to move later.\r
-#define CANTP_DEV_ERROR_DETECT STD_ON /** req: CanTp239, development error detection on/off. */\r
-#define CANTP_MAIN_FUNCTION_PERIOD 0.1250 /** req: CanTp240, allow to configure time for MainFunction. */\r
-#define CANTP_TC STD_ON /** req: CanTp242, enabling transmit Cancellation. */\r
-\r
typedef struct {\r
- uint32 main_function_period; /** req: CanTp240: ?? */\r
-} CanTp_GeneralType;\r
+ uint32 main_function_period; /** @req CANTP240 */\r
+} CanTp_GeneralType; /** @req CANTP238 */\r
\r
// - - - - - - - - - - -\r
\r
\r
#include "Std_Types.h"\r
#include "ComStack_Types.h"\r
-#include "Com_Arc_Types.h"\r
\r
\r
-#ifdef COM_DEV_ERROR_DETECT\r
-#include "Det.h"\r
-#endif\r
-\r
#define COM_SW_MAJOR_VERSION 1\r
-#define COM_SW_MINOR_VERSION 0\r
+#define COM_SW_MINOR_VERSION 1\r
#define COM_SW_PATCH_VERSION 0\r
\r
#include "Com_Cfg.h"\r
#include "Com_Types.h"\r
#include "Com_PbCfg.h"\r
+//#include "Com_Internal.h" //TODO: Remove completely?\r
#include "Com_Com.h"\r
#include "Com_Sched.h"\r
\r
-const Com_ConfigType * ComConfig;\r
-\r
-Com_Arc_Config_type Com_Arc_Config;\r
-\r
-\r
-\r
-#ifdef COM_DEV_ERROR_DETECT\r
-\r
-#undef DET_REPORTERROR\r
-#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)\r
-\r
-\r
-// Define macro for parameter check.\r
-#define PduIdCheck(PduId,ApiId,...) \\r
- if (PduId >= Com_Arc_Config.ComNIPdu) { \\r
- DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_INVALID_PDU_ID); \\r
- return __VA_ARGS__; \\r
- } \\r
-\r
-#define COM_VALIDATE_SIGNAL(SignalId, ApiId, ...) \\r
- if (ComConfig->ComSignal[SignalId].Com_Arc_IsSignalGroup) { \\r
- DET_REPORTERROR(COM_MODULE_ID, COM_INSTANCE_ID, ApiId, COM_ERROR_SIGNAL_IS_SIGNALGROUP); \\r
- return __VA_ARGS__; \\r
- } \\r
-\r
-\r
-#else\r
-\r
-#undef DET_REPORTERROR\r
-#define DET_REPORTERROR(_x,_y,_z,_q)\r
-\r
-#define PduIdCheck(PduId,ApiId,...)\r
-#define COM_VALIDATE_SIGNAL(PduId, ApiId, ...)\r
-#endif\r
-\r
-\r
-#define testBit(source,bit) (*((uint8 *)source + (bit / 8)) & (1 << (bit % 8)))\r
-#define setBit(dest,bit) *((uint8 *)dest + (bit / 8)) |= (1 << (bit % 8))\r
-#define clearBit(dest,bit) *((uint8 *)dest + (bit / 8)) &= ~(1 << (bit % 8))\r
-\r
-#define ComGetSignal(SignalId) \\r
- const ComSignal_type * Signal = &ComConfig->ComSignal[SignalId]\\r
-\r
-#define ComGetArcSignal(SignalId) \\r
- Com_Arc_Signal_type * Arc_Signal = &Com_Arc_Config.ComSignal[SignalId]\\r
-\r
-#define ComGetIPdu(IPduId) \\r
- const ComIPdu_type *IPdu = &ComConfig->ComIPdu[IPduId]\\r
-\r
-#define ComGetArcIPdu(IPduId) \\r
- Com_Arc_IPdu_type *Arc_IPdu = &Com_Arc_Config.ComIPdu[IPduId]\\r
-\r
-#define ComGetGroupSignal(GroupSignalId) \\r
- const ComGroupSignal_type *GroupSignal = &ComConfig->ComGroupSignal[GroupSignalId]\\r
-\r
-#define ComGetArcGroupSignal(GroupSignalId) \\r
- Com_Arc_GroupSignal_type *Arc_GroupSignal = &Com_Arc_Config.ComGroupSignal[GroupSignalId]\\r
-\r
//-------------------------------------------------------------------\r
// From OSEK_VDX spec...\r
//\r
\r
\r
// From Autosar\r
-void Com_Init( const Com_ConfigType * ConfigPtr);\r
-void Com_DeInit( void );\r
+void Com_Init(const Com_ConfigType * config);\r
+void Com_DeInit(void);\r
\r
void Com_IpduGroupStart(Com_PduGroupIdType IpduGroupId, boolean Initialize);\r
void Com_IpduGroupStop(Com_PduGroupIdType IpduGroupId);\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+#ifndef COMM_H\r
+#define COMM_H\r
+\r
+/** @req COMM466 @req COMM518 @req COMM692 */\r
+#include "ComStack_Types.h"\r
+#include "ComM_Types.h"\r
+#include "ComM_ConfigTypes.h"\r
+#include "Modules.h"\r
+\r
+#define COMM_MODULE_ID MODULE_ID_COMM\r
+#define COMM_VENDOR_ID 1\r
+\r
+/** @req COMM469 */\r
+#define COMM_AR_MAJOR_VERSION 2\r
+#define COMM_AR_MINOR_VERSION 0\r
+#define COMM_AR_PATCH_VERSION 1\r
+\r
+#define COMM_SW_MAJOR_VERSION 1\r
+#define COMM_SW_MINOR_VERSION 0\r
+#define COMM_SW_PATCH_VERSION 0\r
+\r
+/** @req COMM328 @req COMM456 */\r
+#include "ComM_Cfg.h"\r
+\r
+/** Function call has been successfully but mode can not\r
+ * be granted because of mode inhibition. */\r
+#define COMM_E_MODE_LIMITATION 2\r
+\r
+/** ComM not initialized */\r
+/** @req COMM650 */\r
+#define COMM_E_UNINIT 3\r
+\r
+#define COMM_E_NOT_INITED 0x1 /**< API service used without module initialization */\r
+#define COMM_E_WRONG_PARAMETERS 0x2 /**< API service used with wrong parameters (e.g. a NULL pointer) */\r
+#define COMM_E_ERROR_IN_PROV_SERVICE 0x3 /**< Provided API services of other modules returned with an error. */\r
+\r
+#define COMM_SERVICEID_INIT 0x01\r
+#define COMM_SERVICEID_DEINIT 0x02\r
+#define COMM_SERVICEID_GETSTATUS 0x03\r
+#define COMM_SERVICEID_GETINHIBITIONSTATUS 0x04\r
+#define COMM_SERVICEID_REQUESTCOMMODE 0x05\r
+#define COMM_SERVICEID_GETMAXCOMMODE 0x06\r
+#define COMM_SERVICEID_GETREQUESTEDCOMMODE 0x07\r
+#define COMM_SERVICEID_GETCURRENTCOMMODE 0x08\r
+#define COMM_SERVICEID_PREVENTWAKEUP 0x09\r
+#define COMM_SERVICEID_LIMITCHANNELTONOCOMMODE 0x0b\r
+#define COMM_SERVICEID_LIMITECUTONOCOMMODE 0x0c\r
+#define COMM_SERVICEID_READINHIBITCOUNTER 0x0d\r
+#define COMM_SERVICEID_RESETINHIBITCOUNTER 0x0e\r
+#define COMM_SERVICEID_SETECUGROUPCLASSIFICATION 0x0f\r
+#define COMM_SERVICEID_GETVERSIONINFO 0x10\r
+#define COMM_SERVICEID_NM_NETWORKSTARTINDICATION 0x15\r
+#define COMM_SERVICEID_NM_NETWORKMODE 0x18\r
+#define COMM_SERVICEID_NM_PREPAREBUSSLEEPMODE 0x19\r
+#define COMM_SERVICEID_NM_BUSSLEEPMODE 0x1a\r
+#define COMM_SERVICEID_NM_RESTARTINDICATION 0x1b\r
+#define COMM_SERVICEID_DCM_ACTIVEDIAGNOSTIC 0x1f\r
+#define COMM_SERVICEID_DCM_INACTIVEDIAGNOSTIC 0x20\r
+#define COMM_SERVICEID_ECUM_RUNMODEINDICATION 0x29\r
+#define COMM_SERVICEID_ECUM_WAKEUPINDICATION 0x2a\r
+#define COMM_SERVICEID_BUSSM_MODEINDICATION 0x33\r
+#define COMM_SERVICEID_MAINFUNCTION 0x60\r
+\r
+\r
+#define COMM_MAIN_FUNCTION_PROTOTYPE(channel) \\r
+void ComM_MainFunction_##channel (void)\r
+\r
+#define COMM_MAIN_FUNCTION(channel) \\r
+void ComM_MainFunction_##channel (void) { \\r
+ ComM_MainFunction(COMM_NETWORK_HANDLE_##channel); \\r
+}\r
+\r
+\r
+/** Initializes the AUTOSAR Communication Manager and restarts the internal state machines.*/\r
+void ComM_Init(const ComM_ConfigType* Config); /**< @req COMM146 */\r
+\r
+/** De-initializes (terminates) the AUTOSAR Communication Manager. */\r
+void ComM_DeInit(void); /**< @req COMM147 */\r
+\r
+/** @req COMM370 */\r
+#if (COMM_VERSION_INFO_API == STD_ON)\r
+#define ComM_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,COMM)\r
+#endif\r
+\r
+/** Returns the initialization status of the AUTOSAR Communication Manager. */\r
+Std_ReturnType ComM_GetStatus( ComM_InitStatusType* Status ); /**< @req COMM242 */\r
+Std_ReturnType ComM_GetInhibitionStatus( NetworkHandleType Channel, ComM_InhibitionStatusType* Status ); /**< @req COMM619 */\r
+\r
+Std_ReturnType ComM_RequestComMode( ComM_UserHandleType User, ComM_ModeType ComMode ); /**< @req COMM110 */\r
+Std_ReturnType ComM_GetMaxComMode( ComM_UserHandleType User, ComM_ModeType* ComMode );\r
+Std_ReturnType ComM_GetRequestedComMode( ComM_UserHandleType User, ComM_ModeType* ComMode ); /**< @req COMM79 */\r
+Std_ReturnType ComM_GetCurrentComMode( ComM_UserHandleType User, ComM_ModeType* ComMode ); /**< @req COMM83 */\r
+\r
+Std_ReturnType ComM_PreventWakeUp( NetworkHandleType Channel, boolean Status ); /**< @req COMM156 */\r
+Std_ReturnType ComM_LimitChannelToNoComMode( NetworkHandleType Channel, boolean Status ); /**< @req COMM163 */\r
+Std_ReturnType ComM_LimitECUToNoComMode( boolean Status ); /**< @req COMM124 */\r
+Std_ReturnType ComM_ReadInhibitCounter( uint16* CounterValue ); /**< @req COMM224 */\r
+Std_ReturnType ComM_ResetInhibitCounter(void); /**< @req COMM108 */\r
+Std_ReturnType ComM_SetECUGroupClassification( ComM_InhibitionStatusType Status );\r
+\r
+\r
+#endif /*COMM_H*/\r
#include "ComStack_Types.h"\r
#include "ComM_Types.h"\r
\r
-void ComM_BusSM_ModeIndication(NetworkHandleType Channel,ComM_ModeType ComMode);\r
+void ComM_BusSM_ModeIndication( NetworkHandleType Channel,ComM_ModeType ComMode );\r
\r
#endif /*COMM_BUSSM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef COMM_CONFIGTYPES_H_\r
+#define COMM_CONFIGTYPES_H_\r
+\r
+/* Configuration requirements */\r
+/** @req COMM554.bswbuilder @req COMM555.bswbuilder @req COMM563.bswbuilder @req COMM560.bswbuilder\r
+ * @req COMM561.bswbuilder @req COMM557.bswbuilder @req COMM622.bswbuilder @req COMM653.bswbuilder\r
+ * @req COMM654.bswbuilder @req COMM565.bswbuilder @req COMM567.bswbuilder @req COMM635.bswbuilder\r
+ * @req COMM556.bswbuilder @req COMM607.bswbuilder @req COMM606.bswbuilder @req COMM568.bswbuilder\r
+ * @req COMM657.bswbuilder @req COMM658.bswbuilder @req COMM246.bswbuilder */\r
+\r
+typedef enum {\r
+ COMM_BUS_TYPE_CAN,\r
+ COMM_BUS_TYPE_FR,\r
+ COMM_BUS_TYPE_INTERNAL,\r
+ COMM_BUS_TYPE_LIN\r
+} ComM_BusTypeType;\r
+\r
+typedef enum {\r
+ COMM_NM_VARIANT_NONE,\r
+ COMM_NM_VARIANT_LIGHT,\r
+ COMM_NM_VARIANT_PASSIVE,\r
+ COMM_NM_VARIANT_FULL\r
+} ComM_NmVariantType;\r
+\r
+typedef struct {\r
+ const ComM_BusTypeType BusType; /**< @req COMM322 */\r
+ const NetworkHandleType BusSMNetworkHandle;\r
+ const NetworkHandleType NmChannelHandle;\r
+ const ComM_NmVariantType NmVariant;\r
+ const uint32 MainFunctionPeriod;\r
+ const uint32 LightTimeout;\r
+ const uint8 Number;\r
+} ComM_ChannelType;\r
+\r
+\r
+typedef struct {\r
+ /** @req COMM795 @req COMM796 @req COMM797 @req COMM798 @req COMM327 @req COMM159 */\r
+ const ComM_ChannelType** ChannelList;\r
+ const uint8 ChannelCount;\r
+} ComM_UserType;\r
+\r
+typedef struct {\r
+ const ComM_ChannelType* Channels;\r
+ const ComM_UserType* Users;\r
+} ComM_ConfigType;\r
+\r
+#endif /* COMM_CONFIGTYPES_H_ */\r
\r
\r
\r
-#ifndef COMM_DCM_H_\r
-#define COMM_DCM_H_\r
+#ifndef COMM_DCM_H\r
+#define COMM_DCM_H\r
\r
-#endif /*COMM_DCM_H_*/\r
+void ComM_DCM_ActiveDiagnostic(void);\r
+void ComM_DCM_InactiveDiagnostic(void);\r
+\r
+#endif /*COMM_DCM_H*/\r
\r
\r
\r
-#ifndef COMM_ECUM_H_\r
-#define COMM_ECUM_H_\r
+#ifndef COMM_ECUM_H\r
+#define COMM_ECUM_H\r
\r
-#endif /*COMM_ECUM_H_*/\r
+void ComM_EcuM_RunModeIndication( NetworkHandleType Channel );\r
+void ComM_EcuM_WakeUpIndication( NetworkHandleType Channel );\r
+\r
+#endif /*COMM_ECUM_H*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifndef COMM_NM_H_\r
+#define COMM_NM_H_\r
+\r
+void ComM_Nm_NetworkStartIndication( NetworkHandleType Channel ); /**< @req COMM383 */\r
+void ComM_Nm_NetworkMode( NetworkHandleType Channel ); /**< @req COMM390 */\r
+void ComM_Nm_PrepareBusSleepMode( NetworkHandleType Channel ); /**< @req COMM391 */\r
+void ComM_Nm_BusSleepMode( NetworkHandleType Channel ); /**< @req COMM392 */\r
+void ComM_Nm_RestartIndication( NetworkHandleType Channel ); /**< @req COMM792 */\r
+\r
+#endif /*COMM_NM_H_*/\r
\r
\r
\r
-#ifndef COMM_TYPES_H_\r
-#define COMM_TYPES_H_\r
+#ifndef COMM_TYPES_H\r
+#define COMM_TYPES_H\r
\r
+/** Current mode of the Communication Manager (main state of the state machine). */\r
+/** @req COMM484 @req COMM190 @req COMM248 */\r
typedef enum {\r
-COMM_NO_COMMUNICATION,\r
-COMM_SILENT_COMMUNICATION,\r
-COMM_FULL_COMMUNICATION,\r
-}ComM_ModeType;\r
+ COMM_NO_COMMUNICATION = 0,\r
+ COMM_SILENT_COMMUNICATION = 1,\r
+ COMM_FULL_COMMUNICATION = 2\r
+} ComM_ModeType;\r
\r
-#endif /*COMM_TYPES_H_*/\r
+/** Initialization status of ComM. */\r
+typedef enum {\r
+ COMM_UNINIT,\r
+ COMM_INIT\r
+} ComM_InitStatusType; /**< @req COMM494 */\r
+\r
+/** Inhibition status of ComM. */\r
+typedef uint8 ComM_InhibitionStatusType; /**< @req COMM496 */\r
+\r
+#define COMM_INHIBITION_STATUS_NONE (0u)\r
+/** Wake Up inhibition active */\r
+#define COMM_INHIBITION_STATUS_WAKE_UP (1u)\r
+/** Limit to \93No Communication\94 mode active */\r
+#define COMM_INHIBITION_STATUS_NO_COMMUNICATION (uint8)(1u << 1)\r
+\r
+#endif /*COMM_TYPES_H*/\r
\r
#include "Std_Types.h"\r
\r
-// Proposed by Mattias\r
-// We need a place to store the global PDU ids?\r
-#include "ComGlobals.h"\r
-\r
\r
// Zero-based integer number\r
// The size of this global type depends on the maximum\r
BUFREQ_OK=0,\r
BUFREQ_NOT_OK,\r
BUFREQ_BUSY,\r
- BUFREQ_OVFL,\r
+ BUFREQ_OVFL\r
} BufReq_ReturnType;\r
\r
// 0x00--0x1e General return types\r
#define COM_COM_H_\r
\r
#include "Com.h"\r
-#include "Com_misc.h"\r
#include "PduR.h"\r
\r
uint8 Com_SendSignal(Com_SignalIdType SignalId, const void *SignalDataPtr);\r
\r
void Com_TriggerIPduSend(PduIdType ComTxPduId);\r
\r
-Std_ReturnType Com_RxIndication(PduIdType ComRxPduId, const uint8* PduInfoPtr);\r
+void Com_RxIndication(PduIdType ComRxPduId, const uint8* SduPtr); // TODO: Parameter SduPtr should be const PduInfoType* PduInfoPtr\r
void Com_TxConfirmation(PduIdType ComTxPduId);\r
\r
\r
\r
#include "Com.h"\r
\r
-void Com_MainFunctionRx();\r
-void Com_MainFunctionTx();\r
+void Com_MainFunctionRx(void);\r
+void Com_MainFunctionTx(void);\r
\r
// Not supported in this version.\r
//void Com_MainFunctionRouteSignals();\r
\r
typedef enum {\r
IMMEDIATE,\r
- DEFERRED,\r
+ DEFERRED\r
} Com_IPduSignalProcessingMode;\r
\r
typedef enum {\r
\r
typedef enum {\r
PENDING,\r
- TRIGGERED,\r
+ TRIGGERED\r
} ComTransferProperty_type;\r
\r
typedef enum {\r
DIRECT,\r
MIXED,\r
NONE,\r
- PERIODIC,\r
+ PERIODIC\r
} ComTxModeMode_type;\r
\r
\r
NEVER,\r
NEW_IS_OUTSIDE,\r
NEW_IS_WITHIN,\r
- ONE_EVERY_N,\r
+ ONE_EVERY_N\r
} ComFilterAlgorithm_type;\r
\r
typedef enum {\r
- BIG_ENDIAN,\r
- LITTLE_ENDIAN,\r
- OPAQUE,\r
+ COM_BIG_ENDIAN,\r
+ COM_LITTLE_ENDIAN,\r
+ COM_OPAQUE\r
} ComSignalEndianess_type;\r
\r
typedef enum {\r
type == SINT32 ? sizeof(sint32) : sizeof(boolean)) \\r
\r
#define SignalTypeSignedness(type) \\r
- ((type == SINT8 || type == SINT16 || type == SINT32) ? \\r
+ (( (type == SINT8) || (type == SINT16) || (type == SINT32) ) ? \\r
COM_SIGNALTYPE_SIGNED : COM_SIGNALTYPE_UNSIGNED)\r
\r
/** Filter configuration type.\r
/** Filter for this signal.\r
* NOT SUPPORTED\r
*/\r
- const ComFilter_type ComFilter;\r
+ //const ComFilter_type ComFilter;\r
\r
/* Pointer to the shadow buffer of the signal group that this group signal is contained in.\r
*\r
/** The number of bytes if the signal has type UINT8_N;\r
* Range 1 to 8.\r
*/\r
- const uint8 ComSignalLength;\r
+ //const uint8 ComSignalLength;\r
\r
/** Defines the type of the signal. */\r
const Com_SignalType ComSignalType;\r
/** Filter for this signal.\r
* NOT SUPPORTED.\r
*/\r
- const ComFilter_type ComFilter;\r
+ //const ComFilter_type ComFilter;\r
\r
/** Marks if this signal is a signal group.\r
* Should be set to 1 if the signal is a signal group.\r
/** Array of group signals.\r
* Only applicable if this signal is a signal group.\r
*/\r
- const ComGroupSignal_type **ComGroupSignal;\r
+ const ComGroupSignal_type * const *ComGroupSignal;\r
\r
\r
//void *Com_Arc_ShadowBuffer;\r
boolean (*ComIPduCallout)(PduIdType PduId, const uint8 *IPduData);\r
\r
\r
- /** The ID of this IPDU. */\r
- const uint8 ComIPduRxHandleId;\r
-\r
/** The outgoing PDU id. For polite PDU id handling. */\r
const uint8 ArcIPduOutgoingId;\r
\r
/** References to all signals and signal groups contained in this IPDU.\r
* It probably makes little sense not to define at least one signal or signal group for each IPDU.\r
*/\r
- const ComSignal_type **ComIPduSignalRef;\r
+ const ComSignal_type * const *ComIPduSignalRef;\r
\r
/*\r
* The following two variables are used to control the per I-PDU based Rx/Tx-deadline monitoring.\r
\r
/* REQ:COMPILER040,049,051 */\r
#define AUTOMATIC\r
-#define _STATIC_ static\r
+#define STATIC static\r
#define NULL_PTR ((void *)0)\r
\r
+#define CC_EXTENSION __extension__\r
+\r
/* REQ:COMPILER005 */\r
/* TODO: skip the memclass for now */\r
#define FUNC(rettype,memclass) rettype\r
#ifndef DCM_H_\r
#define DCM_H_\r
\r
+#define DCM_MODULE_ID MODULE_ID_DCM /** @req DCM052 */\r
+#define DCM_VENDOR_ID 1\r
+\r
#define DCM_SW_MAJOR_VERSION 1\r
#define DCM_SW_MINOR_VERSION 0\r
#define DCM_SW_PATCH_VERSION 0\r
#include "Dcm_Cbk.h"\r
\r
#if (DCM_DEV_ERROR_DETECT == STD_ON)\r
-// Error codes produced by this module\r
-#define DCM_E_CONFIG_INVALID 0x41\r
-#define DCM_E_UNEXPECTED_PARAM 0x42\r
+// Error codes produced by this module defined by Autosar\r
+#define DCM_E_INTERFACE_TIMEOUT 0x01\r
+#define DCM_E_INTERFACE_VALUE_OUT_OF_RANGE 0x02\r
+#define DCM_E_INTERFACE_BUFFER_OVERFLOW 0x03\r
+#define DCM_E_INTERFACE_PROTOCOL_MISMATCH 0x04\r
+#define DCM_E_UNINIT 0x05\r
+#define DCM_E_PARAM 0x06\r
+\r
+// Other error codes reported by this module\r
+#define DCM_E_CONFIG_INVALID 0x40\r
+#define DCM_E_NOT_SUPPORTED 0xfe\r
#define DCM_E_NOT_IMPLEMENTED_YET 0xff\r
\r
-// Service ID in this module\r
+// Service IDs in this module defined by Autosar\r
#define DCM_INIT_ID 0x01\r
-#define DCM_HANDLE_RESPONSE_TRANSMISSION 0x80\r
-#define DCM_UDS_READ_DTC_INFO 0x81\r
+#define DCM_PROVIDE_RX_BUFFER_ID 0x02\r
+#define DCM_RX_INDICATION_ID 0x03\r
+#define DCM_PROVIDE_TX_BUFFER_ID 0x04\r
+#define DCM_TX_CONFIRMATION_ID 0x05\r
+#define DCM_GET_SES_CTRL_TYPE_ID 0x06\r
+#define DCM_GET_SECURITY_LEVEL_ID 0x0d\r
+#define DCM_GET_ACTIVE_PROTOCOL_ID 0x0f\r
+#define DCM_COMM_NO_COM_MODE_ENTERED_ID 0x21\r
+#define DCM_COMM_SILENT_COM_MODE_ENTERED_ID 0x22\r
+#define DCM_COMM_FULL_COM_MODE_ENTERED_ID 0x23\r
+#define DCM_MAIN_ID 0x25\r
+\r
+// Other service IDs reported by this module\r
+#define DCM_HANDLE_RESPONSE_TRANSMISSION_ID 0x80\r
+#define DCM_UDS_READ_DTC_INFO_ID 0x81\r
+#define DCM_UDS_RESET_ID 0x82\r
+#define DCM_CHANGE_DIAGNOSTIC_SESSION_ID 0x88\r
#define DCM_GLOBAL_ID 0xff\r
\r
#endif\r
/*\r
* Interfaces for BSW components (8.3.1)\r
*/\r
-#if (DCM_VERSION_INFO_API == STD_ON)\r
-void Dcm_GetVersionInfo(Std_VersionInfoType *versionInfo);\r
+#if ( DCM_VERSION_INFO_API == STD_ON ) /** @req DCM337 */\r
+#define Dcm_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DCM) /** @req DCM065 */ /** @req DCM335 */ /** @req DCM336 */\r
#endif /* DCM_VERSION_INFO_API */\r
\r
-void Dcm_Init( void );\r
+void Dcm_Init( void ); /** @req DCM037 */\r
\r
\r
/*\r
* Interfaces for BSW modules and to SW-Cs (8.3.2)\r
*/\r
-Std_ReturnType Dcm_GetSecurityLevel(Dcm_SecLevelType *secLevel);\r
-Std_ReturnType Dcm_GetSesCtrlType(Dcm_SesCtrlType *sesCtrlType);\r
-Std_ReturnType Dcm_GetActiveProtocol(Dcm_ProtocolType *activeProtocol);\r
+Std_ReturnType Dcm_GetSecurityLevel(Dcm_SecLevelType *secLevel); /** @req DCM338 */\r
+Std_ReturnType Dcm_GetSesCtrlType(Dcm_SesCtrlType *sesCtrlType); /** @req DCM339 */\r
+Std_ReturnType Dcm_GetActiveProtocol(Dcm_ProtocolType *activeProtocol); /** @req DCM340 */\r
\r
/*\r
* Interface for basic software scheduler (8.5)\r
*/\r
-void Dcm_MainFunction( void );\r
+void Dcm_MainFunction( void ); /** @req DCM053 */\r
\r
\r
#endif /*DCM_H_*/\r
#ifndef DCM_CBK_H_\r
#define DCM_CBK_H_\r
\r
+//lint -e451 //451 PC-Lint OK. Slå av regel helt?\r
#include "ComStack_Types.h"\r
\r
/*\r
* Interfaces for callback notifications from PduR and ComM (8.4)\r
*/\r
-BufReq_ReturnType Dcm_ProvideRxBuffer(PduIdType dcmRxPduId, PduLengthType tpSduLength, PduInfoType **pduInfoPtr);\r
-void Dcm_RxIndication(PduIdType dcmRxPduId, NotifResultType result);\r
-BufReq_ReturnType Dcm_ProvideTxBuffer(PduIdType dcmTxPduId, PduInfoType **pduInfoPtr, PduLengthType length);\r
-void Dcm_TxConfirmation(PduIdType dcmTxPduId, NotifResultType result);\r
-void Dcm_ComM_NoComModeEntered(void);\r
-void Dcm_ComM_SilentComModeEntered(void);\r
-void Dcm_ComM_FullComModeEntered(void);\r
+BufReq_ReturnType Dcm_ProvideRxBuffer(PduIdType dcmRxPduId, PduLengthType tpSduLength, PduInfoType **pduInfoPtr); /** @req DCM094 */\r
+void Dcm_RxIndication(PduIdType dcmRxPduId, NotifResultType result); /** @req DCM093 */\r
+BufReq_ReturnType Dcm_ProvideTxBuffer(PduIdType dcmTxPduId, PduInfoType **pduInfoPtr, PduLengthType length); /** @req DCM092 */\r
+void Dcm_TxConfirmation(PduIdType dcmTxPduId, NotifResultType result); /** @req DCM351 */\r
+void Dcm_ComM_NoComModeEntered(void); /** @req DCM356 */\r
+void Dcm_ComM_SilentComModeEntered(void); /** @req DCM358 */\r
+void Dcm_ComM_FullComModeEntered(void); /** @req DCM360 */\r
\r
#endif /*DCM_CBK_H_*/\r
#ifndef DEM_H_\r
#define DEM_H_\r
\r
+#define DEM_MODULE_ID MODULE_ID_DEM\r
+#define DEM_VENDOR_ID 1\r
+\r
#define DEM_SW_MAJOR_VERSION 1\r
#define DEM_SW_MINOR_VERSION 0\r
#define DEM_SW_PATCH_VERSION 0\r
#define DEM_AR_MINOR_VERSION 0\r
#define DEM_AR_PATCH_VERSION 1\r
\r
+/** @req DCM067.Cfg-files */\r
#include "Dem_Types.h"\r
#include "Dem_Cfg.h"\r
#include "Dem_Lcfg.h"\r
-#include "Dem_IntErrId.h"\r
+#include "Dem_IntErrId.h" /** @req DEM115 */\r
#include "Dem_IntEvtId.h"\r
+/** @req DEM153 */ /** @req DEM154 */ /* Realized in Dem_IntErrId.h and Dem_IntEvtId.h */\r
// #include "Rte_Dem.h"\r
\r
\r
#if (DEM_DEV_ERROR_DETECT == STD_ON)\r
-// Error codes produced by this module\r
-#define DEM_E_CONFIG_PTR_INVALID 0x01\r
+// Error codes reported by this module defined by AUTOSAR /** @req DEM116 */ /** @req DEM173 */\r
#define DEM_E_PARAM_CONFIG 0x10\r
#define DEM_E_PARAM_ADDRESS 0x11\r
#define DEM_E_PARAM_DATA 0x12\r
#define DEM_E_UNINIT 0x20\r
#define DEM_E_NODATAAVAILABLE 0x30\r
\r
-#define DEM_E_EVENT_STATUS_BUFF_FULL 0x40\r
-#define DEM_E_EXT_DATA_TOO_BIG 0x41\r
-#define DEM_E_PRE_INIT_EXT_DATA_BUFF_FULL 0x42\r
-#define DEM_E_PRI_MEM_EVENT_BUFF_FULL 0x43\r
-#define DEM_E_PRI_MEM_EXT_DATA_BUFF_FULL 0x44\r
+// Other error codes reported by this module\r
+#define DEM_E_CONFIG_PTR_INVALID 0x40\r
+#define DEM_E_EVENT_STATUS_BUFF_FULL 0x41\r
+#define DEM_E_EXT_DATA_TOO_BIG 0x42\r
+#define DEM_E_PRE_INIT_EXT_DATA_BUFF_FULL 0x43\r
+#define DEM_E_PRI_MEM_EVENT_BUFF_FULL 0x44\r
+#define DEM_E_PRI_MEM_EXT_DATA_BUFF_FULL 0x45\r
\r
#define DEM_E_UNEXPECTED_EXECUTION 0xfe\r
#define DEM_E_NOT_IMPLEMENTED_YET 0xff\r
\r
// Service ID in this module\r
-#define DEM_PREINIT_ID 0x01\r
-#define DEM_INIT_ID 0x02\r
-#define DEM_SETEVENTSTATUS_ID 0x04\r
-#define DEM_RESETEVENTSTATUS_ID 0x05\r
-#define DEM_SETOPERATIONCYCLESTATE_ID 0x08\r
-#define DEM_GETEVENTSTATUS_ID 0x0A\r
-#define DEM_GETEVENTFAILED_ID 0x0B\r
-#define DEM_GETEVENTTESTED_ID 0x0C\r
-#define DEM_REPORTERRORSTATUS_ID 0x0F\r
-#define DEM_GETEXTENDEDDATARECORDBYDTC_ID 0x20\r
-#define DEM_CLEARDTC_ID 0x22\r
-#define DEM_GETFAULTDETECTIONCOUNTER_ID 0x3E\r
-\r
-#define DEM_UPDATE_EVENT_STATUS_ID 0x80\r
-#define DEM_MERGE_EVENT_STATUS_ID 0x81\r
-#define DEM_GET_EXTENDED_DATA_ID 0x82\r
-#define DEM_STORE_EXT_DATA_PRE_INIT_ID 0x83\r
-#define DEM_STORE_EVENT_PRI_MEM_ID 0x84\r
-#define DEM_STORE_EXT_DATA_PRI_MEM_ID 0x85\r
-#define DEM_PREDEBOUNCE_NONE_ID 0x86\r
-#define DEM_PREDEBOUNCE_COUNTER_BASED_ID 0x87\r
-#define DEM_GLOBAL_ID 0xff\r
+#define DEM_PREINIT_ID 0x01\r
+#define DEM_INIT_ID 0x02\r
+#define DEM_SHUTDOWN_ID 0x03\r
+#define DEM_SETEVENTSTATUS_ID 0x04\r
+#define DEM_RESETEVENTSTATUS_ID 0x05\r
+#define DEM_SETOPERATIONCYCLESTATE_ID 0x08\r
+#define DEM_GETEVENTSTATUS_ID 0x0A\r
+#define DEM_GETEVENTFAILED_ID 0x0B\r
+#define DEM_GETEVENTTESTED_ID 0x0C\r
+#define DEM_GETDTCOFEVENT_ID 0x0D\r
+#define DEM_REPORTERRORSTATUS_ID 0x0F\r
+#define DEM_SETDTCFILTER_ID 0x13\r
+#define DEM_GETSTATUSOFDTC_ID 0x15\r
+#define DEM_GETDTCSTATUSAVAILABILITYMASK_ID 0x16\r
+#define DEM_GETNUMBEROFFILTEREDDTC_ID 0x17\r
+#define DEM_GETNEXTFILTEREDDTC_ID 0x18\r
+#define DEM_GETEXTENDEDDATARECORDBYDTC_ID 0x20\r
+#define DEM_GETSIZEOFEXTENDEDDATARECORDBYDTC_ID 0x21\r
+#define DEM_CLEARDTC_ID 0x22\r
+#define DEM_DISABLEDTCSTORAGE_ID 0x24\r
+#define DEM_ENABLEDTCSTORAGE_ID 0x25\r
+#define DEM_GETTRANSLATIONTYPE_ID 0x3c\r
+#define DEM_GETFAULTDETECTIONCOUNTER_ID 0x3E\r
+#define DEM_MAINFUNCTION_ID 0x55\r
+\r
+#define DEM_UPDATE_EVENT_STATUS_ID 0x80\r
+#define DEM_MERGE_EVENT_STATUS_ID 0x81\r
+#define DEM_GET_EXTENDED_DATA_ID 0x82\r
+#define DEM_STORE_EXT_DATA_PRE_INIT_ID 0x83\r
+#define DEM_STORE_EVENT_PRI_MEM_ID 0x84\r
+#define DEM_STORE_EXT_DATA_PRI_MEM_ID 0x85\r
+#define DEM_PREDEBOUNCE_NONE_ID 0x86\r
+#define DEM_PREDEBOUNCE_COUNTER_BASED_ID 0x87\r
+#define DEM_GLOBAL_ID 0xff\r
\r
#endif\r
\r
/*\r
* Interface for upper layer modules (8.3.1)\r
*/\r
-\r
-#if (DEM_VERSION_INFO_API == STD_ON)\r
-void Dem_GetVersionInfo(Std_VersionInfoType *versionInfo);\r
+#if ( DEM_VERSION_INFO_API == STD_ON ) /** @req DEM111 */\r
+#define Dem_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DEM) /** @req DEM177 */ /** @req DEM110 */ /** @req DEM178 */\r
#endif /* DEM_VERSION_INFO_API */\r
\r
/*\r
* Interface ECU State Manager <-> DEM (8.3.2)\r
*/\r
-void Dem_PreInit( void );\r
-void Dem_Init( void );\r
-void Dem_Shutdown( void );\r
+void Dem_PreInit( void ); /** @req DEM179 */\r
+void Dem_Init( void ); /** @req DEM181 */\r
+void Dem_Shutdown( void ); /** @req DEM182 */\r
\r
\r
/*\r
* Interface for basic software scheduler\r
*/\r
-void Dem_MainFunction( void );\r
+void Dem_MainFunction( void ); /** @req DEM266 */\r
\r
\r
/*\r
* Interface SW-Components via RTE <-> DEM (8.3.3)\r
*/\r
-Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, uint8 eventStatus);\r
-Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId);\r
-Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended);\r
-Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed);\r
-Std_ReturnType Dem_GetEventTested(Dem_EventIdType eventId, boolean *eventTested);\r
-Std_ReturnType Dem_GetFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter);\r
-Std_ReturnType Dem_SetOperationCycleState(Dem_OperationCycleIdType OperationCycleId, Dem_OperationCycleStateType CycleState);\r
-Std_ReturnType Dem_GetDTCOfEvent(Dem_EventIdType eventId, Dem_DTCKindType dtcKind, uint32* dtcOfEvent);\r
+Std_ReturnType Dem_SetEventStatus(Dem_EventIdType eventId, uint8 eventStatus); /** @req DEM183 */\r
+Std_ReturnType Dem_ResetEventStatus(Dem_EventIdType eventId); /** @req DEM185 */\r
+Std_ReturnType Dem_GetEventStatus(Dem_EventIdType eventId, Dem_EventStatusExtendedType *eventStatusExtended); /** @req DEM195 */\r
+Std_ReturnType Dem_GetEventFailed(Dem_EventIdType eventId, boolean *eventFailed); /** @req DEM196 */\r
+Std_ReturnType Dem_GetEventTested(Dem_EventIdType eventId, boolean *eventTested); /** @req DEM197 */\r
+Std_ReturnType Dem_GetFaultDetectionCounter(Dem_EventIdType eventId, sint8 *counter); /** @req DEM203 */\r
+Std_ReturnType Dem_SetOperationCycleState(Dem_OperationCycleIdType operationCycleId, Dem_OperationCycleStateType cycleState); /** @req DEM194 */\r
+Std_ReturnType Dem_GetDTCOfEvent(Dem_EventIdType eventId, Dem_DTCKindType dtcKind, uint32* dtcOfEvent); /** @req DEM198 */\r
\r
\r
/*\r
* Interface BSW-Components <-> DEM (8.3.4)\r
*/\r
-void Dem_ReportErrorStatus(Dem_EventIdType eventId ,uint8 eventStatus);\r
+void Dem_ReportErrorStatus(Dem_EventIdType eventId ,uint8 eventStatus); /** @req DEM206 */\r
\r
\r
/*\r
* Interface DCM <-> DEM (8.3.5)\r
*/\r
-Dem_ReturnClearDTCType Dem_ClearDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin);\r
-Dem_ReturnSetDTCFilterType Dem_SetDTCFilter(uint8 dtcStatusMask,\r
- Dem_DTCKindType dtcKind,\r
- Dem_DTCOriginType dtcOrigin,\r
- Dem_FilterWithSeverityType filterWithSeverity,\r
- Dem_DTCSeverityType dtcSeverityMask,\r
- Dem_FilterForFDCType filterForFaultDetectionCounter);\r
-Dem_ReturnGetStatusOfDTCType Dem_GetStatusOfDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, Dem_EventStatusExtendedType* dtcStatus);\r
-Std_ReturnType Dem_GetDTCStatusAvailabilityMask(uint8 *dtcStatusMask);\r
-Dem_ReturnGetNumberOfFilteredDTCType Dem_GetNumberOfFilteredDtc(uint16* numberOfFilteredDTC);\r
-Dem_ReturnGetNextFilteredDTCType Dem_GetNextFilteredDTC(uint32* dtc, Dem_EventStatusExtendedType* dtcStatus);\r
-Dem_ReturnTypeOfDtcSupportedType Dem_GetTranslationType(void);\r
-Dem_ReturnControlDTCStorageType Dem_DisableDTCStorage(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind);\r
-Dem_ReturnControlDTCStorageType Dem_EnableDTCStorage(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind);\r
-Dem_ReturnGetExtendedDataRecordByDTCType Dem_GetExtendedDataRecordByDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint8 *destBuffer, uint8 *bufSize);\r
-Dem_ReturnGetSizeOfExtendedDataRecordByDTCType Dem_GetSizeOfExtendedDataRecordByDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint16 *sizeOfExtendedDataRecord);\r
+Dem_ReturnClearDTCType Dem_ClearDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin); /** @req DEM241 */\r
+Dem_ReturnSetDTCFilterType Dem_SetDTCFilter(uint8 dtcStatusMask, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, Dem_FilterWithSeverityType filterWithSeverity, Dem_DTCSeverityType dtcSeverityMask, Dem_FilterForFDCType filterForFaultDetectionCounter); /** @req DEM208 */\r
+Dem_ReturnGetStatusOfDTCType Dem_GetStatusOfDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, Dem_EventStatusExtendedType* status); /** @req DEM212 */\r
+Std_ReturnType Dem_GetDTCStatusAvailabilityMask(uint8 *dtcStatusMask); /** @req DEM213 */\r
+Dem_ReturnGetNumberOfFilteredDTCType Dem_GetNumberOfFilteredDtc(uint16* numberOfFilteredDTC); /** @req DEM214 */\r
+Dem_ReturnGetNextFilteredDTCType Dem_GetNextFilteredDTC(uint32* dtc, Dem_EventStatusExtendedType* dtcStatus); /** @req DEM215 */\r
+Dem_ReturnTypeOfDtcSupportedType Dem_GetTranslationType(void); /** @req DEM230 */\r
+Dem_ReturnControlDTCStorageType Dem_DisableDTCStorage(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind); /** @req DEM242 */\r
+Dem_ReturnControlDTCStorageType Dem_EnableDTCStorage(Dem_DTCGroupType dtcGroup, Dem_DTCKindType dtcKind); /** @req DEM243 */\r
+Dem_ReturnGetExtendedDataRecordByDTCType Dem_GetExtendedDataRecordByDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint8 *destBuffer, uint16 *bufSize); /** @req DEM239 */\r
+Dem_ReturnGetSizeOfExtendedDataRecordByDTCType Dem_GetSizeOfExtendedDataRecordByDTC(uint32 dtc, Dem_DTCKindType dtcKind, Dem_DTCOriginType dtcOrigin, uint8 extendedDataNumber, uint16 *sizeOfExtendedDataRecord); /** @req DEM240 */\r
\r
\r
\r
/*\r
* Development Error Tracer driver\r
*\r
- * Specification: Autosar v2.0.1, Final\r
- *\r
*/\r
\r
-#ifndef _DET_H_\r
-#define _DET_H_\r
+\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req DET004 */\r
+\r
+#ifndef DET_H\r
+#define DET_H\r
\r
#define DET_MODULE_ID MODULE_ID_DET\r
#define DET_VENDOR_ID 1\r
\r
+/* Implementation version */\r
#define DET_SW_MAJOR_VERSION 1\r
#define DET_SW_MINOR_VERSION 0\r
#define DET_SW_PATCH_VERSION 0\r
\r
+/* AUTOSAR specification document version */\r
#define DET_AR_MAJOR_VERSION 2\r
#define DET_AR_MINOR_VERSION 2\r
#define DET_AR_PATCH_VERSION 2\r
\r
#define DET_CALLBACK_API 0xFF\r
\r
+#define DET_CBK_REGISTRATION_FAILED_INDEX 0xFF\r
+\r
// Type used to store errors\r
typedef struct\r
{\r
} Det_EntryType;\r
\r
#if ( DET_ENABLE_CALLBACKS == STD_ON )\r
-typedef void *(*detCbk_t)( uint16 ModuleId, uint8 InstanceId , uint8 ApiId, uint8 ErrorId);\r
+typedef void (*detCbk_t)( uint16 ModuleId, uint8 InstanceId , uint8 ApiId, uint8 ErrorId);\r
\r
/*\r
* Add a callback function to the array of callback. After a call to Det_ReportError the callback\r
* is called. This can be used in for instance unit tests to verify that correct errors are\r
* reported when sending invalid parameters to a function.\r
* This function returns the index of the callback in the array when registration is successful. If\r
- * not -1 is returned. The index can be used to remove a callback with the Det_RemoveCbk.\r
+ * not DET_CBK_REGISTRATION_FAILED_INDEX is returned.\r
+ * The index can be used to remove a callback with the Det_RemoveCbk.\r
*/\r
uint8 Det_AddCbk ( detCbk_t detCbk);\r
void Det_RemoveCbk ( uint8 detCbkIndex);\r
#endif\r
\r
-void Det_Init( void );\r
+void Det_Init( void ); /** @req DET008 */\r
#if DET_DEINIT_API == STD_ON\r
void Det_DeInit( void );\r
#endif\r
-void Det_ReportError( uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId);\r
-void Det_Start( void );\r
-#define Det_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DET)\r
+void Det_ReportError( uint16 ModuleId, uint8 InstanceId, uint8 ApiId, uint8 ErrorId); /** @req DET009 */\r
+void Det_Start( void ); /** @req DET010 */\r
+#define Det_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DET) /** @req DET011 */ /** @req DET012 */\r
\r
-#endif /*_DET_H_*/\r
+#endif /*DET_H*/\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef DIO_H_\r
-#define DIO_H_\r
-\r
-#include "Std_Types.h"\r
-\r
-// API Service ID's\r
-#define DIO_READCHANNEL_ID 0x00\r
-#define DIO_WRITECHANNEL_ID 0x01\r
-#define DIO_READPORT_ID 0x02\r
-#define DIO_WRITEPORT_ID 0x03\r
-#define DIO_READCHANNELGROUP_ID 0x04\r
-#define DIO_WRITECHANNELGROUP_ID 0x05\r
-#define DIO_GETVERSIONINFO_ID 0x12\r
-\r
-#define DIO_E_PARAM_INVALID_CHANNEL_ID 10\r
-#define DIO_E_PARAM_INVALID_PORT_ID 20\r
-#define DIO_E_PARAM_INVALID_GROUP_ID 31\r
-\r
-typedef uint32 Dio_ChannelType;\r
-typedef uint32 Dio_PortType;\r
-typedef struct\r
-{\r
- Dio_PortType port;\r
- uint8 offset;\r
- uint32 mask;\r
-} Dio_ChannelGroupType;\r
-\r
-#if 0 // Gone from 3.0\r
-typedef enum\r
-{\r
- STD_LOW,\r
- STD_HIGH,\r
-}Dio_LevelType;\r
-#endif\r
-\r
-typedef uint32 Dio_LevelType;\r
-\r
-typedef uint16 Dio_PortLevelType;\r
-\r
-#define DIO_SW_MAJOR_VERSION 1\r
-#define DIO_SW_MINOR_VERSION 0\r
-#define DIO_SW_PATCH_VERSION 0\r
-\r
-#define DIO_AR_MAJOR_VERSION 2\r
-#define DIO_AR_MINOR_VERSION 2 \r
-#define DIO_AR_PATCH_VERSION 1 \r
-\r
-#include "Dio_Cfg.h"\r
-\r
-\r
-#if ( DIO_VERSION_INFO_API == STD_ON)\r
-void Dio_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
-#endif\r
-\r
-Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId);\r
-void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level);\r
-Dio_PortLevelType Dio_ReadPort(Dio_PortType portId);\r
-void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level);\r
-Dio_PortLevelType Dio_ReadChannelGroup( const Dio_ChannelGroupType *channelGroupIdPtr );\r
-void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr, Dio_PortLevelType level);\r
-\r
-#endif /*DIO_H_*/\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DIO_H_
+#define DIO_H_
+
+#include "Std_Types.h" /** @req DIO131 */
+
+// API Service ID's
+#define DIO_READCHANNEL_ID 0x00
+#define DIO_WRITECHANNEL_ID 0x01
+#define DIO_READPORT_ID 0x02
+#define DIO_WRITEPORT_ID 0x03
+#define DIO_READCHANNELGROUP_ID 0x04
+#define DIO_WRITECHANNELGROUP_ID 0x05
+#define DIO_GETVERSIONINFO_ID 0x12
+
+#define DIO_E_PARAM_INVALID_CHANNEL_ID 10
+#define DIO_E_PARAM_INVALID_PORT_ID 20
+#define DIO_E_PARAM_INVALID_GROUP_ID 31
+
+#if defined(CFG_HC1X) || defined(CFG_TMS570)
+typedef uint8 Dio_ChannelType;
+typedef uint8 Dio_PortType;
+
+/** @req DIO021 */
+/** @req DIO022 */
+typedef struct
+{
+ Dio_PortType port;
+ uint8 offset;
+ uint8 mask;
+} Dio_ChannelGroupType;
+
+/** @req DIO023 */
+typedef uint8 Dio_LevelType;
+
+/** @req DIO024 */
+typedef uint8 Dio_PortLevelType;
+
+#else // CFG_PPC, CFG_STM32_STAMP and others
+typedef uint32 Dio_ChannelType;
+typedef uint32 Dio_PortType;
+typedef struct
+{
+ Dio_PortType port;
+ uint8 offset;
+ uint32 mask;
+} Dio_ChannelGroupType;
+
+typedef uint32 Dio_LevelType;
+
+typedef uint16 Dio_PortLevelType;
+#endif
+
+
+#define DIO_MODULE_ID MODULE_ID_DIO
+#define DIO_VENDOR_ID 1
+
+#define DIO_SW_MAJOR_VERSION 1
+#define DIO_SW_MINOR_VERSION 0
+#define DIO_SW_PATCH_VERSION 0
+
+#define DIO_AR_MAJOR_VERSION 2
+#define DIO_AR_MINOR_VERSION 2
+#define DIO_AR_PATCH_VERSION 1
+
+#include "Dio_Cfg.h"
+
+/** @req DIO124 */
+#if ( DIO_VERSION_INFO_API == STD_ON)
+/** @req DIO139 */
+#define Dio_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DIO)
+#endif
+
+/** @req DIO133 */
+/** @req DIO027 */
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId);
+
+/** @req DIO134 */
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level);
+
+/** @req DIO135 */
+/** @req DIO031 */
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId);
+
+/** @req DIO136 */
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level);
+
+/** @req DIO137 */
+Dio_PortLevelType Dio_ReadChannelGroup( const Dio_ChannelGroupType *channelGroupIdPtr );
+
+/** @req DIO138 */
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr, Dio_PortLevelType level);
+
+#endif /*DIO_H_*/
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifndef EA_H_\r
+#define EA_H_\r
+\r
+#include "Ea_Cfg.h"\r
+\r
+\r
+#define EA_MODULE_ID MODULE_ID_EA\r
+#define EA_VENDOR_ID 1\r
+\r
+#define EA_SW_MAJOR_VERSION 1\r
+#define EA_SW_MINOR_VERSION 0\r
+#define EA_SW_PATCH_VERSION 0\r
+#define EA_AR_MAJOR_VERSION 3\r
+#define EA_AR_MINOR_VERSION 0\r
+#define EA_AR_PATCH_VERSION 1\r
+\r
+#if ( EA_VERSION_INFO_API == STD_ON )\r
+#define Ea_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi, EA) /** @req EA092 */\r
+#endif /* EA_VERSION_INFO_API */\r
+\r
+void Ea_MainFunction(void); /** @req EA096 */\r
+\r
+void Ea_Init(void); /** @req EA084 */\r
+void Ea_SetMode(MemIf_ModeType Mode); /** @req EA085 */\r
+Std_ReturnType Ea_Read(uint16 BlockNumber, uint16 BlockOffset, uint8* DataBufferPtr, uint16 Length); /** @req EA086 */\r
+Std_ReturnType Ea_Write(uint16 BlockNumber, uint8* DataBufferPtr); /** @req EA087 */\r
+void Ea_Cancel(void); /** @req EA088 */\r
+MemIf_StatusType Ea_GetStatus(void); /** @req EA089 */\r
+MemIf_JobResultType Ea_GetJobResult(void); /** @req EA090 */\r
+Std_ReturnType Ea_InvalidateBlock(uint16 BlockNumber); /** @req EA091 */\r
+Std_ReturnType Ea_EraseImmediateBlock(uint16 BlockNumber); /** @req EA093 */\r
+\r
+\r
+\r
+#endif /*EA_H_*/\r
\r
\r
\r
-#ifndef MEMIF_CFG_H_\r
-#define MEMIF_CFG_H_\r
+#ifndef EA_CBK_H_\r
+#define EA_CBK_H_\r
\r
-// TODO. include FEE and EA modules\r
+void Ea_JobEndNotification(void); /** @req EA094 */\r
+void Ea_JobErrorNotification(void); /** @req EA095 */\r
\r
-\r
-\r
-#endif /*MEMIF_CFG_H_*/\r
+#endif /*EA_CBK_H_*/\r
\r
/** @name Service id's */\r
//@{\r
+#define ECUM_REQUESTRUN_ID (0x03)\r
+#define ECUM_RELEASERUN_ID (0x04)\r
+#define ECUM_SELECTSHUTDOWNTARGET_ID (0x06)\r
#define ECUM_GETSTATE_ID (0x07)\r
+#define ECUM_GETSHUTDOWNTARGET_ID (0x09)\r
+#define ECUM_COMM_REQUESTRUN_ID (0x0e)\r
+#define ECUM_REQUESTPOSTRUN_ID (0x0a)\r
+#define ECUM_RELEASEPOSTRUN_ID (0x0b)\r
#define ECUM_SELECTAPPMODE_ID (0x0f)\r
+#define ECUM_COMM_RELEASERUN_ID (0x10)\r
#define ECUM_GETAPPMODE_ID (0x11)\r
#define ECUM_SELECT_BOOTARGET_ID (0x12)\r
#define ECUM_GET_BOOTARGET_ID (0x13)\r
#define ECUM_MAINFUNCTION_ID (0x18)\r
+#define ECUM_COMM_HASREQUESTEDRUN_ID (0x1b)\r
\r
/** Possible states */\r
typedef enum {\r
* If hardware cannot distinguish between a\r
* power cycle and a reset reason, then this\r
* shall be the default wakeup source */\r
- ECUM_WKSOURCE_RESET = 0x02,\r
+ ECUM_WKSOURCE_RESET = 0x02\r
};\r
\r
typedef uint32 EcuM_WakeupSourceType;\r
ECUM_WKSTATUS_NONE = 0, /**< No pending wakeup event was detected */\r
ECUM_WKSTATUS_PENDING = 1, /**< The wakeup event was detected but not yet validated */\r
ECUM_WKSTATUS_VALIDATED = 2, /**< The wakeup event is valid */\r
- ECUM_WKSTATUS_EXPIRED = 3, /**< The wakeup event has not been validated and has expired therefore */\r
+ ECUM_WKSTATUS_EXPIRED = 3 /**< The wakeup event has not been validated and has expired therefore */\r
} EcuM_WakeupStatusType;\r
\r
typedef enum\r
{\r
ECUM_WWKACT_RUN = 0, /**< Initialization into RUN state */\r
ECUM_WKACT_TTII = 2, /**< Execute time triggered increased inoperation protocol and shutdown */\r
- ECUM_WKACT_SHUTDOWN = 3, /**< Immediate shutdown */\r
+ ECUM_WKACT_SHUTDOWN = 3 /**< Immediate shutdown */\r
} EcuM_WakeupReactionType;\r
\r
typedef enum\r
{\r
ECUM_BOOT_TARGET_APP = 0, /**< The Ecu will boot into the application */\r
- ECUM_BOOT_TARGET_BOOTLOADER = 1, /**< The Ecu will boot into the bootloader */\r
+ ECUM_BOOT_TARGET_BOOTLOADER = 1 /**< The Ecu will boot into the bootloader */\r
} EcuM_BootTargetType;\r
\r
\r
-#define ECUM_SW_MAJOR_VERSION 1\r
-#define ECUM_SW_MINOR_VERSION 0\r
-#define ECUM_SW_PATCH_VERSION 0\r
+#define ECUM_MODULE_ID MODULE_ID_ECUM\r
+#define ECUM_VENDOR_ID 1\r
\r
-#define ECUM_AR_MAJOR_VERSION 1\r
-#define ECUM_AR_MINOR_VERSION 2\r
-#define ECUM_AR_PATCH_VERSION 2\r
+#define ECUM_SW_MAJOR_VERSION 2\r
+#define ECUM_SW_MINOR_VERSION 0\r
+#define ECUM_SW_PATCH_VERSION 0\r
+\r
+#define ECUM_AR_MAJOR_VERSION 1\r
+#define ECUM_AR_MINOR_VERSION 2\r
+#define ECUM_AR_PATCH_VERSION 2\r
\r
#include "EcuM_Cfg.h"\r
\r
#if ( ECUM_VERSION_INFO_API == STD_ON)\r
-void EcuM_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
+#define EcuM_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,ECUM)\r
#endif\r
\r
void EcuM_Init( void );\r
-void EcuM_StartupTwo();\r
-void EcuM_Shutdown();\r
+void EcuM_StartupTwo(void);\r
+void EcuM_Shutdown(void);\r
\r
Std_ReturnType EcuM_GetState(EcuM_StateType* state);\r
\r
Std_ReturnType EcuM_RequestPOST_RUN(EcuM_UserType user);\r
Std_ReturnType EcuM_ReleasePOST_RUN(EcuM_UserType user);\r
\r
-void EcuM_KillAllRUNRequests();\r
+void EcuM_KillAllRUNRequests(void);\r
\r
#if defined(USE_COM)\r
Std_ReturnType EcuM_ComM_RequestRUN(NetworkHandleType channel);\r
Std_ReturnType EcuM_GetShutdownTarget(EcuM_StateType* target, uint8* mode);\r
Std_ReturnType EcuM_GetLastShutdownTarget(EcuM_StateType* target, uint8* mode);\r
\r
-EcuM_WakeupSourceType EcuM_GetPendingWakeupEvents();\r
+EcuM_WakeupSourceType EcuM_GetPendingWakeupEvents(void);\r
void EcuM_ClearWakeupEvent(EcuM_WakeupSourceType sources);\r
-EcuM_WakeupSourceType EcuM_GetValidatedWakeupEvents();\r
-EcuM_WakeupSourceType EcuM_GetExpiredWakeupEvents();\r
+EcuM_WakeupSourceType EcuM_GetValidatedWakeupEvents(void);\r
+EcuM_WakeupSourceType EcuM_GetExpiredWakeupEvents(void);\r
EcuM_WakeupStatusType EcuM_GetStatusOfWakeupSource(EcuM_WakeupSourceType sources);\r
\r
Std_ReturnType EcuM_SelectApplicationMode(AppModeType appMode);\r
\r
void EcuM_MainFunction(void);\r
\r
-void EcuM_OnGoOffTwo( void );\r
-void EcuM_AL_SwitchOff( void );\r
-\r
#endif /*ECUM_H_*/\r
/** @} */\r
\r
void EcuM_ErrorHook(Std_ReturnType reason);\r
\r
-void EcuM_AL_DriverInitZero();\r
-EcuM_ConfigType* EcuM_DeterminePbConfiguration();\r
+void EcuM_AL_DriverInitZero(void);\r
+EcuM_ConfigType* EcuM_DeterminePbConfiguration(void);\r
void EcuM_AL_DriverInitOne(const EcuM_ConfigType* ConfigPtr);\r
void EcuM_AL_DriverInitTwo(const EcuM_ConfigType* ConfigPtr);\r
void EcuM_AL_DriverInitThree(const EcuM_ConfigType* ConfigPtr);\r
\r
-void EcuM_OnRTEStartup();\r
+void EcuM_OnRTEStartup(void);\r
\r
-void EcuM_OnEnterRUN();\r
-void EcuM_OnExitRun();\r
-void EcuM_OnExitPostRun();\r
+void EcuM_OnEnterRUN(void);\r
+void EcuM_OnExitRun(void);\r
+void EcuM_OnExitPostRun(void);\r
\r
-void EcuM_OnPrepShutdown();\r
-void EcuM_OnGoSleep();\r
-void EcuM_OnGoOffOne();\r
-void EcuM_OnGoOffTwo();\r
+void EcuM_OnPrepShutdown(void);\r
+void EcuM_OnGoSleep(void);\r
+void EcuM_OnGoOffOne(void);\r
+void EcuM_OnGoOffTwo(void);\r
\r
void EcuM_EnableWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
void Ecum_DisableWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
\r
-void EcuM_GenerateRamHash();\r
-uint8 EcuM_CheckRamHash();\r
+void EcuM_GenerateRamHash(void);\r
+uint8 EcuM_CheckRamHash(void);\r
\r
-void EcuM_AL_SwitchOff();\r
-void Ecum_AL_DriverRestart();\r
+void EcuM_AL_SwitchOff(void);\r
+void Ecum_AL_DriverRestart(void);\r
\r
void EcuM_StartWakeupSources(EcuM_WakeupSourceType wakeupSource);\r
void EcuM_CheckValidation(EcuM_WakeupSourceType wakeupSource);\r
EcuM_WakeupReactionType EcuM_OnWakeupReaction(EcuM_WakeupReactionType wact);\r
\r
void EcuM_CheckWakeup(EcuM_WakeupSourceType wakeupSource);\r
-void EcuM_SleepActivity();\r
+void EcuM_SleepActivity(void);\r
\r
#endif /*ECUM_CBK_H_*/\r
#define EEP_E_UNINIT 0x20\r
#define EEP_E_BUSY 0x21\r
\r
+/* Production errors */\r
+// #define EEP_E_COM_FAILURE 0x30 /* Shall be located in DemIntErrId.h when its available */\r
+\r
/* Service id's for fls functions */\r
#define EEP_INIT_ID 0x00\r
#define EEP_SETMODE_ID 0x01\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifndef FEE_H_\r
+#define FEE_H_\r
+\r
+\r
+#define FEE_MODULE_ID MODULE_ID_FEE\r
+#define FEE_VENDOR_ID 1\r
+\r
+#define FEE_SW_MAJOR_VERSION 1\r
+#define FEE_SW_MINOR_VERSION 0\r
+#define FEE_SW_PATCH_VERSION 0\r
+#define FEE_AR_MAJOR_VERSION 3\r
+#define FEE_AR_MINOR_VERSION 0\r
+#define FEE_AR_PATCH_VERSION 1\r
+\r
+#include "Std_Types.h"\r
+#include "Fee_Cfg.h"\r
+#include "Fls.h"\r
+\r
+#if (FEE_DEV_ERROR_DETECT == STD_ON)\r
+// Error codes reported by this module defined by AUTOSAR\r
+#define FEE_E_UNINIT 0x01\r
+#define FEE_E_INVALID_BLOCK_NO 0x02\r
+#define FEE_E_INVALID_BLOCK_OFS 0x03\r
+#define FEE_E_INVALID_DATA_PTR 0x04\r
+#define FEE_E_INVALID_BLOCK_LEN 0x05\r
+#define FEE_E_BUSY 0x06\r
+\r
+\r
+\r
+// Other error codes reported by this module\r
+#define FEE_PARAM_OUT_OF_RANGE 0x40\r
+#define FEE_UNEXPECTED_STATE 0x41\r
+#define FEE_FLASH_CORRUPT 0xfa\r
+#define FEE_UNEXPECTED_STATUS 0xfb\r
+#define FEE_E_WRONG_CONFIG 0xfc\r
+#define FEE_E_UNEXPECTED_EXECUTION 0xfd\r
+#define FEE_E_NOT_SUPPORTED 0xfe\r
+#define FEE_E_NOT_IMPLEMENTED_YET 0xff\r
+\r
+// Service ID in this module\r
+#define FEE_INIT 0x00\r
+#define FEE_SET_MODE_ID 0x01\r
+#define FEE_READ_ID 0x02\r
+#define FEE_WRITE_ID 0x03\r
+#define FEE_CANCEL_ID 0x04\r
+#define FEE_GET_STATUS_ID 0x05\r
+#define FEE_GET_JOB_RESULT_ID 0x06\r
+#define FEE_INVALIDATE_BLOCK_ID 0x07\r
+#define FEE_GET_VERSION_INFO_ID 0x08\r
+#define FEE_ERASE_IMMEDIATE_ID 0x09\r
+#define FEE_JOB_END_NOTIFICTION_ID 0x10\r
+#define FEE_JOB_ERROR_NOTIFICTION_ID 0x11\r
+#define FEE_MAIN_FUNCTION_ID 0x12\r
+\r
+#define FEE_STARTUP_ID 0x40\r
+#define FEE_GARBAGE_WRITE_HEADER_ID 0x41\r
+#define FEE_GLOBAL_ID 0xff\r
+\r
+#endif\r
+\r
+\r
+#if ( FEE_VERSION_INFO_API == STD_ON )\r
+#define Fee_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi, FEE) /** @req FEE093 */\r
+#endif /* FEE_VERSION_INFO_API */\r
+\r
+void Fee_MainFunction(void); /** @req FEE097 */\r
+\r
+void Fee_Init(void); /** @req FEE085 */\r
+void Fee_SetMode(MemIf_ModeType mode); /** @req FEE086 */\r
+Std_ReturnType Fee_Read(uint16 blockNumber, uint16 blockOffset, uint8* dataBufferPtr, uint16 length); /** @req FEE087 */\r
+Std_ReturnType Fee_Write(uint16 blockNumber, uint8* dataBufferPtr); /** @req FEE088 */\r
+void Fee_Cancel(void); /** @req FEE089 */\r
+MemIf_StatusType Fee_GetStatus(void); /** @req FEE090 */\r
+MemIf_JobResultType Fee_GetJobResult(void); /** @req FEE091 */\r
+Std_ReturnType Fee_InvalidateBlock(uint16 blockNumber); /** @req FEE092 */\r
+Std_ReturnType Fee_EraseImmediateBlock(uint16 blockNumber); /** @req FEE094 */\r
+\r
+\r
+\r
+#endif /*FEE_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#ifndef FEE_CBK_H_\r
+#define FEE_CBK_H_\r
+\r
+void Fee_JobEndNotification(void); /** @req FEE095 */\r
+void Fee_JobErrorNotification(void); /** @req FEE096 */\r
+\r
+#endif /*FEE_CBK_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef FEE_CONFIG_TYPES_H_\r
+#define FEE_CONFIG_TYPES_H_\r
+\r
+#include "Std_Types.h"\r
+//#include "Fee_Types.h"\r
+\r
+\r
+/*\r
+ * Callback function prototypes\r
+ */\r
+\r
+typedef void (*Fee_JobEndCallbackFunctionType)(void); /** @req FEE098 */\r
+typedef void (*Fee_JobErrorCallbackFunctionType)(void); /** @req FEE099 */\r
+\r
+/*\r
+ * Containers and configuration parameters
+ */\r
+\r
+typedef struct {\r
+ Fee_JobEndCallbackFunctionType NvmJobEndCallbackNotificationCallback;\r
+ Fee_JobErrorCallbackFunctionType NvmJobErrorCallbackNotificationCallback;\r
+ // The rest of the parameters is realized in Fee_Cfg.h\r
+} Fee_GeneralType; /** @req FEE039 */\r
+\r
+typedef struct {\r
+ uint8 DeviceIndex; /** @req FEE106 */ // Needed by NvM and MemIf\r
+ uint16 BlockNumber; /** @req FEE107 */\r
+ uint16 BlockSize; /** @req FEE108 */\r
+ boolean ImmediateData; /** @req FEE109 */\r
+ uint32 NumberOfWriteCycles; /** @req FEE110 */\r
+} Fee_BlockConfigType; /** @req FEE040 */\r
+\r
+typedef struct {\r
+ // Containers\r
+ Fee_GeneralType General; // 1\r
+ const Fee_BlockConfigType *BlockConfig; // 1..*\r
+} Fee_ConfigType;\r
+\r
+/*\r
+ * Make the Fee_Config visible for others.\r
+ */\r
+extern const Fee_ConfigType Fee_Config;\r
+\r
+\r
+\r
+\r
+#endif /*FEE_CONFIG_TYPES_H_*/\r
//#include "Spi.h"\r
#include "Std_Types.h"\r
#include "Det.h"\r
-//#include "MemIf_Types.h"\r
+#include "MemIf_Types.h"\r
#if defined(USE_DEM)\r
#include "Dem.h"\r
#endif\r
MemIf_StatusType Fls_GetStatus( void );\r
#endif\r
\r
-#if ( FLS_GET_JOB_RESULT_API == STD_ON )\r
+#if ( 1 )\r
MemIf_JobResultType Fls_GetJobResult( void );\r
#endif\r
\r
\r
void Fls_GetVersionInfo( Std_VersionInfoType *VersioninfoPtr );\r
\r
+void Fls_Check( uint32 flsBaseAddress, uint32 flsTotalSize );\r
\r
#endif /*FLS_H_*/\r
\r
#define GPT_SW_MAJOR_VERSION 1\r
#define GPT_SW_MINOR_VERSION 0\r
-#define GPT_SW_PATCH_VERSION 0\r
+#define GPT_SW_PATCH_VERSION 1\r
\r
#define GPT_AR_MAJOR_VERSION 2\r
#define GPT_AR_MINOR_VERSION 2\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
-\r
-#define ECUM_VERSION_INFO_API STD_ON\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-#define ECUM_DEV_ERROR_DETECT STD_ON\r
-\r
-#include "EcuM_Generated_Types.h"\r
-\r
-#endif /*ECUM_CFG_H_*/\r
+#ifndef GPT_CONFIGTYPES_H\r
+#define GPT_CONFIGTYPES_H\r
+\r
+typedef struct {\r
+ uint32 GptChannelClkSrc;\r
+ Gpt_ChannelType GptChannelId;\r
+ Gpt_ChannelMode GptChannelMode;\r
+ void (*GptNotification)();\r
+ uint8 GptNotificationPriority;\r
+ uint32 GptChannelPrescale;\r
+ boolean GptEnableWakeup;\r
+} Gpt_ConfigType;\r
+\r
+#endif /* GPT_CONFIGTYPES_H */\r
MCU_POWER_ON_RESET,\r
MCU_WATCHDOG_RESET,\r
MCU_SW_RESET,\r
- MCU_RESET_UNDEFINED\r
+ MCU_RESET_UNDEFINED,\r
+ MCU_OSC_FAILURE_RESET,\r
+ MCU_CPU_RESET,\r
+ MCU_EXT_RESET,\r
+ MCU_VSW_RESET\r
} Mcu_ResetType;\r
\r
typedef struct {\r
uint8 Pll1; // PLL setting 1\r
uint8 Pll2; // PLL setting 2\r
uint8 Pll3; // PLL setting 3\r
+ uint8 Pll4; // PLL setting 4\r
\r
} Mcu_ClockSettingConfigType;\r
\r
#define Mcu_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,MCU)\r
#endif\r
\r
-typedef uint32_t imask_t;\r
-\r
/* ArcCore extensions */\r
+\r
void Irq_InstallVector(void (*func)(), IrqType vector, uint8_t priority, Cpu_t cpu );\r
void Irq_GenerateSoftInt( IrqType vector );\r
uint8_t Irq_GetCurrentPriority( Cpu_t cpu);\r
uint32_t McuE_GetSystemClock( void );\r
-#if defined(CFG_MPC55XX)\r
+#if defined(CFG_MPC55XX) || defined(CFG_ARM_CR4)\r
uint32_t McuE_GetPeripheralClock( McuE_PeriperalClock_t type );\r
#endif\r
-imask_t McuE_EnterCriticalSection(void);\r
-void McuE_ExitCriticalSection(imask_t old_state);\r
+#include "McuExtensions.h"\r
\r
\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef MCU_EXTENSIONS_H\r
+#define MCU_EXTENSIONS_H\r
+\r
+#include "Std_Types.h"\r
+typedef uint32_t imask_t;\r
+\r
+imask_t McuE_EnterCriticalSection(void);\r
+void McuE_ExitCriticalSection(imask_t old_state);\r
+\r
+#endif\r
\r
#ifndef MEMIF_H_\r
#define MEMIF_H_\r
+#define MEMIF_MODULE_ID MODULE_ID_MEMIF\r
+#define MEMIF_VENDOR_ID 1\r
\r
-/* TODO: Not really know how this is connected with the rest, yet :) */\r
-#define MemIf_SetMode( _mode )\r
+#define MEMIF_SW_MAJOR_VERSION 1\r
+#define MEMIF_SW_MINOR_VERSION 0\r
+#define MEMIF_SW_PATCH_VERSION 0\r
+#define MEMIF_AR_MAJOR_VERSION 3\r
+#define MEMIF_AR_MINOR_VERSION 0\r
+#define MEMIF_AR_PATCH_VERSION 1\r
+\r
+#include "Std_Types.h"\r
+#include "MemIf_Cfg.h"\r
+\r
+#if defined(USE_FEE)\r
+#include "Fee.h"\r
+#endif\r
+\r
+#if defined(USE_EA)\r
+#include "Ea.h"\r
+#endif\r
+\r
+#if (MEMIF_VERSION_INFO_API == STD_ON)\r
+#define MemIf_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi, MEMIF)\r
+#endif /* MEMIF_VERSION_INFO_API */\r
+\r
+#if (MEMIF_NUMBER_OF_DEVICES == 0)\r
+#define MemIf_SetMode(_mode)\r
#define MemIf_Read(_deviceIndex,_blockNumber,_blockOffset,_dataBufferPtr,_length)\r
#define MemIf_Write(_deviceIndex,_blockNumber,_dataBufferPtr)\r
-#define MemIf_Cancel( _deviceIndex )\r
-#define MemIf_GetStatus( _deviceIndex )\r
-#define MemIf_GetJobResult( _deviceIndex )\r
-#define MemIf_InvalidateBlock( _deviceIndex, _block )\r
-#define MemIf_GetVersionInfo( _versionInfo )\r
-#define MemIf_EraseImmediateBlock( _deviceIndex,_blockNumber );\r
+#define MemIf_Cancel(_deviceIndex)\r
+#define MemIf_GetStatus(_deviceIndex)\r
+#define MemIf_GetJobResult(_deviceIndex)\r
+#define MemIf_InvalidateBlock(_deviceIndex,_blockNumber)\r
+#define MemIf_EraseImmediateBlock(_deviceIndex,_blockNumber)\r
+#endif\r
+\r
+#if (MEMIF_NUMBER_OF_DEVICES == 1)\r
+#if (MEMIF_DEVICE_TO_USE == FLS_DRIVER_INDEX)\r
+#define MemIf_SetMode(_mode) Fee_SetMode(_mode)\r
+#define MemIf_Read(_deviceIndex,_blockNumber,_blockOffset,_dataBufferPtr,_length) Fee_Read(_blockNumber,_blockOffset,_dataBufferPtr,_length)\r
+#define MemIf_Write(_deviceIndex,_blockNumber,_dataBufferPtr) Fee_Write(_blockNumber,_dataBufferPtr)\r
+#define MemIf_Cancel(_deviceIndex) Fee_Cancel()\r
+#define MemIf_GetStatus(_deviceIndex) Fee_GetStatus()\r
+#define MemIf_GetJobResult(_deviceIndex) Fee_GetJobResult()\r
+#define MemIf_InvalidateBlock(_deviceIndex,_blockNumber) Fee_InvalidateBlock(blockNumber)\r
+#define MemIf_EraseImmediateBlock(_deviceIndex,_blockNumber) Fee_EraseImmediateBlock(_blockNumber)\r
+\r
+#elif (MEMIF_DEVICE_TO_USE == EEP_DRIVER_INDEX)\r
+#define MemIf_SetMode(_mode) Ea_SetMode(_mode)\r
+#define MemIf_Read(_deviceIndex,_blockNumber,_blockOffset,_dataBufferPtr,_length) Ea_Read(_blockNumber,_blockOffset,_dataBufferPtr,_length)\r
+#define MemIf_Write(_deviceIndex,_blockNumber,_dataBufferPtr) Ea_Write(_blockNumber,_dataBufferPtr)\r
+#define MemIf_Cancel(_deviceIndex) Ea_Cancel()\r
+#define MemIf_GetStatus(_deviceIndex) Ea_GetStatus()\r
+#define MemIf_GetJobResult(_deviceIndex) Ea_GetJobResult()\r
+#define MemIf_InvalidateBlock(_deviceIndex,_blockNumber) Ea_InvalidateBlock(_blockNumber)\r
+#define MemIf_EraseImmediateBlock(_deviceIndex,_blockNumber) Ea_EraseImmediateBlock(_blockNumber)\r
+#else\r
+#error "Memory device unknown (MEMIF_DEVICE_TO_USE)"\r
+#endif\r
+\r
+#endif\r
+\r
+#if (MEMIF_NUMBER_OF_DEVICES > 1)\r
+#error "Support for more than one device is not implemented yet!"\r
+void MemIf_SetMode(MemIf_ModeType Mode);\r
+Std_ReturnType MemIf_Read(uint8 DeviceIndex, uint16 BlockNumber, uint16 BlockOffset, uint8 *DataBufferPtr, uint16 Length);\r
+Std_ReturnType MemIf_Write(uint8 DeviceIndex, uint16 BlockNumber, uint8 *DataBufferPtr);\r
+void MemIf_Cancel(uint8 DeviceIndex);\r
+MemIf_StatusType MemIf_GetStatus(uint8 DeviceIndex);\r
+MemIf_JobResultType MemIf_GetJobResult(uint8 DeviceIndex);\r
+Std_ReturnType MemIf_InvalidateBlock(uint8 DeviceIndex, uint16 BlockNumber);\r
+Std_ReturnType MemIf_EraseImmediateBlock(uint8 DeviceIndex, uint16 BlockNumber);\r
+#endif\r
\r
#endif /*MEMIF_H_*/\r
MEMIF_JOB_FAILED,\r
// The job has not yet been finished.\r
MEMIF_JOB_PENDING,\r
- // The job has been cancelled.\r
+ // The job has been canceled.\r
MEMIF_JOB_CANCELLED,\r
// The requested block is inconsistent, it may contain\r
// corrupted data. \r
MEMIF_BLOCK_INCONSISTENT,\r
// The requested block has been marked as invalid,\r
// the requested operation can not be performed.\r
- MEMIF_BLOCK_INVALID, \r
+ MEMIF_BLOCK_INVALID\r
\r
} MemIf_JobResultType; \r
\r
MEMIF_MODE_SLOW,\r
// The underlying memory abstraction modules and\r
// drivers are working in fast mode.\r
- MEMIF_MODE_FAST,\r
+ MEMIF_MODE_FAST\r
} MemIf_ModeType;\r
\r
-// TODO: I have no idea where the types below are specified\r
-// In Eep these are defined in the header file\r
-// In Fls these are not found in the spec at all..\r
-typedef uint32 MemIf_AddressType;\r
-typedef uint32 MemIf_LengthType;\r
+// Definition of broadcast device ID\r
+#define MEMIF_BROADCAST_ID 0xff\r
\r
#endif /*MEMIF_TYPES_H_*/\r
// Module Id:s from document "List of Basic Sofware Modules" Rev 1.2.1 Part of release 3.0\r
//\r
\r
-#ifndef _MODULES_H_\r
-#define _MODULES_H_\r
+#ifndef MODULES_H\r
+#define MODULES_H\r
\r
#include "Std_Types.h"\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef NM_H_\r
+#define NM_H_\r
+\r
+/** @req NM117.partially */\r
+#include "Std_Types.h"\r
+#include "ComStack_Types.h"\r
+#include "NmStack_Types.h"\r
+#include "Nm_ConfigTypes.h"\r
+#include "ComM_Nm.h"\r
+\r
+#define NM_AR_MAJOR_VERSION 1\r
+#define NM_AR_MINOR_VERSION 0\r
+#define NM_AR_PATCH_VERSION 1\r
+\r
+#define NM_SW_MAJOR_VERSION 1\r
+#define NM_SW_MINOR_VERSION 0\r
+#define NM_SW_PATCH_VERSION 0\r
+\r
+#include "Nm_Cfg.h"\r
+\r
+/** Initializes the NM Interface. */\r
+/** @req NM030 */\r
+void Nm_Init( Nm_ConfigType * const nmConfigPtr );\r
+\r
+/** This service returns the version information of this module */\r
+/** @req NM044 */\r
+void Nm_GetVersionInfo( Std_VersionInfoType* nmVerInfoPtr );\r
+\r
+/** This function calls the <BusNm>_PassiveStartUp function\r
+ * (e.g. CanNm_PassiveStartUp function is called if channel is configured as CAN). */\r
+/** @req NM031 */\r
+Nm_ReturnType Nm_PassiveStartUp( const NetworkHandleType NetworkHandle );\r
+\r
+/** This function calls the <BusNm>_NetworkRequest\r
+ * (e.g. CanNm_NetworkRequest function is called if channel is configured as CAN). */\r
+/** @req NM032 */\r
+Nm_ReturnType Nm_NetworkRequest( const NetworkHandleType NetworkHandle );\r
+\r
+/** This function calls the <BusNm>_NetworkRelease bus specific function\r
+ * (e.g. CanNm_NetworkRelease function is called if channel is configured as CAN). */\r
+/** @req NM046 */\r
+Nm_ReturnType Nm_NetworkRelease( const NetworkHandleType NetworkHandle );\r
+\r
+/** This function calls the CanNm_NetworkRelease bus specific function, to disable\r
+ * the NM PDU transmission ability due to a ISO14229 Communication Control (28hex) service */\r
+/** @req NM033 */\r
+Nm_ReturnType Nm_DisableCommunication( const NetworkHandleType NetworkHandle );\r
+\r
+/** This function calls the CanNm_NetworkRequest bus specific function, to enable\r
+ * the NM PDU transmission ability due to a ISO14229 Communication Control (28hex) service */\r
+/** @req NM034 */\r
+Nm_ReturnType Nm_EnableCommunication( const NetworkHandleType NetworkHandle );\r
+\r
+/** Set user data for NM messages transmitted next on the bus.\r
+ * For that purpose <BusNm>_SetUserData shall be called\r
+ * (e.g. CanNm_SetUserData function is called if channel is configured as CAN). */\r
+/** @req NM035 */\r
+Nm_ReturnType Nm_SetUserData( const NetworkHandleType NetworkHandle, const uint8 * const nmUserDataPtr );\r
+\r
+/** Get user data out of the last successfully received NM message.\r
+ * For that purpose <BusNm>_GetUserData shall be called\r
+ * (e.g. CanNm_GetUserData function is called if channel is configured as CAN). */\r
+/** @req NM036 */\r
+Nm_ReturnType Nm_GetUserData( const NetworkHandleType NetworkHandle, uint8 * const nmUserDataPtr, uint8 * const nmNodeIdPtr );\r
+\r
+/** Get the whole PDU data out of the most recently received NM message.\r
+ * For that purpose CanNm_GetPduData shall be called. */\r
+/** @req NM037 */\r
+Nm_ReturnType Nm_GetPduData( const NetworkHandleType NetworkHandle, uint8 * const nmPduData );\r
+\r
+/** Set Repeat Message Request Bit for NM messages transmitted next on the bus.\r
+ * For that purpose <BusNm>_RepeatMessageRequest shall be called\r
+ * (e.g. CanNm_RepeatMessageRequest function is called if channel is configured as CAN) */\r
+/** @req NM038 */\r
+Nm_ReturnType Nm_RepeatMessageRequest( const NetworkHandleType NetworkHandle );\r
+\r
+/** Get node identifier out of the last successfully received NM-message.\r
+ * The function <BusNm>_GetNodeIdentifier shall be called. */\r
+/** @req NM039 */\r
+Nm_ReturnType Nm_GetNodeIdentifier( const NetworkHandleType NetworkHandle, uint8 * const nmNodeIdPtr );\r
+\r
+/** Get node identifier configured for the local node.\r
+ * For that purpose <BusNm>_GetLocalNodeIdentifier shall be called\r
+ * (e.g. CanNm_GetLocalNodeIdentifier function is called if channel is configured as CAN). */\r
+/** @req NM040 */\r
+Nm_ReturnType Nm_GetLocalNodeIdentifier( const NetworkHandleType NetworkHandle, uint8 * const nmNodeIdPtr );\r
+\r
+/** Check if remote sleep indication takes place or not. This in turn calls the\r
+ * <BusNm>_CheckRemoteSleepIndication for the bus specific NM layer\r
+ * (e.g. CanNm_CheckRemoteSleepIndication function is called if channel is configured as CAN). */\r
+/** @req NM042 */\r
+Nm_ReturnType Nm_CheckRemoteSleepIndication( const NetworkHandleType nmNetworkHandle, boolean * const nmRemoteSleepIndPtr );\r
+\r
+/** Returns the state of the network management. This function in turn calls the\r
+ * <BusNm>_GetState function (e.g. CanNm_GetState function is called if channel is configured as CAN). */\r
+/** @req NM043 */\r
+Nm_ReturnType Nm_GetState( const NetworkHandleType nmNetworkHandle, Nm_StateType* const nmStatePtr, Nm_ModeType* const nmModePtr );\r
+\r
+/** Notification that a NM-message has been received in the Bus-Sleep Mode, what\r
+ * indicates that some nodes in the network have already entered the Network Mode.\r
+ * The callback function shall start the network management state machine. */\r
+/** @req NM104 */\r
+void Nm_NetworkStartIndication( const NetworkHandleType nmNetworkHandle );\r
+\r
+/** Notification that the network management has entered Network Mode. The\r
+ * callback function shall enable transmission of application messages. */\r
+/** @req NM105 */\r
+void Nm_NetworkMode( const NetworkHandleType nmNetworkHandle );\r
+\r
+/** Notification that the network management has entered Prepare Bus-Sleep Mode.\r
+ * The callback function shall disable transmission of application messages. */\r
+/** @req NM106 */\r
+void Nm_PrepareBusSleepMode( const NetworkHandleType nmNetworkHandle );\r
+\r
+/** Notification that the network management has entered Bus-Sleep Mode. */\r
+/** @req NM107 */\r
+void Nm_BusSleepMode( const NetworkHandleType nmNetworkHandle );\r
+\r
+/** Notification that a NM message has been received. */\r
+/** @req NM112 */\r
+void Nm_PduRxIndication( const NetworkHandleType nmNetworkHandle );\r
+\r
+/** Notification that the CAN Generic NM state has changed. */\r
+/** @req NM114 */\r
+void Nm_StateChangeNotification(\r
+ const NetworkHandleType nmNetworkHandle,\r
+ const Nm_StateType nmPreviousState,\r
+ const Nm_StateType nmCurrentState );\r
+\r
+/** This function implements the processes of the NM Interface, which need a fix\r
+ * cyclic scheduling. This function is supplied for the NM coordinator functionality\r
+ * (Nm020). However, specific implementation may not need it (Nm093) */\r
+/** @req NM118 */\r
+void Nm_MainFunction(void);\r
+\r
+\r
+#endif /* NM_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#ifndef NMSTACK_TYPES_H_\r
+#define NMSTACK_TYPES_H_\r
+\r
+/** Return type for NM functions. Derived from Std_ReturnType. */\r
+typedef enum {\r
+ NM_E_OK,\r
+ NM_E_NOT_OK,\r
+ NM_E_NOT_EXECUTED\r
+} Nm_ReturnType;\r
+\r
+/** Operational modes of the network management */\r
+typedef enum {\r
+ NM_MODE_BUS_SLEEP,\r
+ NM_MODE_PREPARE_BUS_SLEEP,\r
+ NM_MODE_SYNCHRONIZE,\r
+ NM_MODE_NETWORK\r
+} Nm_ModeType;\r
+\r
+/** States of the network management state machine */\r
+typedef enum {\r
+ NM_STATE_UNINIT,\r
+ NM_STATE_BUS_SLEEP,\r
+ NM_STATE_PREPARE_BUS_SLEEP,\r
+ NM_STATE_READY_SLEEP,\r
+ NM_STATE_NORMAL_OPERATION,\r
+ NM_STATE_REPEAT_MESSAGE,\r
+ NM_STATE_SYNCHRONIZE\r
+} Nm_StateType;\r
+\r
+/** BusNm Type */\r
+typedef enum {\r
+ NM_BUSNM_CANNM = 0,\r
+ NM_BUSNM_FRNM = 1,\r
+ NM_BUSNM_LINNM = 2,\r
+ NM_BUSNM_UNDEF = 0xFF\r
+} Nm_BusNmType;\r
+\r
+\r
+#endif /* NMSTACK_TYPES_H_ */\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
-/*\r
- * Tests:\r
- * Ramlog\r
- *\r
- * Limitations:\r
- */\r
\r
+#ifndef NM_CBK_H_\r
+#define NM_CBK_H_\r
+\r
+\r
+#endif /* NM_CBK_H_ */\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+#ifndef NM_CONFIGTYPES_H_\r
+#define NM_CONFIGTYPES_H_\r
\r
-\r
-\r
-\r
-\r
-\r
-#ifndef COMM_H_\r
-#define COMM_H_\r
+typedef struct {\r
+ const Nm_BusNmType BusType;\r
+ const NetworkHandleType BusNmNetworkHandle;\r
+ const NetworkHandleType ComMNetworkHandle;\r
+} Nm_ChannelType;\r
\r
typedef struct {\r
- void *canIf;\r
- void *canTp;\r
- void *Frlf;\r
- void *LinIf;\r
- void *LinTp;\r
- void *PduR;\r
- void *IPDUM;\r
- void *Nm;\r
- void *Com;\r
- void *Dcm; \r
-} ComM_ConfigType;\r
+ const Nm_ChannelType* Channels;\r
+} Nm_ConfigType;\r
\r
-void ComM_Init( ComM_ConfigType *);\r
-#endif /*COMM_H_*/\r
+#endif /* NM_CONFIGTYPES_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+/** @req NVM077 */\r
+\r
+\r
+#ifndef NVM_H_\r
+#define NVM_H_\r
+\r
+#define NVM_MODULE_ID MODULE_ID_NVM\r
+#define NVM_VENDOR_ID 1\r
+\r
+#define NVM_SW_MAJOR_VERSION 1\r
+#define NVM_SW_MINOR_VERSION 0\r
+#define NVM_SW_PATCH_VERSION 0\r
+#define NVM_AR_MAJOR_VERSION 3\r
+#define NVM_AR_MINOR_VERSION 0\r
+#define NVM_AR_PATCH_VERSION 1\r
+\r
+#include "NvM_Cfg.h"\r
+/** @req NVM028 */ // NvmCommon configuration block is implemented in the NvM_Cfg.h file\r
+/** @req NVM491 *//** @req NVM492 *//** @req NVM493 *//** @req NVM494 *//** @req NVM495 */\r
+/** @req NVM496 *//** @req NVM497 *//** @req NVM498 *//** @req NVM499 */\r
+/** @req NVM501 *//** @req NVM502 *//** @req NVM503 *//** @req NVM504 *//** @req NVM505 */\r
+\r
+\r
+#if (NVM_DEV_ERROR_DETECT == STD_ON)\r
+// Error codes reported by this module defined by AUTOSAR\r
+#define NVM_E_PARAM_BLOCK_ID 0x0A\r
+#define NVM_E_PARAM_BLOCK_TYPE 0x0B\r
+#define NVM_E_PARAM_BLOCK_DATA_IDX 0x0C\r
+#define NVM_E_PARAM_ADDRESS 0x0D\r
+#define NVM_E_PARAM_DATA 0x0E\r
+#define NVM_E_NOT_INITIALIZED 0x14\r
+#define NVM_E_BLOCK_PENDING 0x15\r
+#define NVM_E_LIST_OVERFLOW 0x16\r
+#define NVM_E_NV_WRITE_PROTECTED 0x17\r
+#define NVM_E_BLOCK_CONFIG 0x18\r
+\r
+\r
+// Other error codes reported by this module\r
+#define NVM_PARAM_OUT_OF_RANGE 0x40\r
+#define NVM_UNEXPECTED_STATE 0x41\r
+#define NVM_E_WRONG_CONFIG 0xfd\r
+#define NVM_E_UNEXPECTED_EXECUTION 0xfe\r
+#define NVM_E_NOT_IMPLEMENTED_YET 0xff\r
+\r
+// Service ID in this module\r
+#define NVM_INIT_ID 0x00\r
+#define NVM_SET_DATA_INDEX_ID 0x01\r
+#define NVM_GET_DATA_INDEX_ID 0x02\r
+#define NVM_SET_BLOCK_PROTECTION_ID 0x03\r
+#define NVM_GET_ERROR_STATUS_ID 0x04\r
+#define NVM_SET_RAM_BLOCK_STATUS_ID 0x05\r
+#define NVM_READ_BLOCK_ID 0x06\r
+#define NVM_WRITE_BLOCK_ID 0x07\r
+#define NVM_RESTORE_BLOCK_DEFAULTS_ID 0x08\r
+#define NVM_ERASE_NV_BLOCK_ID 0x09\r
+#define NVM_CANCEL_WRITE_ALL_ID 0x0a\r
+#define NVM_INVALIDATENV_BLOCK_ID 0x0b\r
+#define NVM_READ_ALL_ID 0x0c\r
+#define NVM_WRITE_ALL_ID 0x0d\r
+#define NVM_MAIN_FUNCTION_ID 0x0e\r
+#define NVM_GET_VERSION_INFO_ID 0x0f\r
+\r
+#define NVM_LOC_READ_BLOCK_ID 0x40\r
+#define NVM_LOC_WRITE_BLOCK_ID 0x41\r
+#define NVM_GLOBAL_ID 0xff\r
+\r
+#endif\r
+\r
+\r
+\r
+#if ( NVM_VERSION_INFO_API == STD_ON ) /** @req NVM452 */\r
+#define NvM_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi, NVM)\r
+#endif /* NVM_VERSION_INFO_API */\r
+\r
+void NvM_MainFunction(void); /** @req NVM464 */\r
+\r
+void NvM_Init( void ); /** @req NVM447 */\r
+void NvM_ReadAll( void ); /** @req NVM460 */\r
+void NvM_WriteAll( void ); /** @req NVM461 */\r
+void NvM_CancelWriteAll( void ); /** @req NVM458 */\r
+void NvM_GetErrorStatus( NvM_BlockIdType blockId, uint8 *requestResultPtr ); /** @req NVM451 */\r
+\r
+#if (NVM_SET_RAM_BLOCK_STATUS_API == STD_ON)\r
+void Nvm_SetRamBlockStatus( NvM_BlockIdType blockId, boolean blockChanged ); /** @req NVM453 */\r
+#endif\r
+\r
+#if (NVM_API_CONFIG_CLASS > NVM_API_CONFIG_CLASS_1)\r
+void NvM_SetDataIndex( NvM_BlockIdType blockId, uint8 dataIndex ); /** @req NVM448 */\r
+void NvM_GetDataIndex( NvM_BlockIdType blockId, uint8 *dataIndexPtr ); /** @req NVM449 */\r
+void Nvm_ReadBlock( NvM_BlockIdType blockId, uint8 *dstPtr ); /** @req NVM454 */\r
+void NvM_WriteBlock( NvM_BlockIdType blockId, const uint8 *srcPtr ); /** @req NVM455 */\r
+void Nvm_RestoreBlockDefaults( NvM_BlockIdType blockId, uint8 *dstPtr ); /** @req NVM456 */\r
+#endif\r
+\r
+#if (NVM_API_CONFIG_CLASS > NVM_API_CONFIG_CLASS_2)\r
+void NvM_SetBlockProtection( NvM_BlockIdType blockId, boolean protectionEnabled ); /** @req NVM450 */\r
+void NvM_EraseNvBlock( NvM_BlockIdType blockId ); /** @req NVM457 */\r
+void NvM_InvalidateNvBlock( NvM_BlockIdType blockId ); /** @req NVM459 */\r
+#endif\r
+\r
+#endif /*NVM_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+/** @req NVM551 */\r
+\r
+\r
+#ifndef NVM_CBK_H_\r
+#define NVM_CBK_H_\r
+\r
+void NvM_JobEndNotification(void); /** @req NVM462 */\r
+void NvM_JobErrorNotification(void); /** @req NVM463 */\r
+\r
+#endif /*NVM_CBK_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef NVM_CONFIG_TYPES_H_\r
+#define NVM_CONFIG_TYPES_H_\r
+\r
+#include "NvM_Types.h"\r
+\r
+/* NvM_ApiConfigClassType */ /** @req NVM491 */\r
+#define NVM_API_CONFIG_CLASS_1 0\r
+#define NVM_API_CONFIG_CLASS_2 1\r
+#define NVM_API_CONFIG_CLASS_3 2\r
+\r
+typedef enum {\r
+ NVM_CRC16,\r
+ NVM_CRC32\r
+} Nvm_BlockCRCTypeType;\r
+\r
+typedef enum {\r
+ NVM_BLOCK_NATIVE,\r
+ NVM_BLOCK_REDUNDANT,\r
+ NVM_BLOCK_DATASET\r
+} NvM_BlockManagementTypeType;\r
+\r
+/*\r
+ * Callback function prototypes\r
+ */\r
+\r
+typedef Std_ReturnType (*NvM_SingleBlockCallbackFunctionType)(uint8 ServiceId, NvM_RequestResultType JobResult); /** @req NVM467 */\r
+typedef void (*NvM_MultiBlockCallbackFunctionType)(uint8 ServiceId, NvM_RequestResultType JobResult); /** @req NVM468 */\r
+typedef Std_ReturnType (*NvM_InitBlockCallbackFunctionType)(void); /** @req NVM469 */\r
+\r
+/*\r
+ * Containers and configuration parameters
+ */\r
+\r
+typedef struct {\r
+ NvM_MultiBlockCallbackFunctionType MultiBlockCallback; /** @req NVM500 */\r
+ // The rest of the parameters is realized in NvM_Cfg.h\r
+} NvM_CommonType;\r
+\r
+#if 0 // Currently not used\r
+typedef struct {\r
+// ??? EaRef; // TODO: Check this\r
+// ??? FeeRef; // TODO: Check this\r
+} NvM_TargetBlockReferenceType;\r
+#endif\r
+\r
+typedef struct {\r
+ // NVRAM block global settings\r
+ uint16 NvramBlockIdentifier; /** @req NVM481 */ // TODO: Remove? Not needed if block nr correspond to array index.\r
+ NvM_BlockManagementTypeType BlockManagementType; /** @req NVM062 */\r
+ uint8 BlockJobPriority; /** @req NVM477 */\r
+ boolean BlockWriteProt; /** @req NVM033 */\r
+ boolean WriteBlockOnce; /** @req NVM072 */\r
+ boolean SelectBlockForReadall; /** @req NVM117 *//** @req NVM245 */\r
+ boolean ResistantToChangesSw; /** @req NVM483 */\r
+ NvM_SingleBlockCallbackFunctionType SingleBlockCallback;\r
+ uint16 NvBlockLength; /** @req NVM479 */ // TODO: Check this\r
+\r
+ // CRC usage of RAM and NV blocks\r
+ boolean BlockUseCrc; /** @req NVM036 */\r
+ Nvm_BlockCRCTypeType BlockCRCType; /** @req NVM476 */\r
+\r
+ // RAM block, RamBlockDataAddress == NULL means temporary block otherwise permanent block\r
+ uint8 *RamBlockDataAddress; /** @req NVM482 */\r
+ boolean CalcRamBlockCrc; /** @req NVM119 */\r
+\r
+ // NV block, FEE/EA references\r
+ uint8 NvBlockNum; /** @req NVM480 */\r
+ uint32 NvramDeviceId; /** @req NVM035 */\r
+ uint16 NvBlockBaseNumber; /** @req NVM478 */\r
+\r
+ // ROM block, reference, if RomBlockDataAdress == NULL no ROM data is available\r
+ uint16 RomBlockNum; /** @req NVM485 */\r
+ uint8 *RomBlockDataAdress; /** @req NVM484 */\r
+ NvM_InitBlockCallbackFunctionType InitBlockCallback; /** @req NVM116 */\r
+\r
+ // Containers\r
+#if 0 // Currently not used\r
+ NvM_TargetBlockReferenceType TargetBlockReference; /** @req NVM486 */\r
+#endif\r
+} NvM_BlockDescriptorType; /** @req NVM061 */\r
+\r
+typedef struct {\r
+ // Containers\r
+ NvM_CommonType Common; // 1\r
+ const NvM_BlockDescriptorType *BlockDescriptor; // 1..65536\r
+} NvM_ConfigType;\r
+\r
+/*\r
+ * Make the NvM_Config visible for others.\r
+ */\r
+extern const NvM_ConfigType NvM_Config;\r
+\r
+\r
+\r
+\r
+#endif /*NVM_CONFIG_TYPES_H_*/\r
\r
\r
\r
+/** @req NVM550 */\r
\r
-#include "NvM.h"\r
-#include "Rte.h"\r
-#if defined(USE_DEM)\r
-#include "Dem.h"\r
-#endif\r
-//#include "Crc.h"\r
\r
-void NvM_Init( void ){\r
+#ifndef NVM_TYPES_H_\r
+#define NVM_TYPES_H_\r
\r
-}\r
+#include "Std_Types.h"\r
\r
-void NvM_ReadAll( void ) {\r
- \r
-}\r
+typedef uint8 NvM_RequestResultType; /** @req NVM470 */\r
+#define NVM_REQ_OK 0x00\r
+#define NVM_REQ_NOT_OK 0x01\r
+#define NVM_REQ_PENDING 0x02\r
+#define NVM_REQ_INTEGRITY_FAILED 0x03\r
+#define NVM_REQ_BLOCK_SKIPPED 0x04\r
+#define NVM_REQ_NV_INVALIDATED 0x05\r
+#define NVM_REQ_CANCELLED 0x06\r
\r
-void NvM_WriteAll( void ) {\r
- \r
-}\r
+typedef uint16 NvM_BlockIdType; /** @req NVM471 */\r
+#define NVM_MULTI_BLOCK_REQUEST_ID 0\r
+#define NVM_REDUNDANT_BLOCK_FOR_CONFIG_ID 1\r
\r
-void NvM_CancelWriteAll( void ) {\r
- \r
-}\r
+\r
+#endif /*NVM_TYPES_H_*/\r
#include "MemMap.h"\r
#include "Cpu.h"\r
\r
+typedef uint8 StatusType;\r
+\r
+#define E_OS_ACCESS (StatusType)1 /**< STD OSEK */\r
+#define E_OS_CALLEVEL (StatusType)2 /**< STD OSEK */\r
+#define E_OS_ID (StatusType)3 /**< STD OSEK */\r
+#define E_OS_LIMIT (StatusType)4 /**< STD OSEK */\r
+#define E_OS_NOFUNC (StatusType)5 /**< STD OSEK */\r
+#define E_OS_RESOURCE (StatusType)6 /**< STD OSEK */\r
+#define E_OS_STATE (StatusType)7 /**< STD OSEK */\r
+#define E_OS_VALUE (StatusType)8 /**< STD OSEK */\r
+\r
+#define E_OS_SERVICEID (StatusType)9 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_RATE (StatusType)10 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_ILLEGAL_ADDRESS (StatusType)11 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_MISSINGEND (StatusType)12 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_DISABLEDINT (StatusType)13 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_STACKFAULT (StatusType)14 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_PROTECTION_MEMORY (StatusType)15 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_PROTECTION_TIME (StatusType)16 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_PROTECTION_LOCKED (StatusType)17 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_PROTECTION_EXCEPTION (StatusType)18 /**< AUTOSAR, see 7.10 */\r
+#define E_OS_PROTECTION_RATE (StatusType)19 /**< AUTOSAR, see 7.10 */\r
+\r
+#define E_COM_ID 255 // TODO: var ska E_COM_ID vara?"\r
+\r
+\r
typedef uint32_t EventMaskType;\r
typedef EventMaskType * EventMaskRefType;\r
typedef uint16_t TaskType;\r
TASK_STATE_WAITING,\r
TASK_STATE_READY,\r
TASK_STATE_SUSPENDED,\r
- TASK_STATE_RUNNING,\r
+ TASK_STATE_RUNNING\r
} TaskStateType;\r
\r
+#define INVALID_TASK 0xdeadU\r
\r
typedef TaskStateType *TaskStateRefType;\r
\r
\r
ApplicationType GetApplicationID( void );\r
ISRType GetISRID( void );\r
+StatusType GetActiveApplicationMode( AppModeType* mode);\r
\r
typedef int8_t Os_IntCounterType;\r
\r
Irq_Disable();\r
Os_IntDisableAllCnt++;\r
/* No nesting allowed */\r
- assert(Os_IntDisableAllCnt>1);\r
+ assert(Os_IntDisableAllCnt==1);\r
}\r
\r
static inline void EnableAllInterrupts( void ) {\r
StatusType ChainTask( TaskType TaskID );\r
StatusType Schedule( void );\r
\r
-typedef uint32 ResourceType;\r
+typedef uint8 ResourceType;\r
#define DeclareResource(x) extern ResourceType (x);\r
StatusType GetResource( ResourceType ResID );\r
StatusType ReleaseResource( ResourceType ResID);\r
\r
/*\r
- * Define the scheduler resource as 0\r
+ * Define scheduler as topmost\r
*/\r
-#define RES_SCHEDULER ~(ResourceType)0\r
+#define RES_SCHEDULER OS_RESOURCE_CNT\r
\r
/*\r
* Priorities of tasks and resources\r
int OsGptChannelRef;\r
} OsDriver;\r
\r
-/*-------------------------------------------------------------------\r
- * Free running timer\r
- *-----------------------------------------------------------------*/\r
-typedef const uint32 OsTickType;\r
-void Os_SysTickInit( void );\r
-void Os_SysTickStart(uint32_t period_ticks);\r
-uint32_t Os_SysTickGetTimeElapsed( void );\r
+\r
\r
/*-------------------------------------------------------------------\r
* Counters\r
StatusType GetCounterValue( CounterType, TickRefType );\r
StatusType GetElapsedCounterValue( CounterType, TickRefType val, TickRefType elapsed_val);\r
\r
+\r
+/*-------------------------------------------------------------------\r
+ * System timer\r
+ *-----------------------------------------------------------------*/\r
+typedef const uint32 OsTickType;\r
+void Os_SysTickInit( void );\r
+void Os_SysTickStart(TickType period_ticks);\r
+TickType Os_SysTickGetValue( void );\r
+TickType Os_SysTickGetElapsedValue( TickType preValue );\r
+\r
/*-------------------------------------------------------------------\r
* Schedule Tables\r
*-----------------------------------------------------------------*/\r
OSServiceId_PostTaskHook,\r
OSServiceId_StartupHook,\r
OSServiceId_ShutdownHook,\r
- OSServiceId_GetTaskState,\r
-} OsServiceIdType;;\r
+ OSServiceId_GetTaskState\r
+} OsServiceIdType;\r
\r
-typedef struct os_error_s {\r
+typedef struct OsError {\r
OsServiceIdType serviceId;\r
uint32_t param1;\r
uint32_t param2;\r
uint32_t param3;\r
-} os_error_t;\r
+} OsErrorType;\r
\r
-extern os_error_t os_error;\r
+extern OsErrorType os_error;\r
\r
// TODO: Add the service id to all OS service methods.\r
static inline OsServiceIdType OSErrorGetServiceId(void) {\r
return os_error.serviceId;\r
}\r
\r
-extern os_error_t os_error;\r
+extern OsErrorType os_error;\r
\r
#define OSError_ActivateTask_TaskID ((TaskType) os_error.param1)\r
#define OSError_ChainTask_TaskID ((TaskType) os_error.param1)\r
\r
\r
\r
-#ifndef _PDUR_H_\r
-#define _PDUR_H_\r
+#ifndef PDUR_H\r
+#define PDUR_H\r
\r
#define PDUR_VENDOR_ID 1\r
#define PDUR_AR_MAJOR_VERSION 2\r
\r
#define PDUR_INSTANCE_ID 0\r
\r
-#include "modules.h"\r
+#include "Modules.h"\r
\r
#include "PduR_Cfg.h"\r
#include "PduR_Types.h"\r
/* Contain the current state of the PDU router. The router is uninitialized\r
* until PduR_Init has been run.\r
*/\r
-PduR_StateType PduRState;\r
+//PduR_StateType PduRState;\r
\r
extern const PduR_PBConfigType *PduRConfig;\r
\r
+/*\r
+ * The state of the PDU router.\r
+ */\r
+extern PduR_StateType PduRState;\r
+\r
\r
#if (PDUR_DEV_ERROR_DETECT == STD_ON)\r
\r
-#undef DET_REPORTERROR\r
-#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)\r
+#define PDUR_DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x,_y,_z,_q)\r
\r
// Define macro for state, parameter and data pointer checks.\r
// TODO Implement data range check if needed.\r
-#define DevCheck(PduId,PduPtr,ApiId,...) \\r
- if (PduRState == PDUR_UNINIT || PduRState == PDUR_REDUCED) { \\r
- DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, ApiId, PDUR_E_INVALID_REQUEST); \\r
- DEBUG(DEBUG_LOW,"PDU Router not initialized. Routing request ignored.\n"); \\r
+#define PduR_DevCheck(PduId,PduPtr,ApiId,...) \\r
+ if ((PduRState == PDUR_UNINIT) || (PduRState == PDUR_REDUCED)) { \\r
+ PDUR_DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, ApiId, PDUR_E_INVALID_REQUEST); \\r
return __VA_ARGS__; \\r
} \\r
- if (PduPtr == 0 && PDUR_DEV_ERROR_DETECT) { \\r
- DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, ApiId, PDUR_E_DATA_PTR_INVALID); \\r
+ if ((PduPtr == 0) && (PDUR_DEV_ERROR_DETECT)) { \\r
+ PDUR_DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, ApiId, PDUR_E_DATA_PTR_INVALID); \\r
return __VA_ARGS__; \\r
} \\r
if ((PduId >= PduRConfig->PduRRoutingTable->NRoutingPaths) && PDUR_DEV_ERROR_DETECT) { \\r
- DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, ApiId, PDUR_E_PDU_ID_INVALID); \\r
+ PDUR_DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, ApiId, PDUR_E_PDU_ID_INVALID); \\r
return __VA_ARGS__; \\r
- } \\r
+ }\r
\r
\r
#else\r
-#undef DET_REPORTERROR\r
-#define DET_REPORTERROR(_x,_y,_z,_q)\r
-#define DevCheck(...)\r
+#define PDUR_DET_REPORTERROR(_x,_y,_z,_q)\r
+#define PduR_DevCheck(...)\r
\r
#endif\r
\r
//#error fail\r
void PduR_Init(const PduR_PBConfigType* ConfigPtr);\r
void PduR_GetVersionInfo(Std_VersionInfoType* versionInfo);\r
-uint32 PduR_GetConfigurationId();\r
+uint32 PduR_GetConfigurationId(void);\r
\r
+void PduR_BufferInc(PduRTxBuffer_type *Buffer, uint8 **ptr);\r
void PduR_BufferQueue(PduRTxBuffer_type *Buffer, const uint8 * SduPtr);\r
void PduR_BufferDeQueue(PduRTxBuffer_type *Buffer, uint8 *SduPtr);\r
void PduR_BufferFlush(PduRTxBuffer_type *Buffer);\r
uint8 PduR_BufferIsFull(PduRTxBuffer_type *Buffer);\r
+void PduR_LoIfRxIndication(PduIdType PduId, const uint8* SduPtr);\r
+void PduR_LoIfTxConfirmation(PduIdType PduId);\r
+void PduR_LoIfTriggerTransmit(PduIdType PduId, uint8* SduPtr);\r
\r
/*\r
* Macros\r
*/\r
-#define setTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 1\r
-#define clearTxConfP(R) R->PduRDestPdu.TxBufferRef->TxConfP = 0\r
+#define setTxConfP(R) (R->PduRDestPdu.TxBufferRef->TxConfP = 1)\r
+#define clearTxConfP(R) (R->PduRDestPdu.TxBufferRef->TxConfP = 0)\r
\r
#endif\r
\r
extern PduR_FctPtrType PduR_StdCanFctPtrs;\r
extern PduR_FctPtrType PduR_StdLinFctPtrs;\r
\r
-#endif /* _PDUR_H_ */\r
+#endif /* PDUR_H */\r
\r
#if (PDUR_ZERO_COST_OPERATION == STD_OFF)\r
\r
- void PduR_CanIfRxIndication (PduIdType CanRxPduId, const uint8 *CanSudPtr );\r
+ void PduR_CanIfRxIndication (PduIdType CanRxPduId, const uint8 *CanSduPtr );\r
void PduR_CanIfTxConfirmation(PduIdType CanTxPduId);\r
\r
#else // Zero cost operation active\r
\r
#else\r
\r
- #define PduR_ComTransmit(... )\r
+ #define PduR_ComTransmit(... ) (E_OK)\r
\r
#endif\r
\r
\r
#else\r
\r
- #define PduR_DcmTransmit(... )\r
+ #define PduR_DcmTransmit(... ) E_OK\r
\r
#endif\r
\r
* Type definitions for PDU Router.\r
*/\r
\r
-#ifndef _PDUR_TYPES_H\r
-#define _PDUR_TYPES_H\r
+#ifndef PDUR_TYPES_H\r
+#define PDUR_TYPES_H\r
\r
#include "ComStack_Types.h"\r
\r
} PduR_DataProvisionType;\r
\r
\r
-/* ################## EXTERNAL STRUCTURES ##################\r
- *\r
- * These structures will be external in final implementation\r
- */\r
-typedef struct {\r
- const int foo;\r
-} PduR_LConfigType;\r
-\r
-\r
\r
\r
/* ################ NEW DEFINITIONS ################### */\r
typedef struct {\r
- Std_ReturnType (*TargetIndicationFctPtr)(PduIdType, const uint8*); /**< Pointer to target function in layer above PDU router. */\r
- Std_ReturnType (*TargetTransmitFctPtr)(PduIdType, const PduInfoType*); /**< Pointer to target function below PDU router. */\r
+ Std_ReturnType (*TargetIndicationFctPtr)(PduIdType pduId, const uint8* data); /**< Pointer to target function in layer above PDU router. */\r
+ Std_ReturnType (*TargetTransmitFctPtr)(PduIdType pduId, const PduInfoType* pduInfo); /**< Pointer to target function below PDU router. */\r
\r
\r
- void (*TargetConfirmationFctPtr)(PduIdType);\r
+ void (*TargetConfirmationFctPtr)(PduIdType pduId);\r
\r
/**\r
* Target function for trigger transmit requests from the interface modules, e.g. Com_TriggerTransmit. Only\r
* needed if gateway mode is not used, that is, if .DataProvision is set to PDUR_NO_PROVISION.\r
*/\r
- Std_ReturnType (*TargetTriggerTransmitFctPtr)(PduIdType, uint8*);\r
+ Std_ReturnType (*TargetTriggerTransmitFctPtr)(PduIdType pduId, uint8* data);\r
\r
\r
- Std_ReturnType (*TargetGatewayFctPtr)(PduIdType, const PduInfoType*);\r
+ Std_ReturnType (*TargetGatewayFctPtr)(PduIdType pduId, const PduInfoType* pduInfo);\r
\r
} PduR_FctPtrType;\r
\r
/*\r
* Not part of autosar standard. Added by ArcCore.\r
*/\r
- int BufferId;\r
+ uint16 BufferId;\r
PduR_DataProvisionType BufferType;\r
//uint8 SduLength;\r
uint8 *Last;\r
* General platform type definitions.\r
*/\r
\r
-#ifndef _PLATFORM_TYPES_H_\r
-#define _PLATFORM_TYPES_H_\r
+#include <stdbool.h>\r
+\r
+#ifndef PLATFORM_TYPES_H\r
+#define PLATFORM_TYPES_H\r
\r
#define CPU_TYPE CPU_TYPE_32 \r
#define CPU_BIT_ORDER MSB_FIRST \r
#define CPU_BYTE_ORDER HIGH_BYTE_FIRST\r
\r
-#define FALSE 0\r
-#define TRUE 1\r
+#define FALSE (boolean)false\r
+#define TRUE (boolean)true\r
\r
-typedef unsigned long boolean; \r
+//typedef unsigned long boolean;\r
+typedef _Bool boolean;\r
typedef signed char sint8; \r
typedef unsigned char uint8; \r
typedef signed short sint16; \r
typedef unsigned short uint16; \r
typedef signed long sint32; \r
-typedef unsigned long uint32; \r
+typedef unsigned long uint32;\r
typedef unsigned long long uint64;\r
typedef unsigned long uint8_least; \r
typedef unsigned long uint16_least; \r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/** @addtogroup Port Port Driver\r
- * @{ */\r
-\r
-/** @file Port.h\r
- * API and type definitions for Port Driver.\r
- */\r
-\r
-#ifndef PORT_H_\r
-#define PORT_H_\r
-\r
-#define PORT_SW_MAJOR_VERSION 1 \r
-#define PORT_SW_MINOR_VERSION 0 \r
-#define PORT_SW_PATCH_VERSION 0 \r
-\r
-#define PORT_AR_MAJOR_VERSION 3\r
-#define PORT_AR_MINOR_VERSION 0 \r
-#define PORT_AR_PATCH_VERSION 2 \r
-\r
-#include "Port_Cfg.h"\r
-\r
-#if PORT_VERSION_INFO_API == STD_ON\r
-void Port_GetVersionInfo( Std_VersionInfoType *versionInfo );\r
-#endif \r
-\r
-/** @name Error Codes */\r
-//@{\r
-#define PORT_E_PARAM_PIN 0x0a\r
-#define PORT_E_DIRECTION_UNCHANGEABLE 0x0b\r
-#define PORT_E_PARAM_CONFIG 0x0c\r
-#define PORT_E_PARAM_INVALID_MODE 0x0d\r
-#define PORT_E_MODE_UNCHANGEABLE 0x0e\r
-#define PORT_E_UNINIT 0x0f\r
-//@}\r
-\r
-/** @name Service id's */\r
-//@{\r
-#define PORT_INIT_ID 0x00\r
-#define PORT_SET_PIN_DIRECTION_ID 0x01\r
-#define PORT_REFRESH_PORT_DIRECTION_ID 0x02\r
-#define PORT_GET_VERSION_INFO_ID 0x03\r
-#define PORT_SET_PIN_MODE_ID 0x04\r
-//@}\r
-\r
-/**\r
- * PORT046: The type Port_PinDirectionType is a type for defining the direction of a Port Pin. \r
- * PORT_PIN_IN Sets port pin as input. \r
- * PORT_PIN_OUT Sets port pin as output. \r
- */\r
-typedef enum\r
-{\r
- PORT_PIN_IN = 0,\r
- PORT_PIN_OUT,\r
-} Port_PinDirectionType;\r
-\r
-typedef uint32 Port_PinModeType;\r
-typedef enum\r
-{\r
- PORT_UNINITIALIZED = 0,\r
- PORT_INITIALIZED,\r
-} Port_StateType;\r
-\r
-void Port_Init( const Port_ConfigType *configType );\r
-void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction );\r
-void Port_RefreshPortDirection( void );\r
-void Port_SetPinMode( Port_PinType Pin, Port_PinModeType Mode );\r
-\r
-#endif /*PORT_H_*/\r
-/** @} */\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Port Port Driver
+ * @{ */
+
+/** @file Port.h
+ * API and type definitions for Port Driver.
+ */
+
+#ifndef PORT_H_
+#define PORT_H_
+
+#define PORT_SW_MAJOR_VERSION 1
+#define PORT_SW_MINOR_VERSION 0
+#define PORT_SW_PATCH_VERSION 0
+
+#define PORT_AR_MAJOR_VERSION 3
+#define PORT_AR_MINOR_VERSION 1
+#define PORT_AR_PATCH_VERSION 0
+
+#include "Port_Cfg.h" /** @req PORT130 */
+
+#if (PORT_VERSION_INFO_API == STD_ON)
+void Port_GetVersionInfo(Std_VersionInfoType *versionInfo);
+#endif
+
+/** @name Error Codes */
+/** @req PORT051 */
+/** @req PORT116 */
+#define PORT_E_PARAM_PIN 0x0a
+#define PORT_E_DIRECTION_UNCHANGEABLE 0x0b
+#define PORT_E_PARAM_CONFIG 0x0c
+#define PORT_E_PARAM_INVALID_MODE 0x0d
+#define PORT_E_MODE_UNCHANGEABLE 0x0e
+#define PORT_E_UNINIT 0x0f
+//@}
+
+/** @name Service id's */
+//@{
+#define PORT_INIT_ID 0x00
+#define PORT_SET_PIN_DIRECTION_ID 0x01
+#define PORT_REFRESH_PORT_DIRECTION_ID 0x02
+#define PORT_GET_VERSION_INFO_ID 0x03
+#define PORT_SET_PIN_MODE_ID 0x04
+//@}
+
+/** @req PORT046
+ * The type Port_PinDirectionType is a type for defining the direction of a Port Pin.
+ * PORT_PIN_IN Sets port pin as input.
+ * PORT_PIN_OUT Sets port pin as output.
+ */
+typedef enum
+{
+ PORT_PIN_IN = 0, PORT_PIN_OUT,
+} Port_PinDirectionType;
+
+#if defined(CFG_HC1X)
+/** @req PORT124 */
+typedef uint8 Port_PinModeType;
+#else // CFG_PPC, CFG_STM32_STAMP and others
+typedef uint32 Port_PinModeType;
+#endif
+
+void Port_Init(const Port_ConfigType *configType);
+
+#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )
+void Port_SetPinDirection(Port_PinType pin, Port_PinDirectionType direction);
+#endif
+
+void Port_RefreshPortDirection(void);
+
+#if (PORT_SET_PIN_MODE_API == STD_ON)
+void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode);
+#endif
+
+#endif /*PORT_H_*/
+/** @} */
# define Pwm_ReportError(ErrorId)\r
#endif\r
\r
+#if PWM_DEV_ERROR_DETECT==STD_ON\r
+# define Pwm_ReportError(ErrorId) Det_ReportError( MODULE_ID_PWM, 0, 0, ErrorId);\r
+#else\r
+# define Pwm_ReportError(ErrorId)\r
+#endif\r
+\r
/**************************************************************\r
* Type definitions\r
**************************************************************/\r
\r
\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
#ifndef RTE_H_\r
#define RTE_H_\r
\r
-\r
-\r
-/* Contract \r
- * rte_sws_1143\r
- * <name>_<c>_<p>_<o>\r
- * <p> - port name, e.g \r
- * <c> - component name, e.g. doors, lights\r
- * <o> - operation name or element name\r
- *\r
- * and more \r
- * Rte_Pim?\r
- * Rte_CData?\r
- */\r
-\r
-/* \r
- * Generated, rte_sws_3730(p.154)\r
- */\r
-#define Rte_Send_p_d\r
-#define Rte_Switch_p_m\r
-#define Rte_Write_p_d\r
-#define Rte_Invalidate_p_d\r
-#define Rte_Feedback_p_d\r
-#define Rte_Read_p_d\r
-#define Rte_Receive_p_d\r
-#define Rte_Call_p_o\r
-#define Rte_Result_p_o\r
-#define Rte_Mode_p_o\r
-\r
+#include "Std_Types.h"\r
\r
// Errors\r
-typedef uint8 Std_ReturnType;\r
#define RTE_E_OK ((Std_ReturnType) 0)\r
#define RTE_E_INVALID ((Std_ReturnType) 1)\r
#define RTE_E_COMMS_ERROR ((Std_ReturnType) 128)\r
#define RTE_E_MAX_AGE_EXCEEDED ((Std_ReturnType) 64)\r
\r
\r
-// RTE Mode, TODO\r
-\r
-// Rte_Ports\r
-#define Rte_PortHandle_i_RP\r
-#define Rte_Ports_i_RP\r
-\r
-// Rte_NPorts\r
-#define Rte_NPorts_i_RP\r
-\r
-// Rte_Port\r
-//#define Rte_PortHandle_i_RP\r
-#define Rte_Port_RP\r
-\r
-// Rte_Send/Rte_Write/Rte_Switch\r
-#define Rte_Write_p_o\r
-#define Rte_Send_p_o\r
-#define Rte_Swich_p_o\r
-\r
-// Rte_Invalidate\r
-#define Rte_Invalidate_p_o\r
-\r
-// Rte_Feedback\r
-#define Rte_Feedback_p_o\r
-\r
-// Rte_Read\r
-#define Rte_Read_p_o\r
-\r
-// Rte_Receive\r
-#define Rte_Receive_p_o\r
-\r
-// Rte_Call\r
-#define Rte_Call_p_o\r
-\r
-// Rte_Result\r
-#define Rte_Result_p_o\r
-\r
-//Rte_Pim\r
-#define Rte_Pim_name\r
-\r
-// Rte_CData\r
-#define Rte_CData_name\r
-\r
-// Rte_IRead\r
-#define Rte_IRead_re_p_d\r
-\r
-// Rte_IWrite\r
-#define Rte_IWrite_re_p_d\r
-\r
-// Rte_IInvalidate\r
-#define Rte_IInvalidate_re_p_d\r
-\r
-// Rte_IStatus\r
-#define Rte_IStatus_re_p_d\r
-\r
-// Rte_IrvIRead\r
-#define Rte_IrvIRead_re_name\r
-\r
-// TODO: bla bla bla .. more methods\r
-//\r
-\r
-\r
-// RTE Lifecycle API reference.( see chap 5.8 )\r
-Std_ReturnType Rte_Start( void );\r
-Std_ReturnType Rte_Stop( void );\r
-\r
#endif /*RTE_H_*/\r
-\r
-\r
-\r
-\r
-\r
-\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+#ifndef RTE_MAIN_H_\r
+#define RTE_MAIN_H_\r
\r
+Std_ReturnType Rte_Start( void );\r
+Std_ReturnType Rte_Stop( void );\r
\r
-\r
-\r
-\r
-\r
-\r
-#ifndef MEMIF_CFG_H_\r
-#define MEMIF_CFG_H_\r
-\r
-// TODO. include FEE and EA modules\r
-\r
-\r
-\r
-#endif /*MEMIF_CFG_H_*/\r
+#endif /*RTE_MAIN_H_*/\r
* Definitions of General types.\r
*/\r
\r
-#ifndef _STD_TYPES_H\r
-#define _STD_TYPES_H\r
+#ifndef STD_TYPES_H\r
+#define STD_TYPES_H\r
\r
// Autosar include files....\r
// TODO: we haven't really defined the autosar types yet.\r
#include "Compiler.h"\r
\r
#ifndef NULL\r
+//lint -esym(960,20.2) // PC-Lint LINT EXCEPTION\r
#define NULL 0\r
#endif\r
\r
#define STD_GET_VERSION (_major,_minor,_patch) (_major * 10000 + _minor * 100 + _patch)\r
\r
/** Create Std_VersionInfoType */\r
+// PC-Lint Exception MISRA rule 19.12\r
+//lint -save -esym(960,19.12)\r
#define STD_GET_VERSION_INFO(_vi,_module) \\r
- ((_vi)->vendorID = _module ## _VENDOR_ID);\\r
- ((_vi)->moduleID = _module ## _MODULE_ID);\\r
- ((_vi)->sw_major_version = _module ## _SW_MAJOR_VERSION);\\r
- ((_vi)->sw_minor_version = _module ## _SW_MINOR_VERSION);\\r
- ((_vi)->sw_patch_version = _module ## _SW_PATCH_VERSION);\\r
- ((_vi)->ar_major_version = _module ## _AR_MAJOR_VERSION);\\r
- ((_vi)->ar_minor_version = _module ## _AR_MINOR_VERSION);\\r
- ((_vi)->ar_patch_version = _module ## _AR_PATCH_VERSION);\r
-\r
-\r
-// TODO: Move to OSEK implementation, See 8.2 in SWS_StandardTypes\r
-\r
-#define STATUSTYPEDEFINED\r
-typedef enum {\r
- E_OK = 0,\r
- E_OS_ACCESS = 1, /**< STD OSEK */\r
- E_OS_CALLEVEL = 2, /**< STD OSEK */\r
- E_OS_ID = 3, /**< STD OSEK */\r
- E_OS_LIMIT = 4, /**< STD OSEK */\r
- E_OS_NOFUNC = 5, /**< STD OSEK */\r
- E_OS_RESOURCE = 6, /**< STD OSEK */\r
- E_OS_STATE = 7, /**< STD OSEK */\r
- E_OS_VALUE = 8, /**< STD OSEK */\r
-\r
- E_OS_SERVICEID, /**< AUTOSAR, see 7.10 */\r
- E_OS_RATE , /**< AUTOSAR, see 7.10 */\r
- E_OS_ILLEGAL_ADDRESS , /**< AUTOSAR, see 7.10 */\r
- E_OS_MISSINGEND , /**< AUTOSAR, see 7.10 */\r
- E_OS_DISABLEDINT , /**< AUTOSAR, see 7.10 */\r
- E_OS_STACKFAULT , /**< AUTOSAR, see 7.10 */\r
- E_OS_PROTECTION_MEMORY , /**< AUTOSAR, see 7.10 */\r
- E_OS_PROTECTION_TIME , /**< AUTOSAR, see 7.10 */\r
- E_OS_PROTECTION_LOCKED , /**< AUTOSAR, see 7.10 */\r
- E_OS_PROTECTION_EXCEPTION , /**< AUTOSAR, see 7.10 */\r
- E_OS_PROTECTION_RATE, /**< AUTOSAR, see 7.10 */\r
-\r
- /* COM.. TODO: move ?? */\r
- E_COM_ID,\r
-\r
-\r
- /** Implementation specific */\r
- E_OS_SYS_APA,\r
-\r
- E_NOT_OK,\r
-} StatusType;\r
-\r
-typedef uint8 Std_ReturnType;\r
+ if(_vi != NULL) {\\r
+ ((_vi)->vendorID = _module ## _VENDOR_ID);\\r
+ ((_vi)->moduleID = _module ## _MODULE_ID);\\r
+ ((_vi)->sw_major_version = _module ## _SW_MAJOR_VERSION);\\r
+ ((_vi)->sw_minor_version = _module ## _SW_MINOR_VERSION);\\r
+ ((_vi)->sw_patch_version = _module ## _SW_PATCH_VERSION);\\r
+ ((_vi)->ar_major_version = _module ## _AR_MAJOR_VERSION);\\r
+ ((_vi)->ar_minor_version = _module ## _AR_MINOR_VERSION);\\r
+ ((_vi)->ar_patch_version = _module ## _AR_PATCH_VERSION);\\r
+ }\r
+//lint -restore\r
\r
\r
-#ifndef STATUSTYPEDEFINED\r
-#define STATUSTYPEDEFINED\r
-#define E_OK 0\r
-typedef unsigned char StatusType;\r
-#endif\r
-\r
-#define E_NOT_OK 1\r
+typedef uint8 Std_ReturnType;\r
\r
-#define E_NO_DTC_AVAILABLE 2\r
-#define E_SESSION_NOT_ALLOWED 4\r
-#define E_PROTOCOL_NOT_ALLOWED 5\r
-#define E_REQUEST_NOT_ACCEPTED 8\r
-#define E_REQUEST_ENV_NOK 9\r
-#define E_PENDING 10\r
-#define E_COMPARE_KEY_FAILED 11\r
-#define E_FORCE_RCRRP 12\r
+#define E_OK (Std_ReturnType)0\r
+#define E_NOT_OK (Std_ReturnType)1\r
+\r
+#define E_NO_DTC_AVAILABLE (Std_ReturnType)2\r
+#define E_SESSION_NOT_ALLOWED (Std_ReturnType)4\r
+#define E_PROTOCOL_NOT_ALLOWED (Std_ReturnType)5\r
+#define E_REQUEST_NOT_ACCEPTED (Std_ReturnType)8\r
+#define E_REQUEST_ENV_NOK (Std_ReturnType)9\r
+#define E_PENDING (Std_ReturnType)10\r
+#define E_COMPARE_KEY_FAILED (Std_ReturnType)11\r
+#define E_FORCE_RCRRP (Std_ReturnType)12\r
\r
#define STD_HIGH 0x01\r
#define STD_LOW 0x00\r
\r
void Os_Arc_GetStackInfo( TaskType pid, StackInfoType *s );\r
\r
-#define OS_STACK_USAGE(_x) ((((_x)->size - (uint32_t)((_x)->usage - (_x)->top))*100)/(_x)->size)\r
+#define OS_STACK_USAGE(_x) ((((_x)->size - (uint32_t)((size_t)(_x)->usage - (size_t)(_x)->top))*100)/(_x)->size)\r
\r
// int printf(const char *format, ...);\r
\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#ifndef CPU_H_\r
-#define CPU_H_\r
-\r
-#include <stdint.h>\r
-#include "stm32f10x.h"\r
-#include "core_cm3.h"\r
-\r
-#define SIMULATOR() (0==0)\r
-\r
-/* Call intrinsic functions directly */\r
-#define Irq_Disable() __disable_irq()\r
-#define Irq_Enable() __enable_irq()\r
-\r
-/* TODO: This is of course wrong */\r
-#define Irq_Save(_flags) _flags =_Irq_Save();\r
-#define Irq_Restore(_flags) _Irq_Restore(_flags);\r
-\r
-\r
-#define Irq_SuspendAll() Irq_Disable()\r
-#define Irq_ResumeAll() Irq_Enable()\r
-\r
-#define Irq_SuspendOs() Irq_Disable()\r
-#define Irq_ResumeOs() Irq_Enable()\r
-\r
-static inline unsigned long _Irq_Save(void)\r
-{\r
- unsigned long val = __get_PRIMASK();\r
- Irq_Disable();\r
- return val;\r
-}\r
-\r
-/*-----------------------------------------------------------------*/\r
-\r
-static inline void _Irq_Restore(unsigned mask) {\r
- __set_PRIMASK(mask);\r
-}\r
-\r
-#define CallService(index,param)\r
-\r
-#endif /* CPU_H_ */\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#ifndef CPU_H_
+#define CPU_H_
+
+#include <stdint.h>
+
+#if defined(CFG_ARM_CM3)
+#include "stm32f10x.h"
+#elif defined(CFG_ARM_CR4)
+#include "core_cr4.h"
+#endif
+
+/* Call architecture specific code */
+#define Irq_Disable() __disable_irq()
+#define Irq_Enable() __enable_irq()
+
+#define Irq_Save(_flags) _flags = _Irq_Save();
+#define Irq_Restore(_flags) _Irq_Restore(_flags);
+
+#define Irq_SuspendAll() Irq_Disable()
+#define Irq_ResumeAll() Irq_Enable()
+
+#define Irq_SuspendOs() Irq_Disable()
+#define Irq_ResumeOs() Irq_Enable()
+
+
+#define CallService(index,param)
+
+#endif /* CPU_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef ADC_CONFIGTYPES_H_\r
+#define ADC_CONFIGTYPES_H_\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+/* Group definitions. */\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK\r
+}Adc_ClockSourceType;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DISABLED,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ Adc_ClockSourceType clockSource;\r
+ uint8_t hwUnitId;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_64_CLOCKS,\r
+ ADC_CONVERSION_TIME_128_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+/* Channel definitions, std container */\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType adcChannelConvTime;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;\r
+ // NOT SUPPORTED Adc_ResolutionType adcChannelResolution;\r
+ // NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;\r
+} Adc_ChannelConfigurationType;\r
+\r
+/* Used ?? */\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINUOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+/* Implementation specific */\r
+typedef struct\r
+{\r
+ // NOT SUPPORTED Adc_GroupAccessModeType accessMode;\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ // NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;\r
+ // NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;\r
+ void (*groupCallback)(void);\r
+ // NOT SUPPORTED Adc_StreamBufferModeType streamBufferMode;\r
+ // NOT SUPPORTED Adc_StreamNumSampleType streamNumSamples;\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ // NOT SUPPORTED Adc_CommandType *commandBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+ // NOT SUPPORTED Dma_ChannelType dmaCommandChannel;\r
+ // NOT SUPPORTED Dma_ChannelType dmaResultChannel;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMACommands;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMAResults;\r
+} Adc_GroupDefType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_ChannelConfigurationType* channelConfigPtr;\r
+ const uint16_t nbrOfChannels;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+ const uint16_t nbrOfGroups;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig [];\r
+\r
+\r
+#endif /* ADC_CONFIGTYPES_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef MCU_CONFIGTYPES_H_\r
+#define MCU_CONFIGTYPES_H_\r
+\r
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)\r
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)\r
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)\r
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)\r
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)\r
+\r
+#ifndef STM32F10X_CL\r
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)\r
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)\r
+#else\r
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)\r
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)\r
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)\r
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)\r
+#endif\r
+\r
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)\r
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)\r
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)\r
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)\r
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)\r
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)\r
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)\r
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)\r
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)\r
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)\r
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)\r
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)\r
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)\r
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)\r
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)\r
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)\r
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)\r
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)\r
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)\r
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)\r
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)\r
+\r
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)\r
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)\r
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)\r
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)\r
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)\r
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)\r
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)\r
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)\r
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)\r
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)\r
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)\r
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)\r
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)\r
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)\r
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)\r
+\r
+typedef struct {\r
+ uint32 AHBClocksEnable;\r
+ uint32 APB1ClocksEnable;\r
+ uint32 APB2ClocksEnable;\r
+} Mcu_PerClockConfigType;\r
+\r
+extern const Mcu_PerClockConfigType McuPerClockConfigData;\r
+\r
+\r
+#endif /* MCU_CONFIGTYPES_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef PORT_CONFIGTYPES_H_\r
+#define PORT_CONFIGTYPES_H_\r
+\r
+#define GPIO_INPUT_MODE (0)\r
+#define GPIO_OUTPUT_10MHz_MODE (1)\r
+#define GPIO_OUTPUT_2MHz_MODE (2)\r
+#define GPIO_OUTPUT_50MHz_MODE (3)\r
+\r
+/* Valid for input modes. */\r
+#define GPIO_ANALOG_INPUT_CNF (0 << 2)\r
+#define GPIO_FLOATING_INPUT_CNF (1 << 2)\r
+#define GPIO_INPUT_PULLUP_CNF (2 << 2)\r
+#define GPIO_RESERVED_CNF (3 << 2)\r
+\r
+/* Valid for output modes. */\r
+#define GPIO_OUTPUT_PUSHPULL_CNF (0 << 2)\r
+#define GPIO_OUTPUT_OPENDRAIN_CNF (1 << 2)\r
+#define GPIO_ALT_PUSHPULL_CNF (2 << 2)\r
+#define GPIO_ALT_OPENDRAIN_CNF (3 << 2)\r
+\r
+#define GPIO_OUTPUT_LOW (0)\r
+#define GPIO_OUTPUT_HIGH (1)\r
+\r
+typedef struct\r
+{\r
+ uint8_t GpioPinCnfMode_0:4;\r
+ uint8_t GpioPinCnfMode_1:4;\r
+ uint8_t GpioPinCnfMode_2:4;\r
+ uint8_t GpioPinCnfMode_3:4;\r
+ uint8_t GpioPinCnfMode_4:4;\r
+ uint8_t GpioPinCnfMode_5:4;\r
+ uint8_t GpioPinCnfMode_6:4;\r
+ uint8_t GpioPinCnfMode_7:4;\r
+ uint8_t GpioPinCnfMode_8:4;\r
+ uint8_t GpioPinCnfMode_9:4;\r
+ uint8_t GpioPinCnfMode_10:4;\r
+ uint8_t GpioPinCnfMode_11:4;\r
+ uint8_t GpioPinCnfMode_12:4;\r
+ uint8_t GpioPinCnfMode_13:4;\r
+ uint8_t GpioPinCnfMode_14:4;\r
+ uint8_t GpioPinCnfMode_15:4;\r
+}GpioPinCnfMode_Type;\r
+\r
+typedef struct\r
+{\r
+ uint8_t GpioPinOutLevel_0:1;\r
+ uint8_t GpioPinOutLevel_1:1;\r
+ uint8_t GpioPinOutLevel_2:1;\r
+ uint8_t GpioPinOutLevel_3:1;\r
+ uint8_t GpioPinOutLevel_4:1;\r
+ uint8_t GpioPinOutLevel_5:1;\r
+ uint8_t GpioPinOutLevel_6:1;\r
+ uint8_t GpioPinOutLevel_7:1;\r
+ uint8_t GpioPinOutLevel_8:1;\r
+ uint8_t GpioPinOutLevel_9:1;\r
+ uint8_t GpioPinOutLevel_10:1;\r
+ uint8_t GpioPinOutLevel_11:1;\r
+ uint8_t GpioPinOutLevel_12:1;\r
+ uint8_t GpioPinOutLevel_13:1;\r
+ uint8_t GpioPinOutLevel_14:1;\r
+ uint8_t GpioPinOutLevel_15:1;\r
+}GpioPinOutLevel_Type;\r
+\r
+/* To be compatible with Port.h */\r
+typedef uint8_t Port_PinType;\r
+\r
+/** Top level configuration container */\r
+typedef struct\r
+{\r
+ /** Total number of pins */\r
+ uint16_t padCnt;\r
+ /** List of pin configurations */\r
+ const GpioPinCnfMode_Type *padConfig;\r
+ const GpioPinOutLevel_Type *outConfig;\r
+ /** Total number of pin default levels */\r
+\r
+ uint16_t remapCount;\r
+ const uint32_t* remaps;\r
+\r
+} Port_ConfigType;\r
+\r
+\r
+#endif /* PORT_CONFIGTYPES_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef PWM_CONFIGTYPES_H_\r
+#define PWM_CONFIGTYPES_H_\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+typedef enum {\r
+ PWM_CHANNEL_11 = 0, // TIM1 Channel 1\r
+ PWM_CHANNEL_12,\r
+ PWM_CHANNEL_13,\r
+ PWM_CHANNEL_14,\r
+ PWM_CHANNEL_21, // TIM2 Channel 1\r
+ PWM_CHANNEL_22,\r
+ PWM_CHANNEL_23,\r
+ PWM_CHANNEL_24,\r
+ PWM_CHANNEL_31, // TIM3 Channel 1\r
+ PWM_CHANNEL_32,\r
+ PWM_CHANNEL_33,\r
+ PWM_CHANNEL_34,\r
+ PWM_CHANNEL_41, // TIM4 Channel 1\r
+ PWM_CHANNEL_42,\r
+ PWM_CHANNEL_43,\r
+ PWM_CHANNEL_44,\r
+ PWM_TOTAL_NOF_CHANNELS,\r
+} Pwm_ChannelType;\r
+\r
+typedef enum {\r
+ PWM_CHANNEL_PRESCALER_1=0,\r
+ PWM_CHANNEL_PRESCALER_2,\r
+ PWM_CHANNEL_PRESCALER_3,\r
+ PWM_CHANNEL_PRESCALER_4,\r
+} Pwm_ChannelPrescalerType;\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period\r
+\r
+typedef struct {\r
+ /* Number of duty ticks */\r
+ uint32_t duty:32;\r
+ /* Length of period, in ticks */\r
+ uint32_t period:32;\r
+ /* Counter */\r
+ uint32_t counter:32;\r
+ /* Enable freezing the channel when in debug mode */\r
+ uint32_t freezeEnable:1;\r
+ /* Disable output */\r
+ uint32_t outputDisable:1;\r
+ /* Select which bus disables the bus\r
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */\r
+ uint32_t outputDisableSelect:2;\r
+ /* Prescale the emios clock some more? */\r
+ Pwm_ChannelPrescalerType prescaler:2;\r
+ /* Prescale the emios clock some more? */\r
+ uint32_t usePrescaler:1;\r
+ /* Whether to use DMA. Currently unsupported */\r
+ uint32_t useDma:1;\r
+ uint32_t reserved_2:1;\r
+ /* Input filter. Ignored in output mode. */\r
+ uint32_t inputFilter:4;\r
+ /* Input filter clock source. Ignored in output mode */\r
+ uint32_t filterClockSelect:1;\r
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */\r
+ uint32_t flagEnable:1;\r
+ uint32_t reserved_3:3;\r
+ /* Trigger a match on channel A */\r
+ uint32_t forceMatchA:1;\r
+ /* Triggers a match on channel B */\r
+ uint32_t forceMatchB:1;\r
+ uint32_t reserved_4:1;\r
+ /* We can use different buses for the counter. Use the internal counter */\r
+ uint32_t busSelect:2;\r
+ /* What edges to flag on? */\r
+ uint32_t edgeSelect:1;\r
+ /* Polarity of the channel */\r
+ uint32_t edgePolarity:1;\r
+ /* EMIOS mode. 0x58 for buffered output PWM */\r
+ uint32_t mode:7;\r
+} Pwm_ChannelRegisterType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelRegisterType r;\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+\r
+\r
+// Channel configuration macro.\r
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \\r
+ {\\r
+ .channel = _hwchannel,\\r
+ .r = {\\r
+ DUTY_AND_PERIOD(_duty, _period),\\r
+ .freezeEnable = 1,\\r
+ .outputDisable = 0,\\r
+ .usePrescaler = 1,\\r
+ .prescaler = _prescaler,\\r
+ .useDma = 0,\\r
+ .flagEnable = 0, /* See PWM052 */ \\r
+ .busSelect = 3, /* Use the internal counter bus */\\r
+ .edgePolarity = _polarity,\\r
+ .mode = 0\\r
+ }\\r
+ }\r
+\r
+#endif /* PWM_CONFIGTYPES_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#ifndef CIRQ_BUFFER_H_
+#define CIRQ_BUFFER_H_
+
+#include <stddef.h>
+
+typedef struct {
+ /* The max number of elements in the list */
+ int maxCnt;
+ int currCnt;
+
+ /* Size of the elements in the list */
+ size_t dataSize;
+ /* List head and tail */
+ void *head;
+ void *tail;
+
+ /* Buffer start/stop */
+ void *bufStart;
+ void *bufEnd;
+} CirqBufferType;
+
+/* Dynamic implementation */
+CirqBufferType *CirqBuffDynCreate( size_t size, size_t dataSize );
+int CirqBuffDynDestroy(CirqBufferType *cPtr );
+
+/* Static implementation */
+CirqBufferType CirqBuffStatCreate(void *buffer, int maxCnt, size_t dataSize);
+
+int CirqBuffPush( CirqBufferType *cPtr, void *dataPtr );
+int CirqBuffPop(CirqBufferType *cPtr, void *dataPtr );
+
+#endif /* CIRQ_BUFFER_H_ */
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
+// PC-Lint Exception to MISRA rule 19.12: stdio ok in debug.h.\r
+//lint -e(829)\r
+\r
\r
#ifndef DEBUG_H_\r
#define DEBUG_H_\r
\r
-\r
/**\r
*\r
* NOTE!!!!\r
#endif\r
\r
#if defined(USE_LDEBUG_PRINTF)\r
-#define LDEBUG_PRINTF(format,...) printf(format,## __VA_ARGS__ )\r
+#define LDEBUG_PRINTF(format,...) printf(format,## __VA_ARGS__ )\r
+#define LDEBUG_FPUTS(_str) fputs((_str),stdout)\r
#else\r
#define LDEBUG_PRINTF(format,...)\r
+#define LDEBUG_FPUTS(_str)\r
#endif\r
\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef CPU_H\r
+#define CPU_H\r
+\r
+#include "Std_Types.h"\r
+\r
+#define Irq_Save(flags) ((flags) = 0) // Dummy assignment to avoid compiler warnings\r
+#define Irq_Restore(flags) (void)(flags)\r
+\r
+#define Irq_Disable()\r
+#define Irq_Enable()\r
+\r
+#define Irq_SuspendAll() Irq_Disable()\r
+#define Irq_ResumeAll() Irq_Enable()\r
+\r
+#define Irq_SuspendOs() Irq_Disable()\r
+#define Irq_ResumeOs() Irq_Enable()\r
+\r
+#endif /* CPU_H */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef ADC_CONFIGTYPES_H_\r
+#define ADC_CONFIGTYPES_H_\r
+\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_NOF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_4_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_16_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+\r
+typedef enum\r
+{\r
+ ADC_RESOLUTION_10_BIT,\r
+ ADC_RESOLUTION_8_BIT,\r
+}Adc_ResolutionType;\r
+\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINUOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+typedef struct\r
+{\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ void (*groupCallback)(void);\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+} Adc_GroupDefType;\r
+\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType convTime;\r
+ Adc_ResolutionType resolution;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig[];\r
+#endif /* ADC_CONFIGTYPES_H_ */\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
#ifndef _REGS_H_\r
#define _REGS_H_\r
\r
-#define IO_BASE 0\r
-\r
-#define ienable() __asm("cli");\r
-#define idisable() __asm("orcc #0x10")\r
-#define xenable() __asm("andcc #0xbf")\r
-#define xdisable()__asm("orcc #0x40")\r
-\r
-/**\r
- * constant offsets to use where a C expression doesn't work\r
- * You may use it with GEL\r
- */\r
-#define M6811_PORTA 0x00\r
-#define M6811_PORTB 0x01\r
-#define M6811_PTT 0x240\r
-#define M6811_PTM 0x250\r
-#define M6811_PTP 0x258\r
-#define M6811_PTH 0x260\r
-\r
-#define PORTIO_8 *(volatile unsigned char *)\r
-#define PORTIO_16 *(volatile unsigned short int *)\r
-\r
-\r
-/* \r
- * Core HC12 Registers\r
- */\r
-#define PORTA PORTIO_8(IO_BASE + 0x00) /* port A */\r
-#define PORTB PORTIO_8(IO_BASE + 0x01) /* port B */\r
-#define DDRA PORTIO_8(IO_BASE + 0x02) /* data direction port A */\r
-#define DDRB PORTIO_8(IO_BASE + 0x03) /* data direction port B */\r
-#define PORTE PORTIO_8(IO_BASE + 0x08) /* port E */\r
-#define DDRE PORTIO_8(IO_BASE + 0x09) /* data direction port E */\r
-#define PEAR PORTIO_8(IO_BASE + 0x0a) /* port E assignment register */\r
-#define MODE PORTIO_8(IO_BASE + 0x0b) /* mode register */\r
-#define PUCR PORTIO_8(IO_BASE + 0x0c) /* pull-up control register */\r
-#define RDRIV PORTIO_8(IO_BASE + 0x0d) /* reduced drive of I/O lines */\r
-#define EBICTL PORTIO_8(IO_BASE + 0x0e) /* external bus control */\r
-#define INITRM PORTIO_8(IO_BASE + 0x10) /* RAM mapping register */\r
-#define INITRG PORTIO_8(IO_BASE + 0x11) /* IO mapping register */\r
-#define INITEE PORTIO_8(IO_BASE + 0x12) /* EEPROM mapping register */\r
-#define MISC PORTIO_8(IO_BASE + 0x13) /* mapping control register */\r
-#define MTST0 PORTIO_8(IO_BASE + 0x14) /* mapping test register 0 */\r
-#define ITCR PORTIO_8(IO_BASE + 0x15) /* interrupt test control reg. */\r
-#define ITEST PORTIO_8(IO_BASE + 0x16) /* interrupt test register */\r
-#define MTST1 PORTIO_8(IO_BASE + 0x17) /* mapping test register 1 */\r
-#define PARTID PORTIO_16(IO_BASE + 0x1a) /* part ID register */\r
-#define MEMSIZ0 PORTIO_8(IO_BASE + 0x1c) /* memory size register 0 */\r
-#define MEMSIZ1 PORTIO_8(IO_BASE + 0x1d) /* memory size register 1 */\r
-#define INTCR PORTIO_8(IO_BASE + 0x1e) /* interrupt control */\r
-#define HPRIO PORTIO_8(IO_BASE + 0x1f) /* highest priority */\r
-\r
-// Bitflags - PEAR\r
-#define NOACCE 0x80\r
-#define PIPOE 0x20\r
-#define NECLK 0x10\r
-#define LSTRE 0x08\r
-#define RDWE 0x04\r
-\r
-// INTCR bitflags\r
-#define IRQE 0x80\r
-#define IRQEN 0x40\r
-#define DLY 0x20\r
-\r
-// BKP Module\r
-#define BKPCT0 PORTIO_8(IO_BASE + 0x28) /* Breakpoint Control 0 */\r
-#define BKPCT1 PORTIO_8(IO_BASE + 0x29) /* Breakpoint Control 1 */\r
-#define BKP0X PORTIO_8(IO_BASE + 0x2a) /* Breakpoint 0 address upper */\r
-#define BKP0 PORTIO_16(IO_BASE + 0x2b) /* Breakpoint 0 address */\r
-#define BKP1X PORTIO_8(IO_BASE + 0x2d) /* Breakpoint 1 address upper */\r
-#define BKP1 PORTIO_16(IO_BASE + 0x2e) /* Breakpoint 1 address */\r
-\r
-// MEBI Module \r
-#define PPAGE PORTIO_8(IO_BASE + 0x30) /* program page register */\r
-#define PORTK PORTIO_8(IO_BASE + 0x32) /* port K data register */\r
-#define DDRK PORTIO_8(IO_BASE + 0x33) /* port K data direction */\r
-\r
-// CRG Module \r
-#define SYNR PORTIO_8(IO_BASE + 0x34) /* synthesizer register */\r
-#define REFDV PORTIO_8(IO_BASE + 0x35) /* reference divider register */\r
-#define CTFLG PORTIO_8(IO_BASE + 0x36) /* clock test flag register */\r
-#define CRGFLG PORTIO_8(IO_BASE + 0x37) /* clock generator flag register */\r
-#define CRGINT PORTIO_8(IO_BASE + 0x38) /* clock interrupt enable */\r
-#define CLKSEL PORTIO_8(IO_BASE + 0x39) /* clock select register */\r
-#define PLLCTL PORTIO_8(IO_BASE + 0x3a) /* PLL control register */\r
-#define RTICTL PORTIO_8(IO_BASE + 0x3b) /* clock real time control reg. */\r
-#define COPCTL PORTIO_8(IO_BASE + 0x3c) /* COP control register */\r
-#define FORBYP PORTIO_8(IO_BASE + 0x3d) /* clock force and bypass register */\r
-#define CTCTL PORTIO_8(IO_BASE + 0x3e) /* clock test control register */\r
-#define ARMCOP PORTIO_8(IO_BASE + 0x3f) /* COP arm/reset register with sequence 0x55,0xaa. */\r
-\r
-// CRG bitflags\r
-#define RTIF 0x80\r
-#define RTIE 0x80\r
-#define LOCK 0x08\r
-#define AUTO 0x20\r
-#define PLLSEL 0x80\r
-\r
-// COPCTL bitflags\r
-#define WCOP 0x80\r
-#define RSBCK 0x40\r
-\r
-// ECT Module\r
-#define TIOS PORTIO_8(IO_BASE + 0x40) /* timer select register */\r
-#define TCFORC PORTIO_8(IO_BASE + 0x41) /* compare force register */\r
-#define TOC7M PORTIO_8(IO_BASE + 0x42) /* oc7 mask register */\r
-#define TOC7D PORTIO_8(IO_BASE + 0x43) /* oc7 data register */\r
-#define TCNT PORTIO_16(IO_BASE + 0x44) /* timer counter */\r
-#define TSCR1 PORTIO_8(IO_BASE + 0x46) /* system control register 1 */\r
-#define TTOV PORTIO_8(IO_BASE + 0x47) /* toggle on overflow register */\r
-#define TCTL1 PORTIO_8(IO_BASE + 0x48) /* control register 1 */\r
-#define TCTL2 PORTIO_8(IO_BASE + 0x49) /* control register 2 */\r
-#define TCTL3 PORTIO_8(IO_BASE + 0x4a) /* control register 3 */\r
-#define TCTL4 PORTIO_8(IO_BASE + 0x4b) /* control register 4 */\r
-#define TIE PORTIO_8(IO_BASE + 0x4c) /* interrupt enable register */\r
-#define TSCR2 PORTIO_8(IO_BASE + 0x4d) /* system control register 2 */\r
-#define TFLG1 PORTIO_8(IO_BASE + 0x4e) /* interrupt flag register 1 */\r
-#define TFLG2 PORTIO_8(IO_BASE + 0x4f) /* interrupt flag register 2 */\r
-#define TC0 PORTIO_16(IO_BASE + 0x50) /* capture/compare register 0 */\r
-#define TC1 PORTIO_16(IO_BASE + 0x52) /* capture/compare register 0 */\r
-#define TC2 PORTIO_16(IO_BASE + 0x54) /* capture/compare register 0 */\r
-#define TC3 PORTIO_16(IO_BASE + 0x56) /* capture/compare register 0 */\r
-#define TC4 PORTIO_16(IO_BASE + 0x58) /* capture/compare register 0 */\r
-#define TC5 PORTIO_16(IO_BASE + 0x5a) /* capture/compare register 0 */\r
-#define TC6 PORTIO_16(IO_BASE + 0x5c) /* capture/compare register 0 */\r
-#define TC7 PORTIO_16(IO_BASE + 0x5e) /* capture/compare register 0 */\r
-#define PACTL PORTIO_8(IO_BASE + 0x60) /* pulse accumulator A control */\r
-#define PAFLG PORTIO_8(IO_BASE + 0x61) /* pulse accumulator A flag */\r
-#define PACN3 PORTIO_8(IO_BASE + 0x62) /* pulse accumulator A3 count */\r
-#define PACN2 PORTIO_8(IO_BASE + 0x63) /* pulse accumulator A2 count */\r
-#define PACN1 PORTIO_8(IO_BASE + 0x64) /* pulse accumulator A1 count */\r
-#define PACN0 PORTIO_8(IO_BASE + 0x65) /* pulse accumulator A0 count */\r
-#define MCCTL PORTIO_8(IO_BASE + 0x66) /* modulus counter control reg */\r
-#define MCFLG PORTIO_8(IO_BASE + 0x67) /* modulus counter flag reg */\r
-#define ICPAR PORTIO_8(IO_BASE + 0x68) /* input control pulse acc reg */\r
-#define DLYCT PORTIO_8(IO_BASE + 0x69) /* delay counter control reg */\r
-#define ICOVW PORTIO_8(IO_BASE + 0x6a) /* input control overwrite reg */\r
-#define ICSYS PORTIO_8(IO_BASE + 0x6b) /* input control system reg */\r
-#define TIMTST PORTIO_8(IO_BASE + 0x6d) /* timer test register */\r
-#define PBCTL PORTIO_8(IO_BASE + 0x70) /* pulse accumulator B control */\r
-#define PBFLG PORTIO_8(IO_BASE + 0x71) /* pulse accumulator B flag */\r
-#define PA3H PORTIO_8(IO_BASE + 0x72) /* pulse accumulator B3 count */\r
-#define PA2H PORTIO_8(IO_BASE + 0x73) /* pulse accumulator B2 count */\r
-#define PA1H PORTIO_8(IO_BASE + 0x74) /* pulse accumulator B1 count */\r
-#define PA0H PORTIO_8(IO_BASE + 0x75) /* pulse accumulator B0 count */\r
-#define MCCNT PORTIO_16(IO_BASE + 0x76) /* modulus counter count reg */\r
-#define TC0H PORTIO_16(IO_BASE + 0x78) /* timer input capture hold 0 */\r
-#define TC1H PORTIO_16(IO_BASE + 0x7a) /* timer input capture hold 1 */\r
-#define TC2H PORTIO_16(IO_BASE + 0x7c) /* timer input capture hold 2 */\r
-#define TC3H PORTIO_16(IO_BASE + 0x7e) /* timer input capture hold 3 */\r
-\r
-#define TEN 0x80\r
-#define TSFRZ 0x20\r
-#define TOI 0x80\r
-#define MCZI 0x80\r
-#define MODMC 0x40\r
-#define MCEN 0x4\r
-#define MCPR1 0x2\r
-#define MCPR0 0x1\r
-\r
-#define MCPRE_VAL_1 0\r
-#define MCPRE_VAL_4 MCPR0\r
-#define MCPRE_VAL_8 MCPR1\r
-#define MCPRE_VAL_16 MCPR0 | MCPR1\r
-\r
-// ATD0 Module \r
-#define ATD0_BASE (IO_BASE + 0x80)\r
-#define ATD0CTL0 PORTIO_8(IO_BASE + 0x80) /* A/D0 control register 0 */\r
-#define ATD0CTL1 PORTIO_8(IO_BASE + 0x81) /* A/D0 control register 1 */\r
-#define ATD0CTL2 PORTIO_8(IO_BASE + 0x82) /* A/D0 control register 2 */\r
-#define ATD0CTL3 PORTIO_8(IO_BASE + 0x83) /* A/D0 control register 3 */\r
-#define ATD0CTL4 PORTIO_8(IO_BASE + 0x84) /* A/D0 control register 4 */\r
-#define ATD0CTL5 PORTIO_8(IO_BASE + 0x85) /* A/D0 control register 5 */\r
-#define ATD0STAT0 PORTIO_8(IO_BASE + 0x86) /* A/D0 status register 0 */\r
-#define ATD0STAT1 PORTIO_8(IO_BASE + 0x87) /* A/D0 status register 1 */\r
-#define ATD0TEST0 PORTIO_8(IO_BASE + 0x88) /* A/D0 test register 0 */\r
-#define ATD0TEST1 PORTIO_8(IO_BASE + 0x89) /* A/D0 test register 1 */\r
-#define ATD0DIEN PORTIO_8(IO_BASE + 0x8d) /* A/D0 interrupt enable */\r
-#define PORTAD0 PORTIO_8(IO_BASE + 0x8f) /* port AD0 data input register */\r
-#define ATD0DR0 PORTIO_16(IO_BASE + 0x90) /* A/D0 result 0 */\r
-#define ATD0DR0H PORTIO_8(IO_BASE + 0x90) /* A/D0 result 0 */\r
-#define ATD0DR1 PORTIO_16(IO_BASE + 0x92) /* A/D0 result 1 */\r
-#define ATD0DR1H PORTIO_8(IO_BASE + 0x92) /* A/D0 result 1 */\r
-#define ATD0DR2 PORTIO_16(IO_BASE + 0x94) /* A/D0 result 2 */\r
-#define ATD0DR2H PORTIO_8(IO_BASE + 0x94) /* A/D0 result 2 */\r
-#define ATD0DR3 PORTIO_16(IO_BASE + 0x96) /* A/D0 result 3 */\r
-#define ATD0DR3H PORTIO_8(IO_BASE + 0x96) /* A/D0 result 3 */\r
-#define ATD0DR4 PORTIO_16(IO_BASE + 0x98) /* A/D0 result 4 */\r
-#define ATD0DR4H PORTIO_8(IO_BASE + 0x98) /* A/D0 result 4 */\r
-#define ATD0DR5 PORTIO_16(IO_BASE + 0x9a) /* A/D0 result 5 */\r
-#define ATD0DR5H PORTIO_8(IO_BASE + 0x9a) /* A/D0 result 5 */\r
-#define ATD0DR6 PORTIO_16(IO_BASE + 0x9c) /* A/D0 result 6 */\r
-#define ATD0DR6H PORTIO_8(IO_BASE + 0x9c) /* A/D0 result 6 */\r
-#define ATD0DR7 PORTIO_16(IO_BASE + 0x9e) /* A/D0 result 7 */\r
-#define ATD0DR7H PORTIO_8(IO_BASE + 0x9e) /* A/D0 result 7 */\r
-\r
-// ATDnCTL5 bitflags\r
-#define DJM 0x80\r
-#define DSGN 0x40\r
-#define SCAN 0x20\r
-#define MULT 0x10\r
-\r
-// ATDnSTAT0 bitflags\r
-#define SCF 0x80\r
-#define ETORF 0x20\r
-#define FIFOR 0x10\r
-\r
-// PWM Module \r
-#define PWME PORTIO_8(IO_BASE + 0xa0) /* PWM Enable */\r
-#define PWMPOL PORTIO_8(IO_BASE + 0xa1) /* PWM Clock Polarity */\r
-#define PWMCLK PORTIO_8(IO_BASE + 0xa2) /* PWM Clocks */\r
-#define PWMPRCLK PORTIO_8(IO_BASE + 0xa3) /* PWM prescale clock select */\r
-#define PWMCAE PORTIO_8(IO_BASE + 0xa4) /* PWM center align enable */\r
-#define PWMCTL PORTIO_8(IO_BASE + 0xa5) /* PWM Control Register */\r
-#define PWMTST PORTIO_8(IO_BASE + 0xa6) /* PWM Test Register */\r
-#define PWMPRSC PORTIO_8(IO_BASE + 0xa7) /* PWM Test Register */\r
-#define PWMSCLA PORTIO_8(IO_BASE + 0xa8) /* PWM scale A */\r
-#define PWMSCLB PORTIO_8(IO_BASE + 0xa9) /* PWM scale B */\r
-#define PWMSCNTA PORTIO_8(IO_BASE + 0xaa) /* PWM Test Register A */\r
-#define PWMSCNTB PORTIO_8(IO_BASE + 0xab) /* PWM Test Register B */\r
-#define PWMCNT0 PORTIO_8(IO_BASE + 0xac) /* PWM Channel Counter 0 */\r
-#define PWMCNT1 PORTIO_8(IO_BASE + 0xad) /* PWM Channel Counter 1 */\r
-#define PWMCNT2 PORTIO_8(IO_BASE + 0xae) /* PWM Channel Counter 2 */\r
-#define PWMCNT3 PORTIO_8(IO_BASE + 0xaf) /* PWM Channel Counter 3 */\r
-#define PWMCNT4 PORTIO_8(IO_BASE + 0xb0) /* PWM Channel Counter 4 */\r
-#define PWMCNT5 PORTIO_8(IO_BASE + 0xb1) /* PWM Channel Counter 5 */\r
-#define PWMCNT6 PORTIO_8(IO_BASE + 0xb2) /* PWM Channel Counter 6 */\r
-#define PWMCNT7 PORTIO_8(IO_BASE + 0xb3) /* PWM Channel Counter 7 */\r
-#define PWMPER0 PORTIO_8(IO_BASE + 0xb4) /* PWM Channel Period 0 */\r
-#define PWMPER1 PORTIO_8(IO_BASE + 0xb5) /* PWM Channel Period 1 */\r
-#define PWMPER2 PORTIO_8(IO_BASE + 0xb6) /* PWM Channel Period 2 */\r
-#define PWMPER3 PORTIO_8(IO_BASE + 0xb7) /* PWM Channel Period 3 */\r
-#define PWMPER4 PORTIO_8(IO_BASE + 0xb8) /* PWM Channel Period 4 */\r
-#define PWMPER5 PORTIO_8(IO_BASE + 0xb9) /* PWM Channel Period 5 */\r
-#define PWMPER6 PORTIO_8(IO_BASE + 0xba) /* PWM Channel Period 6 */\r
-#define PWMPER7 PORTIO_8(IO_BASE + 0xbb) /* PWM Channel Period 7 */\r
-#define PWMDTY0 PORTIO_8(IO_BASE + 0xbc) /* PWM Channel Duty 0 */\r
-#define PWMDTY1 PORTIO_8(IO_BASE + 0xbd) /* PWM Channel Duty 1 */\r
-#define PWMDTY2 PORTIO_8(IO_BASE + 0xbe) /* PWM Channel Duty 2 */\r
-#define PWMDTY3 PORTIO_8(IO_BASE + 0xbf) /* PWM Channel Duty 3 */\r
-#define PWMDTY4 PORTIO_8(IO_BASE + 0xc0) /* PWM Channel Duty 4 */\r
-#define PWMDTY5 PORTIO_8(IO_BASE + 0xc1) /* PWM Channel Duty 5 */\r
-#define PWMDTY6 PORTIO_8(IO_BASE + 0xc2) /* PWM Channel Duty 6 */\r
-#define PWMDTY7 PORTIO_8(IO_BASE + 0xc3) /* PWM Channel Duty 7 */\r
-#define PWMSDN PORTIO_8(IO_BASE + 0xc4) /* PWM shutdown register */\r
-\r
-#define PWMCNT01_16BIT PORTIO_16(IO_BASE + 0xac) /* pwm channel 0,1 counter, 16bit */\r
-#define PWMCNT23_16BIT PORTIO_16(IO_BASE + 0xae) /* pwm channel 2,3 counter, 16bit */\r
-#define PWMCNT45_16BIT PORTIO_16(IO_BASE + 0xb0) /* pwm channel 4,5 counter, 16bit */\r
-#define PWMCNT67_16BIT PORTIO_16(IO_BASE + 0xb2) /* pwm channel 6,7 counter, 16bit */\r
-#define PWMPER01_16BIT PORTIO_16(IO_BASE + 0xb4) /* pwm channel 0,1 period, 16bit */\r
-#define PWMPER23_16BIT PORTIO_16(IO_BASE + 0xb6) /* pwm channel 2,3 period, 16bit */\r
-#define PWMPER45_16BIT PORTIO_16(IO_BASE + 0xb8) /* pwm channel 4,5 period, 16bit */\r
-#define PWMPER67_16BIT PORTIO_16(IO_BASE + 0xba) /* pwm channel 6,7 period, 16bit */\r
-#define PWMDTY01_16BIT PORTIO_16(IO_BASE + 0xbc) /* pwm channel 0,1 duty cycle, 16bit */\r
-#define PWMDTY23_16BIT PORTIO_16(IO_BASE + 0xbe) /* pwm channel 2,3 duty cycle, 16bit */\r
-#define PWMDTY45_16BIT PORTIO_16(IO_BASE + 0xc0) /* pwm channel 4,5 duty cycle, 16bit */\r
-#define PWMDTY67_16BIT PORTIO_16(IO_BASE + 0xc2) /* pwm channel 6,7 duty cycle, 16bit */\r
-\r
-\r
-\r
-// SCI register offsets\r
-#define _SCIBD 0x0 /* SCI baud rate high */\r
-#define _SCIBDH 0x0 /* SCI baud rate high */\r
-#define _SCIBDL 0x1 /* SCI baud rate low */\r
-#define _SCICR1 0x2 /* SCI control register 1 */\r
-#define _SCICR2 0x3 /* SCI control register 2 */\r
-#define _SCISR1 0x4 /* SCI status register 1 */\r
-#define _SCISR2 0x5 /* SCI status register 2 */\r
-#define _SCIDRH 0x6 /* SCI data register high */\r
-#define _SCIDRL 0x7 /* SCI data register low */\r
-\r
-// SCI0 Module\r
-#define SCI0_BASE (IO_BASE + 0xc8)\r
-#define SCI0BD PORTIO_16(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
-#define SCI0BDH PORTIO_8(IO_BASE + 0xc8) /* SCI 0 baud rate high */\r
-#define SCI0BDL PORTIO_8(IO_BASE + 0xc9) /* SCI 0 baud rate low */\r
-#define SCI0CR1 PORTIO_8(IO_BASE + 0xca) /* SCI 0 control register 1 */\r
-#define SCI0CR2 PORTIO_8(IO_BASE + 0xcb) /* SCI 0 control register 2 */\r
-#define SCI0SR1 PORTIO_8(IO_BASE + 0xcc) /* SCI 0 status register 1 */\r
-#define SCI0SR2 PORTIO_8(IO_BASE + 0xcd) /* SCI 0 status register 2 */\r
-#define SCI0DRH PORTIO_8(IO_BASE + 0xce) /* SCI 0 data register high */\r
-#define SCI0DRL PORTIO_8(IO_BASE + 0xcf) /* SCI 0 data register low */\r
-\r
-// SCI1 Module \r
-#define SCI1_BASE (IO_BASE + 0xd0)\r
-#define SCI1BD PORTIO_16(IO_BASE + 0xd0) /* SCI 1 16bit baud rate */\r
-#define SCI1BDH PORTIO_8(IO_BASE + 0xd0) /* SCI 1 baud rate high */\r
-#define SCI1BDL PORTIO_8(IO_BASE + 0xd1) /* SCI 1 baud rate low */\r
-#define SCI1CR1 PORTIO_8(IO_BASE + 0xd2) /* SCI 1 control register 1 */\r
-#define SCI1CR2 PORTIO_8(IO_BASE + 0xd3) /* SCI 1 control register 2 */\r
-#define SCI1SR1 PORTIO_8(IO_BASE + 0xd4) /* SCI 1 status register 1 */\r
-#define SCI1SR2 PORTIO_8(IO_BASE + 0xd5) /* SCI 1 status register 2 */\r
-#define SCI1DRH PORTIO_8(IO_BASE + 0xd6) /* SCI 1 data register high */\r
-#define SCI1DRL PORTIO_8(IO_BASE + 0xd7) /* SCI 1 data register low */\r
-\r
-// SCInSR1\r
-#define TDRE 0x80\r
-#define RDRF 0x20\r
-#define IDLE 0x10\r
-\r
-// SPI register offsets\r
-#define _SPICR1 PORTIO_8(IO_BASE + 0x0) /* SPI control register 1 */\r
-#define _SPICR2 PORTIO_8(IO_BASE + 0x1) /* SPI control register 2 */\r
-#define _SPIBR PORTIO_8(IO_BASE + 0x2) /* SPI baud rate register */\r
-#define _SPISR PORTIO_8(IO_BASE + 0x3) /* SPI status register */\r
-#define _SPIDR PORTIO_8(IO_BASE + 0x5) /* SPI data register */\r
-\r
-// SPI0 Module \r
-#define SPI0_BASE (IO_BASE + 0xd8)\r
-#define SPI0CR1 PORTIO_8(IO_BASE + 0xd8) /* SPI 0 control register 1 */\r
-#define SPI0CR2 PORTIO_8(IO_BASE + 0xd9) /* SPI 0 control register 2 */\r
-#define SPI0BR PORTIO_8(IO_BASE + 0xda) /* SPI 0 baud rate register */\r
-#define SPI0SR PORTIO_8(IO_BASE + 0xdb) /* SPI 0 status register */\r
-#define SPI0DR PORTIO_8(IO_BASE + 0xdd) /* SPI 0 data register */\r
-\r
-// SPInCR1\r
-#define SPIE 0x80\r
-#define SPE 0x40\r
-#define SPTIE 0x20\r
-#define MSTR 0x10\r
-#define CPOL 0x08\r
-#define CPHA 0x04\r
-#define SSOE 0x02\r
-#define LSBFE 0x01\r
-\r
-// SPInSR\r
-#define SPIF 0x80\r
-#define SPTEF 0x20\r
-#define MODF 0x10\r
-\r
-// I2C Module \r
-#define IBAD PORTIO_8(IO_BASE + 0xe0) /* I2C address register */\r
-#define IBFD PORTIO_8(IO_BASE + 0xe1) /* I2C freqency divider reg */\r
-#define IBCR PORTIO_8(IO_BASE + 0xe2) /* I2C control register */\r
-#define IBSR PORTIO_8(IO_BASE + 0xe3) /* I2C status register */\r
-#define IBDR PORTIO_8(IO_BASE + 0xe4) /* I2C data register */\r
-\r
-// IBSR\r
-#define TCF 0x80\r
-#define IAAS 0x40\r
-#define IBB 0x20\r
-#define IBAL 0x10\r
-#define SRW 0x04\r
-#define IBIF 0x02\r
-#define RXAK 0x01\r
-\r
-// BDLC Module\r
-#define DLCBCR1 PORTIO_8(IO_BASE + 0xe8) /* BDLC control register 1 */\r
-#define DLCBSVR PORTIO_8(IO_BASE + 0xe9) /* BDLC state vector register */\r
-#define DLCBCR2 PORTIO_8(IO_BASE + 0xea) /* BDLC control register 2 */\r
-#define DLCBDR PORTIO_8(IO_BASE + 0xeb) /* BDLC data register */\r
-#define DLCBARD PORTIO_8(IO_BASE + 0xec) /* BDLC analog round trip delay */\r
-#define DLCBRSR PORTIO_8(IO_BASE + 0xed) /* BDLC rate select register */\r
-#define DLCSCR PORTIO_8(IO_BASE + 0xee) /* BDLC control register */\r
-#define DLCBSTAT PORTIO_8(IO_BASE + 0xef) /* BDLC status register */\r
-\r
-// SPI1 Module\r
-#define SPI1_BASE (IO_BASE + 0xf0)\r
-#define SPI1CR1 PORTIO_8(IO_BASE + 0xf0) /* SPI 1 control register 1 */\r
-#define SPI1CR2 PORTIO_8(IO_BASE + 0xf1) /* SPI 1 control register 2 */\r
-#define SPI1BR PORTIO_8(IO_BASE + 0xf2) /* SPI 1 baud rate register */\r
-#define SPI1SR PORTIO_8(IO_BASE + 0xf3) /* SPI 1 status register */\r
-#define SPI1DR PORTIO_8(IO_BASE + 0xf5) /* SPI 1 data register */\r
-\r
-// SPI2 Module\r
-#define SPI2_BASE (IO_BASE + 0xf8)\r
-#define SPI2CR1 PORTIO_8(IO_BASE + 0xf8) /* SPI 2 control register 1 */\r
-#define SPI2CR2 PORTIO_8(IO_BASE + 0xf9) /* SPI 2 control register 2 */\r
-#define SPI2BR PORTIO_8(IO_BASE + 0xfa) /* SPI 2 baud rate register */\r
-#define SPI2SR PORTIO_8(IO_BASE + 0xfb) /* SPI 2 status register */\r
-#define SPI2DR PORTIO_8(IO_BASE + 0xfd) /* SPI 2 data register */\r
-\r
-// FLC Module\r
-#define FCLKDIV PORTIO_8(IO_BASE + 0x100) /* flash clock divider */\r
-#define FSEC PORTIO_8(IO_BASE + 0x101) /* flash security register */\r
-#define FCNFG PORTIO_8(IO_BASE + 0x103) /* flash configuration register */\r
-#define FPROT PORTIO_8(IO_BASE + 0x104) /* flash protection register */\r
-#define FSTAT PORTIO_8(IO_BASE + 0x105) /* flash status register */\r
-#define FCMD PORTIO_8(IO_BASE + 0x106) /* flash command register */\r
-\r
-// EEPROM Module\r
-#define ECLKDIV PORTIO_8(IO_BASE + 0x110) /* eeprom clock divider */\r
-#define ECNFG PORTIO_8(IO_BASE + 0x113) /* eeprom configuration register */\r
-#define EPROT PORTIO_8(IO_BASE + 0x114) /* eeprom protection register */\r
-#define ESTAT PORTIO_8(IO_BASE + 0x115) /* eeprom status register */\r
-#define ECMD PORTIO_8(IO_BASE + 0x116) /* eeprom command register */\r
-\r
-// ATD1 Module \r
-#define ATD1_BASE (IO_BASE + 0x120)\r
-#define ATD1CTL0 PORTIO_8(IO_BASE + 0x120) /* A/D1 control register 0 */\r
-#define ATD1CTL1 PORTIO_8(IO_BASE + 0x121) /* A/D1 control register 1 */\r
-#define ATD1CTL2 PORTIO_8(IO_BASE + 0x122) /* A/D1 control register 2 */\r
-#define ATD1CTL3 PORTIO_8(IO_BASE + 0x123) /* A/D1 control register 3 */\r
-#define ATD1CTL4 PORTIO_8(IO_BASE + 0x124) /* A/D1 control register 4 */\r
-#define ATD1CTL5 PORTIO_8(IO_BASE + 0x125) /* A/D1 control register 5 */\r
-#define ATD1STAT0 PORTIO_8(IO_BASE + 0x126) /* A/D1 status register 0 */\r
-#define ATD1STAT1 PORTIO_8(IO_BASE + 0x127) /* A/D1 status register 1 */\r
-#define ATD1TEST0 PORTIO_8(IO_BASE + 0x128) /* A/D1 test register 0 */\r
-#define ATD1TEST1 PORTIO_8(IO_BASE + 0x129) /* A/D1 test register 1 */\r
-#define ATD1DIEN PORTIO_8(IO_BASE + 0x12d) /* A/D1 interrupt enable */\r
-#define PORTAD1 PORTIO_8(IO_BASE + 0x12f) /* port AD1 data input register */\r
-#define ATD1DR0 PORTIO_16(IO_BASE + 0x130) /* A/D1 result 0 */\r
-#define ATD1DR0H PORTIO_8(IO_BASE + 0x130) /* A/D1 result 0 */\r
-#define ATD1DR1 PORTIO_16(IO_BASE + 0x132) /* A/D1 result 1 */\r
-#define ATD1DR1H PORTIO_8(IO_BASE + 0x132) /* A/D1 result 1 */\r
-#define ATD1DR2 PORTIO_16(IO_BASE + 0x134) /* A/D1 result 2 */\r
-#define ATD1DR2H PORTIO_8(IO_BASE + 0x134) /* A/D1 result 2 */\r
-#define ATD1DR3 PORTIO_16(IO_BASE + 0x136) /* A/D1 result 3 */\r
-#define ATD1DR3H PORTIO_8(IO_BASE + 0x136) /* A/D1 result 3 */\r
-#define ATD1DR4 PORTIO_16(IO_BASE + 0x138) /* A/D1 result 4 */\r
-#define ATD1DR4H PORTIO_8(IO_BASE + 0x138) /* A/D1 result 4 */\r
-#define ATD1DR5 PORTIO_16(IO_BASE + 0x13a) /* A/D1 result 5 */\r
-#define ATD1DR5H PORTIO_8(IO_BASE + 0x13a) /* A/D1 result 5 */\r
-#define ATD1DR6 PORTIO_16(IO_BASE + 0x13c) /* A/D1 result 6 */\r
-#define ATD1DR6H PORTIO_8(IO_BASE + 0x13c) /* A/D1 result 6 */\r
-#define ATD1DR7 PORTIO_16(IO_BASE + 0x13e) /* A/D1 result 7 */\r
-#define ATD1DR7H PORTIO_8(IO_BASE + 0x13e) /* A/D1 result 7 */\r
-\r
-// CAN0 Module \r
-#define CAN0_BASE (IO_BASE + 0x140)\r
-#define CAN0CTL0 PORTIO_8(IO_BASE + 0x140) /* CAN0 control register 0 */\r
-#define CAN0CTL1 PORTIO_8(IO_BASE + 0x141) /* CAN0 control register 1 */\r
-#define CAN0BTR0 PORTIO_8(IO_BASE + 0x142) /* CAN0 bus timing register 0 */\r
-#define CAN0BTR1 PORTIO_8(IO_BASE + 0x143) /* CAN0 bus timing register 1 */\r
-#define CAN0RFLG PORTIO_8(IO_BASE + 0x144) /* CAN0 receiver flag register */\r
-#define CAN0RIER PORTIO_8(IO_BASE + 0x145) /* CAN0 receiver interrupt reg */\r
-#define CAN0TFLG PORTIO_8(IO_BASE + 0x146) /* CAN0 transmitter flag reg */\r
-#define CAN0TIER PORTIO_8(IO_BASE + 0x147) /* CAN0 transmitter control reg */\r
-#define CAN0TARQ PORTIO_8(IO_BASE + 0x148) /* CAN0 transmitter abort request */\r
-#define CAN0TAAK PORTIO_8(IO_BASE + 0x149) /* CAN0 transmitter abort acknowledge */\r
-#define CAN0TBSEL PORTIO_8(IO_BASE + 0x14a) /* CAN0 transmit buffer selection */\r
-#define CAN0IDAC PORTIO_8(IO_BASE + 0x14b) /* CAN0 identifier acceptance */\r
-#define CAN0RXERR PORTIO_8(IO_BASE + 0x14e) /* CAN0 receive error counter */\r
-#define CAN0TXERR PORTIO_8(IO_BASE + 0x14f) /* CAN0 transmit error counter */\r
-#define CAN0IDAR0 PORTIO_8(IO_BASE + 0x150) /* CAN0 id acceptance reg 0 */\r
-#define CAN0IDAR1 PORTIO_8(IO_BASE + 0x151) /* CAN0 id acceptance reg 1 */\r
-#define CAN0IDAR2 PORTIO_8(IO_BASE + 0x152) /* CAN0 id acceptance reg 2 */\r
-#define CAN0IDAR3 PORTIO_8(IO_BASE + 0x153) /* CAN0 id acceptance reg 3 */\r
-#define CAN0IDMR0 PORTIO_8(IO_BASE + 0x154) /* CAN0 id mask register 0 */\r
-#define CAN0IDMR1 PORTIO_8(IO_BASE + 0x155) /* CAN0 id mask register 1 */\r
-#define CAN0IDMR2 PORTIO_8(IO_BASE + 0x156) /* CAN0 id mask register 2 */\r
-#define CAN0IDMR3 PORTIO_8(IO_BASE + 0x157) /* CAN0 id mask register 3 */\r
-#define CAN0IDAR4 PORTIO_8(IO_BASE + 0x158) /* CAN0 id acceptance reg 4 */\r
-#define CAN0IDAR5 PORTIO_8(IO_BASE + 0x159) /* CAN0 id acceptance reg 5 */\r
-#define CAN0IDAR6 PORTIO_8(IO_BASE + 0x15a) /* CAN0 id acceptance reg 6 */\r
-#define CAN0IDAR7 PORTIO_8(IO_BASE + 0x15b) /* CAN0 id acceptance reg 7 */\r
-#define CAN0IDMR4 PORTIO_8(IO_BASE + 0x15c) /* CAN0 id mask register 4 */\r
-#define CAN0IDMR5 PORTIO_8(IO_BASE + 0x15d) /* CAN0 id mask register 5 */\r
-#define CAN0IDMR6 PORTIO_8(IO_BASE + 0x15e) /* CAN0 id mask register 6 */\r
-#define CAN0IDMR7 PORTIO_8(IO_BASE + 0x15f) /* CAN0 id mask register 7 */\r
-#define CAN0RXFG PORTIO_8(IO_BASE + 0x160) /* CAN0 receive buffer */\r
-#define CAN0TXFG PORTIO_8(IO_BASE + 0x170) /* CAN0 transmit buffer */\r
-\r
-// CAN1 Module \r
-#define CAN1_BASE (IO_BASE + 0x180)\r
-#define CAN1CTL0 PORTIO_8(IO_BASE + 0x180) /* CAN1 control register 0 */\r
-#define CAN1CTL1 PORTIO_8(IO_BASE + 0x181) /* CAN1 control register 1 */\r
-#define CAN1BTR0 PORTIO_8(IO_BASE + 0x182) /* CAN1 bus timing register 0 */\r
-#define CAN1BTR1 PORTIO_8(IO_BASE + 0x183) /* CAN1 bus timing register 1 */\r
-#define CAN1RFLG PORTIO_8(IO_BASE + 0x184) /* CAN1 receiver flag register */\r
-#define CAN1RIER PORTIO_8(IO_BASE + 0x185) /* CAN1 receiver interrupt reg */\r
-#define CAN1TFLG PORTIO_8(IO_BASE + 0x186) /* CAN1 transmitter flag reg */\r
-#define CAN1TIER PORTIO_8(IO_BASE + 0x187) /* CAN1 transmitter control reg */\r
-#define CAN1TARQ PORTIO_8(IO_BASE + 0x188) /* CAN1 transmitter abort request */\r
-#define CAN1TAAK PORTIO_8(IO_BASE + 0x189) /* CAN1 transmitter abort acknowledge */\r
-#define CAN1TBSEL PORTIO_8(IO_BASE + 0x18a) /* CAN1 transmit buffer selection */\r
-#define CAN1IDAC PORTIO_8(IO_BASE + 0x18b) /* CAN1 identifier acceptance */\r
-#define CAN1RXERR PORTIO_8(IO_BASE + 0x18e) /* CAN1 transmitter control reg */\r
-#define CAN1TXERR PORTIO_8(IO_BASE + 0x18f) /* CAN1 transmit error counter */\r
-#define CAN1IDAR0 PORTIO_8(IO_BASE + 0x190) /* CAN1 id acceptance reg 0 */\r
-#define CAN1IDAR1 PORTIO_8(IO_BASE + 0x191) /* CAN1 id acceptance reg 1 */\r
-#define CAN1IDAR2 PORTIO_8(IO_BASE + 0x192) /* CAN1 id acceptance reg 2 */\r
-#define CAN1IDAR3 PORTIO_8(IO_BASE + 0x193) /* CAN1 id acceptance reg 3 */\r
-#define CAN1IDMR0 PORTIO_8(IO_BASE + 0x194) /* CAN1 id mask register 0 */\r
-#define CAN1IDMR1 PORTIO_8(IO_BASE + 0x195) /* CAN1 id mask register 1 */\r
-#define CAN1IDMR2 PORTIO_8(IO_BASE + 0x196) /* CAN1 id mask register 2 */\r
-#define CAN1IDMR3 PORTIO_8(IO_BASE + 0x197) /* CAN1 id mask register 3 */\r
-#define CAN1IDAR4 PORTIO_8(IO_BASE + 0x198) /* CAN1 id acceptance reg 4 */\r
-#define CAN1IDAR5 PORTIO_8(IO_BASE + 0x199) /* CAN1 id acceptance reg 5 */\r
-#define CAN1IDAR6 PORTIO_8(IO_BASE + 0x19a) /* CAN1 id acceptance reg 6 */\r
-#define CAN1IDAR7 PORTIO_8(IO_BASE + 0x19b) /* CAN1 id acceptance reg 7 */\r
-#define CAN1IDMR4 PORTIO_8(IO_BASE + 0x19c) /* CAN1 id mask register 4 */\r
-#define CAN1IDMR5 PORTIO_8(IO_BASE + 0x19d) /* CAN1 id mask register 5 */\r
-#define CAN1IDMR6 PORTIO_8(IO_BASE + 0x19e) /* CAN1 id mask register 6 */\r
-#define CAN1IDMR7 PORTIO_8(IO_BASE + 0x19f) /* CAN1 id mask register 7 */\r
-#define CAN1RXFG PORTIO_8(IO_BASE + 0x1a0) /* CAN1 receive buffer */\r
-#define CAN1TXFG PORTIO_8(IO_BASE + 0x1b0) /* CAN1 transmit buffer */\r
-\r
-// CAN2 Module \r
-#define CAN2_BASE (IO_BASE + 0x1c0)\r
-#define CAN2CTL0 PORTIO_8(IO_BASE + 0x1c0) /* CAN2 control register 0 */\r
-#define CAN2CTL1 PORTIO_8(IO_BASE + 0x1c1) /* CAN2 control register 1 */\r
-#define CAN2BTR0 PORTIO_8(IO_BASE + 0x1c2) /* CAN2 bus timing register 0 */\r
-#define CAN2BTR1 PORTIO_8(IO_BASE + 0x1c3) /* CAN2 bus timing register 1 */\r
-#define CAN2RFLG PORTIO_8(IO_BASE + 0x1c4) /* CAN2 receiver flag register */\r
-#define CAN2RIER PORTIO_8(IO_BASE + 0x1c5) /* CAN2 receiver interrupt reg */\r
-#define CAN2TFLG PORTIO_8(IO_BASE + 0x1c6) /* CAN2 transmitter flag reg */\r
-#define CAN2TIER PORTIO_8(IO_BASE + 0x1c7) /* CAN2 transmitter control reg */\r
-#define CAN2TARQ PORTIO_8(IO_BASE + 0x1c8) /* CAN2 transmitter abort request */\r
-#define CAN2TAAK PORTIO_8(IO_BASE + 0x1c9) /* CAN2 transmitter abort acknowledge */\r
-#define CAN2TBSEL PORTIO_8(IO_BASE + 0x1ca) /* CAN2 transmit buffer selection */\r
-#define CAN2IDAC PORTIO_8(IO_BASE + 0x1cb) /* CAN2 identifier acceptance */\r
-#define CAN2RXERR PORTIO_8(IO_BASE + 0x1ce) /* CAN2 transmitter control reg */\r
-#define CAN2TXERR PORTIO_8(IO_BASE + 0x1cf) /* CAN2 transmit error counter */\r
-#define CAN2IDAR0 PORTIO_8(IO_BASE + 0x1d0) /* CAN2 id acceptance reg 0 */\r
-#define CAN2IDAR1 PORTIO_8(IO_BASE + 0x1d1) /* CAN2 id acceptance reg 1 */\r
-#define CAN2IDAR2 PORTIO_8(IO_BASE + 0x1d2) /* CAN2 id acceptance reg 2 */\r
-#define CAN2IDAR3 PORTIO_8(IO_BASE + 0x1d3) /* CAN2 id acceptance reg 3 */\r
-#define CAN2IDMR0 PORTIO_8(IO_BASE + 0x1d4) /* CAN2 id mask register 0 */\r
-#define CAN2IDMR1 PORTIO_8(IO_BASE + 0x1d5) /* CAN2 id mask register 1 */\r
-#define CAN2IDMR2 PORTIO_8(IO_BASE + 0x1d6) /* CAN2 id mask register 2 */\r
-#define CAN2IDMR3 PORTIO_8(IO_BASE + 0x1d7) /* CAN2 id mask register 3 */\r
-#define CAN2IDAR4 PORTIO_8(IO_BASE + 0x1d8) /* CAN2 id acceptance reg 4 */\r
-#define CAN2IDAR5 PORTIO_8(IO_BASE + 0x1d9) /* CAN2 id acceptance reg 5 */\r
-#define CAN2IDAR6 PORTIO_8(IO_BASE + 0x1da) /* CAN2 id acceptance reg 6 */\r
-#define CAN2IDAR7 PORTIO_8(IO_BASE + 0x1db) /* CAN2 id acceptance reg 7 */\r
-#define CAN2IDMR4 PORTIO_8(IO_BASE + 0x1dc) /* CAN2 id mask register 4 */\r
-#define CAN2IDMR5 PORTIO_8(IO_BASE + 0x1dd) /* CAN2 id mask register 5 */\r
-#define CAN2IDMR6 PORTIO_8(IO_BASE + 0x1de) /* CAN2 id mask register 6 */\r
-#define CAN2IDMR7 PORTIO_8(IO_BASE + 0x1df) /* CAN2 id mask register 7 */\r
-#define CAN2RXFG PORTIO_8(IO_BASE + 0x1e0) /* CAN2 receive buffer */\r
-#define CAN2TXFG PORTIO_8(IO_BASE + 0x1f0) /* CAN2 transmit buffer */\r
-\r
-// CAN3 Module \r
-#define CAN3_BASE (IO_BASE + 0x200)\r
-#define CAN3CTL0 PORTIO_8(IO_BASE + 0x200) /* CAN3 control register 0 */\r
-#define CAN3CTL1 PORTIO_8(IO_BASE + 0x201) /* CAN3 control register 1 */\r
-#define CAN3BTR0 PORTIO_8(IO_BASE + 0x202) /* CAN3 bus timing register 0 */\r
-#define CAN3BTR1 PORTIO_8(IO_BASE + 0x203) /* CAN3 bus timing register 1 */\r
-#define CAN3RFLG PORTIO_8(IO_BASE + 0x204) /* CAN3 receiver flag register */\r
-#define CAN3RIER PORTIO_8(IO_BASE + 0x205) /* CAN3 receiver interrupt reg */\r
-#define CAN3TFLG PORTIO_8(IO_BASE + 0x206) /* CAN3 transmitter flag reg */\r
-#define CAN3TIER PORTIO_8(IO_BASE + 0x207) /* CAN3 transmitter control reg */\r
-#define CAN3TARQ PORTIO_8(IO_BASE + 0x208) /* CAN3 transmitter abort request */\r
-#define CAN3TAAK PORTIO_8(IO_BASE + 0x209) /* CAN3 transmitter abort acknowledge */\r
-#define CAN3TBSEL PORTIO_8(IO_BASE + 0x20a) /* CAN3 transmit buffer selection */\r
-#define CAN3IDAC PORTIO_8(IO_BASE + 0x20b) /* CAN3 identifier acceptance */\r
-#define CAN3RXERR PORTIO_8(IO_BASE + 0x20e) /* CAN3 transmitter control reg */\r
-#define CAN3TXERR PORTIO_8(IO_BASE + 0x20f) /* CAN3 transmit error counter */\r
-#define CAN3IDAR0 PORTIO_8(IO_BASE + 0x210) /* CAN3 id acceptance reg 0 */\r
-#define CAN3IDAR1 PORTIO_8(IO_BASE + 0x211) /* CAN3 id acceptance reg 1 */\r
-#define CAN3IDAR2 PORTIO_8(IO_BASE + 0x212) /* CAN3 id acceptance reg 2 */\r
-#define CAN3IDAR3 PORTIO_8(IO_BASE + 0x213) /* CAN3 id acceptance reg 3 */\r
-#define CAN3IDMR0 PORTIO_8(IO_BASE + 0x214) /* CAN3 id mask register 0 */\r
-#define CAN3IDMR1 PORTIO_8(IO_BASE + 0x215) /* CAN3 id mask register 1 */\r
-#define CAN3IDMR2 PORTIO_8(IO_BASE + 0x216) /* CAN3 id mask register 2 */\r
-#define CAN3IDMR3 PORTIO_8(IO_BASE + 0x217) /* CAN3 id mask register 3 */\r
-#define CAN3IDAR4 PORTIO_8(IO_BASE + 0x218) /* CAN3 id acceptance reg 4 */\r
-#define CAN3IDAR5 PORTIO_8(IO_BASE + 0x219) /* CAN3 id acceptance reg 5 */\r
-#define CAN3IDAR6 PORTIO_8(IO_BASE + 0x21a) /* CAN3 id acceptance reg 6 */\r
-#define CAN3IDAR7 PORTIO_8(IO_BASE + 0x21b) /* CAN3 id acceptance reg 7 */\r
-#define CAN3IDMR4 PORTIO_8(IO_BASE + 0x21c) /* CAN3 id mask register 4 */\r
-#define CAN3IDMR5 PORTIO_8(IO_BASE + 0x21d) /* CAN3 id mask register 5 */\r
-#define CAN3IDMR6 PORTIO_8(IO_BASE + 0x21e) /* CAN3 id mask register 6 */\r
-#define CAN3IDMR7 PORTIO_8(IO_BASE + 0x21f) /* CAN3 id mask register 7 */\r
-#define CAN3RXFG PORTIO_8(IO_BASE + 0x220) /* CAN3 receive buffer */\r
-#define CAN3TXFG PORTIO_8(IO_BASE + 0x230) /* CAN3 transmit buffer */\r
-\r
-\r
-// Port T register offsets\r
-#define PTT PORTIO_8(IO_BASE + 0x240) /* port T data register */\r
-#define PTIT PORTIO_8(IO_BASE + 0x241) /* port T input register */\r
-#define DDRT PORTIO_8(IO_BASE + 0x242) /* port T data direction */\r
-#define RDRT PORTIO_8(IO_BASE + 0x243) /* port T reduce drive */\r
-#define PERT PORTIO_8(IO_BASE + 0x244) /* port T pull enable */\r
-#define PPST PORTIO_8(IO_BASE + 0x245) /* port T polarity select */\r
-\r
-// Port S\r
-#define PTS PORTIO_8(IO_BASE + 0x248) /* port S data register */\r
-#define PTIS PORTIO_8(IO_BASE + 0x249) /* port S input register */\r
-#define DDRS PORTIO_8(IO_BASE + 0x24a) /* port S data direction */\r
-#define RDRS PORTIO_8(IO_BASE + 0x24b) /* port S reduce drive */\r
-#define PERS PORTIO_8(IO_BASE + 0x24c) /* port S pull enable */\r
-#define PPSS PORTIO_8(IO_BASE + 0x24d) /* port S polarity select */\r
-#define WOMS PORTIO_8(IO_BASE + 0x24e) /* port S wired-or mode */\r
-\r
-// Port M\r
-#define PTM PORTIO_8(IO_BASE + 0x250) /* port M data register */\r
-#define PTIM PORTIO_8(IO_BASE + 0x251) /* port M input register */\r
-#define DDRM PORTIO_8(IO_BASE + 0x252) /* port M data direction */\r
-#define RDRM PORTIO_8(IO_BASE + 0x253) /* port M reduce drive */\r
-#define PERM PORTIO_8(IO_BASE + 0x254) /* port M pull enable */\r
-#define PPSM PORTIO_8(IO_BASE + 0x255) /* port M polarity select */\r
-#define WOMM PORTIO_8(IO_BASE + 0x256) /* port M wired-or mode */\r
-\r
-// Port P\r
-#define PTP PORTIO_8(IO_BASE + 0x258) /* port P data register */\r
-#define PTIP PORTIO_8(IO_BASE + 0x259) /* port P input register */\r
-#define DDRP PORTIO_8(IO_BASE + 0x25a) /* port P data direction */\r
-#define RDRP PORTIO_8(IO_BASE + 0x25b) /* port P reduce drive */\r
-#define PERP PORTIO_8(IO_BASE + 0x25c) /* port P pull enable */\r
-#define PPSP PORTIO_8(IO_BASE + 0x25d) /* port P polarity select */\r
-#define PIEP PORTIO_8(IO_BASE + 0x25e) /* port P interrupt enable */\r
-#define PIFP PORTIO_8(IO_BASE + 0x25f) /* port P interrupt flag */\r
-\r
-// Port H\r
-#define PTH PORTIO_8(IO_BASE + 0x260) /* port H data register */\r
-#define PTIH PORTIO_8(IO_BASE + 0x261) /* port H input register */\r
-#define DDRH PORTIO_8(IO_BASE + 0x262) /* port H data direction */\r
-#define RDRH PORTIO_8(IO_BASE + 0x263) /* port H reduce drive */\r
-#define PERH PORTIO_8(IO_BASE + 0x264) /* port H pull enable */\r
-#define PPSH PORTIO_8(IO_BASE + 0x265) /* port H polarity select */\r
-#define PIEH PORTIO_8(IO_BASE + 0x266) /* port H interrupt enable */\r
-#define PIFH PORTIO_8(IO_BASE + 0x267) /* port H interrupt flag */\r
-\r
-// Port J\r
-#define PTJ PORTIO_8(IO_BASE + 0x268) /* port J data register */\r
-#define PTIJ PORTIO_8(IO_BASE + 0x269) /* port J input register */\r
-#define DDRJ PORTIO_8(IO_BASE + 0x26a) /* port J data direction */\r
-#define RDRJ PORTIO_8(IO_BASE + 0x26b) /* port J reduce drive */\r
-#define PERJ PORTIO_8(IO_BASE + 0x26c) /* port J pull enable */\r
-#define PPSJ PORTIO_8(IO_BASE + 0x26d) /* port J polarity select */\r
-#define PIEJ PORTIO_8(IO_BASE + 0x26e) /* port J interrupt enable */\r
-#define PIFJ PORTIO_8(IO_BASE + 0x26f) /* port J interrupt flag */\r
-\r
-\r
-\r
-// CAN4 Module \r
-#define CAN4_BASE (IO_BASE + 0x280)\r
-#define CAN4CTL0 PORTIO_8(IO_BASE + 0x280) /* CAN4 control register 0 */\r
-#define CAN4CTL1 PORTIO_8(IO_BASE + 0x281) /* CAN4 control register 1 */\r
-#define CAN4BTR0 PORTIO_8(IO_BASE + 0x282) /* CAN4 bus timing register 0 */\r
-#define CAN4BTR1 PORTIO_8(IO_BASE + 0x283) /* CAN4 bus timing register 1 */\r
-#define CAN4RFLG PORTIO_8(IO_BASE + 0x284) /* CAN4 receiver flag register */\r
-#define CAN4RIER PORTIO_8(IO_BASE + 0x285) /* CAN4 receiver interrupt reg */\r
-#define CAN4TFLG PORTIO_8(IO_BASE + 0x286) /* CAN4 transmitter flag reg */\r
-#define CAN4TIER PORTIO_8(IO_BASE + 0x287) /* CAN4 transmitter control reg */\r
-#define CAN4TARQ PORTIO_8(IO_BASE + 0x288) /* CAN4 transmitter abort request */\r
-#define CAN4TAAK PORTIO_8(IO_BASE + 0x289) /* CAN4 transmitter abort acknowledge */\r
-#define CAN4TBSEL PORTIO_8(IO_BASE + 0x28a) /* CAN4 transmit buffer selection */\r
-#define CAN4IDAC PORTIO_8(IO_BASE + 0x28b) /* CAN4 identifier acceptance */\r
-#define CAN4RXERR PORTIO_8(IO_BASE + 0x28e) /* CAN4 transmitter control reg */\r
-#define CAN4TXERR PORTIO_8(IO_BASE + 0x28f) /* CAN4 transmit error counter */\r
-#define CAN4IDAR0 PORTIO_8(IO_BASE + 0x290) /* CAN4 id acceptance reg 0 */\r
-#define CAN4IDAR1 PORTIO_8(IO_BASE + 0x291) /* CAN4 id acceptance reg 1 */\r
-#define CAN4IDAR2 PORTIO_8(IO_BASE + 0x292) /* CAN4 id acceptance reg 2 */\r
-#define CAN4IDAR3 PORTIO_8(IO_BASE + 0x293) /* CAN4 id acceptance reg 3 */\r
-#define CAN4IDMR0 PORTIO_8(IO_BASE + 0x294) /* CAN4 id mask register 0 */\r
-#define CAN4IDMR1 PORTIO_8(IO_BASE + 0x295) /* CAN4 id mask register 1 */\r
-#define CAN4IDMR2 PORTIO_8(IO_BASE + 0x296) /* CAN4 id mask register 2 */\r
-#define CAN4IDMR3 PORTIO_8(IO_BASE + 0x297) /* CAN4 id mask register 3 */\r
-#define CAN4IDAR4 PORTIO_8(IO_BASE + 0x298) /* CAN4 id acceptance reg 4 */\r
-#define CAN4IDAR5 PORTIO_8(IO_BASE + 0x299) /* CAN4 id acceptance reg 5 */\r
-#define CAN4IDAR6 PORTIO_8(IO_BASE + 0x29a) /* CAN4 id acceptance reg 6 */\r
-#define CAN4IDAR7 PORTIO_8(IO_BASE + 0x29b) /* CAN4 id acceptance reg 7 */\r
-#define CAN4IDMR4 PORTIO_8(IO_BASE + 0x29c) /* CAN4 id mask register 4 */\r
-#define CAN4IDMR5 PORTIO_8(IO_BASE + 0x29d) /* CAN4 id mask register 5 */\r
-#define CAN4IDMR6 PORTIO_8(IO_BASE + 0x29e) /* CAN4 id mask register 6 */\r
-#define CAN4IDMR7 PORTIO_8(IO_BASE + 0x29f) /* CAN4 id mask register 7 */\r
-#define CAN4RXFG PORTIO_8(IO_BASE + 0x2a0) /* CAN4 receive buffer */\r
-#define CAN4TXFG PORTIO_8(IO_BASE + 0x2b0) /* CAN4 transmit buffer */\r
-\r
-\r
-\r
-# define SCIBD PORTIO_16(SCI_BASE + _SCIBD)\r
-# define SCICR1 PORTIO_8(SCI_BASE + _SCICR1)\r
-# define SCICR2 PORTIO_8(SCI_BASE + _SCICR2)\r
-# define SCISR1 PORTIO_8(SCI_BASE + _SCISR1)\r
-# define SCISR2 PORTIO_8(SCI_BASE + _SCISR2)\r
-# define SCIDRL PORTIO_8(SCI_BASE + _SCIDRL)\r
+#if defined(CFG_HCS12D)\r
+#include "regs_hcs12d.h"\r
+#elif defined(CFG_HCS12XD)\r
+#include "regs_hcs12xd.h"\r
+#else\r
+#error NO MCU SELECTED!!!!\r
+#endif\r
\r
#endif /* ifndef _REGS_H_ */\r
*/\r
void Irq_Init( void );\r
\r
-/**\r
- * End-Of-Interrupt. Called by the OS it wants to clear the interrupt.\r
- */\r
-void Irq_EOI( void );\r
+\r
+\r
\r
#if defined(CFG_HC1X)\r
/**\r
* @param type\r
*/\r
static inline void Irq_SetIsrType( IrqType vector, IsrType type ) {\r
- Irq_IsrTypeTable[vector + IRQ_INTERRUPT_OFFSET ] = type;\r
+ Irq_IsrTypeTable[vector] = type;\r
}\r
\r
/**\r
* 1 - Isr2\r
*/\r
static inline IsrType Irq_GetIsrType( IrqType vector ) {\r
- return Irq_IsrTypeTable[vector + IRQ_INTERRUPT_OFFSET ];\r
+ return Irq_IsrTypeTable[vector];\r
}\r
\r
\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-#ifndef MCU_CFG_H_\r
-#define MCU_CFG_H_\r
-\r
-#define MCU_DEV_ERROR_DETECT STD_ON\r
-#define MCU_PERFORM_RESET_API STD_ON\r
-#define MCU_VERSION_INFO_API STD_ON\r
-\r
-#include "Std_Types.h"\r
-\r
-typedef enum {\r
- MCU_CLOCKTYPE_EXT_REF_80MHZ = 0,\r
- MCU_CLOCKTYPE_EXT_REF_66MHZ,\r
- MCU_NBR_OF_CLOCKS,\r
-} Mcu_ClockType;\r
-\r
-#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
-\r
-#endif /*MCU_CFG_H_*/\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#ifndef MBOX_H_
+#define MBOX_H_
+
+#include "cirq_buffer.h"
+
+typedef struct
+{
+ CirqBufferType *cirqPtr;
+} Arc_MBoxType;
+
+
+typedef enum {
+ SOME_ERROR,
+} Arc_MBoxErrType;
+
+Arc_MBoxType* Arc_MBoxCreate( size_t size );
+void Arc_MBoxDestroy( Arc_MBoxType *mPtr );
+int Arc_MBoxPost( Arc_MBoxType *mPtr, void *msg );
+int Arc_MBoxFetch(Arc_MBoxType *mPtr, void *msg);
+
+#endif /* MBOX_H_ */
#endif\r
}\r
\r
-os_error_t os_error;\r
+OsErrorType os_error;\r
\r
//-------------------------------------------------------------------\r
\r
}\r
#endif\r
\r
-/*-----------------------------------------------------------------*/\r
-int Os_CfgGetTaskCnt(void) {\r
- return OS_TASK_CNT;\r
-}\r
/*-----------------------------------------------------------------*/\r
\r
OsResourceType *Os_CfgGetResource( ResourceType resource ) {\r
+#if OS_RESOURCE_CNT!=0\r
return &resource_list[resource];\r
-}\r
-\r
-int Os_CfgGetResourceCnt() {\r
- return OS_RESOURCE_CNT;\r
+#else\r
+ return NULL;\r
+#endif\r
}\r
\r
/*-----------------------------------------------------------------*/\r
return &counter_list[count_id];\r
}\r
\r
-uint32 Os_CfgGetCounterCnt(void ) {\r
- return OS_COUNTER_CNT;\r
-// return sizeof(counter_list)/sizeof(OsCounterType);\r
-}\r
/*-----------------------------------------------------------------*/\r
\r
-uint32 Os_CfgGetSchedCnt( void ) {\r
- return OS_SCHTBL_CNT;\r
-}\r
-\r
OsSchTblType *Os_CfgGetSched( ScheduleTableType sched_id ) {\r
#if (OS_SCHTBL_CNT!=0)\r
if(sched_id < OS_SCHTBL_CNT) {\r
\r
/*-----------------------------------------------------------------*/\r
\r
-uint32 Os_CfgGetAlarmCnt(void) {\r
- return OS_ALARM_CNT;\r
-}\r
-\r
OsAlarmType *Os_CfgGetAlarmObj( AlarmType alarm_id ) {\r
#if (OS_ALARM_CNT!=0)\r
if( alarm_id < OS_ALARM_CNT) {\r
\r
StatusType rv = E_OK;\r
\r
- if( alarm_id >= Os_CfgGetAlarmCnt() ) {\r
+ if( alarm_id >= OS_ALARM_CNT ) {\r
rv = E_OS_ID;\r
- }\r
+ } else {\r
#if (OS_ALARM_CNT!=0)\r
- *info = alarm_list[alarm_id].counter->alarm_base;\r
+ *info = alarm_list[alarm_id].counter->alarm_base;\r
#endif\r
+ }\r
return rv;\r
}\r
\r
.ShutdownHook = _shutdown, \\r
.ErrorHook = _error, \\r
.PreTaskHook = _pretask, \\r
- .PostTaskHook = _posttask, \\r
-};\r
+ .PostTaskHook = _posttask \\r
+}\r
#else\r
#define GEN_HOOKS( _startup, _protection, _shutdown, _error, _pretask, _posttask ) \\r
struct OsHooks os_conf_global_hooks = { \\r
.ShutdownHook = _shutdown, \\r
.ErrorHook = _error, \\r
.PreTaskHook = _pretask, \\r
- .PostTaskHook = _posttask, \\r
-};\r
+ .PostTaskHook = _posttask \\r
+}\r
\r
#endif\r
\r
* Note! Tried lots of other ways to do this but came up empty\r
*/\r
\r
-#define get_spr(spr_nr) \\r
+#define get_spr(spr_nr) CC_EXTENSION \\r
({\\r
uint32_t __val;\\r
asm volatile (" mfspr %0," STRINGIFY__(spr_nr) : "=r"(__val) : );\\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef SLEEP_H_\r
+#define SLEEP_H_\r
+\r
+#include "os.h"\r
+\r
+#define SLEEP(_x_) \\r
+do{ \\r
+ TaskType task; \\r
+ GetTaskID(&task); \\r
+ Sleep(_x_, task, EVENT_MASK_SLEEP_ALARM ); \\r
+ WaitEvent(EVENT_MASK_SLEEP_ALARM); \\r
+ ClearEvent(EVENT_MASK_SLEEP_ALARM); \\r
+}while(0);\r
+\r
+void Sleep(uint32_t nofTicks, TaskType TaskID, EventMaskType Mask );\r
+void SleepInit();\r
+\r
+#endif /* SLEEP_H_ */\r
# build with:\r
-# make subdir1 - build the subdir1 \r
-# make subdir1/subdir2 - build subdir2\r
-# \r
-# clean:\r
-# Removed all generated files \r
+# $ make BOARDDIR=<board> BDIR=<dir>[,<dir>] CROSS_COMPILE=<gcc> all|clean|clean_all\r
#\r
-# BOARDDIR=<board dir> \r
+# TARGETS\r
+# all: Target when building\r
+# clean: Remove generatated files for a board \r
+# clean_all: Remove all generated files\r
+# help: Print some help\r
+#\r
+# VARIABLES:\r
+# BOARDDIR=<board dir> \r
# Select what board to build for \r
-\r
-# BOARDDIR=<board dir> \r
-# Select what board to build for\r
-# \r
-# Q=[(@)/empty] \r
+# BDIR=<dir>[,<dir>] \r
+# Select what directories to build. The kernel if always built.\r
+# CROSS_COMPILE\r
+# Specify the compiler to use. \r
+# Q=[(@)/empty] \r
# If Q=@ cmd's will not be echoed.\r
-# \r
-# Build\r
-# >make BOARDDIR=mpc551xsim BDIR=system/kernel,examples/simple all \r
-# Clean \r
-# >make BOARDDIR=mpc551xsim BDIR=system/kernel,examples/simple clean\r
+#\r
+# EXAMPLES\r
+# Clean all\r
+# $ make clean_all\r
+#\r
+# Clean for a specific board\r
+# $ make BDIR=mpc551xsim clean\r
+#\r
+# Build the simple example (assuming CROSS_COMPILE set)\r
+# $ make BOARDDIR= mpc551xsim BDIR=examples/simple all\r
#\r
\r
+\r
export UNAME:=$(shell uname)\r
\r
ifneq ($(findstring Darwin,$(UNAME)),)\r
export SED=sed\r
endif\r
\r
-\r
Q?=@\r
export Q\r
export TOPDIR = $(CURDIR)\r
\r
ifneq ($(filter clean_all,$(MAKECMDGOALS)),clean_all)\r
ifeq (${BOARDDIR},)\r
- $(error BOARDDIR is empty) \r
+# $(error BOARDDIR is empty) \r
endif\r
endif\r
\r
# Tools\r
# Ugly thing to make things work under cmd.exe \r
PATH := /usr/bin/:$(PATH) \r
-find := $(shell which find)\r
+#find := $(shell which find)\r
+FIND := $(shell which find)\r
\r
export objdir = obj_$(BOARDDIR)\r
\r
comma:= ,\r
split = $(subst $(comma), ,$(1))\r
dir_cmd_goals := $(call split,$(BDIR))\r
-cmd_cmd_goals := $(filter clean all install,$(MAKECMDGOALS))\r
+cmd_cmd_goals := $(filter all clean config,$(MAKECMDGOALS))\r
+\r
+# Check for CROSS_COMPILE\r
+ifneq ($(cmd_cmd_goals),)\r
+#ifndef CROSS_COMPILE\r
+# $(error CROSS_COMPILE not defined)\r
+#endif\r
+\r
+# Check that the board actually exist\r
+ifdef BOARDDIR\r
+ all_boards := $(subst boards/,,$(shell $(FIND) boards/ -maxdepth 1 -type d))\r
+ ifeq ($(filter $(BOARDDIR),$(all_boards)),)\r
+ $(error no such board: $(BOARDDIR), valid boards are: $(all_boards))\r
+ endif\r
+endif\r
+\r
+# Check BDIR\r
+endif\r
\r
libs:\r
mkdir -p $@\r
\r
+.PHONY all:\r
+\r
all: libs $(dir_cmd_goals)\r
\r
+\r
+test:\r
+ @echo $(all_boards)\r
+\r
show_build:\r
- @echo Building for $(dir_cmd_goals)\r
- @echo BOARDDIR: $(BOARDDIR)\r
- @echo ARCH_FAM/ARCH: $(ARCH_FAM)/$(ARCH)\r
+ @echo "BUILD INFO"\r
+ @echo "BOARDDIR: $(BOARDDIR) [$(origin BOARDDIR)]"\r
+ @echo "BDIR: $(BDIR) [$(origin BDIR)]"\r
+ @echo "CROSS_COMPILE: $(CROSS_COMPILE) [$(origin CROSS_COMPILE)]"\r
+ @echo "cmd_cmd_goals: $(cmd_cmd_goals)"\r
+ \r
\r
-\r
$(dir_cmd_goals) :: show_build FORCE \r
@echo ==========[ $@ ]===========\r
+ @if [ ! -d $@ ]; then echo "No such directory: \"$@\" quitting"; exit 1; fi\r
+@[ -d $@/$(objdir) ] || mkdir -p $@/$(objdir)\r
@chmod 777 $@/$(objdir)\r
$(Q)$(MAKE) -r -C $@/$(objdir) -f $(CURDIR)/scripts/rules.mk ROOTDIR=$(CURDIR) SUBDIR=$@ $(cmd_cmd_goals)\r
\r
FORCE:\r
\r
+.PHONY: boards\r
+boards:\r
+ @find . -type d -name *\r
+\r
clean_all:\r
@find . -type d -name obj_* | xargs rm -rf\r
@find . -type f -name *.a | xargs rm -rf\r
echo Done!\r
\r
+config: $(dir_cmd_goals) \r
+ \r
+.PHONY clean: \r
clean: $(dir_cmd_goals)\r
@echo "Clean:"\r
@echo " Removing objectfiles and libs for ARCH=$(ARCH)"\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+//lint -emacro(904,VALIDATE_RV,VALIDATE_NO_RV) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
+\r
+// Exception made as a result of that NVM_DATASET_SELECTION_BITS can be zero\r
+//lint -emacro(835, MIN_BLOCKNR) // 835 PC-lint: A zero has been given as right argument to operator '<<' or '>>'\r
+//lint -emacro(835, GET_BLOCK_INDEX_FROM_BLOCK_NUMBER) // 835 PC-lint: A zero has been given as right argument to operator '<<' or '>>'\r
+//lint -emacro(835, GET_DATASET_FROM_BLOCK_NUMBER) // 835 PC-lint: A zero has been given as right argument to operator '<<' or '>>'\r
+//lint -emacro(778, GET_DATASET_FROM_BLOCK_NUMBER) // 778 PC-lint: Constant expression evaluates to 0 in operation '-'\r
+//lint -emacro(845, GET_DATASET_FROM_BLOCK_NUMBER) // 845 PC-lint: The right argument to operator '&' is certain to be 0\r
+//lint -emacro(835, BLOCK_INDEX_AND_SET_TO_BLOCKNR) // 835 PC-lint: A zero has been given as right argument to operator '<<' or '>>'\r
+\r
+#include <string.h>\r
+#include "Fee.h"\r
+#include "Fee_Cbk.h"\r
+#include "Fee_Memory_Cfg.h"\r
+#include "NvM.h"\r
+#include "Fls.h"\r
+#include "Rte.h" // ???\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+//#include "SchM_NvM.h"\r
+#include "MemMap.h"\r
+\r
+/*\r
+ * Local definitions\r
+ */\r
+\r
+/*\r
+ * Validation macros\r
+ */\r
+#if ( FEE_DEV_ERROR_DETECT == STD_ON )\r
+#include "Det.h"\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_FEE, 0, _api, _err); \\r
+ }\r
+\r
+#define VALIDATE_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_FEE, 0, _api, _err); \\r
+ return _rv; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_FEE, 0, _api, _err); \\r
+ return; \\r
+ }\r
+\r
+#define DET_REPORTERROR(_module,_instance,_api,_err) Det_ReportError(_module,_instance,_api,_err)\r
+\r
+#define MIN_BLOCKNR ((uint16)((uint16)1 << NVM_DATASET_SELECTION_BITS))\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_RV(_exp,_api,_err,_rv )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_module,_instance,_api,_err)\r
+#endif\r
+\r
+\r
+/*\r
+ * Block numbering recalculation macros
+ */\r
+#define GET_BLOCK_INDEX_FROM_BLOCK_NUMBER(_blocknr) (((_blocknr) >> NVM_DATASET_SELECTION_BITS) - 1u)\r
+#define GET_DATASET_FROM_BLOCK_NUMBER(_blocknr) ((_blocknr) & ((uint16)((uint16)1u << NVM_DATASET_SELECTION_BITS) - 1u))\r
+#define BLOCK_INDEX_AND_SET_TO_BLOCKNR(_blocknr, _set) ((uint16)((_blocknr + 1u) << NVM_DATASET_SELECTION_BITS) | _set)\r
+\r
+/*\r
+ * Page alignment macros
+ */\r
+#define PAGE_ALIGN(_size) ((uint16)((((_size) + FEE_VIRTUAL_PAGE_SIZE - 1) / FEE_VIRTUAL_PAGE_SIZE) * FEE_VIRTUAL_PAGE_SIZE))\r
+\r
+/*\r
+ * Bank properties list
+ */\r
+#define NUM_OF_BANKS 2\r
+typedef struct {\r
+ Fls_AddressType Start;\r
+ Fls_LengthType End;\r
+} BankPropType;\r
+\r
+static const BankPropType BankProp[NUM_OF_BANKS] = {\r
+ {\r
+ .Start = FEE_BANK1_OFFSET,\r
+ .End = FEE_BANK1_OFFSET + FEE_BANK1_LENGTH\r
+ },\r
+ {\r
+ .Start = FEE_BANK2_OFFSET,\r
+ .End = FEE_BANK2_OFFSET + FEE_BANK2_LENGTH\r
+ },\r
+};\r
+\r
+\r
+\r
+/*\r
+ * Macros and variables for flash bank administration
+ */\r
+#define BANK_STATUS_OLD 0x00\r
+#define BANK_STATUS_NEW 0xFF\r
+typedef uint8 FlsBankStatusType;\r
+\r
+#define BANK_CTRL_PAGE_SIZE PAGE_ALIGN(sizeof(FlsBankStatusType))\r
+\r
+typedef union {\r
+ FlsBankStatusType BankStatus;\r
+ uint8 Data[BANK_CTRL_PAGE_SIZE];\r
+} FlsBankCtrlPageType;\r
+\r
+\r
+/*\r
+ * Macros and variables for flash block administration in flash
+ */\r
+#define BLOCK_STATUS_INUSE 0x00\r
+#define BLOCK_STATUS_INVALIDATED 0x02\r
+#define BLOCK_STATUS_EMPTY 0xFF\r
+typedef uint8 BlockStatusType;\r
+\r
+typedef struct {\r
+ BlockStatusType Status;\r
+ uint16 BlockNo;\r
+ Fls_AddressType BlockDataAddress;\r
+ uint16 BlockDataLength;\r
+} FlsBlockCtrlDataType;\r
+\r
+#define BLOCK_CTRL_DATA_PAGE_SIZE PAGE_ALIGN(sizeof(FlsBlockCtrlDataType))\r
+\r
+typedef union {\r
+ FlsBlockCtrlDataType Data;\r
+ uint8 Byte[BLOCK_CTRL_DATA_PAGE_SIZE];\r
+} FlsBlockCtrlDataPageType;\r
+\r
+\r
+#define BLOCK_MAGIC_LEN 4\r
+static const uint8 BlockMagicMaster[BLOCK_MAGIC_LEN] = { 0xeb, 0xba, 0xba, 0xbe };\r
+#define BLOCK_CTRL_MAGIC_PAGE_SIZE PAGE_ALIGN(BLOCK_MAGIC_LEN)\r
+\r
+\r
+typedef union {\r
+ uint8 Magic[BLOCK_MAGIC_LEN];\r
+ uint8 Byte[BLOCK_CTRL_MAGIC_PAGE_SIZE];\r
+} FlsBlockCtrlMagicPageType;\r
+\r
+typedef struct {\r
+ FlsBlockCtrlDataPageType DataPage;\r
+ FlsBlockCtrlMagicPageType MagicPage;\r
+} FlsBlockControlType;\r
+\r
+#define BLOCK_CTRL_PAGE_SIZE PAGE_ALIGN(sizeof(FlsBlockControlType))\r
+\r
+#define BLOCK_CTRL_DATA_POS_OFFSET (/*lint --e(835)*/0) // Inform PC-Lint that I want the constant to be zero\r
+#define BLOCK_CTRL_MAGIC_POS_OFFSET BLOCK_CTRL_DATA_PAGE_SIZE\r
+\r
+typedef union {\r
+ FlsBlockControlType BlockCtrl;\r
+ FlsBankCtrlPageType BankCtrl;\r
+ uint8 Byte[BLOCK_CTRL_PAGE_SIZE];\r
+} ReadWriteBufferType;\r
+\r
+static ReadWriteBufferType RWBuffer;\r
+\r
+#define RWBUFFER_SIZE sizeof(ReadWriteBufferType)\r
+\r
+\r
+/*\r
+ * Variables for flash administration\r
+ */\r
+typedef struct {\r
+ BlockStatusType Status;\r
+ Fls_AddressType BlockAdminAddress;\r
+ Fls_AddressType BlockDataAddress;\r
+} AdminFlsBlockType;\r
+\r
+typedef struct {\r
+ uint8 BankNumber;\r
+ Fls_AddressType NewBlockAdminAddress;\r
+ Fls_AddressType NewBlockDataAddress;\r
+ FlsBankStatusType BankStatus[NUM_OF_BANKS];\r
+ AdminFlsBlockType BlockDescrTbl[FEE_NUM_OF_BLOCKS][FEE_MAX_NUM_SETS];\r
+} AdminFlsType;\r
+\r
+static AdminFlsType AdminFls;\r
+\r
+\r
+/*\r
+ * Variables for quick reporting of status and job result
+ */\r
+static MemIf_StatusType ModuleStatus = MEMIF_UNINIT;\r
+static MemIf_JobResultType JobResult = MEMIF_JOB_OK;\r
+\r
+/*\r
+ * Variables for the current job
+ */\r
+typedef enum {\r
+ FEE_UNINITIALIZED = 0,\r
+ FEE_STARTUP_REQUESTED,\r
+ FEE_STARTUP_READ_BANK1_STATUS,\r
+ FEE_STARTUP_READ_BANK2_STATUS_REQUESTED,\r
+ FEE_STARTUP_READ_BANK2_STATUS,\r
+ FEE_STARTUP_READ_BLOCK_ADMIN_REQUESTED,\r
+ FEE_STARTUP_READ_BLOCK_ADMIN,\r
+\r
+ FEE_IDLE,\r
+\r
+ FEE_WRITE_REQUESTED,\r
+ FEE_WRITE_MARK_BANK_OLD,\r
+ FEE_WRITE_HEADER_REQUESTED,\r
+ FEE_WRITE_HEADER,\r
+ FEE_WRITE_DATA_REQUESTED,\r
+ FEE_WRITE_DATA,\r
+ FEE_WRITE_MAGIC_REQUESTED,\r
+ FEE_WRITE_MAGIC,\r
+\r
+ FEE_READ_REQUESTED,\r
+ FEE_READ,\r
+\r
+ FEE_INVALIDATE_REQUESTED,\r
+ FEE_INVALIDATE_MARK_BANK_OLD,\r
+ FEE_WRITE_INVALIDATE_HEADER_REQUESTED,\r
+ FEE_WRITE_INVALIDATE_HEADER,\r
+\r
+ FEE_GARBAGE_COLLECT_REQUESTED,\r
+ FEE_GARBAGE_COLLECT_HEADER_WRITE,\r
+ FEE_GARBAGE_COLLECT_DATA_READ_REQUESTED,\r
+ FEE_GARBAGE_COLLECT_DATA_READ,\r
+ FEE_GARBAGE_COLLECT_DATA_WRITE_REQUESTED,\r
+ FEE_GARBAGE_COLLECT_DATA_WRITE,\r
+ FEE_GARBAGE_COLLECT_MAGIC_WRITE_REQUESTED,\r
+ FEE_GARBAGE_COLLECT_MAGIC_WRITE,\r
+ FEE_GARBAGE_COLLECT_ERASE\r
+} CurrentJobStateType;\r
+\r
+typedef struct {\r
+ CurrentJobStateType State;\r
+ uint16 InStateCounter;\r
+ uint16 BlockNumber;\r
+ uint16 Length;\r
+ const Fee_BlockConfigType *BlockConfigPtr;\r
+ AdminFlsBlockType *AdminFlsBlockPtr;\r
+ union {\r
+ struct {\r
+ uint8 NrOfBanks;\r
+ uint8 BankNumber;\r
+ Fls_AddressType BlockAdminAddress;\r
+ }Startup;\r
+ struct {\r
+ uint16 Offset;\r
+ uint8 *RamPtr;\r
+ }Read;\r
+ struct {\r
+ uint8 *RamPtr;\r
+ Fls_AddressType WriteAdminAddress;\r
+ Fls_AddressType WriteDataAddress;\r
+ }Write;\r
+ struct {\r
+ Fls_AddressType WriteAdminAddress;\r
+ Fls_AddressType WriteDataAddress;\r
+ }Invalidate;\r
+ struct {\r
+ uint8 BankNumber;\r
+ Fls_AddressType WriteAdminAddress;\r
+ Fls_AddressType WriteDataAddress;\r
+ uint16 BytesLeft;\r
+ uint16 DataOffset;\r
+ }GarbageCollect;\r
+ } Op;\r
+} CurrentJobType;\r
+\r
+static CurrentJobType CurrentJob = {\r
+ .State = FEE_IDLE,\r
+ .InStateCounter = 0\r
+ //lint -e{785} PC-Lint (785) - rest of structure members is initialized when used.\r
+};\r
+\r
+/*\r
+ * Misc definitions
+ */\r
+#define STATE_COUNTER_MAX 0xffff\r
+#define GARBAGE_COLLECTION_DELAY 10\r
+\r
+/***************************************\r
+ * Local functions *\r
+ ***************************************/\r
+\r
+#if (FEE_POLLING_MODE == STD_ON)\r
+#define SetFlsJobBusy() /* Nothing needs to be done here */\r
+\r
+static boolean CheckFlsJobFinnished(void)\r
+{\r
+ MemIf_JobResultType flsJobResult;\r
+\r
+ flsJobResult = Fls_GetJobResult();\r
+ return (flsJobResult != MEMIF_JOB_PENDING);\r
+}\r
+#else\r
+static boolean FlsJobReady = TRUE;\r
+\r
+static void SetFlsJobBusy()\r
+{\r
+ FlsJobReady = FALSE;\r
+}\r
+\r
+static boolean CheckFlsJobFinnished(void)\r
+{\r
+ return (FlsJobReady);\r
+}\r
+\r
+#endif\r
+\r
+\r
+static void FinnishStartup(void)\r
+{\r
+ CurrentJob.State = FEE_IDLE;\r
+ ModuleStatus = MEMIF_IDLE;\r
+ JobResult = MEMIF_JOB_OK;\r
+}\r
+\r
+\r
+static void AbortStartup(MemIf_JobResultType result)\r
+{\r
+ CurrentJob.State = FEE_IDLE;\r
+ ModuleStatus = MEMIF_IDLE;\r
+ JobResult = result;\r
+}\r
+\r
+\r
+static void FinnishJob(void)\r
+{\r
+ CurrentJob.State = FEE_IDLE;\r
+ ModuleStatus = MEMIF_IDLE;\r
+ JobResult = MEMIF_JOB_OK;\r
+\r
+ if (Fee_Config.General.NvmJobEndCallbackNotificationCallback != NULL) {\r
+ Fee_Config.General.NvmJobEndCallbackNotificationCallback();\r
+ }\r
+}\r
+\r
+\r
+static void AbortJob(MemIf_JobResultType result)\r
+{\r
+ CurrentJob.State = FEE_IDLE;\r
+ ModuleStatus = MEMIF_IDLE;\r
+ JobResult = result;\r
+\r
+ if (Fee_Config.General.NvmJobErrorCallbackNotificationCallback != NULL) {\r
+ Fee_Config.General.NvmJobErrorCallbackNotificationCallback();\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start of bank status 1 read\r
+ */\r
+static void StartupStartJob(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_STARTUP_READ_BANK1_STATUS;\r
+ /* Read bank status of bank 1 */\r
+ // PC-Lint exception (MISRA 11.4) - Pointer to pointer conversion ok by AUTOSAR\r
+ if (Fls_Read(BankProp[0].End - BANK_CTRL_PAGE_SIZE, /*lint -e(926)*/(uint8*)&AdminFls.BankStatus[0], sizeof(FlsBankStatusType)) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortStartup(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of bank 1 status read, if ok request for bank 2 status read\r
+ */\r
+static void StartupReadBank1Status(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ CurrentJob.State = FEE_STARTUP_READ_BANK2_STATUS_REQUESTED;\r
+ } else {\r
+ AbortStartup(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start of bank status 2 read\r
+ */\r
+static void StartupReadBank2StatusRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ /* Read bank status of bank 2 */\r
+ CurrentJob.State = FEE_STARTUP_READ_BANK2_STATUS;\r
+ // PC-Lint exception (MISRA 11.4) - Pointer to pointer conversion ok by AUTOSAR\r
+ if (Fls_Read(BankProp[1].End - BANK_CTRL_PAGE_SIZE, /*lint -e(926)*/(uint8*)&AdminFls.BankStatus[1], sizeof(FlsBankStatusType)) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortStartup(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of bank status 2 read - request for block status reading
+ */\r
+static void StartupReadBank2Status(void)\r
+{\r
+ MemIf_JobResultType jobResult;\r
+\r
+ if (CheckFlsJobFinnished()) {\r
+ jobResult = Fls_GetJobResult();\r
+ if (jobResult == MEMIF_JOB_OK) {\r
+ /* Select which bank to start with */\r
+ if ((AdminFls.BankStatus[0] != BANK_STATUS_OLD) && (AdminFls.BankStatus[1] != BANK_STATUS_OLD)){\r
+ /* None is marked as old, just start with one of them */\r
+ CurrentJob.Op.Startup.BankNumber = 0;\r
+ CurrentJob.Op.Startup.NrOfBanks = 2;\r
+ } else if ((AdminFls.BankStatus[0] == BANK_STATUS_OLD) && (AdminFls.BankStatus[1] == BANK_STATUS_OLD) ) {\r
+ /* Both banks are marked as old, this shall not be possible */\r
+ DET_REPORTERROR(MODULE_ID_FEE, 0, FEE_STARTUP_ID, FEE_FLASH_CORRUPT);\r
+ jobResult = MEMIF_JOB_FAILED;\r
+ } else if (AdminFls.BankStatus[0] == BANK_STATUS_OLD) {\r
+ CurrentJob.Op.Startup.BankNumber = 0;\r
+ CurrentJob.Op.Startup.NrOfBanks = 2;\r
+ } else {\r
+ CurrentJob.Op.Startup.BankNumber = 1;\r
+ CurrentJob.Op.Startup.NrOfBanks = 2;\r
+ }\r
+ }\r
+\r
+ if (jobResult != MEMIF_JOB_OK) {\r
+ AbortStartup(jobResult);\r
+ } else {\r
+ CurrentJob.Op.Startup.BlockAdminAddress = BankProp[CurrentJob.Op.Startup.BankNumber].End - (BLOCK_CTRL_PAGE_SIZE + BANK_CTRL_PAGE_SIZE);\r
+ CurrentJob.State = FEE_STARTUP_READ_BLOCK_ADMIN_REQUESTED;\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Start of block admin read
+ */\r
+static void StartupReadBlockAdminRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ /* Start reading the banks */\r
+ CurrentJob.State = FEE_STARTUP_READ_BLOCK_ADMIN;\r
+ if (Fls_Read(CurrentJob.Op.Startup.BlockAdminAddress, RWBuffer.Byte, BLOCK_CTRL_PAGE_SIZE) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortStartup(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of block admin read, if all block processed finish\r
+ * otherwise request for a new block admin read
+ */\r
+static void StartupReadBlockAdmin(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ if (RWBuffer.BlockCtrl.DataPage.Data.Status == BLOCK_STATUS_EMPTY) {\r
+ VALIDATE(CurrentJob.Op.Startup.NrOfBanks != 0, FEE_STARTUP_ID, FEE_FLASH_CORRUPT);\r
+ CurrentJob.Op.Startup.NrOfBanks--;\r
+ CurrentJob.Op.Startup.BankNumber = (CurrentJob.Op.Startup.BankNumber + 1) % 2;\r
+ CurrentJob.Op.Startup.BlockAdminAddress = BankProp[CurrentJob.Op.Startup.BankNumber].End - (BLOCK_CTRL_PAGE_SIZE + BANK_CTRL_PAGE_SIZE);\r
+ } else { /* Block not empty */\r
+ if ((memcmp(RWBuffer.BlockCtrl.MagicPage.Magic, BlockMagicMaster, BLOCK_MAGIC_LEN) == 0) &&\r
+ ((RWBuffer.BlockCtrl.DataPage.Data.Status == BLOCK_STATUS_INUSE) || (RWBuffer.BlockCtrl.DataPage.Data.Status == BLOCK_STATUS_INVALIDATED))) {\r
+ /* This is a valid admin block */\r
+ uint16 blockIndex;\r
+ uint16 dataSet;\r
+\r
+ blockIndex = GET_BLOCK_INDEX_FROM_BLOCK_NUMBER(RWBuffer.BlockCtrl.DataPage.Data.BlockNo);\r
+ dataSet = GET_DATASET_FROM_BLOCK_NUMBER(RWBuffer.BlockCtrl.DataPage.Data.BlockNo);\r
+\r
+ if ((blockIndex < FEE_NUM_OF_BLOCKS) && (dataSet < FEE_MAX_NUM_SETS)) {\r
+ AdminFls.BlockDescrTbl[blockIndex][dataSet].BlockAdminAddress = CurrentJob.Op.Startup.BlockAdminAddress;\r
+ AdminFls.BlockDescrTbl[blockIndex][dataSet].BlockDataAddress = RWBuffer.BlockCtrl.DataPage.Data.BlockDataAddress;\r
+ AdminFls.BlockDescrTbl[blockIndex][dataSet].Status = RWBuffer.BlockCtrl.DataPage.Data.Status;\r
+\r
+ AdminFls.BankNumber = CurrentJob.Op.Startup.BankNumber;\r
+ AdminFls.NewBlockDataAddress = RWBuffer.BlockCtrl.DataPage.Data.BlockDataAddress + RWBuffer.BlockCtrl.DataPage.Data.BlockDataLength;\r
+ if (CurrentJob.Op.Startup.BlockAdminAddress <= AdminFls.NewBlockDataAddress) {\r
+ /* This shall never happen */\r
+ DET_REPORTERROR(MODULE_ID_FEE, 0, FEE_STARTUP_ID, FEE_FLASH_CORRUPT);\r
+ }\r
+ }\r
+ }\r
+ CurrentJob.Op.Startup.BlockAdminAddress -= BLOCK_CTRL_PAGE_SIZE;\r
+ AdminFls.NewBlockAdminAddress = CurrentJob.Op.Startup.BlockAdminAddress;\r
+ }\r
+\r
+ if (CurrentJob.Op.Startup.NrOfBanks == 0) {\r
+ /* If current bank is marked as old we need to switch to a new bank */\r
+ if (AdminFls.BankStatus[AdminFls.BankNumber] == BANK_STATUS_OLD) {\r
+ AdminFls.BankNumber = (AdminFls.BankNumber + 1) % 2;\r
+ AdminFls.NewBlockAdminAddress = BankProp[AdminFls.BankNumber].End - (BLOCK_CTRL_PAGE_SIZE + BANK_CTRL_PAGE_SIZE);\r
+ AdminFls.NewBlockDataAddress = BankProp[AdminFls.BankNumber].Start;\r
+ }\r
+ /* We are done! */\r
+ FinnishStartup();\r
+ } else {\r
+ CurrentJob.State = FEE_STARTUP_READ_BLOCK_ADMIN_REQUESTED;\r
+ }\r
+\r
+\r
+ } else { /* ErrorStatus not E_OK */\r
+ AbortStartup(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start of read block data\r
+ */\r
+static void ReadStartJob(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ if (CurrentJob.AdminFlsBlockPtr->Status != BLOCK_STATUS_EMPTY) {\r
+ if (CurrentJob.AdminFlsBlockPtr->Status != BLOCK_STATUS_INVALIDATED) {\r
+ CurrentJob.State = FEE_READ;\r
+ /* Read the actual data */\r
+ if (Fls_Read(CurrentJob.AdminFlsBlockPtr->BlockDataAddress + CurrentJob.Op.Read.Offset, CurrentJob.Op.Read.RamPtr, CurrentJob.Length) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ } else {\r
+ /* Invalid */\r
+ AbortJob(MEMIF_BLOCK_INVALID);\r
+ }\r
+ } else {\r
+ /* Inconsistent */\r
+ AbortJob(MEMIF_BLOCK_INCONSISTENT);\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Check job result of block data read
+ */\r
+static void Reading(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ FinnishJob();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Write bank header\r
+ */\r
+static void BankHeaderOldWrite(uint8 bank)\r
+{\r
+ /* Mark the bank as old */\r
+ memset(RWBuffer.BankCtrl.Data, 0xff, BANK_CTRL_PAGE_SIZE);\r
+ RWBuffer.BankCtrl.BankStatus = BANK_STATUS_OLD;\r
+ if (Fls_Write(BankProp[bank].End - BANK_CTRL_PAGE_SIZE, RWBuffer.BankCtrl.Data, BANK_CTRL_PAGE_SIZE) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Write block header\r
+ */\r
+static void BlockHeaderDataWrite(void)\r
+{\r
+ /* Write the header excluding the magic */\r
+ memset(RWBuffer.BlockCtrl.DataPage.Byte, 0xff, BLOCK_CTRL_DATA_PAGE_SIZE);\r
+ RWBuffer.BlockCtrl.DataPage.Data.Status = BLOCK_STATUS_INUSE;\r
+ RWBuffer.BlockCtrl.DataPage.Data.BlockNo = CurrentJob.BlockNumber;\r
+ RWBuffer.BlockCtrl.DataPage.Data.BlockDataAddress = AdminFls.NewBlockDataAddress;\r
+ RWBuffer.BlockCtrl.DataPage.Data.BlockDataLength = CurrentJob.Length;\r
+ if (Fls_Write(CurrentJob.Op.Write.WriteAdminAddress + BLOCK_CTRL_DATA_POS_OFFSET, RWBuffer.Byte, BLOCK_CTRL_DATA_PAGE_SIZE) == E_OK) {\r
+ SetFlsJobBusy();\r
+ AdminFls.NewBlockDataAddress += CurrentJob.Length;\r
+ AdminFls.NewBlockAdminAddress -= BLOCK_CTRL_PAGE_SIZE;\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check if bank switch needed:\r
+ * - Yes, start mark current bank as old\r
+ * - No, start of header write\r
+ */\r
+static void WriteStartJob(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ if (AdminFls.NewBlockDataAddress + CurrentJob.BlockConfigPtr->BlockSize > AdminFls.NewBlockAdminAddress - BLOCK_CTRL_PAGE_SIZE) {\r
+ /* Bank switch needed, mark current bank as "old" */\r
+ CurrentJob.State = FEE_WRITE_MARK_BANK_OLD;\r
+ BankHeaderOldWrite(AdminFls.BankNumber);\r
+ } else {\r
+ CurrentJob.Op.Write.WriteDataAddress = AdminFls.NewBlockDataAddress;\r
+ CurrentJob.Op.Write.WriteAdminAddress = AdminFls.NewBlockAdminAddress;\r
+\r
+ CurrentJob.State = FEE_WRITE_HEADER;\r
+ BlockHeaderDataWrite();\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of mark bank as old, if ok request for header write\r
+ */\r
+static void WriteMarkBankOldState(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ /* Mark for garbage collection */\r
+ AdminFls.BankStatus[AdminFls.BankNumber] = BANK_STATUS_OLD;\r
+\r
+ /* Change of bank */\r
+ AdminFls.BankNumber ^= 0x1u;\r
+ AdminFls.NewBlockDataAddress = BankProp[AdminFls.BankNumber].Start;\r
+ AdminFls.NewBlockAdminAddress = BankProp[AdminFls.BankNumber].End - (BLOCK_CTRL_PAGE_SIZE + BANK_CTRL_PAGE_SIZE);\r
+\r
+ CurrentJob.Op.Write.WriteDataAddress = AdminFls.NewBlockDataAddress;\r
+ CurrentJob.Op.Write.WriteAdminAddress = AdminFls.NewBlockAdminAddress;\r
+\r
+ CurrentJob.State = FEE_WRITE_HEADER_REQUESTED;\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start of header write
+ */\r
+static void WriteHeaderRequested()\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_WRITE_HEADER;\r
+ BlockHeaderDataWrite();\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of write header, if ok request for block data write\r
+ */\r
+static void WriteHeaderState(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ CurrentJob.State = FEE_WRITE_DATA_REQUESTED;\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start block data write
+ */\r
+static void WriteDataRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_WRITE_DATA;\r
+ /* Write the actual data */\r
+ if (Fls_Write(CurrentJob.Op.Write.WriteDataAddress, CurrentJob.Op.Write.RamPtr, CurrentJob.Length) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of data write - request for magic write\r
+ */\r
+static void WriteDataState(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ CurrentJob.State = FEE_WRITE_MAGIC_REQUESTED;\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start magic write
+ */\r
+static void WriteMagicRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_WRITE_MAGIC;\r
+ memset(RWBuffer.BlockCtrl.MagicPage.Byte, 0xff, BLOCK_CTRL_MAGIC_PAGE_SIZE);\r
+ memcpy(RWBuffer.BlockCtrl.MagicPage.Magic, BlockMagicMaster, BLOCK_MAGIC_LEN);\r
+ if (Fls_Write(CurrentJob.Op.Write.WriteAdminAddress + BLOCK_CTRL_MAGIC_POS_OFFSET, RWBuffer.BlockCtrl.MagicPage.Byte, BLOCK_CTRL_MAGIC_PAGE_SIZE) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of write magic, if ok update the block admin table and finish\r
+ */\r
+static void WriteMagicState(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ /* Update the block admin table */\r
+ CurrentJob.AdminFlsBlockPtr->Status = BLOCK_STATUS_INUSE;\r
+ CurrentJob.AdminFlsBlockPtr->BlockAdminAddress = CurrentJob.Op.Write.WriteAdminAddress;\r
+ CurrentJob.AdminFlsBlockPtr->BlockDataAddress = CurrentJob.Op.Write.WriteDataAddress;\r
+\r
+ FinnishJob();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check if any bank is marked as old\r
+ */\r
+static void CheckIfGarbageCollectionNeeded(void)\r
+{\r
+ if ((AdminFls.BankStatus[0] == BANK_STATUS_OLD) || (AdminFls.BankStatus[1] == BANK_STATUS_OLD)) {\r
+ ModuleStatus = MEMIF_BUSY_INTERNAL;\r
+ JobResult = MEMIF_JOB_PENDING;\r
+\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_REQUESTED;\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Checks if any blocks needs to be moved if so start with writing a new header\r
+ * or if no blocks needs to be moved request for bank erase.\r
+ */\r
+static void GarbageCollectStartJob(void)\r
+{\r
+ uint16 blockIndex;\r
+ uint16 set;\r
+ boolean found = FALSE;\r
+ uint8 sourceBank;\r
+\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ if ((AdminFls.BankStatus[0] == BANK_STATUS_OLD) || (AdminFls.BankStatus[1] == BANK_STATUS_OLD)) {\r
+ if (AdminFls.BankStatus[0] == BANK_STATUS_OLD) {\r
+ sourceBank = 0;\r
+ } else {\r
+ sourceBank = 1;\r
+ }\r
+\r
+ for (blockIndex = 0; (blockIndex < FEE_NUM_OF_BLOCKS) && (!found); blockIndex++) {\r
+ for (set = 0; (set < FEE_MAX_NUM_SETS) && (!found); set++) {\r
+ if (AdminFls.BlockDescrTbl[blockIndex][set].Status != BLOCK_STATUS_EMPTY) {\r
+ if ((AdminFls.BlockDescrTbl[blockIndex][set].BlockAdminAddress >= BankProp[sourceBank].Start) && (AdminFls.BlockDescrTbl[blockIndex][set].BlockAdminAddress < (BankProp[sourceBank].End))) {\r
+ CurrentJob.AdminFlsBlockPtr = &AdminFls.BlockDescrTbl[blockIndex][set];\r
+ CurrentJob.BlockConfigPtr = &Fee_Config.BlockConfig[blockIndex];\r
+ CurrentJob.BlockNumber = BLOCK_INDEX_AND_SET_TO_BLOCKNR(blockIndex, set);\r
+ if (AdminFls.BlockDescrTbl[blockIndex][set].Status == BLOCK_STATUS_INVALIDATED) {\r
+ CurrentJob.Length = 0;\r
+ } else {\r
+ CurrentJob.Length = PAGE_ALIGN(CurrentJob.BlockConfigPtr->BlockSize);\r
+ }\r
+\r
+ found = TRUE;\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ if (found) {\r
+ CurrentJob.Op.GarbageCollect.WriteDataAddress = AdminFls.NewBlockDataAddress;\r
+ CurrentJob.Op.GarbageCollect.WriteAdminAddress = AdminFls.NewBlockAdminAddress;\r
+\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_HEADER_WRITE;\r
+ BlockHeaderDataWrite();\r
+ } else {\r
+ if (Fls_Erase(BankProp[sourceBank].Start, BankProp[sourceBank].End - BankProp[sourceBank].Start) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ CurrentJob.Op.GarbageCollect.BankNumber = sourceBank;\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_ERASE;\r
+ }\r
+ } else {\r
+ CurrentJob.State = FEE_IDLE;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of write header, if ok request for read block data\r
+ */\r
+static void GarbageCollectWriteHeader(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ if (CurrentJob.AdminFlsBlockPtr->Status == BLOCK_STATUS_INUSE) {\r
+ CurrentJob.Op.GarbageCollect.BytesLeft = PAGE_ALIGN(CurrentJob.BlockConfigPtr->BlockSize);\r
+ CurrentJob.Op.GarbageCollect.DataOffset = 0;\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_DATA_READ_REQUESTED;\r
+ } else {\r
+ /* Yes, we are finished */\r
+ VALIDATE_NO_RV(CurrentJob.AdminFlsBlockPtr->Status == BLOCK_STATUS_INVALIDATED, FEE_GARBAGE_WRITE_HEADER_ID, FEE_UNEXPECTED_STATUS);\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_MAGIC_WRITE_REQUESTED;\r
+ }\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start of read block data, if data length is more than buffer size\r
+ * the reading is segmented.\r
+ */\r
+static void GarbageCollectReadDataRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_DATA_READ;\r
+ if (CurrentJob.Op.GarbageCollect.BytesLeft <= RWBUFFER_SIZE) {\r
+ CurrentJob.Length = CurrentJob.Op.GarbageCollect.BytesLeft;\r
+ } else {\r
+ CurrentJob.Length = RWBUFFER_SIZE;\r
+ }\r
+ if (Fls_Read(CurrentJob.AdminFlsBlockPtr->BlockDataAddress + CurrentJob.Op.GarbageCollect.DataOffset, RWBuffer.Byte, CurrentJob.Length) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of read block data, if ok request for a data write\r
+ */\r
+static void GarbageCollectReadData(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_DATA_WRITE_REQUESTED;\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start of write block data\r
+ */\r
+static void GarbageCollectWriteDataRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_DATA_WRITE;\r
+ /* Write the actual data */\r
+ if (Fls_Write(CurrentJob.Op.GarbageCollect.WriteDataAddress + CurrentJob.Op.GarbageCollect.DataOffset, RWBuffer.Byte, CurrentJob.Length) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of write data, if ok request for write magic or\r
+ * next data read depending on if there are more block data to move.\r
+ */\r
+static void GarbageCollectWriteData(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ if (CurrentJob.Op.GarbageCollect.BytesLeft <= RWBUFFER_SIZE) {\r
+ /* Yes, we are finished */\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_MAGIC_WRITE_REQUESTED;\r
+ } else {\r
+ /* More data to move */\r
+ CurrentJob.Op.GarbageCollect.DataOffset += RWBUFFER_SIZE;\r
+ CurrentJob.Op.GarbageCollect.BytesLeft -= RWBUFFER_SIZE;\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_DATA_READ_REQUESTED;\r
+ }\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Start write magic\r
+ */\r
+static void GarbageCollectWriteMagicRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_GARBAGE_COLLECT_MAGIC_WRITE;\r
+ memset(RWBuffer.BlockCtrl.MagicPage.Byte, 0xff, BLOCK_CTRL_MAGIC_PAGE_SIZE);\r
+ memcpy(RWBuffer.BlockCtrl.MagicPage.Magic, BlockMagicMaster, BLOCK_MAGIC_LEN);\r
+ if (Fls_Write(CurrentJob.Op.GarbageCollect.WriteAdminAddress + BLOCK_CTRL_MAGIC_POS_OFFSET, RWBuffer.BlockCtrl.MagicPage.Byte, BLOCK_CTRL_MAGIC_PAGE_SIZE) == E_OK) {\r
+ SetFlsJobBusy();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check the job result of write magic, if ok update the admin table with the new position of data.\r
+ */\r
+static void GarbageCollectWriteMagic(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ CurrentJob.AdminFlsBlockPtr->BlockAdminAddress = CurrentJob.Op.GarbageCollect.WriteAdminAddress;\r
+ CurrentJob.AdminFlsBlockPtr->BlockDataAddress = CurrentJob.Op.GarbageCollect.WriteDataAddress;\r
+ FinnishJob();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check the result of the erase job\r
+ */\r
+static void GarbageCollectErase(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ AdminFls.BankStatus[CurrentJob.Op.GarbageCollect.BankNumber] = BANK_STATUS_NEW;\r
+ FinnishJob();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Write an "Invalidated" block header\r
+ */\r
+static void BlockHeaderInvalidWrite(void)\r
+{\r
+ // Write the header including the magic\r
+ memset(RWBuffer.Byte, 0xff, BLOCK_CTRL_PAGE_SIZE);\r
+ RWBuffer.BlockCtrl.DataPage.Data.Status = BLOCK_STATUS_INVALIDATED;\r
+ RWBuffer.BlockCtrl.DataPage.Data.BlockNo = CurrentJob.BlockNumber;\r
+ RWBuffer.BlockCtrl.DataPage.Data.BlockDataAddress = AdminFls.NewBlockDataAddress;\r
+ RWBuffer.BlockCtrl.DataPage.Data.BlockDataLength = 0;\r
+ memset(RWBuffer.BlockCtrl.MagicPage.Byte, 0xff, BLOCK_CTRL_MAGIC_PAGE_SIZE);\r
+ memcpy(RWBuffer.BlockCtrl.MagicPage.Magic, BlockMagicMaster, BLOCK_MAGIC_LEN);\r
+\r
+ if (Fls_Write(CurrentJob.Op.Invalidate.WriteAdminAddress + BLOCK_CTRL_DATA_POS_OFFSET, RWBuffer.Byte, BLOCK_CTRL_PAGE_SIZE) == E_OK) {\r
+ SetFlsJobBusy();\r
+ AdminFls.NewBlockDataAddress += CurrentJob.Length;\r
+ AdminFls.NewBlockAdminAddress -= BLOCK_CTRL_PAGE_SIZE;\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check if bank switch is needed, if yes request for marking current bank as old,\r
+ * if no request for writing a header with "Invalid" status set.\r
+ */\r
+static void InvalidateStartJob(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ if (AdminFls.NewBlockDataAddress + CurrentJob.BlockConfigPtr->BlockSize > AdminFls.NewBlockAdminAddress - BLOCK_CTRL_PAGE_SIZE) {\r
+ /* Bank switch needed, mark current bank as "old" */\r
+ CurrentJob.State = FEE_INVALIDATE_MARK_BANK_OLD;\r
+ BankHeaderOldWrite(AdminFls.BankNumber);\r
+ } else {\r
+ CurrentJob.Op.Invalidate.WriteDataAddress = AdminFls.NewBlockDataAddress;\r
+ CurrentJob.Op.Invalidate.WriteAdminAddress = AdminFls.NewBlockAdminAddress;\r
+\r
+ CurrentJob.State = FEE_WRITE_INVALIDATE_HEADER;\r
+ BlockHeaderInvalidWrite();\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check job result of mark bank old, if ok continue with request for writing\r
+ * a header with "Invalid" status set.\r
+ */\r
+static void InvalidateMarkBankOld(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ // Mark for garbage collection\r
+ AdminFls.BankStatus[AdminFls.BankNumber] = BANK_STATUS_OLD;\r
+\r
+ // Change of bank\r
+ AdminFls.BankNumber ^= 0x1u;\r
+ AdminFls.NewBlockDataAddress = BankProp[AdminFls.BankNumber].Start;\r
+ AdminFls.NewBlockAdminAddress = BankProp[AdminFls.BankNumber].End - (BLOCK_CTRL_PAGE_SIZE + BANK_CTRL_PAGE_SIZE);\r
+\r
+ CurrentJob.Op.Invalidate.WriteDataAddress = AdminFls.NewBlockDataAddress;\r
+ CurrentJob.Op.Invalidate.WriteAdminAddress = AdminFls.NewBlockAdminAddress;\r
+\r
+ CurrentJob.State = FEE_WRITE_INVALIDATE_HEADER_REQUESTED;\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+/*\r
+ * Start the writing of the "Invalid" header.
+ */\r
+static void InvalidateWriteInvalidateHeaderRequested(void)\r
+{\r
+ if (Fls_GetStatus() == MEMIF_IDLE) {\r
+ CurrentJob.State = FEE_WRITE_INVALIDATE_HEADER;\r
+ BlockHeaderInvalidWrite();\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Check the job result of "Invalid" header write, if ok update the block admin table\r
+ */\r
+static void InvalidateWriteInvalidateHeader(void)\r
+{\r
+ if (CheckFlsJobFinnished()) {\r
+ if (Fls_GetJobResult() == MEMIF_JOB_OK) {\r
+ // Update the block admin table\r
+ CurrentJob.AdminFlsBlockPtr->Status = BLOCK_STATUS_INVALIDATED;\r
+ CurrentJob.AdminFlsBlockPtr->BlockAdminAddress = CurrentJob.Op.Invalidate.WriteAdminAddress;\r
+ CurrentJob.AdminFlsBlockPtr->BlockDataAddress = CurrentJob.Op.Invalidate.WriteDataAddress;\r
+\r
+ FinnishJob();\r
+ } else {\r
+ AbortJob(Fls_GetJobResult());\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/***************************************\r
+ * External accessible functions *\r
+ ***************************************/\r
+/*\r
+ * Procedure: Fee_Init\r
+ * Reentrant: No\r
+ */\r
+void Fee_Init(void)\r
+{\r
+ uint16 i,j;\r
+\r
+ /* Reporting information */\r
+ ModuleStatus = MEMIF_BUSY_INTERNAL;\r
+ JobResult = MEMIF_JOB_OK;\r
+\r
+ /* State of device */\r
+ CurrentJob.State = FEE_STARTUP_REQUESTED;\r
+ CurrentJob.InStateCounter = 0;\r
+#if (FEE_POLLING_MODE == STD_OFF)\r
+ FlsJobReady = TRUE;\r
+#endif\r
+\r
+ AdminFls.BankNumber = 0;\r
+ AdminFls.NewBlockDataAddress = BankProp[AdminFls.BankNumber].Start;\r
+ AdminFls.NewBlockAdminAddress = BankProp[AdminFls.BankNumber].End - (BLOCK_CTRL_PAGE_SIZE + BANK_CTRL_PAGE_SIZE);\r
+\r
+ for (i = 0; i < NUM_OF_BANKS; i++) {\r
+ AdminFls.BankStatus[i] = BANK_STATUS_NEW;\r
+ }\r
+\r
+ for (i = 0; i < FEE_NUM_OF_BLOCKS; i++) {\r
+ for (j = 0; j < FEE_MAX_NUM_SETS; j++) {\r
+ AdminFls.BlockDescrTbl[i][j].Status = BLOCK_STATUS_EMPTY;\r
+ AdminFls.BlockDescrTbl[i][j].BlockAdminAddress= 0;\r
+ AdminFls.BlockDescrTbl[i][j].BlockDataAddress = 0;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_SetMode\r
+ * Reentrant: No\r
+ */\r
+void Fee_SetMode(MemIf_ModeType mode)\r
+{\r
+#if ( FLS_SET_MODE_API == STD_ON )\r
+ Fls_SetMode(mode);\r
+#else\r
+ //lint --e{715} PC-Lint (715) - variable "mode" not used in this case\r
+ DET_REPORTERROR(MODULE_ID_FEE, 0, FEE_SET_MODE_ID, FEE_E_NOT_SUPPORTED);\r
+#endif\r
+}\r
+\r
+/*\r
+ * Procedure: Fee_Read\r
+ * Reentrant: No\r
+ */\r
+Std_ReturnType Fee_Read(uint16 blockNumber, uint16 blockOffset, uint8* dataBufferPtr, uint16 length)\r
+{\r
+ uint16 blockIndex;\r
+ uint16 dataset;\r
+\r
+ VALIDATE_RV(ModuleStatus != MEMIF_UNINIT, FEE_READ_ID, FEE_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_RV(ModuleStatus == MEMIF_IDLE, FEE_READ_ID, FEE_E_BUSY, E_NOT_OK);\r
+\r
+ VALIDATE_RV(blockNumber >= MIN_BLOCKNR, FEE_READ_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+ blockIndex = GET_BLOCK_INDEX_FROM_BLOCK_NUMBER(blockNumber);\r
+ VALIDATE_RV(blockIndex < FEE_NUM_OF_BLOCKS, FEE_READ_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+ VALIDATE_RV(dataBufferPtr != NULL, FEE_READ_ID, FEE_E_INVALID_DATA_PTR, E_NOT_OK);\r
+ VALIDATE_RV(blockOffset < Fee_Config.BlockConfig[blockIndex].BlockSize, FEE_READ_ID, FEE_E_INVALID_BLOCK_OFS, E_NOT_OK);\r
+ VALIDATE_RV(blockOffset + length <= Fee_Config.BlockConfig[blockIndex].BlockSize, FEE_READ_ID, FEE_E_INVALID_BLOCK_LEN, E_NOT_OK);\r
+\r
+ dataset = GET_DATASET_FROM_BLOCK_NUMBER(blockNumber);\r
+ VALIDATE_RV(dataset < FEE_MAX_NUM_SETS, FEE_READ_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+\r
+\r
+ /** @req FEE022 */\r
+ ModuleStatus = MEMIF_BUSY;\r
+ JobResult = MEMIF_JOB_PENDING;\r
+\r
+ CurrentJob.BlockNumber = blockNumber;\r
+ CurrentJob.BlockConfigPtr = &Fee_Config.BlockConfig[blockIndex];\r
+ CurrentJob.AdminFlsBlockPtr = &AdminFls.BlockDescrTbl[blockIndex][dataset];\r
+ CurrentJob.Length = length;\r
+ CurrentJob.Op.Read.Offset = blockOffset;\r
+ CurrentJob.Op.Read.RamPtr = dataBufferPtr;\r
+ CurrentJob.State = FEE_READ_REQUESTED;\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_Write\r
+ * Reentrant: No\r
+ */\r
+Std_ReturnType Fee_Write(uint16 blockNumber, uint8* dataBufferPtr)\r
+{\r
+ uint16 blockIndex;\r
+ uint16 dataset;\r
+\r
+ VALIDATE_RV(ModuleStatus != MEMIF_UNINIT, FEE_WRITE_ID, FEE_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_RV(ModuleStatus == MEMIF_IDLE, FEE_WRITE_ID, FEE_E_BUSY, E_NOT_OK);\r
+\r
+ VALIDATE_RV(blockNumber >= MIN_BLOCKNR, FEE_WRITE_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+ blockIndex = GET_BLOCK_INDEX_FROM_BLOCK_NUMBER(blockNumber);\r
+ VALIDATE_RV(blockIndex < FEE_NUM_OF_BLOCKS, FEE_WRITE_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+ VALIDATE_RV(dataBufferPtr != NULL, FEE_WRITE_ID, FEE_E_INVALID_DATA_PTR, E_NOT_OK);\r
+\r
+ dataset = GET_DATASET_FROM_BLOCK_NUMBER(blockNumber);\r
+ VALIDATE_RV(dataset < FEE_MAX_NUM_SETS, FEE_WRITE_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+\r
+\r
+ /** @req FEE025 */\r
+ ModuleStatus = MEMIF_BUSY;\r
+ JobResult = MEMIF_JOB_PENDING;\r
+\r
+ CurrentJob.BlockConfigPtr = &Fee_Config.BlockConfig[blockIndex];\r
+ CurrentJob.AdminFlsBlockPtr = &AdminFls.BlockDescrTbl[blockIndex][dataset];\r
+ CurrentJob.BlockNumber = blockNumber;\r
+ CurrentJob.Length = PAGE_ALIGN(CurrentJob.BlockConfigPtr->BlockSize);\r
+ CurrentJob.Op.Write.RamPtr = dataBufferPtr;\r
+ CurrentJob.State = FEE_WRITE_REQUESTED;\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_Cancel\r
+ * Reentrant: No\r
+ */\r
+void Fee_Cancel(void)\r
+{\r
+ DET_REPORTERROR(MODULE_ID_FEE, 0, FEE_CANCEL_ID, FEE_E_NOT_IMPLEMENTED_YET);\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_GetStatus\r
+ * Reentrant: No\r
+ */\r
+MemIf_StatusType Fee_GetStatus(void)\r
+{\r
+ return ModuleStatus;\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_GetJobResult\r
+ * Reentrant: No\r
+ */\r
+MemIf_JobResultType Fee_GetJobResult(void)\r
+{\r
+ return JobResult;\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_InvalidateBlock\r
+ * Reentrant: No\r
+ */\r
+Std_ReturnType Fee_InvalidateBlock(uint16 blockNumber)\r
+{\r
+ uint16 blockIndex;\r
+ uint16 dataset;\r
+\r
+ VALIDATE_RV(ModuleStatus != MEMIF_UNINIT, FEE_INVALIDATE_BLOCK_ID, FEE_E_UNINIT, E_NOT_OK);\r
+ VALIDATE_RV(ModuleStatus == MEMIF_IDLE, FEE_INVALIDATE_BLOCK_ID, FEE_E_BUSY, E_NOT_OK);\r
+\r
+ VALIDATE_RV(blockNumber >= MIN_BLOCKNR, FEE_INVALIDATE_BLOCK_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+ blockIndex = GET_BLOCK_INDEX_FROM_BLOCK_NUMBER(blockNumber);\r
+ VALIDATE_RV(blockIndex < FEE_NUM_OF_BLOCKS, FEE_INVALIDATE_BLOCK_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+\r
+ dataset = GET_DATASET_FROM_BLOCK_NUMBER(blockNumber);\r
+ VALIDATE_RV(dataset < FEE_MAX_NUM_SETS, FEE_INVALIDATE_BLOCK_ID, FEE_E_INVALID_BLOCK_NO, E_NOT_OK);\r
+\r
+\r
+ ModuleStatus = MEMIF_BUSY;\r
+ JobResult = MEMIF_JOB_PENDING;\r
+\r
+ CurrentJob.BlockConfigPtr = &Fee_Config.BlockConfig[blockIndex];\r
+ CurrentJob.AdminFlsBlockPtr = &AdminFls.BlockDescrTbl[blockIndex][dataset];\r
+ CurrentJob.BlockNumber = blockNumber;\r
+ CurrentJob.State = FEE_INVALIDATE_REQUESTED;\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_EraseImmediateBlock\r
+ * Reentrant: No\r
+ */\r
+Std_ReturnType Fee_EraseImmediateBlock(uint16 blockNumber)\r
+{\r
+ //lint --e{715} PC-Lint (715) - function is not implemented and thus variable "blockNumber" is not used yet\r
+\r
+ DET_REPORTERROR(MODULE_ID_FEE, 0, FEE_ERASE_IMMEDIATE_ID, FEE_E_NOT_IMPLEMENTED_YET);\r
+\r
+\r
+ return E_NOT_OK;\r
+}\r
+\r
+\r
+/***************************************\r
+ * Scheduled functions *\r
+ ***************************************/\r
+/*\r
+ * Procedure: Fee_MainFunction\r
+ * Reentrant: No\r
+ */\r
+void Fee_MainFunction(void)\r
+{\r
+ static CurrentJobStateType LastState = FEE_UNINITIALIZED;\r
+\r
+ if (CurrentJob.State == LastState) {\r
+ if (CurrentJob.InStateCounter < STATE_COUNTER_MAX) {\r
+ CurrentJob.InStateCounter++;\r
+ }\r
+ } else {\r
+ LastState = CurrentJob.State;\r
+ CurrentJob.InStateCounter = 0;\r
+ }\r
+\r
+ switch (CurrentJob.State) {\r
+ case FEE_UNINITIALIZED:\r
+ break;\r
+\r
+ case FEE_IDLE:\r
+ if (CurrentJob.InStateCounter > GARBAGE_COLLECTION_DELAY) {\r
+ CheckIfGarbageCollectionNeeded();\r
+ }\r
+ break;\r
+\r
+ /*\r
+ * Startup states\r
+ */\r
+ case FEE_STARTUP_REQUESTED:\r
+ StartupStartJob();\r
+ break;\r
+\r
+ case FEE_STARTUP_READ_BANK1_STATUS:\r
+ StartupReadBank1Status();\r
+ break;\r
+\r
+ case FEE_STARTUP_READ_BANK2_STATUS_REQUESTED:\r
+ StartupReadBank2StatusRequested();\r
+ break;\r
+\r
+ case FEE_STARTUP_READ_BANK2_STATUS:\r
+ StartupReadBank2Status();\r
+ break;\r
+\r
+ case FEE_STARTUP_READ_BLOCK_ADMIN_REQUESTED:\r
+ StartupReadBlockAdminRequested();\r
+ break;\r
+\r
+ case FEE_STARTUP_READ_BLOCK_ADMIN:\r
+ StartupReadBlockAdmin();\r
+ break;\r
+\r
+ /*\r
+ * Read states\r
+ */\r
+ case FEE_READ_REQUESTED:\r
+ ReadStartJob();\r
+ break;\r
+\r
+ case FEE_READ:\r
+ Reading();\r
+ break;\r
+\r
+ /*\r
+ * Write states
+ */\r
+ case FEE_WRITE_REQUESTED:\r
+ WriteStartJob();\r
+ break;\r
+\r
+ case FEE_WRITE_MARK_BANK_OLD:\r
+ WriteMarkBankOldState();\r
+ break;\r
+\r
+ case FEE_WRITE_HEADER_REQUESTED:\r
+ WriteHeaderRequested();\r
+ break;\r
+\r
+ case FEE_WRITE_HEADER:\r
+ WriteHeaderState();\r
+ break;\r
+\r
+ case FEE_WRITE_DATA_REQUESTED:\r
+ WriteDataRequested();\r
+ break;\r
+\r
+ case FEE_WRITE_DATA:\r
+ WriteDataState();\r
+ break;\r
+\r
+ case FEE_WRITE_MAGIC_REQUESTED:\r
+ WriteMagicRequested();\r
+ break;\r
+\r
+ case FEE_WRITE_MAGIC:\r
+ WriteMagicState();\r
+ break;\r
+\r
+ /*\r
+ * Garbage collection states
+ */\r
+ case FEE_GARBAGE_COLLECT_REQUESTED:\r
+ GarbageCollectStartJob();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_HEADER_WRITE:\r
+ GarbageCollectWriteHeader();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_DATA_READ_REQUESTED:\r
+ GarbageCollectReadDataRequested();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_DATA_READ:\r
+ GarbageCollectReadData();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_DATA_WRITE_REQUESTED:\r
+ GarbageCollectWriteDataRequested();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_DATA_WRITE:\r
+ GarbageCollectWriteData();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_MAGIC_WRITE_REQUESTED:\r
+ GarbageCollectWriteMagicRequested();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_MAGIC_WRITE:\r
+ GarbageCollectWriteMagic();\r
+ break;\r
+\r
+ case FEE_GARBAGE_COLLECT_ERASE:\r
+ GarbageCollectErase();\r
+ break;\r
+\r
+ /*\r
+ * Invalidate states
+ */\r
+ case FEE_INVALIDATE_REQUESTED:\r
+ InvalidateStartJob();\r
+ break;\r
+\r
+ case FEE_INVALIDATE_MARK_BANK_OLD:\r
+ InvalidateMarkBankOld();\r
+ break;\r
+\r
+ case FEE_WRITE_INVALIDATE_HEADER_REQUESTED:\r
+ InvalidateWriteInvalidateHeaderRequested();\r
+ break;\r
+\r
+ case FEE_WRITE_INVALIDATE_HEADER:\r
+ InvalidateWriteInvalidateHeader();\r
+ break;\r
+\r
+\r
+ /*\r
+ * Other
+ */\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/***************************************\r
+ * Call-back notifications functions *\r
+ ***************************************/\r
+#if (FEE_POLLING_MODE == STD_OFF)\r
+/*\r
+ * Procedure: Fee_JobEndNotification\r
+ * Reentrant: No\r
+ */\r
+void Fee_JobEndNotification(void)\r
+{\r
+ FlsJobReady = TRUE;\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: Fee_JobErrorNotification\r
+ * Reentrant: No\r
+ */\r
+void Fee_JobErrorNotification(void)\r
+{\r
+ FlsJobReady = TRUE;\r
+}\r
+#endif\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+/*\r
+ * General requirements\r
+ */\r
+/** @req NVM076 */\r
+/** @req NVM552 */\r
+/** @req NVM689 */\r
+\r
+\r
+/*\r
+ * NB! Even though some code exist for handling crc, the functionality is not complete\r
+ * and shall not be used.
+ */\r
+\r
+//lint -esym(522,CalcCrc) // 522 PC-Lint exception for empty functions\r
+//lint -emacro(904,VALIDATE_RV,VALIDATE_NO_RV) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
+\r
+// Exception made as a result of that NVM_DATASET_SELECTION_BITS can be zero\r
+//lint -emacro(835, BLOCK_BASE_AND_SET_TO_BLOCKNR) // 835 PC-lint: A zero has been given as right argument to operator '<<' or '>>'\r
+\r
+\r
+\r
+#include "NvM.h"\r
+#include "NvM_Cbk.h"\r
+#include "Rte.h" // ???\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#include "MemIf.h"\r
+//#include "SchM_NvM.h"\r
+#include "MemMap.h"\r
+//#include "Crc.h" // Optional\r
+\r
+/*\r
+ * Local definitions
+ */\r
+#define NVM_SERVICE_ID 0x00 // TODO: What number shall this ID have?\r
+\r
+#if ( NVM_DEV_ERROR_DETECT == STD_ON )\r
+#include "Det.h"\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_NVM, 0, _api, _err); \\r
+ }\r
+\r
+/*\r
+#define VALIDATE_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_NVM, 0, _api, _err); \\r
+ return _rv; \\r
+ }\r
+*/\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_NVM, 0, _api, _err); \\r
+ return; \\r
+ }\r
+#define DET_REPORTERROR(_module,_instance,_api,_err) Det_ReportError(_module,_instance,_api,_err)\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_RV(_exp,_api,_err,_rv )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_module,_instance,_api,_err)\r
+#endif\r
+\r
+#define BLOCK_BASE_AND_SET_TO_BLOCKNR(_blockbase, _set) ((uint16)(_blockbase << NVM_DATASET_SELECTION_BITS) | _set)\r
+\r
+\r
+// State variable\r
+typedef enum {\r
+ NVM_UNINITIALIZED = 0,\r
+ NVM_IDLE,\r
+ NVM_READ_ALL_REQUESTED,\r
+ NVM_READ_ALL_PROCESSING,\r
+ NVM_READ_ALL_PENDING,\r
+ NVM_WRITE_ALL_REQUESTED,\r
+ NVM_WRITE_ALL_PROCESSING,\r
+ NVM_WRITE_ALL_PENDING\r
+} NvmStateType;\r
+\r
+typedef enum {\r
+ BLOCK_STATE_IDLE,\r
+ BLOCK_STATE_RECALC_CRC,\r
+ BLOCK_STATE_RECALC_CRC_DONE,\r
+ BLOCK_STATE_POSTCALC_CRC,\r
+ BLOCK_STATE_POSTCALC_CRC_DONE,\r
+\r
+ BLOCK_STATE_LOAD_FROM_NV,\r
+// BLOCK_STATE_LOAD_FROM_NV_DONE,\r
+// BLOCK_STATE_LOAD_FROM_NV_REDUNDANT,\r
+// BLOCK_STATE_LOAD_FROM_ROM,\r
+\r
+ BLOCK_STATE_WRITE_TO_NV\r
+// BLOCK_STATE_WRITE_TO_NV_DONE\r
+} BlockStateType;\r
+\r
+\r
+static NvmStateType nvmState = NVM_UNINITIALIZED;\r
+\r
+typedef struct {\r
+ BlockStateType BlockState;\r
+ uint8 DataIndex; // Selected data index if "Data Set" type\r
+ boolean BlockWriteProtected; // Block write protected?\r
+ NvM_RequestResultType ErrorStatus; // Status of block\r
+ boolean BlockChanged; // Block changed?\r
+ boolean BlockValid; // Block valid?\r
+ uint8 NumberOfWriteFailed; // Current write retry cycle\r
+} AdministrativeBlockType;\r
+\r
+static AdministrativeBlockType AdminBlock[NVM_NUM_OF_NVRAM_BLOCKS];\r
+\r
+typedef struct {\r
+ NvM_RequestResultType ErrorStatus; // Status from multi block requests i.e. Read/Write/CancelWrite-all\r
+} AdministrativeMultiBlockType;\r
+\r
+static AdministrativeMultiBlockType AdminMultiBlock;\r
+\r
+/*\r
+ * This function needs to be implemented!
+ */\r
+static void CalcCrc(void)\r
+{\r
+ // TODO: Calculate CRC\r
+}\r
+\r
+typedef struct {\r
+ boolean JobFinished;\r
+ Std_ReturnType JobStatus;\r
+ MemIf_JobResultType JobResult;\r
+ const NvM_BlockDescriptorType *BlockDescriptor;\r
+ AdministrativeBlockType *BlockAdmin;\r
+} MemIfJobAdminType;\r
+\r
+static MemIfJobAdminType MemIfJobAdmin = {\r
+ .JobFinished = TRUE,\r
+ .JobStatus = E_OK,\r
+ .JobResult = MEMIF_JOB_OK,\r
+ .BlockDescriptor = NULL,\r
+ .BlockAdmin = NULL\r
+};\r
+\r
+typedef struct {\r
+ uint16 NextBlockIndex; // Keeps track of next unfinished block\r
+ NvM_RequestResultType PendingErrorStatus; // Status from multi block requests i.e. Read/Write/CancelWrite-all\r
+} AdminMultiReqType;\r
+\r
+static AdminMultiReqType AdminMultiReq;\r
+\r
+/*\r
+ * Set the MemIf job as busy
+ */\r
+static void SetMemifJobBusy()\r
+{\r
+ MemIfJobAdmin.JobFinished = FALSE;\r
+}\r
+\r
+\r
+#if (NVM_POLLING_MODE == STD_ON)\r
+/*\r
+ * Check if the MemIf job is finished
+ */\r
+static boolean CheckMemIfJobFinished(void)\r
+{\r
+ MemIf_JobResultType jobResult;\r
+\r
+ if (!MemIfJobAdmin.JobFinished) {\r
+ jobResult = MemIf_GetJobResult();\r
+\r
+ if (jobResult == MEMIF_JOB_OK) {\r
+ MemIfJobAdmin.JobFinished = TRUE;\r
+ MemIfJobAdmin.JobStatus = E_OK;\r
+ MemIfJobAdmin.JobResult = jobResult;\r
+ } else if (jobResult != MEMIF_JOB_PENDING) {\r
+ MemIfJobAdmin.JobFinished = TRUE;\r
+ MemIfJobAdmin.JobStatus = E_NOT_OK;\r
+ MemIfJobAdmin.JobResult = jobResult;\r
+ }\r
+ }\r
+\r
+ return MemIfJobAdmin.JobFinished;\r
+}\r
+#else\r
+/*\r
+ * Check if the MemIf job is finished\r
+ */\r
+static boolean CheckMemIfJobFinished(void)\r
+{\r
+ return MemIfJobAdmin.JobFinished;\r
+}\r
+#endif\r
+\r
+\r
+/*\r
+ * Abort the MemIf job with E_NOT_OK\r
+ */\r
+static void AbortMemIfJob(MemIf_JobResultType jobResult)\r
+{\r
+ MemIfJobAdmin.JobFinished = TRUE;\r
+ MemIfJobAdmin.JobStatus = E_NOT_OK;\r
+ MemIfJobAdmin.JobResult = jobResult;\r
+}\r
+\r
+\r
+/*\r
+ * Request a read of a block from MemIf
+ */\r
+static void ReadBlock(const NvM_BlockDescriptorType *blockDescriptor, AdministrativeBlockType *adminBlock, uint8 setNumber, uint8 *destAddress)\r
+{\r
+ Std_ReturnType returnCode;\r
+ uint16 blockOffset = 0; // TODO: How to calculate this?\r
+\r
+ if (setNumber < blockDescriptor->NvBlockNum) {\r
+ SetMemifJobBusy();\r
+ MemIfJobAdmin.BlockAdmin = adminBlock;\r
+ MemIfJobAdmin.BlockDescriptor = blockDescriptor;\r
+ returnCode = MemIf_Read(blockDescriptor->NvramDeviceId, BLOCK_BASE_AND_SET_TO_BLOCKNR(blockDescriptor->NvBlockBaseNumber, setNumber), blockOffset, destAddress, blockDescriptor->NvBlockLength);\r
+ if (returnCode != E_OK) {\r
+ AbortMemIfJob(MEMIF_JOB_FAILED);\r
+ }\r
+ } else if (setNumber < blockDescriptor->NvBlockNum + blockDescriptor->RomBlockNum) {\r
+ // TODO: Read from ROM\r
+ } else {\r
+ // Error: setNumber out of range\r
+ DET_REPORTERROR(MODULE_ID_NVM, 0, NVM_LOC_READ_BLOCK_ID, NVM_PARAM_OUT_OF_RANGE);\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Initiate the read all job
+ */\r
+static void ReadAllInit(void)\r
+{\r
+ /*\r
+ * Initiate the read all job
+ */\r
+ const NvM_BlockDescriptorType *BlockDescriptorList = NvM_Config.BlockDescriptor;\r
+ AdministrativeBlockType *AdminBlockTable = AdminBlock;\r
+ uint16 i;\r
+\r
+ nvmState = NVM_READ_ALL_PROCESSING;\r
+ AdminMultiReq.PendingErrorStatus = NVM_REQ_OK;\r
+ AdminMultiReq.NextBlockIndex = 0;\r
+\r
+ for (i = 0; i < NVM_NUM_OF_NVRAM_BLOCKS; i++) {\r
+ if ((BlockDescriptorList->SelectBlockForReadall)\r
+#if (NVM_SET_RAM_BLOCK_STATUS_API == STD_ON) /** @req NVM345 */\r
+ && ((!AdminBlockTable->BlockValid) // TODO: Check if this is to be done like this\r
+ || (!AdminBlockTable->BlockChanged)) // TODO: Check if this is to be done like this\r
+#endif\r
+ ) {\r
+ VALIDATE_NO_RV(BlockDescriptorList->RamBlockDataAddress != NULL, NVM_READ_ALL_ID, NVM_E_WRONG_CONFIG);\r
+ VALIDATE_NO_RV(BlockDescriptorList->BlockManagementType != NVM_BLOCK_DATASET, NVM_READ_ALL_ID, NVM_E_WRONG_CONFIG);\r
+ if (BlockDescriptorList->CalcRamBlockCrc) {\r
+ VALIDATE(BlockDescriptorList->BlockUseCrc == STD_ON, NVM_READ_ALL_ID, NVM_E_BLOCK_CONFIG);\r
+ AdminBlockTable->BlockState = BLOCK_STATE_RECALC_CRC;\r
+ } else {\r
+ AdminBlockTable->BlockState = BLOCK_STATE_LOAD_FROM_NV;\r
+ }\r
+ } else {\r
+ AdminBlockTable->ErrorStatus = NVM_REQ_BLOCK_SKIPPED;\r
+ }\r
+\r
+ AdminBlockTable++;\r
+ BlockDescriptorList++;\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Main function for the read all job
+ */\r
+static void ReadAllMain(void)\r
+{\r
+ const NvM_BlockDescriptorType *BlockDescriptorList = NvM_Config.BlockDescriptor;\r
+ AdministrativeBlockType *AdminBlockTable = AdminBlock;\r
+ uint16 i;\r
+\r
+ // Search forward to first unfinished block\r
+ while ((AdminMultiReq.NextBlockIndex < NVM_NUM_OF_NVRAM_BLOCKS) && (AdminBlockTable[AdminMultiReq.NextBlockIndex].ErrorStatus != NVM_REQ_PENDING)) {\r
+ AdminMultiReq.NextBlockIndex++;\r
+ }\r
+\r
+ if (AdminMultiReq.NextBlockIndex == NVM_NUM_OF_NVRAM_BLOCKS) {\r
+ // All block processed\r
+ if (AdminMultiReq.PendingErrorStatus == NVM_REQ_OK) {\r
+ AdminMultiBlock.ErrorStatus = NVM_REQ_OK;\r
+ } else {\r
+ AdminMultiBlock.ErrorStatus = NVM_REQ_NOT_OK;\r
+ }\r
+\r
+ nvmState = NVM_IDLE;\r
+\r
+ if (NvM_Config.Common.MultiBlockCallback != NULL) {\r
+ NvM_Config.Common.MultiBlockCallback(NVM_SERVICE_ID, AdminMultiBlock.ErrorStatus);\r
+ }\r
+\r
+ } else {\r
+ for (i = AdminMultiReq.NextBlockIndex; (i < NVM_NUM_OF_NVRAM_BLOCKS) && (nvmState == NVM_READ_ALL_PROCESSING); i++) {\r
+ switch (AdminBlockTable[i].BlockState) {\r
+ case BLOCK_STATE_POSTCALC_CRC_DONE:\r
+ // TODO: Check CRC\r
+ break;\r
+\r
+ case BLOCK_STATE_RECALC_CRC_DONE:\r
+ // TODO: If CRC is ok do not reload from NVRAM\r
+ // TODO: else reload\r
+ break;\r
+\r
+ case BLOCK_STATE_LOAD_FROM_NV:\r
+ nvmState = NVM_READ_ALL_PENDING;\r
+ ReadBlock(&BlockDescriptorList[i], &AdminBlockTable[i], 0, BlockDescriptorList[i].RamBlockDataAddress);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ } // Switch\r
+ } // for\r
+ } // else\r
+}\r
+\r
+\r
+/*\r
+ * Handles the MemIf result of one block read
+ */\r
+static void ReadAllCheckReadResult(void)\r
+{\r
+ if (MemIfJobAdmin.JobStatus == E_OK) {\r
+ if (MemIfJobAdmin.BlockDescriptor->BlockUseCrc) {\r
+ MemIfJobAdmin.BlockAdmin->BlockState = BLOCK_STATE_POSTCALC_CRC; /** @req NVM292 */\r
+ } else {\r
+ MemIfJobAdmin.BlockAdmin->BlockState = BLOCK_STATE_IDLE;\r
+ MemIfJobAdmin.BlockAdmin->ErrorStatus = NVM_REQ_OK;\r
+ MemIfJobAdmin.BlockAdmin->BlockValid = TRUE;\r
+ MemIfJobAdmin.BlockAdmin->BlockChanged = FALSE;\r
+\r
+ if (MemIfJobAdmin.BlockDescriptor->WriteBlockOnce) {\r
+ MemIfJobAdmin.BlockAdmin->BlockWriteProtected = TRUE;\r
+ }\r
+\r
+ if (MemIfJobAdmin.BlockDescriptor->SingleBlockCallback != NULL) {\r
+ (void)MemIfJobAdmin.BlockDescriptor->SingleBlockCallback(NVM_SERVICE_ID, MemIfJobAdmin.BlockAdmin->ErrorStatus); /** @req NVM281 */\r
+ }\r
+ }\r
+ } else {\r
+ // TODO: Handle reread from NVRAM if type NVM_BLOCK_REDUNDANT\r
+ // TODO: Handle read from ROM if available\r
+\r
+ // Read has failed\r
+ AdminMultiReq.PendingErrorStatus = NVM_REQ_NOT_OK;\r
+\r
+ MemIfJobAdmin.BlockAdmin->BlockState = BLOCK_STATE_IDLE;\r
+ MemIfJobAdmin.BlockAdmin->BlockValid = FALSE;\r
+ MemIfJobAdmin.BlockAdmin->BlockChanged = FALSE;\r
+\r
+ switch (MemIfJobAdmin.JobResult ) {\r
+ case MEMIF_BLOCK_INVALID:\r
+ MemIfJobAdmin.BlockAdmin->ErrorStatus = NVM_REQ_NV_INVALIDATED; /** @req NVM342 */\r
+ break;\r
+\r
+ case MEMIF_BLOCK_INCONSISTENT: /** @req NVM360 */\r
+ MemIfJobAdmin.BlockAdmin->ErrorStatus = NVM_REQ_INTEGRITY_FAILED;\r
+#if defined(USE_DEM)\r
+ Dem_ReportErrorStatus(NVM_E_INTEGRITY_FAILED,DEM_EVENT_STATUS_FAILED);\r
+#endif\r
+ break;\r
+\r
+ case MEMIF_JOB_FAILED: /** @req NVM361 */\r
+ MemIfJobAdmin.BlockAdmin->ErrorStatus = NVM_REQ_NOT_OK;\r
+#if defined(USE_DEM)\r
+ Dem_ReportErrorStatus(NVM_E_REQ_FAILED,DEM_EVENT_STATUS_FAILED);\r
+#endif\r
+ break;\r
+\r
+ default:\r
+ MemIfJobAdmin.BlockAdmin->ErrorStatus = NVM_REQ_NOT_OK;\r
+ break;\r
+ }\r
+\r
+ if (MemIfJobAdmin.BlockDescriptor->SingleBlockCallback != NULL) {\r
+ (void)MemIfJobAdmin.BlockDescriptor->SingleBlockCallback(NVM_SERVICE_ID, MemIfJobAdmin.BlockAdmin->ErrorStatus); /** @req NVM281 */\r
+ }\r
+ }\r
+ nvmState = NVM_READ_ALL_PROCESSING;\r
+}\r
+\r
+\r
+/*\r
+ * Request writing of a block to MemIf
+ */\r
+static void WriteBlock(const NvM_BlockDescriptorType *blockDescriptor, AdministrativeBlockType *adminBlock, uint8 setNumber, uint8 *sourceAddress)\r
+{\r
+ Std_ReturnType returnCode;\r
+\r
+ if (setNumber < blockDescriptor->NvBlockNum) {\r
+ SetMemifJobBusy();\r
+ MemIfJobAdmin.BlockAdmin = adminBlock;\r
+ MemIfJobAdmin.BlockDescriptor = blockDescriptor;\r
+ returnCode = MemIf_Write(blockDescriptor->NvramDeviceId, BLOCK_BASE_AND_SET_TO_BLOCKNR(blockDescriptor->NvBlockBaseNumber, setNumber), sourceAddress);\r
+ if (returnCode != E_OK) {\r
+ AbortMemIfJob(MEMIF_JOB_FAILED);\r
+ }\r
+ } else {\r
+ // Error: setNumber out of range\r
+ DET_REPORTERROR(MODULE_ID_NVM, 0, NVM_LOC_WRITE_BLOCK_ID, NVM_PARAM_OUT_OF_RANGE);\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Initiate the write all job\r
+ */\r
+static void WriteAllInit(void)\r
+{\r
+ const NvM_BlockDescriptorType *BlockDescriptorList = NvM_Config.BlockDescriptor;\r
+ AdministrativeBlockType *AdminBlockTable = AdminBlock;\r
+ uint16 i;\r
+\r
+ nvmState = NVM_WRITE_ALL_PROCESSING;\r
+ AdminMultiReq.PendingErrorStatus = NVM_REQ_OK;\r
+ AdminMultiReq.NextBlockIndex = 0;\r
+\r
+ for (i = 0; i < NVM_NUM_OF_NVRAM_BLOCKS; i++) {\r
+ if ((BlockDescriptorList->RamBlockDataAddress != NULL)\r
+#if (NVM_SET_RAM_BLOCK_STATUS_API == STD_ON) /** @req NVM344 */\r
+ && (AdminBlockTable->BlockValid) /** @req NVM682 */\r
+ && (AdminBlockTable->BlockChanged) /** @req NVM682 */\r
+#endif\r
+ && (!AdminBlockTable->BlockWriteProtected)){ /** @req NVM432 *//** @req NVM433 */\r
+ if (BlockDescriptorList->BlockUseCrc) {\r
+ AdminBlockTable->BlockState = BLOCK_STATE_RECALC_CRC; /** @req NVM253 */\r
+ } else {\r
+ AdminBlockTable->BlockState = BLOCK_STATE_WRITE_TO_NV;\r
+ AdminBlockTable->NumberOfWriteFailed = 0;\r
+ }\r
+ } else {\r
+ AdminBlockTable->ErrorStatus = NVM_REQ_BLOCK_SKIPPED; /** @req NVM298 */\r
+ }\r
+\r
+ AdminBlockTable++;\r
+ BlockDescriptorList++;\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Main function for the write all job\r
+ */\r
+static void WriteAllMain(void)\r
+{\r
+ const NvM_BlockDescriptorType *BlockDescriptorList = NvM_Config.BlockDescriptor;\r
+ AdministrativeBlockType *AdminBlockTable = AdminBlock;\r
+ uint16 i;\r
+\r
+ // Search forward to first unfinished block\r
+ while ((AdminMultiReq.NextBlockIndex < NVM_NUM_OF_NVRAM_BLOCKS) && (AdminBlockTable[AdminMultiReq.NextBlockIndex].ErrorStatus != NVM_REQ_PENDING)) {\r
+ AdminMultiReq.NextBlockIndex++;\r
+ }\r
+\r
+ if (AdminMultiReq.NextBlockIndex == NVM_NUM_OF_NVRAM_BLOCKS) {\r
+ // All block processed\r
+ if (AdminMultiReq.PendingErrorStatus == NVM_REQ_OK) {\r
+ AdminMultiBlock.ErrorStatus = NVM_REQ_OK;\r
+ } else {\r
+ AdminMultiBlock.ErrorStatus = NVM_REQ_NOT_OK;\r
+ }\r
+\r
+ nvmState = NVM_IDLE;\r
+\r
+ if (NvM_Config.Common.MultiBlockCallback != NULL) {\r
+ NvM_Config.Common.MultiBlockCallback(NVM_SERVICE_ID, AdminMultiBlock.ErrorStatus);\r
+ }\r
+\r
+ } else {\r
+ for (i = AdminMultiReq.NextBlockIndex; (i < NVM_NUM_OF_NVRAM_BLOCKS) && (nvmState == NVM_WRITE_ALL_PROCESSING); i++) {\r
+ switch (AdminBlockTable[i].BlockState) {\r
+ case BLOCK_STATE_POSTCALC_CRC_DONE:\r
+ // TODO: Check CRC\r
+ break;\r
+\r
+ case BLOCK_STATE_RECALC_CRC_DONE:\r
+ // TODO: If CRC is ok do not reload from NVRAM\r
+ // TODO: else reload\r
+ break;\r
+\r
+ case BLOCK_STATE_WRITE_TO_NV:\r
+ nvmState = NVM_WRITE_ALL_PENDING;\r
+ WriteBlock(&BlockDescriptorList[i], &AdminBlockTable[i], 0, BlockDescriptorList[i].RamBlockDataAddress);\r
+ break;\r
+\r
+ default:\r
+ break;\r
+ } // Switch\r
+ } // for\r
+ } // else\r
+}\r
+\r
+\r
+/*\r
+ * Handles the result of one MemIf block write\r
+ */\r
+static void WriteAllCheckWriteResult(void)\r
+{\r
+ if (MemIfJobAdmin.JobStatus == E_OK) {\r
+ // TODO: Check if redundant block shall be written NVM337\r
+\r
+ if (MemIfJobAdmin.BlockDescriptor->WriteBlockOnce) {\r
+ MemIfJobAdmin.BlockAdmin->BlockWriteProtected = TRUE; /** @req NVM329 */\r
+ }\r
+ MemIfJobAdmin.BlockAdmin->BlockState = BLOCK_STATE_IDLE;\r
+ MemIfJobAdmin.BlockAdmin->ErrorStatus = NVM_REQ_OK;\r
+\r
+ if (MemIfJobAdmin.BlockDescriptor->SingleBlockCallback != NULL) {\r
+ (void)MemIfJobAdmin.BlockDescriptor->SingleBlockCallback(NVM_SERVICE_ID, MemIfJobAdmin.BlockAdmin->ErrorStatus);\r
+ }\r
+ } else {\r
+ MemIfJobAdmin.BlockAdmin->NumberOfWriteFailed++;\r
+ if (MemIfJobAdmin.BlockAdmin->NumberOfWriteFailed > NVM_MAX_NUMBER_OF_WRITE_RETRIES) {\r
+ // TODO: Check if redundant block shall be written NVM337\r
+\r
+ // Write has failed\r
+ AdminMultiReq.PendingErrorStatus = NVM_REQ_NOT_OK;\r
+\r
+ MemIfJobAdmin.BlockAdmin->BlockState = BLOCK_STATE_IDLE;\r
+ MemIfJobAdmin.BlockAdmin->ErrorStatus = NVM_REQ_NOT_OK; /** @req NVM296 */\r
+#if defined(USE_DEM)\r
+ Dem_ReportErrorStatus(NVM_E_REQ_FAILED,DEM_EVENT_STATUS_FAILED);\r
+#endif\r
+\r
+ if (MemIfJobAdmin.BlockDescriptor->SingleBlockCallback != NULL) {\r
+ (void)MemIfJobAdmin.BlockDescriptor->SingleBlockCallback(NVM_SERVICE_ID, MemIfJobAdmin.BlockAdmin->ErrorStatus);\r
+ }\r
+ }\r
+ }\r
+ nvmState = NVM_WRITE_ALL_PROCESSING;\r
+}\r
+\r
+\r
+/***************************************\r
+ * External accessible functions *\r
+ ***************************************/\r
+/*\r
+ * Procedure: NvM_Init\r
+ * Reentrant: No\r
+ */\r
+void NvM_Init(void)\r
+{\r
+ /** @req NVM399 *//** @req NVM193 */\r
+ const NvM_BlockDescriptorType *BlockDescriptorList = NvM_Config.BlockDescriptor;\r
+ AdministrativeBlockType *AdminBlockTable = AdminBlock;\r
+ uint16 i;\r
+\r
+ // Initiate the administration blocks\r
+ for (i = 0; i< NVM_NUM_OF_NVRAM_BLOCKS; i++) {\r
+ if (BlockDescriptorList->BlockManagementType == NVM_BLOCK_DATASET) {\r
+ AdminBlockTable->DataIndex = 0; /** @req NVM192 */\r
+ }\r
+ AdminBlockTable->BlockWriteProtected = BlockDescriptorList->BlockWriteProt;\r
+ AdminBlockTable->ErrorStatus = NVM_REQ_NOT_OK;\r
+ AdminBlockTable->BlockChanged = FALSE;\r
+ AdminBlockTable->BlockValid = FALSE;\r
+ AdminBlockTable->NumberOfWriteFailed = 0;\r
+\r
+ AdminBlockTable++;\r
+ BlockDescriptorList++;\r
+ }\r
+\r
+ AdminMultiBlock.ErrorStatus = NVM_REQ_NOT_OK;\r
+\r
+ // Set status to initialized\r
+ nvmState = NVM_IDLE; /** @req NVM399 */\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: NvM_ReadAll\r
+ * Reentrant: No\r
+ */\r
+void NvM_ReadAll(void)\r
+{\r
+ AdministrativeBlockType *AdminBlockTable = AdminBlock;\r
+ uint16 i;\r
+\r
+ VALIDATE_NO_RV(nvmState != NVM_UNINITIALIZED, NVM_READ_ALL_ID, NVM_E_NOT_INITIALIZED);\r
+ // Check queue\r
+ // TODO: Check queue\r
+\r
+ // Check state\r
+ if (nvmState == NVM_IDLE) {\r
+ nvmState = NVM_READ_ALL_REQUESTED; /** @req NVM243 */\r
+\r
+ // Set status to pending in the administration blocks\r
+ AdminMultiBlock.ErrorStatus = NVM_REQ_PENDING;\r
+\r
+ for (i = 0; i < NVM_NUM_OF_NVRAM_BLOCKS; i++) {\r
+ AdminBlockTable->ErrorStatus = NVM_REQ_PENDING;\r
+ AdminBlockTable++;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: NvM_WriteAll\r
+ * Reentrant: No\r
+ */\r
+void NvM_WriteAll(void)\r
+{\r
+ AdministrativeBlockType *AdminBlockTable = AdminBlock;\r
+ uint16 i;\r
+\r
+ VALIDATE_NO_RV(nvmState != NVM_UNINITIALIZED, NVM_READ_ALL_ID, NVM_E_NOT_INITIALIZED);\r
+ // Check queue\r
+ // TODO: Check queue\r
+\r
+ // Check state\r
+ if (nvmState == NVM_IDLE) {\r
+ nvmState = NVM_WRITE_ALL_REQUESTED; /** @req NVM254 */\r
+\r
+ // Set status to pending in the administration blocks\r
+ AdminMultiBlock.ErrorStatus = NVM_REQ_PENDING;\r
+\r
+ for (i = 0; i < NVM_NUM_OF_NVRAM_BLOCKS; i++) {\r
+ AdminBlockTable->ErrorStatus = NVM_REQ_PENDING; /** @req NVM549 */\r
+ AdminBlockTable++;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*\r
+ * Procedure: NvM_CancelWriteAll\r
+ * Reentrant: No\r
+ */\r
+void NvM_CancelWriteAll(void)\r
+{\r
+ \r
+}\r
+\r
+\r
+/*\r
+ * Procedure: NvM_GetErrorStatus\r
+ * Reentrant: Yes\r
+ */\r
+void NvM_GetErrorStatus(NvM_BlockIdType blockId, uint8 *requestResultPtr)\r
+{\r
+ VALIDATE_NO_RV(nvmState != NVM_UNINITIALIZED, NVM_GET_ERROR_STATUS_ID, NVM_E_NOT_INITIALIZED);\r
+ VALIDATE_NO_RV(blockId < NVM_NUM_OF_NVRAM_BLOCKS+1, NVM_GET_ERROR_STATUS_ID, NVM_E_PARAM_BLOCK_ID);\r
+\r
+ if (blockId == 0) {\r
+ // Multiblock ID\r
+ *requestResultPtr = AdminMultiBlock.ErrorStatus;\r
+ } else {\r
+ *requestResultPtr = AdminBlock[blockId-1].ErrorStatus;\r
+ }\r
+\r
+}\r
+\r
+\r
+#if (NVM_SET_RAM_BLOCK_STATUS_API == STD_ON) /** @req NVM408 */\r
+/*\r
+ * Procedure: Nvm_SetRamBlockStatus\r
+ * Reentrant: Yes\r
+ */\r
+void Nvm_SetRamBlockStatus(NvM_BlockIdType blockId, boolean blockChanged)\r
+{\r
+ const NvM_BlockDescriptorType *BlockDescriptorList = NvM_Config.BlockDescriptor;\r
+\r
+ VALIDATE_NO_RV(nvmState != NVM_UNINITIALIZED, NVM_SET_RAM_BLOCK_STATUS_ID, NVM_E_NOT_INITIALIZED); /** @req NVM497 */\r
+ VALIDATE_NO_RV(blockId < NVM_NUM_OF_NVRAM_BLOCKS+1, NVM_SET_RAM_BLOCK_STATUS_ID, NVM_E_PARAM_BLOCK_ID);\r
+ VALIDATE_NO_RV(blockId > 1, NVM_SET_RAM_BLOCK_STATUS_ID, NVM_E_PARAM_BLOCK_ID);\r
+\r
+ if (BlockDescriptorList[blockId-1].RamBlockDataAddress != NULL) { /** @req NVM240 */\r
+ if (blockChanged) {\r
+ AdminBlock[blockId-1].BlockChanged = TRUE; /** @req NVM406 */\r
+ AdminBlock[blockId-1].BlockValid = TRUE; /** @req NVM241 */\r
+ if (BlockDescriptorList[blockId-1].BlockUseCrc) {\r
+ AdminBlock[blockId-1].BlockState = BLOCK_STATE_RECALC_CRC; /** @req NVM121 */\r
+ }\r
+ } else {\r
+ AdminBlock[blockId-1].BlockChanged = FALSE; /** @req NVM405 */\r
+ AdminBlock[blockId-1].BlockValid = FALSE;\r
+ } // else blockChanged\r
+ } // if permanent block\r
+}\r
+#endif\r
+\r
+\r
+/***************************************\r
+ * Scheduled functions *\r
+ ***************************************/\r
+/*\r
+ * Procedure: NvM_MainFunction\r
+ * Reentrant: No\r
+ */\r
+void NvM_MainFunction(void)\r
+{\r
+ switch (nvmState) {\r
+ case NVM_UNINITIALIZED:\r
+ break;\r
+\r
+ case NVM_IDLE:\r
+ CalcCrc();\r
+ break;\r
+\r
+ case NVM_READ_ALL_REQUESTED:\r
+ ReadAllInit();\r
+ break;\r
+\r
+ case NVM_READ_ALL_PROCESSING:\r
+ if (MemIf_GetStatus() == MEMIF_IDLE) {\r
+ ReadAllMain();\r
+ }\r
+ CalcCrc();\r
+ break;\r
+\r
+ case NVM_READ_ALL_PENDING:\r
+ if (CheckMemIfJobFinished()) {\r
+ ReadAllCheckReadResult();\r
+ }\r
+ CalcCrc();\r
+ break;\r
+\r
+ case NVM_WRITE_ALL_REQUESTED:\r
+ WriteAllInit();\r
+ break;\r
+\r
+ case NVM_WRITE_ALL_PROCESSING:\r
+ if (MemIf_GetStatus() == MEMIF_IDLE) {\r
+ WriteAllMain();\r
+ }\r
+ CalcCrc();\r
+ break;\r
+\r
+ case NVM_WRITE_ALL_PENDING:\r
+ if (CheckMemIfJobFinished()) {\r
+ WriteAllCheckWriteResult();\r
+ }\r
+ CalcCrc();\r
+ break;\r
+\r
+ default:\r
+ DET_REPORTERROR(MODULE_ID_NVM, 0, NVM_MAIN_FUNCTION_ID, NVM_UNEXPECTED_STATE);\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/***************************************\r
+ * Call-back notifications functions *\r
+ ***************************************/\r
+#if (NVM_POLLING_MODE == STD_OFF)\r
+/*\r
+ * Procedure: NvM_JobEndNotification\r
+ * Reentrant: No\r
+ */\r
+void NvM_JobEndNotification(void)\r
+{\r
+ MemIfJobAdmin.JobFinished = TRUE;\r
+ MemIfJobAdmin.JobStatus = E_OK;\r
+ MemIfJobAdmin.JobResult = MemIf_GetJobResult();\r
+}\r
+\r
+/*\r
+ * Procedure: NvM_JobErrorNotification\r
+ * Reentrant: No\r
+ */\r
+void NvM_JobErrorNotification(void)\r
+{\r
+ MemIfJobAdmin.JobFinished = TRUE;\r
+ MemIfJobAdmin.JobStatus = E_NOT_OK;\r
+ MemIfJobAdmin.JobResult = MemIf_GetJobResult();\r
+}\r
+#endif\r
+\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef NVM_H_\r
-#define NVM_H_\r
-\r
-#include "NvM_Cfg.h"\r
-\r
-void NvM_Init( void );\r
-void NvM_ReadAll( void );\r
-void NvM_WriteAll( void );\r
-void NvM_CancelWriteAll( void );\r
-\r
-#endif /*NVM_H_*/\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef NVM_TYPES_H_\r
-#define NVM_TYPES_H_\r
-\r
-#include "Std_Types.h"\r
-\r
-typedef uint8 NvM_RequestResultType;\r
-\r
-typedef uint16 NvM_BlockIdType;\r
-\r
-void NvM_Init( void );\r
-void NvM_SetDataIndex( NvM_BlockIdType BlockId, uint8 DataIndex );\r
-void NvM_GetDataIndex( NvM_BlockIdType BlockId,uint8 *DataIndexPtr );\r
-void NvM_SetBlockProtection( NvM_BlockIdType BlockId, boolean ProtectionEnabled );\r
-void NvM_GetErrorStatus( NvM_BlockIdType BlockId, uint8 *RequestResultPtr );\r
-void NvM_GetVersionInfo( Std_VersionInfoType *VersionInfo );\r
-void Nvm_SetRamBlockStatus( NvM_BlockIdType BlockId, boolean BlockChanged );\r
-void Nvm_ReadBlock( NvM_BlockIdType BlockId, uint8 *NvM_DstPtr );\r
-void NvM_WriteBlock( NvM_BlockIdType BlockId, const uint8 *NvM_SrcPtr );\r
-void Nvm_RestoreBlockDefaults( NvM_BlockIdType BlockId, uint8 *NvM_DstPtr );\r
-void NvM_EraseNvBlock( NvM_BlockIdType BlockId );\r
-void NvM_CancelWriteAll( void );\r
-void NvM_InvalidateNvBlock( NvM_BlockIdType BlockId );\r
-void NvM_ReadAll( void );\r
-void NvM_WriteAll( void );\r
-\r
-#endif /*NVM_TYPES_H_*/\r
\r
-OsTick\r
-\r
- GENERATED\r
- OsTickType OsTickFreq = 1000;\r
-\r
- \r
- SYSTICK SETUP\r
- {\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
- Os_SysTickInit();\r
- Os_SysTickStart(sys_freq/OsTickFreq);\r
- }\r
-\r
-USE CASE\r
- I want to setup a 4ms alarm?\r
- \r
- \r
+Arctic Core - the open source AUTOSAR embedded platform\r
+\r
+\r
+For information on getting started with Arctic Core, please take a look at: \r
+ http://arccore.com/wiki/Quick-start_Tutorial\r
+\r
+For more general information and help, browse the wiki at:\r
+ http://arccore.com/wiki/\r
+\r
+or post a question in the forum:\r
+ https://arccore.com/forum/\r
\r
\r
\r
source ${SCRIPT_DIR}/guess_cc.sh
export BDIR=examples/tiny
-make BOARDDIR=et_stm32_stamp clean
-make BOARDDIR=et_stm32_stamp all
+make BOARDDIR=stm32_stm3210c clean
+make BOARDDIR=stm32_stm3210c all
if [ $? -ne 0 ]; then quit 1
fi
-export BDIR=system/kernel/testsystem
-make BOARDDIR=et_stm32_stamp clean
-make BOARDDIR=et_stm32_stamp all
+export BDIR=examples/simple
+make BOARDDIR=stm32_stm3210c clean
+make BOARDDIR=stm32_stm3210c all
if [ $? -ne 0 ]; then quit 1
fi
+
+# Problems memory..
+#export BDIR=system/kernel/testsystem/suite_01,system/kernel/testsystem/suite_02, system/kernel/testsystem/suite_03
+#make BOARDDIR=stm32_stm3210c clean
+#make BOARDDIR=stm32_stm3210c all
+#if [ $? -ne 0 ]; then quit 1
+#fi
+
+
#
# build_ppc
#
+# This script file is quite braindead... remake when time..
+
function quit {
echo
SCRIPT_DIR=`dirname $0`
ARCH=PPC
source ${SCRIPT_DIR}/guess_cc.sh
-
-export BDIR=system/kernel/testsystem
+
+export BDIR=system/kernel/testsystem/suite_01,system/kernel/testsystem/suite_02,,system/kernel/testsystem/suite_03
make BOARDDIR=mpc5554sim clean
make BOARDDIR=mpc5554sim all
if [ $? -ne 0 ]; then quit 1
if [ $? -ne 0 ]; then quit 1
fi
-export BDIR=system/kernel/testsystem,examples/blinker_node
+export examples/blinker_node
make BOARDDIR=mpc5567qrtech clean
make BOARDDIR=mpc5567qrtech all
if [ $? -ne 0 ]; then quit 1
fi
+
+# Build the examples...
+
+export BDIR=examples/blinker_node
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/pwm_node
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/pwm_node2
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/simple
+make BOARDDIR=mpc551xsim clean
+make BOARDDIR=mpc551xsim all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/switch_node
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/tiny
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+
+
+
+
+
+
+
\r
# Warnings\r
cflags-y += -Wall\r
-cflags-y += -Winline # warn if inline failed\r
+#cflags-y += -Winline # warn if inline failed\r
#cflags-y += -pedantic\r
\r
# Conformance\r
# It seems some versions of make want "\=" and some "="\r
# "=" - msys cpmake on windows 7 \r
gcc_lib_path := "$(subst /libgcc.a,,$(shell $(CC) $(CFLAGS) --print-libgcc-file-name))" \r
+gcc_lib_path := $(subst \libgcc.a,,$(gcc_lib_path)) \r
lib_lib_path := "$(subst /libc.a,,$(shell $(CC) $(CFLAGS) --print-file-name=libc.a))"\r
+lib_lib_path := $(subst \libc.a,,$(lib_lib_path))\r
+text_chunk := $(subst \,/,$(shell touch i_m_here.c; $(CC) -v -c i_m_here.c &> i_m_here.txt;gawk -f $(TOPDIR)/scripts/gcc_getinclude.awk i_m_here.txt))\r
+cc_inc_path := $(realpath $(text_chunk))\r
libpath-y += -L$(lib_lib_path)\r
libpath-y += -L$(gcc_lib_path)\r
\r
--- /dev/null
+\r
+lintdef_ext=-d\r
+lintinc_ext=-i\r
+\r
+lint_extra=+v -b -i$(TOPDIR)/scripts/pclint -i$(TOPDIR)/scripts/pclint/lnt std.lnt\r
+inc-y += $(cc_inc_path)\r
+#lint_files=$(TOPDIR)/scripts/lint/std.lnt\r
+#lint_files=$(TOPDIR)/scripts/lint/lnt/au-misra2.lnt\r
+#lint_files+=$(TOPDIR)/scripts/lint/lnt/au-misra2.lnt\r
+\r
+#$(addprefix -i,$(abs-inc-y)) /C/lint/std.lnt $(abspath $<))\r
--- /dev/null
+\r
+lintdef_ext=-D\r
+lintinc_ext=-I\r
+\r
+#splint_extra=+v -b -i$(TOPDIR)/scripts/pclint -i$(TOPDIR)/scripts/pclint/lnt std.lnt\r
+splint_extra=+nolib\r
+inc-y += $(cc_inc_path)\r
+#lint_files=$(TOPDIR)/scripts/lint/std.lnt\r
+#lint_files=$(TOPDIR)/scripts/lint/lnt/au-misra2.lnt\r
+#lint_files+=$(TOPDIR)/scripts/lint/lnt/au-misra2.lnt\r
+\r
+#$(addprefix -i,$(abs-inc-y)) /C/lint/std.lnt $(abspath $<))\r
--- /dev/null
+#!/bin/bash
+
+ARC_DIR=../
+EXAMPLE_DIR=${ARC_DIR}/examples/
+COMPILER_DIR=/opt/compilers/
+OUTPUT=test_output.xml
+BUILDOUTTMP=tmp_out.txt
+
+
+function failedTest {
+echo "<FailedTest id=\"${1}\"> \
+ <Name>${2}</Name> \
+ <Message>${3}</Message> \
+</FailedTest>" >> $OUTPUT
+
+# echo "<Location>"
+# echo "<File>c:/ArcticStudio/workspace/arc-tests/ComTests/com_test.c</File>"
+# echo "<Line>444</Line>"
+# echo "</Location>"
+# echo "<Message>UPNotificationCalled == getNumberOfSignalsInPdu(IPduId) && 0</Message>"
+}
+
+function successfulTest {
+echo "<Test id=\"${1}\"> \
+ <Name>${2}</Name> \
+</Test>" >> $OUTPUT
+}
+
+function warningTest {
+echo "<Test id=\"${1}\"> \
+ <Name>${2}</Name> \
+ <Warning>${3}</Warning>
+</Test>" >> $OUTPUT
+}
+
+
+
+
+echo "<?xml version=\"1.0\" encoding='utf8' standalone='yes' ?> \
+<?xml-stylesheet type=\"text/xsl\" href=\"unittests.xsl\" ?> \
+<TestRuns> \
+<TestRun> \
+<CompileExamples>" > $OUTPUT
+
+TEST_ID=1
+for EXAMPLE in `ls $EXAMPLE_DIR`; do
+ for BOARD in `ls ${EXAMPLE_DIR}${EXAMPLE}/config`; do
+
+ C=`grep $BOARD compilers.txt`
+ COMPILER=${COMPILER_DIR}${C#$BOARD:}
+
+ TEST_NAME=${EXAMPLE}-${BOARD}
+
+ if [ -x "${COMPILER}gcc" ]; then
+ BUILD_FILE=${EXAMPLE}_${BOARD}.elf
+ make -C ${ARC_DIR} CROSS_COMPILE=$COMPILER BOARDDIR=$BOARD BDIR=examples/$EXAMPLE build-exe-y=${BUILD_FILE} clean all
+
+ if [ -a ${ARC_DIR}/binaries/${BUILD_FILE} ]; then
+ successfulTest $TEST_ID $TEST_NAME
+ else
+ BUILDOUT=`cat $BUILDOUTTMP`
+ failedTest $TEST_ID $TEST_NAME "See console output for information"
+ fi
+ else
+ warningTest $TEST_ID $TEST_NAME "No compiler found"
+ fi
+ let TEST_ID=TEST_ID+1
+ done
+done
+
+echo "</CompileExamples> \
+</TestRun> \
+</TestRuns>" >> $OUTPUT
+
--- /dev/null
+ti_tms570ls:arm-none-eabi/bin/arm-none-eabi-
+stm32_mcbstm32:arm-none-eabi/bin/arm-none-eabi-
+stm32_stm3210c:arm-none-eabi/bin/arm-none-eabi-
+mpc5516it:powerpc-eabispe/bin/powerpc-eabispe-
+mpc5567qrtech:powerpc-eabispe/bin/powerpc-eabispe-
+mpc551xsim:powerpc-eabispe/bin/powerpc-eabispe-
+mpc5554sim:powerpc-eabispe/bin/powerpc-eabispe-
+hcs12_elmicro_card12:m6811-elf/bin/m6811-elf-
+hcs12x_elmicro_tboard:m6811-elf/bin/m6811-elf-
+linux:
--- /dev/null
+#\r
+# Get include dirs from:\r
+# touch apa.c \r
+# gcc -v -c apa.c\r
+#\r
+# "#include <...> search starts here:" to "End of search list."\r
+#\r
+\r
+/#include <...> search starts here:/,/End of search list/ {\r
+\r
+ if (!(($1=="#include")||($1=="End")))\r
+ print $0\r
+}\r
+\r
+\r
+\r
--- /dev/null
+-ss2
+-si4
+-sl4
+-sll8
+-sf4
+-sd8
+-sld8
+-sp4
+
--- /dev/null
+\r
+// au-misra.lnt -- Author options - MISRA\r
+// Traditionally this file has held the lastest misra standard.\r
+// There have been two standards published: MISRA 1998 and MISRA 2004.\r
+// We have two files bearing options that, respectively, activate\r
+// these standards: au-misra1.lnt and au-misra2.lnt\r
+// Currently MISRA 2004 is the preferred standard.\r
+// Prior to publishing the 2nd standard, the file au-misra.lnt was\r
+// used to hold the then current misra standard. We are maintaining\r
+// this file to afford backward compatibility.\r
+\r
+au-misra2.lnt\r
--- /dev/null
+\r
+// au-misra2.lnt -- Author options - MISRA 2004\r
+\r
+/*\r
+ This options file can be used to explicitly activate those\r
+ checks advocated by the Motor Industry Software Reliability\r
+ Association.\r
+\r
+ You can use this file directly when linting your programs as in:\r
+\r
+ lin au-misra2 files\r
+\r
+ Gimpel Software relies on the document, "MISRA-C:2004\r
+ Guidelines for the use of the C language in critical systems",\r
+ copyright 2004 by MIRA Limited, as the primary source for this\r
+ file. Gimpel Software makes no warranty as to the completeness\r
+ or applicability of this options file and reserves the right to\r
+ amend or alter the official contents of such at any time.\r
+\r
+ "MISRA" is a registered trademark of MIRA Limited, held on\r
+ behalf of the MISRA Consortium.\r
+\r
+ */\r
+ -misra(2)\r
+ +e960 /* enable special MISRA 2 messages */\r
+ +elib(960) \r
+ +e961 /* enable special MISRA 2 messages */\r
+ +elib(961) \r
+\r
+/* Rule 1.1 (req) **********************************/\r
+\r
+ -A(C90) /* strict ANSI */\r
+ +e950 /* flag non-ANSI word or construct */\r
+ +elib(950) \r
+ -append(950,[MISRA 2004 Rule 1.1])\r
+\r
+/* Rule 1.2 (req) **********************************/\r
+\r
+ /* Avoid the use of undefined or unspecified behavior as described\r
+ in ISO C, Appendix A.6.1 and Appendix A.6.2 */\r
+\r
+ /* Source file not ending in a new-line character, ending in\r
+ new-line character immediately preceded by a backslash\r
+ character, or ending in a partial preprocessing token or\r
+ comment (ISO C, Appendix A.6.2, point 1).\r
+ */\r
+ +e406 /* unclosed comment */\r
+ +elib(406)\r
+ -append(406,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Non-standard character usage (ISO C, Appendix A.6.2, point 2).\r
+ */\r
+ +e27 /* illegal character */\r
+ +elib(27)\r
+ -append(27,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Unclosed quotes (ISO C, Appendix A.6.2, point 4).\r
+ */\r
+ +e2 /* unclose quote */\r
+ +elib(2)\r
+ -append(2,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Repeated label within a function (ISO C, Appendix A.6.2, point\r
+ 5).\r
+ */\r
+ +e31 /* symbol redefinition */\r
+ +elib(31)\r
+ -append(31,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Non-visible identifier used (ISO C, Appendix A.6.2, point 6).\r
+ */\r
+ +e40 /* undeclared identifier */\r
+ +elib(40)\r
+ -append(40,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Identifiers for the same entity differ beyond the minimal\r
+ significant characters (ISO C, Appendix A.6.2, point 7).\r
+ See Rules 1.4 and 5.1\r
+ */\r
+\r
+ /* The same identifier has both internal and external linkage in\r
+ the same translation unit (ISO C, Appendix A.6.2, point 8).\r
+ */\r
+ +e401 /* symbol not previously declared static */\r
+ +elib(401)\r
+ -append(401,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Multiple definitions for the same externally linked identifier\r
+ (ISO C, Appendix A.6.2, point 9).\r
+ */\r
+ +e31 /* symbol redefinition */\r
+ +elib(31)\r
+\r
+ /* Using automatic storage data via a pointer after the data's\r
+ lifetime (ISO C, Appendix A.6.2, point 10).\r
+ */\r
+ +e604 /* returning address of auto variable */\r
+ +elib(604)\r
+ -append(604,[MISRA 2004 Rule 1.2])\r
+ +e934 /* taking address of near auto variable */\r
+ +elib(934)\r
+ -append(934,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Incompatible redeclarations (ISO C, Appendix A.6.2, point 11).\r
+ See Rule 8.3\r
+ */\r
+\r
+ /* Non-standard escape sequence (ISO C, Appendix A.6.2, point 12).\r
+ See Rule 4.1\r
+ */\r
+\r
+ /* Non-standard character in header name (ISO C, Appendix A.6.2,\r
+ point 15).\r
+ See Rule 19.2\r
+ */\r
+\r
+ /* No complete type available (ISO C, Appendix A.6.2, point 16).\r
+ */\r
+ +e86 /* structure has no data elements */\r
+ +elib(86)\r
+ -append(86,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Using or converting a void expression (ISO C, Appendix A.6.2,\r
+ point 17).\r
+ */\r
+ +e64 /* type mismatch */\r
+ +elib(64)\r
+ -append(64,[MISRA 2004 Rule 1.2])\r
+ +e67 /* cannot cast between types */\r
+ +elib(67)\r
+ -append(67,[MISRA 2004 Rule 1.2])\r
+ +e144 /* non-existent return value */\r
+ +elib(144)\r
+ -append(144,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Modifying an object more than once or modifying and accessing\r
+ between two sequence points (ISO C, Appendix A.6.2, point 18).\r
+ See Rule 12.2\r
+ */\r
+\r
+ /* Invalid arithmetic operations or unrepresentable results\r
+ (ISO C, Appendix A.6.2, point 19).\r
+ */\r
+ +e54 /* division by 0 */\r
+ +elib(54)\r
+ -append(54,[MISRA 2004 Rule 1.2])\r
+ +e414 /* possible division by 0 */\r
+ +elib(414)\r
+ -append(414,[MISRA 2004 Rule 1.2])\r
+ +e795 /* conceivable division by 0 */\r
+ +elib(795)\r
+ -append(795,[MISRA 2004 Rule 1.2])\r
+ /* Also, see Rule 12.11 */\r
+\r
+ /* Passing a void argument to a function (ISO C, Appendix A.6.2,\r
+ point 20).\r
+ */\r
+ +e64 /* type mismatch */\r
+ +elib(64)\r
+\r
+ /* Incompatible function redeclaration (ISO C, Appendix A.6.2,\r
+ point 22).\r
+ See Rule 8.3\r
+ */\r
+\r
+ /* An invalid array reference, null pointer reference, or\r
+ reference to an object declared with automatic storage duration in\r
+ a terminated block occurs (ISO C, Appendix A.6.2, point 24).\r
+ */\r
+ +e64 /* type mismatch */\r
+ +elib(64)\r
+ +e413 /* likely use of null pointer */\r
+ +elib(413)\r
+ -append(413,[MISRA 2004 Rule 1.2])\r
+ +e415 /* out-of-bounds pointer */\r
+ +elib(415)\r
+ -append(415,[MISRA 2004 Rule 1.2])\r
+ +e416 /* out-of-bounds pointer */\r
+ +elib(416)\r
+ -append(416,[MISRA 2004 Rule 1.2])\r
+ +e428 /* negative subscript */\r
+ +elib(428)\r
+ -append(428,[MISRA 2004 Rule 1.2])\r
+ /* Also, see Rule 17.6 */\r
+\r
+ /* A pointer to a function is converted to a pointer to an object\r
+ or a pointer to an object is converted to a pointer to a function\r
+ (ISO C, Appendix A.6.2, point 26).\r
+ */\r
+ +e64 /* type mismatch */\r
+ +elib(64)\r
+ +e740 /* unusual pointer cast */\r
+ +elib(740)\r
+ -append(740,[MISRA 2004 Rule 1.2])\r
+ /* Also, see Rule 11.2 */\r
+\r
+ /* A pointer is converted to other than an integral or pointer\r
+ type (ISO C, Appendix A.6.2, point 27).\r
+ */\r
+ +e64 /* type mismatch */\r
+ +elib(64)\r
+ +e71 /* cannot cast */\r
+ +elib(71)\r
+ +esym(920,pointer) /* cast to void */\r
+ -append(920,[MISRA 2004 Rule 1.2])\r
+\r
+ /* An expression is shifted by a negative number or by an amount\r
+ greater than or equal to the width in bits of the expression being\r
+ shifted (ISO C, Appendix A.6.2, point 30).\r
+ */\r
+ +e504 /* unusual shift */\r
+ +elib(504)\r
+ -append(504,[MISRA 2004 Rule 1.2])\r
+\r
+ /* An identifier for an object is declared with no linkage and the\r
+ type of the object is incomplete after its declarator, or after its\r
+ init-declarator if it has an initializer (ISO C, Appendix\r
+ A.6.2, point 33).\r
+ */\r
+ +e86 /* structure has no data elements */\r
+ +elib(86)\r
+\r
+ /* Declaring a function at block scope with a storage-class\r
+ specifier other than extern (ISO C, Appendix A.6.2, point 34).\r
+ */\r
+ +e629 /* static class for function */\r
+ +elib(629)\r
+ -append(629,[MISRA 2004 Rule 1.2])\r
+\r
+ /* A bit-field is declared with a type other than int, signed int,\r
+ or unsigned int (ISO C, Appendix A.6.2, point 35).\r
+ See Rule 6.4\r
+ */\r
+\r
+ /* Attempting to modify an object with const-qualified type by\r
+ means of an lvalue with non-const-qualified type (ISO C,\r
+ Appendix A.6.2, point 36).\r
+ */\r
+ +e158 /* assignment increases capability */\r
+ +elib(158)\r
+ -append(158,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Attempting to refer to an object with volatile-qualified type\r
+ by means of an lvalue with non-volatile-qualified type (ISO C,\r
+ Appendix A.6.2, point 37).\r
+ */\r
+ +e158 /* assignment increases capability */\r
+ +elib(158)\r
+\r
+ /* Using the value of uninitialized automatic object (ISO C,\r
+ Appendix A.6.2, point 38).\r
+ See Rule 9.1\r
+ */\r
+\r
+ /* An object with aggregate or union type with static storage\r
+ duration has a non-brace-enclosed initializer, or an object\r
+ with aggregate or union type with automatic storage duration\r
+ has either a single expression initializer with a type other\r
+ than that of the object or a non-brace-enclosed initializer\r
+ (ISO C, Appendix A.6.2, point 39).\r
+ Also, see Rule 9.2\r
+ */\r
+ +e64 /* type mismatch */\r
+ +elib(64)\r
+\r
+ /* The value of a function is used, but no value was returned\r
+ (ISO C, Appendix A.6.2, point 40).\r
+ See Rule 16.8\r
+ */\r
+\r
+ /* A function that accepts a variable number of arguments is\r
+ defined without a parameter type list that ends with the\r
+ ellipsis notation (ISO C, Appendix A.6.2, point 41).\r
+ See Rule 8.3\r
+ */\r
+\r
+ /* An identifier for an object with internal linkage and an\r
+ incomplete type is declared with a tentative definition (ISO C,\r
+ Appendix A.6.2, point 42).\r
+ */\r
+ +e86 /* structure has no data elements */\r
+ +elib(86)\r
+\r
+ /* Non-standard #include preprocessing directive (ISO C, Appendix\r
+ A.6.2, point 44).\r
+ See Rule 19.3\r
+ */\r
+\r
+ /* Non-standard #line directive (ISO C, Appendix A.6.2, point 49).\r
+ */\r
+ +"estring(10,a numeric constant)"\r
+\r
+ /* #defining or #undefing any of: defined, __LINE__, __FILE__,\r
+ __DATE__, __TIME__, or __STDC__ (ISO C, Appendix A.6.2, point 50).\r
+ */\r
+ +e136 /* illegal macro name */\r
+ +elib(136)\r
+ -append(136,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Format-argument mismatch in an fprintf or fscanf type of\r
+ function (ISO C, Appendix A.6.2, point 75).\r
+ */\r
+ +e558 /* too few arguments */\r
+ +elib(558)\r
+ -append(558,[MISRA 2004 Rule 1.2])\r
+ +e719 /* too many arguments */\r
+ +elib(719)\r
+ -append(719,[MISRA 2004 Rule 1.2])\r
+\r
+ /* A %% conversion specification for the fprintf or fscanf\r
+ function contains characters between the pair of % characters\r
+ (ISO C, Appendix A.6.2, point 77).\r
+ */\r
+ +e557 /* unrecognized format */\r
+ +elib(557)\r
+ -append(557,[MISRA 2004 Rule 1.2])\r
+\r
+ /* An aggregate or union, or a pointer to an aggregate or union is\r
+ an argument to the fprintf function, except for the conversion\r
+ specifiers %s (for an array of character type) or %p (for a pointer\r
+ to void) (ISO C, Appendix A.6.2, point 81).\r
+ */\r
+ +e437 /* passing struct to ellipsis */\r
+ +elib(437)\r
+ -append(437,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Referring to deallocated space (ISO C, Appendix A.6.2, point\r
+ 87).\r
+ */\r
+ +e449 /* previously deallocated pointer */\r
+ +elib(449)\r
+ -append(449,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Misuse of free or realloc (ISO C, Appendix A.6.2, point 88).\r
+ */\r
+ +esym(424,free) /* inappropriate deallocation */\r
+ -append(424,[MISRA 2004 Rule 1.2])\r
+\r
+ /* An array written to by a copying or concatenation function is\r
+ too small (ISO C, Appendix A.6.2, point 91).\r
+ */\r
+ +e419 /* data overrun */\r
+ +elib(419)\r
+ -append(419,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Order of evaluation (ISO C, Appendix A.6.1, point 7).\r
+ */\r
+ +e564 /* variable depends on order of evaluation */\r
+ +elib(564)\r
+ -append(564,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Side effects order (ISO C, Appendix A.6.1, point 8).\r
+ */\r
+ +e931 /* both sides of an expression have side-effects */\r
+ +elib(931)\r
+ -append(931,[MISRA 2004 Rule 1.2])\r
+\r
+ /* Function argument evaluation (ISO C, Appendix A.6.1, point 9).\r
+ */\r
+ +e564 /* variable depends on order of evaluation */\r
+ +elib(564)\r
+\r
+ /* The order in which # and ## operations are evaluated during\r
+ macro substitution (ISO C, Appendix A.6.1, point 12).\r
+ */\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 19.12,\r
+ multiple use of '#/##' operators in macro definition\r
+ */\r
+\r
+ /* Whether setjmp is a macro or an external identifier (ISO C,\r
+ Appendix A.6.1, point 14).\r
+ See Rule 20.1\r
+ */\r
+\r
+/* Rule 1.3 (req) **********************************/\r
+\r
+ /* This is an environmental requirement on inter-language\r
+ interfacing and is not statically checkable\r
+ */\r
+\r
+/* Rule 1.4 (req) **********************************/\r
+\r
+ -idlen(31) /* flag names identical in the first 31 characters */\r
+ +e621 /* Identifier clash - length set by -idlen */\r
+ +elib(621) \r
+ -append(621,[MISRA 2004 Rule 1.4])\r
+\r
+/* Rule 1.5 (adv) **********************************/\r
+\r
+ /* This is an environmental requirement involving the floating\r
+ point hardware and is not statically checkable\r
+ */\r
+\r
+/* Rule 2.1 (req) **********************************/\r
+\r
+ +e586 /* to activate the deprecation message */\r
+ +elib(586)\r
+ -deprecate(keyword,asm,[MISRA 2004 Rule 2.1])\r
+\r
+/* Rule 2.2 (req) **********************************/\r
+\r
+ -A(C90) /* strict ANSI */\r
+ +e950 /* flag non-ANSI word or construct */\r
+ +elib(950)\r
+ -append(950,[MISRA 2004 Rule 2.2])\r
+\r
+/* Rule 2.3 (req) **********************************/\r
+\r
+ -fnc /* flag nested comments */\r
+ +e602 /* comment within comment */\r
+ +elib(602) \r
+ -append(602,[MISRA 2004 Rule 2.3])\r
+\r
+/* Rule 2.4 (adv) **********************************/\r
+\r
+ /* This requirement (that there be no commented-out code) is, in\r
+ principle, not statically checkable. The reason given for the\r
+ requirement is that comments do not nest. Thus a commented\r
+ out section of code that happens to use slash-star commenting\r
+ could inadvertently introduce unwanted code. Rule 2.3, however,\r
+ addresses the nested comment issue and hence the major concern\r
+ that this requirement seeks to address is indeed checkable.\r
+ */\r
+ -fnc /* flag nested comments */\r
+ +e602 /* comment within comment */\r
+ +elib(602) \r
+ -append(602,[MISRA 2004 Rule 2.4])\r
+\r
+/* Rule 3.1 (req) **********************************/\r
+\r
+ /* This is a documentation requirement and as such is not statically\r
+ checkable.\r
+ */\r
+\r
+/* Rule 3.2 (req) **********************************/\r
+\r
+ /* As stated in the description of the requirement, this is a\r
+ documentation requirement denoting the characters that may be\r
+ placed in string and character literals. It is not statically\r
+ checkable.\r
+ */\r
+\r
+/* Rule 3.3 (adv) **********************************/\r
+\r
+ /* This is a requirement on the hardware implementation of\r
+ integer division and/or the program's understanding of it.\r
+ It is not statically checkable.\r
+ */\r
+\r
+/* Rule 3.4 (req) **********************************/\r
+\r
+ /* This rule requires that all uses of the pragma directive\r
+ be documented. To assist in this documentation\r
+ effort we can report on unknown pragmas. By default, all\r
+ pragmas are unknown except two, push_macro and pop_macro.\r
+ These have been approved by the C standards committee but\r
+ nonetheless may be disabled (and thus reported upon as unknown)\r
+ by use of the -pragma option. These and other pragmas can be\r
+ later added using the +pragma option.\r
+ */\r
+ +e975 /* report on unknown macros */\r
+ -pragma( push_macro ) /* disable push_macro */\r
+ -pragma( pop_macro ) /* disable pop_macro */\r
+ -append(975,[MISRA 2004 Rule 3.4])\r
+\r
+\r
+/* Rule 3.5 (req) **********************************/\r
+\r
+ /* This rule is a documentation requirement when bit fields\r
+ are being used. As such, it is not statically checkable.\r
+ */\r
+\r
+/* Rule 3.6 (req) **********************************/\r
+\r
+ /* PC-lint and FlexeLint analyze auto-generated code in precisely\r
+ the same manner as non-auto-generated code.\r
+ */\r
+\r
+/* Rule 4.1 (req) **********************************/\r
+\r
+ +e606 /* non-ANSI escape sequence */\r
+ +elib(606) \r
+ -append(606,[MISRA 2004 Rule 4.1])\r
+\r
+/* Rule 4.2 (req) **********************************/\r
+\r
+ -ftg /* inhibit use of trigraphs */\r
+ +e739 /* activate trigraph in string message */\r
+ +elib(739) \r
+ -append(739,[MISRA 2004 Rule 4.2])\r
+\r
+/* Rule 5.1 (req) **********************************/\r
+\r
+ -idlen(31) /* flag names identical in the first 31 characters */\r
+ +e621 /* Identifier clash - length set by -idlen */\r
+ +elib(621) \r
+ -append(621,[MISRA 2004 Rule 5.1])\r
+ \r
+/* Rule 5.2 (req) **********************************/\r
+\r
+ +e578 /* enable reports of name hiding */\r
+ +elib(578) \r
+ -append(578,[MISRA 2004 Rule 5.2])\r
+\r
+/* Rule 5.3 (req) **********************************/\r
+\r
+ +e578 /* enable reports of name hiding */\r
+ +elib(578)\r
+ -append(578,[MISRA 2004 Rule 5.3])\r
+ +e623 /* redefining the storage class of symbol */\r
+ +elib(623) \r
+ -append(623,[MISRA 2004 Rule 5.3])\r
+\r
+/* Rule 5.4 (req) **********************************/\r
+\r
+ +e578 /* Declaration of Symbol hides Symbol */\r
+ +elib(578)\r
+ -append(578,[MISRA 2004 Rule 5.4])\r
+ +e14 /* Symbol previously defined */\r
+ +elib(14)\r
+ -append(14,[MISRA 2004 Rule 5.4])\r
+ +e15 /* Symbol redeclared */\r
+ +elib(15)\r
+ -append(15,[MISRA 2004 Rule 5.4])\r
+\r
+/* Rule 5.5 (adv) **********************************/\r
+\r
+ +e578 /* Declaration of Symbol hides Symbol */\r
+ +elib(578)\r
+ -append(578,[MISRA 2004 Rule 5.5])\r
+ +e580 /* enable reports of name hiding */\r
+ +elib(580) \r
+ -append(580,[MISRA 2004 Rule 5.5])\r
+\r
+/* Rule 5.6 (adv) **********************************/\r
+\r
+ +e578 /* enable reports of name hiding */\r
+ +elib(578)\r
+ -append(578,[MISRA 2004 Rule 5.6])\r
+ +e580 /* enable reports of name hiding */\r
+ +elib(580) \r
+ -append(580,[MISRA 2004 Rule 5.6])\r
+\r
+/* Rule 5.7 (adv) **********************************/\r
+\r
+ +e578 /* enable reports of name hiding */\r
+ +elib(578)\r
+ -append(578,[MISRA 2004 Rule 5.7])\r
+ +e580 /* enable reports of name hiding */\r
+ +elib(580) \r
+ -append(580,[MISRA 2004 Rule 5.7])\r
+\r
+/* Rule 6.1 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 6.1, \r
+ Disallowed use of non-character value, or \r
+ Plain char mixed with type other than plain char, or \r
+ Plain char used with prohibited operator, or \r
+ Disallowed cast of plain char \r
+ */\r
+\r
+/* Rule 6.2 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 6.2, \r
+ Disallowed use of non-numeric value \r
+ */\r
+\r
+/* Rule 6.3 (adv) **********************************/\r
+\r
+ +e970 /* flag modifiers used outside of typedefs */\r
+ +elib(970)\r
+ -append(970,[MISRA 2004 Rule 6.3])\r
+\r
+/* Rule 6.4 (req) **********************************/\r
+\r
+ +e46 /* field type should be int */\r
+ +elib(46)\r
+ -append(46,[MISRA 2004 Rule 6.4])\r
+\r
+/* Rule 6.5 (req) **********************************/\r
+\r
+ +e806 /* small bit field is signed rather than unsigned */\r
+ +elib(806)\r
+ -append(806,[MISRA 2004 Rule 6.5])\r
+\r
+/* Rule 7.1 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 7.1,\r
+ Octal constant or octal escape sequence used\r
+ */\r
+\r
+/* Rule 8.1 (req) **********************************/\r
+\r
+ +e718 /* Symbol undeclared */\r
+ +elib(718)\r
+ -append(718,[MISRA 2004 Rule 8.1])\r
+ +e746 /* Call to function not made in the\r
+ presence of a prototype\r
+ */\r
+ +elib(746)\r
+ -append(746,[MISRA 2004 Rule 8.1])\r
+ +e937 /* old-style function declaration */\r
+ +elib(937)\r
+ -append(937,[MISRA 2004 Rule 8.1])\r
+ +e957 /* function defined without a prototype\r
+ in scope\r
+ */\r
+ +elib(957)\r
+ -append(957,[MISRA 2004 Rule 8.1])\r
+\r
+/* Rule 8.2 (req) **********************************/\r
+\r
+ +e745 /* function has no explicit type */\r
+ +elib(745)\r
+ -append(745,[MISRA 2004 Rule 8.2])\r
+ +e939 /* return type defaults to int */\r
+ +elib(939)\r
+ -append(939,[MISRA 2004 Rule 8.2])\r
+\r
+/* Rule 8.3 (req) **********************************/\r
+\r
+ -fvr /* varying return mode not allowed */\r
+ +e18 /* symbol redeclared */\r
+ +elib(18)\r
+ -append(18,[Encompasses MISRA 2004 Rule 8.3])\r
+ +e516 /* argument type conflict */\r
+ +elib(516)\r
+ -append(516,[MISRA 2004 Rule 8.3])\r
+ +e532 /* return mode of symbol inconsistent */\r
+ +elib(532)\r
+ -append(532,[MISRA 2004 Rule 8.3])\r
+\r
+/* Rule 8.4 (req) **********************************/\r
+\r
+ +e15 /* symbol redeclared */\r
+ +elib(15)\r
+ -append(15,[MISRA 2004 Rule 8.4])\r
+ +e64 /* flag type mismatch */\r
+ +elib(64)\r
+ -append(64,[MISRA 2004 Rule 8.4])\r
+\r
+/* Rule 8.5 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 8.5,\r
+ no object/function definitions in header files\r
+ */\r
+\r
+/* Rule 8.6 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 8.6,\r
+ function not declared at file scope\r
+ */\r
+\r
+/* Rule 8.7 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 8.7, \r
+ Could define variable at block scope \r
+ */\r
+\r
+/* Rule 8.8 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 8.8, \r
+ Object/function previously declared in location \r
+ */\r
+\r
+/* Rule 8.9 (req) **********************************/\r
+\r
+ +e14 /* Symbol previously defined */\r
+ +elib(14)\r
+ -append(14,[MISRA 2004 Rule 8.9])\r
+\r
+/* Rule 8.10 (req) *********************************/\r
+\r
+ +e765 /* symbol could be made static */\r
+ +elib(765)\r
+ -append(765,[MISRA 2004 Rule 8.10])\r
+\r
+/* Rule 8.11 (req) *********************************/\r
+\r
+ +e512 /* symbol previously used as static */\r
+ +elib(512)\r
+ -append(512,[MISRA 2004 Rule 8.11])\r
+\r
+/* Rule 8.12 (req) *********************************/\r
+\r
+ +e85 /* Array has 0 dimension */\r
+ +elib(85)\r
+ -append(85,[MISRA 2004 Rule 8.12])\r
+\r
+/* Rule 9.1 (req) **********************************/\r
+\r
+ +e644 /* Symbol may not have been initialized */\r
+ +elib(644)\r
+ -append(644,[MISRA 2004 Rule 9.1])\r
+ +e771 /* Symbol conceivably not initialized */\r
+ +elib(771)\r
+ -append(771,[MISRA 2004 Rule 9.1])\r
+ +e530 /* Symbol not initialized */\r
+ +elib(530)\r
+ -append(530,[MISRA 2004 Rule 9.1])\r
+\r
+/* Rule 9.2 (req) **********************************/\r
+\r
+ +e940 /* omitted braces within an initializer */\r
+ +elib(940)\r
+ -append(940,[MISRA 2004 Rule 9.2])\r
+\r
+/* Rule 9.3 (req) **********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 9.3,\r
+ should initialize either all enum members or only the first\r
+ */\r
+\r
+/* Rule 10.1 (req) *********************************/\r
+\r
+ +e524 /* loss of precision */\r
+ +elib(524)\r
+ -append(524,[MISRA 2004 Rule 10.1])\r
+ +e653 /* possible loss of fraction */\r
+ +elib(653)\r
+ -append(653,[MISRA 2004 Rule 10.1])\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 10.1,\r
+ Prohibited Implicit Conversion, or\r
+ Implicit conversion from integer to floating point type, or\r
+ Implicit conversion of integer to smaller type, or\r
+ Implicit conversion changes signedness, or\r
+ Implicit conversion of complex integer expression\r
+ */\r
+\r
+/* Rule 10.2 (req) *********************************/\r
+\r
+ +e747 /* significant prototype coercion */\r
+ +elib(747)\r
+ -append(747,[MISRA 2004 Rule 10.2])\r
+ +e918 /* prototype coercion of pointers */\r
+ +elib(918)\r
+ -append(918,[MISRA 2004 Rule 10.2])\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 10.2,\r
+ Prohibited Implicit Conversion, or\r
+ Implicit conversion from floating point to integer type, or\r
+ Implicit conversion of floating point to smaller type, or\r
+ Implicit conversion of complex floating point expression\r
+ */\r
+\r
+/* Rule 10.3 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 10.3,\r
+ Prohibited cast of complex integer expression\r
+ */\r
+\r
+/* Rule 10.4 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 10.4,\r
+ Prohibited cast of complex floating-point expression: Casting\r
+ to larger type\r
+ */\r
+\r
+/* Rule 10.5 (req) *********************************/\r
+\r
+ +e701 /* shift left of signed quantity */\r
+ +elib(701)\r
+ -append(701,[MISRA 2004 Rule 10.5])\r
+ +e702 /* shift right of signed quantity */\r
+ +elib(702)\r
+ -append(702,[MISRA 2004 Rule 10.5])\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 10.5,\r
+ Operators '~' and '<<' require recasting to underlying type for\r
+ sub-integers\r
+ */\r
+\r
+/* Rule 10.6 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 10.6, \r
+ Unsigned integer literals require a 'U' suffix \r
+ */\r
+\r
+/* Rule 11.1 (req) *********************************/\r
+\r
+ +esym(68,pointer) /* cannot cast to/from pointer */\r
+ -append(68,[MISRA 2004 Rule 11.1])\r
+ +esym(922,pointer) /* cast to/from pointer */\r
+ +e923 /* cast pointer/non-pointer */\r
+ +elib(923)\r
+ -append(923,[Encompasses MISRA 2004 Rule 11.1])\r
+\r
+/* Rule 11.2 (req) *********************************/\r
+\r
+ +esym(68,pointer) /* Cannot cast from pointer to float */\r
+ -append(68,[MISRA 2004 Rule 11.2])\r
+ +e71 /* Cannot cast between types */\r
+ +elib(71)\r
+ -append(71,[MISRA 2004 Rule 11.2])\r
+\r
+/* Rule 11.3 (adv) *********************************/\r
+\r
+ +e923 /* cast pointer/non-pointer */\r
+ +elib(923)\r
+ -append(923,[MISRA 2004 Rule 11.3])\r
+\r
+/* Rule 11.4 (adv) *********************************/\r
+\r
+ +e926 /* cast from pointer to pointer */\r
+ +elib(926)\r
+ -append(926,[MISRA 2004 Rule 11.4])\r
+ +e927 /* cast from pointer to pointer */\r
+ +elib(927)\r
+ -append(927,[MISRA 2004 Rule 11.4])\r
+ +e928 /* cast from pointer to pointer */\r
+ +elib(928)\r
+ -append(928,[MISRA 2004 Rule 11.4])\r
+ +e929 /* cast from pointer to pointer */\r
+ +elib(929)\r
+ -append(929,[MISRA 2004 Rule 11.4])\r
+\r
+/* Rule 11.5 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 11.5, \r
+ Attempt to cast away const/volatile from a pointer or reference \r
+ */\r
+\r
+/* Rule 12.1 (adv) *********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 961: Violates MISRA 2004 Advisory Rule 12.1,\r
+ dependence placed on C's operator precedence\r
+ */\r
+ +e834 /* confusing operator sequence (same precedence) */\r
+ +elib(834)\r
+ -append(834,[MISRA 2004 Rule 12.1])\r
+\r
+/* Rule 12.2 (req) *********************************/\r
+\r
+ +e564 /* order of evaluation */\r
+ +elib(564)\r
+ -append(564,[MISRA 2004 Rule 12.2])\r
+\r
+/* Rule 12.3 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 12.3,\r
+ 'sizeof' used on expressions with side effect\r
+ */\r
+\r
+/* Rule 12.4 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 12.4,\r
+ side effects on right hand side of logical operator\r
+ */\r
+\r
+/* Rule 12.5 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 12.5, \r
+ Non-primary expression used with logical operator \r
+ */\r
+\r
+/* Rule 12.6 (adv) *********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 961: Violates MISRA 2004 Advisory Rule 12.6, \r
+ Boolean expression used with non-permitted operator, or \r
+ Boolean expression required for operator\r
+ */\r
+\r
+/* Rule 12.7 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 12.7,\r
+ Bitwise operator applied to signed underlying type\r
+ */\r
+\r
+/* Rule 12.8 (req) *********************************/\r
+\r
+ +e572 /* excessive shift value */\r
+ +elib(572)\r
+ -append(572,[MISRA 2004 Rule 12.8])\r
+\r
+/* Rule 12.9 (req) *********************************/\r
+\r
+ +e501 /* expected signed type */\r
+ +elib(501)\r
+ -append(501,[MISRA 2004 Rule 12.9])\r
+\r
+/* Rule 12.10 (req) ********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 12.10,\r
+ comma operator used\r
+ */\r
+\r
+/* Rule 12.11 (adv) ********************************/\r
+\r
+ +e648 /* overflow in computing constant */\r
+ +elib(648)\r
+ -append(648,[MISRA 2004 Rule 12.11])\r
+\r
+/* Rule 12.12 (req) ********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 12.12, \r
+ Bit representation of a floating point type used \r
+ */\r
+\r
+/* Rule 12.13 (req) ********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 12.13, \r
+ Increment or decrement combined with another operator \r
+ */\r
+\r
+/* Rule 13.1 (req) *********************************/\r
+\r
+ +e720 /* Boolean test of assignment */\r
+ +elib(720)\r
+ -append(720,[MISRA 2004 Rule 13.1])\r
+ +e820 /* Boolean test of parenthesized\r
+ assignment\r
+ */\r
+ +elib(820)\r
+ -append(820,[MISRA 2004 Rule 13.1])\r
+\r
+/* Rule 13.2 (adv) *********************************/\r
+\r
+ +e720 /* Boolean test of assignment */\r
+ +elib(720)\r
+ -append(720,[MISRA 2004 Rule 13.2])\r
+\r
+/* Rule 13.3 (req) *********************************/\r
+\r
+ /* PC-lint and FlexeLint partially support this rule with the\r
+ following options.\r
+ */\r
+ +e777 /* testing floats for equality */\r
+ +elib(777)\r
+ -append(777,[MISRA 2004 Rule 13.3])\r
+\r
+/* Rule 13.4 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 13.4,\r
+ floating point variable used as loop counter\r
+ */\r
+\r
+/* Rule 13.5 (req) *********************************/\r
+\r
+ +e440 /* Compare 2nd 'for' expression with the 3rd */\r
+ +elib(440)\r
+ -append(440,[MISRA 2004 Rule 13.5])\r
+ +e443 /* Compare 1st 'for' expression with the 3rd */\r
+ +elib(443)\r
+ -append(443,[MISRA 2004 Rule 13.5])\r
+\r
+/* Rule 13.6 (req) *********************************/\r
+\r
+ +e850 /* detect loop variables modified within the loop */\r
+ +elib(850)\r
+ -append(850,[MISRA 2004 Rule 13.6])\r
+\r
+/* Rule 13.7 (req) *********************************/\r
+\r
+ +e506 /* constant value boolean */\r
+ +elib(506)\r
+ -append(506,[MISRA 2004 Rule 13.7])\r
+\r
+/* Rule 14.1 (req) *********************************/\r
+\r
+ +e506 /* constant value boolean */\r
+ +elib(506)\r
+ -append(506,[MISRA 2004 Rule 14.1])\r
+ +e527 /* unreachable */\r
+ +elib(527)\r
+ -append(527,[MISRA 2004 Rule 14.1])\r
+ +e681 /* loop not entered */\r
+ +elib(681)\r
+ -append(681,[MISRA 2004 Rule 14.1])\r
+ +e827 /* loop not reachable */\r
+ +elib(827)\r
+ -append(827,[MISRA 2004 Rule 14.1])\r
+\r
+/* Rule 14.2 (req) *********************************/\r
+\r
+ +e505 /* redundant left argument to comma */\r
+ +elib(505)\r
+ -append(505,[MISRA 2004 Rule 14.2])\r
+ +e522 /* no side-effects */\r
+ +elib(522)\r
+ -append(522,[MISRA 2004 Rule 14.2])\r
+\r
+/* Rule 14.3 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 14.3,\r
+ null statement not in line by itself\r
+ */\r
+\r
+/* Rule 14.4 (req) *********************************/\r
+\r
+ +e801 /* use of 'goto' is deprecated */\r
+ +elib(801)\r
+ -append(801,[MISRA 2004 Rule 14.4])\r
+\r
+/* Rule 14.5 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 14.5,\r
+ continue statement detected\r
+ */\r
+\r
+/* Rule 14.6 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 14.6,\r
+ more than one 'break' terminates loop\r
+ */\r
+\r
+/* Rule 14.7 (req) *********************************/\r
+\r
+ +e904 /* return before function end */\r
+ +elib(904)\r
+ -append(904,[MISRA 2004 Rule 14.7])\r
+\r
+/* Rule 14.8 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 14.8,\r
+ left brace expected for switch, for, do and while\r
+ */\r
+\r
+/* Rule 14.9 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 14.9,\r
+ left brace expected for if, else and else if\r
+ */\r
+\r
+/* Rule 14.10 (req) ********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 14.10,\r
+ no 'else' at end of 'if ... else if' chain\r
+ */\r
+\r
+/* Rule 15.1 (req) *********************************/\r
+\r
+ +e44 /* Need a switch */\r
+ +elib(44)\r
+ -append(44,[MISRA 2004 Rule 15.1])\r
+\r
+/* Rule 15.2 (req) *********************************/\r
+\r
+ +e616 /* control flows into case/default */\r
+ +elib(616)\r
+ -append(616,[MISRA 2004 Rule 15.2])\r
+ +e825 /* control flows into case/default without\r
+ -fallthrough comment\r
+ */\r
+ +elib(825)\r
+ -append(825,[MISRA 2004 Rule 15.2])\r
+\r
+/* Rule 15.3 (req) *********************************/\r
+\r
+ /* PC-lint and FlexeLint partially support this rule with the\r
+ following options.\r
+ */\r
+ +e744 /* switch statement has no default */\r
+ +elib(744)\r
+ -append(744,[MISRA 2004 Rule 15.3])\r
+\r
+/* Rule 15.4 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 15.4,\r
+ boolean value in switch statement\r
+ */\r
+\r
+/* Rule 15.5 (req) *********************************/\r
+\r
+ +e764 /* switch does not have a case */\r
+ +elib(764)\r
+ -append(764,[MISRA 2004 Rule 15.5])\r
+\r
+/* Rule 16.1 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 16.1,\r
+ function has variable number of arguments\r
+ */\r
+\r
+/* Rule 16.2 (req) *********************************/\r
+\r
+ +stack()\r
+ +estring(974,*recursive*) /* worst case function stack usage */\r
+ -append(974,[MISRA 2004 Rule 16.2])\r
+\r
+/* Rule 16.3 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 16.3,\r
+ all parameters shall have identifiers\r
+ */\r
+\r
+/* Rule 16.4 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 16.4, \r
+ Function parameter list differs from prior declaration \r
+ */\r
+\r
+/* Rule 16.5 (req) *********************************/\r
+\r
+ +e937 /* old-style function declaration */\r
+ +elib(937)\r
+ -append(937,[MISRA 2004 Rule 16.5])\r
+\r
+/* Rule 16.6 (req) *********************************/\r
+\r
+ +e118 /* too few arguments for prototype */\r
+ +elib(118)\r
+ -append(118,[MISRA 2004 Rule 16.6])\r
+ +e119 /* too many arguments for prototype */\r
+ +elib(119)\r
+ -append(119,[MISRA 2004 Rule 16.6])\r
+\r
+/* Rule 16.7 (adv) *********************************/\r
+\r
+ +e818 /* use const on paramaters where appropriate */\r
+ +elib(818)\r
+ -append(818,[MISRA 2004 Rule 16.7])\r
+\r
+/* Rule 16.8 (req) *********************************/\r
+\r
+ +e533 /* function should return a value */\r
+ +elib(533)\r
+ -append(533,[MISRA 2004 Rule 16.8])\r
+\r
+/* Rule 16.9 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 16.9, \r
+ Function identifier used without '&' or parenthisized parameter\r
+ list \r
+ */\r
+\r
+/* Rule 16.10 (req) ********************************/\r
+\r
+ +e534 /* ignoring return value of function */\r
+ +elib(534)\r
+ -append(534,[Encompasses MISRA 2004 Rule 16.10])\r
+\r
+/* Rule 17.1 (req) *********************************/\r
+\r
+ /* not currently supported */\r
+\r
+/* Rule 17.2 (req) *********************************/\r
+\r
+ +e946 /* relational or subtract operator applied to pointers */\r
+ +elib(946)\r
+ -append(946,[MISRA 2004 Rule 17.2])\r
+ +e947 /* relational or subtract operator applied to pointers */\r
+ +elib(947)\r
+ -append(947,[MISRA 2004 Rule 17.2])\r
+\r
+/* Rule 17.3 (req) *********************************/\r
+\r
+ +e946 /* relational or subtract operator applied to pointers */\r
+ +elib(946)\r
+ -append(946,[MISRA 2004 Rule 17.3])\r
+ +e947 /* relational or subtract operator applied to pointers */\r
+ +elib(947)\r
+ -append(947,[MISRA 2004 Rule 17.3])\r
+\r
+/* Rule 17.4 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 17.4, \r
+ Pointer arithmetic other than array indexing used, or \r
+ Pointer arithmetic by increment or decrement used\r
+ */\r
+\r
+/* Rule 17.5 (adv) *********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 961: Violates MISRA 2004 Advisory Rule 17.5,\r
+ More than two pointer indirection levels used \r
+ */\r
+\r
+/* Rule 17.6 (req) *********************************/\r
+\r
+ +e733 /* assigning address of auto to outer scope symbol */\r
+ +elib(733)\r
+ -append(733,[MISRA 2004 Rule 17.6])\r
+ +e789 /* assigning address of auto to static */\r
+ +elib(789)\r
+ -append(789,[MISRA 2004 Rule 17.6])\r
+\r
+/* Rule 18.1 (req) *********************************/\r
+\r
+ +e43 /* vacuous type for variable */\r
+ +elib(43)\r
+ -append(43,[MISRA 2004 Rule 18.1])\r
+\r
+/* Rule 18.2 (req) *********************************/\r
+\r
+ /* not currently supported */\r
+\r
+/* Rule 18.3 (req) *********************************/\r
+\r
+ /* Determining whether areas of memory are\r
+ being reused for 'unrelated' purposes is not\r
+ statically checkable.\r
+ */\r
+\r
+/* Rule 18.4 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 18.4,\r
+ unions shall not be used\r
+ */\r
+\r
+/* Rule 19.1 (adv) *********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 961: Violates MISRA 2004 Advisory Rule 19.1,\r
+ only preprocessor statements and comments before '#include'\r
+ */\r
+\r
+/* Rule 19.2 (adv) *********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 961: Violates MISRA 2004 Advisory Rule 19.2,\r
+ header file name with non-standard character\r
+ */\r
+\r
+/* Rule 19.3 (req) *********************************/\r
+\r
+ +e12 /* Need < or " after #include */\r
+ +elib(12)\r
+ -append(12,[MISRA 2004 Rule 19.3])\r
+\r
+/* Rule 19.4 (req) *********************************/\r
+\r
+ +e773 /* expression-like macro not parenthesized */\r
+ +elib(773)\r
+ -append(773,[MISRA 2004 Rule 19.4])\r
+\r
+/* Rule 19.5 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 19.5,\r
+ '#define/#undef' used within a block\r
+ */\r
+\r
+/* Rule 19.6 (req) *********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 19.6,\r
+ use of '#undef' is discouraged\r
+ */\r
+\r
+/* Rule 19.7 (adv) *********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 961: Violates MISRA 2004 Advisory Rule 19.7,\r
+ Function-like macro defined \r
+ */\r
+\r
+/* Rule 19.8 (req) *********************************/\r
+\r
+ +e131 /* syntax error in call of macro */\r
+ +elib(131)\r
+ -append(131,[MISRA 2004 Rule 19.8])\r
+\r
+/* Rule 19.9 (req) *********************************/\r
+\r
+ +e436 /* preprocessor directive in invocation of macro */\r
+ +elib(436)\r
+ -append(436,[MISRA 2004 Rule 19.9])\r
+\r
+/* Rule 19.10 (req) ********************************/\r
+\r
+ +e773 /* expression-like macro not parenthesized */\r
+ +elib(773)\r
+ -append(773,[MISRA 2004 Rule 19.10])\r
+\r
+/* Rule 19.11 (req) ********************************/\r
+\r
+ +e553 /* undefined preprocessor variable */\r
+ +elib(553)\r
+ -append(553,[MISRA 2004 Rule 19.11])\r
+\r
+/* Rule 19.12 (req) ********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 19.12,\r
+ multiple use of '#/##' operators in macro definition\r
+ */\r
+\r
+/* Rule 19.13 (adv) ********************************/\r
+\r
+ /* we generate note 961 as follows:\r
+ Note 961: Violates MISRA 2004 Advisory Rule 19.13,\r
+ '#/##' operators used\r
+ */\r
+\r
+/* Rule 19.14 (req) ********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 19.14,\r
+ non-standard use of 'defined' preprocessor statement\r
+ */\r
+\r
+/* Rule 19.15 (req) ********************************/\r
+\r
+ +e537 /* Repeated include file */\r
+ +elib(537)\r
+ -append(537,[MISRA 2004 Rule 19.15])\r
+\r
+/* Rule 19.16 (req) ********************************/\r
+\r
+ +e544 /* endif or else not followed by EOL */\r
+ +elib(544)\r
+ -append(544,[MISRA 2004 Rule 19.16])\r
+ +e16 /* # directive not followed by recognizable word */\r
+ +elib(16)\r
+ -append(16,[MISRA 2004 Rule 19.16])\r
+ /* other parts to the intent of this rule such as a syntax check\r
+ of the disabled portions of the code do not seem to be\r
+ statically checkable\r
+ */\r
+\r
+/* Rule 19.17 (req) ********************************/\r
+\r
+ +e405 /* #if not closed off */\r
+ +elib(405)\r
+ -append(405,[MISRA 2004 Rule 19.17])\r
+\r
+/* Rule 20.1 (req) *********************************/\r
+\r
+ +e683 /* complain about #define standard functions */\r
+ +elib(683)\r
+ -append(683,[MISRA 2004 Rule 20.1])\r
+ /* Undefining standard library macros is covered by rule 19.6. */\r
+ /* Defining/redefining reserved/standard identifiers is covered\r
+ by rule 20.2.\r
+ */\r
+\r
+/* Rule 20.2 (req) *********************************/\r
+\r
+ /* we generate note 960 as follows:\r
+ Note 960: Violates MISRA 2004 Required Rule 20.2,\r
+ Re-use of reserved identifier \r
+ */\r
+\r
+/* Rule 20.3 (req) *********************************/\r
+\r
+ /* The arguments to over 100 calls to standard library functions\r
+ are monitored; users can specify additional constraints for\r
+ other functions.\r
+ */\r
+\r
+/* Rule 20.4 (req) *********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( function, calloc, [MISRA 2004 Rule 20.4] )\r
+ -deprecate( function, malloc, [MISRA 2004 Rule 20.4] )\r
+ -deprecate( function, realloc, [MISRA 2004 Rule 20.4] )\r
+ -deprecate( function, free, [MISRA 2004 Rule 20.4] )\r
+\r
+/* Rule 20.5 (req) *********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( variable, errno, [MISRA 2004 Rule 20.5] )\r
+\r
+/* Rule 20.6 (req) *********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( macro, offsetof, [MISRA 2004 Rule 20.6] )\r
+\r
+/* Rule 20.7 (req) *********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( function, longjmp, [MISRA 2004 Rule 20.7] )\r
+ -deprecate( function, setjmp, [MISRA 2004 Rule 20.7] )\r
+\r
+/* Rule 20.8 (req) *********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( function, signal, [MISRA 2004 Rule 20.8] )\r
+ -deprecate( function, raise, [MISRA 2004 Rule 20.8] )\r
+\r
+/* Rule 20.9 (req) *********************************/\r
+\r
+ +e829 /* warn on header usage */\r
+ +elib(829)\r
+ -headerwarn(stdio.h)\r
+ -append(829(stdio.h),[MISRA 2004 Rule 20.9])\r
+\r
+/* Rule 20.10 (req) ********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( function, atof, [MISRA 2004 Rule 20.10] )\r
+ -deprecate( function, atoi, [MISRA 2004 Rule 20.10] )\r
+ -deprecate( function, atol, [MISRA 2004 Rule 20.10] )\r
+\r
+/* Rule 20.11 (req) ********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( function, abort, [MISRA 2004 Rule 20.11] )\r
+ -deprecate( function, exit, [MISRA 2004 Rule 20.11] )\r
+ -deprecate( function, getenv, [MISRA 2004 Rule 20.11] )\r
+ -deprecate( function, system, [MISRA 2004 Rule 20.11] )\r
+\r
+/* Rule 20.12 (req) ********************************/\r
+\r
+ +e586 /* Symbol is deprecated */\r
+ +elib(586)\r
+ -deprecate( function, time, [MISRA 2004 Rule 20.12] )\r
+ -deprecate( function, strftime, [MISRA 2004 Rule 20.12] )\r
+ -deprecate( function, clock, [MISRA 2004 Rule 20.12] )\r
+ -deprecate( function, difftime, [MISRA 2004 Rule 20.12] )\r
+ -deprecate( function, mktime, [MISRA 2004 Rule 20.12] )\r
+\r
+/* Rule 21.1 (req) *********************************/\r
+\r
+ /* achieved by using PC-lint/FlexeLint */\r
--- /dev/null
+#ifndef CO_GCC_H_\r
+#define CO_GCC_H_\r
+\r
+#ifdef _lint /* Make sure no compiler comes this way */\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Standard library headers typically define the assert macro so that it\r
+ expands to a complicated conditional expression that uses special\r
+ funtions that Lint does not know about by default. For linting\r
+ purposes, we can simplify things a bit by forcing assert() to expand to\r
+ a call to a special function that has the appropriate 'assert'\r
+ semantics.\r
+ */\r
+//lint -function( __assert, __lint_assert )\r
+void __lint_assert( int );\r
+//lint ++d"assert(e)=__lint_assert(!!(e))"\r
+//(++d makes this definition permanently immutable for the Lint run.)\r
+//Now that we've made our own 'assert', we need to keep people from being\r
+//punished when the marco in 'assert.h' appears not to be used:\r
+//lint -efile(766,*assert.h)\r
+\r
+/*\r
+ The headers included below must be generated; For C++, generate\r
+ with:\r
+\r
+ g++ [usual build options] -E -dM t.cpp >lint_cppmac.h\r
+\r
+ For C, generate with:\r
+\r
+ gcc [usual build options] -E -dM t.c >lint_cmac.h\r
+\r
+ ...where "t.cpp" and "t.c" are empty source files.\r
+\r
+ It's important to use the same compiler options used when compiling\r
+ project code because they can affect the existence and precise\r
+ definitions of certain predefined macros. See gcc-readme.txt for\r
+ details and a tutorial.\r
+ */\r
+#if defined(__cplusplus)\r
+# include "lint_cppmac.h"\r
+#else\r
+# include "lint_cmac.h"\r
+#endif\r
+\r
+/* If the macro set given by the generated macro files must be adjusted in\r
+ order for Lint to cope, then you can make those adjustments here.\r
+ */\r
+\r
+#define LINT_CO_GCC_H_GCC_VERSION ( __GNUC__ * 10000 + \\r
+ __GNUC_MINOR__ * 100 + \\r
+ __GNUC_PATCHLEVEL__ )\r
+\r
+/* The following is a workaround for versions of GCC with bug 25717, in\r
+ which the preprocessor does not dump a #define directive for __STDC__\r
+ when -dM is given:\r
+ http://gcc.gnu.org/bugzilla/show_bug.cgi?id=25717\r
+\r
+ We know the unconditional definition of __STDC__ was introduced no\r
+ later than version 3.0; the preprocessor bug was fixed no later than\r
+ version 4.1.0.\r
+ */\r
+#if ( LINT_CO_GCC_H_GCC_VERSION >= 30000 && \\r
+ LINT_CO_GCC_H_GCC_VERSION < 40100 )\r
+# define __STDC__ 1\r
+#endif\r
+\r
+\r
+#if LINT_CO_GCC_H_GCC_VERSION >= 40300\r
+# define __COUNTER__ __lint__COUNTER__\r
+//lint +rw( *type_traits ) // Enable type traits support\r
+#endif\r
+\r
+\r
+#ifdef __cplusplus\r
+} /* extern "C" */\r
+#endif\r
+#endif /* _lint */\r
+#endif /* CO_GCC_H_ */\r
--- /dev/null
+/* co-gcc.lnt: This is the seed file for configuring Lint for use with\r
+ GCC versions 2.95.3 and later.\r
+\r
+ Like all compiler options files this file is intended to be used\r
+ as follows:\r
+\r
+ lint co-gcc.lnt source-files-to-be-linted\r
+\r
+ Some of the information that co-gcc.lnt requires needs to be furnished\r
+ with the help of the gcc system itself. The easiest way to generate\r
+ this information is to use the makefile co-gcc.mak (supplied with the\r
+ Lint distribution) in an invocation of GNU Make; for details, see the\r
+ commentary at the top of co-gcc.mak.\r
+*/\r
+\r
+-cgnu // Notifies FlexeLint that gcc is being used.\r
+\r
+// ===========================\r
+// Preprocessor Configuration:\r
++fdi // GCC starts its #include search in the directory of the including\r
+ // file.\r
+\r
+++fln // Allow:\r
+ // # digit-sequence " [s-char-sequence] " new-line\r
+ // as a synonym for:\r
+ // # line digit-sequence " [s-char-sequence] " new-line\r
+ // GCC additionally allows flag values to follow the\r
+ // s-char-sequence, but currently Lint ignores them.\r
+\r
+-header(co-gcc.h) // Includes headers generated by GCC (bringing in\r
+ // predefined macros).\r
++libh(co-gcc.h) // Marks that header as library code.\r
+\r
+// gcc-include-path.lnt // This .lnt file should contain --i options\r
+ // and should be generated by invoking gcc with its '-v' option.\r
+ // (GCC's implicit #include search path is presented in the output.)\r
+ // This happens automatically when 'make -f co-gcc.mak' is invoked.\r
+\r
+// Assertion directives (a feature of GCC's preprocessor) have been\r
+// considered obsolete in GCC's documentation since version 3.0, so we do\r
+// not use them here. If support for #assert is needed in the form of a\r
+// lint option, one may use '-a#' like so:\r
+// -a#machine(i386) // #assert's machine(i386) (SVR4 facility).\r
+\r
+//+cpp(.cc,.C) // extensions for C++ that are commonly used in addition\r
+ // to the default extensions of .cpp and .cxx\r
+\r
+\r
+// =============\r
+// Size Options:\r
+// +fwc // wchar_t might be builtin; if so, uncomment this option. (NOTE:\r
+// // this option needs to be set before a size option is given for\r
+// // wchar_t; see the documentation for -sw# in the Lint manual.)\r
+\r
+size-options.lnt // This .lnt file should be generated (preferrably\r
+ // by a program created by invoking GCC with the compile options that\r
+ // are used in the compilation of the project to be linted). This\r
+ // happens automatically when 'make -f co-gcc.mak' is invoked.\r
+\r
+\r
+// ===========================================\r
+// +rw and -d options to cope with GNU syntax:\r
++ppw(ident) // Tolerate #ident\r
++ppw(warning)\r
+\r
+// GCC provides alternative spellings of certain keywords:\r
+-rw_asgn(__inline,inline)\r
+-rw_asgn(__inline__,inline)\r
+-rw_asgn(__signed__,signed)\r
+-rw_asgn(__signed,signed)\r
+-rw_asgn( __volatile__, volatile )\r
+-rw_asgn( __volatile, volatile )\r
+++d__const=const // gconv.h uses __const rather than const\r
+++dconst=const // ensure const expands to const.\r
+\r
+-rw_asgn( asm, _up_to_brackets )\r
+-rw_asgn( __asm, _up_to_brackets )\r
+-rw_asgn( __asm__, _up_to_brackets )\r
+// This re-definition of the various spellings of the asm keyword enables\r
+// Lint to pass gracefully over expression-statements like:\r
+// __asm __volatile ("fsqrt" : "=t" (__result) : "0" (__x));\r
+// But it may be necessary to suppress certain error messages that are\r
+// triggered by tokens that are part of an assembly declaration or\r
+// statement. For example:\r
+\r
+ -d"__asm__(p...)=/*lint -e{19}*/ __asm__(p)"\r
+\r
+// ...causes Lint to be quiet about the semicolon that follows an\r
+// __asm__() declaration. Note, the -e{N} form of suppression takes\r
+// effect only for the forward-declaration, definition or\r
+// [possibly-compound] statement that immediately follows. Because a\r
+// semicolon is seen as a declaration-terminator, Error 19 will be\r
+// re-enabled immediately after the semicolon in '__asm__(...);'.\r
+// (The elipsis after the macro parameter p allows zero or more commas to\r
+// appear in the operand.)\r
+//\r
+// If you encounter other diagnostics that appear to need suppression in\r
+// or near assembly regions, please let us know!\r
+//\r
+-esym(123,__asm__)\r
+\r
+-rw_asgn(__alignof__,__alignof)\r
+\r
+++d__attribute__()= // ignore this keyword and following parenthetical\r
+++d__attribute()= // variant spelling of "__attribute__"\r
+\r
+// "__extension__" is GCC's way of allowing the use of non-standard\r
+// constructs in a strict Standard-conforming mode. We don't currently\r
+// have explicit support for it, but we can use local suppressions. For\r
+// example, we can use -e(160) so that we will not see any Errors about\r
+// GNU statement-expressions wrapped in __extension__().\r
+++d"__extension__=/*lint -e(160) */"\r
+\r
+++d__builtin_va_list=void* // used by stdarg.h\r
+++d__builtin_stdarg_start()=_to_semi // ditto\r
+++d__builtin_va_end()=_to_semi // ditto\r
+++d"__builtin_va_arg(a,b)=(*( (b *) ( ((a) += sizeof(b)) - sizeof(b) )))"\r
+++d__null=0\r
++rw(_to_semi) // needed for the two macros above.\r
++rw(__typeof__) // activate __typeof__ keyword\r
+-d__typeof=__typeof__ // an alternative to using __typeof__\r
+\r
++rw( __restrict )\r
++rw( __restrict__ )\r
+-rw(__except) // This MS reserved word is used as an identifier\r
++rw( __complex__, __real__, __imag__ ) // reserved words that can be ignored.\r
+++d__builtin_strchr=(char*) // permits the inline definition ...\r
+++d__builtin_strpbrk=(char*) // of these functions to be linted ...\r
+++d__builtin_strrchr=(char*) // without drawing a complaint\r
+++d__builtin_strstr=(char*) // about the use of a non-standard name\r
+++d__PRETTY_FUNCTION__=___function___ // lint defines ___function___ internally\r
+++d__FUNCTION__=___function___ // lint defines ___function___ internally\r
+++d__func__=___function___ // Some C++ modes suport the implicit __func__\r
+ // identifier.\r
+\r
+// =========================================================\r
+// Other options supporting GNU C/C++ syntax:\r
++fld // enables the processing of _L_abel _D_esignators E.g.:\r
+ // union { double d; int i; } u = { d: 3.141 };\r
+\r
+// =========================================================\r
+// Generally useful suppressions:\r
+-wlib(1) // sets the warning level within library headers to 1\r
+ // (no warnings, just syntax errors). Comment out if you\r
+ // are actually linting library headers.\r
+-elib(123) // 123 is really a warning, but it's in the "Error" range.\r
+-elib(93) // allow newlines within quoted string arguments to macros\r
+-elib(46) // allow bit fields to have integral types other than\r
+ // '_Bool' and 'int'.\r
+-elibsym(628) // Suppress 628 for __builtin symbols.\r
+\r
+-esym(528,__huge_val,__nan,__qnan,__qnanf,__snan,__snanf)\r
+ // We don't care if we don't reference some GNU functions\r
+-esym(528,__gnu_malloc,__gnu_calloc)\r
+\r
+// The following functions exhibit variable return modes.\r
+// That is, they may equally-usefully be called for a value\r
+// as called just for their effects. Accordingly we inhibit\r
+// Warning 534 for these functions.\r
+// Feel free to add to or subtract from this list.\r
+\r
+-esym(534,close,creat,fclose,fprintf,fputc)\r
+-esym(534,fputs,fscanf,fseek,fwrite,lseek,memcpy,memmove,memset)\r
+-esym(534,printf,puts,scanf,sprintf,sscanf,strcat,strcpy)\r
+-esym(534,strncat,strncpy,unlink,write)\r
+\r
+// For non-ANSI compilers we suppress messages 515 and 516\r
+// for functions known to have variable argument lists.\r
+// For ANSI compilers, header files should take care of this.\r
+\r
+-esym(515,fprintf,printf,sprintf,fscanf,scanf,sscanf)\r
+-esym(516,fprintf,printf,sprintf,fscanf,scanf,sscanf)\r
+-esym(1702,*operator<<,*operator>>)\r
+-esym(534,*operator<<,*operator>>)\r
+-esym(1055,*__builtin*)\r
+-esym(718,*__builtin*) // The compiler does not need these ...\r
+-esym(746,*__builtin*) // declared and it knows their prototypes.\r
--- /dev/null
+#define __DBL_MIN_EXP__ (-1021)\r
+#define __FLT_MIN__ 1.17549435e-38F\r
+#define __CHAR_BIT__ 8\r
+#define __WCHAR_MAX__ 2147483647\r
+#define __DBL_DENORM_MIN__ 4.9406564584124654e-324\r
+#define __FLT_EVAL_METHOD__ 0\r
+#define __DBL_MIN_10_EXP__ (-307)\r
+#define __FINITE_MATH_ONLY__ 0\r
+#define __GNUC_PATCHLEVEL__ 2\r
+#define __INTMAX_TYPE__ long long int\r
+#define __SHRT_MAX__ 32767\r
+#define __LDBL_MAX__ 1.7976931348623157e+308L\r
+#define __UINTMAX_TYPE__ long long unsigned int\r
+#define __CHAR_UNSIGNED__ 1\r
+#define __LDBL_MAX_EXP__ 1024\r
+#define __SCHAR_MAX__ 127\r
+#define __USER_LABEL_PREFIX__ \r
+#define __STDC_HOSTED__ 1\r
+#define __LDBL_HAS_INFINITY__ 1\r
+#define __DBL_DIG__ 15\r
+#define __FLT_EPSILON__ 1.19209290e-7F\r
+#define _CALL_SYSV 1\r
+#define __LDBL_MIN__ 2.2250738585072014e-308L\r
+#define __DECIMAL_DIG__ 17\r
+#define __LDBL_HAS_QUIET_NAN__ 1\r
+#define __GNUC__ 4\r
+#define __NO_LWSYNC__ 1\r
+#define __DBL_MAX__ 1.7976931348623157e+308\r
+#define __DBL_HAS_INFINITY__ 1\r
+#define __DBL_MAX_EXP__ 1024\r
+#define __LONG_LONG_MAX__ 9223372036854775807LL\r
+#define __PPC__ 1\r
+#define __GXX_ABI_VERSION 1002\r
+#define __FLT_MIN_EXP__ (-125)\r
+#define __DBL_MIN__ 2.2250738585072014e-308\r
+#define __DBL_HAS_QUIET_NAN__ 1\r
+#define __REGISTER_PREFIX__ \r
+#define __NO_INLINE__ 1\r
+#define _ARCH_PPC 1\r
+#define __FLT_MANT_DIG__ 24\r
+#define __VERSION__ "4.1.2"\r
+#define __embedded__ 1\r
+#define __BIG_ENDIAN__ 1\r
+#define _BIG_ENDIAN 1\r
+#define __SIZE_TYPE__ unsigned int\r
+#define __ELF__ 1\r
+#define __FLT_RADIX__ 2\r
+#define __LDBL_EPSILON__ 2.2204460492503131e-16L\r
+#define __LDBL_DIG__ 15\r
+#define __FLT_HAS_QUIET_NAN__ 1\r
+#define __FLT_MAX_10_EXP__ 38\r
+#define __LONG_MAX__ 2147483647L\r
+#define __FLT_HAS_INFINITY__ 1\r
+#define __PPC 1\r
+#define __SPE__ 1\r
+#define __LDBL_MANT_DIG__ 53\r
+#define __WCHAR_TYPE__ long int\r
+#define __NO_FPRS__ 1\r
+#define __FLT_DIG__ 6\r
+#define __INT_MAX__ 2147483647\r
+#define __FLT_MAX_EXP__ 128\r
+#define __DBL_MANT_DIG__ 53\r
+#define __WINT_TYPE__ unsigned int\r
+#define __LDBL_MIN_EXP__ (-1021)\r
+#define __LDBL_MAX_10_EXP__ 308\r
+#define __DBL_EPSILON__ 2.2204460492503131e-16\r
+#define PPC 1\r
+#define __INTMAX_MAX__ 9223372036854775807LL\r
+#define __FLT_DENORM_MIN__ 1.40129846e-45F\r
+#define __FLT_MAX__ 3.40282347e+38F\r
+#define __FLT_MIN_10_EXP__ (-37)\r
+#define __GNUC_MINOR__ 1\r
+#define __DBL_MAX_10_EXP__ 308\r
+#define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L\r
+#define __STDC__ 1\r
+#define __PTRDIFF_TYPE__ int\r
+#define __LDBL_MIN_10_EXP__ (-307)\r
--- /dev/null
+-ss2
+-si4
+-sl4
+-sll8
+-sf4
+-sd8
+-sld8
+-sp4
+
--- /dev/null
+// Gnu C/C++ (version 2.95.3 or later), -si4 -sp4, \r
+// Standard lint options\r
+\r
+//c:\lint\au-misra2.lnt //To check MISRA C rules\r
+//c:\lint\lnt\co-gcc.lnt\r
+\r
+au-misra2.lnt //To check MISRA C rules\r
+lnt\co-gcc.lnt\r
+\r
+//c:\lint\options.lnt -si4 -sp4\r
+\r
+\r
+// EIJAS STUFF:\r
+-u //unit-checkout since not checking the test-files. Supresses the inter-module\r
+ //messages 526,552,628,714.720,755-759,765,768-769,948,974,1526-1527,1711,1714-1715,1755\r
+\r
+-zero //always return exit code 0 (avoiding makefile interruption)\r
+\r
+// SET WARNING LEVEL:\r
+-w3 //-wlib(0)// 1:only errors, 2: +warnings 3: + infos\r
+\r
+//Reset which files are viewed library-files to only treat <> as such\r
++libclass(angle)\r
+\r
+//+os(lintOutput.TMP) //append output to file\r
+//+oe(lintErrorOutput.TMP)//append error output to file\r
+\r
+//MESSAGE FORMAT:\r
++ffn // force full path names\r
+-width(0) // don't insert line breaks (unlimited output width).\r
+-hf1 // message height one\r
+-format=%f:%l:%c:\s%t:\s%n\sPC-lint:\s%m\r
+\r
+\r
+\r
+\r
+\r
+-A(C99)//use C99 standard\r
+\r
++fie // Use to view enums as ints (tar bort tex PC641)\r
+\r
+\r
+// RULES TO TURN OFF (diskussed and confirmed)\r
+//-efile(755,*.h)\r
+-e755 //e switch off for header files\r
+-e756 //e switch off for header files\r
+-e757 //e switch off for header files\r
+-e758 //e switch off for header files\r
+-e768 //e switch off for header files\r
+-e769 //e switch off for header files\r
+\r
+-e537 //e switch off (unjustified complain about 19.15)\r
+\r
+-esym(961, 19.7) //Advisory Rule that should be switched off\r
+-esym(961, 19.13)//Advisory Rule that should be switched off\r
+\r
+\r
+-esym(960, 10.1) //implicit conversion...\r
+-esym(960,18.4) // Unions shall not be used.\r
+-e621 //Complains about identifiers names longer than _ characters. Length set by -idlen(). [1.4, 5.1] OK in autosar.\r
+\r
+-e766 //Header file not used in module...\r
+\r
+// Rules ok to remove by autosar:\r
+// [1.4, 5.1](621), 8.10, 12.10, 11.1-11.5, 14.3(960).\r
+-esym(960,14.3)\r
+\r
+\r
+// RULES MAYBE TO TURN OFF\r
+//-e534 //only turned of for OS, printf? kolla hur vanlig...\r
+//-e757\r
+//-e526 vad betyder detta fel?\r
+\r
+\r
+// RULES THAT MAY BE SWITCHED OFF LOCALLY\r
+// * 13.7, 14.1 Constant value boolean \r
+// * 14.2 \r
+\r
+// RULES TO DISCUSS IF TO SWITCH OFF OR NOT\r
+-esym(961,12.6)//Advisory Rule (Boolean expression required for operator...)\r
+-esym(961,12.13)//Advisory Rule (++, -- not with other operators...)\r
+-esym(961,12.1)\r
+\r
+-e830 //location cited in prior message\r
+-e831 //reference cited in prior message\r
+\r
+-e788 // PC-Lint message: Enum constant 'Symbol' not used within defaulted switch\r
+\r
+-esym(960, 16.9) // Function identifier used without '&'\r
+\r
+\r
+// RULES TO TURN OFF FOR OLD MODULES, but think of them when having new modules\r
+-esym(960,17.4) // To many messages to be possible to handle locally!\r
+\r
+\r
+// ERRORS SWITCHED OFF TEMPORARLY\r
+//-e525\r
+//-e526\r
+\r
+//-esym(960, 10.1) //implicit conversion....\r
+//-e714 //Symbol not referenced\r
+//-e715 //Symbol not referenced\r
+\r
+//-esym(960, 12.5) //Non-primary expression used with logical operator.\r
+\r
+//-e785 // Too few initializers for aggregate ...\r
$(foreach mod,$(MOD_AVAIL),$(eval $(call MOD_AVAIL_template,${mod})))\r
$(foreach mod,$(MOD_USE),$(eval $(call MOD_USE_template,${mod})))\r
$(foreach mod,$(CFG),$(eval $(call CFG_template,${mod})))\r
-def-y += $(ARCH) $(ARCH_FAM) $(ARCH_MCU) \r
+#def-y += $(ARCH) $(ARCH_FAM) $(ARCH_MCU) \r
\r
# Select console / debug\r
$(foreach mod,$(SELECT_OS_CONSOLE),$(eval $(call MOD_USE_template,${mod})))\r
SELECT_OPT=OPT_DEBUG\r
endif\r
\r
-CFG_$(SELECT_OPT)=y\r
+$(eval CFG_$(SELECT_OPT)=y)\r
\r
ARCH_PATH-y = arch/$(ARCH_FAM)/$(ARCH)\r
\r
include $(ROOTDIR)/$(ARCH_PATH-y)/scripts/gcc.mk\r
endif\r
include $(ROOTDIR)/scripts/cc_$(COMPILER).mk\r
+ifneq ($(PCLINT),)\r
+include $(ROOTDIR)/scripts/cc_pclint.mk\r
+endif\r
+ifneq ($(SPLINT),)\r
+include $(ROOTDIR)/scripts/cc_splint.mk\r
+endif\r
+\r
+\r
\r
# Get object files\r
include ../makefile\r
\r
+\r
+##### For backwards compatability with older project makefiles\r
+# Remove dependency on libkernel\r
+deprecated-libs += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+deprecated-libs-included = $(filter $(deprecated-libs),$(libitem-y))\r
+ifneq ($(deprecated-libs-included),)\r
+$(info >>>> Ignoring deprecated lib dependencies: $(deprecated-libs-included)')\r
+libitem-y := $(filter-out $(deprecated-libs),$(libitem-y))\r
+endif\r
+\r
+# Automatic preprocessing of std linkscripts\r
+old-ldcmdfile = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+new-ldcmdfile = linkscript_gcc.ldp\r
+old-ldcmdfile-used = $(filter $(old-ldcmdfile),$(ldcmdfile-y))\r
+ifneq ($(old-ldcmdfile-used),)\r
+$(info >>>> Changing linkscript to preprocessed version: $(old-ldcmdfile) -> $(new-ldcmdfile)')\r
+ldcmdfile-y := $(subst $(old-ldcmdfile),$(new-ldcmdfile),$(ldcmdfile-y))\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+endif\r
+\r
+#####\r
+\r
inc-y += $(ROOTDIR)/include\r
-#inc-$(CFG_PPC) += $(ROOTDIR)/include/ppc\r
-#inc-$(CFG_ARM) += $(ROOTDIR)/include/arm\r
inc-y += $(ROOTDIR)/include/$(ARCH_FAM)\r
+inc-y += $(ROOTDIR)/include/$(ARCH_FAM)/$(ARCH)\r
\r
-.PHONY config:\r
\r
-config:\r
+.PHONY clean: \r
+clean: FORCE\r
+ @-rm -f *.o *.d *.h *.elf *.a *.ldp\r
+\r
+.PHONY config: \r
+config: FORCE\r
@echo "board modules:" $(MOD_AVAIL)\r
@echo "example modules:" $(MOD_USE)\r
@echo $(MOD) ${def-y}\r
\r
+FORCE:\r
\r
$(ROOTDIR)/binaries:\r
@mkdir -p $@\r
\r
# build- targets are "end" target that the included makefile want's to build\r
-all: $(build-exe-y) $(build-hex-y) $(build-lib-y) $(ROOTDIR)/binaries\r
- @cp -v $(build-lib-y) $(build-exe-y) $(build-hex-y) $(ROOTDIR)/binaries\r
+.PHONY all:\r
+all: $(build-exe-y) $(build-hex-y) $(build-lib-y) $(build-bin-y) $(ROOTDIR)/binaries\r
+ @cp -v $(build-lib-y) $(build-exe-y) $(build-hex-y) $(build-bin-y) $(ROOTDIR)/binaries\r
\r
-#.PHONY post_process:\r
-#post_process:: $(ROOTDIR)/binaries\r
- \r
\r
# Determine what kind of filetype to build from \r
VPATH += $(ROOTDIR)/$(SUBDIR)/src\r
# Some dependency for xxx_offset.c/h also\r
-include $(subst .h,.d,$(dep-y))\r
\r
+#LINT:\r
+LINT_EXCLUDE_PATHS := $(abspath $(LINT_EXCLUDE_PATHS))\r
+$(info $(LINT_EXCLUDE_PATHS))\r
+\r
+LINT_BAD_EXCLUDE_PATHS := $(filter %/,$(LINT_EXCLUDE_PATHS))\r
+ifneq ($(LINT_BAD_EXCLUDE_PATHS),)\r
+$(warning LINT_EXCLUDE_PATHS entries must not end in '/'. Ignoring $(LINT_BAD_EXCLUDE_PATHS))\r
+endif\r
+\r
+LINT_NICE_EXCLUDE_PATHS := $(filter-out %/,$(LINT_EXCLUDE_PATHS))\r
+LINT_NICE_EXCLUDE_PATHS := $(foreach path,$(LINT_NICE_EXCLUDE_PATHS),$(path)/)\r
+\r
+ifneq ($(PCLINT),)\r
+define run_pclint\r
+$(if \r
+$(filter $(dir $(abspath $<)),$(LINT_NICE_EXCLUDE_PATHS)),\r
+$(info $(abspath $<):0:0: Info: Not running lint check on $(abspath $<)),\r
+$(Q)$(PCLINT) $(lint_extra) $(addprefix $(lintinc_ext),$(inc-y)) $(addprefix $(lintdef_ext),$(def-y)) $(abspath $<))\r
+endef\r
+endif\r
+\r
+ifneq ($(SPLINT),)\r
+define run_splint\r
+$(if \r
+$(filter $(dir $(abspath $<)),$(LINT_NICE_EXCLUDE_PATHS)),\r
+$(info $(abspath $<):0:0: Info: Not running lint check on $(abspath $<)),\r
+$(Q)$(SPLINT) $(splint_extra) $(addprefix $(lintinc_ext),$(inc-y)) $(addprefix $(lintdef_ext),$(def-y)) $(abspath $<))\r
+endef\r
+endif\r
+\r
+\r
# Compile\r
%.o: %.c\r
@echo " >> CC $(notdir $<)"\r
+# compile\r
$(Q)$(CC) -c $(CFLAGS) -o $(goal) $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $(abspath $<)\r
+# run lint if enabled\r
+ $(run_pclint)\r
+ $(run_splint)\r
\r
# Assembler\r
\r
$(Q)$(CPP) -x assembler-with-cpp -E -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
\r
\r
+# Board linker files are in the board directory \r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+\r
+# Preprocess linker files..\r
+%.ldp: %.ldf\r
+ @echo " >> CPP $<"\r
+ $(Q)$(CPP) -E -P -x assembler-with-cpp -o $@ $(addprefix -I ,$(inc-y)) $(addprefix -D,$(def-y)) $<\r
+\r
# @cat $@ \r
\r
.PHONY $(ROOTDIR)/libs:\r
$(build-hex-y): $(build-exe-y)\r
@echo " >> OBJCOPY $@" \r
$(Q)$(CROSS_COMPILE)objcopy -O ihex $< $@\r
+ \r
+$(build-bin-y): $(build-exe-y)\r
+ @echo " >> OBJCOPY $@" \r
+ $(Q)$(CROSS_COMPILE)objcopy -O binary $< $@ \r
\r
+# Linker\r
# Could use readelf -S instead of parsing the *.map file.\r
$(build-exe-y): $(dep-y) $(obj-y) $(sim-y) $(libitem-y) $(ldcmdfile-y)\r
@echo " >> LD $@"\r
+ifeq ($(CROSS_COMPILE),)\r
+ $(Q)$(CC) $(LDFLAGS) -o $@ $(libpath-y) $(obj-y) $(lib-y) $(libitem-y) \r
+else \r
$(Q)$(LD) $(LDFLAGS) -T $(ldcmdfile-y) -o $@ $(libpath-y) --start-group $(obj-y) $(lib-y) $(libitem-y) --end-group $(LDMAPFILE)\r
ifdef CFG_MC912DG128A\r
@$(CROSS_COMPILE)objdump -h $@ | gawk -f $(ROOTDIR)/scripts/hc1x_memory.awk\r
/^\.data/ { print " data:" $$3+0 " bytes"; rom+=$$3; ram+=$$3}; \\r
/^\.bss/ { print " bss :" $$3+0 " bytes"; ram+=$$3}; \\r
END { print " ROM: ~" rom " bytes"; print " RAM: ~" ram " bytes"}' $(subst .elf,.map,$@)\r
+ifeq ($(BUILD_LOAD_MODULE),y)\r
+ @$(CROSS_COMPILE)objcopy -O srec $@ $@.raw.s19\r
+ srec_cat $@.raw.s19 --crop 0x8008000 0x803fffc --fill 0x00 0x8008000 0x803fffc --l-e-crc32 0x803fffc -o $@.lm.s19\r
+endif\r
endif\r
+endif\r
+ @echo\r
@echo " >>>>>>> DONE <<<<<<<<<"\r
+ @echo\r
+ \r
\r
-\r
$(size-exe-y): $(build-exe-y)\r
$(Q)$(OBJDUMP) -h $<\r
@echo TODO: Parse the file....\r
\r
-.PHONY clean:\r
- @-rm -f *.o *.d *.h *.elf *.a\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
+//lint -emacro(904,VALIDATE,VALIDATE_RV,VALIDATE_NO_RV) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
\r
#include "EcuM.h"\r
#include "Modules.h"\r
-#include "string.h"\r
+#include <string.h>\r
#include "Os.h"\r
#include "EcuM_Internals.h"\r
#include "EcuM_Cbk.h"\r
#include "Mcu.h"\r
#include "Det.h"\r
#include "irq.h"\r
+#if defined(USE_NVM)\r
+#include "Nvm.h"\r
+#endif\r
+#if defined(USE_RTE)\r
+#include "Rte_Main.h"\r
+#endif\r
\r
EcuM_GobalType internal_data;\r
\r
-#if ( ECUM_VERSION_INFO_API == STD_ON )\r
-static Std_VersionInfoType _EcuM_VersionInfo =\r
-{\r
- .vendorID = (uint16)1,\r
- .moduleID = (uint16)1,\r
- .instanceID = (uint8)1,\r
- .sw_major_version = (uint8)ECUM_SW_MAJOR_VERSION,\r
- .sw_minor_version = (uint8)ECUM_SW_MINOR_VERSION,\r
- .sw_patch_version = (uint8)ECUM_SW_PATCH_VERSION,\r
- .ar_major_version = (uint8)ECUM_AR_MAJOR_VERSION,\r
- .ar_minor_version = (uint8)ECUM_AR_MINOR_VERSION,\r
- .ar_patch_version = (uint8)ECUM_AR_PATCH_VERSION,\r
-};\r
-#endif\r
-\r
void EcuM_Init( void )\r
{\r
internal_data.current_state = ECUM_STATE_STARTUP_ONE;\r
// Enable interrupts\r
Irq_Init();\r
\r
-\r
// Determine PostBuild configuration\r
internal_data.config = EcuM_DeterminePbConfiguration();\r
\r
\r
// Set default application mode\r
internal_data.app_mode = internal_data.config->EcuMDefaultAppMode;\r
+#if defined(USE_COMM)\r
+ internal_data.run_comm_requests = 0;\r
+#endif\r
+ internal_data.run_requests = 0;\r
+ internal_data.postrun_requests = 0;\r
\r
internal_data.initiated = TRUE;\r
\r
StartOS(internal_data.app_mode);\r
}\r
\r
-void EcuM_StartupTwo()\r
+void EcuM_StartupTwo(void)\r
{\r
-#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
- uint32 timer;\r
+#if defined(USE_NVM)\r
+ extern CounterType Os_Arc_OsTickCounter;\r
+ TickType tickTimerStart, tickTimer, tickTimerElapsed;\r
+ StatusType tickTimerStatus;\r
+ static NvM_RequestResultType readAllResult;\r
#endif\r
\r
internal_data.current_state = ECUM_STATE_STARTUP_TWO;\r
// Initialize drivers that don't need NVRAM data\r
EcuM_AL_DriverInitTwo(internal_data.config);\r
\r
-#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
+#if defined(USE_NVM)\r
// Start timer to wait for NVM job to complete\r
- timer = Os_SysTickGetTimeElapsed();\r
+ tickTimerStatus = GetCounterValue(Os_Arc_OsTickCounter , &tickTimerStart);\r
+ if (tickTimerStatus != E_OK) {\r
+ // TODO: Generate error?\r
+ }\r
#endif\r
\r
// Prepare the system to startup RTE\r
// TODO EcuM_OnRTEStartup();\r
+#if defined(USE_RTE)\r
+ Rte_Start();\r
+#endif\r
\r
- //Rte_Start();\r
-\r
-#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
- // Wait for the NVM job to terminate\r
- while(Os_SysTickGetTimeElapsed()-timer < internal_data.config.EcuMNvramReadAllTimeout)\r
- {\r
- //TODO\r
- }\r
+#if defined(USE_NVM)\r
+ // Wait for the NVM job (NvmReadAll) to terminate\r
+ do {\r
+ NvM_GetErrorStatus(0, &readAllResult); // Read the multiblock status\r
+ tickTimer = tickTimerStart; // Save this because the GetElapsedCounterValue() will destroy it.\r
+ tickTimerStatus = GetElapsedCounterValue(Os_Arc_OsTickCounter, &tickTimer, &tickTimerElapsed);\r
+ if (tickTimerStatus != E_OK) {\r
+ // TODO: Generate error?\r
+ }\r
+ } while( (readAllResult == NVM_REQ_PENDING) && (tickTimerElapsed < internal_data.config->EcuMNvramReadAllTimeout) );\r
#endif\r
\r
// Initialize drivers that need NVRAM data\r
\r
// Indicate mode change to RTE\r
// TODO\r
+\r
+ // If coming from startup sequence, enter Run mode\r
+// if (internal_data.current_state == ECUM_STATE_STARTUP_TWO)\r
+ EcuM_enter_run_mode();\r
+\r
}\r
\r
// Typically called from OS shutdown hook\r
-void EcuM_Shutdown()\r
+void EcuM_Shutdown(void)\r
{\r
internal_data.current_state = ECUM_STATE_GO_OFF_TWO;\r
\r
#if (MCU_PERFORM_RESET_API == STD_ON)\r
Mcu_PerformReset();\r
#else\r
- for(;;);\r
+ for(;;)\r
+ {\r
+ ;\r
+ }\r
#endif\r
}\r
}\r
\r
Std_ReturnType EcuM_GetState(EcuM_StateType* state)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (state == NULL)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETSTATE_ID, ECUM_E_NULL_POINTER);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(state != NULL, ECUM_GETSTATE_ID, ECUM_E_NULL_POINTER, E_NOT_OK);\r
\r
*state = internal_data.current_state;\r
\r
\r
Std_ReturnType EcuM_SelectApplicationMode(AppModeType appMode)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_SELECTAPPMODE_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_SELECTAPPMODE_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
\r
// TODO Save this application mode for next startup\r
+ (void) appMode;\r
\r
return E_NOT_OK;\r
}\r
\r
Std_ReturnType EcuM_GetApplicationMode(AppModeType* appMode)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETAPPMODE_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-\r
- if (appMode == NULL)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GETAPPMODE_ID, ECUM_E_NULL_POINTER);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_GETAPPMODE_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(appMode != NULL, ECUM_GETAPPMODE_ID, ECUM_E_NULL_POINTER, E_NOT_OK);\r
\r
*appMode = internal_data.app_mode;\r
\r
\r
Std_ReturnType EcuM_SelectBootTarget(EcuM_BootTargetType target)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_SELECT_BOOTARGET_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_SELECT_BOOTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
\r
// TODO Do something great here\r
+ (void) target;\r
\r
return E_NOT_OK;\r
}\r
\r
Std_ReturnType EcuM_GetBootTarget(EcuM_BootTargetType* target)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data.initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GET_BOOTARGET_ID, ECUM_E_NOT_INITIATED);\r
- return E_NOT_OK;\r
- }\r
-\r
- if (target == NULL)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_GET_BOOTARGET_ID, ECUM_E_NULL_POINTER);\r
- return E_NOT_OK;\r
- }\r
-#endif\r
+ VALIDATE_RV(internal_data.initiated, ECUM_GET_BOOTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(target != NULL, ECUM_GET_BOOTARGET_ID, ECUM_E_NULL_POINTER, E_NOT_OK);\r
\r
// TODO Return selected boot target here\r
+ (void) target;\r
\r
return E_NOT_OK;\r
}\r
\r
-#if (ECUM_VERSION_INFO_API == STD_ON)\r
-void EcuM_GetVersionInfo(Std_VersionInfoType *versionInfo)\r
+\r
+Std_ReturnType EcuM_SelectShutdownTarget(EcuM_StateType target, uint8 mode)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_SELECTSHUTDOWNTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV((target == ECUM_STATE_OFF) || (target == ECUM_STATE_RESET) || (target == ECUM_STATE_SLEEP), ECUM_SELECTSHUTDOWNTARGET_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.shutdown_target = target;\r
+ internal_data.shutdown_mode = mode;\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType EcuM_GetShutdownTarget(EcuM_StateType *target, uint8 *mode)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_GETSHUTDOWNTARGET_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+\r
+ *target = internal_data.shutdown_target;\r
+ *mode = internal_data.shutdown_mode;\r
+\r
+ return E_OK;\r
+}\r
+\r
+\r
+Std_ReturnType EcuM_RequestRUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_REQUESTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_REQUESTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_requests |= (uint32)1 << user;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_ReleaseRUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_RELEASERUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_RELEASERUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_requests &= ~((uint32)1 << user);\r
+\r
+ return E_OK;\r
+}\r
+\r
+#if defined(USE_COMM)\r
+Std_ReturnType EcuM_ComM_RequestRUN(NetworkHandleType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_COMM_REQUESTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < 32, ECUM_COMM_REQUESTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_comm_requests |= (uint32)1 << user;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_ComM_ReleaseRUN(NetworkHandleType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_COMM_RELEASERUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < 32, ECUM_COMM_RELEASERUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.run_comm_requests &= ~((uint32)1 << user);\r
+\r
+ return E_OK;\r
+}\r
+\r
+boolean EcuM_ComM_HasRequestedRUN(NetworkHandleType user)\r
{\r
- memcpy(versionInfo, &_EcuM_VersionInfo, sizeof(Std_VersionInfoType));\r
+ VALIDATE_RV(internal_data.initiated, ECUM_COMM_HASREQUESTEDRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < 32, ECUM_COMM_HASREQUESTEDRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ return (internal_data.run_comm_requests &((uint32)1 << user)) != 0;\r
}\r
#endif\r
\r
+Std_ReturnType EcuM_RequestPOST_RUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_REQUESTPOSTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_REQUESTPOSTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.postrun_requests |= (uint32)1 << user;\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType EcuM_ReleasePOST_RUN(EcuM_UserType user)\r
+{\r
+ VALIDATE_RV(internal_data.initiated, ECUM_RELEASEPOSTRUN_ID, ECUM_E_NOT_INITIATED, E_NOT_OK);\r
+ VALIDATE_RV(user < ECUM_USER_ENDMARK, ECUM_RELEASEPOSTRUN_ID, ECUM_E_INVALID_PAR, E_NOT_OK);\r
+\r
+ internal_data.postrun_requests &= ~((uint32)1 << user);\r
+\r
+ return E_OK;\r
+}\r
+\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef ECUM_CFG_H_\r
-#define ECUM_CFG_H_\r
-\r
-#define ECUM_VERSION_INFO_API STD_ON\r
-#define ECUM_INCLUDE_NVRAM_MGR STD_OFF\r
-#define ECUM_DEV_ERROR_DETECT STD_ON\r
-\r
-#include "EcuM_Generated_Types.h"\r
-\r
-extern EcuM_ConfigType EcuMConfig;\r
-\r
-\r
-#endif /*ECUM_CFG_H_*/\r
#ifndef _ECUM_INTERNALS_H_\r
#define _ECUM_INTERNALS_H_\r
\r
+#if ( ECUM_DEV_ERROR_DETECT == STD_ON )\r
+#include "Det.h"\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_ECUM, 0, _api, _err); \\r
+ }\r
+\r
+#define VALIDATE_RV(_exp,_api,_err,_rv ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_ECUM, 0, _api, _err); \\r
+ return _rv; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_ECUM, 0, _api, _err); \\r
+ return; \\r
+ }\r
+#define DET_REPORTERROR(_module,_instance,_api,_err) Det_ReportError(_module,_instance,_api,_err)\r
+\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_RV(_exp,_api,_err,_rv )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_module,_instance,_api,_err)\r
+#endif\r
+\r
+\r
+\r
typedef struct\r
{\r
boolean initiated;\r
uint8 shutdown_mode;\r
AppModeType app_mode;\r
EcuM_StateType current_state;\r
+#if defined(USE_COMM)\r
+ uint32 run_comm_requests;\r
+#endif\r
+ uint32 run_requests;\r
+ uint32 postrun_requests;\r
} EcuM_GobalType;\r
\r
extern EcuM_GobalType internal_data;\r
\r
+void EcuM_enter_run_mode(void);\r
+\r
#endif /*_ECUM_INTERNALS_H_*/\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
+//lint -emacro(904,VALIDATE,VALIDATE_RV,VALIDATE_NO_RV) //904 PC-Lint exception to MISRA 14.7 (validate macros).\r
\r
+#include "EcuM.h"\r
+#include "EcuM_Cbk.h"\r
+#include "EcuM_Internals.h"\r
+#if defined(USE_DEM)\r
+#include "Dem.h"\r
+#endif\r
+#if defined(USE_NVM)\r
+#include "Nvm.h"\r
+#endif\r
\r
+static uint32 internal_data_run_state_timeout = 0;\r
+#if defined(USE_NVM)\r
+static uint32 internal_data_go_off_one_state_timeout = 0;\r
+#endif\r
\r
\r
+void EcuM_enter_run_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_APP_RUN;\r
+ EcuM_OnEnterRUN();\r
+ internal_data_run_state_timeout = internal_data.config->EcuMRunMinimumDuration / ECUM_MAIN_FUNCTION_PERIOD;\r
+}\r
\r
+static inline void enter_post_run_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_APP_POST_RUN;\r
+}\r
\r
+static inline void enter_prep_shutdown_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_PREP_SHUTDOWN;\r
+ EcuM_OnPrepShutdown();\r
+}\r
\r
-#include "EcuM.h"\r
-#include "EcuM_Internals.h"\r
+static inline void enter_go_sleep_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_GO_SLEEP;\r
+ EcuM_OnGoSleep();\r
+}\r
+\r
+static inline void enter_go_off_one_mode(void)\r
+{\r
+ internal_data.current_state = ECUM_STATE_GO_OFF_ONE;\r
+ EcuM_OnGoOffOne();\r
+\r
+#if defined(USE_COMM)\r
+ ComM_DeInit();\r
+#endif\r
+\r
+#if defined(USE_NVM)\r
+\r
+ // Start NvM_WriteAll and timeout timer\r
+ NvM_WriteAll();\r
+\r
+ internal_data_go_off_one_state_timeout = internal_data.config->EcuMNvramWriteAllTimeout / ECUM_MAIN_FUNCTION_PERIOD;\r
+#endif\r
+}\r
+\r
+static inline boolean hasRunRequests(void)\r
+{\r
+ uint32 result = internal_data.run_requests;\r
+\r
+#if defined(USE_COMM)\r
+ result |= internal_data.run_comm_requests;\r
+#endif\r
+\r
+ return (result != 0);\r
+}\r
+\r
+static inline boolean hasPostRunRequests(void)\r
+{\r
+ return (internal_data.postrun_requests != 0);\r
+}\r
\r
void EcuM_MainFunction(void)\r
{\r
-#if (ECUM_DEV_ERROR_DETECT == STD_ON)\r
- if (!internal_data->initiated)\r
- {\r
- Det_ReportError(MODULE_ID_ECUM, 1, ECUM_MAINFUNCTION_ID, ECUM_E_NOT_INITIATED);\r
- return;\r
- }\r
+#if defined(USE_NVM)\r
+static NvM_RequestResultType writeAllResult;\r
#endif\r
\r
- // If coming from startup sequence, enter Run mode\r
- if (internal_data->current_state == ECUM_STATE_STARTUP_TWO)\r
- enter_run_mode();\r
+VALIDATE_NO_RV(internal_data.initiated, ECUM_MAINFUNCTION_ID, ECUM_E_NOT_INITIATED);\r
\r
- if (internal_data->current_state == ECUM_STATE_APP_RUN)\r
+ if (internal_data.current_state == ECUM_STATE_APP_RUN)\r
{\r
- if (!hasRunRequests() && (internal_data_run_state_timeout == 0))\r
+ if (internal_data_run_state_timeout)\r
+ {\r
+ internal_data_run_state_timeout--;\r
+ }\r
+\r
+ if ((!hasRunRequests()) && (internal_data_run_state_timeout == 0))\r
{\r
+ EcuM_OnExitRun(); // ECUM_2865\r
enter_post_run_mode();\r
- return;\r
+ /*lint --e(904)*/ return;\r
}\r
}\r
\r
- if (internal_data->current_state == ECUM_STATE_APP_POST_RUN)\r
+ if (internal_data.current_state == ECUM_STATE_APP_POST_RUN)\r
{\r
if (hasRunRequests())\r
{\r
- enter_run_mode(); // ECUM_2866\r
- return;\r
+ EcuM_enter_run_mode(); // ECUM_2866\r
+ /*lint --e(904)*/ return;\r
}\r
\r
if (!hasPostRunRequests())\r
{\r
EcuM_OnExitPostRun(); // ECUM_2761\r
enter_prep_shutdown_mode();\r
- return;\r
+ /*lint --e(904)*/ return;\r
+ }\r
+ }\r
+\r
+ if (internal_data.current_state == ECUM_STATE_PREP_SHUTDOWN)\r
+ {\r
+#if defined(USE_DEM)\r
+ // DEM shutdown\r
+ Dem_Shutdown();\r
+#endif\r
+\r
+ // Switch shutdown mode\r
+ if ((internal_data.shutdown_target == ECUM_STATE_OFF) || (internal_data.shutdown_target == ECUM_STATE_RESET)) {\r
+ enter_go_off_one_mode();\r
+ }\r
+\r
+ if (internal_data.shutdown_target == ECUM_STATE_SLEEP) {\r
+ enter_go_sleep_mode();\r
+ }\r
+ }\r
+\r
+ if (internal_data.current_state == ECUM_STATE_GO_OFF_ONE)\r
+ {\r
+#if defined(USE_NVM)\r
+ if (internal_data_go_off_one_state_timeout)\r
+ internal_data_go_off_one_state_timeout--;\r
+\r
+ // Wait for the NVM job (NvmWriteAll) to terminate\r
+ NvM_GetErrorStatus(0, &writeAllResult);\r
+ if ((writeAllResult != NVM_REQ_PENDING) || (internal_data_go_off_one_state_timeout == 0))\r
+ {\r
+ ShutdownOS(E_OK);\r
}\r
+#else\r
+ ShutdownOS(E_OK);\r
+#endif\r
}\r
+\r
+ if (internal_data.current_state == ECUM_STATE_GO_SLEEP)\r
+ {\r
+ // TODO: Fill out\r
+ }\r
+\r
}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-/* Post Build time configuration */\r
-\r
-unsigned char ECUM_DEFAULT_APP_MODE = 0; \r
-unsigned char ECUM_DEFAULT_SHUTDOWN_TARGET = 0;\r
-unsigned char ECUM_RUN_SELF_REQUEST_PERIOD = 0;\r
#define COUNTER_MAX(x) (x)->counter->alarm_base.maxallowedvalue\r
#define COUNTER_MIN_CYCLE(x) (x)->counter->alarm_base.mincycle\r
#define ALARM_CHECK_ID(x) \\r
- if( (x) > Os_CfgGetAlarmCnt()) { \\r
+ if( (x) > OS_ALARM_CNT) { \\r
rv = E_OS_ID; \\r
goto err; \\r
}\r
rv = E_OS_VALUE;\r
goto err;\r
} else {\r
- if( Cycle == 0 ||\r
- (Cycle >= COUNTER_MIN_CYCLE(aPtr)) ||\r
- (Cycle <= COUNTER_MAX(aPtr)) ) {\r
- /* OK */\r
- } else {\r
+ if( Cycle != 0 &&\r
+ ( (Cycle < COUNTER_MIN_CYCLE(aPtr)) ||\r
+ (Cycle > COUNTER_MAX(aPtr)) ) ) {\r
/** @req OS304 */\r
rv = E_OS_VALUE;\r
goto err;\r
\r
OS_STD_END_3(OSServiceId_SetRelAlarm,AlarmId, Increment, Cycle);\r
}\r
+
+/**
+ * The system service occupies the alarm <AlarmID> element.
+ * When <start> ticks are reached, the task assigned to the alarm
+ *
+ * If the absolute value <start> is very close to the current counter
+ * value, the alarm may expire, and the task may become ready or
+ * the alarm-callback may be called before the system service
+ * returns to the user.
+ * If the absolute value <start> already was reached before the
+ * system call, the alarm shall only expire when the absolute value
+ * <start> is reached again, i.e. after the next overrun of the
+ * counter.
+ *
+ * If <cycle> is unequal zero, the alarm element is logged on again
+ * immediately after expiry with the relative value <cycle>.
+ *
+ * The alarm <AlarmID> shall not already be in use.
+ * To change values of alarms already in use the alarm shall be
+ * cancelled first.
+ *
+ * If the alarm is already in use, this call will be ignored and the
+ * error E_OS_STATE is returned.
+ *
+ * Allowed on task level and in ISR, but not in hook routines.
+ *
+ * @param AlarmId
+ * @param Start
+ * @param Cycle
+ * @return
+ */
\r
StatusType SetAbsAlarm(AlarmType AlarmId, TickType Start, TickType Cycle) {\r
\r
/** @req OS304 */\r
rv = E_OS_VALUE;\r
goto err;\r
- } else {\r
- if( Cycle == 0 ||\r
- (Cycle >= COUNTER_MIN_CYCLE(aPtr)) ||\r
- (Cycle <= COUNTER_MAX(aPtr)) ) {\r
- /* OK */\r
- } else {\r
- /** @req OS304 */\r
- rv = E_OS_VALUE;\r
- goto err;\r
- }\r
+ }\r
+\r
+ if( Cycle != 0 &&\r
+ ( (Cycle < COUNTER_MIN_CYCLE(aPtr)) ||\r
+ (Cycle > COUNTER_MAX(aPtr)) ) ) {\r
+ /** @req OS304 */\r
+ rv = E_OS_VALUE;\r
+ goto err;\r
}\r
\r
Irq_Save(flags);\r
if( aPtr->active == 1 ) {\r
- rv = E_OS_STATE;\r
+ rv = E_OS_STATE;
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
}\r
}\r
\r
+void Os_AlarmAutostart(void) {\r
+ int j;\r
+ for (j = 0; j < OS_ALARM_CNT; j++) {\r
+ OsAlarmType *alarmPtr;\r
+ alarmPtr = Os_CfgGetAlarmObj(j);\r
+ if (alarmPtr->autostartPtr != NULL) {\r
+ const OsAlarmAutostartType *autoPtr = alarmPtr->autostartPtr;\r
+\r
+ if (os_sys.appMode & autoPtr->appModeRef) {\r
+ if (autoPtr->autostartType == ALARM_AUTOSTART_ABSOLUTE) {\r
+ SetAbsAlarm(j, autoPtr->alarmTime, autoPtr->cycleTime);\r
+ } else {\r
+ SetRelAlarm(j, autoPtr->alarmTime, autoPtr->cycleTime);\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include <stdlib.h>\r
+#include "Os.h"\r
+\r
+#include "internal.h"\r
+#include "arc.h"\r
+#include "arch.h"\r
+\r
+\r
+StatusType GetActiveApplicationMode( AppModeType* mode) {\r
+ *mode = os_sys.appMode;\r
+ return E_OK;\r
+}\r
\r
void interrupt( void ) {\r
\r
- apa((void *)0x123);\r
+// apa((void *)0x123);\r
}\r
\r
\r
\r
}\r
\r
+int func3( int a ) {\r
+ if( a == 0) {\r
+ return 5;\r
+ }\r
+ return 4;\r
+}\r
+\r
int func2( void ) {\r
int a;\r
a = 3;\r
\r
func1(5);\r
+ func3(0);\r
\r
return 2;\r
}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#include "Os.h"\r
-#include "internal.h"\r
-\r
-/* Queued message\r
- * The messages are put in a queue. Copied to the destination...\r
- *\r
- * Unqueued message\r
- * Latest message in queue. Put the message in a container ref by message_id.\r
- * It's just a copy. The message can be read by "anyone" and as many times as you\r
- * would like\r
- *\r
- * Add new functions ??\r
- * SendMessageNoCopy( ) .. must have GetMsgApa().. this gets to be a resource lock... hmm\r
- *\r
- *\r
- *\r
- */\r
-\r
-StatusType SendMessage( MessageType message_id, ApplicationDataRef dataRef ) {\r
-\r
-\r
- OsMessageType *msg;\r
-\r
- // Is the message valid ?\r
- if( message_id > Os_CfgGetMessageCnt() ) {\r
- // TODO: Add error hook here\r
- return E_COM_ID;\r
- }\r
-\r
- if( msg->property != SEND_STATIC_INTERNAL ) {\r
- // TODO: Add error hook here\r
- return E_COM_ID;\r
- }\r
-\r
- // Copy the data to interal buffers\r
- msg = Os_CfgGetMessage(message_id);\r
-\r
- // copy data\r
- memcpy(msg->data,dataRef,msg->data_size);\r
-\r
-\r
-#if 0\r
- // Is it a queue message?\r
- switch( msg->notification ) {\r
- case MESSAGE_NOTIFICATION_ACTION_ACTIVATETASK:\r
- // TODO: Is this activatetask ???\r
- break;\r
- case MESSAGE_NOTIFICATION_ACTION_SETEVENT:\r
- // TODO:\r
- break;\r
- case MESSAGE_NOTIFICATION_ACTION_NONE:\r
- break;\r
- default:\r
- assert(0);\r
- break;\r
- }\r
-#endif\r
-\r
- return E_OK;\r
-}\r
-\r
-StatusType ReceiveMessage( MessageType message_id, ApplicationDataRef dataRef ) {\r
- OsMessageType *msg;\r
- // Check if valid\r
-\r
- // Copy from container to dataRef\r
- msg = Os_CfgGetMessage(message_id);\r
- memcpy(dataRef,msg->data,msg->data_size);\r
-\r
- return E_OK;\r
-}\r
-\r
-\r
-\r
#endif\r
\r
\r
-#define IsCounterValid(_counterId) ((_counterId) <= Os_CfgGetCounterCnt())\r
+#define IsCounterValid(_counterId) ((_counterId) <= OS_COUNTER_CNT)\r
\r
/**\r
*\r
StatusType IncrementCounter( CounterType counter_id ) {\r
StatusType rv = E_OK;\r
OsCounterType *cPtr;\r
+ uint32_t flags;\r
cPtr = Os_CfgGetCounter(counter_id);\r
\r
+ Irq_Save(flags);\r
/** @req OS376 */\r
if( !IsCounterValid(counter_id) ) {\r
rv = E_OS_ID;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
/* Check param */\r
/** @req OS285 */\r
if( ( cPtr->type != COUNTER_TYPE_SOFT ) ||\r
- ( counter_id >= Os_CfgGetCounterCnt() ) ) {\r
+ ( counter_id >= OS_COUNTER_CNT ) ) {\r
rv = E_OS_ID;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
/** @req OS286 */\r
cPtr->val = Os_CounterAdd( cPtr->val, Os_CounterGetMaxValue(cPtr), 1 );\r
\r
+#if OS_ALARM_CNT!=0\r
Os_AlarmCheck(cPtr);\r
+#endif\r
+#if OS_SCHTBL_CNT!=0\r
Os_SchTblCheck(cPtr);\r
+#endif\r
+\r
+ Irq_Restore(flags);\r
\r
/** @req OS321 */\r
COUNTER_STD_END;\r
cPtr->val = Os_CounterAdd( cPtr->val, Os_CounterGetMaxValue(cPtr), 1 );\r
\r
// os_sys.tick = cPtr->val;\r
-\r
+#if OS_ALARM_CNT!=0\r
Os_AlarmCheck(cPtr);\r
+#endif\r
+#if OS_SCHTBL_CNT!=0\r
Os_SchTblCheck(cPtr);\r
+#endif\r
}\r
}\r
\r
* Initialize alarms and schedule-tables for the counters\r
*/\r
void Os_CounterInit( void ) {\r
- OsCounterType *counter;\r
- OsAlarmType *alarm_obj;\r
- OsSchTblType *sched_obj;\r
- /* Create a list from the counter to the alarms */\r
- for(int i=0; i < Os_CfgGetCounterCnt() ; i++) {\r
- counter = Os_CfgGetCounter(i);\r
- // Alarms\r
- SLIST_INIT(&counter->alarm_head);\r
- for(int j=0; j < Os_CfgGetAlarmCnt(); j++ ) {\r
- alarm_obj = Os_CfgGetAlarmObj(j);\r
- // Add the alarms\r
- SLIST_INSERT_HEAD(&counter->alarm_head,alarm_obj, alarm_list);\r
- }\r
- // Schedule tables\r
- SLIST_INIT(&counter->sched_head);\r
- for(int j=0; j < Os_CfgGetSchedCnt(); j++ ) {\r
- sched_obj = Os_CfgGetSched(j);\r
- // Add the alarms\r
- SLIST_INSERT_HEAD(&counter->sched_head,\r
- sched_obj,\r
- sched_list);\r
+#if OS_ALARM_CNT!=0\r
+ {\r
+ OsCounterType *cPtr;\r
+ OsAlarmType *aPtr;\r
+\r
+ /* Add the alarms to counters */\r
+ for (int i = 0; i < OS_ALARM_CNT; i++) {\r
+ aPtr = Os_CfgGetAlarmObj(i);\r
+ cPtr = aPtr->counter;\r
+ SLIST_INSERT_HEAD(&cPtr->alarm_head, aPtr, alarm_list);\r
}\r
+ }\r
+#endif\r
\r
+#if OS_SCHTBL_CNT!=0\r
+ {\r
+ OsCounterType *cPtr;\r
+ OsSchTblType *sPtr;\r
\r
+ /* Add the schedule tables to counters */\r
+ for(int i=0; i < OS_SCHTBL_CNT; i++ ) {\r
+\r
+ sPtr = Os_CfgGetSched(i);\r
+ cPtr = sPtr->counter;\r
+ SLIST_INSERT_HEAD(&cPtr->sched_head, sPtr, sched_list);\r
+ }\r
}\r
+#endif\r
}\r
\r
OsPcbType *curr_pcb = get_curr_pcb();\r
StatusType rv = E_OK;\r
\r
+ OS_DEBUG(D_EVENT,"# WaitEvent %s\n",Os_TaskGetCurrent()->name);\r
+\r
if( os_sys.int_nest_cnt != 0 ) {\r
rv = E_OS_CALLEVEL;\r
goto err;\r
}\r
\r
+ if (curr_pcb->proc_type != PROC_EXTENDED) {\r
+ rv = E_OS_ACCESS;\r
+ goto err;\r
+ }\r
+\r
+ if ( Os_TaskOccupiesResources(curr_pcb) ) {\r
+ rv = E_OS_RESOURCE;\r
+ goto err;\r
+ }\r
+\r
/* Remove from ready queue */\r
Irq_Disable();\r
\r
if( !(curr_pcb->ev_set & Mask) ) {\r
\r
curr_pcb->ev_wait = Mask;\r
- Os_TaskMakeWaiting(curr_pcb);\r
- Os_Dispatch(0);\r
+\r
+ if ( Os_SchedulerResourceIsFree() ) {\r
+ // Os_TaskMakeWaiting(curr_pcb);\r
+ Os_Dispatch(OP_WAIT_EVENT);\r
+ assert( curr_pcb->state & ST_RUNNING );\r
+ } else {\r
+ Os_TaskMakeWaiting(curr_pcb);\r
+ }\r
}\r
\r
Irq_Enable();\r
OsPcbType *currPcbPtr;\r
uint32_t flags;\r
\r
- dest_pcb = os_get_pcb(TaskID);\r
-\r
+ OS_DEBUG(D_EVENT,"# SetEvent %s\n",Os_TaskGetCurrent()->name);\r
\r
- if( TaskID >= Os_CfgGetTaskCnt() ) {\r
+ if( TaskID >= OS_TASK_CNT ) {\r
rv = E_OS_ID;\r
goto err;\r
}\r
\r
- if( (dest_pcb->state & ST_SUSPENDED ) ) {\r
- rv = E_OS_STATE;\r
- goto err;\r
- }\r
+ dest_pcb = os_get_pcb(TaskID);\r
\r
+#if (OS_STATUS_EXTENDED == STD_ON )\r
if( dest_pcb->proc_type != PROC_EXTENDED ) {\r
rv = E_OS_ACCESS;\r
goto err;\r
}\r
\r
+ if( (dest_pcb->state & ST_SUSPENDED ) ) {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+#endif\r
+\r
Irq_Save(flags);\r
\r
/* Calling SetEvent causes the task <TaskID> to be transferred\r
dest_pcb->ev_set |= Mask;\r
\r
if( (Mask & dest_pcb->ev_wait) ) {\r
- /* We have a an event match */\r
+ /* We have an event match */\r
if( dest_pcb->state & ST_WAITING) {\r
Os_TaskMakeReady(dest_pcb);\r
\r
currPcbPtr = Os_TaskGetCurrent();\r
/* Checking "4.6.2 Non preemptive scheduling" it does not dispatch if NON */\r
if( (os_sys.int_nest_cnt == 0) &&\r
- (currPcbPtr->scheduling == FULL) )\r
+ (currPcbPtr->scheduling == FULL) &&\r
+ (dest_pcb->prio > currPcbPtr->prio) &&\r
+ (Os_SchedulerResourceIsFree()) )\r
{\r
- Os_Dispatch(0);\r
+ Os_Dispatch(OP_SET_EVENT);\r
}\r
\r
- } else if(dest_pcb->state & ST_READY ) {\r
+ } else if(dest_pcb->state & (ST_READY|ST_RUNNING) ) {\r
/* Hmm, we do nothing */\r
+ } else {\r
+ assert( 0 );\r
}\r
}\r
\r
OS_STD_END_2(OSServiceId_SetEvent,TaskID, Mask);\r
}\r
\r
+\r
+/**\r
+ * This service returns the current state of all event bits of the task\r
+ * <TaskID>, not the events that the task is waiting for.\r
+ * The service may be called from interrupt service routines, task\r
+ * level and some hook routines (see Figure 12-1).\r
+ * The current status of the event mask of task <TaskID> is copied\r
+ * to <Event>.\r
+ *\r
+ * @param TaskId Task whose event mask is to be returned.\r
+ * @param Mask Reference to the memory of the return data.\r
+ * @return\r
+ */\r
StatusType GetEvent( TaskType TaskId, EventMaskRefType Mask) {\r
\r
OsPcbType *dest_pcb;\r
StatusType rv = E_OK;\r
\r
+ if( TaskId >= OS_TASK_CNT ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
dest_pcb = os_get_pcb(TaskId);\r
\r
- VALIDATE_W_RV(dest_pcb->state & ST_SUSPENDED,E_OS_STATE);\r
VALIDATE_W_RV(dest_pcb->proc_type != PROC_EXTENDED,E_OS_ACCESS);\r
+ VALIDATE_W_RV(dest_pcb->state & ST_SUSPENDED,E_OS_STATE);\r
\r
*Mask = dest_pcb->ev_set;\r
\r
}\r
\r
\r
+/**\r
+ * The events of the extended task calling ClearEvent are cleared\r
+ * according to the event mask <Mask>.\r
+ *\r
+ *\r
+ * @param Mask\r
+ * @return\r
+ */\r
StatusType ClearEvent( EventMaskType Mask) {\r
StatusType rv = E_OK;\r
OsPcbType *pcb;\r
}\r
\r
pcb = get_curr_pcb();\r
+\r
+ if (pcb->proc_type != PROC_EXTENDED) {\r
+ rv = E_OS_ACCESS;\r
+ goto err;\r
+ }\r
+\r
pcb->ev_set &= ~Mask;\r
\r
if (0) goto err;\r
ALARM_ACTION_ACTIVATETASK=0,\r
ALARM_ACTION_SETEVENT,\r
ALARM_ACTION_ALARMCALLBACK, /* Only class 1 */\r
- ALARM_ACTION_INCREMENTCOUNTER, /* SWS OS302 */\r
+ ALARM_ACTION_INCREMENTCOUNTER/* SWS OS302 */\r
} alarm_action_type_t;\r
\r
\r
// Start with SetAbsAlarm()\r
ALARM_AUTOSTART_ABSOLUTE,\r
// Start with SetRelAlarm()\r
- ALARM_AUTOSTART_RELATIVE,\r
+ ALARM_AUTOSTART_RELATIVE\r
};\r
\r
\r
\r
\r
void Os_AlarmCheck(OsCounterType *c_p);\r
+void Os_AlarmAutostart(void);\r
\r
#endif /*ALARM_I_H_*/\r
* - Jump to main?!\r
* - De-init for some devices?\r
*\r
- * @param type OS_REBOOT_COLD - Reboot cold. It quite close to reset.\r
+ * @param type OS_REBOOT_COLD - Reboot cold. Soft reset.\r
* OS_REBOOT_WARM - Reboot warm. Does not run init on sections (crt0)\r
*/\r
void Os_ArchReboot( int type );\r
+++ /dev/null
-\r
-#ifndef COM_INTERNAL_H_\r
-#define COM_INTERNAL_H_\r
-\r
-\r
-/*-----------------------------------------------------------------*/\r
-\r
-/*\r
- * The only information about the COM that is valid is\r
- * in the COM specification ..SWS_COM.pdf.\r
- *\r
- * The most important requirements are COM010 and COM013\r
- *\r
- * Com_Init()\r
- * Com_DeInit()\r
- *\r
- * No error hooks..\r
- * No. GetMessageStatus()\r
- * No. SendZeroMessage()\r
- * No. SendDynamicMessage(), RecieveDynamicMessage()\r
- * Yes. SendMessage()\r
- *\r
- * */\r
-\r
-typedef enum OsMessageProperty {\r
- // ???\r
- SEND_STATIC_INTERNAL,\r
- // messages are not consumed during read\r
- RECEIVE_UNQUEUED_INTERNAL,\r
- // We have an internal queue\r
- RECEIVE_QUEUE_INTERNAL,\r
-} OsMessagePropertyType;\r
-\r
-\r
-\r
-typedef enum OsMessageNotificationAction {\r
- MESSAGE_NOTIFICATION_ACTION_NONE=0,\r
- MESSAGE_NOTIFICATION_ACTION_ACTIVATETASK,\r
- MESSAGE_NOTIFICATION_ACTION_SETEVENT,\r
-} OsMessageNotificationActionType;\r
-\r
-typedef struct OsMessageNotification {\r
- OsMessageNotificationActionType type;\r
- TaskType task_id;\r
- EventMaskType event_id;\r
-} OsMessageNotificationType;\r
-\r
-\r
-typedef struct OsMessage {\r
- OsMessagePropertyType property; // send/recieve...\r
- OsMessageNotificationType notification;\r
- int q_size; // 0-Not queued\r
-\r
- // TODO: This is not a good solution but it will have to do for now\r
- void *data;\r
- int data_size;\r
-} OsMessageType;\r
-\r
-\r
-#endif /* COM_INTERNAL_H_ */\r
\r
\r
#define PRETASKHOOK() \\r
+ assert( os_sys.curr_pcb->state & ST_RUNNING ); \\r
+ assert( os_sys.curr_pcb->flags == SYS_FLAG_HOOK_STATE_EXPECTING_PRE ); \\r
+ os_sys.curr_pcb->flags = SYS_FLAG_HOOK_STATE_EXPECTING_POST; \\r
if( os_sys.hooks->PreTaskHook != NULL ) { \\r
os_sys.hooks->PreTaskHook(); \\r
}\r
\r
#define POSTTASKHOOK() \\r
+ assert( os_sys.curr_pcb->state & ST_RUNNING ); \\r
+ assert( os_sys.curr_pcb->flags == SYS_FLAG_HOOK_STATE_EXPECTING_POST ); \\r
+ os_sys.curr_pcb->flags = SYS_FLAG_HOOK_STATE_EXPECTING_PRE; \\r
if( os_sys.hooks->PostTaskHook != NULL ) { \\r
os_sys.hooks->PostTaskHook(); \\r
}\r
*/\r
\r
static inline uint32_t os_task_nr_to_mask( uint32_t nr ) {\r
- return (1<<nr);\r
+ return ((uint32_t) 1 << nr); // 701 PC-lint [10.5]: OK om skriver 1u... får då istället: 960 PC-lint [10.5]: Båda ok om skriver 1ul eller castar till uint32_t\r
}\r
\r
// task_i.c\r
// resource.c\r
void Os_ResourceGetInternal(void );\r
void Os_ResourceReleaseInternal( void );\r
+void Os_ResourceAlloc( OsResourceType *rPtr, OsPcbType *pcbPtr);\r
+void Os_ResourceFree( OsResourceType *rPtr , OsPcbType *pcbPtr);\r
\r
void Os_ResourceInit( void );\r
\r
+\r
+static inline void Os_ResourceFreeAll( OsPcbType *pcbPtr ) {\r
+ OsResourceType *rPtr;\r
+\r
+ /* Pop the queue */\r
+ TAILQ_FOREACH(rPtr, &pcbPtr->resource_head, listEntry ) {\r
+ Os_ResourceFree(rPtr,pcbPtr);\r
+ }\r
+}\r
+\r
+#if 0\r
/**\r
*\r
* @return 1 - if any resources were found.\r
}\r
return rv;\r
}\r
+#endif\r
+\r
+static inline _Bool Os_TaskOccupiesResources( OsPcbType *pcb ) {\r
+ return !(TAILQ_EMPTY(&pcb->resource_head));\r
+}\r
+\r
+/*\r
+static inline void Os_GetSchedulerResource() {\r
+ os_sys.scheduler_lock = 1;\r
+}\r
\r
+static inline void Os_ReleaseSchedulerResource() {\r
+ os_sys.scheduler_lock = 0;\r
+}\r
+*/\r
+/*\r
+static inline _Bool Os_SchedulerResourceIsOccupied() {\r
+#if 0\r
+ return (os_sys.resScheduler.owner != NO_TASK_OWNER );\r
+#else\r
+ return (os_sys.scheduler_lock == 1);\r
+#endif\r
+}\r
+*/\r
+#define NO_TASK_OWNER (TaskType)(~0)\r
+\r
+static inline _Bool Os_SchedulerResourceIsFree() {\r
+#if 1\r
+ return (os_sys.resScheduler.owner == NO_TASK_OWNER );\r
+#else\r
+ return (os_sys.scheduler_lock == 0);\r
+#endif\r
+}\r
\r
// Create.c\r
OsPcbType * os_alloc_new_pcb( void );\r
\r
void OsTick( void );\r
\r
+#if defined(CFG_ARM_CM3)\r
+void Os_Isr_cm3( void *isr_p );\r
+void TailChaining(void *stack);\r
+#endif\r
+\r
void *Os_Isr( void *stack, void *pcb_p );\r
-void Os_Dispatch( _Bool force );\r
+void Os_Dispatch( uint32_t op );\r
\r
#define STACK_PATTERN 0x42\r
\r
uint8_t *end = pcbPtr->stack.top;\r
rv = ( *end == STACK_PATTERN);\r
if( !rv ) {\r
- OS_DEBUG(D_TASK,"Stack End Mark is bad for %s curr: %08x curr: %08x\n",\r
+ OS_DEBUG(D_TASK,"Stack End Mark is bad for %s curr: %p curr: %p\n",\r
pcbPtr->name,\r
pcbPtr->stack.curr,\r
pcbPtr->stack.top );\r
return rv;\r
}\r
\r
+static inline void Os_StackPerformCheck( OsPcbType *pcbPtr ) {\r
+#if (OS_STACK_MONITORING == 1)\r
+ if( !Os_StackIsEndmarkOk(pcbPtr) ) {\r
+#if ( OS_SC1 == 1) || ( OS_SC2 == 1)\r
+ /** @req OS068 */\r
+ ShutdownOS(E_OS_STACKFAULT);\r
+#else\r
+#error SC3 or SC4 not supported. Protection hook should be called here\r
+#endif\r
+ }\r
+#endif\r
+}\r
+\r
\r
int Os_CfgGetTaskCnt(void);\r
void Os_ContextReInit( OsPcbType *pcbPtr );\r
*\r
* Use cases:\r
* 1. We don't have a RAMLOG (low on RAM) so we want to print to serial console:\r
- * #define CFG_OS_DEBUG\r
+ * #define CFG_OS_DEBUG = STD_ON\r
* #define USE_SERIAL_PORT\r
* #define SELECT_OS_CONSOLE=TTY_SERIAL0\r
* 2. We have a RAMLOG but we have a debugger connected and want the OS debug\r
* to go there instead:\r
- * #define CFG_OS_DEBUG\r
+ * #define CFG_OS_DEBUG = STD_ON\r
* #define USE_RAMLOG\r
* #define USE_TTY_T32\r
* #define SELECT_OS_CONSOLE=TTY_T32\r
* 3. We have only the ramlog:\r
- * #define CFG_OS_DEBUG\r
+ * #define CFG_OS_DEBUG = STD_ON\r
* #define USE_RAMLOG\r
* #define SELECT_OS_CONSOLE=TTY_RAMLOG\r
* 4. We use no debug.\r
*\r
*/\r
\r
-#if defined(CFG_OS_DEBUG)\r
+#if (CFG_OS_DEBUG == STD_ON)\r
# if (SELECT_OS_CONSOLE==RAMLOG)\r
# ifndef USE_RAMLOG\r
# error USE_RAMLOG must be defined.\r
# define OS_DEBUG(_mask,...) \\r
do { \\r
if( os_dbg_mask & (_mask) ) { \\r
- printf("[%08u] : ",(unsigned)GetOsTick()); \\r
+ printf("[%08u] : %s %d ",(unsigned)GetOsTick(), __FUNCTION__, __LINE__ ); \\r
printf(__VA_ARGS__ ); \\r
}; \\r
} while(0);\r
\r
typedef enum {\r
LOCK_TYPE_RESOURCE,\r
- LOCK_TYPE_INTERRUPT,\r
+ LOCK_TYPE_INTERRUPT\r
} OsLocktypeType;\r
\r
typedef struct OsLockingtime {\r
} OsStackType;\r
\r
\r
-\r
+#define SYS_FLAG_HOOK_STATE_EXPECTING_PRE 0\r
+#define SYS_FLAG_HOOK_STATE_EXPECTING_POST 1\r
\r
/* We do ISR and TASK the same struct for now */\r
typedef struct OsPcb {\r
#endif\r
void (*entry)();\r
proc_type_t proc_type;\r
- uint8 autostart:1; // TASK\r
+ int autostart:1; // TASK\r
OsStackType stack; // TASK\r
\r
int vector; // ISR\r
OsEventType ev_wait; // TASK\r
OsEventType ev_set; // TASK\r
\r
+ uint32_t flags;\r
+\r
enum OsTaskSchedule scheduling; // TASK\r
/* belongs to this application */\r
struct OsApplication *application;\r
\r
// What resource that are currently held by this task\r
// Typically (1<<RES_xxx) | (1<<RES_yyy)\r
-// uint32_t resourceHolds;\r
+ uint32_t resourceMaskTaken;\r
\r
- TAILQ_HEAD(,OsResource) resource_head; // TASK\r
+ TAILQ_HEAD(head,OsResource) resource_head; // TASK\r
\r
const struct OsRomPcb *pcb_rom_p;\r
\r
// Start with StartScheduleTableRel()\r
SCHTBL_AUTOSTART_RELATIVE,\r
// Start with StartScheduleTableSyncon()\r
- SCHTBL_AUTOSTART_SYNCHRONE,\r
+ SCHTBL_AUTOSTART_SYNCHRONE\r
};\r
\r
\r
SA_LIST_GET(&sPtr->expirePointList, SA_LIST_CNT(&sPtr->expirePointList)-1)->offset);\r
}\r
\r
+void Os_SchTblCheck(OsCounterType *c_p);\r
\r
\r
#endif /*SCHED_TABLE_I_H_*/\r
\r
struct os_conf_global_hook_s;\r
\r
+typedef enum {\r
+ OP_SET_EVENT = 1,\r
+ OP_WAIT_EVENT = 2,\r
+ OP_ACTIVATE_TASK = 4,\r
+ OP_TERMINATE_TASK = 8,\r
+ OP_SCHEDULE = 16,\r
+ OP_CHAIN_TASK = 32,\r
+ OP_RELEASE_RESOURCE = 64\r
+} OpType ;\r
+\r
typedef struct sys_s {\r
// OsApplicationType *curr_application;\r
/* Current running task*/\r
OsPcbType *curr_pcb;\r
/* List of all tasks */\r
OsPcbType *pcb_list;\r
+\r
+ OsPcbType *chainedPcbPtr;\r
/* Interrupt nested count */\r
uint32 int_nest_cnt;\r
+ /* The current operation */\r
+ uint8_t op;\r
/* Ptr to the interrupt stack */\r
void *int_stack;\r
// The os tick\r
TickType tick;\r
// 1-The scheduler is locked (by GetResource() or something else)\r
- int scheduler_lock;\r
+// int scheduler_lock;\r
/* Hooks */\r
struct OsHooks *hooks;\r
\r
/* Current Application mode */\r
AppModeType appMode;\r
\r
+// uint32_t flags;\r
+\r
uint32_t task_cnt;\r
/* List of all pcb's,\r
* Only needed for non-static configuration of the kernel\r
TAILQ_HEAD(,OsPcb) pcb_head;\r
/* Ready queue */\r
TAILQ_HEAD(,OsPcb) ready_head;\r
+\r
+ /* Occording to OSEK 8.3 RES_SCHEDULER is accessible to all tasks */\r
+ OsResourceType resScheduler;\r
} sys_t;\r
\r
extern sys_t os_sys;\r
// ActivateTask(pid)\r
// SetEvent(pid)\r
static inline void Os_TaskMakeReady( OsPcbType *pcb ) {\r
- if( pcb->state != ST_READY ) {\r
+ if( !( pcb->state & ( ST_READY | ST_RUNNING )) ) {\r
pcb->state = ST_READY;\r
TAILQ_INSERT_TAIL(& os_sys.ready_head,pcb,ready_list);\r
OS_DEBUG(D_TASK,"Added %s to ready list\n",pcb->name);\r
\r
#define os_pcb_get_state(pcb) ((pcb)->state)\r
\r
-void os_swap_context(OsPcbType *old_pcb, OsPcbType *new_pcb );\r
+void Os_TaskSwapContext(OsPcbType *old_pcb, OsPcbType *new_pcb );\r
void Os_TaskSwapContextTo(OsPcbType *old_pcb, OsPcbType *new_pcb );\r
\r
\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-#include "Os.h"\r
-#include "internal.h"\r
-#include "arc.h"\r
-#include "debug.h"\r
-#include "arch.h"\r
-\r
-extern void Os_CfgGetInterruptStackInfo( OsStackType *stack );\r
-extern uint32_t McuE_GetSystemClock( void );\r
-extern OsTickType OsTickFreq;\r
-\r
-sys_t os_sys;\r
-\r
-Os_IntCounterType Os_IntDisableAllCnt;\r
-Os_IntCounterType Os_IntSuspendAllCnt;\r
-Os_IntCounterType Os_IntSuspendOsCnt;\r
-\r
-\r
-/**\r
- * Copy rom pcb data(r_pcb) to ram data\r
- *\r
- * @param pcb ram data\r
- * @param r_pcb rom data\r
- */\r
-\r
-static void os_pcb_rom_copy( OsPcbType *pcb, const OsRomPcbType *r_pcb ) {\r
-\r
-#if 0 //?????\r
- // Check to that the memory is ok\r
- {\r
- int cnt = sizeof(OsPcbType);\r
- for(int i=0;i<cnt;i++) {\r
- if( *((unsigned char *)pcb) != 0 ) {\r
- while(1);\r
- }\r
- }\r
- }\r
-#endif\r
-\r
-// memset(pcb,sizeof(OsPcbType),0);\r
- pcb->pid = r_pcb->pid;\r
- pcb->prio = r_pcb->prio;\r
-#if ( OS_SC3 == STD_ON ) || ( OS_SC4 == STD_ON )\r
- pcb->application = Os_CfgGetApplObj(r_pcb->application_id);\r
-#endif\r
- pcb->entry = r_pcb->entry;\r
- pcb->proc_type = r_pcb->proc_type;\r
- pcb->autostart = r_pcb->autostart;\r
- pcb->stack= r_pcb->stack;\r
- pcb->pcb_rom_p = r_pcb;\r
- pcb->resource_int_p = r_pcb->resource_int_p;\r
- pcb->scheduling = r_pcb->scheduling;\r
- pcb->resourceAccess = r_pcb->resourceAccess;\r
- pcb->activationLimit = r_pcb->activationLimit;\r
-// pcb->app = &app_list[r_pcb->app];\r
-// pcb->app_mask = app_mask[r_pcb->app];\r
- strncpy(pcb->name,r_pcb->name,16);\r
-}\r
-\r
-static _Bool init_os_called = 0;\r
-\r
-/**\r
- * Initialization of kernel structures and start of the first\r
- * task.\r
- */\r
-\r
-void InitOS( void ) {\r
- int i;\r
- OsPcbType *tmp_pcb;\r
- OsStackType int_stack;\r
-\r
- init_os_called = 1;\r
-\r
- DEBUG(DEBUG_LOW,"os_init");\r
-\r
- /* Clear sys */\r
- memset(&os_sys,0,sizeof(sys_t));\r
-\r
- Os_ArchInit();\r
-\r
- // Assign pcb list and init ready queue\r
- os_sys.pcb_list = pcb_list;\r
- TAILQ_INIT(& os_sys.ready_head);\r
- TAILQ_INIT(& os_sys.pcb_head);\r
-\r
- // Calc interrupt stack\r
- Os_CfgGetInterruptStackInfo(&int_stack);\r
- // TODO: 16 is arch dependent\r
- os_sys.int_stack = int_stack.top + int_stack.size - 16;\r
-\r
- // Init counter.. with alarms and schedule tables\r
- Os_CounterInit();\r
- Os_SchTblInit();\r
-\r
- // Put all tasks in the pcb list\r
- // Put the one that belong in the ready queue there\r
- // TODO: we should really hash on priority here to get speed, but I don't care for the moment\r
- // TODO: Isn't this just EXTENED tasks ???\r
- for( i=0; i < Os_CfgGetTaskCnt(); i++) {\r
- tmp_pcb = os_get_pcb(i);\r
-\r
- assert(tmp_pcb->prio<=OS_TASK_PRIORITY_MAX);\r
-\r
- os_pcb_rom_copy(tmp_pcb,os_get_rom_pcb(i));\r
- if( !(tmp_pcb->proc_type & PROC_ISR) ) {\r
- Os_ContextInit(tmp_pcb);\r
- }\r
-\r
- TAILQ_INIT(&tmp_pcb->resource_head);\r
-\r
- Os_AddTask(tmp_pcb);\r
-\r
- DEBUG(DEBUG_LOW,"pid:%d name:%s prio:%d\n",tmp_pcb->pid,tmp_pcb->name,tmp_pcb->prio);\r
- }\r
-\r
- Os_ResourceInit();\r
-\r
- // Now all tasks should be created.\r
-}\r
-\r
-static void os_start( void ) {\r
- OsPcbType *tmp_pcb;\r
-\r
- // We will be setting up interrupts,\r
- // but we don't want them to fire just yet\r
- Irq_Disable();\r
-\r
- assert(init_os_called);\r
-\r
- /* TODO: fix ugly */\r
- /* Call the startup hook */\r
- extern struct OsHooks os_conf_global_hooks;\r
- os_sys.hooks = &os_conf_global_hooks;\r
- if( os_sys.hooks->StartupHook!=NULL ) {\r
- os_sys.hooks->StartupHook();\r
- }\r
-\r
- /* Alarm autostart */\r
- for(int j=0; j < Os_CfgGetAlarmCnt(); j++ ) {\r
- OsAlarmType *alarmPtr;\r
- alarmPtr = Os_CfgGetAlarmObj(j);\r
- if(alarmPtr->autostartPtr != NULL ) {\r
- const OsAlarmAutostartType *autoPtr = alarmPtr->autostartPtr;\r
-\r
- if( os_sys.appMode & autoPtr->appModeRef) {\r
- if( autoPtr->autostartType == ALARM_AUTOSTART_ABSOLUTE ) {\r
- SetAbsAlarm(j,autoPtr->alarmTime, autoPtr->cycleTime);\r
- } else {\r
- SetRelAlarm(j,autoPtr->alarmTime, autoPtr->cycleTime);\r
- }\r
- }\r
- }\r
- }\r
-\r
- Os_SchTblAutostart();\r
-\r
- // Set up the systick interrupt\r
- {\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
- Os_SysTickInit();\r
- Os_SysTickStart(sys_freq/OsTickFreq);\r
- }\r
-\r
- /* Find highest Autostart task */\r
- {\r
- OsPcbType *iterPcbPtr;\r
- OsPriorityType topPrio = -1;\r
-\r
- TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {\r
- if( iterPcbPtr->autostart ) {\r
- if( iterPcbPtr->prio > topPrio ) {\r
- tmp_pcb = iterPcbPtr;\r
- topPrio = iterPcbPtr->prio;\r
- }\r
- }\r
- }\r
- }\r
-\r
- // Swap in prio proc.\r
- {\r
- // FIXME: Do this in a more structured way.. setting os_sys.curr_pcb manually is not the way to go..\r
- os_sys.curr_pcb = tmp_pcb;\r
- // NOTE! We don't go for os_swap_context() here..\r
- // first arg(NULL) is dummy only\r
- Os_TaskSwapContextTo(NULL,tmp_pcb);\r
- // We should not return here\r
- assert(0);\r
- }\r
-}\r
-#if 0\r
-static void os_start( void ) {\r
-\r
-}\r
-#endif\r
-\r
-#define TEST_DATA 12345\r
-int test_data = TEST_DATA;\r
-int test_bss = 0;\r
-\r
-\r
-void noooo( void ) {\r
- while(1);\r
-}\r
-\r
-extern void EcuM_Init();\r
-int main( void )\r
-{\r
- EcuM_Init();\r
-\r
-}\r
-\r
-/**\r
- * Starts the OS\r
- *\r
- * @param Mode - Application mode to start in\r
- *\r
- */\r
-void StartOS(AppModeType Mode) {\r
-\r
- /* Check link file */\r
- if (TEST_DATA != test_data) {\r
- noooo();\r
- }\r
-\r
- if (test_bss != 0) {\r
- noooo();\r
- }\r
-\r
- os_sys.appMode = Mode;\r
-\r
- Os_CfgValidate();\r
-\r
- os_start();\r
-\r
- /** @req OS424 */\r
- assert(0);\r
-}\r
-\r
-/**\r
- * OS shutdown\r
- *\r
- * @param Error - Reason for shutdown\r
- */\r
-\r
-/** @req OS071 */\r
-void ShutdownOS( StatusType Error ) {\r
-\r
- if( os_sys.hooks->ShutdownHook != NULL ) {\r
- os_sys.hooks->ShutdownHook(Error);\r
- }\r
-\r
- Irq_Disable();\r
- /** @req OS425 */\r
- while(1) { }\r
-\r
-}\r
-\r
-\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include <stdlib.h>
+#include <string.h>
+#include "Os.h"
+#include "internal.h"
+#include "arc.h"
+#include "debug.h"
+#include "arch.h"
+
+extern void Os_CfgGetInterruptStackInfo( OsStackType *stack );
+extern uint32_t McuE_GetSystemClock( void );
+extern OsTickType OsTickFreq;
+
+sys_t os_sys;
+
+Os_IntCounterType Os_IntDisableAllCnt;
+Os_IntCounterType Os_IntSuspendAllCnt;
+Os_IntCounterType Os_IntSuspendOsCnt;
+
+
+/**
+ * Copy rom pcb data(r_pcb) to ram data
+ *
+ * @param pcb ram data
+ * @param r_pcb rom data
+ */
+
+static void os_pcb_rom_copy( OsPcbType *pcb, const OsRomPcbType *r_pcb ) {
+
+#if 0 //?????
+ // Check to that the memory is ok
+ {
+ int cnt = sizeof(OsPcbType);
+ for(int i=0;i<cnt;i++) {
+ if( *((unsigned char *)pcb) != 0 ) {
+ while(1);
+ }
+ }
+ }
+#endif
+
+// memset(pcb,sizeof(OsPcbType),0);
+ pcb->pid = r_pcb->pid;
+ pcb->prio = r_pcb->prio;
+#if ( OS_SC3 == STD_ON ) || ( OS_SC4 == STD_ON )
+ pcb->application = Os_CfgGetApplObj(r_pcb->application_id);
+#endif
+ pcb->entry = r_pcb->entry;
+ pcb->proc_type = r_pcb->proc_type;
+ pcb->autostart = r_pcb->autostart;
+ pcb->stack= r_pcb->stack;
+ pcb->pcb_rom_p = r_pcb;
+ pcb->resource_int_p = r_pcb->resource_int_p;
+ pcb->scheduling = r_pcb->scheduling;
+ pcb->resourceAccess = r_pcb->resourceAccess;
+ pcb->activationLimit = r_pcb->activationLimit;
+// pcb->app = &app_list[r_pcb->app];
+// pcb->app_mask = app_mask[r_pcb->app];
+ strncpy(pcb->name,r_pcb->name,16);
+ pcb->name[15] = '\0';
+}
+
+static _Bool init_os_called = 0;
+
+/**
+ * Initialization of kernel structures and start of the first
+ * task.
+ */
+
+void InitOS( void ) {
+ int i;
+ OsPcbType *tmp_pcb;
+ OsStackType int_stack;
+
+ init_os_called = 1;
+
+ DEBUG(DEBUG_LOW,"os_init");
+
+ /* Clear sys */
+ memset(&os_sys,0,sizeof(sys_t));
+
+ Os_ArchInit();
+
+ // Assign pcb list and init ready queue
+ os_sys.pcb_list = pcb_list;
+ TAILQ_INIT(& os_sys.ready_head);
+ TAILQ_INIT(& os_sys.pcb_head);
+
+ // Calc interrupt stack
+ Os_CfgGetInterruptStackInfo(&int_stack);
+ // TODO: 16 is arch dependent
+ os_sys.int_stack = (void *)((size_t)int_stack.top + (size_t)int_stack.size - 16);
+
+ // Init counter.. with alarms and schedule tables
+#if OS_COUNTER_CNT!=0
+ Os_CounterInit();
+#endif
+#if OS_SCHTBL_CNT!=0
+ Os_SchTblInit();
+#endif
+
+ // Put all tasks in the pcb list
+ // Put the one that belong in the ready queue there
+ // TODO: we should really hash on priority here to get speed, but I don't care for the moment
+ // TODO: Isn't this just EXTENED tasks ???
+ for( i=0; i < OS_TASK_CNT; i++) {
+ tmp_pcb = os_get_pcb(i);
+
+ assert(tmp_pcb->prio<=OS_TASK_PRIORITY_MAX);
+
+ os_pcb_rom_copy(tmp_pcb,os_get_rom_pcb(i));
+ if( !(tmp_pcb->proc_type & PROC_ISR) ) {
+ Os_ContextInit(tmp_pcb);
+ }
+
+ TAILQ_INIT(&tmp_pcb->resource_head);
+
+ Os_AddTask(tmp_pcb);
+
+ DEBUG(DEBUG_LOW,"pid:%d name:%s prio:%d\n",tmp_pcb->pid,tmp_pcb->name,tmp_pcb->prio);
+ }
+
+ Os_ResourceInit();
+
+ // Now all tasks should be created.
+}
+
+static void os_start( void ) {
+ OsPcbType *tmp_pcb;
+
+ // We will be setting up interrupts,
+ // but we don't want them to fire just yet
+ Irq_Disable();
+
+ assert(init_os_called);
+
+ /* TODO: fix ugly */
+ /* Call the startup hook */
+ extern struct OsHooks os_conf_global_hooks;
+ os_sys.hooks = &os_conf_global_hooks;
+ if( os_sys.hooks->StartupHook!=NULL ) {
+ os_sys.hooks->StartupHook();
+ }
+
+ /* Alarm autostart */
+#if OS_ALARM_CNT!=0
+ Os_AlarmAutostart();
+#endif
+
+#if OS_SCHTBL_CNT!=0
+ Os_SchTblAutostart();
+#endif
+
+ // Set up the systick interrupt
+ {
+ uint32_t sys_freq = McuE_GetSystemClock();
+ Os_SysTickInit();
+ Os_SysTickStart(sys_freq/OsTickFreq);
+ }
+
+ /* Find highest Autostart task */
+ {
+ OsPcbType *iterPcbPtr;
+ OsPriorityType topPrio = -1;
+
+ TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {
+ if( iterPcbPtr->autostart ) {
+ if( iterPcbPtr->prio > topPrio ) {
+ tmp_pcb = iterPcbPtr;
+ topPrio = iterPcbPtr->prio;
+ }
+ }
+ }
+ }
+
+ // Swap in prio proc.
+ {
+ // FIXME: Do this in a more structured way.. setting os_sys.curr_pcb manually is not the way to go..
+ os_sys.curr_pcb = tmp_pcb;
+
+ // register this auto-start activation
+ assert(tmp_pcb->activations < tmp_pcb->activationLimit);
+ tmp_pcb->activations++;
+
+ // NOTE! We don't go for os_swap_context() here..
+ // first arg(NULL) is dummy only
+ Os_TaskSwapContextTo(NULL,tmp_pcb);
+ // We should not return here
+ assert(0);
+ }
+}
+#if 0
+static void os_start( void ) {
+
+}
+#endif
+
+#define TEST_DATA 12345
+int test_data = TEST_DATA;
+int test_bss = 0;
+
+
+void noooo( void ) {
+ while(1);
+}
+
+extern void EcuM_Init();
+int main( void )
+{
+ EcuM_Init();
+
+}
+
+/**
+ * Starts the OS
+ *
+ * @param Mode - Application mode to start in
+ *
+ */
+void StartOS(AppModeType Mode) {
+
+ /* Check link file */
+ if (TEST_DATA != test_data) {
+ noooo();
+ }
+
+ if (test_bss != 0) {
+ noooo();
+ }
+
+ os_sys.appMode = Mode;
+
+ Os_CfgValidate();
+
+ os_start();
+
+ /** @req OS424 */
+ assert(0);
+}
+
+/**
+ * OS shutdown
+ *
+ * @param Error - Reason for shutdown
+ */
+
+/** @req OS071 */
+void ShutdownOS( StatusType Error ) {
+
+ if( os_sys.hooks->ShutdownHook != NULL ) {
+ os_sys.hooks->ShutdownHook(Error);
+ }
+
+ Irq_Disable();
+ /** @req OS425 */
+ while(1) { }
+
+}
+
+
+
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#include <sys/types.h>\r
-#include <stdint.h>\r
-#include <string.h>\r
-#include "internal.h"\r
-#include "irq.h"\r
-#if 0\r
-\r
-\r
-#include <stdint.h>\r
-#include <stdlib.h>\r
-#include <assert.h>\r
-#include <sys/queue.h>\r
-#include <string.h>\r
-#include "internal.h"\r
-\r
-#endif\r
-\r
-\r
-// TODO: remove. Make soft links or whatever\r
-#if defined(CFG_ARM_CM3)\r
-#include "irq_types.h"\r
-//#include "stm32f10x.h"\r
-//#include "stm32f10x_arc.h"\r
-#endif\r
-\r
-extern caddr_t *sbrk(int);\r
-\r
-#define os_alloc(_x) sbrk(_x)\r
-\r
-OsPcbType * os_alloc_new_pcb( void ) {\r
- void *h = os_alloc(sizeof(OsPcbType));\r
- memset(h,0,sizeof(OsPcbType));\r
- assert(h!=NULL);\r
- return h;\r
-}\r
-\r
-#if 0\r
-typedef void (*Os_IsrEntryType)(void);\r
-\r
-\r
-typedef Os_IsrInfo_s {\r
- Os_IsrEntryType entry;\r
- uint32_t vector;\r
- uint8_t priority;\r
-} Os_IsrInfoType;\r
-#endif\r
-\r
-\r
-extern TaskType Os_AddTask( OsPcbType *pcb );\r
-\r
-static uint8 stackTop = 0x42;\r
-\r
-TaskType Os_Arc_CreateIsr( void (*entry)(void ), uint8_t prio, const char *name )\r
-{\r
- OsPcbType *pcb = os_alloc_new_pcb();\r
- strncpy(pcb->name,name,TASK_NAME_SIZE);\r
- pcb->vector = -1;\r
- pcb->prio = prio;\r
- /* TODO: map to interrupt controller priority */\r
- assert(prio<=OS_TASK_PRIORITY_MAX);\r
- pcb->proc_type = PROC_ISR2;\r
- pcb->state = ST_SUSPENDED;\r
- pcb->entry = entry;\r
- pcb->stack.top = &stackTop;\r
-\r
- return Os_AddTask(pcb);\r
-}\r
-\r
-\r
-#if defined(CFG_ARM_CM3)\r
-extern void Irq_EOI2(void *pc);\r
-#endif\r
-\r
-\r
-/**\r
- * Handle ISR type 2 interrupts from interrupt controller.\r
- *\r
- * @param stack Ptr to the current stack\r
- * @param vector The vector that took the interrupt\r
- */\r
-void *Os_Isr( void *stack, void *pcb_p ) {\r
- struct OsPcb *pcb;\r
- struct OsPcb *preempted_pcb;\r
-\r
- os_sys.int_nest_cnt++;\r
-\r
- // Save info for preempted pcb\r
- preempted_pcb = get_curr_pcb();\r
- preempted_pcb->stack.curr = stack;\r
- preempted_pcb->state = ST_READY;\r
- OS_DEBUG(D_TASK,"Preempted %s\n",preempted_pcb->name);\r
-\r
- POSTTASKHOOK();\r
-\r
- pcb = (struct OsPcb *)pcb_p;\r
- pcb->state = ST_RUNNING;\r
- set_curr_pcb(pcb);\r
-\r
- PRETASKHOOK();\r
-\r
- // We should not get here if we're NON\r
- if( pcb->scheduling == NON) {\r
- // TODO:\r
- // assert(0);\r
- while(1);\r
- }\r
-\r
- Irq_Enable();\r
- pcb->entry();\r
- Irq_Disable();\r
-\r
- /** @req OS368 */\r
- if( Os_IrqAnyDisabled() ) {\r
- Os_IrqClearAll();\r
- ERRORHOOK(E_OS_DISABLEDINT);\r
- }\r
-\r
- /** @req OS369 */\r
- Os_ResourceCheckAndRelease(pcb);\r
-\r
- pcb->state = ST_SUSPENDED;\r
- POSTTASKHOOK();\r
-\r
- Irq_EOI();\r
-\r
- --os_sys.int_nest_cnt;\r
-\r
- // TODO: Check stack check marker....\r
- // We have preempted a task\r
- if( (os_sys.int_nest_cnt == 0) && (os_sys.scheduler_lock==0) ) { //&& is_idle_task() ) {\r
- /* If we get here:\r
- * - the preempted task is saved with large context.\r
- * - We are on interrupt stack..( this function )\r
- *\r
- * if we find a new task:\r
- * - just switch in the new context( don't save the old because\r
- * its already saved )\r
- */\r
- OsPcbType *new_pcb;\r
- new_pcb = Os_TaskGetTop();\r
- if( new_pcb != preempted_pcb ) {\r
- OS_DEBUG(D_TASK,"Found candidate %s\n",new_pcb->name);\r
-//#warning Os_TaskSwapContextTo should call the pretaskswaphook\r
-// TODO: This shuould go away!!!!\r
-#if defined(CFG_ARM_CM3)\r
- void *p;\r
- p = &&really_ugly;\r
- Irq_EOI2(p);\r
-really_ugly:\r
-#endif\r
- Os_TaskSwapContextTo(NULL,new_pcb);\r
- } else {\r
- if( new_pcb == NULL ) {\r
- assert(0);\r
- }\r
- preempted_pcb->state = ST_RUNNING;\r
- set_curr_pcb(preempted_pcb);\r
- }\r
- } else {\r
- set_curr_pcb(preempted_pcb);\r
- PRETASKHOOK();\r
- }\r
-\r
- return stack;\r
-}\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include "internal.h"
+#include "irq.h"
+#if 0
+
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <sys/queue.h>
+#include <string.h>
+#include "internal.h"
+
+#endif
+
+
+// TODO: remove. Make soft links or whatever
+#if defined(CFG_ARM_CM3)
+#include "irq_types.h"
+//#include "stm32f10x.h"
+//#include "stm32f10x_arc.h"
+#endif
+
+extern caddr_t *sbrk(int);
+
+#define os_alloc(_x) sbrk(_x)
+
+OsPcbType * os_alloc_new_pcb( void ) {
+ void *h = os_alloc(sizeof(OsPcbType));
+ memset(h,0,sizeof(OsPcbType));
+ assert(h!=NULL);
+ return h;
+}
+
+#if 0
+typedef void (*Os_IsrEntryType)(void);
+
+
+typedef Os_IsrInfo_s {
+ Os_IsrEntryType entry;
+ uint32_t vector;
+ uint8_t priority;
+} Os_IsrInfoType;
+#endif
+
+
+extern TaskType Os_AddTask( OsPcbType *pcb );
+
+static uint8 stackTop = 0x42;
+
+/**
+ * Creates an ISR dynamically
+ * @param entry
+ * @param prio
+ * @param name
+ *
+ * @return The PID of the ISR created
+ */
+TaskType Os_Arc_CreateIsr( void (*entry)(void ), uint8_t prio, const char *name )
+{
+ OsPcbType *pcb = os_alloc_new_pcb();
+ strncpy(pcb->name,name,TASK_NAME_SIZE);
+ pcb->vector = -1;
+ pcb->prio = prio;
+ /* TODO: map to interrupt controller priority */
+ assert(prio<=OS_TASK_PRIORITY_MAX);
+ pcb->proc_type = PROC_ISR2;
+ pcb->state = ST_SUSPENDED;
+ pcb->entry = entry;
+ pcb->stack.top = &stackTop;
+
+ return Os_AddTask(pcb);
+}
+
+/**
+ * Before we have proper editor for ISR2 use this function to add resources
+ * to an ISR2
+ *
+ * @param isr
+ * @param resource
+ * @return
+ */
+StatusType Os_IsrAddResource( TaskType isr, ResourceType resource ) {
+ return E_OK;
+}
+
+#if defined(CFG_ARM_CM3)
+extern void Irq_EOI( void );
+
+void TailChaining(void *stack)
+{
+ struct OsPcb *pPtr = NULL;
+
+ POSTTASKHOOK();
+
+ /* Save info for preempted pcb */
+ pPtr = get_curr_pcb();
+ pPtr->stack.curr = stack;
+ pPtr->state = ST_READY;
+ OS_DEBUG(D_TASK,"Preempted %s\n",pPtr->name);
+
+ Os_StackPerformCheck(pPtr);
+
+ /* We interrupted a task */
+ OsPcbType *new_pcb = Os_TaskGetTop();
+
+ Os_StackPerformCheck(new_pcb);
+
+ if( (new_pcb == os_sys.curr_pcb) ||
+ (os_sys.curr_pcb->scheduling == NON) ||
+ !Os_SchedulerResourceIsFree() )
+ {
+ /* Just bring the preempted task back to running */
+ Os_TaskSwapContextTo(NULL,os_sys.curr_pcb);
+ } else {
+ OS_DEBUG(D_TASK,"Found candidate %s\n",new_pcb->name);
+ Os_TaskSwapContextTo(NULL,new_pcb);
+ }
+}
+
+void Os_Isr_cm3( void *isr_p ) {
+
+ struct OsPcb *isrPtr;
+
+ os_sys.int_nest_cnt++;
+
+ /* Grab the ISR "pcb" */
+ isrPtr = (struct OsPcb *)isr_p;
+ isrPtr->state = ST_RUNNING;
+
+ if( isrPtr->proc_type & ( PROC_EXTENDED | PROC_BASIC ) ) {
+ assert(0);
+ }
+
+ Irq_Enable();
+ isrPtr->entry();
+ Irq_Disable();
+
+ /* Check so that ISR2 haven't disabled the interrupts */
+ /** @req OS368 */
+ if( Os_IrqAnyDisabled() ) {
+ Os_IrqClearAll();
+ ERRORHOOK(E_OS_DISABLEDINT);
+ }
+
+ /* Check so that the ISR2 have called ReleaseResource() for each GetResource() */
+ /** @req OS369 */
+ if( Os_TaskOccupiesResources(isrPtr) ) {
+ Os_ResourceFreeAll(isrPtr);
+ ERRORHOOK(E_OS_RESOURCE);
+ }
+
+ isrPtr->state = ST_SUSPENDED;
+
+ Irq_EOI();
+
+ --os_sys.int_nest_cnt;
+
+ /* Scheduling is done in PendSV handler for ARM CM3 */
+ *((uint32_t volatile *)0xE000ED04) = 0x10000000; // PendSV
+}
+#endif
+
+/**
+ * Handle ISR type 2 interrupts from interrupt controller.
+ *
+ * @param stack Ptr to the current stack
+ * @param vector The vector that took the interrupt
+ */
+void *Os_Isr( void *stack, void *isr_p ) {
+ struct OsPcb *isrPtr;
+ struct OsPcb *pPtr = NULL;
+
+ /* Check if we interrupted a task or ISR */
+ if( os_sys.int_nest_cnt == 0 ) {
+ /* We interrupted a task */
+ POSTTASKHOOK();
+
+ /* Save info for preempted pcb */
+ pPtr = get_curr_pcb();
+ pPtr->stack.curr = stack;
+ pPtr->state = ST_READY;
+ OS_DEBUG(D_TASK,"Preempted %s\n",pPtr->name);
+
+ Os_StackPerformCheck(pPtr);
+ } else {
+ /* We interrupted an ISR */
+ }
+
+ os_sys.int_nest_cnt++;
+
+ /* Grab the ISR "pcb" */
+ isrPtr = (struct OsPcb *)isr_p;
+ isrPtr->state = ST_RUNNING;
+
+ if( isrPtr->proc_type & ( PROC_EXTENDED | PROC_BASIC ) ) {
+ assert(0);
+ }
+
+ Irq_SOI();
+
+#if !defined(CFG_HCS12D)
+ Irq_Enable();
+ isrPtr->entry();
+ Irq_Disable();
+#else
+ isrPtr->entry();
+#endif
+
+ /* Check so that ISR2 haven't disabled the interrupts */
+ /** @req OS368 */
+ if( Os_IrqAnyDisabled() ) {
+ Os_IrqClearAll();
+ ERRORHOOK(E_OS_DISABLEDINT);
+ }
+
+ /* Check so that the ISR2 have called ReleaseResource() for each GetResource() */
+ /** @req OS369 */
+ if( Os_TaskOccupiesResources(isrPtr) ) {
+ Os_ResourceFreeAll(isrPtr);
+ ERRORHOOK(E_OS_RESOURCE);
+ }
+
+ isrPtr->state = ST_SUSPENDED;
+
+ Irq_EOI();
+
+ --os_sys.int_nest_cnt;
+
+#if defined(CFG_ARM_CM3)
+ /* Scheduling is done in PendSV handler for ARM CM3 */
+ *((uint32_t volatile *)0xE000ED04) = 0x10000000; // PendSV
+#else
+ // We have preempted a task
+ if( (os_sys.int_nest_cnt == 0) ) {
+ OsPcbType *new_pcb = Os_TaskGetTop();
+
+ Os_StackPerformCheck(new_pcb);
+
+ if( (new_pcb == os_sys.curr_pcb) ||
+ (os_sys.curr_pcb->scheduling == NON) ||
+ !Os_SchedulerResourceIsFree() )
+ {
+ /* Just bring the preempted task back to running */
+ os_sys.curr_pcb->state = ST_RUNNING;
+ PRETASKHOOK();
+ } else {
+ OS_DEBUG(D_TASK,"Found candidate %s\n",new_pcb->name);
+ Os_TaskSwapContextTo(NULL,new_pcb);
+ }
+ } else {
+ /* We have a nested interrupt, do nothing */
+ }
+#endif
+
+ return stack;
+}
#obj-y += asm_sample.o\r
#CFLAGS_asm_sample.o += -O3\r
obj-y += arch_krn.o\r
-obj-$(CFG_HCS12D) += arch_irq.o\r
+obj-$(CFG_HC1X) += arch_irq.o\r
#obj-y += stm32f10x_it.o\r
\r
# object files \r
#obj-y += stack.o\r
obj-y += isr.o\r
obj-y += os_arctest.o\r
+obj-y += application.o\r
\r
\r
# These are VERY cpu dependent.. remove\r
dep-y += asm_offset.h\r
dep-y += kernel_offset.h\r
dep-$(CFG_ARM_CM3) += arch_offset.h\r
-obj-$(CFG_ARM_CM3) += misc.o\r
\r
\r
# ARM assembler generates "define STACK_APA $12". The extra '$' we want to go.\r
inc-y += $(ROOTDIR)/arch/$(ARCH_FAM)/$(ARCH)/config\r
inc-y += $(ROOTDIR)/arch/$(ARCH)\r
inc-y += $(ROOTDIR)/include/$(ARCH_FAM)\r
-\r
-\r
-build-lib-y = $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
\r
\r
\r
\r
#include "Os.h"\r
#include "internal.h"\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
\r
#if !defined(MAX)\r
#define MAX(_x,_y) (((_x) > (_y)) ? (_x) : (_y))\r
#endif\r
\r
+\r
+/*\r
+Resource management at interrupt level is NOT supported\r
+\r
+\r
+Testing\r
+RM:\r
+1. Priority ceiling: Call GetResource() from preemtive\r
+ task and activate a task with higher priority than the ceiling protocol.\r
+ The higher priority task should be swapped in.\r
+2. Verify that you cannot allocate an internal resource with\r
+ a) GetResource()\r
+ b) ReleaseResource()\r
+3. Internal resource. Allocate 1 internal resource to 3 tasks of different\r
+ priorities. Verify that\r
+ a) Higher priority tasks than the group can preement\r
+ b) For tasks which have the same or lower priority as the highest priority within a group,\r
+ the tasks within the group behave like non preemptable tasks ( OSEK 4.6.3)\r
+4. Attempt to release a resource which has a lower ceiling priority\r
+ than the statically assigned priority of the calling task or\r
+ interrupt routine, E_OS_ACCESS\r
+5. The general restriction on some system calls that they are not to be called with resources\r
+ occupied (chapter 8.2) does not apply to internal resources, as internal resources are handled\r
+ within those calls. However, all standard resources have to be released before the internal\r
+ resource can be released (see chapter 8.2, \93LIFO principle\94).\r
+6. Check LIFO order. Return E_OS_ACCESS if not in LIFO order..\r
+7. Test Os_IsrAddResource().\r
+\r
+\r
+task\r
+- GetResource(RES_SCHEDULER) will lock the scheduler even for ISR2\r
+\r
+TODO:\r
+1. task.resourceAccess is already calculated by BSW builder. This is the bitmask\r
+ of what resources is accessable by the task.\r
+2.\r
+\r
+ task.rsrcAccessMask & (1 << RES_SCHEDULER)\r
+\r
+ *
+ */\r
+\r
/* INFO\r
* - If OsTaskSchedule = NON, Task it not preemptable, no internal resource may be assigned to a task\r
* (cause it already have one of prio 32)\r
*\r
*/\r
\r
-#define valid_standard_id() (rPtr->nr < Os_CfgGetResourceCnt()) //&& !(rPtr->type == RESOURCE_TYPE_INTERNAL) )\r
-#define valid_internal_id() (rPtr->nr < Os_CfgGetResourceCnt()) //&& (rPtr->type == RESOURCE_TYPE_INTERNAL) )\r
+#define valid_standard_id() (rPtr->nr < OS_RESOURCE_CNT) //&& !(rPtr->type == RESOURCE_TYPE_INTERNAL) )\r
+#define valid_internal_id() (rPtr->nr < OS_RESOURCE_CNT) //&& (rPtr->type == RESOURCE_TYPE_INTERNAL) )\r
+\r
+\r
+void Os_ResourceAlloc( OsResourceType *rPtr, OsPcbType *pcbPtr) {\r
+ /* Save old task prio in resource and set new task prio */\r
+ rPtr->owner = pcbPtr->pid;\r
+ rPtr->old_task_prio = pcbPtr->prio;\r
+ pcbPtr->prio = rPtr->ceiling_priority;\r
+\r
+ if( rPtr->type != RESOURCE_TYPE_INTERNAL ) {\r
+ TAILQ_INSERT_TAIL(&pcbPtr->resource_head, rPtr, listEntry);\r
+ }\r
+}\r
+\r
+void Os_ResourceFree( OsResourceType *rPtr , OsPcbType *pcbPtr) {\r
+ assert( rPtr->owner == pcbPtr->pid );\r
+ rPtr->owner = NO_TASK_OWNER;\r
+ pcbPtr->prio = rPtr->old_task_prio;\r
+\r
+ if( rPtr->type != RESOURCE_TYPE_INTERNAL ) {\r
+ /* The list can't be empty here */\r
+ assert( !TAILQ_EMPTY(&pcbPtr->resource_head) );\r
\r
+ /* The list should be popped in LIFO order */\r
+ assert( TAILQ_LAST(&pcbPtr->resource_head, head) == rPtr );\r
\r
-static StatusType GetResource_( OsResourceType * );\r
-StatusType ReleaseResource_( OsResourceType * );\r
+ /* Remove the entry */\r
+ TAILQ_REMOVE(&pcbPtr->resource_head, rPtr, listEntry);\r
+ }\r
+}\r
\r
/**\r
* This call serves to enter critical sections in the code that are\r
* @param ResID\r
* @return\r
*/\r
+\r
+\r
StatusType GetResource( ResourceType ResID ) {\r
- OsResourceType *rPtr = Os_CfgGetResource(ResID);\r
- StatusType rv = GetResource_(rPtr);\r
+ StatusType rv = E_OK;\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rPtr;\r
+ uint32_t flags;\r
+\r
+ Irq_Save(flags);\r
+\r
+ if( ResID == RES_SCHEDULER ) {\r
+\r
+ rPtr = &os_sys.resScheduler;\r
+ } else {\r
+ /* Check we can access it */\r
+ if( (pcbPtr->resourceAccess & ( (uint32_t) 1 << ResID)) == 0 ) {\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+\r
+ rPtr = Os_CfgGetResource(ResID);\r
+ }\r
+\r
+ /* Check for invalid configuration */\r
+ if( (rPtr->owner != NO_TASK_OWNER) ||\r
+ (pcbPtr->prio > rPtr->ceiling_priority) )\r
+ {\r
+ rv = E_OS_ACCESS;\r
+ Irq_Restore(flags);\r
+ goto err;\r
+ }\r
+\r
+ Os_ResourceAlloc(rPtr,pcbPtr);\r
+ Irq_Restore(flags);\r
\r
if (rv != E_OK)\r
- goto err;\r
+ goto err;\r
\r
OS_STD_END_1(OSServiceId_GetResource,ResID);\r
}\r
*/\r
\r
StatusType ReleaseResource( ResourceType ResID) {\r
- StatusType rv = E_OK;\r
- if( ResID == RES_SCHEDULER ) {\r
- os_sys.scheduler_lock=0;\r
- } else {\r
- OsResourceType *rPtr = Os_CfgGetResource(ResID);\r
- rv = ReleaseResource_(rPtr);\r
- }\r
-\r
- if (rv != E_OK)\r
- goto err;\r
-\r
- OS_STD_END_1(OSServiceId_ReleaseResource,ResID);\r
-}\r
-\r
-\r
-/**\r
- * Internal GetResource function...\r
- *\r
- * @param rPtr\r
- * @return\r
- */\r
-\r
-static StatusType GetResource_( OsResourceType * rPtr ) {\r
StatusType rv = E_OK;\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rPtr;\r
+ uint32_t flags;\r
\r
- if( rPtr->nr == RES_SCHEDULER ) {\r
- // Lock the scheduler\r
- os_sys.scheduler_lock = 1;\r
+ Irq_Save(flags);\r
+ if( ResID == RES_SCHEDULER ) {\r
+ rPtr = &os_sys.resScheduler;\r
+ } else {\r
+ /* Check we can access it */\r
+ if( (pcbPtr->resourceAccess & ( (uint32_t) 1 << ResID) ) == 0 ) {// 960 PC-lint [10.5]: varför klagar? funkar inte heller om (unsigned char)1 )\r
+ rv = E_OS_ID;\r
+ goto err;\r
+ }\r
+ rPtr = Os_CfgGetResource(ResID);\r
}\r
\r
- /* Check if valid resource */\r
- if( !valid_standard_id() ) {\r
- rv = E_OS_ID;\r
+ /* Check for invalid configuration */\r
+ if( rPtr->owner == NO_TASK_OWNER)\r
+ {\r
+ rv = E_OS_NOFUNC;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
- /* @req OSEK\r
- * Attempt to get a resource which is already occupied by any task\r
- * or ISR, or the statically assigned priority of the calling task or\r
- * interrupt routine is higher than the calculated ceiling priority,\r
- * E_OS_ACCESS\r
- */\r
- if( (Os_TaskGetCurrent()->prio > rPtr->ceiling_priority )\r
-#if ( OS_SC3 == STD_ON ) || ( OS_SC4 == STD_ON )\r
- || ( get_curr_application_id() != rPtr->application_owner_id)\r
-#endif\r
- || ( rPtr->owner != (TaskType)(-1)))\r
+ if( (pcbPtr->prio < rPtr->ceiling_priority))\r
{\r
rv = E_OS_ACCESS;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
- rPtr->owner = get_curr_pid();\r
- rPtr->old_task_prio = os_pcb_set_prio(Os_TaskGetCurrent() ,rPtr->ceiling_priority);\r
-\r
- if( rPtr->type != RESOURCE_TYPE_INTERNAL ) {\r
- TAILQ_INSERT_TAIL(&Os_TaskGetCurrent()->resource_head, rPtr, listEntry);\r
- }\r
+ Os_ResourceFree(rPtr,pcbPtr);\r
\r
- goto ok;\r
-err:\r
- ERRORHOOK(rv);\r
-ok:\r
- return rv;\r
-}\r
+ /* do a rescheduling (in some cases) (see OSEK OS 4.6.1) */\r
+ if ( (pcbPtr->scheduling == FULL) &&\r
+ (os_sys.int_nest_cnt == 0) &&\r
+ (Os_SchedulerResourceIsFree()) ) {\r
\r
+ OsPcbType* top_pcb = Os_TaskGetTop();\r
\r
-/**\r
- * Internal release resource..\r
- * @param rPtr\r
- * @return\r
- */\r
-StatusType ReleaseResource_( OsResourceType * rPtr ) {\r
- if (!valid_standard_id()) {\r
- return E_OS_ID;\r
- } else {\r
- // Release it...\r
- rPtr->owner = (TaskType) (-1);\r
- TAILQ_REMOVE(&Os_TaskGetCurrent()->resource_head, rPtr, listEntry);\r
- os_pcb_set_prio(Os_TaskGetCurrent(), rPtr->old_task_prio);\r
- return E_OK;\r
+ /* only dispatch if some other ready task has higher prio */\r
+ if (top_pcb->prio > Os_TaskGetCurrent()->prio) {\r
+ Os_Dispatch(OP_RELEASE_RESOURCE);\r
+ }\r
}\r
+ Irq_Restore(flags);\r
+\r
+ OS_STD_END_1(OSServiceId_ReleaseResource,ResID);\r
}\r
\r
\r
void Os_ResourceGetInternal( void ) {\r
- OsResourceType *rt = os_get_resource_int_p();\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rt = pcbPtr->resource_int_p;\r
\r
if( rt != NULL ) {\r
OS_DEBUG(D_RESOURCE,"Get IR proc:%s prio:%u old_task_prio:%u\n",\r
get_curr_pcb()->name,\r
(unsigned)rt->ceiling_priority,\r
(unsigned)rt->old_task_prio);\r
- GetResource_(rt);\r
+ Os_ResourceAlloc(rt,pcbPtr);\r
}\r
}\r
\r
void Os_ResourceReleaseInternal( void ) {\r
- OsResourceType *rt = os_get_resource_int_p();\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rt = pcbPtr->resource_int_p;\r
\r
if( rt != NULL ) {\r
OS_DEBUG(D_RESOURCE,"Rel IR proc:%s prio:%u old_task_prio:%u\n",\r
get_curr_pcb()->name,\r
(unsigned)rt->ceiling_priority,\r
(unsigned)rt->old_task_prio);\r
- ReleaseResource_(rt);\r
+ Os_ResourceFree(rt,pcbPtr);\r
}\r
}\r
\r
OsResourceType *rsrc_p;\r
int topPrio;\r
\r
+\r
+ /* For now, assign the scheduler resource here */\r
+ os_sys.resScheduler.ceiling_priority = OS_RES_SCHEDULER_PRIO;\r
+ strcpy(os_sys.resScheduler.id,"RES_SCHEDULER");\r
+ os_sys.resScheduler.nr = RES_SCHEDULER;\r
+ os_sys.resScheduler.owner = NO_TASK_OWNER;\r
+\r
/* Calculate ceiling priority\r
* We make this as simple as possible. The ceiling priority\r
* is set to the same priority as the highest priority task that\r
* access it.\r
+ *\r
+ * Note that this applies both internal and standard resources.\r
* */\r
- for( int i=0; i < Os_CfgGetResourceCnt(); i++) {\r
+ for( int i=0; i < OS_RESOURCE_CNT; i++) {\r
rsrc_p = Os_CfgGetResource(i);\r
topPrio = 0;\r
\r
- for( int pi = 0; pi < Os_CfgGetTaskCnt(); pi++) {\r
+ for( int pi = 0; pi < OS_TASK_CNT; pi++) {\r
\r
pcb_p = os_get_pcb(pi);\r
- if(pcb_p->resourceAccess & (1<<i) ) {\r
- topPrio = MAX(topPrio,pcb_p->prio);\r
- }\r
- }\r
- rsrc_p->ceiling_priority = topPrio;\r
- }\r
\r
\r
+ if(pcb_p->resourceAccess & ( (uint32_t) 1<<i) ) {\r
+ topPrio = MAX(topPrio,pcb_p->prio);\r
+ }\r
\r
- /* From OSEK:\r
- * Non preemptable tasks are the most common usage of the concept\r
- * of internal resources; they are tasks with a special internal\r
- * resource of highest task priority assigned.\r
- * --> Interpret this as we can set the priority to 32.\r
- *\r
- * Assign an internal resource with prio 32 to the tasks\r
- * with scheduling=NON\r
- *\r
- *\r
- */\r
- for( int i=0; i < Os_CfgGetTaskCnt(); i++) {\r
- pcb_p = os_get_pcb(i);\r
- if(pcb_p->scheduling == NON ) {\r
- pcb_p->prio = OS_RES_SCHEDULER_PRIO;\r
+ /* Generator fix, add RES_SCHEDULER */\r
+ pcb_p->resourceAccess |= (1 << RES_SCHEDULER) ;\r
}\r
+ rsrc_p->ceiling_priority = topPrio;\r
}\r
}\r
\r
// Cancel\r
\r
#define SCHED_CHECK_ID(x) \\r
- if( (x) > Os_CfgGetSchedCnt()) { \\r
+ if( (x) > OS_SCHTBL_CNT) { \\r
rv = E_OS_ID; \\r
goto err; \\r
}\r
return rv;\r
\r
extern TickType GetCountValue( OsCounterType *counter );\r
-void Os_SchTblUpdateState( OsSchTblType *stbl );\r
+\r
+static void Os_SchTblUpdateState( OsSchTblType *stbl );\r
\r
#if 0\r
enum OsScheduleTableSyncStrategy getSyncStrategy( OsSchTblType *stblPtr ) {\r
/** @req OS408 */\r
for(iter=0; iter < SA_LIST_CNT(&sTblPtr->expirePointList) ; iter++) {\r
delta = SA_LIST_GET(&sTblPtr->expirePointList,iter)->offset - delta;\r
- assert( delta >= minCycle );\r
+ /* initial offset may be zero (OS443) */\r
+ if(iter!=0) {\r
+ assert( delta >= minCycle );\r
+ }\r
assert( delta <= maxValue );\r
}\r
\r
/* Check if the expire point have been hit */\r
if( (sched_obj->state == SCHEDULETABLE_RUNNING ||\r
sched_obj->state == SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS ) &&\r
- (c_p->val == sched_obj->expire_val) )\r
+ (c_p->val == sched_obj->expire_val) )\r
{\r
if ( sched_obj->expire_curr_index < SA_LIST_CNT(&sched_obj->expirePointList) ) {\r
- OsScheduleTableExpiryPointType * action;\r
- int i;\r
+ OsScheduleTableExpiryPointType * action;\r
+ int i;\r
\r
- action = SA_LIST_GET(&sched_obj->expirePointList,sched_obj->expire_curr_index);\r
+ action = SA_LIST_GET(&sched_obj->expirePointList,sched_obj->expire_curr_index);\r
\r
- /** @req OS407 */\r
- /** @req OS412 */\r
+ /** @req OS407 */\r
+ /** @req OS412 */\r
\r
- /* According to OS412 activate tasks before events */\r
- for(i=0; i< action->taskListCnt;i++ ) {\r
- ActivateTask(action->taskList[i]);\r
- }\r
+ /* According to OS412 activate tasks before events */\r
+ for(i=0; i< action->taskListCnt;i++ ) {\r
+ ActivateTask(action->taskList[i]);\r
+ }\r
\r
- for(i=0; i< action->eventListCnt;i++ ) {\r
- SetEvent( action->eventList[i].task, action->eventList[i].event);\r
- }\r
+ for(i=0; i< action->eventListCnt;i++ ) {\r
+ SetEvent( action->eventList[i].task, action->eventList[i].event);\r
+ }\r
}\r
// Calc new expire val and state\r
Os_SchTblUpdateState(sched_obj);\r
*/\r
void Os_SchTblInit( void ) {\r
OsSchTblType *s_p;\r
- for( int i=0; i < Os_CfgGetSchedCnt();i++ ) {\r
+ for( int i=0; i < OS_SCHTBL_CNT;i++ ) {\r
s_p = Os_CfgGetSched(i);\r
\r
ScheduleTableConsistenyCheck(s_p);\r
\r
void Os_SchTblAutostart( void ) {\r
\r
- for(int j=0; j < Os_CfgGetSchedCnt(); j++ ) {\r
+ for(int j=0; j < OS_SCHTBL_CNT; j++ ) {\r
OsSchTblType *sPtr;\r
sPtr = Os_CfgGetSched(j);\r
\r
case SCHTBL_AUTOSTART_RELATIVE:\r
StartScheduleTableRel(j,autoPtr->offset);\r
break;\r
-#if defined(OS_SC2) || defined(OS_SC4)\r
+ #if defined(OS_SC2) || defined(OS_SC4)\r
case SCHTBL_AUTOSTART_SYNCHRONE:\r
/* TODO: */\r
break;\r
-#endif\r
+ #endif\r
default:\r
assert(0); // Illegal value\r
break;\r
*\r
* @param stbl Ptr to a Schedule Table.\r
*/\r
-void Os_SchTblUpdateState( OsSchTblType *stbl ) {\r
+static void Os_SchTblUpdateState( OsSchTblType *stbl ) {\r
\r
TickType delta;\r
TickType initalOffset;\r
OsSchTblType *nextStblPtr;\r
_Bool handleLast = 0;\r
\r
-\r
-\r
if( (stbl->expire_curr_index) == (SA_LIST_CNT(&stbl->expirePointList) - 1) ) {\r
/* We are at the last expiry point */\r
finalOffset = Os_SchTblGetFinalOffset(stbl);\r
/** @req OS067 */\r
\r
_Bool os_pcb_pid_valid( OsPcbType *restrict pcb ) {\r
- return ( pcb->pid > Os_CfgGetTaskCnt() ) ? 0 : 1;\r
+ return ( pcb->pid > OS_TASK_CNT ) ? 0 : 1;\r
}\r
/**\r
* Start an extended task.\r
*\r
*/\r
void Os_TaskStartExtended( void ) {\r
- OsPcbType *pcb;\r
\r
- PRETASKHOOK();\r
+ OsPcbType *pcb;\r
\r
pcb = Os_TaskGetCurrent();\r
+#if 0\r
Os_ResourceGetInternal();\r
Os_TaskMakeRunning(pcb);\r
+#endif\r
+\r
+// PRETASKHOOK();\r
\r
Os_ArchFirstCall();\r
\r
+ /* We got back without any TerminateTask() or ChainTask()\r
+ *\r
+ * OSEK:\r
+ * Each task shall terminate itself at the end of its code.\r
+ * Ending the task without a call to TerminateTask or ChainTask\r
+ * is strictly forbidden and causes undefined behaviour.\r
+ *\r
+ * Autosar:\r
+ * OS052, OS069, OS070 and OS239\r
+ * */\r
+\r
/** @req OS239 */\r
Irq_Disable();\r
if( Os_IrqAnyDisabled() ) {\r
Os_IrqClearAll();\r
}\r
\r
-// TODO:Dont I have to check this at terminate task also?\r
+ /** @req OS070 */\r
+ if( Os_TaskOccupiesResources(pcb) ) {\r
+ Os_ResourceFreeAll(pcb);\r
+ }\r
\r
/** @req OS069 */\r
ERRORHOOK(E_OS_MISSINGEND);\r
*/\r
\r
void Os_TaskStartBasic( void ) {\r
- OsPcbType *pcb;\r
\r
- PRETASKHOOK();\r
+ OsPcbType *pcb;\r
\r
pcb = Os_TaskGetCurrent();\r
+#if 0\r
Os_ResourceGetInternal();\r
Os_TaskMakeRunning(pcb);\r
- Os_ArchFirstCall();\r
+#endif\r
+\r
+// PRETASKHOOK();\r
\r
+ Os_ArchFirstCall();\r
\r
/** @req OS239 */\r
Irq_Disable();\r
Os_IrqClearAll();\r
}\r
\r
+ /** @req OS070 */\r
+ if( Os_TaskOccupiesResources(pcb) ) {\r
+ Os_ResourceFreeAll(pcb);\r
+ }\r
+\r
/** @req OS069 */\r
ERRORHOOK(E_OS_MISSINGEND);\r
\r
OsPcbType *top_prio_pcb = NULL;\r
OsPriorityType top_prio = PRIO_ILLEGAL;\r
\r
- OS_DEBUG(D_TASK,"os_find_top_prio_proc\n");\r
+// OS_DEBUG(D_TASK,"os_find_top_prio_proc\n");\r
\r
TAILQ_FOREACH(i_pcb,& os_sys.ready_head,ready_list) {\r
// all ready task are canidates\r
* ActivateTask()\r
* WaitEvent()\r
* TerminateTask()\r
+ * ChainTask()\r
*\r
* @param force Force a re-scheduling\r
*\r
*/\r
-void Os_Dispatch( _Bool force ) {\r
+void Os_Dispatch( uint32_t op ) {\r
OsPcbType *pcbPtr;\r
- OsPcbType *currPcbPtr;\r
- (void)force;\r
+ OsPcbType *currPcbPtr = Os_TaskGetCurrent();\r
\r
assert(os_sys.int_nest_cnt == 0);\r
- assert(os_sys.scheduler_lock == 0 );\r
+ assert(Os_SchedulerResourceIsFree());\r
+\r
+ /* When calling post hook we must still be in ST_RUNNING */\r
+ assert( currPcbPtr->state & ST_RUNNING );\r
+ POSTTASKHOOK();\r
+\r
+ /* Go the correct state for running task */\r
+ if( op & ( OP_SET_EVENT | OP_SCHEDULE | OP_RELEASE_RESOURCE )) {\r
+ Os_TaskRunningToReady(currPcbPtr);\r
+ } else if( op & OP_WAIT_EVENT ) {\r
+ Os_TaskMakeWaiting(currPcbPtr);\r
+ } else if( op & OP_ACTIVATE_TASK ) {\r
+ Os_TaskMakeReady(currPcbPtr);\r
+ } else if( op & OP_CHAIN_TASK ) {\r
+ assert( os_sys.chainedPcbPtr != NULL );\r
+\r
+ /* # from chain top\r
+ * ----------------------------------------------------------\r
+ * 1 1 1 1 1->RUNNING\r
+ * 2 1 1 2 1->READY, 2->RUNNING\r
+ * 3 1 2 2 1->SUSPENDED/READY*, 2->RUNNING\r
+ * 4 1 2 3 1->SUSPENDED/READY*, 2->READY , 3-RUNNING\r
+ *\r
+ * *) Depends on the number of activations.\r
+ *\r
+ * - Chained task is always READY when coming from ChainTask()\r
+ */\r
+ if( currPcbPtr != os_sys.chainedPcbPtr ) {\r
+ /* #3 and #4 */\r
+ --currPcbPtr->activations;\r
+ if( currPcbPtr->activations <= 0 ) {\r
+ currPcbPtr->activations = 0;\r
+ Os_TaskMakeSuspended(currPcbPtr);\r
+ } else {\r
+ Os_TaskRunningToReady(currPcbPtr);\r
+ }\r
+ /* Chained task is already in READY */\r
+ }\r
+ os_sys.chainedPcbPtr = NULL;\r
+\r
+ } else if( op & OP_TERMINATE_TASK ) {\r
+ /*@req OSEK TerminateTask\r
+ * In case of tasks with multiple activation requests,\r
+ * terminating the current instance of the task automatically puts the next\r
+ * instance of the same task into the ready state\r
+ */\r
+ --currPcbPtr->activations;\r
+\r
+ if( currPcbPtr->activations <= 0 ) {\r
+ currPcbPtr->activations = 0;\r
+ Os_TaskMakeSuspended(currPcbPtr);\r
+ }\r
+ } else {\r
+ assert(0);\r
+ }\r
\r
pcbPtr = Os_TaskGetTop();\r
- currPcbPtr = Os_TaskGetCurrent();\r
+\r
+\r
+\r
/* Swap if we found any process or are forced (multiple activations)*/\r
if( pcbPtr != currPcbPtr ) {\r
- /* Add us to the ready list */\r
- if( currPcbPtr->state & ST_RUNNING ) {\r
+\r
+ if( (op & OP_CHAIN_TASK) && ( currPcbPtr == os_sys.chainedPcbPtr ) ) {\r
+ /* #2 */\r
Os_TaskRunningToReady(currPcbPtr);\r
}\r
-\r
/*\r
* Swap context\r
*/\r
- /** @req OS052 */\r
- POSTTASKHOOK();\r
assert(pcbPtr!=NULL);\r
\r
Os_ResourceReleaseInternal();\r
#endif\r
}\r
#endif\r
+ OS_DEBUG(D_TASK,"Swapping to: %s\n",pcbPtr->name);\r
+ Os_TaskSwapContext(currPcbPtr,pcbPtr);\r
\r
- Os_ArchSwapContext(currPcbPtr,pcbPtr);\r
+ /* ActivateTask, SetEvent, Schedule, .. */\r
+// pcbPtr = Os_TaskGetCurrent();\r
+// Os_TaskMakeRunning(pcbPtr);\r
+// PRETASKHOOK();\r
\r
- pcbPtr = Os_TaskGetCurrent();\r
- Os_TaskMakeRunning(pcbPtr);\r
-\r
- Os_ResourceGetInternal();\r
-\r
- PRETASKHOOK();\r
+// Os_ResourceGetInternal();\r
\r
} else {\r
- /* We want to run the same task, again. This only happens\r
- * when we have multiple activation of a basic task (\r
- * extended tasks have an activation limit of 1)\r
- */\r
-\r
+ OS_DEBUG(D_TASK,"Continuing task %s\n",pcbPtr->name);\r
/* Setup the stack again, and just call the basic task */\r
Os_StackSetup(pcbPtr);\r
+ /* TODO: release and get the internal resource ? */\r
+ Os_TaskMakeRunning(pcbPtr);\r
+ PRETASKHOOK();\r
Os_ArchSetSpAndCall(pcbPtr->stack.curr,Os_TaskStartBasic);\r
+ assert(0);\r
}\r
}\r
\r
-// We come here from\r
-// - os_init\r
\r
-volatile static int a1, b1, c1;\r
-volatile static OsPcbType *o1;\r
-volatile static OsPcbType *n1;\r
+/*\r
+ * Thoughts on task switching and memory protection\r
+ *\r
+ * If we would have had memory protection:\r
+ * - Applications have their own MMU settings.\r
+ * - Swapping between tasks in same Application does NOT involve the MMU.\r
+ * - When running a non-trusted Application I need will have to:\r
+ * - Run kernel in supervisor mode.\r
+ * - Trap the start of each task\r
+ * - All calls to the kernel will have a trap interface, i.e. Os_ResourceGetInternal(ActivateTask(TASK_ID_foo);\r
+ * - An ISR2:\r
+ * - The interupt is taken, the kernel runs in supervisor mode\r
+ * - If the ISR2 activates\r
+ *\r
+ * Stack design:\r
+ * ALT1: 1 kernel stack...\r
+ * ALT2:\r
+ *\r
+ * Do we need virtual memory??\r
+ */\r
\r
-void hej(int a, int b, int c, OsPcbType *o, OsPcbType *n) {\r
- a1 = a;\r
- b1 = b;\r
- c1 = c;\r
- o1 = o;\r
- n1 = n;\r
+void Os_TaskSwapContext(OsPcbType *old_pcb, OsPcbType *new_pcb ) {\r
+ set_curr_pcb(new_pcb);\r
+ Os_ResourceGetInternal();\r
+ Os_TaskMakeRunning(new_pcb);\r
+ /* TODO: The pretask hook is not called with the right stack\r
+ * (it's called on the old task stack, not the new ) */\r
+ PRETASKHOOK();\r
+ Os_ArchSwapContext(old_pcb,new_pcb);\r
}\r
\r
-/**\r
- * Called when a task is to be run for the first time.\r
- */\r
void Os_TaskSwapContextTo(OsPcbType *old_pcb, OsPcbType *new_pcb ) {\r
-\r
- hej(1, 2, 3, old_pcb, new_pcb);\r
-\r
+ set_curr_pcb(new_pcb);\r
+ Os_ResourceGetInternal();\r
+ Os_TaskMakeRunning(new_pcb);\r
+ PRETASKHOOK();\r
Os_ArchSwapContextTo(old_pcb,new_pcb);\r
- /* TODO: When do we return here ?? */\r
+ assert(0);\r
}\r
\r
\r
}\r
\r
\r
+#define TASK_CHECK_ID(x) \\r
+ if( (x) > OS_TASK_CNT) { \\r
+ rv = E_OS_ID; \\r
+ goto err; \\r
+ }\r
+\r
+\r
/**\r
* Returns the state of a task (running, ready, waiting, suspended)\r
* at the time of calling GetTaskState.\r
*/\r
\r
StatusType GetTaskState(TaskType TaskId, TaskStateRefType State) {\r
- state_t curr_state = os_pcb_get_state(os_get_pcb(TaskId));\r
+ state_t curr_state;\r
StatusType rv = E_OK;\r
\r
+ TASK_CHECK_ID(TaskId);\r
+\r
+ curr_state = os_pcb_get_state(os_get_pcb(TaskId));\r
+\r
// TODO: Lazy impl. for now */\r
switch(curr_state) {\r
case ST_RUNNING: *State = TASK_STATE_RUNNING; break;\r
* @param task_id Reference to the task which is currently running\r
* @return\r
*/\r
-StatusType GetTaskID( TaskRefType task_id ) {\r
- *task_id = os_sys.curr_pcb->pid;\r
- return E_OK;\r
+StatusType GetTaskID( TaskRefType TaskID ) {\r
+ StatusType rv = E_OK;\r
+ *TaskID = INVALID_TASK;\r
+\r
+ /* Test specification say return CALLEVEL if in ISR\r
+ * but impl. spec says otherwise */\r
+ if( os_sys.int_nest_cnt == 0 ) {\r
+ if( os_sys.curr_pcb->state & ST_RUNNING ) {\r
+ *TaskID = os_sys.curr_pcb->pid;\r
+ } else {\r
+ /* This is not a real error since this could\r
+ * be the case when called from ErrorHook */
+ }\r
+ }\r
+\r
+ return rv;\r
}\r
\r
\r
return (ISRType)Os_TaskGetCurrent()->pid;\r
}\r
\r
-#define TASK_CHECK_ID(x) \\r
- if( (x) > Os_CfgGetTaskCnt()) { \\r
- rv = E_OS_ID; \\r
- goto err; \\r
+static inline void Os_Arc_SetCleanContext( OsPcbType *pcb ) {\r
+ if (pcb->proc_type == PROC_EXTENDED) {\r
+ /** @req OSEK ActivateTask Cleanup events\r
+ * OSEK,ActivateTask, When an extended task is transferred from suspended\r
+ * state into ready state all its events are cleared.*/\r
+ pcb->ev_set = 0;\r
+ pcb->ev_wait = 0;\r
}\r
-\r
+ Os_StackSetup(pcb);\r
+ Os_ArchSetTaskEntry(pcb);\r
+ Os_ArchSetupContext(pcb);\r
+}\r
\r
/**\r
* The task <TaskID> is transferred from the suspended state into\r
OsPcbType *pcb = os_get_pcb(TaskID);\r
StatusType rv = E_OK;\r
\r
- OS_DEBUG(D_TASK,"ActivateTask %s\n",pcb->name);\r
+ OS_DEBUG(D_TASK,"# ActivateTask %s\n",pcb->name);\r
\r
#if (OS_STATUS_EXTENDED == STD_ON )\r
+ /* extended */\r
TASK_CHECK_ID(TaskID);\r
+#endif\r
\r
+ Irq_Save(msr);\r
/* @req OS093 ActivateTask */\r
if( Os_IrqAnyDisabled() ) {\r
+ /* Standard */\r
rv = E_OS_DISABLEDINT;\r
goto err;\r
}\r
-#endif\r
-\r
- Irq_Save(msr);\r
-\r
- if( os_pcb_get_state(pcb) == ST_SUSPENDED ) {\r
- pcb->activations++;\r
- if (pcb->proc_type == PROC_EXTENDED) {\r
- /** @req OSEK ActivateTask Cleanup events\r
- * OSEK,ActivateTask, When an extended task is transferred from suspended\r
- * state into ready state all its events are cleared.*/\r
- pcb->ev_set = 0;\r
- pcb->ev_wait = 0;\r
- }\r
- Os_StackSetup(pcb);\r
- Os_ArchSetTaskEntry(pcb);\r
- Os_ArchSetupContext(pcb);\r
- Os_TaskMakeReady(pcb);\r
- } else {\r
-\r
- if( pcb->proc_type == PROC_EXTENDED ) {\r
- /** @req OSEK Activate task.\r
- * An extended task be activated once. See Chapter 4.3 in OSEK\r
- */\r
- rv = E_OS_LIMIT;\r
- goto err;\r
- }\r
\r
+ pcb->activations++;\r
+ if( os_pcb_get_state(pcb) != ST_SUSPENDED ) {\r
/** @req OSEK_? Too many task activations */\r
- if( pcb->activations == pcb->activationLimit ) {\r
+ if( pcb->activations >= (pcb->activationLimit + 1) ) {\r
+ /* Standard */\r
rv=E_OS_LIMIT;\r
+ Irq_Restore(msr);\r
+ --pcb->activations;\r
goto err;\r
- } else {\r
- pcb->activations++;\r
}\r
+ } else {\r
+ /* We have a suspended task, make it ready for use */\r
+ assert( pcb->activations == 1 );\r
+ Os_Arc_SetCleanContext(pcb);\r
+ Os_TaskMakeReady(pcb);\r
}\r
\r
-\r
- /* Preempt only if higher prio than us */\r
- if( (pcb->scheduling == FULL) &&\r
- (os_sys.int_nest_cnt == 0) && (pcb->prio > Os_TaskGetCurrent()->prio) )\r
+ /* Preempt only if we are preemptable and target has higher prio than us */\r
+ if( (Os_TaskGetCurrent()->scheduling == FULL) &&\r
+ (os_sys.int_nest_cnt == 0) &&\r
+ (pcb->prio > Os_TaskGetCurrent()->prio) &&\r
+ (Os_SchedulerResourceIsFree()))\r
{\r
- Os_Dispatch(0);\r
+ Os_Dispatch(OP_ACTIVATE_TASK);\r
}\r
\r
Irq_Restore(msr);\r
StatusType rv = E_OK;\r
uint32_t flags;\r
\r
- OS_DEBUG(D_TASK,"TerminateTask %s\n",curr_pcb->name);\r
+ OS_DEBUG(D_TASK,"# TerminateTask %s\n",curr_pcb->name);\r
\r
#if (OS_STATUS_EXTENDED == STD_ON )\r
\r
goto err;\r
}\r
\r
- /** @req OS070 */\r
- if( Os_ResourceCheckAndRelease(curr_pcb) == 1 ) {\r
+#if 0\r
+ if ( Os_SchedulerResourceIsOccupied() ) {\r
rv = E_OS_RESOURCE;\r
goto err;\r
-\r
}\r
-\r
-\r
#endif\r
\r
-\r
- Irq_Save(flags);\r
-\r
- --curr_pcb->activations;\r
-\r
-\r
-// assert(curr_pcb->activations>=0);\r
-\r
- /*@req OSEK TerminateTask\r
- * In case of tasks with multiple activation requests,\r
- * terminating the current instance of the task automatically puts the next\r
- * instance of the same task into the ready state\r
- */\r
- if( curr_pcb->activations <= 0 ) {\r
- curr_pcb->activations = 0;\r
- Os_TaskMakeSuspended(curr_pcb);\r
- } else {\r
- /* We need to add ourselves to the ready list again,\r
- * with a startup context. */\r
+ if( Os_TaskOccupiesResources(curr_pcb) ) {\r
+ /* Note! Do NOT release the resource here */\r
+ rv = E_OS_RESOURCE;\r
+ goto err;\r
}\r
\r
-// Os_ContextReInit(curr_pcb);\r
+#endif\r
+ Irq_Save(flags);\r
\r
/* Force the dispatcher to find something, even if its us */\r
- Os_Dispatch(1);\r
+ Os_Dispatch(OP_TERMINATE_TASK);\r
\r
- Irq_Restore(flags);\r
- // It must find something here...otherwise something is very wrong..\r
assert(0);\r
\r
- rv = E_NOT_OK;\r
- goto err;\r
-\r
-\r
OS_STD_END(OSServiceId_TerminateTask);\r
}\r
\r
StatusType ChainTask( TaskType TaskId ) {\r
- StatusType rv;\r
+ OsPcbType *curr_pcb = Os_TaskGetCurrent();\r
+ StatusType rv = E_OK;\r
uint32_t flags;\r
+ OsPcbType *pcb = os_get_pcb(TaskId);\r
+\r
+\r
+ OS_DEBUG(D_TASK,"# ChainTask %s\n",curr_pcb->name);\r
\r
#if (OS_STATUS_EXTENDED == STD_ON )\r
+ /* extended */\r
TASK_CHECK_ID(TaskId);\r
\r
if( os_sys.int_nest_cnt != 0 ) {\r
- rv = E_OS_CALLEVEL;\r
+ /* extended */\r
+ rv = E_OS_CALLEVEL;\r
goto err;\r
}\r
+\r
#endif\r
\r
Irq_Save(flags);\r
- rv = ActivateTask(TaskId);\r
- /* TODO: more more here..*/\r
- TerminateTask();\r
- Irq_Restore(flags);\r
\r
- if (rv != E_OK) goto err;\r
+#if (OS_STATUS_EXTENDED == STD_ON )\r
+#if 0\r
+ if ( Os_SchedulerResourceIsOccupied() ) {\r
+ /* extended */\r
+ rv = E_OS_RESOURCE;\r
+ Irq_Restore(flags);\r
+ goto err;\r
+ }\r
+#endif\r
+\r
+ if( Os_TaskOccupiesResources(curr_pcb) ) {\r
+ /* extended */\r
+ rv = E_OS_RESOURCE;\r
+ Irq_Restore(flags);\r
+ goto err;\r
+ }\r
+#endif\r
+\r
+// if( os_pcb_get_state(pcb) != ST_SUSPENDED ) {\r
+ if (curr_pcb != pcb) {\r
+ /** @req OSEK_? Too many task activations */\r
+ if( (pcb->activations + 1) > pcb->activationLimit ) {\r
+ /* standard */\r
+ rv = E_OS_LIMIT;\r
+ Irq_Restore(flags);\r
+ goto err;\r
+ }\r
+\r
+ if( os_pcb_get_state(pcb) == ST_SUSPENDED ) {\r
+ assert( pcb->activations == 0 );\r
+ Os_Arc_SetCleanContext(pcb);\r
+ Os_TaskMakeReady(pcb);\r
+ }\r
+\r
+ pcb->activations++;\r
+\r
+ }\r
+\r
+ os_sys.chainedPcbPtr = pcb;\r
+\r
+ Os_Dispatch(OP_CHAIN_TASK);\r
+\r
+ assert( 0 );\r
\r
OS_STD_END_1(OSServiceId_ChainTask,TaskId);\r
}\r
*\r
*/\r
StatusType Schedule( void ) {\r
-// OsPcbType *pcb;\r
-// OsPcbType *curr_pcb = get_curr_pcb();\r
StatusType rv = E_OK;\r
uint32_t flags;\r
+ OsPcbType *curr_pcb = get_curr_pcb();\r
+\r
+ OS_DEBUG(D_TASK,"# Schedule %s\n",Os_TaskGetCurrent()->name);\r
+\r
+ /* Check that we are not calling from interrupt context */\r
+ if( os_sys.int_nest_cnt != 0 ) {\r
+ rv = E_OS_CALLEVEL;\r
+ goto err;\r
+ }\r
+\r
+ if ( Os_TaskOccupiesResources(curr_pcb) ) {\r
+ rv = E_OS_RESOURCE;\r
+ goto err;\r
+ }\r
+\r
+ assert( Os_TaskGetCurrent()->state & ST_RUNNING );\r
\r
/* We need to figure out if we have an internal resource,\r
* otherwise no re-scheduling.\r
return E_OK;\r
}\r
\r
-#if 0\r
- if( os_get_resource_int_p() == NULL ) {\r
- /* We do nothing */\r
- return E_OK;\r
- }\r
-#endif\r
-\r
- /* Check that we are not calling from interrupt context */\r
- if( os_sys.int_nest_cnt != 0 ) {\r
- rv = E_OS_CALLEVEL;\r
- goto err;\r
+ Irq_Save(flags);\r
+ OsPcbType* top_pcb = Os_TaskGetTop();\r
+ /* only dispatch if some other ready task has higher prio */\r
+ if (top_pcb->prio > Os_TaskGetCurrent()->prio) {\r
+ Os_Dispatch(OP_SCHEDULE);\r
}\r
\r
- Irq_Save(flags);\r
- Os_Dispatch(0);\r
Irq_Restore(flags);\r
-\r
// Prevent label warning. Remove this when proper error handling is implemented.\r
if (0) goto err;\r
\r
+++ /dev/null
-\r
-# Figure out the most of the modules to use.\r
-OPTIMAL_USE = T32_TERM SIMPLE_PRINTF RAMLOG\r
-MOD_USE+=KERNEL MCU $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
-$(warning $(MOD_USE)) \r
-#MOD_USE+=KERNEL MCU T32_TERM SIMPLE_PRINTF RAMLOG\r
-\r
+++ /dev/null
-/* \r
-* Configuration of module Os (Os_Cfg.c)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Wed May 05 23:09:13 CEST 2010\r
-*/\r
-\r
- \r
-\r
-#include <stdlib.h>\r
-#include <stdint.h>\r
-#include "Platform_Types.h"\r
-#include "Os.h" // includes Os_Cfg.h\r
-#include "os_config_macros.h"\r
-#include "kernel.h"\r
-#include "kernel_offset.h"\r
-#include "alist_i.h"\r
-#include "Mcu.h"\r
-\r
-extern void dec_exception( void );\r
-\r
-// Set the os tick frequency\r
-OsTickType OsTickFreq = 1000;\r
-\r
-\r
-// ############################### DEBUG OUTPUT #############################\r
-uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
- \r
-\r
-\r
-// ################################# COUNTERS ###############################\r
-GEN_COUNTER_HEAD {\r
- GEN_COUNTER( COUNTER_ID_OsTick,\r
- "OsTick",\r
- COUNTER_TYPE_HARD,\r
- COUNTER_UNIT_NANO,\r
- 0xffff,\r
- 1,\r
- 1,\r
- 0),\r
- GEN_COUNTER( COUNTER_ID_soft_1,\r
- "soft_1",\r
- COUNTER_TYPE_SOFT,\r
- COUNTER_UNIT_NANO,\r
- 65535,\r
- 1,\r
- 1,\r
- 0),\r
- GEN_COUNTER( COUNTER_ID_soft_2,\r
- "soft_2",\r
- COUNTER_TYPE_SOFT,\r
- COUNTER_UNIT_NANO,\r
- 65535,\r
- 1,\r
- 1,\r
- 0),\r
-};\r
-\r
-CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
-\r
-// ################################## ALARMS ################################\r
-\r
-GEN_ALARM_HEAD {\r
- GEN_ALARM( ALARM_ID_c_soft_1_inc_counter_2,\r
- "c_soft_1_inc_cou",\r
- COUNTER_ID_soft_1,\r
- NULL,\r
- ALARM_ACTION_INCREMENTCOUNTER,\r
- NULL,\r
- NULL,\r
- COUNTER_ID_soft_2 ),\r
- GEN_ALARM( ALARM_ID_c_soft_1_setevent_etask_m,\r
- "c_soft_1_seteven",\r
- COUNTER_ID_soft_1,\r
- NULL,\r
- ALARM_ACTION_SETEVENT,\r
- TASK_ID_etask_sup_m,\r
- EVENT_MASK_notif,\r
- NULL ),\r
- GEN_ALARM( ALARM_ID_c_sys_1_setevent_etask_m,\r
- "c_sys_1_setevent",\r
- COUNTER_ID_OsTick,\r
- NULL,\r
- ALARM_ACTION_SETEVENT,\r
- TASK_ID_etask_sup_m,\r
- EVENT_MASK_notif,\r
- NULL ),\r
- GEN_ALARM( ALARM_ID_c_sys_activate_btask_h,\r
- "c_sys_activate_b",\r
- COUNTER_ID_OsTick,\r
- NULL,\r
- ALARM_ACTION_ACTIVATETASK,\r
- TASK_ID_btask_sup_h,\r
- NULL,\r
- NULL ),\r
-};\r
-\r
-// ################################ RESOURCES ###############################\r
-GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE(\r
- RES_ID_int_1,\r
- RESOURCE_TYPE_INTERNAL,\r
- 0\r
- ),\r
- GEN_RESOURCE(\r
- RES_ID_std_prio_3,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
- GEN_RESOURCE(\r
- RES_ID_std_prio_4,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
- GEN_RESOURCE(\r
- RES_ID_std_prio_5,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
-};\r
-\r
-// ############################## STACKS (TASKS) ############################\r
-DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
-DECLARE_STACK(btask_sup_h,2048);\r
-DECLARE_STACK(btask_sup_l,2048);\r
-DECLARE_STACK(btask_sup_m,2048);\r
-DECLARE_STACK(etask_master,2048);\r
-DECLARE_STACK(etask_sup_h,2048);\r
-DECLARE_STACK(etask_sup_l,2048);\r
-DECLARE_STACK(etask_sup_m,2048);\r
-\r
-// ################################## TASKS #################################\r
-GEN_TASK_HEAD {\r
- GEN_ETASK( OsIdle,\r
- 0,\r
- FULL,\r
- TRUE,\r
- NULL,\r
- 0 \r
- ),\r
- GEN_BTASK(\r
- btask_sup_h,\r
- 6,\r
- FULL,\r
- FALSE,\r
- NULL,\r
- RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0,\r
- 1\r
- ),\r
- \r
- GEN_BTASK(\r
- btask_sup_l,\r
- 2,\r
- FULL,\r
- FALSE,\r
- NULL,\r
- RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0,\r
- 1\r
- ),\r
- \r
- GEN_BTASK(\r
- btask_sup_m,\r
- 4,\r
- FULL,\r
- FALSE,\r
- NULL,\r
- RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0,\r
- 1\r
- ),\r
- \r
- GEN_ETASK(\r
- etask_master,\r
- 1,\r
- FULL,\r
- TRUE,\r
- NULL,\r
- 0\r
- ),\r
- \r
- \r
- GEN_ETASK(\r
- etask_sup_h,\r
- 6,\r
- FULL,\r
- FALSE,\r
- NULL,\r
- RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0\r
- ),\r
- \r
- \r
- GEN_ETASK(\r
- etask_sup_l,\r
- 2,\r
- FULL,\r
- FALSE,\r
- NULL,\r
- RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0\r
- ),\r
- \r
- \r
- GEN_ETASK(\r
- etask_sup_m,\r
- 4,\r
- FULL,\r
- FALSE,\r
- NULL,\r
- RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0\r
- ),\r
- \r
- \r
-};\r
-\r
-// ################################## HOOKS #################################\r
-GEN_HOOKS( \r
- StartupHook, \r
- NULL, \r
- ShutdownHook, \r
- ErrorHook,\r
- PreTaskHook, \r
- PostTaskHook \r
-);\r
-\r
-// ################################## ISRS ##################################\r
-\r
-\r
-// ############################ SCHEDULE TABLES #############################\r
-\r
-// Table data 0\r
-\r
-GEN_SCHTBL_TASK_LIST_HEAD( 0, 5 ) { \r
- \r
- TASK_ID_etask_sup_m,\r
- \r
-};\r
-\r
-\r
-\r
-\r
-GEN_SCHTBL_EVENT_LIST_HEAD( 0, 7 ) {\r
- \r
- { \r
- EVENT_MASK_notif, \r
- TASK_ID_etask_sup_m \r
- },\r
- \r
-};\r
-\r
-\r
-GEN_SCHTBL_TASK_LIST_HEAD( 0, 11 ) { \r
- \r
- TASK_ID_etask_sup_m,\r
- \r
-};\r
-\r
-GEN_SCHTBL_EVENT_LIST_HEAD( 0, 11 ) {\r
- \r
- { \r
- EVENT_MASK_notif, \r
- TASK_ID_etask_sup_m \r
- },\r
- \r
-};\r
-\r
-\r
-GEN_SCHTBL_EXPIRY_POINT_HEAD( 0 ) {\r
- GEN_SCHTBL_EXPIRY_POINT_W_TASK(0, 5),\r
- GEN_SCHTBL_EXPIRY_POINT_W_EVENT(0, 7),\r
- GEN_SCHTBL_EXPIRY_POINT_W_TASK_EVENT(0, 11),\r
- \r
-};\r
-\r
-GEN_SCHTBL_AUTOSTART(\r
- 0,\r
- SCHTBL_AUTOSTART_ABSOLUTE,\r
- 1, \r
- OSDEFAULTAPPMODE\r
-);\r
-\r
-// Table data 1\r
-\r
-GEN_SCHTBL_TASK_LIST_HEAD( 1, 2 ) { \r
- \r
- TASK_ID_etask_sup_m,\r
- \r
-};\r
-\r
-\r
-\r
-GEN_SCHTBL_EXPIRY_POINT_HEAD( 1 ) {\r
- GEN_SCHTBL_EXPIRY_POINT_W_TASK(1, 2),\r
- \r
-};\r
-\r
-\r
-// Table heads\r
-GEN_SCHTBL_HEAD {\r
- GEN_SCHEDULETABLE(\r
- 0,\r
- "0",\r
- COUNTER_ID_soft_1,\r
- SINGLE_SHOT,\r
- 15,\r
- GEN_SCHTBL_AUTOSTART_NAME(0)\r
- ),\r
- GEN_SCHEDULETABLE(\r
- 1,\r
- "1",\r
- COUNTER_ID_soft_1,\r
- SINGLE_SHOT,\r
- 5,\r
- NULL\r
- ),\r
-};\r
-\r
-GEN_PCB_LIST()\r
-\r
-uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
-\r
-GEN_IRQ_VECTOR_TABLE_HEAD {};\r
-GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
-GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
-\r
-#include "os_config_funcs.h"\r
+++ /dev/null
-/* \r
-* Configuration of module Os (Os_Cfg.h)\r
-* \r
-* Created by: \r
-* Configured for (MCU): MPC551x\r
-* \r
-* Module editor vendor: ArcCore\r
-* Module editor version: 2.0.7\r
-* \r
-* \r
-* Generated by Arctic Studio (http://arccore.com)\r
-* on Wed May 05 23:09:13 CEST 2010\r
-*/\r
-\r
-\r
-#if (OS_SW_MAJOR_VERSION != 2) \r
-#error "Os: Configuration file version differs from BSW version."\r
-#endif\r
-\r
-\r
-#ifndef OS_CFG_H_\r
-#define OS_CFG_H_\r
-\r
-\r
-// Alarm Id's\r
-#define ALARM_ID_c_soft_1_inc_counter_2 0\r
-#define ALARM_ID_c_soft_1_setevent_etask_m 1\r
-#define ALARM_ID_c_sys_1_setevent_etask_m 2\r
-#define ALARM_ID_c_sys_activate_btask_h 3\r
-\r
-// Counter Id's\r
-#define COUNTER_ID_OsTick 0\r
-#define COUNTER_ID_soft_1 1\r
-#define COUNTER_ID_soft_2 2\r
-\r
-// Counter macros\r
-#define OSMAXALLOWEDVALUE_OsTick 65535\r
-#define OSMAXALLOWEDVALUE_soft_1 65535\r
-#define OSMAXALLOWEDVALUE_soft_2 65535\r
-\r
-\r
-// Event masks\r
-#define EVENT_MASK_kill 32768\r
-#define EVENT_MASK_notif 1\r
-\r
-// Isr Id's\r
-\r
-// Resource Id's\r
-#define RES_ID_int_1 0\r
-#define RES_ID_std_prio_3 1\r
-#define RES_ID_std_prio_4 2\r
-#define RES_ID_std_prio_5 3\r
-\r
-// Linked resource id's\r
-\r
-// Resource masks\r
-#define RES_MASK_int_1 (1 << 0)\r
-#define RES_MASK_std_prio_3 (1 << 1)\r
-#define RES_MASK_std_prio_4 (1 << 2)\r
-#define RES_MASK_std_prio_5 (1 << 3)\r
-\r
-// Task Id's\r
-#define TASK_ID_OsIdle 0\r
-#define TASK_ID_btask_sup_h 1\r
-#define TASK_ID_btask_sup_l 2\r
-#define TASK_ID_btask_sup_m 3\r
-#define TASK_ID_etask_master 4\r
-#define TASK_ID_etask_sup_h 5\r
-#define TASK_ID_etask_sup_l 6\r
-#define TASK_ID_etask_sup_m 7\r
-\r
-// Task entry points\r
-void OsIdle( void );\r
-void btask_sup_h( void );\r
-void btask_sup_l( void );\r
-void btask_sup_m( void );\r
-void etask_master( void );\r
-void etask_sup_h( void );\r
-void etask_sup_l( void );\r
-void etask_sup_m( void );\r
-\r
-// Schedule table id's\r
-#define SCHTBL_ID_0 0\r
-#define SCHTBL_ID_1 1\r
-\r
-// Stack size\r
-#define OS_INTERRUPT_STACK_SIZE 2048\r
-#define OS_OSIDLE_STACK_SIZE 512\r
-\r
-#define OS_ALARM_CNT 4 \r
-#define OS_TASK_CNT 8\r
-#define OS_SCHTBL_CNT 2\r
-#define OS_COUNTER_CNT 3\r
-#define OS_EVENTS_CNT 2\r
-#define OS_ISRS_CNT 0\r
-#define OS_RESOURCE_CNT 4\r
-#define OS_LINKED_RESOURCE_CNT 0\r
-\r
-#define CFG_OS_DEBUG STD_ON\r
-\r
-#define OS_SC1 STD_ON \r
-#define OS_STACK_MONITORING STD_ON\r
-#define OS_STATUS_EXTENDED STD_ON\r
-#define OS_USE_GET_SERVICE_ID STD_ON\r
-#define OS_USE_PARAMETER_ACCESS STD_ON\r
-#define OS_RES_SCHEDULER STD_ON\r
-\r
-#endif /*OS_CFG_H_*/\r
+++ /dev/null
-\r
-# included from rules.mk\r
-\r
-# =======================================================================\r
-# APPLICATION\r
-\r
-obj-y += test_master.o\r
-obj-y += test_01_task.o\r
-obj-y += test_02_resource.o\r
-obj-y += test_03_alarm.o\r
-obj-y += test_04_stable.o\r
-obj-y += test_05_const.o\r
-obj-y += test_06_event.o\r
-\r
-#obj-y += test_sup_01.o\r
-#obj-y += test_sup_02.o\r
-#obj-y += test_sup_03.o\r
-#obj-y += test_sup_04.o \r
-obj-y += test_framework.o\r
-\r
-obj-y += Os_Cfg.o\r
-\r
-# Not supported yet...\r
-#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
-\r
-# Grab the board the board files.\r
-include $(ROOTDIR)/boards/board_common.mk\r
-\r
-# What modules do we use\r
-MOD_USE+=KERNEL MCU\r
-\r
-MOD_USE+=T32_TERM\r
-#MOD_USE+=PROTECTIONHOOK STARTUPHOOK SHUTDOWNHOOK ERRORHOOK 1\r
-#MOD_USE+=PRETASKHOOK POSTTASKHOOK\r
-CFG+=CONSOLE_T32\r
-CFG+=CONSOLE_WINIDEA\r
-\r
-\r
-# TODO: Fix this....\r
-\r
-vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
-vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
-vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
-vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
-VPATH += $(vpath-y)\r
-VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
-\r
-\r
-# libs needed by us \r
-libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
-\r
-#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
-#ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
-\r
-inc-y += ..\r
-inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
-inc-y += $(ROOTDIR)/system/kernel/include\r
-inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
-inc-y += $(ROOTDIR)/drivers/include\r
-inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
-inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
-inc-y += ../config\r
-\r
-# What I want to build\r
-build-exe-y = $(target).elf\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#ifndef OS_TEST_H_\r
-#define OS_TEST_H_\r
-\r
-#include "test_framework.h"\r
-#include "debug.h"\r
-\r
-typedef void (*test_func_t)( void );\r
-\r
-#define TEST_FAIL(_text) test_fail((_text), __FILE__, __LINE__, __FUNCTION__ )\r
-#define TEST_OK() test_ok();\r
-#define TEST_ASSERT(_cond) if(!(_cond)) { TEST_FAIL(#_cond); }\r
-#define TEST_RUN() printf("Running test %d\n",test_nr);\r
-\r
-\r
-extern int test_suite;\r
-extern int test_nr;\r
-\r
-#define TASK_ID_ILL 99\r
-#define RES_ID_ILL 99\r
-#define ALARM_ID_ILL 99\r
-#define SCHTBL_ID_ILL 99\r
-#define COUNTER_ID_ILL 99\r
-\r
-#if 1\r
-#define SECTION_SUP\r
-#define SECTION_USER\r
-#else\r
-#define SECTION_SUP __attribute__ ((section(".text_app_sup")))\r
-#define SECTION_USER __attribute__ ((section(".text_app_user")))\r
-#endif\r
-\r
-#define SECTION_BSS_SUPER __attribute__ ((aligned (16),section(".bss")))\r
-#define SECTION_BSS_USER __attribute__ ((aligned (16),section(".bss")))\r
-\r
-#define OS_STR__(x) #x\r
-#define OS_STRSTR__(x) OS_STR__(x)\r
-\r
-#define DECLARE_TEST_BTASK(_nr, _task1, _task2, _task3 ) \\r
- __attribute__ ((section (".test_btask"))) const test_func_t btask_sup_matrix_ ## _nr[3] = { _task1, _task2, _task3 }\r
-\r
-#define DECLARE_TEST_ETASK(_nr, _task1, _task2, _task3 ) \\r
- __attribute__ ((section (".test_etask"))) const test_func_t etask_sup_matrix_ ## _nr[3] = { _task1, _task2, _task3 }\r
-\r
-#define DECLARE_TASKS(_nr) \\r
- void etask_sup_l_##_nr( void ); \\r
- void etask_sup_m_##_nr( void ); \\r
- void etask_sup_h_##_nr( void ); \\r
- void btask_sup_l_##_nr( void ); \\r
- void btask_sup_m_##_nr( void ); \\r
- void btask_sup_h_##_nr( void );\r
-\r
-\r
-/*\r
- * Declare tests\r
- */\r
-\r
-// Test master processes\r
-void OsIdle(void );\r
-void etask_master( void );\r
-void etask_sup_l( void ) SECTION_SUP;\r
-void etask_sup_m( void ) SECTION_SUP;\r
-void etask_sup_h( void ) SECTION_SUP;\r
-\r
-void btask_sup_l( void ) SECTION_SUP;\r
-void btask_sup_m( void ) SECTION_SUP;\r
-void btask_sup_h( void ) SECTION_SUP;\r
-\r
-\r
-// Tests\r
-DECLARE_TASKS(01);\r
-DECLARE_TASKS(02);\r
-DECLARE_TASKS(03);\r
-DECLARE_TASKS(04);\r
-\r
-#endif /* OS_TEST_H_ */\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tests tasks:\r
- *\r
- * OSEK\r
- * - ActivateTask E_OS_ID, E_OS_LIMIT\r
- * - TerminateTask E_OS_RESOURCE, E_OS_CALLEVEL\r
- * - ChainTask E_OS_ID, E_OS_LIMIT, E_OS_RESOURCE, E_OS_CALLLEVEL\r
- * - Schedule E_OS_CALLEVEL, E_OS_RESOURCE\r
- * - GetTaskID\r
- * - GetTaskState E_OS_ID\r
- *\r
- *\r
- * Limitations:\r
- * - No way to detect if in ISR1 or hooks\r
- * - NON tasks are not tested.\r
- * - ActivateTask() with own taskid?\r
- */\r
-\r
-#include "Os.h"\r
-#include "os_test.h"\r
-#include "arc.h"\r
-\r
-int btaskRunCnt = 0;\r
-\r
-static int status_100 = 0;\r
-\r
-void isr_l(void ) {\r
- StatusType rv;\r
- switch(test_nr) {\r
- case 11:\r
- rv = TerminateTask();\r
- TEST_ASSERT(rv=E_OS_CALLEVEL);\r
- break;\r
- case 12:\r
- break;\r
- case 13:\r
- break;\r
- default:\r
- while(1);\r
- }\r
-}\r
-\r
-void etask_sup_l_01(void) {\r
- _Bool done = 0;\r
- StatusType rv;\r
-\r
- while (!done) {\r
- TEST_RUN();\r
-\r
- switch (test_nr) {\r
- case 1:\r
- /*@req E_OS_ID ActivateTask */\r
- rv = ActivateTask(TASK_ID_ILL);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- test_nr = 2;\r
- break;\r
- case 2:\r
- /*@req E_OS_LIMIT ActivateTask\r
- * Test the activation limit and check that activated task is run\r
- * the activation limit times */\r
-\r
- /* Activate higher prio task to do the test */\r
- rv = ActivateTask(TASK_ID_btask_sup_h);\r
- TEST_ASSERT(rv == E_OK);\r
-\r
- /* Was it run activation times? */\r
- TEST_ASSERT(btaskRunCnt == Os_ArcTest_GetTaskActivationLimit(TASK_ID_btask_sup_m));\r
- test_nr = 10;\r
- break;\r
- case 10:\r
- /*@req E_OS_RESOURCE TerminateTask\r
- * Terminate a task that still holds resources\r
- * This is done in the TASK_ID_btask_sup_m task..\r
- */\r
- rv = ActivateTask(TASK_ID_btask_sup_m);\r
- TEST_ASSERT(rv == E_OK);\r
- test_nr++;\r
- break;\r
- case 11:\r
- /*@req E_OS_CALLEVEL TerminateTask */\r
- Os_ArcTest_SetIrqNestLevel(1);\r
- isr_l();\r
- Os_ArcTest_SetIrqNestLevel(0);\r
- test_nr=20;\r
- break;\r
-\r
- case 20:\r
- /*@req E_OS_ID ChainTask */\r
- rv = ChainTask(TASK_ID_ILL);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- test_nr = 100;\r
- case 21:\r
- /*@req E_OS_LIMIT ChainTask */\r
- case 22:\r
- /*@req E_OS_RESOURCE ChainTask */\r
- case 23:\r
- /*@req E_OS_CALLLEVEL ChainTask */\r
- break;\r
-\r
- case 30:\r
- /*@req E_OS_CALLEVEL Schedule */\r
- case 31:\r
- /*@req E_OS_RESOURCE Schedule */\r
- break;\r
-\r
- case 100:\r
- /* Check that tasks as run in priority order and that the oldest task\r
- * of the same priority should be scheduled first.\r
- * 1. esup_l: Activate(sup_m)\r
- * 2. bsup_m: Activate(sup_l) (should not be taken)\r
- * 3. bsup_m: Activate(sup_h) (taken)\r
- * 4. bsup_h: Terminate()\r
- * (We should now have bsup_m, esup_l, bsup_l )\r
- * 5. bsup_m: Terminate()\r
- * 6. esup_l : Terminate()\r
- * 7. bsup_l : Activate(esup_l) (found by dispatcher)\r
- * 8. esup_l: Back again!!!!\r
- *\r
- * */\r
- if(status_100==6) {\r
- test_nr=101;\r
- break;\r
- }\r
- btaskRunCnt = 0;\r
- rv = ActivateTask(TASK_ID_btask_sup_m);\r
- TEST_ASSERT(status_100=3);\r
- status_100=4;\r
- TerminateTask(); // Step 6.\r
-\r
- // Should never get here since we have restarded ourselves.\r
- assert(0);\r
- break;\r
- case 101:\r
- /* End Testing of this module */\r
- TerminateTask();\r
- break;\r
- default:\r
- while(1);\r
- }\r
- }\r
-}\r
-\r
-void btask_sup_l_01( void ) {\r
- switch(test_nr){\r
- case 100:\r
- btaskRunCnt++;\r
- /* Make it go up again */\r
- TEST_ASSERT(status_100=4);\r
- status_100=5;\r
- ActivateTask(TASK_ID_etask_sup_l); // Step 7.\r
- TEST_ASSERT(status_100=5);\r
- status_100=6;\r
- break;\r
- default:\r
- break;\r
- }\r
-\r
-}\r
-\r
-void btask_sup_m_01( void ) {\r
- int rv;\r
- switch(test_nr){\r
- case 2:\r
- btaskRunCnt++;\r
- TerminateTask();\r
- break;\r
- case 10:\r
- rv = GetResource(RES_ID_std_prio_3);\r
- TEST_ASSERT(rv == E_OK);\r
-\r
- rv = TerminateTask();\r
- TEST_ASSERT(rv==E_OS_RESOURCE);\r
-\r
- rv = ReleaseResource(RES_ID_std_prio_3);\r
- TEST_ASSERT(rv==E_OK);\r
- TerminateTask();\r
- break;\r
- case 100:\r
- /* We got here from etask_l, so it should be oldest */\r
- rv = ActivateTask(TASK_ID_btask_sup_l);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT(status_100==0);\r
- status_100=1;\r
- rv = ActivateTask(TASK_ID_btask_sup_h);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT(status_100==2);\r
- status_100=3;\r
- break;\r
- default:\r
- while(1);\r
- }\r
-\r
-}\r
-\r
-void btask_sup_h_01(void) {\r
- StatusType rv;\r
- int limit;\r
-\r
- switch (test_nr) {\r
- case 2:\r
- /* Activate a basic task to many times */\r
- limit = Os_ArcTest_GetTaskActivationLimit(TASK_ID_btask_sup_m);\r
- for (int i = 0; i < limit; i++) {\r
- rv = ActivateTask(TASK_ID_btask_sup_m);\r
- TEST_ASSERT(rv == E_OK);\r
- }\r
- rv = ActivateTask(TASK_ID_btask_sup_m);\r
- TEST_ASSERT(rv == E_OS_LIMIT);\r
- /* Let the us terminate and count the number of times the tasks\r
- * was actually activated\r
- *\r
- * TODO:@req Since the etask and btask have the same priority, who gets scheduled?\r
- * Oldest is scheduled first..\r
- * */\r
- break;\r
- case 100:\r
- TEST_ASSERT(status_100==1);\r
- status_100=2;\r
- break;\r
- default:\r
- while(1);\r
-\r
- }\r
-}\r
-\r
-DECLARE_TEST_ETASK(01, etask_sup_l_01, NULL, NULL );\r
-DECLARE_TEST_BTASK(01, btask_sup_l_01, btask_sup_m_01, btask_sup_h_01);\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tests:\r
- *\r
- * OSEK:\r
- * - GetResource E_OS_ID, E_OS_ACCESS\r
- * - ReleaseResource E_OS_ID, E_OS_ACCESS, E_OS_NOFUNC\r
- *\r
- * More tests here:\r
- * - GetResource(RES_SCHEDULER)\r
- * - Check the ceiling protocol\r
- * - Linked resources\r
- * - Nested allocation of the same resource is forbidden.\r
- *\r
- *\r
- * Limitations:\r
- * - Internal resources.\r
- */\r
-\r
-#include "Os.h"\r
-#include "os_test.h"\r
-#include "arc.h"\r
-#include "irq.h"\r
-\r
-\r
-static int isr2RunCnt = 0;\r
-static int taskRunCnt = 0;\r
-\r
-static void isr2( void ) {\r
- isr2RunCnt++;\r
- ActivateTask(TASK_ID_btask_sup_m);\r
-#if 0\r
- {\r
- TaskType task;\r
- GetTaskID(&task);\r
- printf("ISR2: %d\n",task);\r
- }\r
-#endif\r
-}\r
-\r
-static void isr1( void ) {\r
-\r
-}\r
-\r
-void etask_sup_l_02(void) {\r
- _Bool done = 0;\r
- StatusType rv;\r
- TaskType isrTask;\r
- TaskType task;\r
-\r
- while (!done) {\r
- TEST_RUN();\r
- switch (test_nr) {\r
- case 1:\r
- rv = GetResource(RES_ID_std_prio_3);\r
- TEST_ASSERT(rv == E_OK);\r
- rv = ReleaseResource(RES_ID_std_prio_3);\r
- TEST_ASSERT(rv == E_OK);\r
- test_nr++;\r
- break;\r
- case 2:\r
- /* Get the same resource twice */\r
- rv = GetResource(RES_ID_std_prio_3);\r
- TEST_ASSERT(rv == E_OK);\r
- rv = GetResource(RES_ID_std_prio_3);\r
- TEST_ASSERT(rv == E_OS_ACCESS);\r
- test_nr = 10;\r
- break;\r
- case 10:\r
- /* Test RES_SCHEDULER.\r
- * Since GetResource(RES_SCHEDULER) only locks the\r
- * scheduler (interrupts are still working) we the interrupt\r
- * task should trigger a higher prio task, but that should\r
- * not be swapped in.\r
- */\r
-\r
- /* Create an ISR2 */\r
- isrTask = Os_Arc_CreateIsr( isr2, 4/*prio*/,"soft_0");\r
- Irq_AttachIsr2(isrTask,NULL,INTC_SSCIR0_CLR0);\r
- /* Create an ISR1 */\r
- Irq_AttachIsr1(isr1,NULL,INTC_SSCIR0_CLR1,6);\r
-\r
- GetTaskID(&task);\r
- TEST_ASSERT( task == TASK_ID_etask_sup_l );\r
- /* Lock the scheduler */\r
- rv = GetResource(RES_SCHEDULER);\r
- Irq_GenerateSoftInt( INTC_SSCIR0_CLR0 );\r
-\r
- GetTaskID(&task);\r
-\r
- TEST_ASSERT( task == TASK_ID_etask_sup_l );\r
-\r
- /* TODO: Should we re-schedule here? */\r
- rv = ReleaseResource(RES_SCHEDULER);\r
- // TODO: ReleaseResource should re-schedule\r
-\r
- TEST_ASSERT( task == TASK_ID_etask_sup_l );\r
-\r
-// TEST_ASSERT( taskRunCnt == 1 );\r
- // TODO:\r
-\r
- test_nr = 100;\r
- break;\r
- case 100:\r
- TerminateTask();\r
- break;\r
- }\r
- }\r
-}\r
-\r
-void btask_sup_l_02(void) {\r
-}\r
-\r
-void btask_sup_m_02(void) {\r
- TaskType task;\r
- GetTaskID(&task);\r
-\r
- taskRunCnt++;\r
- TEST_ASSERT( task == TASK_ID_btask_sup_m );\r
-}\r
-\r
-\r
-DECLARE_TEST_ETASK(02, etask_sup_l_02, NULL, NULL );\r
-DECLARE_TEST_BTASK(02, btask_sup_l_02, btask_sup_m_02, NULL );\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tests:\r
- *\r
- * OSEK\r
- * - GetAlarmBase E_OS_ID\r
- * - GetAlarm E_OS_ID, E_OS_NOFUNC\r
- * - SetRelAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE\r
- * - SetAbsAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE\r
- * - CancelAlarm E_OS_ID, E_OS_NOFUNC\r
- *\r
- * Autosar\r
- * - IncrementCounter E_OS_ID\r
- * - GetCounterValue E_OS_ID\r
- * - GetElapsedCounterValue E_OS_ID, E_OS_VALUE\r
- *\r
- * More tests here:\r
- *\r
- * Limitations:\r
- */\r
-\r
-\r
-#include "Os.h"\r
-#include "os_test.h"\r
-#include "arc.h"\r
-\r
-\r
-void etask_sup_l_03(void) {\r
- _Bool done = 0;\r
- StatusType rv;\r
- AlarmBaseType alarmBase;\r
- TickType tick;\r
- TickType tickElapsed;\r
-\r
- int i;\r
-\r
- rv = ActivateTask(TASK_ID_etask_sup_m);\r
- assert( rv == E_OK );\r
-\r
- while (!done) {\r
- TEST_RUN();\r
- switch (test_nr) {\r
- /*--------------------------------------------------------------------\r
- * API tests\r
- *--------------------------------------------------------------------\r
- */\r
- case 1:\r
- /* GetAlarmBase E_OS_ID */\r
- rv = GetAlarmBase(ALARM_ID_c_sys_activate_btask_h, &alarmBase);\r
- TEST_ASSERT(rv == E_OK);\r
- rv = GetAlarmBase(ALARM_ID_ILL, &alarmBase);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- test_nr++;\r
- break;\r
- case 2:\r
- /* GetAlarm E_OS_ID and E_OS_NO_FUNC */\r
- rv = GetAlarm(ALARM_ID_c_sys_activate_btask_h,&tick);\r
- TEST_ASSERT(rv == E_OS_NOFUNC);\r
- rv = GetAlarm(ALARM_ID_ILL,&tick);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- test_nr++;\r
- break;\r
- case 3:\r
- /* SetRelAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE */\r
- rv = SetRelAlarm(ALARM_ID_ILL,1,10);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,0,10);\r
- TEST_ASSERT(rv == E_OS_VALUE);\r
- rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
- TEST_ASSERT(rv == E_OK);\r
- rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
- TEST_ASSERT(rv == E_OS_STATE);\r
- rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
- TEST_ASSERT(rv == E_OK);\r
- test_nr++;\r
- break;\r
- case 4:\r
- /* SetAbsAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE */\r
- rv = SetAbsAlarm(ALARM_ID_ILL,1,10);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,\r
- OSMAXALLOWEDVALUE_soft_1 + 1, 10);\r
- TEST_ASSERT(rv == E_OS_VALUE);\r
- rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
- TEST_ASSERT(rv == E_OK);\r
- rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
- TEST_ASSERT(rv == E_OS_STATE);\r
- rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
- TEST_ASSERT(rv == E_OK);\r
- test_nr++;\r
- break;\r
- case 5:\r
- /* CancelAlarm E_OS_ID, E_OS_NOFUNC */\r
- rv = CancelAlarm(ALARM_ID_ILL);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
- TEST_ASSERT(rv == E_OS_NOFUNC);\r
- test_nr++;\r
- break;\r
- case 6:\r
- /* IncrementCounter E_OS_ID */\r
- rv = IncrementCounter(COUNTER_ID_ILL);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- test_nr++;\r
- break;\r
- case 7:\r
- /* GetCounterValue E_OS_ID */\r
- rv = GetCounterValue(COUNTER_ID_ILL,&tick);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- test_nr++;\r
- break;\r
- case 8:\r
- /* GetElapsedCounterValue E_OS_ID, E_OS_VALUE */\r
- rv = GetElapsedCounterValue(COUNTER_ID_ILL,&tick,&tick);\r
- TEST_ASSERT(rv == E_OS_ID);\r
- test_nr = 10;\r
- break;\r
-\r
- /*--------------------------------------------------------------------\r
- * Functional tests, Counters\r
- *--------------------------------------------------------------------\r
- * IncrementCounter\r
- * GetCounterValue\r
- * GetElapsedCounterValue\r
- */\r
- case 10:\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- TEST_ASSERT(rv == E_OK);\r
- rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
- TEST_ASSERT(rv == E_OK);\r
- TEST_ASSERT(tick == 1);\r
- rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
- &tick,\r
- &tickElapsed);\r
- TEST_ASSERT(tick == 1);\r
- TEST_ASSERT(tickElapsed == 0);\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- TEST_ASSERT(rv == E_OK);\r
- rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
- &tick,\r
- &tickElapsed);\r
- TEST_ASSERT(tick == 2);\r
- TEST_ASSERT(tickElapsed == 1);\r
-\r
- /* Test max value */\r
- for( i=0; i< OSMAXALLOWEDVALUE_soft_1 - 2; i++ ) {\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- TEST_ASSERT(rv == E_OK);\r
- }\r
-\r
- rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
- TEST_ASSERT(tick == OSMAXALLOWEDVALUE_soft_1);\r
-\r
- tick = 0;\r
- rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
- &tick,\r
- &tickElapsed);\r
-\r
- TEST_ASSERT(tick == OSMAXALLOWEDVALUE_soft_1 );\r
- TEST_ASSERT(tickElapsed == OSMAXALLOWEDVALUE_soft_1);\r
-\r
- /* Check that wrapping calculation works */\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
- &tick,\r
- &tickElapsed);\r
-\r
- TEST_ASSERT(tick == 1);\r
- TEST_ASSERT(tickElapsed == 2);\r
-\r
- test_nr++;\r
- break;\r
-\r
- /*--------------------------------------------------------------------\r
- * Functional tests, Alarm\r
- *--------------------------------------------------------------------\r
- * GetAlarmBase\r
- * GetAlarm\r
- * SetRelAlarm\r
- * SetAbsAlarm\r
- * CancelAlarm\r
- */\r
-\r
- case 11:\r
- rv = GetAlarmBase(ALARM_ID_c_soft_1_setevent_etask_m, &alarmBase);\r
- TEST_ASSERT(alarmBase.maxallowedvalue == OSMAXALLOWEDVALUE_soft_1 );\r
- /* TODO: Fix this in the editor */\r
- TEST_ASSERT(alarmBase.mincycle == 1 );\r
- TEST_ASSERT(alarmBase.tickperbase == 1 );\r
- test_nr++;\r
- break;\r
-\r
- case 12:\r
- /* Test single-shot alarm */\r
- rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,2,0);\r
- TEST_ASSERT( rv == E_OK );\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 2 );\r
-\r
- IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 1 );\r
-\r
- IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OS_NOFUNC );\r
- test_nr++;\r
- break;\r
- case 13:\r
- /* Test cyclic alarm */\r
- rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,2,5);\r
- TEST_ASSERT( rv == E_OK );\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 2 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 1 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 5 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT(tick == 4 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT(tick == 1 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- TEST_ASSERT( rv == E_OK );\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 5 );\r
-\r
- rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
- TEST_ASSERT( rv == E_OK );\r
- test_nr++;\r
- break;\r
- case 14:\r
- /*\r
- * SetAbsAlarm\r
- */\r
-\r
- /* Start from 0 */\r
- rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
- for(i=0;i<OSMAXALLOWEDVALUE_soft_1 - tick + 1 ;i++) {\r
- IncrementCounter(COUNTER_ID_soft_1);\r
- }\r
-\r
- rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
- TEST_ASSERT(tick == 0);\r
-\r
- /* Test single-shot alarm */\r
- rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,2,0);\r
- TEST_ASSERT( rv == E_OK );\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 2 );\r
-\r
- IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 1 );\r
-\r
- IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OS_NOFUNC );\r
- test_nr++;\r
- break;\r
- case 15:\r
-\r
- /* Start from 1 */\r
- rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
- for(i=0;i<OSMAXALLOWEDVALUE_soft_1 - tick + 1 ;i++) {\r
- IncrementCounter(COUNTER_ID_soft_1);\r
- }\r
- IncrementCounter(COUNTER_ID_soft_1);\r
-\r
- /* Test cyclic alarm */\r
- rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,3,5);\r
- TEST_ASSERT( rv == E_OK );\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 2 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 1 );\r
-\r
- /* Trigger the alarm */\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- /* The abs alarm is now a relative alarm cith cycle */\r
- TEST_ASSERT(tick == 5 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT(tick == 4 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT(tick == 1 );\r
-\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- TEST_ASSERT( rv == E_OK );\r
- rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(tick == 5 );\r
-\r
- rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
- TEST_ASSERT( rv == E_OK );\r
- test_nr++;\r
- break;\r
- case 16:\r
- test_nr = 100;\r
- break;\r
- case 100:\r
- SetEvent(TASK_ID_etask_sup_m, EVENT_MASK_kill);\r
- TerminateTask();\r
- break;\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_m_03(void) {\r
-\r
- for(;;) {\r
-\r
- WaitEvent(EVENT_MASK_notif | EVENT_MASK_kill );\r
- switch (test_nr) {\r
- case 12:\r
- case 13:\r
- case 14:\r
- case 15:\r
- ClearEvent(EVENT_MASK_notif);\r
- break;\r
- case 100:\r
- TerminateTask();\r
- break;\r
- default:\r
- assert(0);\r
- }\r
- }\r
-\r
-}\r
-\r
-void btask_sup_l_03(void) {\r
-}\r
-\r
-\r
-DECLARE_TEST_ETASK(03, etask_sup_l_03, etask_sup_m_03, NULL );\r
-DECLARE_TEST_BTASK(03, btask_sup_l_03, NULL, NULL );\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-/*\r
- * From Autosar 3.1\r
- *\r
- * Tests:\r
- * - StartScheduleTableRel E_OS_ID, E_OS_VALUE, E_OS_STATE\r
- * - StartScheduleTableAbs E_OS_ID, E_OS_VALUE, E_OS_STATE\r
- * - StopScheduleTable E_OS_ID, E_OS_NO_FUNC\r
- * - NextScheduleTable E_OS_ID, E_OS_NO_FUNC, E_OS_STATE\r
- * - GetScheduleTableStatus E_OS_ID,\r
- *\r
- * Class 2 and 4\r
- * - StartScheduleTableSynchrone E_OS_ID, E_OS_STATE\r
- * - SyncScheduleTable E_OS_ID, E_OS_VALUE, E_OS_STATE\r
- * - SetScheduleTableAsync E_OS_ID,\r
- *\r
- * More tests here:\r
- *\r
- * Limitations:\r
- */\r
-\r
-#include "Os.h"\r
-#include "os_test.h"\r
-#include "arc.h"\r
-\r
-\r
-static int subTest = 0;\r
-\r
-void etask_sup_l_04(void) {\r
- _Bool done = 0;\r
- StatusType rv;\r
- ScheduleTableStatusType status;\r
-\r
- while (!done) {\r
- TEST_RUN();\r
- switch (test_nr) {\r
- case 1:\r
- /* StartScheduleTableRel E_OS_ID, E_OS_VALUE, E_OS_STATE */\r
- rv = StartScheduleTableRel(SCHTBL_ID_ILL,1);\r
- TEST_ASSERT(rv==E_OS_ID);\r
- rv = StartScheduleTableRel(SCHTBL_ID_0,0);\r
- TEST_ASSERT(rv==E_OS_VALUE);\r
- rv = StartScheduleTableRel(SCHTBL_ID_0,1);\r
- TEST_ASSERT(rv==E_OK);\r
- rv = StartScheduleTableRel(SCHTBL_ID_0,1);\r
- TEST_ASSERT(rv==E_OS_STATE);\r
- rv = StopScheduleTable(SCHTBL_ID_0);\r
- test_nr++;\r
- break;\r
- case 2:\r
- /* StartScheduleTableAbs E_OS_ID, E_OS_VALUE, E_OS_STATE */\r
- rv = StartScheduleTableAbs(SCHTBL_ID_ILL,1);\r
- TEST_ASSERT(rv==E_OS_ID);\r
-#if 0\r
- /* TODO:Must supply an offset bigger than OsCounterMaxAllowedValue */\r
- StartScheduleTableAbs(SCHTBL_ID_0,0);\r
- TEST_ASSERT(rv==E_OS_VALUE);\r
-#endif\r
- rv = StartScheduleTableAbs(SCHTBL_ID_0,1);\r
- TEST_ASSERT(rv==E_OK);\r
- rv = StartScheduleTableAbs(SCHTBL_ID_0,1);\r
- TEST_ASSERT(rv==E_OS_STATE);\r
- rv = StopScheduleTable(SCHTBL_ID_0);\r
- test_nr++;\r
- break;\r
- case 3:\r
- /* StopScheduleTable E_OS_ID, E_OS_NO_FUNC */\r
- rv = StopScheduleTable(SCHTBL_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID);\r
- rv = StopScheduleTable(SCHTBL_ID_0);\r
- TEST_ASSERT(rv==E_OS_NOFUNC);\r
- test_nr++;\r
- break;\r
- case 4:\r
- /* NextScheduleTable E_OS_ID, E_OS_NO_FUNC, E_OS_STATE */\r
- rv = NextScheduleTable(SCHTBL_ID_ILL, SCHTBL_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID);\r
- rv = NextScheduleTable(SCHTBL_ID_ILL, SCHTBL_ID_0);\r
- TEST_ASSERT(rv==E_OS_ID);\r
- rv = NextScheduleTable(SCHTBL_ID_0, SCHTBL_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID);\r
-\r
- rv = NextScheduleTable(SCHTBL_ID_0,SCHTBL_ID_0);\r
- TEST_ASSERT(rv==E_OS_NOFUNC);\r
-\r
- rv = StartScheduleTableRel(SCHTBL_ID_0,1);\r
- rv = StartScheduleTableRel(SCHTBL_ID_1,1);\r
- rv = NextScheduleTable(SCHTBL_ID_0,SCHTBL_ID_1);\r
- TEST_ASSERT(rv==E_OS_STATE);\r
-\r
- /* Cleanup */\r
- rv = StopScheduleTable(SCHTBL_ID_0);\r
- TEST_ASSERT(rv==E_OK);\r
- rv = StopScheduleTable(SCHTBL_ID_1);\r
- TEST_ASSERT(rv==E_OK);\r
- test_nr = 10;\r
- break;\r
- /*--------------------------------------------------------------------\r
- * Functional tests, ScheduleTables\r
- *--------------------------------------------------------------------\r
- * - StartScheduleTableRel\r
- * - StartScheduleTableAbs\r
- * - StopScheduleTable\r
- * - NextScheduleTable\r
- * - GetScheduleTableStatus\r
- */\r
- case 10:\r
- subTest = 0;\r
- rv = ActivateTask(TASK_ID_etask_sup_m);\r
- TEST_ASSERT( rv == E_OK );\r
-\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
- rv = StartScheduleTableRel(SCHTBL_ID_0,2);\r
- TEST_ASSERT(rv==E_OK);\r
-\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
-\r
- /* 2+ 5 */\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- subTest = 5;\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
-\r
- /* 2 more for next*/\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- subTest = 7;\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
-\r
- /* 4 more for next*/\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- subTest = 11;\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
-\r
- /* and the final offset */\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
-\r
- /* First offset, again. */\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
-\r
- /* TODO: More here */\r
-\r
- test_nr = 100;\r
- break;\r
-\r
-\r
-#if 0 /* Working single shot case */\r
- case 10:\r
- subTest = 0;\r
- rv = ActivateTask(TASK_ID_etask_sup_m);\r
- TEST_ASSERT( rv == E_OK );\r
-\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
- rv = StartScheduleTableRel(SCHTBL_ID_0,2);\r
- TEST_ASSERT(rv==E_OK);\r
-\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
-\r
- /* 2+ 5 */\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- subTest = 5;\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
-\r
- /* 2 more for next*/\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- subTest = 7;\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
-\r
- /* 4 more for next*/\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- subTest = 11;\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
-\r
- /* and the final offset */\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = IncrementCounter(COUNTER_ID_soft_1);\r
- rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(rv==E_OK);\r
- TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
- test_nr = 100;\r
-\r
- break;\r
-#endif\r
-\r
-\r
- case 100:\r
- rv = SetEvent(TASK_ID_etask_sup_m, EVENT_MASK_kill);\r
- TEST_ASSERT( rv == E_OK );\r
- TerminateTask();\r
- break;\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_m_04(void) {\r
-\r
- TaskType currTask;\r
- EventMaskType eventMask;\r
- GetTaskID(&currTask);\r
- StatusType rv;\r
-\r
- for(;;) {\r
- WaitEvent(EVENT_MASK_notif | EVENT_MASK_kill );\r
- switch(test_nr) {\r
- case 10:\r
- switch(subTest) {\r
- case 7:\r
- case 11:\r
- printf("etask\n");\r
- rv = GetEvent(currTask,&eventMask);\r
- TEST_ASSERT( rv == E_OK );\r
- TEST_ASSERT(eventMask == EVENT_MASK_notif );\r
- ClearEvent(EVENT_MASK_notif);\r
- break;\r
-\r
- default:\r
- TEST_ASSERT(0);\r
- break;\r
-\r
- }\r
- break;\r
- case 100:\r
- rv = TerminateTask();\r
- TEST_ASSERT( rv == E_OK );\r
- break;\r
-\r
- default:\r
- TEST_ASSERT(0);\r
- break;\r
- }\r
- }\r
-}\r
-\r
-\r
-void btask_sup_l_04(void) {\r
-\r
-\r
-\r
-}\r
-\r
-void btask_sup_m_04(void) {\r
-\r
- switch(test_nr) {\r
- case 10:\r
- switch(subTest) {\r
- case 5:\r
- case 11:\r
- printf("btask\n");\r
- break;\r
-\r
- default:\r
- TEST_ASSERT(0);\r
- break;\r
- }\r
-\r
- break;\r
- }\r
-\r
-}\r
-\r
-\r
-DECLARE_TEST_ETASK(04, etask_sup_l_04, etask_sup_m_04, NULL );\r
-DECLARE_TEST_BTASK(04, btask_sup_l_04, btask_sup_m_04, NULL );\r
-\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tests:\r
- *\r
- * OSEK\r
- * - DisableAllInterrupts\r
- * - EnableAllInterrupts\r
- * - SuspendAllInterrupts\r
- * - ResumeAllInterrupts\r
- * - SuspendOSInterrupts\r
- * - ResumeOSInterrupts\r
- *\r
- * - GetActiveApplicationMode\r
- * - StartOS\r
- * - ShutdownOS\r
- *\r
- *\r
- * Autosar\r
- *\r
- * Class 3 and 4\r
- * - GetApplicationID\r
- * - GetISRID IVALID_ISR\r
- * - CallTrustedFunction ...\r
- * - CheckISRMemoryAccess ...\r
- * - CheckTaskMemoryAccess\r
- * - CheckObjectMemoryAccess\r
- * - CheckObjectOwnership\r
- * - TerminateApplication\r
- *\r
- * Autosar additional tests:\r
- *\r
- * Class 2,3,4\r
- * - ProtectionHook\r
- *\r
- * Class 2,4\r
- * - Timing Protection\r
- * - Global Time\r
- *\r
- * Class 3,4\r
- * - Memory Protection\r
- * - Os-Applications\r
- * - Service Protection\r
- * - Call trusted function\r
- *\r
- * Limitations:\r
- */\r
-\r
-void intTest( void ) {\r
-\r
- /* Just call them to its works */\r
- DisableAllInterrupts();\r
- EnableAllInterrupts();\r
-\r
- SuspendAllInterrupts();\r
- ResumeAllInterrupts();\r
-\r
- SuspendOSInterrupts();\r
- ResumeOSInterrupts();\r
-\r
- /** @req OS092 */\r
- /* We should be able to call them and they should be ignored */\r
- EnableAllInterrupts();\r
- EnableAllInterrupts();\r
-\r
- ResumeAllInterrupts();\r
- ResumeAllInterrupts();\r
-\r
- ResumeOSInterrupts();\r
- ResumeOSInterrupts();\r
-\r
- /* No nesting for DisableAllInterrupts() and EnableAllInterrupts */\r
- DisableAllInterrupts();\r
- /* No calls allowed here */\r
- EnableAllInterrupts();\r
-\r
- /* Nesting allowed for these calls */\r
- SuspendAllInterrupts();\r
- SuspendAllInterrupts();\r
- SuspendOSInterrupts();\r
- ResumeOSInterrupts();\r
- ResumeAllInterrupts();\r
- ResumeAllInterrupts();\r
-\r
- /* MORE MORE */\r
-\r
-}\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#include <stdint.h>\r
-#include <stdio.h>\r
-#include "Platform_Types.h"\r
-\r
-int test_suite = 1;\r
-int test_nr = 1;\r
-int _test_ok = 0;\r
-int _test_failed = 0;\r
-\r
-int testCnt = 0;\r
-struct test {\r
- uint8_t testSuite;\r
- uint8_t testNr;\r
- uint16_t status;\r
-};\r
-\r
-struct test testTable[50] = { {0} };\r
-\r
-\r
-void test_done( void ) {\r
- printf( "\nTest summary\n"\r
- "Total: %d\n"\r
- "OK : %d\n"\r
- "FAIL : %d\n", _test_ok + _test_failed, _test_ok, _test_failed);\r
-\r
-}\r
-\r
-void test_fail( const char *text,char *file, int line, const char *function ) {\r
- printf("%02d %02d FAILED, %s , %d, %s\n",test_suite, test_nr, file, line, function);\r
- testTable[testCnt].testSuite = test_suite;\r
- testTable[testCnt].testNr = test_nr;\r
- testTable[testCnt].status = 0;\r
- testCnt++;\r
- _test_failed++;\r
-}\r
-\r
-\r
-void test_ok( void ) {\r
- printf("%02d %02d OK\n",test_suite, test_nr);\r
- testTable[testCnt].testSuite = test_suite;\r
- testTable[testCnt].testNr = test_nr;\r
- testTable[testCnt].status = 1;\r
- testCnt++;\r
- _test_ok++;\r
-}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/* CONFIGURATION\r
- * - The "etask_master" should be the only autostarted task.\r
- * - It can hold at most 3 extended task and 3 basic tasks. They must be called\r
- * etask_sup_l, etask_sup_m, etask_sup_h,\r
- * btask_sup_l, btask_sup_m, btask_sup_h\r
- */\r
-\r
-\r
-\r
-\r
-\r
-#include <stdlib.h>\r
-#include "Os.h"\r
-#include "os_test.h"\r
-#include "Mcu.h"\r
-#if defined(USE_GPT)\r
-#include "Gpt.h"\r
-#endif\r
-\r
-\r
-//#define USE_LDEBUG_PRINTF\r
-#include "debug.h"\r
-#include "arc.h"\r
-\r
-\r
-typedef struct {\r
- uint32 nr;\r
- uint32 sub_nr;\r
- uint32 failed;\r
-} test_master_cfg_t;\r
-\r
-TaskType test_activate_pid_list[] =\r
-{\r
-/* 01*/ TASK_ID_etask_sup_l,\r
-/* 02*/ TASK_ID_etask_sup_l,\r
-/* 03*/ TASK_ID_etask_sup_l,\r
-/* 04*/ TASK_ID_etask_sup_l,\r
-};\r
-\r
-static int test_case = 0;\r
-\r
-/*\r
- * Master test process, everything is controlled from here.\r
- */\r
-void etask_master( void ) {\r
- TaskType pid;\r
-\r
- for( ; test_case < sizeof(test_activate_pid_list)/sizeof(TaskType); test_case++)\r
- {\r
- test_nr = 1;\r
- printf("-----> Test Suite %02d\n",test_suite);\r
- pid = test_activate_pid_list[test_case];\r
- ActivateTask(pid);\r
- /* We are lowest prio task in the system (apart from idle) so\r
- * all tasks in the test are now terminated...\r
- */\r
- test_suite++;\r
- }\r
-\r
- test_done();\r
-\r
- // Test complete..\r
- while(1);\r
-\r
-}\r
-\r
-extern test_func_t etask_sup_matrix[][3];\r
-extern test_func_t btask_sup_matrix[][3];\r
-\r
-//--------------------------------------------------------------------\r
-//--------------------------------------------------------------------\r
-\r
-void etask_sup_l( void )\r
-{\r
- test_func_t func;\r
- func = etask_sup_matrix[test_case][0];\r
- if( func != NULL )\r
- func();\r
-\r
- TerminateTask();\r
-}\r
-\r
-void etask_sup_m( void )\r
-{\r
- test_func_t func;\r
- func = etask_sup_matrix[test_case][1];\r
- if( func != NULL )\r
- func();\r
-\r
- TerminateTask();\r
-}\r
-\r
-void etask_sup_h( void )\r
-{\r
- test_func_t func;\r
- func = etask_sup_matrix[test_case][2];\r
- if( func != NULL )\r
- func();\r
-\r
- TerminateTask();\r
-}\r
-\r
-//--------------------------------------------------------------------\r
-//--------------------------------------------------------------------\r
-\r
-void btask_sup_l( void ) {\r
- test_func_t func;\r
- func = btask_sup_matrix[test_case][0];\r
- if( func != NULL )\r
- func();\r
-}\r
-void btask_sup_m( void ) {\r
- test_func_t func;\r
- func = btask_sup_matrix[test_case][1];\r
- if( func != NULL )\r
- func();\r
-}\r
-void btask_sup_h( void ) {\r
- test_func_t func;\r
- func = btask_sup_matrix[test_case][2];\r
- if( func != NULL )\r
- func();\r
-}\r
-\r
-\r
-void OsIdle(void ) {\r
- for(;;);\r
-}\r
-\r
-\r
-/* Global hooks */\r
-ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
- printf("## ProtectionHook\n");\r
- return PRO_KILLAPPL;\r
-}\r
-\r
-void StartupHook( void ) {\r
-// LDEBUG_PRINTF("## StartupHook\n");\r
-\r
-#ifdef USE_MCU\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
- (void)sys_freq;\r
- LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
-#endif\r
-}\r
-\r
-void ShutdownHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ShutdownHook\n");\r
- const char *err;\r
- err = Arc_StatusToString(Error);\r
- while(1) {\r
- err = err;\r
- }\r
-}\r
-\r
-void ErrorHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);\r
- const char *err;\r
- err = Arc_StatusToString(Error);\r
-// while(1);\r
-}\r
-\r
-void PreTaskHook( void ) {\r
- TaskType task;\r
- GetTaskID(&task);\r
- if( task > 10 ) {\r
- while(1);\r
- }\r
- LDEBUG_PRINTF("## PreTaskHook, taskid=%d\n",task);\r
-}\r
-\r
-void PostTaskHook( void ) {\r
- TaskType task;\r
- GetTaskID(&task);\r
- if( task > 10 ) {\r
- while(1);\r
- }\r
-\r
- LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
-#if 0\r
- {\r
- StackInfoType si;\r
- Os_Arc_GetStackInfo(task,&si);\r
-// LDEBUG_PRINTF("Stack usage %d%% (this=%08x, top=%08x, size=%08x,usage=%08x )\n",OS_STACK_USAGE(&si),si.curr, si.top,si.size,si.usage);\r
- }\r
-#endif\r
-}\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tested: Tasks\r
- */\r
-\r
-//#include "Platform_Types.h"\r
-#include "Os.h"\r
-#include "debug.h"\r
-#include "os_test.h"\r
-//#include "test_cfg.h"\r
-\r
-#define EVENT_NR 1\r
-#define TASK_1 1\r
-#define TASK_2 2\r
-\r
-#define E_TEST_OUT_OF_SYNC 100\r
-\r
-\r
-//#define EVENT_1 1\r
-//#define EVENT_2 2\r
-\r
-DeclareResource(RES_1);\r
-\r
-//static int test = 1;\r
-\r
-#define TASK_ID_ILL 99\r
-#define RES_ID_ILL 99\r
-#define ALARM_ID_ILL 99\r
-\r
-static void taskApiTests( void ) {\r
- StatusType rv;\r
- TaskStateType taskState;\r
- EventMaskType eventMask;\r
- AlarmBaseType alarmInfo;\r
- TickType tick;\r
-\r
- /*@req E_OS_ID */\r
- rv = ActivateTask(TASK_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID );\r
- rv = ChainTask(TASK_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID );\r
-\r
- rv = GetTaskState(TASK_ID_ILL,&taskState);\r
- TEST_ASSERT(rv==E_OS_ID );\r
-\r
- rv = GetResource(RES_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID );\r
- rv = ReleaseResource(RES_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID );\r
-\r
- rv = SetEvent(TASK_ID_ILL,1);\r
- TEST_ASSERT(rv==E_OS_ID );\r
- rv = GetEvent(TASK_ID_ILL,&eventMask);\r
- TEST_ASSERT(rv==E_OS_ID );\r
-\r
- rv = GetAlarmBase(ALARM_ID_ILL,&alarmInfo);\r
- TEST_ASSERT(rv==E_OS_ID );\r
- rv = GetAlarm(ALARM_ID_ILL,&tick);\r
- TEST_ASSERT(rv==E_OS_ID );\r
- rv = SetRelAlarm(ALARM_ID_ILL,1,2);\r
- TEST_ASSERT(rv==E_OS_ID );\r
- rv = SetAbsAlarm(ALARM_ID_ILL,1,2);\r
- TEST_ASSERT(rv==E_OS_ID );\r
- rv = CancelAlarm(ALARM_ID_ILL);\r
- TEST_ASSERT(rv==E_OS_ID );\r
-}\r
-\r
-void etask_sup_l_01( void ){\r
-\r
- _Bool done = 0;\r
-\r
- while(!done) {\r
- switch( test_nr ) {\r
- case 1:\r
- /*@req OSEK_TASK_1 */\r
- ActivateTask(TASK_ID_etask_sup_m);\r
- /* Switch to higher prio */\r
- Schedule();\r
- break;\r
- case 4:\r
- // From WaitEvent() in sup_m\r
- TEST_OK();\r
- ++test_nr;\r
- ClearEvent(EVENT_1);\r
- // trigger sup_m to ready state(since it's waiting for the event)\r
- SetEvent(TASK_ID_etask_sup_m,EVENT_1);\r
- // Let SUP_M take the event\r
-#warning Something is very wrong here...\r
- WaitEvent(EVENT_1);\r
- break;\r
- case 7:\r
- // We get scheduled again from sup_m\r
- TEST_OK();\r
- test_nr = 100;\r
- break;\r
-\r
- case 100:\r
- SetEvent(TASK_ID_etask_sup_m,EVENT_1);\r
- // Let SUP_M finish...\r
- // Schedule();\r
- // The test case is done! Kill ourselves\r
- TerminateTask();\r
-// done = 1;\r
- break;\r
- default:\r
- TEST_FAIL("default in switch\n");\r
-// ErrorHook(E_TEST_OUT_OF_SYNC);\r
- break;\r
- }\r
- }\r
- // Cleanup\r
-\r
-\r
-}\r
-\r
-void etask_sup_m_01( void ){\r
- _Bool done = 0;\r
-\r
- while( !done ) {\r
- switch( test_nr ) {\r
- case 1:\r
- TEST_OK();\r
- ++test_nr;\r
- break;\r
- case 2:\r
- Schedule();\r
- // We should stay here\r
- TEST_OK();\r
- ++test_nr;\r
- break;\r
- case 3:\r
- SetEvent(TASK_ID_etask_sup_l,EVENT_1);\r
- // We should stay here since we are higher prio\r
- TEST_OK();\r
- ++test_nr;\r
- break;\r
- case 4:\r
- // No event waiting so this should trigger sup_l\r
- WaitEvent(EVENT_1);\r
- break;\r
- case 5:\r
- SetEvent(TASK_ID_etask_sup_l,EVENT_1);\r
- TEST_OK();\r
- ++test_nr;\r
- break;\r
- case 6:\r
- // The event isn't cleared yet, so we should return right away\r
- WaitEvent(EVENT_1);\r
- TEST_OK();\r
- ++test_nr;\r
- break;\r
- case 7:\r
- ClearEvent(EVENT_1);\r
- // Switch to sup_l\r
- WaitEvent(EVENT_1);\r
- break;\r
- case 100:\r
- TerminateTask();\r
-\r
-#if 0\r
- ClearEvent(1);\r
- done = 1;\r
-#endif\r
- break;\r
- default:\r
- TEST_FAIL("default in switch");\r
- ErrorHook(E_TEST_OUT_OF_SYNC);\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_h_01( void ){\r
-\r
-}\r
-\r
-#if 0\r
-void test_sup_master( void ) {\r
-\r
- for(;;) {\r
- os_printf("test1_1,msr=%x\n",get_msr());\r
-\r
- GetResource(RES_1);\r
- ReleaseResource(RES_1);\r
- SetEvent(TASK_2,EVENT_NR);\r
- WaitEvent(EVENT_NR);\r
- ClearEvent(EVENT_NR);\r
- }\r
-}\r
-\r
-void test1_2( void ) {\r
- for(;;) {\r
- os_printf("test1_2,msr=%x\n",get_msr());\r
- WaitEvent(EVENT_NR);\r
- ClearEvent(EVENT_NR);\r
- SetEvent(TASK_1,EVENT_NR);\r
- }\r
-}\r
-#endif\r
-\r
-#if 0\r
-void idle_proc( void )\r
-{\r
- for(;;) {}\r
-}\r
-#endif\r
-\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tested: alarms and events\r
- *\r
- * COUNTER_ID_soft_1 drives alarms:\r
- * ALARM_ID_c_soft_1_setevent_etask_m\r
- * ALARM_ID_c_soft_1_inc_counter_2\r
- */\r
-\r
-#include "Os.h"\r
-#include "debug.h"\r
-#include <assert.h>\r
-#include "os_test.h"\r
-\r
-\r
-void etask_sup_l_02( void ) {\r
-\r
- for(;;) {\r
- switch(test_nr){\r
- case 1:\r
- ChainTask(TASK_ID_btask_sup_l);\r
- break;\r
- case 2:\r
- /*\r
- * Check GetAlarmBase()\r
- */\r
- TEST_OK();\r
- {\r
- AlarmBaseType alarm;\r
- TickType tick;\r
- GetAlarmBase(ALARM_ID_c_soft_1_setevent_etask_m,&alarm);\r
- LDEBUG_PRINTF("Alarm %d,%d,%d\n", alarm.maxallowedvalue,\r
- alarm.tickperbase,\r
- alarm.mincycle);\r
-\r
- /* Get ticks before alarm expires */\r
- GetAlarm(TASK_ID_btask_sup_l,&tick);\r
- test_nr = 3;\r
- break;\r
- }\r
- case 3:\r
- // Make cyclic alarm\r
- SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m, 2, 5);\r
- // Let sup_m wait for the event.\r
- ActivateTask(TASK_ID_etask_sup_m);\r
- IncrementCounter(COUNTER_ID_soft_1); // 1\r
- IncrementCounter(COUNTER_ID_soft_1); // 2\r
- // Should trigger trigger after here, since higher prio it should swap\r
- break;\r
- case 4:\r
- IncrementCounter(COUNTER_ID_soft_1); // 3\r
- IncrementCounter(COUNTER_ID_soft_1); // 4\r
- IncrementCounter(COUNTER_ID_soft_1); // 5\r
- IncrementCounter(COUNTER_ID_soft_1); // 1\r
- Schedule();\r
- IncrementCounter(COUNTER_ID_soft_1); // 2\r
- Schedule();\r
- CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m );\r
- test_nr = 100;\r
- break;\r
- case 100:\r
- TerminateTask();\r
- break;\r
- default:\r
- assert(0);\r
- while(1);\r
- }\r
- }\r
-//SetAbsAlarm(TASK_ID_btask_sup_l,1000,0);\r
-\r
- while(1);\r
-}\r
-\r
-void etask_sup_m_02( void ) {\r
- while(1) {\r
- switch(test_nr) {\r
- case 3:\r
- WaitEvent(EVENT_1);\r
- ClearEvent(EVENT_1);\r
- TEST_OK();\r
- test_nr = 4;\r
- break;\r
- case 4:\r
- // Back to SUP_L\r
- WaitEvent(EVENT_1);\r
- TEST_OK();\r
- test_nr++;\r
- TerminateTask();\r
- break;\r
- default:\r
- assert(0);\r
- while(1);\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_h_02( void ) {\r
- while(1);\r
-}\r
-\r
-\r
-#if 0\r
-void test_sup_m_02( void ) {\r
- switch(test){\r
- case 1:\r
- TEST_OK();\r
- test_nr++;\r
- ChainTask(SUP_L_BASIC);\r
- break;\r
- case 3:\r
- TEST_OK();\r
- default:\r
- break;\r
- }\r
-}\r
-#endif\r
-\r
-void btest_sup_l_02( void ) {\r
- switch(test_nr){\r
- case 1:\r
- TEST_OK();\r
- test_nr++;\r
- ChainTask(TASK_ID_etask_sup_l);\r
- break;\r
- default:\r
- while(1);\r
- }\r
-\r
-}\r
-\r
-void btest_sup_m_02( void ) {\r
-}\r
-\r
-void btest_sup_h_02( void ) {\r
-}\r
-\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-/*\r
- * Tested: scheduletables\r
- */\r
-\r
-#include "Os.h"\r
-#include "debug.h"\r
-//#include <stdio.h>\r
-#include <assert.h>\r
-#include "os_test.h"\r
-\r
-\r
-//static int test = 1;\r
-\r
-/*\r
- * Table 0: period 10\r
- * 5 - Activate task sup_m\r
- * 7 - Setevent, EVENT_2 in sup_m\r
- *\r
- * Table 1: period 5\r
- * 2 - activate task_sup_m\r
- */\r
-\r
-void etask_sup_l_03( void ) {\r
- ScheduleTableStatusType status;\r
- test_nr = 1;\r
- for(;;) {\r
- switch(test_nr){\r
-\r
- case 1:\r
-\r
- GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_STOPPED);\r
-\r
- // Start a schedule with expire points at 2 and 5\r
- StartScheduleTableRel(SCHTBL_ID_0,SCHEDULETABLE_DURATION_1*2/10);\r
- GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_RUNNING);\r
-\r
- IncrementCounter(COUNTER_ID_soft_2);\r
- // This one should trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M\r
- IncrementCounter(COUNTER_ID_soft_2);\r
-\r
- TEST_ASSERT(test_nr==2);\r
- break;\r
-\r
- case 2:\r
- // test 02 ===============================================\r
- // back from trigger, go to next expire point (5 more)\r
- IncrementCounter(COUNTER_ID_soft_2); // 3\r
- IncrementCounter(COUNTER_ID_soft_2);\r
- IncrementCounter(COUNTER_ID_soft_2);\r
- IncrementCounter(COUNTER_ID_soft_2); // 6\r
- // Trigger the SCHEDULE_ACTION_SETEVENT, TASK_SUP_M\r
- IncrementCounter(COUNTER_ID_soft_2); // 7\r
- // Schedule to check if the is an event in TASK_SUP_M queue\r
- Schedule();\r
-\r
- TEST_ASSERT(test_nr==3);\r
-\r
- break;\r
- case 3:\r
-\r
- // test 03 ===============================================\r
- // back from trigger, period is 10 so another 2 should start all over again.\r
- IncrementCounter(COUNTER_ID_soft_2); // 8\r
- IncrementCounter(COUNTER_ID_soft_2); // 9\r
- IncrementCounter(COUNTER_ID_soft_2); // 10\r
-\r
- // Trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M\r
- Schedule();\r
-\r
- TEST_ASSERT(test_nr==4);\r
-\r
- case 4:\r
-\r
- // Go with the next schedule table, while 0 is running\r
- // (The current table must complete first)\r
- NextScheduleTable(SCHTBL_ID_0, SCHTBL_ID_1);\r
-\r
- GetScheduleTableStatus(SCHTBL_ID_1,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_NEXT);\r
-\r
- IncrementCounter(COUNTER_ID_soft_2); // 1\r
- IncrementCounter(COUNTER_ID_soft_2); // 2\r
- IncrementCounter(COUNTER_ID_soft_2); // 3\r
- IncrementCounter(COUNTER_ID_soft_2); // 4\r
- IncrementCounter(COUNTER_ID_soft_2); // 5, ActivateTask\r
-\r
- IncrementCounter(COUNTER_ID_soft_2); // 6\r
- IncrementCounter(COUNTER_ID_soft_2); // 7, SetEvent\r
- IncrementCounter(COUNTER_ID_soft_2); // 8\r
- IncrementCounter(COUNTER_ID_soft_2); // 9\r
- IncrementCounter(COUNTER_ID_soft_2); // 10\r
-\r
- GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_STOPPED);\r
- GetScheduleTableStatus(SCHTBL_ID_1,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_RUNNING);\r
-\r
- IncrementCounter(COUNTER_ID_soft_2); // 0 On table 1\r
-\r
-\r
-// StartScheduleTableRel(SCHTBL_ID_0,SCHEDULETABLE_DURATION_1*3/10);\r
-\r
- // Done\r
- break;\r
- default:\r
- assert(0);\r
- while(1);\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_m_03( void ) {\r
- for(;;) {\r
- switch(test_nr) {\r
- case 1:\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 2:\r
- // back to TASK_SUP_L\r
- WaitEvent(EVENT_2);\r
- TEST_OK()\r
- test_nr++;\r
- break;\r
- case 3:\r
- // we have started again\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 4:\r
- break;\r
- default:\r
- assert(0);\r
- break;\r
- }\r
- }\r
-}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tested: Resources\r
- *\r
- * Calls: GetResource()\r
- * ReleaseResource()\r
- * Schedule()\r
- *\r
- */\r
-\r
-#include "Os.h"\r
-#include "debug.h"\r
-//#include <stdio.h>\r
-#include <assert.h>\r
-#include "os_test.h"\r
-#include "irq.h"\r
-\r
-#if 0\r
-void isr_l(void ) {\r
- switch(test_nr) {\r
- case 2:\r
- TEST_OK();\r
- test_nr++;\r
- case 5:\r
- test_nr++;\r
- /* Trigger higher prio interrupt */\r
- Irq_GenerateSoftInt(EXTI1_IRQn);\r
- TEST_ASSERT(test_nr==8);\r
- break;\r
- default:\r
- assert(0);\r
- }\r
-}\r
-\r
-void isr_m(void ) {\r
- switch(test_nr) {\r
- case 3:\r
- TEST_OK();\r
- test_nr++;\r
- case 6:\r
- test_nr++;\r
- /* Trigger higher prio interrupt */\r
- Irq_GenerateSoftInt(EXTI2_IRQn);\r
- TEST_ASSERT(test_nr==7);\r
- test_nr++;\r
- break;\r
- default:\r
- assert(0);\r
- }\r
-\r
-}\r
-#endif\r
-\r
-\r
-void etask_sup_l_04( void ) {\r
- test_nr = 1;\r
- TaskType isr1;\r
- TaskType isr2;\r
- TaskType isr3;\r
-\r
- for(;;) {\r
- switch(test_nr){\r
- case 1:\r
- // test 01 ===============================================\r
- // Test: Grab and release the one and only standard resource.\r
- GetResource(RES_SCHEDULER);\r
- ReleaseResource(RES_SCHEDULER);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
-\r
- case 2:\r
- // test 02 ===============================================\r
- // Test: Grab resource twice. Should result in E_OS_ACCESS\r
- GetResource(RES_SCHEDULER);\r
- GetResource(RES_SCHEDULER);\r
- ReleaseResource(RES_SCHEDULER);\r
- // ??\r
- TEST_OK();\r
- test_nr++;\r
-\r
- break;\r
- case 3:\r
- // test 03 ===============================================\r
- // Test: Check that the scheduler is locked when doing this.\r
- // SetEvent() on higher prio process.\r
- GetResource(RES_SCHEDULER);\r
- // TODO:\r
- ReleaseResource(RES_SCHEDULER);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 4:\r
- // test 04 ===============================================\r
- // Test: Check that priority inversion works.\r
- // Allocate resource and check priority.\r
- GetResource(RES_ID_ext_prio_3);\r
- ReleaseResource(RES_ID_ext_prio_3);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 5:\r
- // test 05 ===============================================\r
- // Test: Attempt to get a resource which the statically assigned\r
- // priority of the calling task or interrupt routine is\r
- // higher than the calculated ceiling priority, E_OS_ACCESS\r
- TEST_ASSERT(test_nr==5);\r
- break;\r
- case 6:\r
- // test 06 ===============================================\r
- // Test: Nest resources\r
- GetResource(RES_ID_ext_prio_3);\r
- GetResource(RES_ID_ext_prio_4);\r
- ReleaseResource(RES_ID_ext_prio_4);\r
- ReleaseResource(RES_ID_ext_prio_3);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 100:\r
- TerminateTask();\r
- default:\r
- assert(0);\r
- while(1);\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_m_04( void ) {\r
- switch(test_nr){\r
- case 1:\r
- TEST_OK();\r
- test_nr++;\r
- ChainTask(TASK_ID_etask_sup_l);\r
- break;\r
- default:\r
- while(1);\r
- }\r
-\r
-}\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tested: Resources\r
- *\r
- * Calls: GetResource()\r
- * ReleaseResource()\r
- * Schedule()\r
- *\r
- */\r
-\r
-#include "Os.h"\r
-#include "debug.h"\r
-//#include <stdio.h>\r
-#include <assert.h>\r
-#include "os_test.h"\r
-#include "irq.h"\r
-\r
-#if 0\r
-void isr_l(void ) {\r
- switch(test_nr) {\r
- case 2:\r
- TEST_OK();\r
- test_nr++;\r
- case 5:\r
- test_nr++;\r
- /* Trigger higher prio interrupt */\r
- Irq_GenerateSoftInt(EXTI1_IRQn);\r
- TEST_ASSERT(test_nr==8);\r
- break;\r
- default:\r
- assert(0);\r
- }\r
-}\r
-\r
-void isr_m(void ) {\r
- switch(test_nr) {\r
- case 3:\r
- TEST_OK();\r
- test_nr++;\r
- case 6:\r
- test_nr++;\r
- /* Trigger higher prio interrupt */\r
- Irq_GenerateSoftInt(EXTI2_IRQn);\r
- TEST_ASSERT(test_nr==7);\r
- test_nr++;\r
- break;\r
- default:\r
- assert(0);\r
- }\r
-\r
-}\r
-#endif\r
-\r
-\r
-void etask_sup_l_04( void ) {\r
- test_nr = 1;\r
- TaskType isr1;\r
- TaskType isr2;\r
- TaskType isr3;\r
-\r
- for(;;) {\r
- switch(test_nr){\r
- case 1:\r
- // test 01 ===============================================\r
- // Test: Grab and release the one and only standard resource.\r
- GetResource(RES_SCHEDULER);\r
- ReleaseResource(RES_SCHEDULER);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
-\r
- case 2:\r
- // test 02 ===============================================\r
- // Test: Grab resource twice. Should result in E_OS_ACCESS\r
- GetResource(RES_SCHEDULER);\r
- GetResource(RES_SCHEDULER);\r
- ReleaseResource(RES_SCHEDULER);\r
- // ??\r
- TEST_OK();\r
- test_nr++;\r
-\r
- break;\r
- case 3:\r
- // test 03 ===============================================\r
- // Test: Check that the scheduler is locked when doing this.\r
- // SetEvent() on higher prio process.\r
- GetResource(RES_SCHEDULER);\r
- // TODO:\r
- ReleaseResource(RES_SCHEDULER);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 4:\r
- // test 04 ===============================================\r
- // Test: Check that priority inversion works.\r
- // Allocate resource and check priority.\r
- GetResource(RES_ID_ext_prio_3);\r
- ReleaseResource(RES_ID_ext_prio_3);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 5:\r
- // test 05 ===============================================\r
- // Test: Attempt to get a resource which the statically assigned\r
- // priority of the calling task or interrupt routine is\r
- // higher than the calculated ceiling priority, E_OS_ACCESS\r
- TEST_ASSERT(test_nr==5);\r
- break;\r
- case 6:\r
- // test 06 ===============================================\r
- // Test: Nest resources\r
- GetResource(RES_ID_ext_prio_3);\r
- GetResource(RES_ID_ext_prio_4);\r
- ReleaseResource(RES_ID_ext_prio_4);\r
- ReleaseResource(RES_ID_ext_prio_3);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 100:\r
- TerminateTask();\r
- default:\r
- assert(0);\r
- while(1);\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_m_04( void ) {\r
- switch(test_nr){\r
- case 1:\r
- TEST_OK();\r
- test_nr++;\r
- ChainTask(TASK_ID_etask_sup_l);\r
- break;\r
- default:\r
- while(1);\r
- }\r
-\r
-}\r
-\r
-/* In the OS you can queue activations for a task.\r
- * Example: Two tasks, main with prio 2 and slave with prio 1,activate 2.\r
- */\r
-\r
-void ActivationQueue(void) {\r
- {\r
- StatusType rv;\r
- /* Queue up */\r
- for(int i=0;i<2;i++) {\r
- rv=ActivateTask(slave);\r
- assert(rv==E_OK);\r
- }\r
-\r
- /* Try to queue up more....that will not succeed */\r
- for(int i=0;i<2;i++) {\r
- rv=ActivateTask(slave);\r
- assert(rv==E_OS_LIMIT);\r
- }\r
- /* When we terminate slave will be run twice */\r
- TerminateTask();\r
- }\r
-\r
-}\r
-\r
-\r
-\r
-\r
+++ /dev/null
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/*\r
- * Tested: Irq and nesting of interrupts\r
- */\r
-\r
-#include "Os.h"\r
-#include "debug.h"\r
-//#include <stdio.h>\r
-#include <assert.h>\r
-#include "os_test.h"\r
-#include "irq.h"\r
-\r
-void isr_l(void ) {\r
- switch(test_nr) {\r
- case 2:\r
- TEST_OK();\r
- test_nr++;\r
- case 5:\r
- test_nr++;\r
- /* Trigger higher prio interrupt */\r
- Irq_GenerateSoftInt(EXTI1_IRQn);\r
- TEST_ASSERT(test_nr==8);\r
- break;\r
- default:\r
- assert(0);\r
- }\r
-}\r
-\r
-void isr_m(void ) {\r
- switch(test_nr) {\r
- case 3:\r
- TEST_OK();\r
- test_nr++;\r
- case 6:\r
- test_nr++;\r
- /* Trigger higher prio interrupt */\r
- Irq_GenerateSoftInt(EXTI2_IRQn);\r
- TEST_ASSERT(test_nr==7);\r
- test_nr++;\r
- break;\r
- default:\r
- assert(0);\r
- }\r
-\r
-}\r
-\r
-void isr_h(void ) {\r
- switch(test_nr) {\r
- case 4:\r
- TEST_OK();\r
- test_nr++;\r
- case 7:\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- default:\r
- assert(0);\r
- }\r
-}\r
-\r
-\r
-void etask_sup_l_04( void ) {\r
- test_nr = 1;\r
- TaskType isr1;\r
- TaskType isr2;\r
- TaskType isr3;\r
-\r
- for(;;) {\r
- switch(test_nr){\r
- case 1:\r
- // test 01 ===============================================\r
- isr1 = Os_Arc_CreateIsr(isr_l,6/*prio*/,"ISR_L");\r
- Irq_AttachIsr2(isr1,NULL, EXTI0_IRQn);\r
-\r
- isr2 = Os_Arc_CreateIsr(isr_m,7/*prio*/,"ISR_M");\r
- Irq_AttachIsr2(isr2,NULL, EXTI1_IRQn);\r
-\r
- isr3 = Os_Arc_CreateIsr(isr_h,8/*prio*/,"ISR_H");\r
- Irq_AttachIsr2(isr3,NULL, EXTI2_IRQn);\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
-\r
- case 2:\r
- // test 02 ===============================================\r
- Irq_GenerateSoftInt(EXTI0_IRQn);\r
- TEST_ASSERT(test_nr==3);\r
- break;\r
- case 3:\r
- // test 03 ===============================================\r
- Irq_GenerateSoftInt(EXTI1_IRQn);\r
- TEST_ASSERT(test_nr==4);\r
- break;\r
- case 4:\r
- // test 04 ===============================================\r
- Irq_GenerateSoftInt(EXTI2_IRQn);\r
- TEST_ASSERT(test_nr==5);\r
- break;\r
- case 5:\r
- // test 05 ===============================================\r
- Irq_GenerateSoftInt(EXTI2_IRQn);\r
- TEST_ASSERT(test_nr==5);\r
- break;\r
- case 100:\r
- TerminateTask();\r
- default:\r
- assert(0);\r
- while(1);\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_m_04( void ) {\r
- switch(test_nr){\r
- case 1:\r
- TEST_OK();\r
- test_nr++;\r
- ChainTask(TASK_ID_etask_sup_l);\r
- break;\r
- default:\r
- while(1);\r
- }\r
-\r
-}\r
add\r
menu\r
(\r
- popup "Autosar"\r
+ popup "ArcCore"\r
(\r
popup "&Breakpoint"\r
(\r
menuitem "Reset,ALT+r" "sys.up"\r
menuitem "Restore layout,CTRL+l" "do lay"\r
menuitem "View ramlog,CTRL+s" "do ramlog"\r
+ menuitem "Run kernel testsuite" "do test"\r
) \r
)\r
\r
\r
\r
\r
+\r
\r
\r
pos 1. 1. 14.\r
text "CPU:"\r
pos 1. 2. 10.\r
-CPU: PULLDOWN "mpc5516,mpc5554,mpc5633M,CortexM3,HC12DG128A"\r
+CPU: PULLDOWN "MPC5516,MPC5554,MPC5633M,CortexM3,CortexR4F,HC12DG128A"\r
(\r
)\r
HEADER "Project config"\r
DEFBUTTON "Cancel" "jumpto win_close"\r
CLOSE "jumpto win_close"\r
)\r
+ dialog.set CPU "&cfg_cpu_g"\r
stop\r
save_close:\r
&cfg_cpu_g=dialog.string(CPU)\r
\r
\r
\r
+\r
+\r
\r
\r
\r
gosub &var\r
)\r
ELSE\r
- gosub &cmd\r
+ gosub &cmd &arg1\r
\r
\r
\r
//-------------------------------------------------------------\r
load:\r
LOCAL &file\r
- dialog.file "&cfg_project_path_g"/*.elf\r
ENTRY &file\r
-\r
- IF OS.FILE(&file)\r
+ IF "&file"==""\r
+ (\r
+ dialog.file "&cfg_project_path_g"/*.elf\r
+ ENTRY &file\r
+ )\r
+ IF OS.FILE("&file")\r
&cfg_loadfile_g="&file"\r
\r
do config save\r
r.s MSP 0x20005000\r
RETURN\r
\r
-postload_mpc5516:\r
-postload_MPC5554:\r
+postload_MPC5516:\r
postload_MPC5554:\r
postload_mpc5633M:\r
RETURN\r
postload_HC12DG128A:\r
RETURN\r
\r
+postload_CortexR4F:\r
+ RETURN\r
+\r
//-------------------------------------------------------------\r
\r
path_fast:\r
\r
\r
\r
+\r
+\r
+\r
\r
\r
\r
setup.var %SYMBOL.on %HEX.on %decimal.on %index.on %string.on\r
setup.tabsize 2.\r
\r
-menu.rp autosar.men\r
+menu.rp arccore.men\r
\r
winpos 0% 70% 50% 30%\r
area\r
\r
area.select\r
-print "## Welcome to Arc-Core simulator environment for T32 ##"\r
+print "## Welcome to ArcCore simulator environment for T32 ##"\r
print ""\r
\r
-\r
enddo\r
\r
\r
+// Manage T32 terminal \r
+// \r
+// args\r
+// 1 - file, if non-empty output is also written to this file.\r
+\r
+LOCAL &file\r
+ENtry &file\r
winclear my_term\r
WinPOS 50% 50% 50% 50% 1. 1. my_term\r
term.size 80. 300.\r
ELSE\r
(\r
term.view e:address.offset(v.address(t32_outport)) e:0\r
- term.write e:address.offset(v.address(t32_outport)) hoppsan.log \r
+ IF "&file"!=""\r
+ term.write e:address.offset(v.address(t32_outport)) "&file"\r
)\r
\r
enddo\r
\r
\r
\r
+\r
--- /dev/null
+// Copyright ArcCore AB\r
+// \r
+// DESCRIPTION \r
+// A simple testscript that runs all the test-suite located in the \r
+// system/kernel/testsystem folder (it looks for the binaries in \r
+// the "binaries" folder)\r
+\r
+// Make the !run() command work\r
+screen.always\r
+LOCAL &datafile &file &rfile &data &tmpfile &stop &testfiles\r
+\r
+&stop="no"\r
+&datafile="va1.txt"\r
+&rfile="test_result.txt"\r
+&testfiles=0.\r
+\r
+&tdir="&cfg_project_path_g\binaries\*osek*.elf"\r
+os cmd /c dir &tdir/B /O:N > &datafile\r
+\r
+os cmd /c del &rfile\r
+os cmd /c echo "" > &rfile\r
+wait 100ms\r
+\r
+// Start file at #10 to make space for others to use #1..#9\r
+OPEN #10 &datafile /read\r
+READ #10 &data\r
+WHILE "&data"!=""\r
+( \r
+// &file="&cfg_project_path_g"+"/binaries/system_kernel_testsystem_"+"&data"+".elf"\r
+ &file="&cfg_project_path_g"+"/binaries/"+"&data"\r
+\r
+ IF OS.FILE("&file")\r
+ (\r
+ &tmpfile=os.tmpfile()\r
+ GOSUB testrun &file "hopp.txt"\r
+ os cmd /c type hopp.txt >> &rfile \r
+ &testfiles=&testfiles+1\r
+ )\r
+ IF "&stop"=="yes"\r
+ (\r
+ print "Press any key"\r
+ inkey \r
+ )\r
+\r
+ READ #10 &data\r
+) \r
+\r
+CLOSE #10\r
+\r
+IF &testfiles==0\r
+ print "NO testfiles found"\r
+ELSE\r
+(\r
+ beep\r
+ print "Ran:" &testfiles " testfiles"\r
+ type "&rfile"\r
+)\r
+\r
+enddo\r
+\r
+//-------------------------------------\r
+testrun:\r
+ LOCAL &file &term_file\r
+ ENTRY &file &term_file\r
+\r
+ IF ("&file"=="")||!OS.FILE("&file")\r
+ RETURN\r
+\r
+ sys.up\r
+ do load load &file\r
+ do term &term_file\r
+ b.s exit\r
+ b.s _exit\r
+ go\r
+ wait !run()\r
+ b.d /all\r
+ term.close\r
+ RETURN\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
projects / arc.git / commitdiff