^.*obj_.*\.[h|c|s]\r
\r
\r
+
+syntax: regexp
+^.project$
\ No newline at end of file
#endif\r
}\r
\r
-\r
-#if 0\r
-void Adc_ConfigureEQADCInterrupts (void)\r
-{\r
- Adc_GroupType group;\r
-\r
-#if defined(USE_KERNEL)\r
- TaskType tid;\r
- tid = Os_Arc_CreateIsr(Adc_EQADCError,EQADC_FISR_OVER_PRIORITY,"Adc_Err");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR_OVER);\r
-\r
- tid = Os_Arc_CreateIsr(Adc_Group0ConversionComplete,EQADC_FIFO0_END_OF_QUEUE_PRIORITY,"Adc_Grp0");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR0_EOQF0);\r
-\r
- tid = Os_Arc_CreateIsr(Adc_Group1ConversionComplete,EQADC_FIFO1_END_OF_QUEUE_PRIORITY,"Adc_Grp1");\r
- Irq_AttachIsr2(tid,NULL,EQADC_FISR1_EOQF1);\r
-\r
-#else\r
- Irq_InstallVector (Adc_EQADCError,\r
- EQADC_FISR_OVER,\r
- EQADC_FISR_OVER_PRIORITY, CPU_Z1);\r
-\r
- Irq_InstallVector (Adc_Group0ConversionComplete,\r
- EQADC_FISR0_EOQF0,\r
- EQADC_FIFO0_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
-\r
- Irq_InstallVector (Adc_Group1ConversionComplete,\r
- EQADC_FISR1_EOQF1,\r
- EQADC_FIFO1_END_OF_QUEUE_PRIORITY, CPU_Z1);\r
-\r
-#endif\r
- for (group = ADC_GROUP0; group < AdcConfigPtr->nbrOfGroups; group++)\r
- {\r
- /* Enable end of queue, queue overflow/underflow interrupts. Clear corresponding flags. */\r
- EQADC.FISR[group].B.RFOF = 1;\r
- EQADC.IDCR[group].B.RFOIE = 1;\r
-\r
- EQADC.FISR[group].B.CFUF = 1;\r
- EQADC.IDCR[group].B.CFUIE = 1;\r
-\r
- EQADC.FISR[group].B.TORF = 1;\r
- EQADC.IDCR[group].B.TORIE = 1;\r
-\r
- EQADC.FISR[group].B.EOQF = 1;\r
- EQADC.IDCR[group].B.EOQIE = 1;\r
- }\r
-}\r
-#endif\r
-\r
#if (ADC_ENABLE_START_STOP_GROUP_API == STD_ON)\r
void Adc_StartGroupConversion (Adc_GroupType group)\r
{\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include "Can.h"\r
+\r
+#ifndef USE_CAN_STUB
+#include "stm32f10x.h"\r
+#include "stm32f10x_can.h"
+#include "Cpu.h"\r
+#include "Mcu.h"\r
+#include "CanIf_Cbk.h"\r
+#include "Det.h"
+#if defined(USE_DEM)
+#include "Dem.h"\r
+#endif
+#include <assert.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include "Os.h"
+#include "irq.h"\r
+#include "arc.h"
+\r
+
+/* CONFIGURATION NOTES\r
+ * ------------------------------------------------------------------\r
+ * - CanHandleType must be CAN_ARC_HANDLE_TYPE_BASIC\r
+ * i.e. CanHandleType=CAN_ARC_HANDLE_TYPE_FULL NOT supported\r
+ * i.e CanIdValue is NOT supported\r
+ * - All CanXXXProcessing must be CAN_ARC_PROCESS_TYPE_INTERRUPT\r
+ * ie CAN_ARC_PROCESS_TYPE_POLLED not supported\r
+ * - HOH's for Tx are global and Rx are for each controller\r
+ */\r
+\r
+/* IMPLEMENTATION NOTES\r
+ * -----------------------------------------------\r
+ * - A HOH us unique for a controller( not a config-set )\r
+ * - Hrh's are numbered for each controller from 0\r
+ * - loopback in HW NOT supported
+ * - Only one transmit mailbox is used because otherwise
+ * we cannot use tx_confirmation since there is no way to know
+ * which mailbox caused the tx interrupt. TP will need this feature.
+ * - Sleep,wakeup not fully implemented since other modules lack functionality\r
+ */\r
+\r
+/* ABBREVATIONS\r
+ * -----------------------------------------------\r
+ * - Can Hardware unit - One or multiple Can controllers of the same type.\r
+ * - Hrh - HOH with receive definitions\r
+ * - Hth - HOH with transmit definitions\r
+ *\r
+ */\r
+
+typedef CAN_TypeDef CAN_HW_t;\r
+//-------------------------------------------------------------------\r
+\r
+#define GET_CONTROLLER_CONFIG(_controller) \\r
+ &Can_Global.config->CanConfigSet->CanController[(_controller)]\r
+\r
+#define GET_CALLBACKS() \\r
+ (Can_Global.config->CanConfigSet->CanCallbacks)\r
+\r
+#define GET_PRIVATE_DATA(_controller) \\r
+ &CanUnit[_controller]\r
+\r
+#define GET_CONTROLLER_CNT() (CAN_CONTROLLER_CNT)\r
+\r
+//-------------------------------------------------------------------\r
+\r
+#if ( CAN_DEV_ERROR_DETECT == STD_ON )\r
+#define VALIDATE(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return CAN_NOT_OK; \\r
+ }\r
+\r
+#define VALIDATE_NO_RV(_exp,_api,_err ) \\r
+ if( !(_exp) ) { \\r
+ Det_ReportError(MODULE_ID_CAN,0,_api,_err); \\r
+ return; \\r
+ }\r
+\r
+#define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)\r
+#else\r
+#define VALIDATE(_exp,_api,_err )\r
+#define VALIDATE_NO_RV(_exp,_api,_err )\r
+#define DET_REPORTERROR(_x,_y,_z,_q)\r
+#endif\r
+
+#if defined(USE_DEM)
+#define VALIDATE_DEM_NO_RV(_exp,_err ) \
+ if( !(_exp) ) { \
+ Dem_ReportErrorStatus(_err, DEM_EVENT_STATUS_FAILED); \
+ return; \
+ }
+#else
+#define VALIDATE_DEM_NO_RV(_exp,_err )
+#endif\r
+
+//-------------------------------------------------------------------\r
+
+typedef enum\r
+{\r
+ CAN_UNINIT = 0,\r
+ CAN_READY\r
+} Can_DriverStateType;\r
+\r
+// Mapping between HRH and Controller//HOH\r
+typedef struct Can_Arc_ObjectHOHMapStruct\r
+{\r
+ CanControllerIdType CanControllerRef; // Reference to controller\r
+ const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.\r
+} Can_Arc_ObjectHOHMapType;\r
+\r
+/* Type for holding global information used by the driver */\r
+typedef struct {\r
+ Can_DriverStateType initRun;\r
+\r
+ // Our config\r
+ const Can_ConfigType *config;\r
+\r
+ // One bit for each channel that is configured.\r
+ // Used to determine if validity of a channel\r
+ // 1 - configured\r
+ // 0 - NOT configured\r
+ uint32 configured;\r
+ // Maps the a channel id to a configured channel id\r
+ uint8 channelMap[CAN_CONTROLLER_CNT];\r
+\r
+ // This is a map that maps the HTH:s with the controller and Hoh. It is built\r
+ // during Can_Init and is used to make things faster during a transmit.\r
+ Can_Arc_ObjectHOHMapType CanHTHMap[NUM_OF_HTHS];\r
+} Can_GlobalType;\r
+\r
+// Global config\r
+Can_GlobalType Can_Global =\r
+{\r
+ .initRun = CAN_UNINIT,\r
+};\r
+\r
+/* Type for holding information about each controller */\r
+typedef struct {\r
+ CanIf_ControllerModeType state;\r
+ uint32 lock_cnt;\r
+\r
+ // Statistics\r
+ Can_Arc_StatisticsType stats;\r
+\r
+ // Data stored for Txconfirmation callbacks to CanIf\r
+ PduIdType swPduHandle; //\r
+} Can_UnitType;\r
+\r
+Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =\r
+{\r
+ {\r
+ .state = CANIF_CS_UNINIT,\r
+ },
+ {\r
+ .state = CANIF_CS_UNINIT,\r
+ },\r
+};\r
+\r
+//-------------------------------------------------------------------\r
+static CAN_HW_t * GetController(int unit)
+{
+ return ((CAN_HW_t *)(CAN1_BASE + unit*0x400));
+}\r
+
+//-------------------------------------------------------------------\r
+/**\r
+ * Function that finds the Hoh( HardwareObjectHandle ) from a Hth\r
+ * A HTH may connect to one or several HOH's. Just find the first one.\r
+ *\r
+ * @param hth The transmit handle\r
+ * @returns Ptr to the Hoh\r
+ */\r
+static const Can_HardwareObjectType * Can_FindHoh( Can_Arc_HTHType hth , uint32* controller)\r
+{\r
+ const Can_HardwareObjectType *hohObj;\r
+ const Can_Arc_ObjectHOHMapType *map;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+\r
+ map = &Can_Global.CanHTHMap[hth];\r
+\r
+ // Verify that this is the correct map\r
+ if (map->CanHOHRef->CanObjectId != hth)\r
+ {\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+ }\r
+\r
+ canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[map->CanControllerRef]);\r
+\r
+ hohObj = map->CanHOHRef;\r
+\r
+ // Verify that this is the correct Hoh type\r
+ if ( hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ *controller = map->CanControllerRef;\r
+ return hohObj;\r
+ }\r
+\r
+ DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);\r
+\r
+ return NULL;\r
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+static void Can_RxIsr( int unit );
+static void Can_TxIsr( int unit );
+static void Can_ErrIsr( int unit );\r
+
+void Can_1_RxIsr( void ) { Can_RxIsr(CAN_CTRL_1); }
+void Can_2_RxIsr( void ) { Can_RxIsr(CAN_CTRL_2); }
+
+void Can_1_TxIsr( void ) { Can_TxIsr(CAN_CTRL_1); }
+void Can_2_TxIsr( void ) { Can_TxIsr(CAN_CTRL_2); }
+
+void Can_1_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_1); }
+void Can_2_ErrIsr( void ) { Can_ErrIsr(CAN_CTRL_2); }
+\r
+
+//-------------------------------------------------------------------\r
+
+// Uses 25.4.5.1 Transmission Abort Mechanism
+static void Can_AbortTx( CAN_HW_t *canHw, Can_UnitType *canUnit ) {
+ // Disable Transmit irq
+
+ // check if mb's empty
+
+ // Abort all pending mb's
+
+ // Wait for mb's being emptied
+}
+
+/**
+ * Hardware wake ISR for CAN
+ *
+ * @param unit CAN controller number( from 0 )
+ */
+static void Can_WakeIsr( int unit ) {
+ if (GET_CALLBACKS()->ControllerWakeup != NULL)
+ {
+ GET_CALLBACKS()->ControllerWakeup(unit);
+ }
+ // 269,270,271
+ Can_SetControllerMode(unit, CAN_T_STOP);
+
+ // TODO EcuM_CheckWakeup();
+}\r
+
+/**\r
+ * Hardware error ISR for CAN\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_ErrIsr( int unit ) {\r
+ CAN_HW_t *canHw = GetController(unit);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
+ Can_Arc_ErrorType err;\r
+ err.R = 0;
+
+ // Check wake up
+ if(SET == CAN_GetITStatus(canHw, CAN_IT_WKU)){\r
+ Can_WakeIsr(unit);\r
+ CAN_ClearITPendingBit(canHw, CAN_IT_WKU);
+ }
+
+ if(SET == CAN_GetITStatus(canHw, CAN_IT_BOF)){
+ canUnit->stats.boffCnt++;
+ if (GET_CALLBACKS()->ControllerBusOff != NULL)
+ {
+ GET_CALLBACKS()->ControllerBusOff(unit);
+ }
+ Can_SetControllerMode(unit, CAN_T_STOP); // CANIF272
+
+ Can_AbortTx( canHw, canUnit ); // CANIF273
+
+ // Clear int
+ CAN_ClearITPendingBit(canHw, CAN_IT_BOF);
+ }
+
+ if (err.R != 0)
+ {
+ if (GET_CALLBACKS()->Arc_Error != NULL)
+ {
+ GET_CALLBACKS()->Arc_Error( unit, err );
+ }
+ }
+}\r
+\r
+//-------------------------------------------------------------------\r
+\r
+/**\r
+ * ISR for CAN. Normal Rx/operation\r
+ *\r
+ * @param unit CAN controller number( from 0 )\r
+ */\r
+static void Can_RxIsr(int unit) {\r
+\r
+ CAN_HW_t *canHw= GetController(unit);\r
+ const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);\r
+ const Can_HardwareObjectType *hohObj;
+
+ CanRxMsg RxMessage;
+
+ RxMessage.StdId=0x00;
+ RxMessage.ExtId=0x00;
+ RxMessage.IDE=0;
+ RxMessage.DLC=0;
+ RxMessage.FMI=0;
+ RxMessage.Data[0]=0x00;
+ RxMessage.Data[1]=0x00;
+ CAN_Receive(canHw,CAN_FIFO0, &RxMessage);\r
+
+ // Loop over all the Hoh's\r
+ hohObj= canHwConfig->Can_Arc_Hoh;\r
+ --hohObj;\r
+ do {\r
+ ++hohObj;\r
+\r
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)\r
+ {\r
+ Can_IdType id=0;
+
+ // According to autosar MSB shuould be set if extended\r
+ if (RxMessage.IDE != CAN_ID_STD) {
+ id = RxMessage.ExtId;
+ id |= 0x80000000;\r
+ } else {
+ id = RxMessage.StdId;
+ }\r
+\r
+ if (GET_CALLBACKS()->RxIndication != NULL)\r
+ {\r
+ GET_CALLBACKS()->RxIndication(hohObj->CanObjectId,\r
+ id,\r
+ RxMessage.DLC,\r
+ (uint8 *)&RxMessage.Data[0] ); // Next layer will copy\r
+ }\r
+ // Increment statistics\r
+ canUnit->stats.rxSuccessCnt++;\r
+ }\r
+ } while ( !hohObj->Can_Arc_EOL);\r
+}\r
+
+/**
+ * ISR for CAN. Normal Tx operation
+ *
+ * @param unit CAN controller number( from 0 )
+ */
+static void Can_TxIsr(int unit) {
+ CAN_HW_t *canHw= GetController(unit);
+ const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
+ const Can_HardwareObjectType *hohObj;
+
+ // Loop over all the Hoh's
+ hohObj= canHwConfig->Can_Arc_Hoh;
+ --hohObj;
+ do {
+ ++hohObj;
+
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
+ {
+ if (GET_CALLBACKS()->TxConfirmation != NULL)
+ {
+ GET_CALLBACKS()->TxConfirmation(canUnit->swPduHandle);
+ }
+ canUnit->swPduHandle = 0; // Is this really necessary ??
+
+ // Clear Tx interrupt
+ CAN_ClearITPendingBit(canHw,CAN_IT_RQCP0);
+ CAN_ClearITPendingBit(canHw,CAN_IT_RQCP1);
+ CAN_ClearITPendingBit(canHw,CAN_IT_RQCP2);
+ }
+ } while ( !hohObj->Can_Arc_EOL);
+}\r
+
+//-------------------------------------------------------------------\r
+\r
+#define INSTALL_HANDLERS(_can_name,_sce,_rx,_tx) \\r
+ do { \\r
+ TaskType tid; \\r
+ tid = Os_Arc_CreateIsr(_can_name ## _ErrIsr,2/*prio*/,"Can"); \
+ Irq_AttachIsr2(tid,NULL,_sce); \
+ tid = Os_Arc_CreateIsr(_can_name ## _RxIsr,2/*prio*/,"Can"); \
+ Irq_AttachIsr2(tid,NULL,_rx); \
+ tid = Os_Arc_CreateIsr(_can_name ## _TxIsr,2/*prio*/,"Can"); \
+ Irq_AttachIsr2(tid,NULL,_tx); \
+ } while(0);\r
+\r
+// This initiates ALL can controllers\r
+void Can_Init( const Can_ConfigType *config ) {\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint32 ctlrId;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_UNINIT), 0x0, CAN_E_TRANSITION );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x0, CAN_E_PARAM_POINTER );\r
+\r
+ // Save config\r
+ Can_Global.config = config;\r
+ Can_Global.initRun = CAN_READY;\r
+\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ // Assign the configuration channel used later..\r
+ Can_Global.channelMap[canHwConfig->CanControllerId] = configId;\r
+ Can_Global.configured |= (1<<ctlrId);\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
+
+ // Note!
+ // Could install handlers depending on HW objects to trap more errors
+ // in configuration
+ switch( canHwConfig->CanControllerId ) {
+#ifndef STM32F10X_CL
+ case CAN_CTRL_1:
+ INSTALL_HANDLERS(Can_1, CAN1_SCE_IRQn, USB_LP_CAN1_RX0_IRQn, USB_HP_CAN1_TX_IRQn); break;
+#else
+ case CAN_CTRL_1:
+ INSTALL_HANDLERS(Can_1, CAN1_SCE_IRQn, CAN1_RX0_IRQn, CAN1_TX_IRQn); break;
+ case CAN_CTRL_2:
+ INSTALL_HANDLERS(Can_2, CAN2_SCE_IRQn, CAN2_RX0_IRQn, CAN2_TX_IRQn); break;
+#endif
+ default:
+ assert(0);
+ }\r
+\r
+ Can_InitController(ctlrId, canHwConfig);\r
+\r
+ // Loop through all Hoh:s and map them into the HTHMap\r
+ const Can_HardwareObjectType* hoh;\r
+ hoh = canHwConfig->Can_Arc_Hoh;\r
+ hoh--;\r
+ do\r
+ {\r
+ hoh++;\r
+\r
+ if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)\r
+ {\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanControllerRef = canHwConfig->CanControllerId;\r
+ Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;\r
+ }\r
+ } while (!hoh->Can_Arc_EOL);\r
+ }\r
+ return;\r
+}\r
+\r
+// Unitialize the module\r
+void Can_DeInit()\r
+{\r
+ Can_UnitType *canUnit;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ uint32 ctlrId;\r
+\r
+ for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {\r
+ canHwConfig = GET_CONTROLLER_CONFIG(configId);\r
+ ctlrId = canHwConfig->CanControllerId;\r
+\r
+ canUnit = GET_PRIVATE_DATA(ctlrId);\r
+ canUnit->state = CANIF_CS_UNINIT;\r
+\r
+ Can_DisableControllerInterrupts(ctlrId);\r
+\r
+ canUnit->lock_cnt = 0;\r
+\r
+ // Clear stats\r
+ memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));\r
+ }\r
+\r
+ Can_Global.config = NULL;\r
+ Can_Global.initRun = CAN_UNINIT;\r
+\r
+ return;\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)
+{\r
+ CAN_HW_t *canHw;\r
+ uint8_t tq;\r
+ uint8_t tqSync;
+ uint8_t tq1;
+ uint8_t tq2;\r
+ uint32_t clock;\r
+ Can_UnitType *canUnit;\r
+ uint8 cId = controller;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ const Can_HardwareObjectType *hohObj;\r
+\r
+ VALIDATE_NO_RV( (Can_Global.initRun == CAN_READY), 0x2, CAN_E_UNINIT );\r
+ VALIDATE_NO_RV( (config != NULL ), 0x2,CAN_E_PARAM_POINTER);\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x2, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state==CANIF_CS_STOPPED), 0x2, CAN_E_TRANSITION );\r
+\r
+ canHw = GetController(cId);\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[cId]);\r
+\r
+ // Start this baby up
+ CAN_DeInit(canHw);\r
+
+ /* CAN filter init. We set up two filters - one for the master (CAN1) and
+ * one for the slave (CAN2)
+ *
+ * CAN_SlaveStartBank(n) denotes which filter is the first of the slave.
+ *
+ * The filter registers reside in CAN1 and is shared to CAN2, so we only need
+ * to set up this once.
+ */
+
+ // We let all frames in and do the filtering in software.
+ CAN_FilterInitTypeDef CAN_FilterInitStructure;
+ CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask;
+ CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit;
+ CAN_FilterInitStructure.CAN_FilterIdHigh=0x0000;
+ CAN_FilterInitStructure.CAN_FilterIdLow=0x0000;
+ CAN_FilterInitStructure.CAN_FilterMaskIdHigh=0x0000;
+ CAN_FilterInitStructure.CAN_FilterMaskIdLow=0x0000;
+ CAN_FilterInitStructure.CAN_FilterFIFOAssignment=CAN_FIFO0;
+ CAN_FilterInitStructure.CAN_FilterActivation=ENABLE;
+
+ // Init filter 0 (CAN1/master)
+ CAN_FilterInitStructure.CAN_FilterNumber=0;
+ CAN_FilterInit(&CAN_FilterInitStructure);
+
+ // Init filter 1 (CAN2/slave)
+ CAN_FilterInitStructure.CAN_FilterNumber=1;
+ CAN_FilterInit(&CAN_FilterInitStructure);
+
+ // Set which filter to use for CAN2.
+ CAN_SlaveStartBank(1);
+
+ // acceptance filters
+ hohObj = canHwConfig->Can_Arc_Hoh;
+ --hohObj;
+ do {
+ ++hohObj;
+ if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
+ {
+ // TODO Hw filtering
+ }
+ }while( !hohObj->Can_Arc_EOL );\r
+
+ // Clock calucation\r
+ // -------------------------------------------------------------------\r
+ //\r
+ // * 1 TQ = Sclk period( also called SCK )\r
+ // * Ftq = Fcanclk / ( PRESDIV + 1 ) = Sclk\r
+ // ( Fcanclk can come from crystal or from the peripheral dividers )\r
+ //\r
+ // -->\r
+ // TQ = 1/Ftq = (PRESDIV+1)/Fcanclk --> PRESDIV = (TQ * Fcanclk - 1 )\r
+ // TQ is between 8 and 25\r
+ clock = McuE_GetSystemClock()/2;
+
+ tqSync = config->CanControllerPropSeg + 1;
+ tq1 = config->CanControllerSeg1 + 1;\r
+ tq2 = config->CanControllerSeg2 + 1;\r
+ tq = tqSync + tq1 + tq2;\r
+\r
+ // Check TQ limitations..
+ VALIDATE_DEM_NO_RV(( (tq1>=1) && (tq1<=16)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq2>=1) && (tq2<=8)), CAN_E_TIMEOUT );\r
+ VALIDATE_DEM_NO_RV(( (tq>=1) && (tq<5 )), CAN_E_TIMEOUT );
+
+ CAN_InitTypeDef CAN_InitStructure;
+ CAN_StructInit(&CAN_InitStructure);
+
+ /* CAN cell init */
+ CAN_InitStructure.CAN_TTCM=DISABLE;
+ CAN_InitStructure.CAN_ABOM=ENABLE;
+ CAN_InitStructure.CAN_AWUM=ENABLE;
+ CAN_InitStructure.CAN_NART=DISABLE;
+ CAN_InitStructure.CAN_RFLM=DISABLE;
+ CAN_InitStructure.CAN_TXFP=DISABLE;
+ CAN_InitStructure.CAN_Mode=CAN_Mode_Normal;//CAN_Mode_LoopBack;
+
+ CAN_InitStructure.CAN_SJW=config->CanControllerPropSeg;
+ CAN_InitStructure.CAN_BS1=config->CanControllerSeg1;
+ CAN_InitStructure.CAN_BS2=config->CanControllerSeg2;
+ CAN_InitStructure.CAN_Prescaler= clock/(config->CanControllerBaudRate*1000*tq);
+
+ if(CANINITOK != CAN_Init(canHw,&CAN_InitStructure))
+ {
+ return;
+ }\r
+
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_EnableControllerInterrupts(cId);\r
+\r
+ return;\r
+}\r
+\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 controller, Can_StateTransitionType transition ) {\r
+ CAN_HW_t *canHw;\r
+ Can_ReturnType rv = CAN_OK;\r
+ VALIDATE( (controller < GET_CONTROLLER_CNT()), 0x3, CAN_E_PARAM_CONTROLLER );\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE( (canUnit->state!=CANIF_CS_UNINIT), 0x3, CAN_E_UNINIT );\r
+ canHw = GetController(controller);\r
+\r
+ switch(transition )\r
+ {\r
+ case CAN_T_START:\r
+ canUnit->state = CANIF_CS_STARTED;\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if (canUnit->lock_cnt == 0){ // REQ CAN196\r
+ Can_EnableControllerInterrupts(controller);
+ }\r
+ McuE_ExitCriticalSection(state);\r
+ break;\r
+ case CAN_T_WAKEUP:
+ VALIDATE(canUnit->state == CANIF_CS_SLEEP, 0x3, CAN_E_TRANSITION);
+ CAN_WakeUp(canHw);
+ canUnit->state = CANIF_CS_STOPPED;
+ break;\r
+ case CAN_T_SLEEP: //CAN258, CAN290\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ CAN_Sleep(canHw);
+ canUnit->state = CANIF_CS_SLEEP;
+ break;
+ case CAN_T_STOP:\r
+ // Stop\r
+ canUnit->state = CANIF_CS_STOPPED;\r
+ Can_AbortTx( canHw, canUnit ); // CANIF282\r
+ break;\r
+ default:\r
+ // Should be reported to DEM but DET is the next best\r
+ VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);\r
+ break;\r
+ }\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+ Can_UnitType *canUnit;\r
+ CAN_HW_t *canHw;\r
+\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x4, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x4, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if(canUnit->lock_cnt > 0 )\r
+ {\r
+ // Interrupts already disabled\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ }\r
+ canUnit->lock_cnt++;\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ /* Don't try to be intelligent, turn everything off */\r
+ canHw = GetController(controller);\r
+\r
+ /* Turn off the tx interrupt mailboxes */\r
+ CAN_ITConfig(canHw, CAN_IT_TME, DISABLE);\r
+
+ /* Turn off the bus off/tx warning/rx warning and error and rx */\r
+ CAN_ITConfig(canHw, CAN_IT_FMP0 | CAN_IT_BOF | CAN_IT_ERR | CAN_IT_WKU, DISABLE);
+}\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller ) {\r
+ Can_UnitType *canUnit;\r
+ CAN_HW_t *canHw;\r
+ const Can_ControllerConfigType *canHwConfig;\r
+ VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x5, CAN_E_PARAM_CONTROLLER );\r
+\r
+ canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x5, CAN_E_UNINIT );\r
+\r
+ imask_t state = McuE_EnterCriticalSection();\r
+ if( canUnit->lock_cnt > 1 )\r
+ {\r
+ // IRQ should still be disabled so just decrement counter\r
+ canUnit->lock_cnt--;\r
+ McuE_ExitCriticalSection(state);\r
+ return;\r
+ } else if (canUnit->lock_cnt == 1)\r
+ {\r
+ canUnit->lock_cnt = 0;\r
+ }\r
+ McuE_ExitCriticalSection(state);\r
+\r
+ canHw = GetController(controller);\r
+\r
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);\r
+\r
+ if( canHwConfig->CanRxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the rx interrupt */\r
+ CAN_ITConfig(canHw, CAN_IT_FMP0, ENABLE);
+ }
+ if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
+ /* Turn on the tx interrupt mailboxes */
+ CAN_ITConfig(canHw, CAN_IT_TME, ENABLE);
+ }\r
+\r
+ // BusOff here represents all errors and warnings\r
+ if( canHwConfig->CanBusOffProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {\r
+ /* Turn on the bus off/tx warning/rx warning and error and rx */
+ CAN_ITConfig(canHw, CAN_IT_BOF | CAN_IT_ERR | CAN_IT_WKU, ENABLE);
+ }\r
+\r
+ return;\r
+}\r
+
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo ) {\r
+ Can_ReturnType rv = CAN_OK;\r
+ CAN_HW_t *canHw;\r
+ const Can_HardwareObjectType *hohObj;\r
+ const Can_ControllerConfigType *canHwConfig;
+ uint32 controller;\r
+ uint32 oldMsr;\r
+
+ VALIDATE( (Can_Global.initRun == CAN_READY), 0x6, CAN_E_UNINIT );\r
+ VALIDATE( (pduInfo != NULL), 0x6, CAN_E_PARAM_POINTER );\r
+ VALIDATE( (pduInfo->length <= 8), 0x6, CAN_E_PARAM_DLC );\r
+ VALIDATE( (hth < NUM_OF_HTHS ), 0x6, CAN_E_PARAM_HANDLE );\r
+\r
+ hohObj = Can_FindHoh(hth, &controller);\r
+ if (hohObj == NULL)\r
+ return CAN_NOT_OK;\r
+\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+\r
+ canHw = GetController(controller);\r
+ oldMsr = McuE_EnterCriticalSection();\r
+
+ CanTxMsg TxMessage;
+
+ TxMessage.RTR=CAN_RTR_DATA;
+ TxMessage.DLC=pduInfo->length;
+
+ memcpy(TxMessage.Data, pduInfo->sdu, pduInfo->length);
+
+ if (hohObj->CanIdType == CAN_ID_TYPE_EXTENDED) {
+ TxMessage.IDE=CAN_ID_EXT;
+ TxMessage.ExtId=pduInfo->id;
+ } else {
+ TxMessage.IDE=CAN_ID_STD;
+ TxMessage.StdId=pduInfo->id;
+ }\r
+
+ // check for any free box\r
+ if(CAN_Transmit(canHw,&TxMessage) != CAN_NO_MB) {
+ canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);
+
+ if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
+ /* Turn on the tx interrupt mailboxes */
+ CAN_ITConfig(canHw,CAN_IT_TME, ENABLE);
+ }
+
+ // Increment statistics
+ canUnit->stats.txSuccessCnt++;\r
+
+ // Store pdu handle in unit to be used by TxConfirmation\r
+ canUnit->swPduHandle = pduInfo->swPduHandle;\r
+ } else {\r
+ rv = CAN_BUSY;\r
+ }\r
+ McuE_ExitCriticalSection(oldMsr);\r
+\r
+ return rv;\r
+}\r
+\r
+void Can_MainFunction_Read( void ) {\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_BusOff( void ) {\r
+ /* Bus-off polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+void Can_MainFunction_Wakeup( void ) {\r
+ /* Wakeup polling events */\r
+\r
+ /* NOT SUPPORTED */\r
+}\r
+\r
+\r
+/**\r
+ * Get send/receive/error statistics for a controller\r
+ *\r
+ * @param controller The controller\r
+ * @param stats Pointer to data to copy statistics to\r
+ */\r
+\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType *stats)\r
+{\r
+ Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);\r
+ *stats = canUnit->stats;\r
+}\r
+\r
+#else // Stub all functions for use in simulator environment\r
+\r
+#include "debug.h"\r
+\r
+void Can_Init( const Can_ConfigType *Config )\r
+{\r
+ // Do initial configuration of layer here\r
+}\r
+\r
+void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)\r
+{\r
+ // Do initialisation of controller here.\r
+}\r
+\r
+Can_ReturnType Can_SetControllerMode( uint8 Controller, Can_StateTransitionType transition )\r
+{\r
+ // Turn on off controller here depending on transition\r
+ return E_OK;\r
+}\r
+\r
+Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo )\r
+{\r
+ // Write to mailbox on controller here.\r
+ DEBUG(DEBUG_MEDIUM, "Can_Write(stub): Received data ");\r
+ for (int i = 0; i < pduInfo->length; i++) {\r
+ DEBUG(DEBUG_MEDIUM, "%d ", pduInfo->sdu[i]);\r
+ }\r
+ DEBUG(DEBUG_MEDIUM, "\n");\r
+\r
+ return E_OK;\r
+}\r
+\r
+extern void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc, const uint8 *CanSduPtr);\r
+Can_ReturnType Can_ReceiveAFrame()\r
+{\r
+ // This function is not part of autosar but needed to feed the stack with data\r
+ // from the mailboxes. Normally this is an interrup but probably not in the PCAN case.\r
+ uint8 CanSduData[] = {1,2,1,0,0,0,0,0};\r
+ CanIf_RxIndication(CAN_HRH_0_1, 3, 8, CanSduData);\r
+\r
+ return E_OK;\r
+}\r
+\r
+void Can_DisableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+void Can_EnableControllerInterrupts( uint8 controller )\r
+{\r
+}\r
+\r
+\r
+// Hth - for Flexcan, the hardware message box number... .We don't care\r
+void Can_Cbk_CheckWakeup( uint8 controller ){}\r
+\r
+void Can_MainFunction_Write( void ){}\r
+void Can_MainFunction_Read( void ){}\r
+void Can_MainFunction_BusOff( void ){}\r
+void Can_MainFunction_Wakeup( void ){}\r
+\r
+void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType * stat){}\r
+\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include "Std_Types.h"\r
+#include "Dio.h"\r
+#include "Det.h"\r
+#include <string.h>\r
+#include "stm32f10x_gpio.h"\r
+\r
+typedef GPIO_TypeDef* GPIO_TypeDefPtr;\r
+const GPIO_TypeDefPtr GPIO_ports[] = { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF };\r
+\r
+#define DIO_GET_PORT_FROM_CHANNEL_ID(_channelId) (_channelId / 16)\r
+#define DIO_GET_BIT_FROM_CHANNEL_ID(_channelId) (1 << (_channelId % 16))\r
+\r
+#if ( DIO_VERSION_INFO_API == STD_ON )\r
+static Std_VersionInfoType _Dio_VersionInfo =\r
+{\r
+ .vendorID = (uint16)1,\r
+ .moduleID = (uint16)1,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)DIO_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)DIO_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)DIO_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)DIO_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)DIO_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)DIO_AR_PATCH_VERSION,\r
+};\r
+#endif\r
+\r
+#if ( DIO_DEV_ERROR_DETECT == STD_ON )\r
+static int Channel_Config_Contains(Dio_ChannelType channelId)\r
+{\r
+ Dio_ChannelType* ch_ptr=(Dio_ChannelType*)CHANNEL_PTR;\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*ch_ptr)\r
+ {\r
+ if (*ch_ptr==channelId)\r
+ {\r
+ rv=1;\r
+ break;\r
+ }\r
+ ch_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Port_Config_Contains(Dio_PortType portId)\r
+{\r
+ Dio_PortType* port_ptr=(Dio_PortType*)PORT_PTR;\r
+ int rv=0;\r
+ while (DIO_END_OF_LIST!=*port_ptr)\r
+ {\r
+ if (*port_ptr==portId)\r
+ { rv=1; break;}\r
+ port_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+static int Channel_Group_Config_Contains(const Dio_ChannelGroupType* _channelGroupIdPtr)\r
+{\r
+ Dio_ChannelGroupType* chGrp_ptr=(Dio_ChannelGroupType*)CHANNEL_GRP_PTR;\r
+ int rv=0;\r
+\r
+ while (DIO_END_OF_LIST!=chGrp_ptr->port)\r
+ {\r
+ if (chGrp_ptr->port==_channelGroupIdPtr->port&&\r
+ chGrp_ptr->offset==_channelGroupIdPtr->offset&&\r
+ chGrp_ptr->mask==_channelGroupIdPtr->mask)\r
+ { rv=1; break;}\r
+ chGrp_ptr++;\r
+ }\r
+ return rv;\r
+}\r
+\r
+#define VALIDATE_CHANNEL(_channelId, _api) \\r
+ if(0==Channel_Config_Contains(channelId)) { \\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_CHANNEL_ID ); \\r
+ level = 0; \\r
+ goto cleanup; \\r
+ }\r
+#define VALIDATE_PORT(_portId, _api)\\r
+ if(0==Port_Config_Contains(_portId)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_PORT_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\\r
+ if(0==Channel_Group_Config_Contains(_channelGroupIdPtr)) {\\r
+ Det_ReportError(MODULE_ID_DIO,0,_api,DIO_E_PARAM_INVALID_GROUP_ID ); \\r
+ level = STD_LOW;\\r
+ goto cleanup;\\r
+ }\r
+#else\r
+#define VALIDATE_CHANNEL(_channelId, _api)\r
+#define VALIDATE_PORT(_portId, _api)\r
+#define VALIDATE_CHANNELGROUP(_channelGroupIdPtr, _api)\r
+#endif\r
+\r
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId)\r
+{\r
+ Dio_LevelType level = 0;\r
+ VALIDATE_PORT(portId, DIO_READPORT_ID);\r
+\r
+ level = GPIO_ReadInputData(GPIO_ports[portId]);\r
+\r
+ cleanup: return level;\r
+}\r
+\r
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level)\r
+{\r
+ VALIDATE_PORT(portId, DIO_WRITEPORT_ID);\r
+\r
+ GPIO_Write(GPIO_ports[portId], level);\r
+\r
+ cleanup: return;\r
+}\r
+\r
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNEL(channelId, DIO_READCHANNEL_ID);\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId));\r
+ Dio_PortLevelType bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if ((portVal & bit) != STD_LOW){\r
+ level = STD_HIGH;\r
+ } else{\r
+ level = STD_LOW;\r
+ }\r
+\r
+ cleanup: return (level);\r
+}\r
+\r
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level)\r
+{\r
+ VALIDATE_CHANNEL(channelId, DIO_WRITECHANNEL_ID);\r
+\r
+ Dio_PortLevelType portVal = Dio_ReadPort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId));\r
+ Dio_PortLevelType bit = DIO_GET_BIT_FROM_CHANNEL_ID(channelId);\r
+\r
+ if(level == STD_HIGH){\r
+ portVal |= bit;\r
+ }else{\r
+ portVal &= ~bit;\r
+ }\r
+\r
+ Dio_WritePort(DIO_GET_PORT_FROM_CHANNEL_ID(channelId), portVal);\r
+\r
+ cleanup: return;\r
+}\r
+\r
+\r
+Dio_PortLevelType Dio_ReadChannelGroup(\r
+ const Dio_ChannelGroupType *channelGroupIdPtr)\r
+{\r
+ Dio_LevelType level;\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_READCHANNELGROUP_ID);\r
+\r
+ // Get masked values\r
+ level = Dio_ReadPort(channelGroupIdPtr->port) & channelGroupIdPtr->mask;\r
+\r
+ // Shift down\r
+ level = level >> channelGroupIdPtr->offset;\r
+\r
+ cleanup: return level;\r
+}\r
+\r
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr,\r
+ Dio_PortLevelType level)\r
+{\r
+ VALIDATE_CHANNELGROUP(channelGroupIdPtr,DIO_WRITECHANNELGROUP_ID);\r
+\r
+ // Shift up and apply mask so that no unwanted bits are affected\r
+ level = (level << channelGroupIdPtr->offset) & channelGroupIdPtr->mask;\r
+\r
+ // Read port and clear out masked bits\r
+ Dio_PortLevelType portVal = Dio_ReadPort(channelGroupIdPtr->port) & (~channelGroupIdPtr->mask);\r
+\r
+ // Or in the upshifted masked level\r
+ portVal |= level;\r
+\r
+ Dio_WritePort(channelGroupIdPtr->port, portVal);\r
+\r
+ cleanup: return;\r
+}\r
+\r
+#if (DIO_VERSION_INFO_API == STD_ON)\r
+void Dio_GetVersionInfo(Std_VersionInfoType *versionInfo)\r
+{\r
+ memcpy(versionInfo, &_Dio_VersionInfo, sizeof(Std_VersionInfoType));\r
+}\r
+#endif\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "stm32f10x_flash.h"\r
+#include "Fls.h"\r
+\r
+static Fls_ConfigType const *flsConfigPtr;\r
+\r
+void Fls_Init(const Fls_ConfigType *ConfigPtr)\r
+{\r
+ flsConfigPtr = ConfigPtr;\r
+}\r
+\r
+Std_ReturnType Fls_Erase(Fls_AddressType TargetAddress, Fls_LengthType Length)\r
+{\r
+ Fls_AddressType pageStart = 0;\r
+ Fls_AddressType erased = 0;\r
+ u32 page = 0;\r
+ u32 pageIndex;\r
+\r
+ /* Unlock the Flash Program Erase controller */\r
+ FLASH_Unlock();\r
+ /* Clear All pending flags */\r
+ FLASH_ClearFlag(FLASH_FLAG_BSY | FLASH_FLAG_EOP | FLASH_FLAG_PGERR | FLASH_FLAG_WRPRTERR);\r
+\r
+ /* Find first sector. */\r
+ page = (TargetAddress - flsConfigPtr->FlsSectorList[0].FlsSectorStartaddress) / flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ pageStart = flsConfigPtr->FlsSectorList[0].FlsSectorStartaddress + page * flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ //page = Length / flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+\r
+ /* Erase the pages... */\r
+ for (pageIndex = page; erased < Length; pageIndex++)\r
+ {\r
+ volatile FLASH_Status status = FLASH_BUSY;\r
+ while(status != FLASH_COMPLETE){\r
+ status = FLASH_ErasePage((uint32_t)pageStart);\r
+ }\r
+ erased += flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ pageStart += flsConfigPtr->FlsSectorList[0].FlsPageSize;\r
+ }\r
+\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType Fls_Write(Fls_AddressType TargetAddress, const uint8 *SourceAddressPtr, Fls_LengthType Length)\r
+{\r
+ FLASH_Status stResult;\r
+ Fls_LengthType len = Length;\r
+ Fls_AddressType addr = TargetAddress;\r
+ const uint8 *srcPtr = SourceAddressPtr;\r
+\r
+ while (len >= sizeof(uint32_t))\r
+ {\r
+ stResult = FLASH_ProgramWord((uint32_t)addr, (uint32_t)*(uint32_t *)srcPtr);\r
+ srcPtr += sizeof(uint32_t);\r
+ addr += sizeof(uint32_t);\r
+ len -= sizeof(uint32_t);\r
+ }\r
+\r
+ if (len == sizeof(uint16_t))\r
+ {\r
+ FLASH_ProgramHalfWord((uint32_t)addr, (uint16_t)*(uint16_t *)srcPtr);\r
+ srcPtr += sizeof(uint16_t);\r
+ addr += sizeof(uint16_t);\r
+ len -= sizeof(uint16_t);\r
+ }\r
+\r
+ return E_OK;\r
+}\r
#include "cpu.h"\r
#include <string.h>\r
#include "Ramlog.h"\r
-#include "system_stm32f10x.h"\r
\r
//#define USE_TRACE 1\r
//#define USE_LDEBUG_PRINTF 1\r
return NULL;\r
}\r
\r
-\r
-\r
/**\r
* Identify the core, just to check that we have support for it.\r
*\r
*/\r
static uint32 Mcu_CheckCpu( void ) {\r
\r
- uint32 pvr;\r
+ uint32 pvr = SCB->CPUID;\r
//uint32 pir;\r
//cpu_info_t *cpuType;\r
core_info_t *coreType;\r
return 0;\r
}\r
\r
+static uint32_t GetPllValueFromMult(uint8_t pll)\r
+{\r
+ return (((uint32_t)pll - 2) << 18);\r
+}\r
+static uint32_t GetPll2ValueFromMult(uint8_t pll)\r
+{\r
+ return (((uint32_t)pll - 2) << 8);\r
+}\r
+\r
+/**\r
+ * Set bus clocks. SysClk,AHBClk,APB1Clk,APB2Clk\r
+ */\r
+static void SetClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+ volatile uint32 StartUpCounter = 0, HSEStatus = 0;\r
+\r
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/\r
+ /* Enable HSE */\r
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
+\r
+ /* Wait till HSE is ready and if Time out is reached exit */\r
+ do\r
+ {\r
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
+ StartUpCounter++;\r
+ } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
+\r
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
+ {\r
+ HSEStatus = (uint32_t)0x01;\r
+ }\r
+ else\r
+ {\r
+ HSEStatus = (uint32_t)0x00;\r
+ }\r
+\r
+ if (HSEStatus == (uint32_t)0x01)\r
+ {\r
+ /* Enable Prefetch Buffer */\r
+ FLASH->ACR |= FLASH_ACR_PRFTBE;\r
+\r
+ /* Flash 2 wait state */\r
+ FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
+ FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;\r
+\r
+\r
+ /* HCLK = SYSCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
+\r
+ /* PCLK2 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
+\r
+ /* PCLK1 = HCLK */\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
+\r
+#ifdef STM32F10X_CL\r
+ /* Configure PLLs ------------------------------------------------------*/\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
+\r
+ RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
+ RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
+ RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | GetPll2ValueFromMult(clockSettingsPtr->Pll2) |\r
+ RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
+\r
+ /* Enable PLL2 */\r
+ RCC->CR |= RCC_CR_PLL2ON;\r
+ /* Wait till PLL2 is ready */\r
+ while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |\r
+ GetPllValueFromMult(clockSettingsPtr->Pll1));\r
+#else\r
+ /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
+ RCC_CFGR_PLLMULL));\r
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | GetPllValueFromMult(clockSettingsPtr->Pll1));\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Enable PLL */\r
+ RCC->CR |= RCC_CR_PLLON;\r
+\r
+ /* Wait till PLL is ready */\r
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
+ {\r
+ }\r
+\r
+ /* Select PLL as system clock source */\r
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;\r
+\r
+ /* Wait till PLL is used as system clock source */\r
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
+ {\r
+ }\r
+ }\r
+ else\r
+ { /* HSE fails to start-up, the application will have wrong clock */\r
+ NVIC_SystemReset();\r
+ }\r
+}\r
+\r
+/**\r
+ * Initialize Peripherals clocks\r
+ */\r
+static void InitPerClocks()\r
+{\r
+ RCC->AHBENR |= McuPerClockConfigData.AHBClocksEnable;\r
+ RCC->APB1ENR |= McuPerClockConfigData.APB1ClocksEnable;\r
+ RCC->APB2ENR |= McuPerClockConfigData.APB2ClocksEnable;\r
+}\r
+\r
+/**\r
+ * Initialize Flash, PLL and clocks.\r
+ */\r
+static void InitMcuClocks(Mcu_ClockSettingConfigType *clockSettingsPtr)\r
+{\r
+ /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
+ /* Set HSION bit */\r
+ RCC->CR |= (uint32_t)0x00000001;\r
+\r
+ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
+#ifndef STM32F10X_CL\r
+ RCC->CFGR &= (uint32_t)0xF8FF0000;\r
+#else\r
+ RCC->CFGR &= (uint32_t)0xF0FF0000;\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Reset HSEON, CSSON and PLLON bits */\r
+ RCC->CR &= (uint32_t)0xFEF6FFFF;\r
+\r
+ /* Reset HSEBYP bit */\r
+ RCC->CR &= (uint32_t)0xFFFBFFFF;\r
+\r
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
+\r
+#ifndef STM32F10X_CL\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x009F0000;\r
+#else\r
+ /* Reset PLL2ON and PLL3ON bits */\r
+ RCC->CR &= (uint32_t)0xEBFFFFFF;\r
+\r
+ /* Disable all interrupts and clear pending bits */\r
+ RCC->CIR = 0x00FF0000;\r
+\r
+ /* Reset CFGR2 register */\r
+ RCC->CFGR2 = 0x00000000;\r
+#endif /* STM32F10X_CL */\r
+\r
+ /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
+ /* Configure the Flash Latency cycles and enable prefetch buffer */\r
+ SetClocks(clockSettingsPtr);\r
+}\r
\r
//-------------------------------------------------------------------\r
\r
{\r
VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );\r
\r
- if( !SIMULATOR() ) {\r
- Mcu_CheckCpu();\r
- }\r
+#if !defined(USE_SIMULATOR)\r
+ Mcu_CheckCpu();\r
+#endif\r
\r
memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));\r
\r
-\r
- SystemInit();\r
-\r
Irq_Enable();\r
\r
Mcu_Global.config = configPtr;\r
Mcu_Global.clockSetting = ClockSetting;\r
clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];\r
\r
+ InitMcuClocks(clockSettingsPtr);\r
+\r
+ InitPerClocks(clockSettingsPtr);\r
\r
return E_OK;\r
}\r
VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );\r
Mcu_PllStatusType rv;\r
\r
- if (!SIMULATOR()) {\r
- if (RCC->CR & RCC_CR_PLLRDY) {\r
- rv = MCU_PLL_LOCKED;\r
- } else {\r
- rv = MCU_PLL_UNLOCKED;\r
- }\r
- } else {\r
- /* We are running on instruction set simulator. PLL is then always in sync... */\r
+#if !defined(USE_SIMULATOR)\r
+ if (RCC->CR & RCC_CR_PLLRDY) {\r
rv = MCU_PLL_LOCKED;\r
+ } else {\r
+ rv = MCU_PLL_UNLOCKED;\r
}\r
-\r
+#else\r
+ /* We are running on instruction set simulator. PLL is then always in sync... */\r
+ rv = MCU_PLL_LOCKED;\r
+#endif\r
return rv;\r
}\r
\r
*/\r
uint32_t McuE_GetSystemClock(void)\r
{\r
- /*\r
- * System clock calculation\r
- *\r
- */\r
+ uint32_t f_sys;\r
\r
- // TODO: This of course wrong....\r
- uint32_t f_sys = 72000000UL;\r
-#if 0\r
uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;\r
-\r
- f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);\r
+ uint32 pll1 = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].Pll1;\r
+\r
+#ifdef STM32F10X_CL\r
+ uint32 pll2 = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].Pll2;\r
+ /* PLL2 configuration: PLL2CLK = (HSE / 5) * PLL2 */\r
+ /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 */\r
+ /* PLL configuration: PLLCLK = PREDIV1 * PLL1 */\r
+ f_sys = (extal / 5 * pll2) / 5 * pll1;\r
+#else\r
+ /* PLL configuration: PLLCLK = HSE * PLL1 */\r
+ f_sys = extal * pll1;\r
#endif\r
\r
-// f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));\r
return f_sys;\r
}\r
\r
imask_t McuE_EnterCriticalSection()\r
{\r
-#if 0\r
- uint32_t msr = get_msr();\r
- Irq_Disable();\r
- return msr;\r
-#endif\r
- return 0;\r
+ uint32_t val;\r
+ Irq_Save(val);\r
+ return val;\r
}\r
\r
void McuE_ExitCriticalSection(uint32_t old_state)\r
{\r
-#if 0\r
- set_msr(old_state);\r
-#endif\r
+ Irq_Restore(old_state);\r
}\r
\r
/**\r
* Get the peripheral clock in Hz for a specific device\r
*/\r
-\r
-#if 0\r
uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)\r
{\r
+ uint32_t res = 0;\r
+\r
+ switch(type)\r
+ {\r
+ case PERIPHERAL_CLOCK_AHB:\r
+ res = McuE_GetSystemClock();\r
+ break;\r
+ case PERIPHERAL_CLOCK_APB1:\r
+ res = McuE_GetSystemClock() / 2;\r
+ break;\r
+ case PERIPHERAL_CLOCK_APB2:\r
+ res = McuE_GetSystemClock();\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
\r
- return 0;\r
+ return res;\r
}\r
-#endif\r
\r
\r
/**\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "Std_Types.h"\r
+#include "Port.h" /** @req PORT131 */\r
+#include "Det.h"\r
+#include "string.h"\r
+#include "stm32f10x_rcc.h"\r
+\r
+typedef enum\r
+{\r
+ PORT_UNINITIALIZED = 0, PORT_INITIALIZED,\r
+} Port_StateType;\r
+\r
+static Port_StateType _portState = PORT_UNINITIALIZED;\r
+static Port_ConfigType * _configPtr = NULL;\r
+\r
+/** @req PORT107 */\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api) \\r
+ if( (_ptr)==((void *)0) ) { \\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_PARAM_CONFIG ); \\r
+ goto cleanup; \\r
+ }\r
+\r
+#define VALIDATE_STATE_INIT(_api)\\r
+ if(PORT_INITIALIZED!=_portState){\\r
+ Det_ReportError(MODULE_ID_PORT, 0, _api, PORT_E_UNINIT ); \\r
+ goto cleanup; \\r
+ }\r
+\r
+#else\r
+#define VALIDATE_PARAM_CONFIG(_ptr,_api)\r
+#define VALIDATE_STATE_INIT(_api)\r
+#define VALIDATE_PARAM_PIN(_api)\r
+#endif\r
+\r
+static Std_VersionInfoType _Port_VersionInfo =\r
+{ .vendorID = (uint16)1, .moduleID = (uint16) MODULE_ID_PORT,\r
+ .instanceID = (uint8)1,\r
+ .sw_major_version = (uint8)PORT_SW_MAJOR_VERSION,\r
+ .sw_minor_version = (uint8)PORT_SW_MINOR_VERSION,\r
+ .sw_patch_version = (uint8)PORT_SW_PATCH_VERSION,\r
+ .ar_major_version = (uint8)PORT_AR_MAJOR_VERSION,\r
+ .ar_minor_version = (uint8)PORT_AR_MINOR_VERSION,\r
+ .ar_patch_version = (uint8)PORT_AR_PATCH_VERSION, };\r
+\r
+/** @req PORT140 */\r
+/** @req PORT041 Comment: To reduce flash usage the configuration tool can disable configuration of some ports */\r
+/** @req PORT078 See environment i.e Ecu State Manager */\r
+/** @req PORT042 */\r
+/** @req PORT113 Number 2 in list is applicable for all pins. */\r
+/** @req PORT043 Comment: Output value is set before direction */\r
+/** @req PORT071 See environment i.e Ecu State Manager */\r
+/** @req PORT002 The _portState varialble is initialised. */\r
+/** @req PORT003 See environment i.e Ecu State Manager */\r
+/** @req PORT055 Comment: Output value is set before direction */\r
+/** @req PORT121 */\r
+void Port_Init(const Port_ConfigType *configType)\r
+{\r
+ VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID); /** @req PORT105 */\r
+\r
+ uint16_t portIndex,pinIndex;\r
+\r
+ // Set up all the ports\r
+ for (portIndex = 0; portIndex < configType->portCount; portIndex++) {\r
+ const Port_PortConfigType* portConfig = configType->ports[portIndex];\r
+\r
+ // set up all pins\r
+ for (pinIndex = 0; pinIndex < portConfig->pinCount; pinIndex++) {\r
+\r
+ GPIO_Init(portConfig->port, &portConfig->pins[pinIndex]);\r
+\r
+ }\r
+ }\r
+\r
+ // Enable remaps\r
+ for (portIndex = 0; portIndex < configType->remapCount; portIndex++) {\r
+ GPIO_PinRemapConfig(configType->remaps[portIndex], ENABLE);\r
+ }\r
+\r
+ _portState = PORT_INITIALIZED;\r
+ _configPtr = configType;\r
+ cleanup: return;\r
+}\r
+\r
+/** @req PORT141 */\r
+/** @req PORT063 */\r
+/** @req PORT054 */\r
+/** @req PORT086 */\r
+#if ( PORT_SET_PIN_DIRECTION_API == STD_ON )\r
+void Port_SetPinDirection( Port_PinType pin, Port_PinDirectionType direction )\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
+\r
+ {\r
+ Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_DIRECTION_ID, PORT_E_PARAM_PIN );\r
+ }\r
+\r
+ cleanup:return;\r
+}\r
+#endif\r
+\r
+/** @req PORT066 */\r
+/** @req PORT142 */\r
+/** @req PORT060 */\r
+/** @req PORT061 */\r
+void Port_RefreshPortDirection(void)\r
+{\r
+ uint8_t curValue;\r
+ VALIDATE_STATE_INIT(PORT_REFRESH_PORT_DIRECTION_ID);\r
+\r
+ cleanup: return;\r
+}\r
+\r
+/** req PORT143 */\r
+/** req PORT102 */\r
+/** req PORT103 */\r
+#if (PORT_VERSION_INFO_API == STD_ON)\r
+void Port_GetVersionInfo(Std_VersionInfoType* versionInfo)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_GET_VERSION_INFO_ID);\r
+ memcpy(versionInfo, &_Port_VersionInfo, sizeof(Std_VersionInfoType));\r
+ cleanup: return;\r
+}\r
+#endif\r
+\r
+/** req PORT145 */\r
+/** req PORT125 */\r
+/** req PORT128 */\r
+#if (PORT_SET_PIN_MODE_API == STD_ON)\r
+void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode)\r
+{\r
+ VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
+\r
+ // Mode of pins not changeable on this CPU\r
+#if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+ Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_MODE_ID, PORT_E_MODE_UNCHANGEABLE );\r
+#endif\r
+\r
+ cleanup: return;\r
+}\r
+#endif\r
+\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file misc.c\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief This file provides all the miscellaneous firmware functions (add-on\r
- * to CMSIS functions).\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "misc.h"\r
-\r
-#define assert_param(expr) ((void)0)\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC \r
- * @brief MISC driver modules\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */ \r
-\r
-/** @defgroup MISC_Private_Defines\r
- * @{\r
- */\r
-\r
-#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Variables\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configures the priority grouping: pre-emption priority and subpriority.\r
- * @param NVIC_PriorityGroup: specifies the priority grouping bits length. \r
- * This parameter can be one of the following values:\r
- * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority\r
- * 4 bits for subpriority\r
- * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority\r
- * 3 bits for subpriority\r
- * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority\r
- * 2 bits for subpriority\r
- * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority\r
- * 1 bits for subpriority\r
- * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority\r
- * 0 bits for subpriority\r
- * @retval None\r
- */\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));\r
- \r
- /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */\r
- SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;\r
-}\r
-\r
-/**\r
- * @brief Initializes the NVIC peripheral according to the specified\r
- * parameters in the NVIC_InitStruct.\r
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains\r
- * the configuration information for the specified NVIC peripheral.\r
- * @retval None\r
- */\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)\r
-{\r
- uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;\r
- \r
- /* Check the parameters */\r
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));\r
- assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); \r
- assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));\r
- \r
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)\r
- {\r
- /* Compute the Corresponding IRQ Priority --------------------------------*/ \r
- tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;\r
- tmppre = (0x4 - tmppriority);\r
- tmpsub = tmpsub >> tmppriority;\r
-\r
- tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;\r
- tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;\r
- tmppriority = tmppriority << 0x04;\r
- \r
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;\r
- \r
- /* Enable the Selected IRQ Channels --------------------------------------*/\r
- NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
- else\r
- {\r
- /* Disable the Selected IRQ Channels -------------------------------------*/\r
- NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =\r
- (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Sets the vector table location and Offset.\r
- * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_VectTab_RAM\r
- * @arg NVIC_VectTab_FLASH\r
- * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100.\r
- * @retval None\r
- */\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)\r
-{ \r
- /* Check the parameters */\r
- assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));\r
- assert_param(IS_NVIC_OFFSET(Offset)); \r
- \r
- SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);\r
-}\r
-\r
-/**\r
- * @brief Selects the condition for the system to enter low power mode.\r
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.\r
- * This parameter can be one of the following values:\r
- * @arg NVIC_LP_SEVONPEND\r
- * @arg NVIC_LP_SLEEPDEEP\r
- * @arg NVIC_LP_SLEEPONEXIT\r
- * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.\r
- * @retval None\r
- */\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_NVIC_LP(LowPowerMode));\r
- assert_param(IS_FUNCTIONAL_STATE(NewState)); \r
- \r
- if (NewState != DISABLE)\r
- {\r
- SCB->SCR |= LowPowerMode;\r
- }\r
- else\r
- {\r
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);\r
- }\r
-}\r
-\r
-/**\r
- * @brief Configures the SysTick clock source.\r
- * @param SysTick_CLKSource: specifies the SysTick clock source.\r
- * This parameter can be one of the following values:\r
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.\r
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.\r
- * @retval None\r
- */\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)\r
-{\r
- /* Check the parameters */\r
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));\r
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)\r
- {\r
- SysTick->CTRL |= SysTick_CLKSource_HCLK;\r
- }\r
- else\r
- {\r
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;\r
- }\r
-}\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-\r
-/**\r
- ******************************************************************************\r
- * @file misc.h\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief This file contains all the functions prototypes for the miscellaneous\r
- * firmware library functions (add-on to CMSIS functions).\r
- ******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
-\r
-/* Define to prevent recursive inclusion -------------------------------------*/\r
-#ifndef __MISC_H\r
-#define __MISC_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-/* Includes ------------------------------------------------------------------*/\r
-#include "stm32f10x.h"\r
-\r
-/** @addtogroup STM32F10x_StdPeriph_Driver\r
- * @{\r
- */\r
-\r
-/** @addtogroup MISC\r
- * @{\r
- */\r
-\r
-/** @defgroup MISC_Exported_Types\r
- * @{\r
- */\r
-\r
-/** \r
- * @brief NVIC Init Structure definition \r
- */\r
-\r
-typedef struct\r
-{\r
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.\r
- This parameter can be a value of @ref IRQn_Type \r
- (For the complete STM32 Devices IRQ Channels list, please\r
- refer to stm32f10x.h file) */\r
-\r
- uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel\r
- specified in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified\r
- in NVIC_IRQChannel. This parameter can be a value\r
- between 0 and 15 as described in the table @ref NVIC_Priority_Table */\r
-\r
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel\r
- will be enabled or disabled. \r
- This parameter can be set either to ENABLE or DISABLE */ \r
-} NVIC_InitTypeDef;\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup NVIC_Priority_Table \r
- * @{\r
- */\r
-\r
-/**\r
-@code \r
- The table below gives the allowed values of the pre-emption priority and subpriority according\r
- to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function\r
- ============================================================================================================================\r
- NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description\r
- ============================================================================================================================\r
- NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority\r
- | | | 4 bits for subpriority\r
- ----------------------------------------------------------------------------------------------------------------------------\r
- NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority\r
- | | | 3 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority\r
- | | | 2 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority\r
- | | | 1 bits for subpriority\r
- ---------------------------------------------------------------------------------------------------------------------------- \r
- NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority\r
- | | | 0 bits for subpriority \r
- ============================================================================================================================\r
-@endcode\r
-*/\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Constants\r
- * @{\r
- */\r
-\r
-/** @defgroup Vector_Table_Base \r
- * @{\r
- */\r
-\r
-#define NVIC_VectTab_RAM ((uint32_t)0x20000000)\r
-#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)\r
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \\r
- ((VECTTAB) == NVIC_VectTab_FLASH))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup System_Low_Power \r
- * @{\r
- */\r
-\r
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)\r
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)\r
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)\r
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \\r
- ((LP) == NVIC_LP_SLEEPDEEP) || \\r
- ((LP) == NVIC_LP_SLEEPONEXIT))\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup Preemption_Priority_Group \r
- * @{\r
- */\r
-\r
-#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority\r
- 4 bits for subpriority */\r
-#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority\r
- 3 bits for subpriority */\r
-#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority\r
- 2 bits for subpriority */\r
-#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority\r
- 1 bits for subpriority */\r
-#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority\r
- 0 bits for subpriority */\r
-\r
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \\r
- ((GROUP) == NVIC_PriorityGroup_1) || \\r
- ((GROUP) == NVIC_PriorityGroup_2) || \\r
- ((GROUP) == NVIC_PriorityGroup_3) || \\r
- ((GROUP) == NVIC_PriorityGroup_4))\r
-\r
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)\r
-\r
-#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0007FFFF)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup SysTick_clock_source \r
- * @{\r
- */\r
-\r
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)\r
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)\r
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \\r
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @defgroup MISC_Exported_Functions\r
- * @{\r
- */\r
-\r
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);\r
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);\r
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);\r
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);\r
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __MISC_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
\r
-#\r
-# Copyright ArcCore AB\r
-#\r
+/*\r
+ * Copyright ArcCore AB\r
+ *\r
+ *\r
+ */\r
\r
#define _ASSEMBLER_\r
#include "kernel_offset.h"\r
mov.w r4,#LC_PATTERN\r
str r4,[sp,#C_CONTEXT_OFFS] \r
mov r0,sp // stack as first arg\r
+ \r
+// When at interrupt nest count = 0, load interrupt stack \r
+ ldr r4,=os_sys\r
+ ldr r5,[r4,#SYS_INT_NEST_CNT]\r
+ cmp r5, #0\r
+ bgt arggg\r
+ \r
+ ldr sp,[r4,#SYS_INT_STACK] \r
+ \r
+arggg: \r
bl Irq_Entry\r
mov sp, r0 // pop from returned stack\r
- b os_lc_restore\r
+\r
+ /* Do a normal exception return */\r
+ add.w sp,sp,#C_SIZE\r
+ pop {REG_SAVE,lr}\r
+ bx lr\r
+\r
+// b os_lc_restore\r
\r
\r
/**\r
*\r
* Don't really know what bits matter on the xPSR here. Not setting\r
* the EPSR[T] is really bad since it will generate a INVSTATE exception.\r
- *\r
- * @param r0 Pointer to PC to set\r
*/\r
.global Irq_EOI2\r
.type Irq_EOI2, %function\r
\r
Irq_EOI2:\r
mov.w r1,0x01000000 /* EPSR[T] bit */\r
+ mov r0,lr\r
push {r0,r1} /* Push PC and xPSR */\r
sub.w sp,sp,#(6*4) /* r0,r1,r2,r3, r12,lr,pc,xPSR */\r
- mov.w lr,#0xfffffff9 /* Return with MSR */\r
- bx lr\r
+ mov.w lr,#0xfffffff9 /* interrupt return with stack=MSR */\r
+ bx lr /* do return */\r
\r
\r
/**\r
bx lr\r
\r
\r
- /* Restore the large context. Cases:\r
- * - Directly from Irq_Handler()\r
- * (the preempted task got swapped in directly)\r
- * - The preempted task, got preemted by a task and\r
- * we have already returned from handler mode.\r
- */\r
-\r
+/* Restore the large context. Cases:\r
+ * 1. Directly from Irq_Handler()\r
+ * (the preempted task got swapped in directly)\r
+ * 2. The preempted task, got preemted by a task and\r
+ * we have already returned from handler mode.\r
+ *\r
+ * NOTE ! Only case 2 is covered here, case 1 is handled in Irq_Handler\r
+ * prologue\r
+ */\r
+ \r
os_lc_restore:\r
add.w sp,sp,#C_SIZE\r
+ /* Pop function stack (LR will be 0xffff_fff9 here, just ignore */\r
pop {REG_SAVE,lr}\r
\r
- /* The usual case is that we are in handler mode (=handling exceptions).\r
- * So, LR(=r14) should be 0xffff_fffx, and x in this case should return \r
- * to threaded mode (=not handling exeptions) 0b1001. (EXC_RETURN)\r
- */\r
- bx lr\r
+ /* If we were in handler mode a "bx lr" would pop back all the registers\r
+ * that were automatically pushed by the CPU. Now we have to do this \r
+ * manually instead. \r
+ * The problem here is PSR since its not a register that we can pop\r
+ * back so we have to do it manually, use r0 as scratch */\r
+ \r
+ /* Grab stack xPSR and move to psr */\r
+ /* TODO: Does this enable interrupts?? */\r
+ ldr r0,[sp,#28]\r
+ msr apsr,r0\r
+ \r
+ /* Update bit[0] of PC.\r
+ *\r
+ * From "3.3.1 STM32F10xxx Cortex-M3 programming manual"\r
+ * Bit[0] of any address written to the PC with a BX, BLX, LDM, LDR, or POP instruction must\r
+ * be 1 for correct execution, because this bit indicates the required instruction set, and the\r
+ * Cortex-M3 processor only supports thumb instructions. */\r
+ ldr r0,[sp,#24]\r
+ orr r0,r0,#1\r
+ str r0,[sp,#24]\r
+ \r
+ /* Pop part of the exception stack */\r
+ pop {r0-r3,r12,lr}\r
+ \r
+ add.w sp,sp,#(2*4) /* Adjust for xPSR and PC */\r
+ /* We do return directly to the preempted task here, so enable interrupts */\r
+ cpsie i /* Enable interrupts */\r
\r
+ /* Jump to PC from PC on stack (the branch value on the stack must be + 1 to\r
+ * stay in thumb mode) */\r
+ ldr pc,[sp,#-8]\r
\r
+ \r
\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#include "internal.h"\r
-#include "task_i.h"\r
-#include "hooks.h"\r
-#include "stm32f10x.h"\r
-#include "misc.h"\r
-#include "irq.h"\r
-#include "core_cm3.h"\r
-\r
-extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];\r
-\r
-void Irq_Init( void ) {\r
- NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);\r
-}\r
-\r
-void Irq_EOI( void ) {\r
- /* Note!\r
- * This is not applicable on the Cortex-M3 since we\r
- * can't terminate the interrupt request without popping\r
- * back registers..have to be solved in the context switches\r
- * themselves.\r
- */\r
-}\r
-\r
-#define ICSR_VECTACTIVE 0x1ff\r
-\r
-/**\r
- * Get Active ISR number field.\r
- * You can subtract 16 from the VECTACTIVE field to index into the Interrupt\r
- * Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority\r
- * Registers. INTISR[0] has vector number 16.\r
- *\r
- */\r
-static uint32_t NVIC_GetActiveVector( void) {\r
- return (SCB->ICSR & ICSR_VECTACTIVE);\r
-}\r
-\r
-/**\r
- *\r
- * @param stack_p Ptr to the current stack.\r
- *\r
- * The stack holds C, NVGPR, VGPR and the EXC frame.\r
- *\r
- */\r
-void *Irq_Entry( void *stack_p )\r
-{\r
- uint32_t vector = 0;\r
- uint32_t *stack;\r
-\r
- Irq_Disable();\r
- stack = (uint32_t *)stack_p;\r
-\r
- /* 0. Set the default handler here....\r
- * 1. Grab the vector from the interrupt controller\r
- * INT_CTRL_ST[VECTACTIVE]\r
- * 2. Irq_VectorTable[vector] is odd -> ISR1\r
- * Irq_VectorTable[vector] is even-> ISR2\r
- */\r
-\r
-\r
- vector = NVIC_GetActiveVector();\r
-\r
- stack = Os_Isr(stack, (void *)Irq_VectorTable[vector]);\r
- Irq_Enable();\r
- return stack;\r
-}\r
-\r
-/**\r
- * Attach an ISR type 1 to the interrupt controller.\r
- *\r
- * @param entry\r
- * @param int_ctrl\r
- * @param vector\r
- * @param prio\r
- */\r
-void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {\r
-\r
- // TODO: Use NVIC_Init here\r
- /*\r
- NVIC_InitTypeDef NVIC_InitStructure;\r
-\r
- // Enable and configure RCC global IRQ channel\r
- NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;\r
- NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;\r
- NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;\r
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;\r
- NVIC_Init(&NVIC_InitStructure);\r
- */\r
-}\r
-\r
-static inline int osPrioToCpuPio( uint8_t prio ) {\r
- assert(prio<32);\r
- return prio>>1;\r
-}\r
-\r
-\r
-/**\r
- * Attach a ISR type 2 to the interrupt controller.\r
- *\r
- * @param tid\r
- * @param int_ctrl\r
- * @param vector\r
- */\r
-void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {\r
- OsPcbType *pcb;\r
- NVIC_InitTypeDef irqInit;\r
-\r
- pcb = os_find_task(tid);\r
- Irq_VectorTable[vector+16] = (void *)pcb;\r
-\r
- irqInit.NVIC_IRQChannel = vector;\r
- irqInit.NVIC_IRQChannelPreemptionPriority = osPrioToCpuPio(pcb->prio);\r
- irqInit.NVIC_IRQChannelSubPriority = 0;\r
- irqInit.NVIC_IRQChannelCmd = ENABLE;\r
-\r
-\r
- // TODO: Same as for AttachIsr1\r
- NVIC_Init(&irqInit);\r
-}\r
-\r
-\r
-/**\r
- * Generates a soft interrupt, ie sets pending bit.\r
- * This could also be implemented using ISPR regs.\r
- *\r
- * @param vector\r
- */\r
-void Irq_GenerateSoftInt( IrqType vector ) {\r
-\r
- NVIC->STIR = (vector + 16);\r
-}\r
-\r
-/**\r
- * Get the current priority from the interrupt controller.\r
- * @param cpu\r
- * @return\r
- */\r
-uint8_t Irq_GetCurrentPriority( Cpu_t cpu) {\r
-\r
- uint8_t prio = 0;\r
-\r
- // SCB_ICSR contains the active vector\r
- return prio;\r
-}\r
-\r
-typedef struct {\r
- uint32_t dummy;\r
-} exc_stack_t;\r
-\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include "internal.h"
+#include "task_i.h"
+#include "hooks.h"
+#include "stm32f10x.h"
+#include "irq.h"
+#include "core_cm3.h"
+
+extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
+
+/*
+* PRIGROUP[2:0] Group prios Sub prios
+* 0b011 16 None
+* 0b100 8 2
+* 0b101 4 4
+* 0b110 2 8
+* 0b111 None 16
+*/
+#define AIRCR_VECTKEY ((uint32_t)0x05FA0000)
+
+/** Set NVIC prio group */
+static void NVIC_SetPrioGroup(uint32_t prioGroup)
+{
+ SCB->AIRCR = AIRCR_VECTKEY | (prioGroup<<8);
+}
+
+void Irq_Init( void ) {
+ NVIC_SetPrioGroup(3); // No sub prioritys
+}
+
+void Irq_EOI( void ) {
+ /* Note!
+ * This is not applicable on the Cortex-M3 since we
+ * can't terminate the interrupt request without popping
+ * back registers..have to be solved in the context switches
+ * themselves.
+ */
+}
+
+#define ICSR_VECTACTIVE 0x1ff
+
+/**
+ * Get Active ISR number field.
+ * You can subtract 16 from the VECTACTIVE field to index into the Interrupt
+ * Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority
+ * Registers. INTISR[0] has vector number 16.
+ *
+ */
+static uint32_t NVIC_GetActiveVector( void) {
+ return (SCB->ICSR & ICSR_VECTACTIVE);
+}
+
+/**
+ * Init NVIC vector. We do not use subriority
+ *
+ */
+
+/**
+ * Init NVIC vector. We do not use subpriority
+ *
+ * @param vector The IRQ number
+ * @param prio NVIC priority, 0-15, 0-high prio
+ */
+static void NVIC_InitVector(IRQn_Type vector, uint32_t prio)
+{
+ // Set prio
+ NVIC_SetPriority(vector,prio);
+ //NVIC->IP[vector] = prio;
+
+ // Enable
+ //NVIC_EnableIRQ(vector);
+ NVIC->ISER[vector >> 5] = (uint32_t)1 << (vector & (uint8_t)0x1F);
+}
+
+/**
+ *
+ * @param stack_p Ptr to the current stack.
+ *
+ * The stack holds C, NVGPR, VGPR and the EXC frame.
+ *
+ */
+void *Irq_Entry( void *stack_p )
+{
+ uint32_t vector = 0;
+ uint32_t *stack;
+
+ Irq_Disable();
+ stack = (uint32_t *)stack_p;
+
+ /* 0. Set the default handler here....
+ * 1. Grab the vector from the interrupt controller
+ * INT_CTRL_ST[VECTACTIVE]
+ * 2. Irq_VectorTable[vector] is odd -> ISR1
+ * Irq_VectorTable[vector] is even-> ISR2
+ */
+
+
+ vector = NVIC_GetActiveVector();
+
+ stack = Os_Isr(stack, (void *)Irq_VectorTable[vector]);
+ Irq_Enable();
+ return stack;
+}
+
+/**
+ * Attach an ISR type 1 to the interrupt controller.
+ *
+ * @param entry
+ * @param int_ctrl
+ * @param vector
+ * @param prio
+ */
+void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
+
+ // TODO: Use NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio)); here
+}
+
+/**
+ * NVIC prio have priority 0-15, 0-highest priority.
+ * Autosar does it the other way around, 0-Lowest priority
+ *
+ * Autosar NVIC
+ * 31 0
+ * 30 0
+ * ..
+ * 0 15
+ * 0 15
+ * @param prio
+ * @return
+ */
+static inline int osPrioToCpuPio( uint8_t prio ) {
+ assert(prio<32);
+ prio = 31 - prio;
+ return (prio>>1);
+}
+
+/**
+ * Attach a ISR type 2 to the interrupt controller.
+ *
+ * @param tid
+ * @param int_ctrl
+ * @param vector
+ */
+void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {
+ OsPcbType *pcb;
+
+ pcb = os_find_task(tid);
+ Irq_VectorTable[vector+16] = (void *)pcb;
+
+ NVIC_InitVector(vector, osPrioToCpuPio(pcb->prio));
+}
+
+
+/**
+ * Generates a soft interrupt, ie sets pending bit.
+ * This could also be implemented using ISPR regs.
+ *
+ * @param vector
+ */
+void Irq_GenerateSoftInt( IrqType vector ) {
+
+ NVIC->STIR = (vector);
+}
+
+/**
+ * Get the current priority from the interrupt controller.
+ * @param cpu
+ * @return
+ */
+uint8_t Irq_GetCurrentPriority( Cpu_t cpu) {
+
+ uint8_t prio = 0;
+
+ // SCB_ICSR contains the active vector
+ return prio;
+}
+
+typedef struct {
+ uint32_t dummy;
+} exc_stack_t;
+
+
#error No device selected\r
#endif\r
\r
+\r
+typedef enum {\r
+ PERIPHERAL_CLOCK_AHB,\r
+ PERIPHERAL_CLOCK_APB1,\r
+ PERIPHERAL_CLOCK_APB2,\r
+} McuE_PeriperalClock_t;\r
+\r
+\r
typedef enum {\r
CPU_0=0,\r
} Cpu_t;\r
*\r
* Misc\r
* r9 - Platform specific ???\r
- * r12 - IP\r
+ * r12 - IP (Intra Procedure call)\r
* r13 - SP\r
* r14 - LR\r
* r15 - PC\r
*\r
+ * See "Procedure Call Standard for the ARM® Architecture" for more information.\r
+ *\r
* Other:\r
* PSR\r
* PRIMASK[0] 0 - No effect,\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+ \r
+ .syntax unified\r
+ .cpu cortex-m3\r
+ .fpu softvfp\r
+ .thumb\r
+\r
+.global g_pfnVectors\r
+.global Default_Handler\r
+\r
+.word _sidata\r
+.word _sdata\r
+.word _edata\r
+.word _sbss\r
+.word _ebss\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor first\r
+ * starts execution following a reset event. Only the absolutely\r
+ * necessary set is performed, after which the application\r
+ * supplied main() routine is called. \r
+ * @param None\r
+ * @retval : None\r
+*/\r
+ .section .text.Reset_Handler\r
+ .weak Reset_Handler\r
+ .type Reset_Handler, %function\r
+Reset_Handler: \r
+\r
+/* Copy the data segment initializers from flash to SRAM */ \r
+ movs r1, #0\r
+ b LoopCopyDataInit\r
+\r
+CopyDataInit:\r
+ ldr r3, =_sidata\r
+ ldr r3, [r3, r1]\r
+ str r3, [r0, r1]\r
+ adds r1, r1, #4\r
+ \r
+LoopCopyDataInit:\r
+ ldr r0, =_sdata\r
+ ldr r3, =_edata\r
+ adds r2, r0, r1\r
+ cmp r2, r3\r
+ bcc CopyDataInit\r
+ ldr r2, =_sbss\r
+ b LoopFillZerobss\r
+/* Zero fill the bss segment. */ \r
+FillZerobss:\r
+ movs r3, #0\r
+ str r3, [r2], #4\r
+ \r
+LoopFillZerobss:\r
+ ldr r3, = _ebss\r
+ cmp r2, r3\r
+ bcc FillZerobss\r
+/* Call the application's entry point.*/\r
+ bl main\r
+ bx lr \r
+.size Reset_Handler, .-Reset_Handler\r
+\r
+/**\r
+ * @brief This is the code that gets called when the processor receives an \r
+ * unexpected interrupt. This simply enters an infinite loop, preserving\r
+ * the system state for examination by a debugger.\r
+ *\r
+ * @param None \r
+ * @retval : None \r
+*/\r
+ .section .text.Default_Handler,"ax",%progbits\r
+Default_Handler:\r
+Infinite_Loop:\r
+ b Infinite_Loop\r
+ .size Default_Handler, .-Default_Handler\r
+/******************************************************************************\r
+* Vector table for a Cortex M3. Vectors start at addr 0x0.\r
+******************************************************************************/ \r
+ .section .isr_vector,"a",%progbits\r
+ .type g_pfnVectors, %object\r
+ .size g_pfnVectors, .-g_pfnVectors\r
+\r
+ .extern Irq_Handler\r
+\r
+ .word _estack\r
+ .word Reset_Handler\r
+ .word NMI_Handler\r
+ .word HardFault_Handler\r
+ .word MemManage_Handler\r
+ .word BusFault_Handler\r
+ .word UsageFault_Handler\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word 0\r
+ .word SVC_Handler\r
+ .word DebugMon_Handler\r
+ .word 0\r
+ .word PendSV_Handler\r
+ .word Irq_Handler+1 /* SysTick */\r
+ .rept 83\r
+ .word Irq_Handler+1\r
+ .endr\r
+ \r
+ .weak NMI_Handler\r
+ .thumb_set NMI_Handler,Default_Handler\r
+\r
+ .weak HardFault_Handler\r
+ .thumb_set HardFault_Handler,Default_Handler\r
+\r
+ .weak MemManage_Handler\r
+ .thumb_set MemManage_Handler,Default_Handler\r
+\r
+ .weak BusFault_Handler\r
+ .thumb_set BusFault_Handler,Default_Handler\r
+\r
+ .weak UsageFault_Handler\r
+ .thumb_set UsageFault_Handler,Default_Handler\r
+\r
+ .weak SVC_Handler\r
+ .thumb_set SVC_Handler,Default_Handler\r
+\r
+ .weak DebugMon_Handler\r
+ .thumb_set DebugMon_Handler,Default_Handler\r
+\r
+ .weak PendSV_Handler\r
+ .thumb_set PendSV_Handler,Default_Handler\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_cl.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Connectivity line Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR \r
- * address.\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF1E0F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
-#if 1\r
-\r
- .extern Irq_Handler\r
-\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word Irq_Handler+1 /* SysTick */\r
- .rept 83\r
- .word Irq_Handler+1\r
- .endr\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-#else\r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word CAN1_TX_IRQHandler\r
- .word CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word OTG_FS_WKUP_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word TIM5_IRQHandler \r
- .word SPI3_IRQHandler \r
- .word UART4_IRQHandler \r
- .word UART5_IRQHandler \r
- .word TIM6_IRQHandler \r
- .word TIM7_IRQHandler \r
- .word DMA2_Channel1_IRQHandler \r
- .word DMA2_Channel2_IRQHandler \r
- .word DMA2_Channel3_IRQHandler \r
- .word DMA2_Channel4_IRQHandler \r
- .word DMA2_Channel5_IRQHandler \r
- .word ETH_IRQHandler \r
- .word ETH_WKUP_IRQHandler \r
- .word CAN2_TX_IRQHandler \r
- .word CAN2_RX0_IRQHandler \r
- .word CAN2_RX1_IRQHandler \r
- .word CAN2_SCE_IRQHandler \r
- .word OTG_FS_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0 \r
- .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
- STM32F10x Connectivity line Devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_TX_IRQHandler\r
- .thumb_set CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX0_IRQHandler\r
- .thumb_set CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak OTG_FS_WKUP_IRQHandler\r
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak TIM5_IRQHandler\r
- .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
- .weak SPI3_IRQHandler \r
- .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
- .weak UART4_IRQHandler \r
- .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
- .weak UART5_IRQHandler \r
- .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler \r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler \r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel1_IRQHandler \r
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel2_IRQHandler \r
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel3_IRQHandler \r
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel4_IRQHandler \r
- .thumb_set DMA2_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel5_IRQHandler \r
- .thumb_set DMA2_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak ETH_IRQHandler \r
- .thumb_set ETH_IRQHandler,Default_Handler\r
-\r
- .weak ETH_WKUP_IRQHandler \r
- .thumb_set ETH_WKUP_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_TX_IRQHandler \r
- .thumb_set CAN2_TX_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_RX0_IRQHandler \r
- .thumb_set CAN2_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_RX1_IRQHandler \r
- .thumb_set CAN2_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN2_SCE_IRQHandler \r
- .thumb_set CAN2_SCE_IRQHandler,Default_Handler\r
-\r
- .weak OTG_FS_IRQHandler \r
- .thumb_set OTG_FS_IRQHandler ,Default_Handler\r
-#endif\r
- \r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_hd.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x High Density Devices vector table for RIDE7 toolchain. \r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address,\r
- * - Configure external SRAM mounted on STM3210E-EVAL board\r
- * to be used as data memory (optional, to be enabled by user)\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\r
-\r
-.equ Initial_spTop, 0x20000400 \r
-.equ BootRAM, 0xF1E0F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
- required, then adjust the Register Addresses */\r
- bl SystemInit_ExtMemCtl\r
-/* restore original stack pointer */ \r
- LDR r0, =_estack\r
- MSR msp, r0\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief Dummy SystemInit_ExtMemCtl function \r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits\r
-SystemInit_ExtMemCtl_Dummy:\r
- bx lr\r
- .size SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word Initial_spTop\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler\r
- .word TIM8_BRK_IRQHandler\r
- .word TIM8_UP_IRQHandler\r
- .word TIM8_TRG_COM_IRQHandler\r
- .word TIM8_CC_IRQHandler\r
- .word ADC3_IRQHandler\r
- .word FSMC_IRQHandler\r
- .word SDIO_IRQHandler\r
- .word TIM5_IRQHandler\r
- .word SPI3_IRQHandler\r
- .word UART4_IRQHandler\r
- .word UART5_IRQHandler\r
- .word TIM6_IRQHandler\r
- .word TIM7_IRQHandler\r
- .word DMA2_Channel1_IRQHandler\r
- .word DMA2_Channel2_IRQHandler\r
- .word DMA2_Channel3_IRQHandler\r
- .word DMA2_Channel4_5_IRQHandler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x1E0. This is for boot in RAM mode for \r
- STM32F10x High Density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_BRK_IRQHandler\r
- .thumb_set TIM8_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_UP_IRQHandler\r
- .thumb_set TIM8_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_TRG_COM_IRQHandler\r
- .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM8_CC_IRQHandler\r
- .thumb_set TIM8_CC_IRQHandler,Default_Handler\r
-\r
- .weak ADC3_IRQHandler\r
- .thumb_set ADC3_IRQHandler,Default_Handler\r
-\r
- .weak FSMC_IRQHandler\r
- .thumb_set FSMC_IRQHandler,Default_Handler\r
-\r
- .weak SDIO_IRQHandler\r
- .thumb_set SDIO_IRQHandler,Default_Handler\r
-\r
- .weak TIM5_IRQHandler\r
- .thumb_set TIM5_IRQHandler,Default_Handler\r
-\r
- .weak SPI3_IRQHandler\r
- .thumb_set SPI3_IRQHandler,Default_Handler\r
-\r
- .weak UART4_IRQHandler\r
- .thumb_set UART4_IRQHandler,Default_Handler\r
-\r
- .weak UART5_IRQHandler\r
- .thumb_set UART5_IRQHandler,Default_Handler\r
-\r
- .weak TIM6_IRQHandler\r
- .thumb_set TIM6_IRQHandler,Default_Handler\r
-\r
- .weak TIM7_IRQHandler\r
- .thumb_set TIM7_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel1_IRQHandler\r
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel2_IRQHandler\r
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel3_IRQHandler\r
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA2_Channel4_5_IRQHandler\r
- .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler\r
-\r
- .weak SystemInit_ExtMemCtl\r
- .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy\r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_ld.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Low Density Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address.\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
- \r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- 0\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- 0\r
- 0\r
- .word SPI1_IRQHandler\r
- 0\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- 0\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32F10x Low Density devices.*/\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler \r
-\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file startup_stm32f10x_md.s\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.\r
- * This module performs:\r
- * - Set the initial SP\r
- * - Set the initial PC == Reset_Handler,\r
- * - Set the vector table entries with the exceptions ISR address\r
- * - Branches to main in the C library (which eventually\r
- * calls main()).\r
- * After Reset the Cortex-M3 processor is in Thread mode,\r
- * priority is Privileged, and the Stack is set to Main.\r
- *******************************************************************************\r
- * @copy\r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- */ \r
- \r
- .syntax unified\r
- .cpu cortex-m3\r
- .fpu softvfp\r
- .thumb\r
-\r
-.global g_pfnVectors\r
-.global SystemInit_ExtMemCtl_Dummy\r
-.global Default_Handler\r
-\r
-/* start address for the initialization values of the .data section. \r
-defined in linker script */\r
-.word _sidata\r
-/* start address for the .data section. defined in linker script */ \r
-.word _sdata\r
-/* end address for the .data section. defined in linker script */\r
-.word _edata\r
-/* start address for the .bss section. defined in linker script */\r
-.word _sbss\r
-/* end address for the .bss section. defined in linker script */\r
-.word _ebss\r
-\r
-.equ BootRAM, 0xF108F85F\r
-/**\r
- * @brief This is the code that gets called when the processor first\r
- * starts execution following a reset event. Only the absolutely\r
- * necessary set is performed, after which the application\r
- * supplied main() routine is called. \r
- * @param None\r
- * @retval : None\r
-*/\r
-\r
- .section .text.Reset_Handler\r
- .weak Reset_Handler\r
- .type Reset_Handler, %function\r
-Reset_Handler: \r
-\r
-/* Copy the data segment initializers from flash to SRAM */ \r
- movs r1, #0\r
- b LoopCopyDataInit\r
-\r
-CopyDataInit:\r
- ldr r3, =_sidata\r
- ldr r3, [r3, r1]\r
- str r3, [r0, r1]\r
- adds r1, r1, #4\r
- \r
-LoopCopyDataInit:\r
- ldr r0, =_sdata\r
- ldr r3, =_edata\r
- adds r2, r0, r1\r
- cmp r2, r3\r
- bcc CopyDataInit\r
- ldr r2, =_sbss\r
- b LoopFillZerobss\r
-/* Zero fill the bss segment. */ \r
-FillZerobss:\r
- movs r3, #0\r
- str r3, [r2], #4\r
- \r
-LoopFillZerobss:\r
- ldr r3, = _ebss\r
- cmp r2, r3\r
- bcc FillZerobss\r
-/* Call the application's entry point.*/\r
- bl main\r
- bx lr \r
-.size Reset_Handler, .-Reset_Handler\r
-\r
-/**\r
- * @brief This is the code that gets called when the processor receives an \r
- * unexpected interrupt. This simply enters an infinite loop, preserving\r
- * the system state for examination by a debugger.\r
- *\r
- * @param None \r
- * @retval : None \r
-*/\r
- .section .text.Default_Handler,"ax",%progbits\r
-Default_Handler:\r
-Infinite_Loop:\r
- b Infinite_Loop\r
- .size Default_Handler, .-Default_Handler\r
-/******************************************************************************\r
-*\r
-* The minimal vector table for a Cortex M3. Note that the proper constructs\r
-* must be placed on this to ensure that it ends up at physical address\r
-* 0x0000.0000.\r
-*\r
-******************************************************************************/ \r
- .section .isr_vector,"a",%progbits\r
- .type g_pfnVectors, %object\r
- .size g_pfnVectors, .-g_pfnVectors\r
- \r
-#if 1\r
-\r
- .extern Irq_Handler\r
-\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word Irq_Handler+1 /* SysTick */\r
- .rept 83\r
- .word Irq_Handler+1\r
- .endr\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
-\r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
-\r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
-\r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
-\r
-#else\r
-g_pfnVectors:\r
- .word _estack\r
- .word Reset_Handler\r
- .word NMI_Handler\r
- .word HardFault_Handler\r
- .word MemManage_Handler\r
- .word BusFault_Handler\r
- .word UsageFault_Handler\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word SVC_Handler\r
- .word DebugMon_Handler\r
- .word 0\r
- .word PendSV_Handler\r
- .word SysTick_Handler\r
- .word WWDG_IRQHandler\r
- .word PVD_IRQHandler\r
- .word TAMPER_IRQHandler\r
- .word RTC_IRQHandler\r
- .word FLASH_IRQHandler\r
- .word RCC_IRQHandler\r
- .word EXTI0_IRQHandler\r
- .word EXTI1_IRQHandler\r
- .word EXTI2_IRQHandler\r
- .word EXTI3_IRQHandler\r
- .word EXTI4_IRQHandler\r
- .word DMA1_Channel1_IRQHandler\r
- .word DMA1_Channel2_IRQHandler\r
- .word DMA1_Channel3_IRQHandler\r
- .word DMA1_Channel4_IRQHandler\r
- .word DMA1_Channel5_IRQHandler\r
- .word DMA1_Channel6_IRQHandler\r
- .word DMA1_Channel7_IRQHandler\r
- .word ADC1_2_IRQHandler\r
- .word USB_HP_CAN1_TX_IRQHandler\r
- .word USB_LP_CAN1_RX0_IRQHandler\r
- .word CAN1_RX1_IRQHandler\r
- .word CAN1_SCE_IRQHandler\r
- .word EXTI9_5_IRQHandler\r
- .word TIM1_BRK_IRQHandler\r
- .word TIM1_UP_IRQHandler\r
- .word TIM1_TRG_COM_IRQHandler\r
- .word TIM1_CC_IRQHandler\r
- .word TIM2_IRQHandler\r
- .word TIM3_IRQHandler\r
- .word TIM4_IRQHandler\r
- .word I2C1_EV_IRQHandler\r
- .word I2C1_ER_IRQHandler\r
- .word I2C2_EV_IRQHandler\r
- .word I2C2_ER_IRQHandler\r
- .word SPI1_IRQHandler\r
- .word SPI2_IRQHandler\r
- .word USART1_IRQHandler\r
- .word USART2_IRQHandler\r
- .word USART3_IRQHandler\r
- .word EXTI15_10_IRQHandler\r
- .word RTCAlarm_IRQHandler\r
- .word USBWakeUp_IRQHandler \r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word 0\r
- .word BootRAM /* @0x108. This is for boot in RAM mode for \r
- STM32F10x Medium Density devices. */\r
- \r
-/*******************************************************************************\r
-*\r
-* Provide weak aliases for each Exception handler to the Default_Handler. \r
-* As they are weak aliases, any function with the same name will override \r
-* this definition.\r
-*\r
-*******************************************************************************/\r
- \r
- .weak NMI_Handler\r
- .thumb_set NMI_Handler,Default_Handler\r
- \r
- .weak HardFault_Handler\r
- .thumb_set HardFault_Handler,Default_Handler\r
- \r
- .weak MemManage_Handler\r
- .thumb_set MemManage_Handler,Default_Handler\r
- \r
- .weak BusFault_Handler\r
- .thumb_set BusFault_Handler,Default_Handler\r
-\r
- .weak UsageFault_Handler\r
- .thumb_set UsageFault_Handler,Default_Handler\r
-\r
- .weak SVC_Handler\r
- .thumb_set SVC_Handler,Default_Handler\r
-\r
- .weak DebugMon_Handler\r
- .thumb_set DebugMon_Handler,Default_Handler\r
-\r
- .weak PendSV_Handler\r
- .thumb_set PendSV_Handler,Default_Handler\r
-\r
- .weak SysTick_Handler\r
- .thumb_set SysTick_Handler,Default_Handler\r
-\r
- .weak WWDG_IRQHandler\r
- .thumb_set WWDG_IRQHandler,Default_Handler\r
-\r
- .weak PVD_IRQHandler\r
- .thumb_set PVD_IRQHandler,Default_Handler\r
-\r
- .weak TAMPER_IRQHandler\r
- .thumb_set TAMPER_IRQHandler,Default_Handler\r
-\r
- .weak RTC_IRQHandler\r
- .thumb_set RTC_IRQHandler,Default_Handler\r
-\r
- .weak FLASH_IRQHandler\r
- .thumb_set FLASH_IRQHandler,Default_Handler\r
-\r
- .weak RCC_IRQHandler\r
- .thumb_set RCC_IRQHandler,Default_Handler\r
-\r
- .weak EXTI0_IRQHandler\r
- .thumb_set EXTI0_IRQHandler,Default_Handler\r
-\r
- .weak EXTI1_IRQHandler\r
- .thumb_set EXTI1_IRQHandler,Default_Handler\r
-\r
- .weak EXTI2_IRQHandler\r
- .thumb_set EXTI2_IRQHandler,Default_Handler\r
-\r
- .weak EXTI3_IRQHandler\r
- .thumb_set EXTI3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI4_IRQHandler\r
- .thumb_set EXTI4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel1_IRQHandler\r
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel2_IRQHandler\r
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel3_IRQHandler\r
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel4_IRQHandler\r
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel5_IRQHandler\r
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel6_IRQHandler\r
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler\r
-\r
- .weak DMA1_Channel7_IRQHandler\r
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler\r
-\r
- .weak ADC1_2_IRQHandler\r
- .thumb_set ADC1_2_IRQHandler,Default_Handler\r
-\r
- .weak USB_HP_CAN1_TX_IRQHandler\r
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler\r
-\r
- .weak USB_LP_CAN1_RX0_IRQHandler\r
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_RX1_IRQHandler\r
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler\r
-\r
- .weak CAN1_SCE_IRQHandler\r
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler\r
-\r
- .weak EXTI9_5_IRQHandler\r
- .thumb_set EXTI9_5_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_BRK_IRQHandler\r
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_UP_IRQHandler\r
- .thumb_set TIM1_UP_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_TRG_COM_IRQHandler\r
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler\r
-\r
- .weak TIM1_CC_IRQHandler\r
- .thumb_set TIM1_CC_IRQHandler,Default_Handler\r
-\r
- .weak TIM2_IRQHandler\r
- .thumb_set TIM2_IRQHandler,Default_Handler\r
-\r
- .weak TIM3_IRQHandler\r
- .thumb_set TIM3_IRQHandler,Default_Handler\r
-\r
- .weak TIM4_IRQHandler\r
- .thumb_set TIM4_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_EV_IRQHandler\r
- .thumb_set I2C1_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C1_ER_IRQHandler\r
- .thumb_set I2C1_ER_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_EV_IRQHandler\r
- .thumb_set I2C2_EV_IRQHandler,Default_Handler\r
-\r
- .weak I2C2_ER_IRQHandler\r
- .thumb_set I2C2_ER_IRQHandler,Default_Handler\r
-\r
- .weak SPI1_IRQHandler\r
- .thumb_set SPI1_IRQHandler,Default_Handler\r
-\r
- .weak SPI2_IRQHandler\r
- .thumb_set SPI2_IRQHandler,Default_Handler\r
-\r
- .weak USART1_IRQHandler\r
- .thumb_set USART1_IRQHandler,Default_Handler\r
-\r
- .weak USART2_IRQHandler\r
- .thumb_set USART2_IRQHandler,Default_Handler\r
-\r
- .weak USART3_IRQHandler\r
- .thumb_set USART3_IRQHandler,Default_Handler\r
-\r
- .weak EXTI15_10_IRQHandler\r
- .thumb_set EXTI15_10_IRQHandler,Default_Handler\r
-\r
- .weak RTCAlarm_IRQHandler\r
- .thumb_set RTCAlarm_IRQHandler,Default_Handler\r
-\r
- .weak USBWakeUp_IRQHandler\r
- .thumb_set USBWakeUp_IRQHandler,Default_Handler\r
-\r
-#endif\r
* @return\r
*/\r
\r
-uint32_t Os_SysTickGetTimeElapsed( void )\r
+uint32_t Os_SysTickGetValue( void )\r
{\r
- return (SysTick->VAL);\r
+ return (SysTick->LOAD) - (SysTick->VAL);\r
}\r
+\r
+\r
+TickType Os_SysTickGetElapsedValue( uint32_t preValue ) {\r
+ uint32_t curr;\r
+ uint32_t max;\r
+\r
+ curr = (SysTick->VAL);\r
+ max = (SysTick->LOAD);\r
+ return Os_CounterDiff((max - curr),preValue,max);\r
+}\r
+\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file system_stm32f10x.c\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\r
- ****************************************************************************** \r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x_system\r
- * @{\r
- */ \r
- \r
-/** @addtogroup STM32F10x_System_Private_Includes\r
- * @{\r
- */\r
-\r
-#include "stm32f10x.h"\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_TypesDefinitions\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Defines\r
- * @{\r
- */\r
-\r
-/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)\r
- frequency (after reset the HSI is used as SYSCLK source)\r
- \r
- IMPORTANT NOTE:\r
- ============== \r
- 1. After each device reset the HSI is used as System clock source.\r
-\r
- 2. Please make sure that the selected System clock doesn't exceed your device's\r
- maximum frequency.\r
- \r
- 3. If none of the define below is enabled, the HSI is used as System clock\r
- source.\r
-\r
- 4. The System clock configuration functions provided within this file assume that:\r
- - For Low, Medium and High density devices an external 8MHz crystal is\r
- used to drive the System clock.\r
- - For Connectivity line devices an external 25MHz crystal is used to drive\r
- the System clock.\r
- If you are using different crystal you have to adapt those functions accordingly.\r
- */\r
- \r
-/* #define SYSCLK_FREQ_HSE HSE_Value */\r
-/* #define SYSCLK_FREQ_24MHz 24000000 */\r
-/* #define SYSCLK_FREQ_36MHz 36000000 */\r
-/* #define SYSCLK_FREQ_48MHz 48000000 */\r
-/* #define SYSCLK_FREQ_56MHz 56000000 */\r
-#define SYSCLK_FREQ_72MHz 72000000\r
-\r
-/*!< Uncomment the following line if you need to use external SRAM mounted\r
- on STM3210E-EVAL board (STM32 High density devices) as data memory */ \r
-#ifdef STM32F10X_HD\r
-/* #define DATA_IN_ExtSRAM */\r
-#endif /* STM32F10X_HD */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Variables\r
- * @{\r
- */\r
-\r
-/*******************************************************************************\r
-* Clock Definitions\r
-*******************************************************************************/\r
-#ifdef SYSCLK_FREQ_HSE\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_HSE; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_HSE; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_HSE; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_24MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_24MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_24MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_24MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_36MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_36MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_36MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_36MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_48MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_48MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_48MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_48MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_48MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#elif defined SYSCLK_FREQ_56MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_56MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_56MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_56MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_56MHz; /*!< APB Peripheral bus 2 (high) speed */ \r
-#elif defined SYSCLK_FREQ_72MHz\r
- const uint32_t SystemFrequency = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = SYSCLK_FREQ_72MHz; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = SYSCLK_FREQ_72MHz; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = (SYSCLK_FREQ_72MHz/2); /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = SYSCLK_FREQ_72MHz; /*!< APB Peripheral bus 2 (high) speed */\r
-#else /*!< HSI Selected as System Clock source */\r
- const uint32_t SystemFrequency = HSI_Value; /*!< System Clock Frequency (Core Clock) */\r
- const uint32_t SystemFrequency_SysClk = HSI_Value; /*!< System clock */\r
- const uint32_t SystemFrequency_AHBClk = HSI_Value; /*!< AHB System bus speed */\r
- const uint32_t SystemFrequency_APB1Clk = HSI_Value; /*!< APB Peripheral bus 1 (low) speed */\r
- const uint32_t SystemFrequency_APB2Clk = HSI_Value; /*!< APB Peripheral bus 2 (high) speed */\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_FunctionPrototypes\r
- * @{\r
- */\r
-\r
-static void SetSysClock(void);\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
- static void SetSysClockToHSE(void);\r
-#elif defined SYSCLK_FREQ_24MHz\r
- static void SetSysClockTo24(void);\r
-#elif defined SYSCLK_FREQ_36MHz\r
- static void SetSysClockTo36(void);\r
-#elif defined SYSCLK_FREQ_48MHz\r
- static void SetSysClockTo48(void);\r
-#elif defined SYSCLK_FREQ_56MHz\r
- static void SetSysClockTo56(void); \r
-#elif defined SYSCLK_FREQ_72MHz\r
- static void SetSysClockTo72(void);\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Private_Functions\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Setup the microcontroller system\r
- * Initialize the Embedded Flash Interface, the PLL and update the SystemFrequency variable.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-void SystemInit (void)\r
-{\r
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */\r
- /* Set HSION bit */\r
- RCC->CR |= (uint32_t)0x00000001;\r
-\r
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */\r
-#ifndef STM32F10X_CL\r
- RCC->CFGR &= (uint32_t)0xF8FF0000;\r
-#else\r
- RCC->CFGR &= (uint32_t)0xF0FF0000;\r
-#endif /* STM32F10X_CL */ \r
- \r
- /* Reset HSEON, CSSON and PLLON bits */\r
- RCC->CR &= (uint32_t)0xFEF6FFFF;\r
-\r
- /* Reset HSEBYP bit */\r
- RCC->CR &= (uint32_t)0xFFFBFFFF;\r
-\r
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */\r
- RCC->CFGR &= (uint32_t)0xFF80FFFF;\r
-\r
-#ifndef STM32F10X_CL\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x009F0000;\r
-#else\r
- /* Reset PLL2ON and PLL3ON bits */\r
- RCC->CR &= (uint32_t)0xEBFFFFFF;\r
-\r
- /* Disable all interrupts and clear pending bits */\r
- RCC->CIR = 0x00FF0000;\r
-\r
- /* Reset CFGR2 register */\r
- RCC->CFGR2 = 0x00000000;\r
-#endif /* STM32F10X_CL */\r
- \r
- /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */\r
- /* Configure the Flash Latency cycles and enable prefetch buffer */\r
- SetSysClock();\r
-\r
-}\r
-\r
-/**\r
- * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClock(void)\r
-{\r
-#if !defined(CFG_SIMULATOR)\r
-#ifdef SYSCLK_FREQ_HSE\r
- SetSysClockToHSE();\r
-#elif defined SYSCLK_FREQ_24MHz\r
- SetSysClockTo24();\r
-#elif defined SYSCLK_FREQ_36MHz\r
- SetSysClockTo36();\r
-#elif defined SYSCLK_FREQ_48MHz\r
- SetSysClockTo48();\r
-#elif defined SYSCLK_FREQ_56MHz\r
- SetSysClockTo56(); \r
-#elif defined SYSCLK_FREQ_72MHz\r
- SetSysClockTo72();\r
-#endif\r
-#endif\r
- \r
- /* If none of the define above is enabled, the HSI is used as System clock\r
- source (default after reset) */ \r
-}\r
-\r
-/**\r
- * @brief Setup the external memory controller. Called in startup_stm32f10x.s \r
- * before jump to __main\r
- * @param None\r
- * @retval None\r
- */ \r
-#ifdef DATA_IN_ExtSRAM\r
-/**\r
- * @brief Setup the external memory controller. \r
- * Called in startup_stm32f10x_xx.s/.c before jump to main.\r
- * This function configures the external SRAM mounted on STM3210E-EVAL\r
- * board (STM32 High density devices). This SRAM will be used as program\r
- * data memory (including heap and stack).\r
- * @param None\r
- * @retval None\r
- */ \r
-void SystemInit_ExtMemCtl(void) \r
-{\r
-/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \r
- required, then adjust the Register Addresses */\r
-\r
- /* Enable FSMC clock */\r
- RCC->AHBENR = 0x00000114;\r
- \r
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ \r
- RCC->APB2ENR = 0x000001E0;\r
- \r
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/\r
-/*---------------- SRAM Address lines configuration -------------------------*/\r
-/*---------------- NOE and NWE configuration --------------------------------*/ \r
-/*---------------- NE3 configuration ----------------------------------------*/\r
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/\r
- \r
- GPIOD->CRL = 0x44BB44BB; \r
- GPIOD->CRH = 0xBBBBBBBB;\r
-\r
- GPIOE->CRL = 0xB44444BB; \r
- GPIOE->CRH = 0xBBBBBBBB;\r
-\r
- GPIOF->CRL = 0x44BBBBBB; \r
- GPIOF->CRH = 0xBBBB4444;\r
-\r
- GPIOG->CRL = 0x44BBBBBB; \r
- GPIOG->CRH = 0x44444B44;\r
- \r
-/*---------------- FSMC Configuration ---------------------------------------*/ \r
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/\r
- \r
- FSMC_Bank1->BTCR[4] = 0x00001011;\r
- FSMC_Bank1->BTCR[5] = 0x00000200;\r
-}\r
-#endif /* DATA_IN_ExtSRAM */\r
-\r
-#ifdef SYSCLK_FREQ_HSE\r
-/**\r
- * @brief Selects HSE as System clock source and configure HCLK, PCLK2\r
- * and PCLK1 prescalers.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockToHSE(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
-\r
-#ifndef STM32F10X_CL\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
-#else\r
- if (HSE_Value <= 24000000)\r
- {\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;\r
- }\r
- else\r
- {\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;\r
- }\r
-#endif /* STM32F10X_CL */\r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
- /* Select HSE as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; \r
-\r
- /* Wait till HSE is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_24MHz\r
-/**\r
- * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers.\r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo24(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 0 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL6); \r
-\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- } \r
-#else \r
- /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_36MHz\r
-/**\r
- * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo36(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL9); \r
-\r
- /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
-#else \r
- /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-#elif defined SYSCLK_FREQ_48MHz\r
-/**\r
- * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo48(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
- \r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL6); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_56MHz\r
-/**\r
- * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo56(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 1 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; \r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL7); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);\r
-\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
-\r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- } \r
-}\r
-\r
-#elif defined SYSCLK_FREQ_72MHz\r
-/**\r
- * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 \r
- * and PCLK1 prescalers. \r
- * @note This function should be used only after reset.\r
- * @param None\r
- * @retval None\r
- */\r
-static void SetSysClockTo72(void)\r
-{\r
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;\r
- \r
- /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ \r
- /* Enable HSE */ \r
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);\r
- \r
- /* Wait till HSE is ready and if Time out is reached exit */\r
- do\r
- {\r
- HSEStatus = RCC->CR & RCC_CR_HSERDY;\r
- StartUpCounter++; \r
- } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut));\r
-\r
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)\r
- {\r
- HSEStatus = (uint32_t)0x01;\r
- }\r
- else\r
- {\r
- HSEStatus = (uint32_t)0x00;\r
- } \r
-\r
- if (HSEStatus == (uint32_t)0x01)\r
- {\r
- /* Enable Prefetch Buffer */\r
- FLASH->ACR |= FLASH_ACR_PRFTBE;\r
-\r
- /* Flash 2 wait state */\r
- FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);\r
- FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; \r
-\r
- \r
- /* HCLK = SYSCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;\r
- \r
- /* PCLK2 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;\r
- \r
- /* PCLK1 = HCLK */\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;\r
-\r
-#ifdef STM32F10X_CL\r
- /* Configure PLLs ------------------------------------------------------*/\r
- /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */\r
- /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */\r
- \r
- RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |\r
- RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);\r
- RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |\r
- RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);\r
- \r
- /* Enable PLL2 */\r
- RCC->CR |= RCC_CR_PLL2ON;\r
- /* Wait till PLL2 is ready */\r
- while((RCC->CR & RCC_CR_PLL2RDY) == 0)\r
- {\r
- }\r
- \r
- \r
- /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ \r
- RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | \r
- RCC_CFGR_PLLMULL9); \r
-#else \r
- /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |\r
- RCC_CFGR_PLLMULL));\r
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);\r
-#endif /* STM32F10X_CL */\r
-\r
- /* Enable PLL */\r
- RCC->CR |= RCC_CR_PLLON;\r
-\r
-\r
- /* Wait till PLL is ready */\r
- while((RCC->CR & RCC_CR_PLLRDY) == 0)\r
- {\r
- }\r
- \r
- /* Select PLL as system clock source */\r
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));\r
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; \r
-\r
- /* Wait till PLL is used as system clock source */\r
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)\r
- {\r
- }\r
- }\r
- else\r
- { /* If HSE fails to start-up, the application will have wrong clock \r
- configuration. User can add here some code to deal with this error */ \r
-\r
- /* Go to infinite loop */\r
- while (1)\r
- {\r
- }\r
- }\r
-}\r
-#endif\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-\r
-/**\r
- ******************************************************************************\r
- * @file system_stm32f10x.h\r
- * @author MCD Application Team\r
- * @version V3.1.0\r
- * @date 06/19/2009\r
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\r
- ****************************************************************************** \r
- *\r
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS\r
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE\r
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY\r
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING\r
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE\r
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.\r
- *\r
- * <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>\r
- ******************************************************************************\r
- */\r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f10x_system\r
- * @{\r
- */ \r
- \r
-/**\r
- * @brief Define to prevent recursive inclusion\r
- */\r
-#ifndef __SYSTEM_STM32F10X_H\r
-#define __SYSTEM_STM32F10X_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
-\r
-/** @addtogroup STM32F10x_System_Includes\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-\r
-/** @addtogroup STM32F10x_System_Exported_types\r
- * @{\r
- */\r
-\r
-extern const uint32_t SystemFrequency; /*!< System Clock Frequency (Core Clock) */\r
-extern const uint32_t SystemFrequency_SysClk; /*!< System clock */\r
-extern const uint32_t SystemFrequency_AHBClk; /*!< AHB System bus speed */\r
-extern const uint32_t SystemFrequency_APB1Clk; /*!< APB Peripheral Bus 1 (low) speed */\r
-extern const uint32_t SystemFrequency_APB2Clk; /*!< APB Peripheral Bus 2 (high) speed */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Constants\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Macros\r
- * @{\r
- */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup STM32F10x_System_Exported_Functions\r
- * @{\r
- */\r
- \r
-extern void SystemInit(void);\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /*__SYSTEM_STM32F10X_H */\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/**\r
- * @}\r
- */ \r
-/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/* \r
+ * Copyright (C) ArcCore AB <contact@arccore.com>\r
+ *\r
+ * ST startup variables: \r
+ * _sidata - Start of .data in flash \r
+ * _sdata - start address of .data in RAM\r
+ * _edata - end address of .data in RAM\r
+ * _sbss - start address of .bss\r
+ * _ebss - end address of .bss\r
+ * _etext - ?\r
+ */\r
+\r
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm","elf32-littlearm")\r
+OUTPUT_ARCH(arm)\r
+ENTRY(Reset_Handler)\r
+\r
+MEMORY\r
+{\r
+ flash(R) : ORIGIN = 0x08008000, LENGTH = 256K-32K\r
+ ram(RW) : ORIGIN = 0x20000000, LENGTH = 64K\r
+}\r
+\r
+SECTIONS\r
+{\r
+\r
+ .isr_vector :\r
+ {\r
+ . = ALIGN(4);\r
+ KEEP(*(.isr_vector))\r
+ . = ALIGN(4);\r
+ } > flash\r
+\r
+ .text :\r
+ {\r
+ *(.text .text.* );\r
+ *(.glue_7) /* TODO */\r
+ *(.glue_7t) /* TODO */\r
+ \r
+ PROVIDE( btask_sup_matrix = .);\r
+ SORT(*)(.test_btask);\r
+ PROVIDE( etask_sup_matrix = .);\r
+ SORT(*)(.test_etask);\r
+ \r
+ /* ST/ARM special variable to initialize .data */\r
+ _etext = .;\r
+ } > flash\r
+\r
+ /* Relocatable Flash Driver */\r
+ .fls_rom : {\r
+ __FLS_ERASE_ROM__ = .;\r
+ *(.fls_erase);\r
+ __FLS_WRITE_ROM__ = .;\r
+ *(.fls_write);\r
+ __FLS_END_ROM__ = .;\r
+ } > flash\r
+\r
+ /* ARM exception section */\r
+ .ARM.exidx : { \r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } > flash\r
+ __exidx_start = .;\r
+\r
+ /* Read-only data section. */\r
+ .rodata : { \r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
+ _sidata = .;\r
+ } > flash\r
+\r
+ .data : AT(ALIGN(LOADADDR(.rodata)+SIZEOF(.rodata),4)) {\r
+ _sdata = .; \r
+ *(.data .data.* .gnu.linkonce.d.* .gnu.linkonce.r.* .eh_frame)\r
+ _edata = .; \r
+ } > ram\r
+\r
+ .t32_outport ALIGN(0x10): { *(.t32_outport); } > ram\r
+ .bss : {\r
+ _sbss = ., \r
+ *(.bss .bss.* COMMON .gnu.linkonce.b.*);\r
+ _ebss = .; \r
+ } > ram\r
+ \r
+ .init_stack ALIGN(16) (NOLOAD) : \r
+ { \r
+ . = . + 200; \r
+ _estack = .; \r
+ } > ram\r
+ \r
+ /* Fls RAM section */\r
+ .fls_ram ALIGN(16) (NOLOAD) : {\r
+ __FLS_ERASE_RAM__ = .;\r
+ . = . + SIZEOF(.fls_rom);\r
+ } > ram\r
+\r
+ .ctors :\r
+ {\r
+ KEEP (*(SORT(.ctors.*)))\r
+ }\r
+\r
+ .uninit ALIGN(0x10) (NOLOAD) : { *(.winidea_port .ramlog .dem_eventmemory_pri) ; } > ram\r
+\r
+ .boot_area 0x2000FE00 (NOLOAD):\r
+ {\r
+ _boot_area_start = .;\r
+ . = . + 256;\r
+ _boot_area_end = .;\r
+ } > ram\r
+ \r
+ PROVIDE (boot_area_start = _boot_area_start);\r
+ PROVIDE (boot_area_end = _boot_area_end);\r
+\r
+ __FLS_SIZE__ = SIZEOF(.fls_rom);\r
+ __FLS_WRITE_RAM__ = __FLS_ERASE_RAM__ + (__FLS_WRITE_ROM__ - __FLS_ERASE_ROM__);\r
+\r
+ /* Stabs debugging sections. */\r
+ .stab 0 : { *(.stab) }\r
+ .stabstr 0 : { *(.stabstr) }\r
+ .stab.excl 0 : { *(.stab.excl) }\r
+ .stab.exclstr 0 : { *(.stab.exclstr) }\r
+ .stab.index 0 : { *(.stab.index) }\r
+ .stab.indexstr 0 : { *(.stab.indexstr) }\r
+ .comment 0 : { *(.comment) }\r
+ /* DWARF debug sections.\r
+ Symbols in the DWARF debugging sections are relative to the beginning\r
+ of the section so we begin them at 0. */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+}\r
+__EXCEPT_START__ = 0x0;\r
+__EXCEPT_END__ = 0x0;\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+\r
+#include "McuExtensions.h"\r
+\r
+imask_t McuE_EnterCriticalSection(void) {\r
+ return 0;\r
+}\r
+\r
+void McuE_ExitCriticalSection(imask_t old_state) {\r
+\r
+}\r
*/\r
\r
/** @req OS383 */\r
-uint32_t Os_SysTickGetTimeElapsed( void )\r
+uint32_t Os_SysTickGetValue( void )\r
{\r
#if 0\r
uint32_t timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
*/\r
\r
/** @req OS383 */\r
-uint32_t Os_SysTickGetTimeElapsed( void )\r
+TickType Os_SysTickGetValue( void )\r
{\r
uint32_t timer = get_spr(SPR_DECAR) - get_spr(SPR_DEC);\r
return (timer);\r
-}\r
+}
+
+TickType Os_SysTickGetElapsedValue( uint32_t preValue ) {
+ uint32_t curr;
+ uint32_t max;
+
+ curr = get_spr(SPR_DEC);
+ max = get_spr(SPR_DECAR);
+ return Os_CounterDiff((max - curr),preValue,max);
+}
+\r
obj-$(CFG_PPC) += crt0.o\r
obj-$(CFG_HCS12D) += crt0.o\r
vpath-$(CFG_ARM_CM3) += $(ARCH_PATH-y)kernel\r
-obj-$(CFG_ARM_CM3) += system_stm32f10x.o\r
obj-$(CFG_ARM_CM3) += core_cm3.o\r
+obj-$(CFG_ARM_CM3) += startup_stm32f10x.o\r
\r
-obj-$(CFG_STM32_MD) += startup_stm32f10x_md.o\r
-obj-$(CFG_STM32_LD) += startup_stm32f10x_ld.o\r
-obj-$(CFG_STM32_HD) += startup_stm32f10x_hd.o\r
-obj-$(CFG_STM32_CL) += startup_stm32f10x_cl.o\r
+\r
+# OS object files. \r
+# (checking if already included for compatability)\r
+ifeq ($(filter Os_Cfg.o,$(obj-y)),)\r
+obj-$(USE_KERNEL) += Os_Cfg.o\r
+endif\r
\r
#Ecu\r
#obj-y += EcuM_$(BOARDDIR).o\r
# Flash\r
obj-$(USE_FLS) += Fls.o\r
obj-$(USE_FLS) += Fls_Cfg.o\r
-obj-$(USE_FLS) += Fls_H7F.o\r
+obj-$(CFG_MPC55XX)-$(USE_FLS) += Fls_H7F.o\r
\r
# Bring in the freescale driver source \r
inc-$(CFG_MPC55XX) += $(ROOTDIR)/$(ARCH_PATH-y)/delivery/mpc5500_h7f/include\r
obj-$(USE_ADC) += Adc_Cfg.o\r
\r
# Include the kernel\r
+ifneq ($(USE_KERNEL),)\r
include $(ROOTDIR)/system/kernel/makefile\r
+endif\r
\r
# Spi\r
obj-$(USE_SPI) += Spi.o\r
obj-$(USE_PWM) += Pwm_Cfg.o\r
\r
# Misc\r
-obj-y += Det.o\r
+obj-$(USE_DET) += Det.o\r
\r
# Lin\r
obj-$(USE_LIN) += Lin_PBcfg.o\r
inc-$(USE_DCM) += $(ROOTDIR)/diagnostic/Dcm\r
vpath-$(USE_DCM) += $(ROOTDIR)/diagnostic/Dcm\r
\r
+obj-$(USE_RAMLOG) += ramlog.o\r
\r
+# Common stuff, if speciied\r
+VPATH += $(ROOTDIR)/common\r
\r
#tests\r
#obj-y += RunTests.o\r
#libitem-$(USE_TESTS) += $(ROOTDIR)/embunit/embUnit/obj_$(ARCH)/libembunit.a\r
#libitem-$(USE_TESTS) += $(ROOTDIR)/embunit/textui/obj_$(ARCH)/libtextui.a\r
\r
-\r
-\r
-# Common\r
+# Newlib overrides (overridden by default)\r
+ifneq ($(CFG_STANDARD_NEWLIB),y)\r
obj-y += xtoa.o\r
-obj-y += arc.o\r
-#obj-y += malloc.o\r
-obj-$(USE_RAMLOG) += ramlog.o\r
-\r
+obj-y += newlib_port.o\r
# If we have configured console output we include printf. \r
-# Overridden to use lib implementation with CFG_USE_NEWLIB_PRINTF\r
-ifndef (CFG_USE_NEWLIB_PRINTF)\r
+# Overridden to use lib implementation with CFG_NEWLIB_PRINTF\r
+ifneq ($(CFG_NEWLIB_PRINTF),y)\r
+# TODO: This assumes that you print to console.. but you could\r
+# just print to a buffer, e.g. sprintf() \r
ifneq (,$(SELECT_CONSOLE) $(SELECT_OS_CONSOLE))\r
obj-y += printf.o\r
-endif\r
-endif\r
\r
-VPATH += $(ROOTDIR)/common\r
+endif # SELECT_CONSOLE\r
+endif # CFG_NEWLIB_PRINTF\r
+endif # CFG_STANDARD_NEWLIB\r
\r
-obj-y += newlib_port.o\r
obj-y += $(obj-y-y)\r
\r
vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL=KERNEL MCU PWM ADC ARM_ITM_TERM DEM DCM IOHWAB\r
-#T32_TERM SIMPLE_PRINTF RAMLOG\r
-#\r
+MOD_AVAIL+=ADC MCU PWM \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
\r
# Needed by us\r
MOD_USE=KERNEL MCU\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+\r
+\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+extern void MyPwmNotificationRoutine(void);\r
+\r
+// TODO remove, just put here for lazyness\r
+void MyPwmNotificationRoutine(void){\r
+}\r
+/* -----------------------------------------------------------------------\r
+ TIM4CLK = 72 MHz, Prescaler = 7199, TIM4 counter clock = 72 MHz\r
+ TIM4 ARR Register = 10000 => TIM4 Frequency = TIM4 counter clock/(ARR*(PSC + 1)\r
+ TIM4 Frequency = 1 Hz.\r
+ TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 12.5%\r
+\r
+\r
+ NOTE!!! All channels on one TIM uses the same Time base. The last configured will\r
+ set the Time base.\r
+ ----------------------------------------------------------------------- */\r
+const Pwm_ConfigType PwmConfig = {\r
+ .Channels = {\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 10000, 0x4000/*50%*/, 29, PWM_HIGH),\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 10000, 0x4000/*50%*/, 29, PWM_LOW)\r
+ },\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ .NotificationHandlers = {\r
+ MyPwmNotificationRoutine, // PWM_CHANNEL_1\r
+ NULL // PWM_CHANNEL_2\r
+ }\r
+#endif\r
+};\r
+\r
+\r
-\r
-# ARCH defines\r
-ARCH=hcs12d\r
-ARCH_FAM=hc1x\r
-ARCH_MCU=MC912DG128A\r
-\r
-# CFG (y/n) macros (These become CFG_XXX=y and def-y += CFG_XXX ) \r
-CFG=HC1X HCS12D MC912DG128A BRD_HCS12_ELMICRO_CARD12 SIMULATOR\r
-\r
-# What buildable modules does this board have, \r
-# default or private (These become MOD_XXX=y )\r
-MOD_AVAIL+=KERNEL MCU GPT DIO PORT COM CAN CANIF PWM ADC DEM DCM PDUR COMM NM CANNM CANSM CANTP\r
-\r
-# Needed by us (These become USE_XXX=y and def-y += USE_XXX )\r
-MOD_USE=KERNEL MCU\r
+
+# ARCH defines
+ARCH=hcs12d
+ARCH_FAM=hc1x
+ARCH_MCU=MC912DG128A
+
+# CFG (y/n) macros (These become CFG_XXX=y and def-y += CFG_XXX )
+CFG=HC1X HCS12D MC912DG128A BRD_HCS12_ELMICRO_CARD12 SIMULATOR
+
+# What buildable modules does this board have,
+# default or private (These become MOD_XXX=y )
+MOD_AVAIL+=MCU GPT
+# System + Communication + Diagnostic
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE
+# Additional
+MOD_AVAIL+=RAMLOG
+
+
+# Needed by us (These become USE_XXX=y and def-y += USE_XXX )
+MOD_USE=KERNEL MCU
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=linux\r
+ARCH_FAM=generic\r
+#ARCH=mpc55xx\r
+#ARCH_FAM=ppc\r
+#ARCH_MCU=mpc5516\r
+\r
+# CFG (y/n) macros\r
+CFG= BRD_LINUX\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+MOD_AVAIL+=COM PDUR DET DCM DEM COMM CANSM CANTP CANIF CANNM NM RTE\r
+\r
+# Needed by us\r
+MOD_USE=\r
+\r
+# Stubs\r
+obj-y += McuExtensionsStub.o
\ No newline at end of file
\r
\r
The Freescale MPC5510 is an PowerPC process with a e200Z1+e200Z0 core. \r
-\r
+ \r
Datasheets:\r
Eval board:\r
http://www.asyst.si/isystem/files/downloads/evaluation_boards/ITMPC5517_V10.pdf \r
-\r
+ \r
MPC5516/7\r
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5510&webpageId=1067371573986721160325&nodeId=0162468rH3bTdG06C10325&fromPage=tax\r
- \r
+\r
Board:\r
8Mhz external crystal\r
\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL+=KERNEL MCU GPT LIN CAN CANIF CANTP PORT DIO WDG WDGM PWM COM ADC DMA DEM DCM PDUR IOHWAB COMM NM CANNM CANSM RTE NVM MEMIF FEE\r
\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG NVM MEMIF FEE FLS \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+= RAMLOG \r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
\r
#define ComConfigurationTimeBase\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0xFF,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_EngineChangeSpeed,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_SIL2MESSAGE,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- //.ComSignalEndianess = BIG_ENDIAN,\r
+ //.ComSignalEndianess = COM_BIG_ENDIAN,\r
//.ComSignalInitValue = 0xFF,\r
//.ComSignalLength = 0,\r
//.ComSignalType = UINT16,\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL=KERNEL MCU GPT LIN CAN WDG WDGM DEM DCM IOHWAB\r
\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
/*\r
* ComGeneral pre-compile time configuration parameters.\r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL+=KERNEL MCU GPT LIN CAN COM WDG WDGM DEM DCM IOHWAB\r
\r
-# Needed by kernel\r
-MOD_USE+=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
\r
# What buildable modules does this board have, \r
# default or private\r
-MOD_AVAIL=KERNEL MCU WDG WDGM PORT DIO WDG WDGM PWM CAN CANIF COM ADC DMA DEM DCM CANTP PDUR IOHWAB COMM NM CANNM CANSM RTE NVM MEMIF FEE FLS\r
\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
+# Memory + Peripherals\r
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG NVM MEMIF FEE FLS \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG \r
\r
\r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
/*\r
* ComGeneral pre-compile time configuration parameters.\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x0,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT8,\r
.ComNotification = NULL,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0xFF,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_EngineChangeSpeed,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalInitValue = 0x00,\r
.ComSignalLength = 0,\r
.ComSignalType = UINT16,\r
.ComNotification = RTE_SIL2MESSAGE,\r
//.ComRxDataTimeoutAction (NOT IMPLEMENTED)\r
//.ComSignalDataInvalidValue (NOT IMPLEMENTED)\r
- //.ComSignalEndianess = BIG_ENDIAN,\r
+ //.ComSignalEndianess = COM_BIG_ENDIAN,\r
//.ComSignalInitValue = 0xFF,\r
//.ComSignalLength = 0,\r
//.ComSignalType = UINT16,\r
-\r
-# ARCH defines\r
-ARCH=mpc55xx\r
-ARCH_FAM=ppc\r
-ARCH_MCU=mpc5633\r
-\r
-# CFG (y/n) macros\r
-CFG=PPC BOOKE E200Z3 MPC55XX MPC5633 BRD_MPC5633SIM SPE\r
-\r
-# What buildable modules does this board have, \r
-# default or private\r
-MOD_AVAIL=KERNEL RAMLOG MCU WDG WDGM PORT DIO WDG WDGM PWM CAN CANIF COM ADC DMA\r
-\r
-# Needed by us\r
-MOD_USE=KERNEL MCU\r
-\r
-\r
+
+# ARCH defines
+ARCH=mpc55xx
+ARCH_FAM=ppc
+ARCH_MCU=mpc5633
+
+# CFG (y/n) macros
+CFG=PPC BOOKE E200Z3 MPC55XX MPC5633 BRD_MPC5633SIM SPE
+
+# What buildable modules does this board have,
+# default or private
+
+# Memory + Peripherals
+MOD_AVAIL+=ADC DIO DMA CAN GPT LIN MCU PORT PWM WDG
+# System + Communication + Diagnostic
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE
+# Additional
+MOD_AVAIL+=RAMLOG
+
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cm3\r
+ARCH_FAM=arm\r
+ARCH_MCU=arm_cm3\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CM3\r
+# Add our board \r
+CFG+=BRD_STM32_MCBSTM32 \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_MD\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+= RAMLOG \r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
+# Use little heap\r
+def-y += HEAPSIZE=4000\r
+# Select the right device in ST header files.\r
+# [ STM32F10X_LD | STM32F10X_MD | STM32F10X_HD |STM32F10X_CL ]\r
+def-y += STM32F10X_MD\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+\r
+#include "Adc.h"\r
+#include "stm32f10x_adc.h"\r
+\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+/* Configuration goes here. */\r
+void Adc_Group0Notification (void)\r
+{\r
+}\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+};\r
+\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_GROUP0_CHANNELS] =\r
+{\r
+ ADC_CH1,ADC_CH1,ADC_CH1,ADC_CH1\r
+};\r
+\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ {\r
+ // NOT SUPPORTED .accessMode = ADC_ACCESS_MODE_SINGLE,\r
+ .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ // NOT SUPPORTED .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ // NOT SUPPORTED .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group0Notification,\r
+ // NOT SUPPORTED .streamBufferMode = ADC_NO_STREAMING,\r
+ // NOT SUPPORTED .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .numberOfChannels = sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0]},\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+/* Group definitions. */\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_POT,\r
+ ADC_TEST_BOARD_POT2,\r
+ ADC_TEST_BOARD_POT3,\r
+ ADC_TEST_BOARD_POT4,\r
+ ADC_NBR_OF_GROUP0_CHANNELS,\r
+}Adc_Group0SignalType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK\r
+}Adc_ClockSourceType;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DISABLED,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ Adc_ClockSourceType clockSource;\r
+ uint8_t hwUnitId;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_64_CLOCKS,\r
+ ADC_CONVERSION_TIME_128_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+/* Channel definitions, std container */\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType adcChannelConvTime;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;\r
+ // NOT SUPPORTED Adc_ResolutionType adcChannelResolution;\r
+ // NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;\r
+} Adc_ChannelConfigurationType;\r
+\r
+/* Used ?? */\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+/* Implementation specific */\r
+typedef struct\r
+{\r
+ // NOT SUPPORTED Adc_GroupAccessModeType accessMode;\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ // NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;\r
+ // NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;\r
+ void (*groupCallback)(void);\r
+ // NOT SUPPORTED Adc_StreamBufferModeType streamBufferMode;\r
+ // NOT SUPPORTED Adc_StreamNumSampleType streamNumSamples;\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ // NOT SUPPORTED Adc_CommandType *commandBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+ // NOT SUPPORTED Dma_ChannelType dmaCommandChannel;\r
+ // NOT SUPPORTED Dma_ChannelType dmaResultChannel;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMACommands;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMAResults;\r
+} Adc_GroupDefType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_ChannelConfigurationType* channelConfigPtr;\r
+ const uint16_t nbrOfChannels;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+ const uint16_t nbrOfGroups;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig [];\r
+\r
+\r
+#endif /*ADC_CFG_H_*/\r
--- /dev/null
+/*
+* Configuration of module Can (Can_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+
+#if (CAN_SW_MAJOR_VERSION != 1)
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+\r
+// Start stm32 unique
+typedef enum {\r
+ CAN_CTRL_1 = 0,\r
+ CAN_CTRL_2 = 1,\r
+ CAN_CONTROLLER_CNT = 2\r
+}CanControllerIdType;\r
+// End stm32 unique
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_2,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_1,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+} Can_GeneralType;
+
+typedef uint32_t Can_FilterMaskType;
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
+\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/*
+* Configuration of module Can (Can_Lcfg.c)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_Mask_1[] = {
+ 0xffffffff,
+ 0xffffffff,
+};\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
+ {\r
+ .CanObjectId = HWObj_1,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = HWObj_2,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_1,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+#define DIO_END_OF_LIST -1\r
+\r
+/** @name DIO channels\r
+ * HW specific dio channels.\r
+ */\r
+// Pin Name GPIO(PCR)Num\r
+//@{\r
+//* req DIO015 */\r
+//* req DIO017 */\r
+typedef enum\r
+{\r
+ DIO_CHANNEL_A0,\r
+ DIO_CHANNEL_A1,\r
+ DIO_CHANNEL_A2,\r
+ DIO_CHANNEL_A3,\r
+ DIO_CHANNEL_A4,\r
+ DIO_CHANNEL_A5,\r
+ DIO_CHANNEL_A6,\r
+ DIO_CHANNEL_A7,\r
+ DIO_CHANNEL_A8,\r
+ DIO_CHANNEL_A9,\r
+ DIO_CHANNEL_A10,\r
+ DIO_CHANNEL_A11,\r
+ DIO_CHANNEL_A12,\r
+ DIO_CHANNEL_A13,\r
+ DIO_CHANNEL_A14,\r
+ DIO_CHANNEL_A15,\r
+\r
+ DIO_CHANNEL_B0,\r
+ DIO_CHANNEL_B1,\r
+ DIO_CHANNEL_B2,\r
+ DIO_CHANNEL_B3,\r
+ DIO_CHANNEL_B4,\r
+ DIO_CHANNEL_B5,\r
+ DIO_CHANNEL_B6,\r
+ DIO_CHANNEL_B7,\r
+ DIO_CHANNEL_B8,\r
+ DIO_CHANNEL_B9,\r
+ DIO_CHANNEL_B10,\r
+ DIO_CHANNEL_B11,\r
+ DIO_CHANNEL_B12,\r
+ DIO_CHANNEL_B13,\r
+ DIO_CHANNEL_B14,\r
+ DIO_CHANNEL_B15,\r
+\r
+ DIO_CHANNEL_C0,\r
+ DIO_CHANNEL_C1,\r
+ DIO_CHANNEL_C2,\r
+ DIO_CHANNEL_C3,\r
+ DIO_CHANNEL_C4,\r
+ DIO_CHANNEL_C5,\r
+ DIO_CHANNEL_C6,\r
+ DIO_CHANNEL_C7,\r
+ DIO_CHANNEL_C8,\r
+ DIO_CHANNEL_C9,\r
+ DIO_CHANNEL_C10,\r
+ DIO_CHANNEL_C11,\r
+ DIO_CHANNEL_C12,\r
+ DIO_CHANNEL_C13,\r
+ DIO_CHANNEL_C14,\r
+ DIO_CHANNEL_C15,\r
+\r
+ DIO_CHANNEL_D0,\r
+ DIO_CHANNEL_D1,\r
+ DIO_CHANNEL_D2,\r
+ DIO_CHANNEL_D3,\r
+ DIO_CHANNEL_D4,\r
+ DIO_CHANNEL_D5,\r
+ DIO_CHANNEL_D6,\r
+ DIO_CHANNEL_D7,\r
+ DIO_CHANNEL_D8,\r
+ DIO_CHANNEL_D9,\r
+ DIO_CHANNEL_D10,\r
+ DIO_CHANNEL_D11,\r
+ DIO_CHANNEL_D12,\r
+ DIO_CHANNEL_D13,\r
+ DIO_CHANNEL_D14,\r
+ DIO_CHANNEL_D15,\r
+\r
+ DIO_CHANNEL_E0,\r
+ DIO_CHANNEL_E1,\r
+ DIO_CHANNEL_E2,\r
+ DIO_CHANNEL_E3,\r
+ DIO_CHANNEL_E4,\r
+ DIO_CHANNEL_E5,\r
+ DIO_CHANNEL_E6,\r
+ DIO_CHANNEL_E7,\r
+ DIO_CHANNEL_E8,\r
+ DIO_CHANNEL_E9,\r
+ DIO_CHANNEL_E10,\r
+ DIO_CHANNEL_E11,\r
+ DIO_CHANNEL_E12,\r
+ DIO_CHANNEL_E13,\r
+ DIO_CHANNEL_E14,\r
+ DIO_CHANNEL_E15,\r
+\r
+ DIO_CHANNEL_F0,\r
+ DIO_CHANNEL_F1,\r
+ DIO_CHANNEL_F2,\r
+ DIO_CHANNEL_F3,\r
+ DIO_CHANNEL_F4,\r
+ DIO_CHANNEL_F5,\r
+ DIO_CHANNEL_F6,\r
+ DIO_CHANNEL_F7,\r
+ DIO_CHANNEL_F8,\r
+ DIO_CHANNEL_F9,\r
+ DIO_CHANNEL_F10,\r
+ DIO_CHANNEL_F11,\r
+ DIO_CHANNEL_F12,\r
+ DIO_CHANNEL_F13,\r
+ DIO_CHANNEL_F14,\r
+ DIO_CHANNEL_F15,\r
+\r
+} Dio_ChannelType;\r
+//@}\r
+\r
+/** HW specific DIO port definitions. */\r
+/** @req DIO018 */\r
+/** @req DIO020 */\r
+typedef enum {\r
+ DIO_PORT_A,\r
+ DIO_PORT_B,\r
+ DIO_PORT_C,\r
+ DIO_PORT_D,\r
+ DIO_PORT_E,\r
+ DIO_PORT_F,\r
+} Dio_PortType;\r
+\r
+/** @req DIO021 */\r
+/** @req DIO022 */\r
+typedef struct\r
+{\r
+ Dio_PortType port;\r
+ uint16 offset;\r
+ uint16 mask;\r
+} Dio_ChannelGroupType;\r
+\r
+/** @req DIO023 */\r
+typedef uint16 Dio_LevelType;\r
+\r
+/** @req DIO024 */\r
+typedef uint16 Dio_PortLevelType;\r
+\r
+#define LED_CHANNEL (DIO_CHANNEL_B13)\r
+\r
+#define LED_PORT (DIO_PORT_B)\r
+\r
+#define LED_GROUP (&DioConfigData[0])\r
+\r
+// Channels\r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+#define CHANNEL_PTR (&DioChannelConfigData)\r
+\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+#define PORT_PTR (&DioPortConfigData)\r
+\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+#define CHANNEL_GRP_PTR (&DioConfigData)\r
+\r
+#endif /* DIO_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] =\r
+{\r
+ LED_CHANNEL,\r
+ DIO_END_OF_LIST,\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] =\r
+{\r
+ LED_PORT,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] =\r
+{\r
+ { .port = DIO_PORT_B, .offset = 7, .mask = 0x80, },\r
+ { .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
+};\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+
+const Fls_SectorType fls_SectorList[] = {
+ {
+ .FlsSectorStartaddress = (Fls_AddressType)0x08000000, // Start address of this sector
+ .FlsPageSize = (Fls_LengthType)(1 KB), // Page size of 1k
+ .FlsSectorSize = (Fls_LengthType)(1 KB),
+ // Number of continuous sectors with the above characteristics.
+ .FlsNumberOfSectors = (uint32)255
+ }
+};
+\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+ .FlsSectorList = &fls_SectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_SectorList)/sizeof(Fls_SectorType),\r
+ .FlsBlockToPartitionMap = NULL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef FLS_CFG_H_\r
+#define FLS_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define FLS_BASE_ADDRESS 0x08000000\r
+#define FLS_TOTAL_SIZE 0x40000 // from addr 0x0800_0000 to 0x0804_0000\r
+\r
+// Configuration description of a flashable sector\r
+typedef struct {\r
+ // Number of continuous sectors with the above characteristics.\r
+ Fls_LengthType FlsNumberOfSectors;\r
+\r
+ // Size of one page of this sector. Implementation Type: Fls_LengthType.\r
+ Fls_LengthType FlsPageSize;\r
+\r
+ // Size of this sector. Implementation Type: Fls_LengthTyp\r
+ Fls_LengthType FlsSectorSize;\r
+\r
+ // Start address of this sector\r
+ Fls_AddressType FlsSectorStartaddress;\r
+\r
+} Fls_SectorType;\r
+\r
+\r
+typedef struct {\r
+ // List of flash:able sectors and pages\r
+ const Fls_SectorType *FlsSectorList;\r
+\r
+ // Size of List of the FlsSectorList\r
+ const uint32 FlsSectorListSize;\r
+\r
+ uint8 *FlsBlockToPartitionMap;\r
+\r
+} Fls_ConfigType;\r
+\r
+extern const Fls_ConfigType FlsConfigSet[];\r
+\r
+\r
+#endif /* FLS_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+
+const Mcu_PerClockConfigType McuPerClockConfigData =
+{
+ .AHBClocksEnable = RCC_AHBPeriph_DMA1,
+ .APB1ClocksEnable = RCC_APB1Periph_TIM2 | RCC_APB1Periph_CAN1,
+ .APB2ClocksEnable = (RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA |
+ RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO),
+};
+\r
+const Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 8000000UL,\r
+ .Pll1 = 9,\r
+ .Pll2 = 0,\r
+ .Pll3 = 0,\r
+ },\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+// .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_8MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+// .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+// .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+#endif
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
+typedef struct {
+ uint32 AHBClocksEnable;
+ uint32 APB1ClocksEnable;
+ uint32 APB2ClocksEnable;
+} Mcu_PerClockConfigType;
+
+extern const Mcu_PerClockConfigType McuPerClockConfigData;
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_8MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+#include "Port_Cfg.h"\r
+\r
+\r
+typedef enum {\r
+ PORTA,\r
+ PORTB,\r
+ PORTC,\r
+ PORTD,\r
+ PORTE,\r
+ NUMBER_OF_PORTS\r
+} Port_PortType;\r
+\r
+const u32 remaps[] = {\r
+ GPIO_Remap1_CAN1,\r
+ GPIO_PartialRemap2_TIM2,\r
+};\r
+\r
+const Port_PortConfigType porta = {\r
+ .port = GPIOA,\r
+ .pinCount = 1,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_1,\r
+ .GPIO_Mode = GPIO_Mode_AIN,\r
+ .GPIO_Speed = GPIO_Speed_2MHz\r
+ },\r
+ }\r
+};\r
+\r
+\r
+const Port_PortConfigType portb = {\r
+ .port = GPIOB,\r
+ .pinCount = 4,\r
+ .pins = {\r
+ /* PB8 is CAN1_RX, remapped: */\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_8,\r
+ .GPIO_Mode = GPIO_Mode_IPU,\r
+ .GPIO_Speed = GPIO_Speed_10MHz\r
+ },\r
+ /* PB9 is CAN1_TX, remapped: */\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_9,\r
+ .GPIO_Mode = GPIO_Mode_AF_PP,\r
+ .GPIO_Speed = GPIO_Speed_10MHz\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11,\r
+ .GPIO_Mode = GPIO_Mode_AF_PP,\r
+ .GPIO_Speed = GPIO_Speed_50MHz\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15,\r
+ .GPIO_Mode = GPIO_Mode_Out_PP,\r
+ .GPIO_Speed = GPIO_Speed_10MHz\r
+ },\r
+\r
+ }\r
+};\r
+\r
+const Port_PortConfigType portc = {\r
+ .port = GPIOC,\r
+ .pinCount = 1,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12,\r
+ .GPIO_Mode = GPIO_Mode_Out_PP,\r
+ .GPIO_Speed = GPIO_Speed_10MHz,\r
+ },\r
+\r
+ }\r
+};\r
+\r
+const Port_PortConfigType portd = {\r
+ .port = GPIOD,\r
+ .pinCount = 1,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = 0xffff,\r
+ .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
+ .GPIO_Speed = GPIO_Speed_2MHz,\r
+ },\r
+ }\r
+};\r
+\r
+const Port_PortConfigType porte = {\r
+ .port = GPIOE,\r
+ .pinCount = 1,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = 0xffff,\r
+ .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
+ .GPIO_Speed = GPIO_Speed_2MHz,\r
+ },\r
+ }\r
+};\r
+\r
+const Port_ConfigType PortConfigData = {\r
+ .portCount = NUMBER_OF_PORTS,\r
+ .ports = {\r
+ &porta,\r
+ &portb,\r
+ &portc,\r
+ &portd,\r
+ &porte\r
+ },\r
+\r
+ .remapCount = sizeof(remaps) / sizeof(u32),\r
+ .remaps = &remaps[0]\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "stm32f10x_gpio.h"\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
+/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+\r
+/** @req PORT124 */\r
+typedef uint8 Port_PinModeType;\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum{\r
+ PIN1,\r
+} Port_PinType;\r
+\r
+/* Configuration of one specific port */\r
+typedef struct {\r
+ uint16_t pinCount;\r
+ GPIO_TypeDef *port;\r
+ const GPIO_InitTypeDef pins[];\r
+\r
+} Port_PortConfigType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct {\r
+ uint16_t remapCount;\r
+ const uint32_t* remaps;\r
+\r
+ uint16_t portCount;\r
+ const Port_PortConfigType* ports[];\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+\r
+\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+extern void MyPwmNotificationRoutine(void);\r
+\r
+// TODO remove, just put here for lazyness\r
+void MyPwmNotificationRoutine(void){\r
+}\r
+/* -----------------------------------------------------------------------\r
+ TIM4CLK = 72 MHz, Prescaler = 7199, TIM4 counter clock = 72 MHz\r
+ TIM4 ARR Register = 10000 => TIM4 Frequency = TIM4 counter clock/(ARR*(PSC + 1)\r
+ TIM4 Frequency = 1 Hz.\r
+ TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 12.5%\r
+\r
+\r
+ NOTE!!! All channels on one TIM uses the same Time base. The last configured will\r
+ set the Time base.\r
+ ----------------------------------------------------------------------- */\r
+const Pwm_ConfigType PwmConfig = {\r
+ .Channels = {\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 10000, 0x4000/*50%*/, 29, PWM_HIGH),\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 10000, 0x4000/*50%*/, 29, PWM_LOW)\r
+ },\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ .NotificationHandlers = {\r
+ MyPwmNotificationRoutine, // PWM_CHANNEL_1\r
+ NULL // PWM_CHANNEL_2\r
+ }\r
+#endif\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+/****************************************************************************\r
+ * Global configuration options and defines\r
+ */\r
+/*\r
+ * PWM003: The detection of development errors is configurable (STD_ON/STD_OFF) at\r
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
+ * the detection of all development errors\r
+ */\r
+#define PWM_DEV_EROR_DETECT STD_ON\r
+#define PWM_GET_OUTPUT_STATE STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_ON\r
+\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+\r
+/*\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only STD_ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/*\r
+ * Setting to STD_ON freezes the current output state of a PWM channel when in\r
+ * debug mode.\r
+ */\r
+#define PWM_FREEZE_ENABLE STD_ON\r
+\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/*\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == eemios channel id.\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_11 = 0, // TIM1 Channel 1\r
+ PWM_CHANNEL_12,\r
+ PWM_CHANNEL_13,\r
+ PWM_CHANNEL_14,\r
+ PWM_CHANNEL_21, // TIM2 Channel 1\r
+ PWM_CHANNEL_22,\r
+ PWM_CHANNEL_23,\r
+ PWM_CHANNEL_24,\r
+ PWM_CHANNEL_31, // TIM3 Channel 1\r
+ PWM_CHANNEL_32,\r
+ PWM_CHANNEL_33,\r
+ PWM_CHANNEL_34,\r
+ PWM_CHANNEL_41, // TIM4 Channel 1\r
+ PWM_CHANNEL_42,\r
+ PWM_CHANNEL_43,\r
+ PWM_CHANNEL_44,\r
+ PWM_TOTAL_NOF_CHANNELS,\r
+} Pwm_ChannelType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_1 = PWM_CHANNEL_23, //PB10\r
+ PWM_CHANNEL_2 = PWM_CHANNEL_24, //PB11\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+\r
+/* NEW NEW */\r
+\r
+typedef enum {\r
+ PWM_CHANNEL_PRESCALER_1=0,\r
+ PWM_CHANNEL_PRESCALER_2,\r
+ PWM_CHANNEL_PRESCALER_3,\r
+ PWM_CHANNEL_PRESCALER_4,\r
+} Pwm_ChannelPrescalerType;\r
+\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period\r
+\r
+typedef struct {\r
+ /* Number of duty ticks */\r
+ uint32_t duty:32;\r
+ /* Length of period, in ticks */\r
+ uint32_t period:32;\r
+ /* Counter */\r
+ uint32_t counter:32;\r
+ /* Enable freezing the channel when in debug mode */\r
+ uint32_t freezeEnable:1;\r
+ /* Disable output */\r
+ uint32_t outputDisable:1;\r
+ /* Select which bus disables the bus\r
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */\r
+ uint32_t outputDisableSelect:2;\r
+ /* Prescale the emios clock some more? */\r
+ Pwm_ChannelPrescalerType prescaler:2;\r
+ /* Prescale the emios clock some more? */\r
+ uint32_t usePrescaler:1;\r
+ /* Whether to use DMA. Currently unsupported */\r
+ uint32_t useDma:1;\r
+ uint32_t reserved_2:1;\r
+ /* Input filter. Ignored in output mode. */\r
+ uint32_t inputFilter:4;\r
+ /* Input filter clock source. Ignored in output mode */\r
+ uint32_t filterClockSelect:1;\r
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */\r
+ uint32_t flagEnable:1;\r
+ uint32_t reserved_3:3;\r
+ /* Trigger a match on channel A */\r
+ uint32_t forceMatchA:1;\r
+ /* Triggers a match on channel B */\r
+ uint32_t forceMatchB:1;\r
+ uint32_t reserved_4:1;\r
+ /* We can use different buses for the counter. Use the internal counter */\r
+ uint32_t busSelect:2;\r
+ /* What edges to flag on? */\r
+ uint32_t edgeSelect:1;\r
+ /* Polarity of the channel */\r
+ uint32_t edgePolarity:1;\r
+ /* EMIOS mode. 0x58 for buffered output PWM */\r
+ uint32_t mode:7;\r
+} Pwm_ChannelRegisterType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelRegisterType r;\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];\r
+#endif\r
+} Pwm_ConfigType;\r
+\r
+// Channel configuration macro.\r
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \\r
+ {\\r
+ .channel = _hwchannel,\\r
+ .r = {\\r
+ DUTY_AND_PERIOD(_duty, _period),\\r
+ .freezeEnable = 1,\\r
+ .outputDisable = 0,\\r
+ .usePrescaler = 1,\\r
+ .prescaler = _prescaler,\\r
+ .useDma = 0,\\r
+ .flagEnable = 0, /* See PWM052 */ \\r
+ .busSelect = 3, /* Use the internal counter bus */\\r
+ .edgePolarity = _polarity,\\r
+ .mode = 0\\r
+ }\\r
+ }\r
+\r
+#endif /*PWM_CFG_H_*/\r
--- /dev/null
+\r
+# ARCH defines\r
+ARCH=arm_cm3\r
+ARCH_FAM=arm\r
+ARCH_MCU=arm_cm3\r
+\r
+#\r
+# CFG (y/n) macros\r
+# \r
+\r
+CFG=ARM ARM_CM3\r
+# Add our board \r
+CFG+=BRD_STM32_MCBSTM32 \r
+\r
+# \r
+# ST have devided devices into ( See chapter 6 in Ref manual )\r
+# LD - Low Density. STM32F101xx,F102xx,F103xx). Flash 16->32Kbytes\r
+# MD - Medium Density. Same as above. Flash 64->128Kbytes\r
+# HD - High Denstiry. STM32F101xx,F103xx. Flash 256->512Kbytes\r
+# CL - Connectivity Line. STM32F105xx,F107xx \r
+# \r
+# [ STM32_MD | CFG_STM32_LD | CFG_STM32_HD | CFG_STM32_CL ] \r
+CFG+=STM32_CL\r
+\r
+# What buildable modules does this board have, \r
+# default or private\r
+\r
+MOD_AVAIL+=ADC CAN DIO MCU FLS PORT PWM \r
+# System + Communication + Diagnostic\r
+MOD_AVAIL+=CANIF CANTP COM DCM DEM DET ECUM IOHWAB KERNEL PDUR WDGM RTE\r
+# Additional\r
+MOD_AVAIL+=RAMLOG TCF LWIP\r
+\r
+#\r
+# Extra defines \r
+#\r
+\r
+# Select the right device in ST header files.\r
+# [ STM32F10X_LD | STM32F10X_MD | STM32F10X_HD |STM32F10X_CL ]\r
+def-y += STM32F10X_CL\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+\r
+#include "Adc.h"\r
+#include "stm32f10x_adc.h"\r
+\r
+\r
+Adc_GroupStatus AdcGroupStatus[ADC_NBR_OF_GROUPS];\r
+\r
+/* Configuration goes here. */\r
+void Adc_Group0Notification (void)\r
+{\r
+}\r
+\r
+const Adc_HWConfigurationType AdcHWUnitConfiguration =\r
+{\r
+ .hwUnitId = 0,\r
+ .adcPrescale = ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ .clockSource = ADC_SYSTEM_CLOCK,\r
+};\r
+\r
+const Adc_ChannelConfigurationType AdcChannelConfiguration [ADC_NBR_OF_CHANNELS] =\r
+{\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+ { .adcChannelConvTime = ADC_SampleTime_55Cycles5 },\r
+};\r
+\r
+const Adc_ChannelType Adc_Group0ChannelList[ADC_NBR_OF_GROUP0_CHANNELS] =\r
+{\r
+ ADC_CH1,ADC_CH1,ADC_CH1,ADC_CH1\r
+};\r
+\r
+\r
+/* Ram buffers for command and result queues. These are located here in the\r
+ configuration to be able to reconfigure system without recompiling the\r
+ drivers. */\r
+Adc_ValueGroupType Adc_Group0Buffer [sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0])];\r
+\r
+const Adc_GroupDefType AdcGroupConfiguration [] =\r
+{\r
+ {\r
+ // NOT SUPPORTED .accessMode = ADC_ACCESS_MODE_SINGLE,\r
+ .conversionMode = ADC_CONV_MODE_ONESHOT,\r
+ .triggerSrc = ADC_TRIGG_SRC_SW,\r
+ // NOT SUPPORTED .hwTriggerSignal = ADC_NO_HW_TRIG,\r
+ // NOT SUPPORTED .hwTriggerTimer = ADC_NO_TIMER,\r
+ .groupCallback = Adc_Group0Notification,\r
+ // NOT SUPPORTED .streamBufferMode = ADC_NO_STREAMING,\r
+ // NOT SUPPORTED .streamNumSamples = 0,\r
+ .channelList = Adc_Group0ChannelList,\r
+ .resultBuffer = Adc_Group0Buffer,\r
+ .numberOfChannels = sizeof(Adc_Group0ChannelList)/sizeof(Adc_Group0ChannelList[0]),\r
+ .status = &AdcGroupStatus[ADC_GROUP0]},\r
+};\r
+\r
+\r
+/******************************************************************/\r
+/* */\r
+/* End of user configuration area. DO NOT modify the code below!! */\r
+/* */\r
+/******************************************************************/\r
+const Adc_ConfigType AdcConfig [] =\r
+{\r
+ {\r
+ .hwConfigPtr = &AdcHWUnitConfiguration,\r
+ .channelConfigPtr = AdcChannelConfiguration,\r
+ .nbrOfChannels = sizeof(AdcChannelConfiguration)/sizeof(AdcChannelConfiguration[0]),\r
+ .groupConfigPtr = AdcGroupConfiguration,\r
+ .nbrOfGroups = sizeof(AdcGroupConfiguration)/sizeof(AdcGroupConfiguration[0])}\r
+};\r
+
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Adc_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: Fredrik\r
+ */\r
+#ifndef ADC_CFG_H_\r
+#define ADC_CFG_H_\r
+\r
+#define ADC_PRIORITY_HW 0\r
+#define ADC_PRIORITY_HW_SW 1\r
+#define ADC_PRIORITY_NONE 2\r
+\r
+#define ADC_DEINIT_API STD_ON\r
+#define ADC_DEV_ERROR_DETECT STD_ON\r
+#define ADC_ENABLE_QUEUING STD_ON\r
+#define ADC_ENABLE_START_STOP_GROUP_API STD_ON\r
+#define ADC_GRP_NOTIF_CAPABILITY STD_ON\r
+#define ADC_HW_TRIGGER_API STD_OFF /* Not implemented. */\r
+#define ADC_PRIORITY_IMPLEMENTATION ADC_PRIORITY_HW\r
+#define ADC_READ_GROUP_API STD_ON\r
+#define ADC_VERSION_API STD_ON /* Not implemented. */\r
+\r
+typedef uint16_t Adc_ValueGroupType;\r
+/* Group definitions. */\r
+\r
+typedef enum\r
+{\r
+ ADC_GROUP0,\r
+ ADC_NBR_OF_GROUPS\r
+}Adc_GroupType;\r
+\r
+typedef enum\r
+{\r
+ ADC_CH0,\r
+ ADC_CH1,\r
+ ADC_CH2,\r
+ ADC_CH3,\r
+ ADC_CH4,\r
+ ADC_CH5,\r
+ ADC_CH6,\r
+ ADC_CH7,\r
+ ADC_CH8,\r
+ ADC_CH9,\r
+ ADC_CH10,\r
+ ADC_CH11,\r
+ ADC_CH12,\r
+ ADC_CH13,\r
+ ADC_CH14,\r
+ ADC_CH15,\r
+ ADC_NBR_OF_CHANNELS,\r
+}Adc_ChannelType;\r
+\r
+typedef enum\r
+{\r
+ ADC_TEST_BOARD_POT,\r
+ ADC_TEST_BOARD_POT2,\r
+ ADC_TEST_BOARD_POT3,\r
+ ADC_TEST_BOARD_POT4,\r
+ ADC_NBR_OF_GROUP0_CHANNELS,\r
+}Adc_Group0SignalType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK\r
+}Adc_ClockSourceType;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_SYSTEM_CLOCK_DISABLED,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_1,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_2,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_4,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_6,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_8,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_10,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_12,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_14,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_16,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_18,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_20,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_22,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_24,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_26,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_28,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_30,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_32,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_34,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_36,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_38,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_40,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_42,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_44,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_46,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_48,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_50,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_52,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_54,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_56,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_58,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_60,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_62,\r
+ ADC_SYSTEM_CLOCK_DIVIDE_FACTOR_64,\r
+}Adc_PrescaleType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ Adc_ClockSourceType clockSource;\r
+ uint8_t hwUnitId;\r
+ Adc_PrescaleType adcPrescale;\r
+}Adc_HWConfigurationType;\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONVERSION_TIME_2_CLOCKS,\r
+ ADC_CONVERSION_TIME_8_CLOCKS,\r
+ ADC_CONVERSION_TIME_64_CLOCKS,\r
+ ADC_CONVERSION_TIME_128_CLOCKS\r
+}Adc_ConversionTimeType;\r
+\r
+/* Channel definitions, std container */\r
+typedef struct\r
+{\r
+ Adc_ConversionTimeType adcChannelConvTime;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcLow;\r
+ // NOT SUPPORTED Adc_VoltageSourceType adcChannelRefVoltSrcHigh;\r
+ // NOT SUPPORTED Adc_ResolutionType adcChannelResolution;\r
+ // NOT SUPPORTED Adc_CalibrationType adcChannelCalibrationEnable;\r
+} Adc_ChannelConfigurationType;\r
+\r
+/* Used ?? */\r
+typedef struct\r
+{\r
+ uint8 notifictionEnable;\r
+ Adc_ValueGroupType * resultBufferPtr;\r
+ Adc_StatusType groupStatus;\r
+} Adc_GroupStatus;\r
+\r
+\r
+/* Std-type, supplier defined */\r
+typedef enum\r
+{\r
+ ADC_CONV_MODE_DISABLED,\r
+ ADC_CONV_MODE_ONESHOT = 1,\r
+ ADC_CONV_MODE_CONTINOUS = 9,\r
+} Adc_GroupConvModeType;\r
+\r
+/* Implementation specific */\r
+typedef struct\r
+{\r
+ // NOT SUPPORTED Adc_GroupAccessModeType accessMode;\r
+ Adc_GroupConvModeType conversionMode;\r
+ Adc_TriggerSourceType triggerSrc;\r
+ // NOT SUPPORTED Adc_HwTriggerSignalType hwTriggerSignal;\r
+ // NOT SUPPORTED Adc_HwTriggerTimerType hwTriggerTimer;\r
+ void (*groupCallback)(void);\r
+ // NOT SUPPORTED Adc_StreamBufferModeType streamBufferMode;\r
+ // NOT SUPPORTED Adc_StreamNumSampleType streamNumSamples;\r
+ const Adc_ChannelType *channelList;\r
+ Adc_ValueGroupType *resultBuffer;\r
+ // NOT SUPPORTED Adc_CommandType *commandBuffer;\r
+ Adc_ChannelType numberOfChannels;\r
+ Adc_GroupStatus *status;\r
+ // NOT SUPPORTED Dma_ChannelType dmaCommandChannel;\r
+ // NOT SUPPORTED Dma_ChannelType dmaResultChannel;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMACommands;\r
+ // NOT SUPPORTED const struct tcd_t * groupDMAResults;\r
+} Adc_GroupDefType;\r
+\r
+/* Non-standard type */\r
+typedef struct\r
+{\r
+ const Adc_HWConfigurationType* hwConfigPtr;\r
+ const Adc_ChannelConfigurationType* channelConfigPtr;\r
+ const uint16_t nbrOfChannels;\r
+ const Adc_GroupDefType* groupConfigPtr;\r
+ const uint16_t nbrOfGroups;\r
+} Adc_ConfigType;\r
+\r
+extern const Adc_ConfigType AdcConfig [];\r
+\r
+\r
+#endif /*ADC_CFG_H_*/\r
--- /dev/null
+/*
+* Configuration of module Can (Can_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+
+#if (CAN_SW_MAJOR_VERSION != 1)
+#error "Can: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef CAN_CFG_H_\r
+#define CAN_CFG_H_\r
+\r
+// Number of controller configs\r
+#define CAN_ARC_CTRL_CONFIG_CNT 1\r
+\r
+#define CAN_DEV_ERROR_DETECT STD_OFF\r
+#define CAN_VERSION_INFO_API STD_OFF\r
+#define CAN_MULTIPLEXED_TRANSMISSION STD_OFF\r
+#define CAN_WAKEUP_SUPPORT STD_OFF // Not supported\r
+#define CAN_HW_TRANSMIT_CANCELLATION STD_OFF // Not supported\r
+\r
+\r
+// Start stm32 unique
+typedef enum {\r
+ CAN_CTRL_1 = 0,\r
+ CAN_CTRL_2 = 1,\r
+ CAN_CONTROLLER_CNT = 2\r
+}CanControllerIdType;\r
+// End stm32 unique
+\r
+\r
+typedef enum {\r
+ CAN_ID_TYPE_EXTENDED,\r
+ CAN_ID_TYPE_MIXED,\r
+ CAN_ID_TYPE_STANDARD,\r
+} Can_IdTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_OBJECT_TYPE_RECEIVE,\r
+ CAN_OBJECT_TYPE_TRANSMIT,\r
+} Can_ObjectTypeType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_HANDLE_TYPE_BASIC,\r
+ CAN_ARC_HANDLE_TYPE_FULL\r
+} Can_Arc_HohType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_2,\r
+ NUM_OF_HTHS\r
+} Can_Arc_HTHType;\r
+\r
+\r
+typedef enum {\r
+ HWObj_1,\r
+ NUM_OF_HRHS\r
+} Can_Arc_HRHType;\r
+\r
+\r
+typedef struct {\r
+ void (*CancelTxConfirmation)( const Can_PduType *);\r
+ void (*RxIndication)( uint8 ,Can_IdType ,uint8 , const uint8 * );\r
+ void (*ControllerBusOff)(uint8);\r
+ void (*TxConfirmation)(PduIdType);\r
+ void (*ControllerWakeup)(uint8);\r
+ void (*Arc_Error)(uint8,Can_Arc_ErrorType);\r
+} Can_CallbackType;\r
+\r
+\r
+typedef struct {\r
+ // Specifies the InstanceId of this module instance. If only one instance is\r
+ // present it shall have the Id 0\r
+ int CanIndex;\r
+} Can_GeneralType;
+
+typedef uint32_t Can_FilterMaskType;
+\r
+typedef struct Can_HardwareObjectStruct {\r
+ // Specifies the type (Full-CAN or Basic-CAN) of a hardware object.\r
+ Can_Arc_HohType CanHandleType;\r
+\r
+ // Specifies whether the IdValue is of type - standard identifier - extended\r
+ // identifier - mixed mode ImplementationType: Can_IdType\r
+ Can_IdTypeType CanIdType;\r
+\r
+ // Specifies (together with the filter mask) the identifiers range that passes\r
+ // the hardware filter.\r
+ uint32 CanIdValue;\r
+\r
+ // Holds the handle ID of HRH or HTH. The value of this parameter is unique\r
+ // in a given CAN Driver, and it should start with 0 and continue without any\r
+ // gaps. The HRH and HTH Ids are defined under two different name-spaces.\r
+ // Example: HRH0-0, HRH1-1, HTH0-2, HTH1-3\r
+ uint32 CanObjectId;\r
+\r
+ // Specifies if the HardwareObject is used as Transmit or as Receive object\r
+ Can_ObjectTypeType CanObjectType;\r
+\r
+ // Reference to the filter mask that is used for hardware filtering togerther\r
+ // with the CAN_ID_VALUE\r
+ Can_FilterMaskType *CanFilterMaskRef;\r
+\r
+ // A "1" in this mask tells the driver that that HW Message Box should be\r
+ // occupied by this Hoh. A "1" in bit 31(ppc) occupies Mb 0 in HW.\r
+ uint32 Can_Arc_MbMask;\r
+\r
+ // End Of List. Set to TRUE is this is the last object in the list.\r
+ boolean Can_Arc_EOL;\r
+} Can_HardwareObjectType;\r
+\r
+\r
+typedef enum {\r
+ CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ CAN_ARC_PROCESS_TYPE_POLLING,\r
+} Can_Arc_ProcessType;\r
+\r
+\r
+typedef struct {\r
+\r
+ // Enables / disables API Can_MainFunction_BusOff() for handling busoff\r
+ // events in polling mode.\r
+ // INTERRUPT or POLLING\r
+ Can_Arc_ProcessType CanBusOffProcessing;\r
+\r
+ // Defines if a CAN controller is used in the configuration.\r
+ boolean CanControllerActivation;\r
+\r
+ // Specifies the buadrate of the controller in kbps.\r
+ uint32 CanControllerBaudRate;\r
+\r
+ // This parameter provides the controller ID which is unique in a given CAN\r
+ // Driver. The value for this parameter starts with 0 and continue without any\r
+ // gaps.\r
+ CanControllerIdType CanControllerId;\r
+\r
+ // Specifies propagation delay in time quantas.\r
+ uint32 CanControllerPropSeg;\r
+\r
+ // Specifies phase segment 1 in time quantas.\r
+ uint32 CanControllerSeg1;\r
+\r
+ // Specifies phase segment 2 in time quantas.\r
+ uint32 CanControllerSeg2;\r
+\r
+ // Specifies the time quanta for the controller. The calculation of the resulting\r
+ // prescaler value depending on module clocking and time quanta shall be\r
+ // done offline Hardware specific.\r
+ uint32 CanControllerTimeQuanta;\r
+\r
+ // Enables / disables API Can_MainFunction_Read() for handling PDU\r
+ // reception events in polling mode.\r
+ Can_Arc_ProcessType CanRxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Write() for handling PDU\r
+ // transmission events in polling mode.\r
+ Can_Arc_ProcessType CanTxProcessing;\r
+\r
+ // Enables / disables API Can_MainFunction_Wakeup() for handling wakeup\r
+ // events in polling mode.\r
+ Can_Arc_ProcessType CanWakeupProcessing;\r
+\r
+ // Reference to the CPU clock configuration, which is set in the MCU driver\r
+ // configuration\r
+ uint32 CanCpuClockRef;\r
+\r
+ // This parameter contains a reference to the Wakeup Source for this\r
+ // controller as defined in the ECU State Manager. Implementation Type:\r
+ // reference to EcuM_WakeupSourceType\r
+ uint32 CanWakeupSourceRef;\r
+\r
+ // List of Hoh id's that belong to this controller\r
+ const Can_HardwareObjectType *Can_Arc_Hoh;\r
+\r
+ boolean Can_Arc_Loopback;\r
+\r
+ // Set this to use the fifo\r
+ boolean Can_Arc_Fifo;\r
+} Can_ControllerConfigType;\r
+\r
+\r
+typedef struct {\r
+ const Can_ControllerConfigType *CanController;\r
+ \r
+ // Callbacks( Extension )\r
+ const Can_CallbackType *CanCallbacks;\r
+} Can_ConfigSetType;\r
+\r
+\r
+typedef struct {\r
+ // This is the multiple configuration set container for CAN Driver\r
+ // Multiplicity 1..*\r
+ const Can_ConfigSetType *CanConfigSet;\r
+ // This container contains the parameters related each CAN\r
+ // Driver Unit.\r
+ // Multiplicity 1..*\r
+ const Can_GeneralType *CanGeneral;\r
+} Can_ConfigType;\r
+\r
+\r
+extern const Can_ConfigType CanConfigData;\r
+extern const Can_ControllerConfigType CanControllerConfigData[];\r
+extern const Can_ConfigSetType Can_ConfigSet;\r
+\r
+#endif /*CAN_CFG_H_*/\r
--- /dev/null
+/*
+* Configuration of module Can (Can_Lcfg.c)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.0
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Wed Apr 21 10:15:00 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include "Can.h"\r
+#include "CanIf_Cbk.h"\r
+\r
+\r
+Can_FilterMaskType Can_FilterMaskConfigData_Controller_1_Mask_1[] = {
+ 0xffffffff,
+ 0xffffffff,
+};\r
+\r
+const Can_HardwareObjectType CanHardwareObjectConfig_Controller_1[] = {\r
+ {\r
+ .CanObjectId = HWObj_1,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_RECEIVE,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 0,\r
+ },\r
+ {\r
+ .CanObjectId = HWObj_2,\r
+ .CanHandleType = CAN_ARC_HANDLE_TYPE_BASIC,\r
+ .CanIdType = CAN_ID_TYPE_EXTENDED,\r
+ .CanObjectType = CAN_OBJECT_TYPE_TRANSMIT,\r
+ .CanFilterMaskRef = &Can_FilterMaskConfigData_Controller_1_Mask_1[0],\r
+ \r
+ .Can_Arc_MbMask = 0x0,\r
+ .Can_Arc_EOL = 1,\r
+ },\r
+};\r
+\r
+\r
+const Can_ControllerConfigType CanControllerConfigData[] =\r
+{\r
+ {\r
+ .CanControllerActivation = TRUE,\r
+ .CanControllerBaudRate = 125,\r
+ .CanControllerId = CAN_CTRL_1,\r
+ .CanControllerPropSeg = 0,\r
+ .CanControllerSeg1 = 12,\r
+ .CanControllerSeg2 = 1,\r
+ .CanBusOffProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanRxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanTxProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanWakeupProcessing = CAN_ARC_PROCESS_TYPE_INTERRUPT,\r
+ .CanCpuClockRef = 0,\r
+ .Can_Arc_Hoh = &CanHardwareObjectConfig_Controller_1[0],\r
+ .Can_Arc_Loopback = FALSE,\r
+ .Can_Arc_Fifo = 0,\r
+ },\r
+};\r
+\r
+const Can_CallbackType CanCallbackConfigData = {\r
+ NULL, //CanIf_CancelTxConfirmation,\r
+ CanIf_RxIndication,\r
+ CanIf_ControllerBusOff,\r
+ CanIf_TxConfirmation,\r
+ NULL, //CanIf_ControllerWakeup,\r
+ CanIf_Arc_Error,\r
+};\r
+\r
+const Can_ConfigSetType CanConfigSetData =\r
+{\r
+ .CanController = CanControllerConfigData,\r
+ .CanCallbacks = &CanCallbackConfigData,\r
+};\r
+\r
+const Can_ConfigType CanConfigData = {\r
+ .CanConfigSet = &CanConfigSetData,\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef DIO_CFG_H_\r
+#define DIO_CFG_H_\r
+\r
+#define DIO_VERSION_INFO_API STD_ON\r
+#define DIO_DEV_ERROR_DETECT STD_ON\r
+#define DIO_END_OF_LIST -1\r
+\r
+/** @name DIO channels\r
+ * HW specific dio channels.\r
+ */\r
+// Pin Name GPIO(PCR)Num\r
+//@{\r
+//* req DIO015 */\r
+//* req DIO017 */\r
+typedef enum\r
+{\r
+ DIO_CHANNEL_A0,\r
+ DIO_CHANNEL_A1,\r
+ DIO_CHANNEL_A2,\r
+ DIO_CHANNEL_A3,\r
+ DIO_CHANNEL_A4,\r
+ DIO_CHANNEL_A5,\r
+ DIO_CHANNEL_A6,\r
+ DIO_CHANNEL_A7,\r
+ DIO_CHANNEL_A8,\r
+ DIO_CHANNEL_A9,\r
+ DIO_CHANNEL_A10,\r
+ DIO_CHANNEL_A11,\r
+ DIO_CHANNEL_A12,\r
+ DIO_CHANNEL_A13,\r
+ DIO_CHANNEL_A14,\r
+ DIO_CHANNEL_A15,\r
+\r
+ DIO_CHANNEL_B0,\r
+ DIO_CHANNEL_B1,\r
+ DIO_CHANNEL_B2,\r
+ DIO_CHANNEL_B3,\r
+ DIO_CHANNEL_B4,\r
+ DIO_CHANNEL_B5,\r
+ DIO_CHANNEL_B6,\r
+ DIO_CHANNEL_B7,\r
+ DIO_CHANNEL_B8,\r
+ DIO_CHANNEL_B9,\r
+ DIO_CHANNEL_B10,\r
+ DIO_CHANNEL_B11,\r
+ DIO_CHANNEL_B12,\r
+ DIO_CHANNEL_B13,\r
+ DIO_CHANNEL_B14,\r
+ DIO_CHANNEL_B15,\r
+\r
+ DIO_CHANNEL_C0,\r
+ DIO_CHANNEL_C1,\r
+ DIO_CHANNEL_C2,\r
+ DIO_CHANNEL_C3,\r
+ DIO_CHANNEL_C4,\r
+ DIO_CHANNEL_C5,\r
+ DIO_CHANNEL_C6,\r
+ DIO_CHANNEL_C7,\r
+ DIO_CHANNEL_C8,\r
+ DIO_CHANNEL_C9,\r
+ DIO_CHANNEL_C10,\r
+ DIO_CHANNEL_C11,\r
+ DIO_CHANNEL_C12,\r
+ DIO_CHANNEL_C13,\r
+ DIO_CHANNEL_C14,\r
+ DIO_CHANNEL_C15,\r
+\r
+ DIO_CHANNEL_D0,\r
+ DIO_CHANNEL_D1,\r
+ DIO_CHANNEL_D2,\r
+ DIO_CHANNEL_D3,\r
+ DIO_CHANNEL_D4,\r
+ DIO_CHANNEL_D5,\r
+ DIO_CHANNEL_D6,\r
+ DIO_CHANNEL_D7,\r
+ DIO_CHANNEL_D8,\r
+ DIO_CHANNEL_D9,\r
+ DIO_CHANNEL_D10,\r
+ DIO_CHANNEL_D11,\r
+ DIO_CHANNEL_D12,\r
+ DIO_CHANNEL_D13,\r
+ DIO_CHANNEL_D14,\r
+ DIO_CHANNEL_D15,\r
+\r
+ DIO_CHANNEL_E0,\r
+ DIO_CHANNEL_E1,\r
+ DIO_CHANNEL_E2,\r
+ DIO_CHANNEL_E3,\r
+ DIO_CHANNEL_E4,\r
+ DIO_CHANNEL_E5,\r
+ DIO_CHANNEL_E6,\r
+ DIO_CHANNEL_E7,\r
+ DIO_CHANNEL_E8,\r
+ DIO_CHANNEL_E9,\r
+ DIO_CHANNEL_E10,\r
+ DIO_CHANNEL_E11,\r
+ DIO_CHANNEL_E12,\r
+ DIO_CHANNEL_E13,\r
+ DIO_CHANNEL_E14,\r
+ DIO_CHANNEL_E15,\r
+\r
+ DIO_CHANNEL_F0,\r
+ DIO_CHANNEL_F1,\r
+ DIO_CHANNEL_F2,\r
+ DIO_CHANNEL_F3,\r
+ DIO_CHANNEL_F4,\r
+ DIO_CHANNEL_F5,\r
+ DIO_CHANNEL_F6,\r
+ DIO_CHANNEL_F7,\r
+ DIO_CHANNEL_F8,\r
+ DIO_CHANNEL_F9,\r
+ DIO_CHANNEL_F10,\r
+ DIO_CHANNEL_F11,\r
+ DIO_CHANNEL_F12,\r
+ DIO_CHANNEL_F13,\r
+ DIO_CHANNEL_F14,\r
+ DIO_CHANNEL_F15,\r
+\r
+} Dio_ChannelType;\r
+//@}\r
+\r
+/** HW specific DIO port definitions. */\r
+/** @req DIO018 */\r
+/** @req DIO020 */\r
+typedef enum {\r
+ DIO_PORT_A,\r
+ DIO_PORT_B,\r
+ DIO_PORT_C,\r
+ DIO_PORT_D,\r
+ DIO_PORT_E,\r
+ DIO_PORT_F,\r
+} Dio_PortType;\r
+\r
+/** @req DIO021 */\r
+/** @req DIO022 */\r
+typedef struct\r
+{\r
+ Dio_PortType port;\r
+ uint16 offset;\r
+ uint16 mask;\r
+} Dio_ChannelGroupType;\r
+\r
+/** @req DIO023 */\r
+typedef uint16 Dio_LevelType;\r
+\r
+/** @req DIO024 */\r
+typedef uint16 Dio_PortLevelType;\r
+\r
+#define LED_CHANNEL1 (DIO_CHANNEL_D3)\r
+#define LED_CHANNEL2 (DIO_CHANNEL_D4)\r
+#define LED_CHANNEL3 (DIO_CHANNEL_D7)\r
+#define LED_CHANNEL4 (DIO_CHANNEL_D13)\r
+\r
+#define LED_PORT (DIO_PORT_D)\r
+\r
+#define LED_GROUP (&DioConfigData[0])\r
+\r
+// Channels\r
+extern const Dio_ChannelType DioChannelConfigData[];\r
+#define CHANNEL_PTR (&DioChannelConfigData)\r
+\r
+// Port\r
+extern const Dio_PortType DioPortConfigData[];\r
+#define PORT_PTR (&DioPortConfigData)\r
+\r
+// Channel group\r
+extern const Dio_ChannelGroupType DioConfigData[];\r
+#define CHANNEL_GRP_PTR (&DioConfigData)\r
+\r
+#endif /* DIO_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+#include "Dio.h"\r
+#include "Dio_Cfg.h"\r
+\r
+const Dio_ChannelType DioChannelConfigData[] =\r
+{\r
+ LED_CHANNEL1,\r
+ LED_CHANNEL2,\r
+ LED_CHANNEL3,\r
+ LED_CHANNEL4,\r
+ DIO_END_OF_LIST,\r
+};\r
+\r
+const Dio_PortType DioPortConfigData[] =\r
+{\r
+ LED_PORT,\r
+ DIO_END_OF_LIST\r
+};\r
+\r
+const Dio_ChannelGroupType DioConfigData[] =\r
+{\r
+ { .port = DIO_PORT_D, .offset = 0, .mask = 0x1094, },\r
+ { .port = DIO_END_OF_LIST, .offset = DIO_END_OF_LIST, .mask = DIO_END_OF_LIST, },\r
+};\r
+\r
+uint32 Dio_GetPortConfigSize(void)\r
+{\r
+ return sizeof(DioConfigData);\r
+}\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include "Fls.h"\r
+#include <stdlib.h>\r
+\r
+\r
+#define KB *1024\r
+
+const Fls_SectorType fls_SectorList[] = {
+ {
+ .FlsSectorStartaddress = (Fls_AddressType)0x08000000, // Start address of this sector
+ .FlsPageSize = (Fls_LengthType)(1 KB), // Page size of 1k
+ .FlsSectorSize = (Fls_LengthType)(1 KB),
+ // Number of continuous sectors with the above characteristics.
+ .FlsNumberOfSectors = (uint32)255
+ }
+};
+\r
+\r
+const Fls_ConfigType FlsConfigSet[]=\r
+{\r
+ {\r
+ .FlsSectorList = &fls_SectorList[0],\r
+ .FlsSectorListSize = sizeof(fls_SectorList)/sizeof(Fls_SectorType),\r
+ .FlsBlockToPartitionMap = NULL,\r
+ }\r
+};\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef FLS_CFG_H_\r
+#define FLS_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define FLS_BASE_ADDRESS 0x08000000\r
+#define FLS_TOTAL_SIZE 0x40000 // from addr 0x0800_0000 to 0x0804_0000\r
+\r
+// Configuration description of a flashable sector\r
+typedef struct {\r
+ // Number of continuous sectors with the above characteristics.\r
+ Fls_LengthType FlsNumberOfSectors;\r
+\r
+ // Size of one page of this sector. Implementation Type: Fls_LengthType.\r
+ Fls_LengthType FlsPageSize;\r
+\r
+ // Size of this sector. Implementation Type: Fls_LengthTyp\r
+ Fls_LengthType FlsSectorSize;\r
+\r
+ // Start address of this sector\r
+ Fls_AddressType FlsSectorStartaddress;\r
+\r
+} Fls_SectorType;\r
+\r
+\r
+typedef struct {\r
+ // List of flash:able sectors and pages\r
+ const Fls_SectorType *FlsSectorList;\r
+\r
+ // Size of List of the FlsSectorList\r
+ const uint32 FlsSectorListSize;\r
+\r
+ uint8 *FlsBlockToPartitionMap;\r
+\r
+} Fls_ConfigType;\r
+\r
+extern const Fls_ConfigType FlsConfigSet[];\r
+\r
+\r
+#endif /* FLS_CFG_H_ */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_C_\r
+#define MCU_CFG_C_\r
+\r
+#include "Mcu.h"\r
+\r
+Mcu_RamSectorSettingConfigType Mcu_RamSectorSettingConfigData[] = {\r
+ {\r
+ // This parameter shall represent the Data pre-setting to be initialized\r
+ .McuRamDefaultValue = 0,\r
+\r
+ // This parameter shall represent the MCU RAM section base address\r
+ .McuRamSectionBaseAddress = 0,\r
+\r
+ // This parameter shall represent the MCU RAM Section size\r
+ .McuRamSectionSize = 0xFF,\r
+ }\r
+};\r
+
+
+const Mcu_PerClockConfigType McuPerClockConfigData =
+{
+ .AHBClocksEnable = RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_ETH_MAC |
+ RCC_AHBPeriph_ETH_MAC_Tx | RCC_AHBPeriph_ETH_MAC_Rx,
+ .APB1ClocksEnable = RCC_APB1Periph_TIM2 | RCC_APB1Periph_CAN1,
+ .APB2ClocksEnable = (RCC_APB2Periph_ADC1 | RCC_APB2Periph_GPIOA |
+ RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC |
+ RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO),
+};
+\r
+Mcu_ClockSettingConfigType Mcu_ClockSettingConfigData[] =\r
+{\r
+ {\r
+ .McuClockReferencePointFrequency = 25000000UL,\r
+ .Pll1 = 9,\r
+ .Pll2 = 8,\r
+ .Pll3 = 0,\r
+ },\r
+};\r
+\r
+\r
+ const Mcu_ConfigType McuConfigData[] = {\r
+ {\r
+ // Enables/Disables clock failure notification. In case this feature is not supported\r
+ // by HW the setting should be disabled.\r
+ .McuClockSrcFailureNotification = 0,\r
+\r
+ // This parameter shall represent the number of Modes available for the\r
+ // MCU. calculationFormula = Number of configured McuModeSettingConf\r
+// .McuNumberOfMcuModes = 1, /* NOT USED */\r
+\r
+ // This parameter shall represent the number of RAM sectors available for\r
+ // the MCU. calculationFormula = Number of configured McuRamSectorSet-\r
+ // tingConf\r
+ .McuRamSectors = 1,\r
+\r
+ // This parameter shall represent the number of clock setting available for\r
+ // the MCU.\r
+ .McuClockSettings = MCU_NBR_OF_CLOCKS,\r
+\r
+ // Default clock frequency used\r
+ .McuDefaultClockSettings = MCU_CLOCKTYPE_EXT_REF_25MHZ,\r
+\r
+ // This parameter relates to the MCU specific reset configuration. This ap-\r
+ // plies to the function Mcu_PerformReset, which performs a microcontroller\r
+ // reset using the hardware feature of the microcontroller.\r
+// .McuResetSetting = 0, /* NOT USED */\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Clock settings of the MCU. Please see MCU031 for more in-\r
+ // formation on the MCU clock settings.\r
+ .McuClockSettingConfig = &Mcu_ClockSettingConfigData[0],\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // Mode setting of the MCU. Please see MCU035 for more infor-\r
+ // mation on the MCU mode settings.\r
+// .McuModeSettingConfig = 0,\r
+\r
+ // This container contains the configuration (parameters) for the\r
+ // RAM Sector setting. Please see MCU030 for more information\r
+ // on RAM sec-tor settings.\r
+ .McuRamSectorSettingConfig = &Mcu_RamSectorSettingConfigData[0],\r
+ },\r
+};\r
+\r
+#endif /*MCU_CFG_C_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#ifndef MCU_CFG_H_\r
+#define MCU_CFG_H_\r
+\r
+#define MCU_DEV_ERROR_DETECT STD_ON\r
+#define MCU_PERFORM_RESET_API STD_ON\r
+#define MCU_VERSION_INFO_API STD_ON\r
+\r
+#include "Std_Types.h"\r
+
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
+
+#ifndef STM32F10X_CL
+ #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+ #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+#else
+ #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+ #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
+ #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
+ #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
+#endif
+
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
+#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+
+typedef struct {
+ uint32 AHBClocksEnable;
+ uint32 APB1ClocksEnable;
+ uint32 APB2ClocksEnable;
+} Mcu_PerClockConfigType;
+
+extern const Mcu_PerClockConfigType McuPerClockConfigData;
+\r
+typedef enum {\r
+ MCU_CLOCKTYPE_EXT_REF_25MHZ = 0,\r
+ MCU_NBR_OF_CLOCKS,\r
+} Mcu_ClockType;\r
+\r
+#define MCU_DEFAULT_CONFIG McuConfigData[0]\r
+\r
+#endif /*MCU_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+#include "Port_Cfg.h"\r
+\r
+\r
+typedef enum {\r
+ PORTA,\r
+ PORTB,\r
+ PORTC,\r
+ PORTD,\r
+ PORTE,\r
+ NUMBER_OF_PORTS\r
+} Port_PortType;\r
+\r
+const u32 remaps[] = {\r
+ GPIO_Remap_ETH,\r
+ GPIO_Remap2_CAN1,\r
+};\r
+\r
+const Port_PortConfigType porta = {\r
+ .port = GPIOA,\r
+ .pinCount = 3,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_2,\r
+ .GPIO_Mode = GPIO_Mode_AF_PP,\r
+ .GPIO_Speed = GPIO_Speed_50MHz\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3,\r
+ .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
+ .GPIO_Speed = GPIO_Speed_50MHz\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_8,\r
+ .GPIO_Mode = GPIO_Mode_AF_PP,\r
+ .GPIO_Speed = GPIO_Speed_50MHz\r
+ },\r
+ }\r
+};\r
+\r
+const Port_PortConfigType portb = {\r
+ .port = GPIOB,\r
+ .pinCount = 2,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13,\r
+ .GPIO_Mode = GPIO_Mode_AF_PP,\r
+ .GPIO_Speed = GPIO_Speed_50MHz\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_10,\r
+ .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
+ .GPIO_Speed = GPIO_Speed_50MHz\r
+ },\r
+\r
+ }\r
+};\r
+\r
+const Port_PortConfigType portc = {\r
+ .port = GPIOC,\r
+ .pinCount = 3,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2,\r
+ .GPIO_Mode = GPIO_Mode_AF_PP,\r
+ .GPIO_Speed = GPIO_Speed_50MHz,\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_3,\r
+ .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
+ .GPIO_Speed = GPIO_Speed_50MHz,\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_4,\r
+ .GPIO_Mode = GPIO_Mode_AIN,\r
+ .GPIO_Speed = GPIO_Speed_10MHz,\r
+ },\r
+\r
+ }\r
+};\r
+\r
+const Port_PortConfigType portd = {\r
+ .port = GPIOD,\r
+ .pinCount = 4,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12,\r
+ .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
+ .GPIO_Speed = GPIO_Speed_50MHz,\r
+ },\r
+ /* PD0 is CAN1_RX, remapped: */\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_0,\r
+ .GPIO_Mode = GPIO_Mode_IPU,\r
+ .GPIO_Speed = GPIO_Speed_10MHz\r
+ },\r
+ /* PD1 is CAN1_TX, remapped: */\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_1,\r
+ .GPIO_Mode = GPIO_Mode_AF_PP,\r
+ .GPIO_Speed = GPIO_Speed_10MHz\r
+ },\r
+ {\r
+ .GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_7 | GPIO_Pin_13,\r
+ .GPIO_Mode = GPIO_Mode_Out_PP,\r
+ .GPIO_Speed = GPIO_Speed_10MHz\r
+ },\r
+ }\r
+};\r
+\r
+const Port_PortConfigType porte = {\r
+ .port = GPIOE,\r
+ .pinCount = 1,\r
+ .pins = {\r
+ {\r
+ .GPIO_Pin = 0xffff,\r
+ .GPIO_Mode = GPIO_Mode_IN_FLOATING,\r
+ .GPIO_Speed = GPIO_Speed_2MHz,\r
+ },\r
+ }\r
+};\r
+\r
+const Port_ConfigType PortConfigData = {\r
+ .portCount = NUMBER_OF_PORTS,\r
+ .ports = {\r
+ &porta,\r
+ &portb,\r
+ &portc,\r
+ &portd,\r
+ &porte\r
+ },\r
+\r
+ .remapCount = sizeof(remaps) / sizeof(u32),\r
+ .remaps = &remaps[0]\r
+};\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef PORT_CFG_H_\r
+#define PORT_CFG_H_\r
+\r
+#include "Std_Types.h"\r
+#include "stm32f10x_gpio.h"\r
+\r
+/** Build version info API */\r
+#define PORT_VERSION_INFO_API STD_ON /** @req PORT100 PORT101 */\r
+/** Enable Development Error Trace */\r
+#define PORT_DEV_ERROR_DETECT STD_ON\r
+/** Build change pin direction API */\r
+#define PORT_SET_PIN_DIRECTION_API STD_ON\r
+/** Allow Pin mode changes during runtime (not avail on this CPU) */\r
+#define PORT_SET_PIN_MODE_API STD_ON\r
+\r
+/** HW specific symbolic names of pins */\r
+/** @req PORT013 */\r
+typedef enum{\r
+ PIN1,\r
+} Port_PinType;\r
+\r
+/* Configuration of one specific port */\r
+typedef struct {\r
+ uint16_t pinCount;\r
+ GPIO_TypeDef *port;\r
+ const GPIO_InitTypeDef pins[];\r
+\r
+} Port_PortConfigType;\r
+\r
+/** Top level configuration container */\r
+/** @req PORT073 */\r
+typedef struct {\r
+ uint16_t remapCount;\r
+ const uint32_t* remaps;\r
+\r
+ uint16_t portCount;\r
+ const Port_PortConfigType* ports[];\r
+} Port_ConfigType;\r
+\r
+/** Instance of the top level configuration container */\r
+extern const Port_ConfigType PortConfigData;\r
+\r
+#endif /*PORT_CFG_H_*/\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.c\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+\r
+\r
+#include "Pwm.h"\r
+#include "Pwm_Cfg.h"\r
+\r
+extern void MyPwmNotificationRoutine(void);\r
+\r
+// TODO remove, just put here for lazyness\r
+void MyPwmNotificationRoutine(void){\r
+}\r
+/* -----------------------------------------------------------------------\r
+ TIM4CLK = 72 MHz, Prescaler = 7199, TIM4 counter clock = 72 MHz\r
+ TIM4 ARR Register = 10000 => TIM4 Frequency = TIM4 counter clock/(ARR*(PSC + 1)\r
+ TIM4 Frequency = 1 Hz.\r
+ TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 12.5%\r
+\r
+\r
+ NOTE!!! All channels on one TIM uses the same Time base. The last configured will\r
+ set the Time base.\r
+ ----------------------------------------------------------------------- */\r
+const Pwm_ConfigType PwmConfig = {\r
+ .Channels = {\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_1, 10000, 0x4000/*50%*/, 29, PWM_HIGH),\r
+ PWM_CHANNEL_CONFIG(PWM_CHANNEL_2, 10000, 0x4000/*50%*/, 29, PWM_LOW)\r
+ },\r
+#if PWM_NOTIFICATION_SUPPORTED==ON\r
+ .NotificationHandlers = {\r
+ MyPwmNotificationRoutine, // PWM_CHANNEL_1\r
+ NULL // PWM_CHANNEL_2\r
+ }\r
+#endif\r
+};\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Pwm_Cfg.h\r
+ *\r
+ * Created on: 2009-okt-02\r
+ * Author: jonte\r
+ */\r
+#ifndef PWM_CFG_H_\r
+#define PWM_CFG_H_\r
+\r
+/****************************************************************************\r
+ * Global configuration options and defines\r
+ */\r
+/*\r
+ * PWM003: The detection of development errors is configurable (STD_ON/STD_OFF) at\r
+ * pre-compile time. The switch PwmDevErorDetect shall activate or disable\r
+ * the detection of all development errors\r
+ */\r
+#define PWM_DEV_EROR_DETECT STD_ON\r
+#define PWM_GET_OUTPUT_STATE STD_ON\r
+#define PWM_STATICALLY_CONFIGURED STD_OFF\r
+#define PWM_NOTIFICATION_SUPPORTED STD_ON\r
+\r
+#define PWM_SET_PERIOD_AND_DUTY STD_ON\r
+\r
+/*\r
+ * PWM132: Switch for enabling the update of duty cycle parameter at the end\r
+ * of the current period.\r
+ *\r
+ * Note: Currently only STD_ON mode is supported.\r
+ */\r
+#define PWM_DUTYCYCLE_UPDATED_ENDPERIOD STD_ON\r
+\r
+/*\r
+ * Setting to STD_ON freezes the current output state of a PWM channel when in\r
+ * debug mode.\r
+ */\r
+#define PWM_FREEZE_ENABLE STD_ON\r
+\r
+typedef uint16 Pwm_PeriodType;\r
+\r
+/*\r
+ * PWM106: This is implementation specific but not all values may be valid\r
+ * within the type. This shall be chosen in order to have the most efficient\r
+ * implementation on a specific microcontroller platform.\r
+ *\r
+ * PWM106 => Pwm_ChannelType == eemios channel id.\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_11 = 0, // TIM1 Channel 1\r
+ PWM_CHANNEL_12,\r
+ PWM_CHANNEL_13,\r
+ PWM_CHANNEL_14,\r
+ PWM_CHANNEL_21, // TIM2 Channel 1\r
+ PWM_CHANNEL_22,\r
+ PWM_CHANNEL_23,\r
+ PWM_CHANNEL_24,\r
+ PWM_CHANNEL_31, // TIM3 Channel 1\r
+ PWM_CHANNEL_32,\r
+ PWM_CHANNEL_33,\r
+ PWM_CHANNEL_34,\r
+ PWM_CHANNEL_41, // TIM4 Channel 1\r
+ PWM_CHANNEL_42,\r
+ PWM_CHANNEL_43,\r
+ PWM_CHANNEL_44,\r
+ PWM_TOTAL_NOF_CHANNELS,\r
+} Pwm_ChannelType;\r
+\r
+/****************************************************************************\r
+ * Enumeration of channels\r
+ * Maps a symbolic name to a hardware channel\r
+ */\r
+typedef enum {\r
+ PWM_CHANNEL_1 = PWM_CHANNEL_23, //PB10\r
+ PWM_CHANNEL_2 = PWM_CHANNEL_24, //PB11\r
+ PWM_NUMBER_OF_CHANNELS = 2\r
+} Pwm_NamedChannelsType;\r
+\r
+\r
+/* NEW NEW */\r
+\r
+typedef enum {\r
+ PWM_CHANNEL_PRESCALER_1=0,\r
+ PWM_CHANNEL_PRESCALER_2,\r
+ PWM_CHANNEL_PRESCALER_3,\r
+ PWM_CHANNEL_PRESCALER_4,\r
+} Pwm_ChannelPrescalerType;\r
+\r
+#define DUTY_AND_PERIOD(_duty,_period) .duty = (_duty*_period)>>15, .period = _period\r
+\r
+typedef struct {\r
+ /* Number of duty ticks */\r
+ uint32_t duty:32;\r
+ /* Length of period, in ticks */\r
+ uint32_t period:32;\r
+ /* Counter */\r
+ uint32_t counter:32;\r
+ /* Enable freezing the channel when in debug mode */\r
+ uint32_t freezeEnable:1;\r
+ /* Disable output */\r
+ uint32_t outputDisable:1;\r
+ /* Select which bus disables the bus\r
+ * TODO: Figure out how this works, i.e. what bus does it refer to? */\r
+ uint32_t outputDisableSelect:2;\r
+ /* Prescale the emios clock some more? */\r
+ Pwm_ChannelPrescalerType prescaler:2;\r
+ /* Prescale the emios clock some more? */\r
+ uint32_t usePrescaler:1;\r
+ /* Whether to use DMA. Currently unsupported */\r
+ uint32_t useDma:1;\r
+ uint32_t reserved_2:1;\r
+ /* Input filter. Ignored in output mode. */\r
+ uint32_t inputFilter:4;\r
+ /* Input filter clock source. Ignored in output mode */\r
+ uint32_t filterClockSelect:1;\r
+ /* Enable interrupts/flags on this channel? Required for DMA as well. */\r
+ uint32_t flagEnable:1;\r
+ uint32_t reserved_3:3;\r
+ /* Trigger a match on channel A */\r
+ uint32_t forceMatchA:1;\r
+ /* Triggers a match on channel B */\r
+ uint32_t forceMatchB:1;\r
+ uint32_t reserved_4:1;\r
+ /* We can use different buses for the counter. Use the internal counter */\r
+ uint32_t busSelect:2;\r
+ /* What edges to flag on? */\r
+ uint32_t edgeSelect:1;\r
+ /* Polarity of the channel */\r
+ uint32_t edgePolarity:1;\r
+ /* EMIOS mode. 0x58 for buffered output PWM */\r
+ uint32_t mode:7;\r
+} Pwm_ChannelRegisterType;\r
+\r
+typedef struct {\r
+ Pwm_ChannelRegisterType r;\r
+ Pwm_ChannelType channel;\r
+} Pwm_ChannelConfigurationType;\r
+\r
+\r
+typedef struct {\r
+ Pwm_ChannelConfigurationType Channels[PWM_NUMBER_OF_CHANNELS];\r
+#if PWM_NOTIFICATION_SUPPORTED==STD_ON\r
+ Pwm_NotificationHandlerType NotificationHandlers[PWM_NUMBER_OF_CHANNELS];\r
+#endif\r
+} Pwm_ConfigType;\r
+\r
+// Channel configuration macro.\r
+#define PWM_CHANNEL_CONFIG(_hwchannel, _period, _duty, _prescaler, _polarity) \\r
+ {\\r
+ .channel = _hwchannel,\\r
+ .r = {\\r
+ DUTY_AND_PERIOD(_duty, _period),\\r
+ .freezeEnable = 1,\\r
+ .outputDisable = 0,\\r
+ .usePrescaler = 1,\\r
+ .prescaler = _prescaler,\\r
+ .useDma = 0,\\r
+ .flagEnable = 0, /* See PWM052 */ \\r
+ .busSelect = 3, /* Use the internal counter bus */\\r
+ .edgePolarity = _polarity,\\r
+ .mode = 0\\r
+ }\\r
+ }\r
+\r
+#endif /*PWM_CFG_H_*/\r
/* TODO: Not threadsafe, add DisableAllInterrts()/EnableAllInterrupts() */
-CirqBufferType CirqBuffStatCreate(void *buffer, int maxCnt, size_t dataSize) {
- CirqBufferType cirqbuffer;
- cirqbuffer.bufStart = buffer;
- cirqbuffer.maxCnt = maxCnt;
- cirqbuffer.bufEnd = (char *)cirqbuffer.bufStart + dataSize*maxCnt;
- cirqbuffer.head = cirqbuffer.bufStart;
- cirqbuffer.tail = cirqbuffer.bufStart;
- cirqbuffer.dataSize = dataSize;
- cirqbuffer.currCnt = 0;
- return cirqbuffer;
-}
-CirqBufferType *CirqBuffDynCreate( size_t size, size_t dataSize ) {
- CirqBufferType *cPtr;
- cPtr = malloc(sizeof(CirqBufferType));
+CirqBufferDynType *CirqBuffDynCreate( size_t size, size_t dataSize ) {
+ CirqBufferDynType *cPtr;
+ cPtr = malloc(sizeof(CirqBufferDynType));
if( cPtr == NULL ) {
return NULL;
}
return cPtr;
}
-
-
-int CirqBuffDynDestroy(CirqBufferType *cPtr ) {
+int CirqBuffDynDestroy(CirqBufferDynType *cPtr ) {
free(cPtr->bufStart);
free(cPtr);
return 0;
}
-int CirqBuffPush( CirqBufferType *cPtr, void *dataPtr ) {
+int CirqBuffDynPush( CirqBufferDynType *cPtr, void *dataPtr ) {
uint32_t flags;
+ Irq_Save(flags);
if( (cPtr->currCnt == cPtr->maxCnt) || (cPtr==NULL) ) {
+ Irq_Restore(flags);
return 1; /* No more room */
}
- Irq_Save(flags);
MEMCPY(cPtr->head,dataPtr,cPtr->dataSize);
cPtr->head = (char *)cPtr->head + cPtr->dataSize;
if( cPtr->head == cPtr->bufEnd) {
return 0;
}
-int CirqBuffPop(CirqBufferType *cPtr, void *dataPtr ) {
+int CirqBuffDynPop(CirqBufferDynType *cPtr, void *dataPtr ) {
uint32_t flags;
+ Irq_Save(flags);
if( (cPtr->currCnt == 0) || (cPtr==NULL) ) {
+ Irq_Restore(flags);
return 1;
}
- Irq_Save(flags);
MEMCPY(dataPtr,cPtr->tail,cPtr->dataSize);
cPtr->tail = (char *)cPtr->tail + cPtr->dataSize;
if( cPtr->tail == cPtr->bufEnd) {
return 0;
}
-
-
#ifdef _TEST_CIRQ_BUFFER_DYN_
int main( void ) {
- CirqBufferType *cPtr;
+ CirqBufferDynType *cPtr;
uint8_t *dataPtr;
int rv;
dataPtr = malloc(DATA_SIZE);
dataPtr[0] = 1;
- rv = CirqBuffPush(cPtr,dataPtr);
+ rv = CirqBuffDynPush(cPtr,dataPtr);
assert(rv == 0);
free(dataPtr);
dataPtr = malloc(DATA_SIZE);
dataPtr[0] = 2;
- rv = CirqBuffPush(cPtr,dataPtr);
+ rv = CirqBuffDynPush(cPtr,dataPtr);
assert(rv == 0);
free(dataPtr);
dataPtr = malloc(DATA_SIZE);
- rv = CirqBuffPop(cPtr,dataPtr);
+ rv = CirqBuffDynPop(cPtr,dataPtr);
assert( dataPtr[0] == 1);
assert(rv == 0);
free(dataPtr);
dataPtr = malloc(DATA_SIZE);
- rv = CirqBuffPop(cPtr,dataPtr);
+ rv = CirqBuffDynPop(cPtr,dataPtr);
assert( dataPtr[0] == 2);
assert(rv == 0);
free(dataPtr);
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * A message box implementation.\r
+ *\r
+ * Notes:\r
+ * - Uses heap\r
+ * - Do NOT use Arc_MBoxDestroy() call, it's there for testing purposes only.
+ */\r
+\r
+//#define _TEST_MBOX_\r
+\r
+#include "mbox.h"\r
+#include <stdlib.h>\r
+#include <string.h>\r
+#include <stddef.h>\r
+#include <stdint.h>\r
+\r
+\r
+#ifdef _TEST_MBOX_\r
+#include <stdio.h>\r
+#include <assert.h>\r
+#endif\r
+\r
+\r
+\r
+Arc_MBoxType* Arc_MBoxCreate( size_t size ) {\r
+ Arc_MBoxType *mPtr;\r
+\r
+ mPtr = malloc(sizeof(Arc_MBoxType));\r
+ mPtr->cirqPtr = CirqBuffDynCreate(size,sizeof(void *));\r
+\r
+ return mPtr;\r
+}\r
+\r
+\r
+void Arc_MBoxDestroy( Arc_MBoxType *mPtr ) {\r
+ CirqBuffDynDestroy(mPtr->cirqPtr);\r
+ free(mPtr);\r
+}\r
+\r
+/**\r
+ * Post a message to a box, non-blocking.\r
+ *
+ */\r
+int Arc_MBoxPost( Arc_MBoxType *mPtr, void *msg ) {\r
+ int rv;\r
+ rv = CirqBuffPush(mPtr->cirqPtr,msg);\r
+ if( rv != 0) {\r
+ return 1;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ *
+ */\r
+int Arc_MBoxFetch(Arc_MBoxType *mPtr, void *msg)\r
+{\r
+ int rv;\r
+ rv = CirqBuffPop(mPtr->cirqPtr,msg);\r
+ if(rv != 0) {\r
+ return 1;\r
+ }\r
+ return 0;\r
+}\r
+\r
+#ifdef _TEST_MBOX_\r
+int main( void ) {\r
+ Arc_MBoxType *myBoxes[10];\r
+ uint8_t *dataPtr;\r
+\r
+ printf("Hej\n");\r
+\r
+ myBoxes[0] = Arc_MBoxCreate(2);\r
+ myBoxes[1] = Arc_MBoxCreate(4);\r
+\r
+ dataPtr = malloc(10);\r
+ dataPtr[0] = 1;\r
+ Arc_MBoxPost(myBoxes[0],&dataPtr);\r
+\r
+ dataPtr = malloc(20);\r
+ dataPtr[0] = 2;\r
+ Arc_MBoxPost(myBoxes[0],&dataPtr);\r
+\r
+ Arc_MBoxFetch(myBoxes[0],&dataPtr);\r
+ assert(dataPtr[0] == 1);\r
+ free(dataPtr);\r
+\r
+ Arc_MBoxFetch(myBoxes[0],&dataPtr);\r
+ assert(dataPtr[0] == 2);\r
+ free(dataPtr);\r
+\r
+ Arc_MBoxDestroy(myBoxes[0]);\r
+ Arc_MBoxDestroy(myBoxes[1]);\r
+ return 0;\r
+}\r
+\r
+#endif\r
* snprintf(buf,) -> vsnprintf(buf,)\r
*\r
* IMPLEMENTATION NOTE:\r
- * If printing more than the limit, e.g. using vsnprintf() then\r
- * the emit function will only stop printing, but not interrupted\r
- * (The code will get more complicated that way)\r
+ * - If printing more than the limit, e.g. using vsnprintf() then\r
+ * the emit function will only stop printing, but not interrupted\r
+ * (The code will get more complicated that way)\r
+ * - ANSI-C and POSIX, streams and POSIX filenumbers.\r
+ * POSIX file-numbers exist in unistd.h and are only to be used by the porting\r
+ * newlib interface i.e. newlib_port.c.\r
+ * The filenumber is actually just a cast of the steampointer and save in the member\r
+ * _cookie in FILE.\r
+ *\r
*/\r
\r
#include <unistd.h>\r
\r
//#define HOST_TEST 1\r
\r
-#ifdef HOST_TEST\r
-#define _STDOUT stdout\r
-#define _STDIN stdin\r
-#define _STDERR stderr\r
-#else\r
-#define _STDOUT (FILE *)STDOUT_FILENO\r
-#define _STDINT STDIN_FILENO\r
-#define _STDERR (FILE *)STDERR_FILENO\r
-#endif\r
-\r
-\r
int arc_putchar(int fd, int c);\r
int print(FILE *file, char **buffer, size_t n, const char *format, va_list ap);\r
\r
int rv;\r
\r
va_start(ap, format);\r
- rv = vfprintf(_STDOUT, format, ap);\r
+ rv = vfprintf(stdout, format, ap);\r
va_end(ap);\r
return rv;\r
}\r
}\r
\r
int vprintf(const char *format, va_list ap) {\r
- return vfprintf(_STDOUT, format, ap);\r
+ return vfprintf(stdout, format, ap);\r
}\r
\r
int vsprintf(char *buffer, const char *format, va_list ap) {\r
\r
int vfprintf(FILE *file, const char *format, va_list ap) {\r
int rv;\r
- /* Just print to _STDOUT */\r
+ /* Just print to stdout */\r
rv = print(file,NULL,~(size_t)0, format,ap);\r
return rv;\r
}\r
--(*left);\r
if( buf == NULL ) {\r
#if HOST_TEST\r
- putc(c, _STDOUT);\r
- fflush(_STDOUT);\r
+ putc(c, stdout);\r
+ fflush(stdout);\r
#else\r
- arc_putchar((int)file, c);\r
+ arc_putchar(file->_cookie, c);\r
#endif\r
} else {\r
**buf = c;\r
#define FL_ALIGN_LEFT (1<<4)\r
#define FL_TYPE_SIGNED_INT (1<<5)\r
#define FL_TYPE_UNSIGNED_INT (1<<6)\r
-\r
+#define FL_TYPE_POINTER (1<<7)\r
\r
static void emitString( FILE *file, char **buffer, char *string, int width, int flags, int *left) {\r
char pad;\r
flags |= FL_TYPE_UNSIGNED_INT;\r
emitInt(file,buffer,va_arg( ap, int ),16,width,flags,&left);\r
break;\r
+ case 'p':\r
+ flags |= FL_TYPE_POINTER;\r
+ emitInt(file,buffer,va_arg( ap, int ),16,width,flags,&left);\r
+ break;\r
case 's':\r
str = (char *)va_arg( ap, int );\r
\r
return 0; // Wrong.. but for now.\r
}\r
\r
-#if defined(HOST_TEST)\r
+#if 0\r
int main(void) {\r
char *ptr = NULL;\r
char buff[30];\r
\r
printf("decimal: 00c000 = %06x \n", 0xc000);\r
\r
- fprintf(_STDOUT, "string: %s = foobar \n", "foobar");\r
+ fprintf(stdout, "string: %s = foobar \n", "foobar");\r
sprintf(buff, "string: %s = foobar \n", "foobar");\r
printf("%s",buff);\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#include "sleep.h"\r
+#include "Mcu.h"\r
+#include "Os.h"\r
+\r
+struct timeoutlist_t{\r
+ uint32_t timeout;\r
+ boolean active;\r
+ EventMaskType mask;\r
+};\r
+static struct timeoutlist_t timeoutlist[OS_TASK_CNT];\r
+\r
+static uint32_t ticks = 0;\r
+\r
+void SleepInit()\r
+{\r
+ uint32_t i;\r
+\r
+ for(i=0;i<OS_TASK_CNT;i++)\r
+ {\r
+ timeoutlist[i].active = FALSE;\r
+ }\r
+}\r
+\r
+void Sleep(uint32_t nofTicks, TaskType TaskID, EventMaskType Mask )\r
+{\r
+ uint32 pval = McuE_EnterCriticalSection();\r
+ if(nofTicks == 0){\r
+ nofTicks=1;\r
+ }\r
+ if(TaskID < OS_TASK_CNT){\r
+ timeoutlist[TaskID].timeout = ticks + nofTicks;\r
+ timeoutlist[TaskID].active = TRUE;\r
+ timeoutlist[TaskID].mask = Mask;\r
+ }else{\r
+ /* Error */\r
+ ErrorHook(E_OS_LIMIT);\r
+ }\r
+ McuE_ExitCriticalSection(pval);\r
+}\r
+\r
+\r
+void SleepTask(void)\r
+{\r
+ uint32_t i;\r
+ for(;;) {\r
+ // Alarms every tick\r
+ WaitEvent(EVENT_MASK_SLEEP_ALARM_TASK);\r
+ ClearEvent(EVENT_MASK_SLEEP_ALARM_TASK);\r
+\r
+ ticks++;\r
+\r
+ for(i=0;i<OS_TASK_CNT;i++)\r
+ {\r
+ if((timeoutlist[i].active == TRUE) && (timeoutlist[i].timeout == ticks))\r
+ {\r
+ timeoutlist[i].active = FALSE;\r
+ SetEvent(i,timeoutlist[i].mask);\r
+ }\r
+ }\r
+ }\r
+\r
+}\r
--- /dev/null
+/*\r
+ * tcf_cfg.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+#include "Tcf_Cfg.h"\r
+\r
+//Service includes\r
+#include "sys_monitor.h"\r
+#include "streams.h"\r
+\r
+const char locator_hello[] = "E\0Locator\0Hello\0[\"Locator\",\"SysMonitor\",\"AsciiStreams\",\"FileSystem\"]\0\x03\x01";\r
+\r
+const TCF_Service_Info tcfServiceCfgList[] = {\r
+ {"Locator", handle_LocatorCommand, handle_LocatorEvent},\r
+ {"FileSystem", handle_FileSystemCommand, handle_FileSystemEvent},\r
+ {"SysMonitor", handle_SysMonCommand, handle_SysMonEvent},\r
+ {"AsciiStreams", handle_StreamsCommand, handle_StreamsEvent},\r
+ {"NULL", NULL},\r
+};\r
--- /dev/null
+/*\r
+ * Tcf_Cfg.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef TCF_CFG_H_\r
+#define TCF_CFG_H_\r
+\r
+#include "tcf.h"\r
+\r
+typedef struct {\r
+ char name[16];\r
+ TCF_Service_CommandHandler commandHandler;\r
+ TCF_Service_EventHandler eventHandler;\r
+} TCF_Service_Info;\r
+\r
+extern const TCF_Service_Info tcfServiceCfgList[];\r
+\r
+extern const char locator_hello[];\r
+\r
+#endif /* TCF_CFG_H_ */\r
--- /dev/null
+/*\r
+ * streams.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#include "Std_Types.h"\r
+#include "streams.h"\r
+#include "tcf.h"\r
+#include <string.h>\r
+#include "internal.h"\r
+#include "xtoa.h"\r
+#include "cirq_buffer.h"\r
+\r
+const char Streams_PID[] = "\"PID\":";\r
+const char Streams_Read[] = "read";\r
+const char Streams_Write[] = "write";\r
+const char Streams_Subscribe[] = "subcribe";\r
+const char Streams_Unsubscribe[] = "unsubscribe";\r
+const char Streams_Connect[] = "connect";\r
+const char Streams_Disconnect[] = "disconnect";\r
+const char Streams_EndofStream[] = "eos";\r
+\r
+const char Streams_LostSize[] = "\"lost size\":";\r
+const char Streams_EOS[] = "\"EOS\":";\r
+const char Streams_true[] = "true";\r
+const char Streams_false[] = "false";\r
+\r
+typedef struct {\r
+ char* id;\r
+ char* size;\r
+ char* data;\r
+} TCF_Streams_Command;\r
+\r
+#define TCF_TTY_SIZE 800\r
+\r
+static boolean tty_initialized = FALSE;\r
+static CirqBufferType cirqBuf;\r
+char tty_buffer[TCF_TTY_SIZE] = "";\r
+\r
+void init_streams()\r
+{\r
+ cirqBuf = CirqBuffStatCreate(tty_buffer, TCF_TTY_SIZE, sizeof(char));\r
+ tty_initialized = TRUE;\r
+}\r
+\r
+uint8_t TCF_TTY_SendChar (uint8_t ch)\r
+{\r
+ int rv = 1;\r
+ if(tty_initialized == TRUE){\r
+ rv = CirqBuffPush(&cirqBuf,&ch);\r
+ }\r
+\r
+ return rv;\r
+}\r
+uint32_t TCF_TTY_ReadString(char *str, uint16_t max_len)\r
+{\r
+ char ch;\r
+ int rv;\r
+ int len = 0;\r
+ if(tty_initialized == TRUE){\r
+ do{\r
+ rv = CirqBuffPop(&cirqBuf,&ch);\r
+ if(rv==0){\r
+ len++;\r
+ *str++=ch;\r
+ if(ch == '\0'){\r
+ rv = 1;\r
+ }\r
+ }\r
+ }while((rv == 0) && (len < max_len));\r
+ }\r
+\r
+ return len;\r
+}\r
+\r
+\r
+uint16_t handle_StreamsEvent(TCF_Event* event, char* buf){\r
+ return 0;\r
+}\r
+\r
+static Std_ReturnType parse_read(char* msg, TCF_Streams_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->id = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->size = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+static Std_ReturnType parse_write(char* msg, TCF_Streams_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->id = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->size = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->data = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+static Std_ReturnType parse_id(char* msg, TCF_Streams_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->id = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+uint16_t handle_StreamsCommand(TCF_Command* command, char* buf) {\r
+ char tmp[200] = "";\r
+ TCF_Streams_Command streams_cmd;\r
+\r
+ /* Start building return message */\r
+ start_tcf_field(buf, (char *)TCF_S_R); /* Start */\r
+ append_tcf_field(buf, command->token); /* Token */\r
+\r
+ if (strcmp(command->commandName, Streams_Read) == 0) {\r
+ /* C \95 <token> \95 Streams \95 read \95 <string: stream ID> \95 <int: size> \95 */\r
+ /* R \95 <token> \95 <string: data> \95 <error report> \95 <int: lost size> \95 <boolean: EOS> */\r
+ if(parse_read(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+\r
+ /* Add data field */\r
+ strcat(buf, JSON_Stringify);\r
+ int len = TCF_TTY_ReadString(tmp, 199);\r
+ tmp[len] = '\0'; /* Terminate to be sure */\r
+ strcat(buf, tmp);\r
+ strcat(buf, JSON_Stringify);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ //strcat(buf, Streams_LostSize);\r
+ ultoa(0,tmp,10);\r
+ strcat(buf,tmp);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ //strcat(buf, Streams_EOS);\r
+ strcat(buf, Streams_false);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ } else if (strcmp(command->commandName, Streams_Write) == 0) {\r
+ /* C \95 <token> \95 Streams \95 write \95 <string: stream ID> \95 <int: size> \95 <string: data> \95 */\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_write(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ } else if (strcmp(command->commandName, Streams_Subscribe) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }else if (strcmp(command->commandName, Streams_Unsubscribe) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }else if (strcmp(command->commandName, Streams_Connect) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }else if (strcmp(command->commandName, Streams_Disconnect) == 0) {\r
+ /* R \95 <token> \95 <error report> */\r
+ if(parse_id(command->arguments,&streams_cmd,command->args_len) != E_OK){\r
+ return 0;\r
+ }\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }\r
+\r
+ convert_to_tcf_message(buf);\r
+ uint16_t len = message_length(buf, TCF_MAX_FIELD_LENGTH);\r
+\r
+ return len;\r
+}\r
--- /dev/null
+/*\r
+ * streams.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef STREAMS_H_\r
+#define STREAMS_H_\r
+\r
+#include "Std_Types.h"\r
+#include "tcf.h"\r
+\r
+uint8_t TCF_TTY_SendChar (uint8_t ch);\r
+void init_streams();\r
+\r
+uint16_t handle_StreamsCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_StreamsEvent(TCF_Event* event, char* buf);\r
+\r
+#endif /* STREAMS_H_ */\r
--- /dev/null
+/*\r
+ * sys_monitor.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#include "Std_Types.h"\r
+#include "sys_monitor.h"\r
+#include "tcf.h"\r
+#include <string.h>\r
+#include "internal.h"\r
+#include "xtoa.h"\r
+\r
+const char SysMon_PID[] = "\"PID\":";\r
+const char SysMon_Prio[] = "\"Priority\":";\r
+const char SysMon_Stackstart[] = "\"StackStart\":";\r
+const char SysMon_Stackend[] = "\"StackEnd\":";\r
+const char SysMon_Stackcurr[] = "\"StackCurr\":";\r
+const char SysMon_State[] = "\"State\":";\r
+\r
+static void AddState(char *buf, state_t state)\r
+{\r
+ /* "RSDZTW" where\r
+ R is running,\r
+ S is sleeping in an interruptible wait,\r
+ D is waiting in uninterruptible disk sleep,\r
+ Z is zombie,\r
+ T is traced or stopped (on a signal), and\r
+ W is paging */\r
+ switch(state)\r
+ {\r
+ case ST_READY:\r
+ strcat(buf,"\"D\"");\r
+ break;\r
+ case ST_WAITING:\r
+ strcat(buf,"\"S\"");\r
+ break;\r
+ case ST_SUSPENDED:\r
+ strcat(buf,"\"T\"");\r
+ break;\r
+ case ST_RUNNING:\r
+ strcat(buf,"\"R\"");\r
+ break;\r
+ case ST_NOT_STARTED:\r
+ strcat(buf,"\"T\"");\r
+ break;\r
+ }\r
+}\r
+\r
+uint16_t handle_SysMonEvent(TCF_Event* event, char* buf){\r
+ return 0;\r
+}\r
+\r
+\r
+uint16_t handle_SysMonCommand(TCF_Command* command, char* buf) {\r
+ OsPcbType *iterPcbPtr;\r
+\r
+ /* Start building return message */\r
+ start_tcf_field(buf, (char *)TCF_S_R); /* Start */\r
+ append_tcf_field(buf, command->token); /* Token */\r
+\r
+ if (strcmp(command->commandName, TCF_getChildren) == 0) {\r
+ boolean first = TRUE;\r
+\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add data field */\r
+ strcat(buf, JSON_ListStart);\r
+ TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {\r
+ if(iterPcbPtr->proc_type < 4)\r
+ {\r
+ if(first){\r
+ first = FALSE;\r
+ }else{\r
+ strcat(buf, JSON_Separator);\r
+ }\r
+ strcat(buf, JSON_Stringify);\r
+ strcat(buf, iterPcbPtr->name);\r
+ strcat(buf, JSON_Stringify);\r
+ }\r
+ }\r
+ strcat(buf, JSON_ListEnd);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ } else if (strcmp(command->commandName, TCF_getContext) == 0) {\r
+ char tmp[20] = "";\r
+\r
+ /* Add error field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add data field */\r
+ char *arg = command->arguments + 1; /* add 1 for " */\r
+ TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {\r
+ if(strncmp(arg, iterPcbPtr->name, strlen(command->arguments)-2) == 0)\r
+ {\r
+ break;\r
+ }\r
+ }\r
+ strcat(buf, JSON_ObjStart);\r
+ strcat(buf, TCF_ID);\r
+ strcat(buf, command->arguments);\r
+\r
+ strcat(buf, JSON_Separator);\r
+ strcat(buf, TCF_File);\r
+ strcat(buf, command->arguments);\r
+\r
+ strcat(buf, JSON_Separator);\r
+ strcat(buf, SysMon_PID);\r
+ ultoa(iterPcbPtr->pid,tmp,10);\r
+ strcat(buf, tmp);\r
+\r
+ strcat(buf, JSON_Separator);\r
+ strcat(buf, SysMon_Prio);\r
+ ultoa(iterPcbPtr->prio,tmp,10);\r
+ strcat(buf, tmp);\r
+\r
+ strcat(buf, JSON_Separator);\r
+ strcat(buf, SysMon_Stackstart);\r
+ ultoa((uint32_t)iterPcbPtr->stack.top,tmp,10);\r
+ strcat(buf, tmp);\r
+\r
+/* strcat(buf, JSON_Separator);\r
+ strcat(buf, SysMon_Stackend);\r
+ ultoa((uint32_t)iterPcbPtr->stack.top + iterPcbPtr->stack.size,tmp,10);\r
+ strcat(buf, tmp);\r
+\r
+ strcat(buf, JSON_Separator);\r
+ strcat(buf, SysMon_Stackcurr);\r
+ ultoa((uint32_t)iterPcbPtr->stack.curr,tmp,10);\r
+ strcat(buf, tmp);\r
+*/\r
+ strcat(buf, JSON_Separator);\r
+ strcat(buf, SysMon_State);\r
+ AddState(buf,iterPcbPtr->state);\r
+\r
+ strcat(buf, JSON_ObjEnd);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+ }\r
+\r
+ convert_to_tcf_message(buf);\r
+ uint16_t len = message_length(buf, TCF_MAX_FIELD_LENGTH);\r
+\r
+ return len;\r
+}\r
--- /dev/null
+/*\r
+ * sys_monitor.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef SYSMONITOR_H_\r
+#define SYSMONITOR_H_\r
+\r
+#include "Std_Types.h"\r
+#include "tcf.h"\r
+\r
+uint16_t handle_SysMonCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_SysMonEvent(TCF_Event* event, char* buf);\r
+\r
+#endif /* SYSMONITOR_H_ */\r
--- /dev/null
+/*\r
+ * tcf.c\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#define USE_LDEBUG_PRINTF\r
+#include "debug.h"\r
+\r
+#include "Std_Types.h"\r
+#include <string.h>\r
+#ifdef USE_LWIP\r
+#include "lwip/tcp.h"\r
+#include "lwip/udp.h"\r
+#include "tcp_handler.h"\r
+#endif\r
+#include "tcf.h"\r
+#include "Tcf_Cfg.h"\r
+#include "xtoa.h"\r
+#include "streams.h"\r
+\r
+\r
+#define TCF_TCP_PORT 1534\r
+\r
+const char TCF_getChildren[] = "getChildren";\r
+const char TCF_getContext[] = "getContext";\r
+const char TCF_ID[] = "\"ID\":";\r
+const char TCF_File[] = "\"File\":";\r
+const char TCF_Service[] = "\"Service\":";\r
+const char TCF_Code[] = "\"Code\":";\r
+\r
+\r
+const char JSON_ObjStart[] = "{";\r
+const char JSON_ObjEnd[] = "}";\r
+const char JSON_null[] = "null";\r
+const char JSON_Separator[] = ",";\r
+\r
+const char JSON_Stringify[] = "\"";\r
+const char JSON_ListStart[] = "[";\r
+const char JSON_ListEnd[] = "]";\r
+\r
+struct tcf_tcp_state\r
+{\r
+ int num;\r
+};\r
+\r
+uint16_t message_length(const char* msg, uint16_t max_length) {\r
+ uint16_t i;\r
+ for (i = 0; i < max_length; ++i) {\r
+ if (msg[i] == '\x01') {\r
+ return i+1;\r
+ }\r
+ }\r
+ return max_length;\r
+}\r
+\r
+void start_tcf_field(char* start, char* field) {\r
+ strcpy(start, field);\r
+ strcat(start, TCF_S_EOFIELD_MARKER);\r
+}\r
+\r
+void append_tcf_field(char* start, char* field) {\r
+ strcat(start, field);\r
+ strcat(start, TCF_S_EOFIELD_MARKER);\r
+}\r
+\r
+void convert_to_tcf_message(char* start) {\r
+ strcat(start, TCF_S_EOM);\r
+ size_t length = strlen(start);\r
+ int i;\r
+ for (i = 0; i < length; ++i) {\r
+ if (start[i] == TCF_C_EOFIELD_MARKER) {\r
+ start[i] = TCF_C_EOFIELD;\r
+ }\r
+ }\r
+}\r
+\r
+char* get_next_tcf_field(char* chars, uint16_t maxlen) {\r
+ int i;\r
+ for(i = 0; i < maxlen; i++) {\r
+ if (chars[i] == TCF_FIELD_DELIMITER) {\r
+ return &chars[i+1];\r
+ }\r
+ }\r
+ return (char*) NULL;\r
+}\r
+\r
+char* get_next_tcf_msg(char* chars, uint16_t *len) {\r
+ int i;\r
+ for(i = 0; i < *len-1; i++) {\r
+ if (chars[i] == '\x03' && chars[i+1] == '\x01') {\r
+ *len -= (i + 1);\r
+ return &chars[i+2];\r
+ }\r
+ }\r
+ *len= 0;\r
+ return (char*) NULL;\r
+}\r
+\r
+static Std_ReturnType parse_command(char* msg, TCF_Command* command, uint16_t len){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->token = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->serviceName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->commandName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, len);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ command->arguments = curr;\r
+\r
+ command->args_len = len -((uint32_t)curr - (uint32_t)msg);\r
+ return E_OK;\r
+}\r
+\r
+Std_ReturnType parse_event(char* msg, TCF_Event* event){\r
+ char* curr = msg;\r
+\r
+ curr = get_next_tcf_field(curr, TCF_MAX_FIELD_LENGTH);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ event->serviceName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, TCF_MAX_FIELD_LENGTH);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ event->eventName = curr;\r
+\r
+ curr = get_next_tcf_field(curr, TCF_MAX_FIELD_LENGTH);\r
+ if (curr == NULL) return E_NOT_OK;\r
+ event->eventData = curr;\r
+\r
+ return E_OK;\r
+}\r
+\r
+uint16_t handle_LocatorCommand(TCF_Command* command, char* buf) {\r
+ return 0;\r
+}\r
+\r
+uint16_t handle_LocatorEvent(TCF_Event* event, char* buf) {\r
+ uint16_t len = 0;\r
+ if(strcmp(event->eventName, "Hello") == 0)\r
+ {\r
+ len = message_length(locator_hello, TCF_MAX_FIELD_LENGTH);\r
+ memcpy(buf,locator_hello,len);\r
+ }else if(strcmp(event->eventName, "peerHeartBeat") == 0){\r
+\r
+ }\r
+\r
+ return len;\r
+}\r
+\r
+uint16_t handle_FileSystemCommand(TCF_Command* command, char* buf) {\r
+ char tmp[20] = "";\r
+\r
+ /* Start building return message */\r
+ start_tcf_field(buf, (char *)TCF_S_R); /* Start */\r
+ append_tcf_field(buf, command->token); /* Token */\r
+\r
+ /* Add error field */\r
+ strcat(buf, JSON_ObjStart);\r
+\r
+ strcat(buf, TCF_Code);\r
+ ultoa(TCF_UNSUPPORTED,tmp,10);\r
+ strcat(buf, tmp);\r
+\r
+ strcat(buf, JSON_ObjEnd);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ /* Add data field */\r
+ strcat(buf, JSON_null);\r
+ strcat(buf, TCF_S_EOFIELD_MARKER);\r
+\r
+ convert_to_tcf_message(buf);\r
+ uint16_t len = message_length(buf, TCF_MAX_FIELD_LENGTH);\r
+\r
+ return len;\r
+}\r
+\r
+uint16_t handle_FileSystemEvent(TCF_Event* event, char* buf) {\r
+ return 0;\r
+}\r
+\r
+/* Not reentrant so buffers can be static */\r
+static char outbuf[TCF_MAX_FIELD_LENGTH] = "";\r
+\r
+static void handle_event(char *buf, uint16_t len)\r
+{\r
+ char *msg = (char *)buf;\r
+ uint8 index;\r
+ uint16_t outlen = 0;\r
+ TCF_Event event;\r
+\r
+ if (parse_event(msg, &event) == E_OK) {\r
+ /* Find and call the requested agent */\r
+ index = 0;\r
+ while(tcfServiceCfgList[index].eventHandler != NULL){\r
+ if(strcmp(event.serviceName, tcfServiceCfgList[index].name) == 0){\r
+ outlen = tcfServiceCfgList[index].eventHandler(&event, outbuf);\r
+ break;\r
+ }\r
+ index++;\r
+ }\r
+ }\r
+\r
+ if(outlen > 0){\r
+#ifdef USE_LWIP\r
+ TcpSendData(outbuf, outlen);\r
+#endif\r
+ }\r
+}\r
+\r
+static void handle_command(char *buf, uint16_t len)\r
+{\r
+ char *msg = (char *)buf;\r
+ uint8 index;\r
+ uint16_t outlen = 0;\r
+ TCF_Command command;\r
+\r
+ if (parse_command(msg, &command, len) == E_OK) {\r
+ //LDEBUG_PRINTF("C %s\n\r", command.token);\r
+ /* Find and call the requested agent */\r
+ index = 0;\r
+ while(tcfServiceCfgList[index].commandHandler != NULL){\r
+ if(strcmp(command.serviceName, tcfServiceCfgList[index].name) == 0){\r
+ outlen = tcfServiceCfgList[index].commandHandler(&command, outbuf);\r
+ break;\r
+ }\r
+ index++;\r
+ }\r
+\r
+ if(outlen > 0){\r
+#ifdef USE_LWIP\r
+ //LDEBUG_PRINTF("R %s\n\r", command.token);\r
+ TcpSendData(outbuf, outlen);\r
+#endif\r
+ }else{\r
+ LDEBUG_PRINTF("TCF: len=0:%s\n\r", command.token);\r
+ }\r
+ }else{\r
+ LDEBUG_PRINTF("TCF: Parse failed:%s\n\r", command.token);\r
+ }\r
+}\r
+\r
+static void handle_incoming(const void* buf, uint16_t len) {\r
+ char *msg = (char *)buf;\r
+\r
+ if(len > 0){\r
+ do{\r
+ char c = msg[0];\r
+ if (c == 'C') {\r
+ handle_command(msg, len);\r
+ } else if (c == 'E') {\r
+ handle_event(msg, len);\r
+ }\r
+\r
+ /* Check if more than one message in buffer */\r
+ msg = get_next_tcf_msg(msg, &len);\r
+ }while((msg != NULL) && (len > 0));\r
+ }\r
+}\r
+\r
+void InitTcf(void){\r
+#ifdef USE_LWIP\r
+ CreateTcpSocket(TCF_TCP_PORT, handle_incoming);\r
+#endif\r
+ init_streams();\r
+}\r
--- /dev/null
+/*\r
+ * tcf.h\r
+ *\r
+ * Created on: 15 sep 2010\r
+ * Author: jcar\r
+ */\r
+\r
+#ifndef TCF_H_\r
+#define TCF_H_\r
+\r
+#include "Std_Types.h"\r
+\r
+#define TCF_C_EOFIELD '\x00'\r
+#define TCF_C_EOFIELD_MARKER '\x04'\r
+\r
+#define TCF_S_EOFIELD "\x00"\r
+#define TCF_S_EOFIELD_MARKER "\x04"\r
+#define TCF_S_R "R"\r
+#define TCF_S_EOM "\x03\x01"\r
+\r
+#define TCF_FIELD_DELIMITER ('\x00')\r
+#define TCF_MAX_FIELD_LENGTH (1400)\r
+\r
+extern const char TCF_getChildren[];\r
+extern const char TCF_getContext[];\r
+extern const char TCF_ID[];\r
+extern const char TCF_File[];\r
+extern const char TCF_Service[];\r
+extern const char TCF_Code[];\r
+\r
+extern const char JSON_ObjStart[];\r
+extern const char JSON_ObjEnd[];\r
+extern const char JSON_null[];\r
+extern const char JSON_Separator[];\r
+\r
+extern const char JSON_Stringify[];\r
+extern const char JSON_ListStart[];\r
+extern const char JSON_ListEnd[];\r
+\r
+/* Standard error codes: */\r
+\r
+typedef enum{\r
+ TCF_OTHER = 1,\r
+ TCF_JSON_SYNTAX = 2,\r
+ TCF_PROTOCOL = 3,\r
+ TCF_BUFFER_OVERFLOW = 4,\r
+ TCF_CHANNEL_CLOSED = 5,\r
+ TCF_COMMAND_CANCELLED = 6,\r
+ TCF_UNKNOWN_PEER = 7,\r
+ TCF_BASE64 = 8,\r
+ TCF_EOF = 9,\r
+ TCF_ALREADY_STOPPED = 10,\r
+ TCF_ALREADY_EXITED = 11,\r
+ TCF_ALREADY_RUNNING = 12,\r
+ TCF_ALREADY_ATTACHED = 13,\r
+ TCF_IS_RUNNING = 14,\r
+ TCF_INV_DATA_SIZE = 15,\r
+ TCF_INV_CONTEXT = 16,\r
+ TCF_INV_ADDRESS = 17,\r
+ TCF_INV_EXPRESSION = 18,\r
+ TCF_INV_FORMAT = 19,\r
+ TCF_INV_NUMBER = 20,\r
+ TCF_INV_DWARF = 21,\r
+ TCF_SYM_NOT_FOUND = 22,\r
+ TCF_UNSUPPORTED = 23,\r
+ TCF_INV_DATA_TYPE = 24,\r
+ TCF_INV_COMMAND = 25,\r
+} TCF_ErrorCode_t;\r
+\r
+\r
+typedef struct {\r
+ char* serviceName;\r
+ char* eventName;\r
+ char* eventData;\r
+} TCF_Event;\r
+\r
+typedef struct {\r
+ char* token;\r
+ char* serviceName;\r
+ char* commandName;\r
+ char* arguments;\r
+ uint16_t args_len;\r
+} TCF_Command;\r
+\r
+typedef struct {\r
+ char* token;\r
+ char* error;\r
+ char* data;\r
+} TCF_Result;\r
+\r
+typedef uint16_t (*TCF_Service_CommandHandler)(TCF_Command* command, char* buf);\r
+typedef uint16_t (*TCF_Service_EventHandler)(TCF_Event* command, char* buf);\r
+\r
+void InitTcf(void);\r
+uint16_t message_length(const char* msg, uint16_t max_length);\r
+char* get_next_tcf_field(char* chars, uint16_t maxlen);\r
+void start_tcf_field(char* start, char* field);\r
+void append_tcf_field(char* start, char* field);\r
+void convert_to_tcf_message(char* start);\r
+void tcf_compile_result(TCF_Result* result, char* buffer);\r
+\r
+/* Locator and Filesystem handlers are in tcf.c file. To be moved */\r
+uint16_t handle_LocatorCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_LocatorEvent(TCF_Event* event, char* buf);\r
+uint16_t handle_FileSystemCommand(TCF_Command* command, char* buf);\r
+uint16_t handle_FileSystemEvent(TCF_Event* event, char* buf);\r
+\r
+#endif /* TCF_H_ */\r
#include "CanSM.h" /**< @req CANSM013 */\r
#include "Com.h" /**< @req CANSM172 */\r
#include "ComM.h" /**< @req CANSM174 */\r
-#include "ComM_BusSM.h" /**< @req CANSM191 */\r
+#include "ComM_BusSm.h" /**< @req CANSM191 */\r
#include "Det.h" /**< @req CANSM015 */\r
#if defined(USE_DEM)\r
#include "Dem.h" /**< @req CANSM014 */\r
#include "CanIf.h" /**< @req CANSM017 */\r
#include "CanSM_Internal.h"\r
\r
+static CanSM_Internal_NetworkType CanSM_InternalNetworks[CANSM_NETWORK_COUNT];\r
+\r
static CanSM_InternalType CanSM_Internal = {\r
.InitStatus = CANSM_STATUS_UNINIT,\r
+ .Networks = CanSM_InternalNetworks,\r
};\r
\r
static const CanSM_ConfigType* CanSM_Config;\r
(void) initRx15765RuntimeData(rxConfig, rxRuntime); /** @req CANTP124 */\r
pduLength = getPduLength(&rxConfig->CanTpAddressingFormant, SINGLE_FRAME, rxPduData);\r
\r
- VALIDATE_NO_RV( rxRuntime->pdurBuffer->SduDataPtr != NULL,\r
+ if (rxRuntime->pdurBuffer != NULL) {\r
+ VALIDATE_NO_RV( rxRuntime->pdurBuffer->SduDataPtr != NULL,\r
SERVICE_ID_CANTP_RX_INDICATION, CANTP_E_INVALID_RX_LENGTH );\r
+ }\r
\r
if (rxConfig->CanTpAddressingFormant == CANTP_STANDARD) { /** @req CANTP094 *//** @req CANTP095 */\r
data = &rxPduData->SduDataPtr[1];\r
#include "Com_Internal.h"\r
#include "Com_misc.h"\r
#include "debug.h"\r
-#include "CanIf.h"\r
#include "PduR.h"\r
#include "PduR_Com.h"\r
#include "Byteorder.h"\r
+#include "Det.h"\r
\r
extern Com_Arc_Config_type Com_Arc_Config;\r
\r
#endif\r
\r
/** @req COMM347 */\r
-#if defined(USE_NM)\r
+#if defined(USE_NM) || defined(COMM_TESTS)\r
#include "Nm.h"\r
#endif\r
\r
static ComM_ConfigType * ComM_Config;\r
\r
\r
-void ComM_Init( ComM_ConfigType * Config ){\r
+void ComM_Init(const ComM_ConfigType * Config ){\r
COMM_VALIDATE_PARAMETER( (Config != NULL), COMM_SERVICEID_INIT);\r
COMM_VALIDATE_PARAMETER( (Config->Channels != NULL), COMM_SERVICEID_INIT);\r
COMM_VALIDATE_PARAMETER( (Config->Users != NULL), COMM_SERVICEID_INIT);\r
\r
Std_ReturnType busSMStatus = E_OK;\r
switch (ChannelConf->BusType) {\r
-#if defined(USE_CANSM)\r
+#if defined(USE_CANSM) || defined(COMM_TESTS)\r
case COMM_BUS_TYPE_CAN:\r
busSMStatus = CanSM_RequestComMode(ChannelConf->BusSMNetworkHandle, ComMode);\r
break;\r
\r
if ((ChannelConf->NmVariant == COMM_NM_VARIANT_FULL) ||\r
(ChannelConf->NmVariant == COMM_NM_VARIANT_PASSIVE)) {\r
-#if defined(USE_NM)\r
+#if defined(USE_NM) || defined(COMM_TESTS)\r
Nm_ReturnType nmStatus = NM_E_OK;\r
if (ChannelInternal->Mode == COMM_FULL_COMMUNICATION) {\r
if (ChannelInternal->SubMode == COMM_SUBMODE_NETWORK_REQUESTED) {\r
#include "Dem.h"\r
#endif\r
#include "PduR.h"\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
#include "debug.h"\r
\r
/*\r
#include "ComM_Dcm.h"\r
#include "PduR_Dcm.h"\r
#include "ComStack_Types.h"\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
\r
// State variable\r
typedef enum\r
\r
\r
#include <string.h>\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
#include "Dcm.h"\r
#include "Dcm_Internal.h"\r
#include "MemMap.h"\r
#include "Dcm_Internal.h"\r
#include "Dem.h"\r
#include "MemMap.h"\r
+#if defined(USE_MCU)\r
#include "Mcu.h"\r
+#endif\r
\r
#define ZERO_SUB_FUNCTION 0x00\r
\r
static Dcm_NegativeResponseCodeType udsReadDtcInfoSub_0x06_0x10(const PduInfoType *pduRxData, PduInfoType *pduTxData)\r
{\r
Dcm_NegativeResponseCodeType responseCode = DCM_E_POSITIVERESPONSE;\r
- Dem_DTCOriginType dtcOrigin = NULL;\r
+ Dem_DTCOriginType dtcOrigin;\r
uint8 startRecNum;\r
uint8 endRecNum;\r
\r
\r
default:\r
responseCode = DCM_E_SUBFUNCTIONNOTSUPPORTED;\r
+ dtcOrigin = 0;\r
break;\r
}\r
\r
if (dspUdsEcuResetData.resetPending) {\r
if (confirmPduId == dspUdsEcuResetData.resetPduId) {\r
dspUdsEcuResetData.resetPending = FALSE;\r
-#if ( MCU_PERFORM_RESET_API == STD_ON )\r
+#if defined(USE_MCU) && ( MCU_PERFORM_RESET_API == STD_ON )\r
Mcu_PerformReset();\r
#else\r
DET_REPORTERROR(MODULE_ID_DCM, 0, DCM_UDS_RESET_ID, DCM_E_NOT_SUPPORTED);\r
//#include "Nvm.h"\r
//#include "SchM_Dem.h"\r
#include "MemMap.h"\r
-#include "Mcu.h"\r
+#include "McuExtensions.h"\r
\r
/*\r
* Local defines\r
\r
if (eventStatusRecPtr != NULL) {\r
// Handle debouncing\r
- switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) { /** @req DEM004 */ /** @req DEM342 */\r
- case DEM_NO_PRE_DEBOUNCE:\r
- eventStatus = preDebounceNone(eventStatus, eventStatusRecPtr);\r
- break;\r
+ if (eventParam->EventClass->PreDebounceAlgorithmClass != NULL) {\r
+ switch (eventParam->EventClass->PreDebounceAlgorithmClass->PreDebounceName) { /** @req DEM004 */ /** @req DEM342 */\r
+ case DEM_NO_PRE_DEBOUNCE:\r
+ eventStatus = preDebounceNone(eventStatus, eventStatusRecPtr);\r
+ break;\r
\r
- case DEM_PRE_DEBOUNCE_COUNTER_BASED:\r
- eventStatus = preDebounceCounterBased(eventStatus, eventStatusRecPtr);\r
- break;\r
+ case DEM_PRE_DEBOUNCE_COUNTER_BASED:\r
+ eventStatus = preDebounceCounterBased(eventStatus, eventStatusRecPtr);\r
+ break;\r
\r
- default:\r
- // Don't know how to handle this.\r
- DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
- break;\r
+ default:\r
+ // Don't know how to handle this.\r
+ DET_REPORTERROR(MODULE_ID_DEM, 0, DEM_UPDATE_EVENT_STATUS_ID, DEM_E_NOT_IMPLEMENTED_YET);\r
+ break;\r
+ }\r
}\r
\r
-\r
eventStatusRecPtr->errorStatusChanged = FALSE;\r
\r
// Check test failed\r
{\r
uint16 i;\r
\r
- for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {\r
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION)\r
+ && (eventParam->EventClass->EventDestination[i] != DEM_EVENT_DESTINATION_END_OF_LIST); i++) {\r
switch (eventParam->EventClass->EventDestination[i])\r
{\r
case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
{\r
uint16 i;\r
\r
- for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {\r
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != DEM_EVENT_DESTINATION_END_OF_LIST); i++) {\r
switch (eventParam->EventClass->EventDestination[i])\r
{\r
case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
{\r
uint16 i;\r
\r
- for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != NULL); i++) {\r
+ for (i = 0; (i < DEM_MAX_NR_OF_EVENT_DESTINATION) && (eventParam->EventClass->EventDestination[i] != DEM_EVENT_DESTINATION_END_OF_LIST); i++) {\r
switch (eventParam->EventClass->EventDestination[i])\r
{\r
case DEM_DTC_ORIGIN_PRIMARY_MEMORY:\r
#define DEM_TYPES_H_\r
#include "Std_Types.h" /** @req DEM176.Std */\r
\r
+#define DEM_EVENT_DESTINATION_END_OF_LIST 0\r
+\r
/*\r
* DTC storage types\r
*/\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU WDG WDGM PORT DIO\r
+MOD_USE+=ECUM KERNEL MCU WDG WDGM PORT DIO DET\r
\r
SELECT_CONSOLE = RAMLOG\r
SELECT_OS_CONSOLE = RAMLOG\r
obj-y += Hooks.o\r
obj-y += Rte.o\r
\r
-VPATH += ..\r
+VPATH += ../\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
VPATH += $(ROOTDIR)/components/blinker\r
inc-y += $(ROOTDIR)/components/blinker\r
\r
-$(warning ROOTDIR: $(ROOTDIR))\r
-$(warning SUBDIR: $(SUBDIR))\r
-$(warning VPATH: $(VPATH))\r
\r
# libs needed by us \r
#libitem-y +=\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU PORT PWM\r
-\r
-SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+MOD_USE+=KERNEL MCU ECUM DET PORT PWM RAMLOG\r
obj-y += Hooks.o\r
obj-y += Rte.o\r
\r
-VPATH += ..\r
+VPATH += ../\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
+\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU\r
-\r
-SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+MOD_USE+=KERNEL MCU ECUM DET PORT COM CAN CANIF PWM RAMLOG\r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
/*\r
* ComGeneral pre-compile time configuration parameters.\r
.ComSignalInitValue = &Com_SignalInitValue_SetLedLevelRx,\r
.ComBitPosition = 7,\r
.ComBitSize = 16,\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalType = UINT16,\r
.ComGroupSignal = NULL,\r
\r
obj-y += Tasks.o\r
obj-y += Hooks.o\r
\r
-VPATH += ..\r
-\r
inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
inc-y += $(ROOTDIR)/system/kernel/include\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
+VPATH += ../\r
+\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
+\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU\r
-\r
-SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+MOD_USE+= DET ECUM MCU KERNEL RAMLOG \r
\r
-def-y += CFG_RAMLOG_SIZE=1024\r
-def-y += HEAPSIZE=1400
\ No newline at end of file
+#def-y += NDEBUG\r
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1000
\ No newline at end of file
* \r
* Copyright ArcCore AB 2010\r
* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:26:09 CEST 2010\r
+* on Thu Jun 17 10:18:14 CEST 2010\r
*/\r
\r
\r
\r
// ################################ RESOURCES ###############################\r
GEN_RESOURCE_HEAD {\r
- GEN_RESOURCE( \r
- RES_SCHEDULER,\r
- RESOURCE_TYPE_STANDARD,\r
- 0\r
- ),\r
};\r
\r
// ############################## STACKS (TASKS) ############################\r
* \r
* Copyright ArcCore AB 2010\r
* Generated by Arctic Studio (http://arccore.com)\r
-* on Mon May 03 11:26:09 CEST 2010\r
+* on Thu Jun 17 10:18:14 CEST 2010\r
*/\r
\r
\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:52:09 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:52:09 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:52:29 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 100, 10, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:52:29 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+#define EVENT_MASK_EVENT_3 3\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
\r
# Our object files\r
obj-y += simple_main.o\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
\r
VPATH += ..\r
VPATH += ../config\r
#linkfile\r
ldcmdfile-y = linkscript_gcc.ldp\r
vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+#ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldp\r
\r
# What I want to build\r
build-exe-y = simple.elf\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-#include "Os.h"\r
-#include "Mcu.h"\r
-#include "arc.h"\r
-\r
-#define USE_LDEBUG_PRINTF\r
-#include "debug.h"\r
-\r
-// How many errors to keep in error log.\r
-#define ERROR_LOG_SIZE 20\r
-\r
-\r
-/**\r
- * Just an example of a basic task.\r
- */\r
-\r
-void btask_3( void ) {\r
- StackInfoType si;\r
- TaskType currTask;\r
- LDEBUG_PRINTF("[%08d] btask_3 start\n", GetOsTick() );\r
-\r
- GetTaskID(&currTask);\r
- Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("btask_3: Stack usage %d%%\n",OS_STACK_USAGE(&si));\r
-\r
- TerminateTask();\r
-}\r
-\r
-/**\r
- * An extended task is auto-started and is also triggered by an alarm\r
- * that sets event 2.\r
- */\r
-\r
-void etask_1( void ) {\r
- volatile float tryFloatingPoint = 0.0F;\r
- StackInfoType si;\r
- TaskType currTask;\r
-\r
-\r
- LDEBUG_PRINTF("etask_1 start\n");\r
- for(;;) {\r
- SetEvent(TASK_ID_etask_2,1);\r
- WaitEvent(2);\r
- ClearEvent(2);\r
- tryFloatingPoint += 1.0F;\r
- GetTaskID(&currTask);\r
- Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("etask_1: Stack usage %d%% \n",OS_STACK_USAGE(&si));\r
-\r
- }\r
-}\r
-\r
-/**\r
- * An extended task that receives events from someone\r
- * and activates task: btask_3.\r
- */\r
-void etask_2( void ) {\r
- LDEBUG_PRINTF("etask_2 start\n");\r
-\r
- for(;;) {\r
- WaitEvent(1);\r
- ClearEvent(1);\r
- ActivateTask(TASK_ID_btask_3);\r
- {\r
- StackInfoType si;\r
- TaskType currTask;\r
- GetTaskID(&currTask);\r
- Os_Arc_GetStackInfo(currTask,&si);\r
- LDEBUG_PRINTF("etask_1: Stack usage %d%% \n",OS_STACK_USAGE(&si));\r
- }\r
- }\r
-}\r
-\r
-\r
-/*\r
- * Functions that must be supplied by the example\r
- */\r
-\r
-void OsIdle( void ) {\r
- for(;;);\r
-}\r
-\r
-\r
-/* Global hooks */\r
-ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
- LDEBUG_PRINTF("## ProtectionHook\n");\r
- return PRO_KILLAPPL;\r
-}\r
-\r
-void StartupHook( void ) {\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
-\r
- LDEBUG_PRINTF("## StartupHook\n");\r
-\r
- LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
-}\r
-\r
-void ShutdownHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ShutdownHook\n");\r
- while(1);\r
-}\r
-\r
-struct LogBad_s {\r
- uint32_t param1;\r
- uint32_t param2;\r
- uint32_t param3;\r
- TaskType taskId;\r
- OsServiceIdType serviceId;\r
- StatusType error;\r
-};\r
-\r
-void ErrorHook( StatusType Error ) {\r
-\r
- TaskType task;\r
- static struct LogBad_s LogBad[ERROR_LOG_SIZE];\r
- static uint8_t ErrorCount = 0;\r
-\r
- GetTaskID(&task);\r
-\r
-\r
- OsServiceIdType service = OSErrorGetServiceId();\r
-\r
- /* Grab the arguments to the functions\r
- * This is the standard way, see 11.2 in OSEK spec\r
- */\r
- switch(service) {\r
- case OSServiceId_SetRelAlarm:\r
- {\r
- // Read the arguments to the faulty functions...\r
- /* (Commented to remove warnings)\r
- AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;\r
- TickType increment = OSError_SetRelAlarm_Increment;\r
- TickType cycle = OSError_SetRelAlarm_Cycle; */\r
- // ... Handle this some way.\r
- break;\r
- }\r
- /*\r
- * The same pattern as above applies for all other OS functions.\r
- * See Os.h for names and definitions.\r
- */\r
-\r
- default:\r
- break;\r
- }\r
-\r
- LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);\r
-\r
- /* Log the errors in a buffer for later review */\r
- LogBad[ErrorCount].param1 = os_error.param1;\r
- LogBad[ErrorCount].param2 = os_error.param2;\r
- LogBad[ErrorCount].param3 = os_error.param3;\r
- LogBad[ErrorCount].serviceId = service;\r
- LogBad[ErrorCount].taskId = task;\r
- LogBad[ErrorCount].error = Error;\r
-\r
- ErrorCount++;\r
-\r
- // Stall if buffer is full.\r
- while(ErrorCount >= ERROR_LOG_SIZE);\r
-}\r
-\r
-void PreTaskHook( void ) {\r
- TaskType task;\r
- GetTaskID(&task);\r
-// LDEBUG_PRINTF("## PreTaskHook, taskid=%d\n",task);\r
-}\r
-\r
-void PostTaskHook( void ) {\r
- TaskType task;\r
- GetTaskID(&task);\r
-// LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
-}\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include "Os.h"
+#include "Mcu.h"
+#include "arc.h"
+
+#define USE_LDEBUG_PRINTF
+#include "debug.h"
+
+// How many errors to keep in error log.
+#define ERROR_LOG_SIZE 20
+
+
+/**
+ * Just an example of a basic task.
+ */
+
+void btask_3( void ) {
+ StackInfoType si;
+ TaskType currTask;
+ LDEBUG_PRINTF("[%08u] btask_3 start\n", (unsigned)GetOsTick() );
+
+ GetTaskID(&currTask);
+ Os_Arc_GetStackInfo(currTask,&si);
+ LDEBUG_PRINTF("btask_3: Stack usage %u%%\n",
+ (unsigned)OS_STACK_USAGE(&si));
+
+ TerminateTask();
+}
+
+/**
+ * An extended task is auto-started and is also triggered by an alarm
+ * that sets event 2.
+ */
+
+void etask_1( void ) {
+ volatile float tryFloatingPoint = 0.0F;
+ StackInfoType si;
+ TaskType currTask;
+
+
+ LDEBUG_PRINTF("etask_1 start\n");
+ for(;;) {
+ SetEvent(TASK_ID_etask_2,EVENT_MASK_EVENT_1);
+ WaitEvent(EVENT_MASK_EVENT_2);
+ ClearEvent(EVENT_MASK_EVENT_2);
+ tryFloatingPoint += 1.0F;
+ GetTaskID(&currTask);
+ Os_Arc_GetStackInfo(currTask,&si);
+ LDEBUG_PRINTF("etask_1: Stack usage %u%% \n",
+ (unsigned)OS_STACK_USAGE(&si));
+
+ }
+}
+
+/**
+ * An extended task that receives events from someone
+ * and activates task: btask_3.
+ */
+void etask_2( void ) {
+ LDEBUG_PRINTF("etask_2 start\n");
+
+ for(;;) {
+ WaitEvent(EVENT_MASK_EVENT_1);
+ ClearEvent(EVENT_MASK_EVENT_1);
+ ActivateTask(TASK_ID_btask_3);
+ {
+ StackInfoType si;
+ TaskType currTask;
+ GetTaskID(&currTask);
+ Os_Arc_GetStackInfo(currTask,&si);
+ LDEBUG_PRINTF("etask_1: Stack usage %u%% \n",
+ (unsigned)OS_STACK_USAGE(&si));
+ }
+ }
+}
+
+
+/*
+ * Functions that must be supplied by the example
+ */
+
+void OsIdle( void ) {
+ for(;;);
+}
+
+
+/* Global hooks */
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {
+ LDEBUG_PRINTF("## ProtectionHook\n");
+ return PRO_KILLAPPL;
+}
+
+void StartupHook( void ) {
+ uint32_t sys_freq = McuE_GetSystemClock();
+
+ LDEBUG_PRINTF("## StartupHook\n");
+
+ LDEBUG_PRINTF("Sys clock %u Hz\n",(unsigned)sys_freq);
+}
+
+void ShutdownHook( StatusType Error ) {
+ LDEBUG_PRINTF("## ShutdownHook\n");
+ while(1);
+}
+
+struct LogBad_s {
+ uint32_t param1;
+ uint32_t param2;
+ uint32_t param3;
+ TaskType taskId;
+ OsServiceIdType serviceId;
+ StatusType error;
+};
+
+void ErrorHook( StatusType Error ) {
+
+ TaskType task;
+ static struct LogBad_s LogBad[ERROR_LOG_SIZE];
+ static uint8_t ErrorCount = 0;
+
+ GetTaskID(&task);
+
+
+ OsServiceIdType service = OSErrorGetServiceId();
+
+ /* Grab the arguments to the functions
+ * This is the standard way, see 11.2 in OSEK spec
+ */
+ switch(service) {
+ case OSServiceId_SetRelAlarm:
+ {
+ // Read the arguments to the faulty functions...
+ AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;
+ TickType increment = OSError_SetRelAlarm_Increment;
+ TickType cycle = OSError_SetRelAlarm_Cycle;
+ (void)alarm_id;
+ (void)increment;
+ (void)cycle;
+
+ // ... Handle this some way.
+ break;
+ }
+ /*
+ * The same pattern as above applies for all other OS functions.
+ * See Os.h for names and definitions.
+ */
+
+ default:
+ break;
+ }
+
+ LDEBUG_PRINTF("## ErrorHook err=%u\n",Error);
+
+ /* Log the errors in a buffer for later review */
+ LogBad[ErrorCount].param1 = os_error.param1;
+ LogBad[ErrorCount].param2 = os_error.param2;
+ LogBad[ErrorCount].param3 = os_error.param3;
+ LogBad[ErrorCount].serviceId = service;
+ LogBad[ErrorCount].taskId = task;
+ LogBad[ErrorCount].error = Error;
+
+ ErrorCount++;
+
+ // Stall if buffer is full.
+ while(ErrorCount >= ERROR_LOG_SIZE);
+}
+
+void PreTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+// LDEBUG_PRINTF("## PreTaskHook, taskid=%u\n",task);
+}
+
+void PostTaskHook( void ) {
+ TaskType task;
+ GetTaskID(&task);
+// LDEBUG_PRINTF("## PostTaskHook, taskid=%u\n",task);
+}
+
<SD GID="MCU">Undefined MCU</SD>\r
<SD GID="AUTHOR">ArcCore AB</SD>\r
<SD GID="COPYRIGHT">Copyright ArcCore AB 2010</SD>\r
- <SD GID="GENDIR"></SD>\r
+ <SD GID="GENDIR">/arc/examples/simple/config/mpc5516it</SD>\r
</SDG>\r
</SDGS>\r
</ADMIN-DATA>\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU ADC DMA \r
+MOD_USE+=ADC DET ECUM DMA KERNEL MCU \r
\r
SELECT_CONSOLE = RAMLOG\r
-SELECT_OS_CONSOLE = RAMLOG\r
+SELECT_OS_CONSOLE = RAMLOG
\ No newline at end of file
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
/*\r
* ComGeneral pre-compile time configuration parameters.\r
.ComSignalInitValue = &Com_SignalInitValue_SetLedLevelTx,\r
.ComBitPosition = 7,\r
.ComBitSize = 16,\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalType = UINT16,\r
.ComGroupSignal = NULL,\r
\r
#define COM_E_TOO_MANY_SIGNAL 107\r
#define COM_E_TOO_MANY_GROUPSIGNAL 108\r
\r
-#define CPU_ENDIANESS BIG_ENDIAN\r
+#define CPU_ENDIANESS COM_BIG_ENDIAN\r
\r
/*\r
* ComGeneral pre-compile time configuration parameters.\r
.ComSignalInitValue = &Com_SignalInitValue_SetLedLevelTx,\r
.ComBitPosition = 7,\r
.ComBitSize = 16,\r
- .ComSignalEndianess = BIG_ENDIAN,\r
+ .ComSignalEndianess = COM_BIG_ENDIAN,\r
.ComSignalType = UINT16,\r
.ComGroupSignal = NULL,\r
\r
obj-y += Tasks.o\r
obj-y += Hooks.o\r
\r
-VPATH += ..\r
-\r
inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
inc-y += $(ROOTDIR)/system/kernel/include\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
+VPATH += ../\r
+\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
+\r
-include ../config/*.mk\r
-include ../config/$(BOARDDIR)/*.mk\r
\r
-MOD_USE+=KERNEL MCU\r
+MOD_USE+=DET ECUM MCU KERNEL RAMLOG \r
\r
SELECT_CONSOLE = RAMLOG\r
SELECT_OS_CONSOLE = RAMLOG\r
\r
def-y += CFG_RAMLOG_SIZE=1024\r
-def-y += HEAPSIZE=400
\ No newline at end of file
--- /dev/null
+\r
+\r
+def-y += HEAPSIZE=1400
\ No newline at end of file
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:51:31 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm_4ms, ALARM_AUTOSTART_ABSOLUTE, 100, 4, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm_4ms,\r
+ "Alarm_4ms",\r
+ COUNTER_ID_OsTick,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm_4ms),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_1,\r
+ EVENT_MASK_EVENT_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_3,2048);\r
+DECLARE_STACK(etask_1,2048);\r
+DECLARE_STACK(etask_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_3,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_1,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by: ArcCore AB
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+* Copyright ArcCore AB 2010
+* Generated by Arctic Studio (http://arccore.com)
+* on Fri Jun 18 12:51:31 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm_4ms 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_EVENT_0 0\r
+#define EVENT_MASK_EVENT_1 1\r
+#define EVENT_MASK_EVENT_2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_3 1\r
+#define TASK_ID_etask_1 2\r
+#define TASK_ID_etask_2 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_3( void );\r
+void etask_1( void );\r
+void etask_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 3\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
\r
-# OS object files.\r
-obj-y += Os_Cfg.o\r
-\r
+# Our object files\r
+obj-y += tiny.o\r
\r
VPATH += ..\r
VPATH += ../config\r
# Board object files\r
include $(ROOTDIR)/boards/board_common.mk\r
\r
-# Our object files\r
-obj-y += tiny.o\r
-\r
# libs needed by us \r
#libitem-y +=\r
\r
#include "Std_Types.h"\r
#include "CanIf_Types.h"\r
#include "ComStack_Types.h"\r
+#if defined(USE_MCU)\r
#include "Mcu.h"\r
+#endif\r
\r
typedef struct {\r
uint32 txSuccessCnt;\r
\r
\r
/** Initializes the AUTOSAR Communication Manager and restarts the internal state machines.*/\r
-void ComM_Init( ComM_ConfigType *); /**< @req COMM146 */\r
+void ComM_Init(const ComM_ConfigType *); /**< @req COMM146 */\r
\r
/** De-initializes (terminates) the AUTOSAR Communication Manager. */\r
void ComM_DeInit(); /**< @req COMM147 */\r
} ComFilterAlgorithm_type;\r
\r
typedef enum {\r
- BIG_ENDIAN,\r
- LITTLE_ENDIAN,\r
- OPAQUE,\r
+ COM_BIG_ENDIAN,\r
+ COM_LITTLE_ENDIAN,\r
+ COM_OPAQUE,\r
} ComSignalEndianess_type;\r
\r
typedef enum {\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-#ifndef DIO_H_\r
-#define DIO_H_\r
-\r
-#include "Std_Types.h" /** @req DIO131 */\r
-\r
-// API Service ID's\r
-#define DIO_READCHANNEL_ID 0x00\r
-#define DIO_WRITECHANNEL_ID 0x01\r
-#define DIO_READPORT_ID 0x02\r
-#define DIO_WRITEPORT_ID 0x03\r
-#define DIO_READCHANNELGROUP_ID 0x04\r
-#define DIO_WRITECHANNELGROUP_ID 0x05\r
-#define DIO_GETVERSIONINFO_ID 0x12\r
-\r
-#define DIO_E_PARAM_INVALID_CHANNEL_ID 10\r
-#define DIO_E_PARAM_INVALID_PORT_ID 20\r
-#define DIO_E_PARAM_INVALID_GROUP_ID 31\r
-\r
-#if defined(CFG_HC1X)\r
-typedef uint8 Dio_ChannelType;\r
-typedef uint8 Dio_PortType;\r
-\r
-/** @req DIO021 */\r
-/** @req DIO022 */\r
-typedef struct\r
-{\r
- Dio_PortType port;\r
- uint8 offset;\r
- uint8 mask;\r
-} Dio_ChannelGroupType;\r
-\r
-/** @req DIO023 */\r
-typedef uint8 Dio_LevelType;\r
-\r
-/** @req DIO024 */\r
-typedef uint8 Dio_PortLevelType;\r
-\r
-#else // CFG_PPC, CFG_STM32_STAMP and others\r
-typedef uint32 Dio_ChannelType;\r
-typedef uint32 Dio_PortType;\r
-typedef struct\r
-{\r
- Dio_PortType port;\r
- uint8 offset;\r
- uint32 mask;\r
-} Dio_ChannelGroupType;\r
-\r
-typedef uint32 Dio_LevelType;\r
-\r
-typedef uint16 Dio_PortLevelType;\r
-#endif\r
-\r
-\r
-#define DIO_MODULE_ID MODULE_ID_DIO\r
-#define DIO_VENDOR_ID 1\r
-\r
-#define DIO_SW_MAJOR_VERSION 1\r
-#define DIO_SW_MINOR_VERSION 0\r
-#define DIO_SW_PATCH_VERSION 0\r
-\r
-#define DIO_AR_MAJOR_VERSION 2\r
-#define DIO_AR_MINOR_VERSION 2 \r
-#define DIO_AR_PATCH_VERSION 1 \r
-\r
-#include "Dio_Cfg.h"\r
-\r
-/** @req DIO124 */\r
-#if ( DIO_VERSION_INFO_API == STD_ON)\r
-/** @req DIO139 */\r
-#define Dio_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DIO)\r
-#endif\r
-\r
-/** @req DIO133 */\r
-/** @req DIO027 */\r
-Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId);\r
-\r
-/** @req DIO134 */\r
-void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level);\r
-\r
-/** @req DIO135 */\r
-/** @req DIO031 */\r
-Dio_PortLevelType Dio_ReadPort(Dio_PortType portId);\r
-\r
-/** @req DIO136 */\r
-void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level);\r
-\r
-/** @req DIO137 */\r
-Dio_PortLevelType Dio_ReadChannelGroup( const Dio_ChannelGroupType *channelGroupIdPtr );\r
-\r
-/** @req DIO138 */\r
-void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr, Dio_PortLevelType level);\r
-\r
-#endif /*DIO_H_*/\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+#ifndef DIO_H_
+#define DIO_H_
+
+#include "Std_Types.h" /** @req DIO131 */
+
+// API Service ID's
+#define DIO_READCHANNEL_ID 0x00
+#define DIO_WRITECHANNEL_ID 0x01
+#define DIO_READPORT_ID 0x02
+#define DIO_WRITEPORT_ID 0x03
+#define DIO_READCHANNELGROUP_ID 0x04
+#define DIO_WRITECHANNELGROUP_ID 0x05
+#define DIO_GETVERSIONINFO_ID 0x12
+
+#define DIO_E_PARAM_INVALID_CHANNEL_ID 10
+#define DIO_E_PARAM_INVALID_PORT_ID 20
+#define DIO_E_PARAM_INVALID_GROUP_ID 31
+
+#if defined(CFG_HC1X)
+typedef uint8 Dio_ChannelType;
+typedef uint8 Dio_PortType;
+
+/** @req DIO021 */
+/** @req DIO022 */
+typedef struct
+{
+ Dio_PortType port;
+ uint8 offset;
+ uint8 mask;
+} Dio_ChannelGroupType;
+
+/** @req DIO023 */
+typedef uint8 Dio_LevelType;
+
+/** @req DIO024 */
+typedef uint8 Dio_PortLevelType;
+
+#else // CFG_PPC, CFG_STM32_STAMP and others
+typedef uint32 Dio_ChannelType;
+typedef uint32 Dio_PortType;
+typedef struct
+{
+ Dio_PortType port;
+ uint8 offset;
+ uint32 mask;
+} Dio_ChannelGroupType;
+
+typedef uint32 Dio_LevelType;
+
+typedef uint16 Dio_PortLevelType;
+#endif
+
+
+#define DIO_MODULE_ID MODULE_ID_DIO
+#define DIO_VENDOR_ID 1
+
+#define DIO_SW_MAJOR_VERSION 1
+#define DIO_SW_MINOR_VERSION 0
+#define DIO_SW_PATCH_VERSION 0
+
+#define DIO_AR_MAJOR_VERSION 2
+#define DIO_AR_MINOR_VERSION 2
+#define DIO_AR_PATCH_VERSION 1
+
+#include "Dio_Cfg.h"
+
+/** @req DIO124 */
+#if ( DIO_VERSION_INFO_API == STD_ON)
+/** @req DIO139 */
+#define Dio_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,DIO)
+#endif
+
+/** @req DIO133 */
+/** @req DIO027 */
+Dio_LevelType Dio_ReadChannel(Dio_ChannelType channelId);
+
+/** @req DIO134 */
+void Dio_WriteChannel(Dio_ChannelType channelId, Dio_LevelType level);
+
+/** @req DIO135 */
+/** @req DIO031 */
+Dio_PortLevelType Dio_ReadPort(Dio_PortType portId);
+
+/** @req DIO136 */
+void Dio_WritePort(Dio_PortType portId, Dio_PortLevelType level);
+
+/** @req DIO137 */
+Dio_PortLevelType Dio_ReadChannelGroup( const Dio_ChannelGroupType *channelGroupIdPtr );
+
+/** @req DIO138 */
+void Dio_WriteChannelGroup(const Dio_ChannelGroupType *channelGroupIdPtr, Dio_PortLevelType level);
+
+#endif /*DIO_H_*/
#define Mcu_GetVersionInfo(_vi) STD_GET_VERSION_INFO(_vi,MCU)\r
#endif\r
\r
-typedef uint32_t imask_t;\r
-\r
/* ArcCore extensions */\r
+\r
void Irq_InstallVector(void (*func)(), IrqType vector, uint8_t priority, Cpu_t cpu );\r
void Irq_GenerateSoftInt( IrqType vector );\r
uint8_t Irq_GetCurrentPriority( Cpu_t cpu);\r
#if defined(CFG_MPC55XX)\r
uint32_t McuE_GetPeripheralClock( McuE_PeriperalClock_t type );\r
#endif\r
-imask_t McuE_EnterCriticalSection(void);\r
-void McuE_ExitCriticalSection(imask_t old_state);\r
+#include "McuExtensions.h"\r
\r
\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef _MCU_EXTENSIONS_H_\r
+#define _MCU_EXTENSIONS_H_\r
+\r
+#include "Std_Types.h"\r
+typedef uint32_t imask_t;\r
+\r
+imask_t McuE_EnterCriticalSection(void);\r
+void McuE_ExitCriticalSection(imask_t old_state);\r
+\r
+#endif\r
TASK_STATE_RUNNING,\r
} TaskStateType;\r
\r
+#define INVALID_TASK 0xdeadU\r
\r
typedef TaskStateType *TaskStateRefType;\r
\r
StatusType ReleaseResource( ResourceType ResID);\r
\r
/*\r
- * Define the scheduler resource as ~0\r
+ * Define scheduler as topmost\r
*/\r
-#define RES_SCHEDULER (ResourceType)(~0)\r
+#define RES_SCHEDULER OS_RESOURCE_CNT\r
\r
/*\r
* Priorities of tasks and resources\r
int OsGptChannelRef;\r
} OsDriver;\r
\r
-/*-------------------------------------------------------------------\r
- * Free running timer\r
- *-----------------------------------------------------------------*/\r
-typedef const uint32 OsTickType;\r
-void Os_SysTickInit( void );\r
-void Os_SysTickStart(uint32_t period_ticks);\r
-uint32_t Os_SysTickGetTimeElapsed( void );\r
+\r
\r
/*-------------------------------------------------------------------\r
* Counters\r
StatusType GetCounterValue( CounterType, TickRefType );\r
StatusType GetElapsedCounterValue( CounterType, TickRefType val, TickRefType elapsed_val);\r
\r
+\r
+/*-------------------------------------------------------------------\r
+ * System timer\r
+ *-----------------------------------------------------------------*/\r
+typedef const uint32 OsTickType;\r
+void Os_SysTickInit( void );\r
+void Os_SysTickStart(TickType period_ticks);\r
+TickType Os_SysTickGetValue( void );\r
+TickType Os_SysTickGetElapsedValue( TickType preValue );\r
+\r
/*-------------------------------------------------------------------\r
* Schedule Tables\r
*-----------------------------------------------------------------*/\r
OSServiceId_GetTaskState,\r
} OsServiceIdType;;\r
\r
-typedef struct os_error_s {\r
+typedef struct OsError {\r
OsServiceIdType serviceId;\r
uint32_t param1;\r
uint32_t param2;\r
uint32_t param3;\r
-} os_error_t;\r
+} OsErrorType;\r
\r
-extern os_error_t os_error;\r
+extern OsErrorType os_error;\r
\r
// TODO: Add the service id to all OS service methods.\r
static inline OsServiceIdType OSErrorGetServiceId(void) {\r
return os_error.serviceId;\r
}\r
\r
-extern os_error_t os_error;\r
+extern OsErrorType os_error;\r
\r
#define OSError_ActivateTask_TaskID ((TaskType) os_error.param1)\r
#define OSError_ChainTask_TaskID ((TaskType) os_error.param1)\r
\r
#define PDUR_INSTANCE_ID 0\r
\r
-#include "modules.h"\r
+#include "Modules.h"\r
\r
#include "PduR_Cfg.h"\r
#include "PduR_Types.h"\r
#define PduR_DevCheck(PduId,PduPtr,ApiId,...) \\r
if (PduRState == PDUR_UNINIT || PduRState == PDUR_REDUCED) { \\r
PDUR_DET_REPORTERROR(MODULE_ID_PDUR, PDUR_INSTANCE_ID, ApiId, PDUR_E_INVALID_REQUEST); \\r
- /* DEBUG(DEBUG_LOW,"PDU Router not initialized. Routing request ignored.\n"); */ \\r
return __VA_ARGS__; \\r
} \\r
if (PduPtr == 0 && PDUR_DEV_ERROR_DETECT) { \\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/** @addtogroup Port Port Driver\r
- * @{ */\r
-\r
-/** @file Port.h\r
- * API and type definitions for Port Driver.\r
- */\r
-\r
-#ifndef PORT_H_\r
-#define PORT_H_\r
-\r
-#define PORT_SW_MAJOR_VERSION 1\r
-#define PORT_SW_MINOR_VERSION 0\r
-#define PORT_SW_PATCH_VERSION 0\r
-\r
-#define PORT_AR_MAJOR_VERSION 3\r
-#define PORT_AR_MINOR_VERSION 0\r
-#define PORT_AR_PATCH_VERSION 2\r
-\r
-#include "Port_Cfg.h" /** @req PORT130 */\r
-\r
-#if (PORT_VERSION_INFO_API == STD_ON)\r
-void Port_GetVersionInfo(Std_VersionInfoType *versionInfo);\r
-#endif\r
-\r
-/** @name Error Codes */\r
-/** @req PORT051 */\r
-/** @req PORT116 */\r
-#define PORT_E_PARAM_PIN 0x0a\r
-#define PORT_E_DIRECTION_UNCHANGEABLE 0x0b\r
-#define PORT_E_PARAM_CONFIG 0x0c\r
-#define PORT_E_PARAM_INVALID_MODE 0x0d\r
-#define PORT_E_MODE_UNCHANGEABLE 0x0e\r
-#define PORT_E_UNINIT 0x0f\r
-//@}\r
-\r
-/** @name Service id's */\r
-//@{\r
-#define PORT_INIT_ID 0x00\r
-#define PORT_SET_PIN_DIRECTION_ID 0x01\r
-#define PORT_REFRESH_PORT_DIRECTION_ID 0x02\r
-#define PORT_GET_VERSION_INFO_ID 0x03\r
-#define PORT_SET_PIN_MODE_ID 0x04\r
-//@}\r
-\r
-/** @req PORT046\r
- * The type Port_PinDirectionType is a type for defining the direction of a Port Pin.\r
- * PORT_PIN_IN Sets port pin as input.\r
- * PORT_PIN_OUT Sets port pin as output.\r
- */\r
-typedef enum\r
-{\r
- PORT_PIN_IN = 0,\r
- PORT_PIN_OUT,\r
-} Port_PinDirectionType;\r
-\r
-#if defined(CFG_HC1X)\r
-/** @req PORT124 */\r
-typedef uint8 Port_PinModeType;\r
-\r
-#else // CFG_PPC, CFG_STM32_STAMP and others\r
-typedef uint32 Port_PinModeType;\r
-#endif\r
-\r
-void Port_Init(const Port_ConfigType *configType);\r
-#if (PORT_SET_PIN_DIRECTION_API == STD_ON)\r
-void Port_SetPinDirection(Port_PinType pin, Port_PinDirectionType direction);\r
-#endif\r
-void Port_RefreshPortDirection(void);\r
-#if (PORT_SET_PIN_MODE_API == STD_ON)\r
-void Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode);\r
-#endif\r
-\r
-#endif /*PORT_H_*/\r
-/** @} */\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/** @addtogroup Port Port Driver
+ * @{ */
+
+/** @file Port.h
+ * API and type definitions for Port Driver.
+ */
+
+#ifndef PORT_H_
+#define PORT_H_
+
+#define PORT_SW_MAJOR_VERSION 1
+#define PORT_SW_MINOR_VERSION 0
+#define PORT_SW_PATCH_VERSION 0
+
+#define PORT_AR_MAJOR_VERSION 3
+#define PORT_AR_MINOR_VERSION 1
+#define PORT_AR_PATCH_VERSION 0
+
+#include "Port_Cfg.h" /** @req PORT130 */
+
+#if (PORT_VERSION_INFO_API == STD_ON)
+void
+Port_GetVersionInfo(Std_VersionInfoType *versionInfo);
+#endif
+
+/** @name Error Codes */
+/** @req PORT051 */
+/** @req PORT116 */
+#define PORT_E_PARAM_PIN 0x0a
+#define PORT_E_DIRECTION_UNCHANGEABLE 0x0b
+#define PORT_E_PARAM_CONFIG 0x0c
+#define PORT_E_PARAM_INVALID_MODE 0x0d
+#define PORT_E_MODE_UNCHANGEABLE 0x0e
+#define PORT_E_UNINIT 0x0f
+//@}
+
+/** @name Service id's */
+//@{
+#define PORT_INIT_ID 0x00
+#define PORT_SET_PIN_DIRECTION_ID 0x01
+#define PORT_REFRESH_PORT_DIRECTION_ID 0x02
+#define PORT_GET_VERSION_INFO_ID 0x03
+#define PORT_SET_PIN_MODE_ID 0x04
+//@}
+
+/** @req PORT046
+ * The type Port_PinDirectionType is a type for defining the direction of a Port Pin.
+ * PORT_PIN_IN Sets port pin as input.
+ * PORT_PIN_OUT Sets port pin as output.
+ */
+typedef enum
+{
+ PORT_PIN_IN = 0, PORT_PIN_OUT,
+} Port_PinDirectionType;
+
+#if defined(CFG_HC1X)
+/** @req PORT124 */
+typedef uint8 Port_PinModeType;
+#else // CFG_PPC, CFG_STM32_STAMP and others
+typedef uint32 Port_PinModeType;
+#endif
+
+void
+Port_Init(const Port_ConfigType *configType);
+#if ( PORT_PIN_DIRECTION_CHANGES_ALLOWED == STD_ON )
+void
+Port_SetPinDirection(Port_PinType pin, Port_PinDirectionType direction);
+#endif
+void
+Port_RefreshPortDirection(void);
+#if (PORT_SET_PIN_MODE_API == STD_ON)
+void
+Port_SetPinMode(Port_PinType Pin, Port_PinModeType Mode);
+#endif
+
+#endif /*PORT_H_*/
+/** @} */
\r
\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
#ifndef RTE_H_\r
#define RTE_H_\r
\r
#include "Std_Types.h"\r
\r
-/* Contract \r
- * rte_sws_1143\r
- * <name>_<c>_<p>_<o>\r
- * <p> - port name, e.g \r
- * <c> - component name, e.g. doors, lights\r
- * <o> - operation name or element name\r
- *\r
- * and more \r
- * Rte_Pim?\r
- * Rte_CData?\r
- */\r
-\r
-/* \r
- * Generated, rte_sws_3730(p.154)\r
- */\r
-#define Rte_Send_p_d\r
-#define Rte_Switch_p_m\r
-#define Rte_Write_p_d\r
-#define Rte_Invalidate_p_d\r
-#define Rte_Feedback_p_d\r
-#define Rte_Read_p_d\r
-#define Rte_Receive_p_d\r
-#define Rte_Call_p_o\r
-#define Rte_Result_p_o\r
-#define Rte_Mode_p_o\r
-\r
-\r
// Errors\r
#define RTE_E_OK ((Std_ReturnType) 0)\r
#define RTE_E_INVALID ((Std_ReturnType) 1)\r
#define RTE_E_MAX_AGE_EXCEEDED ((Std_ReturnType) 64)\r
\r
\r
-// RTE Mode, TODO\r
-\r
-// Rte_Ports\r
-#define Rte_PortHandle_i_RP\r
-#define Rte_Ports_i_RP\r
-\r
-// Rte_NPorts\r
-#define Rte_NPorts_i_RP\r
-\r
-// Rte_Port\r
-//#define Rte_PortHandle_i_RP\r
-#define Rte_Port_RP\r
-\r
-// Rte_Send/Rte_Write/Rte_Switch\r
-#define Rte_Write_p_o\r
-#define Rte_Send_p_o\r
-#define Rte_Swich_p_o\r
-\r
-// Rte_Invalidate\r
-#define Rte_Invalidate_p_o\r
-\r
-// Rte_Feedback\r
-#define Rte_Feedback_p_o\r
-\r
-// Rte_Read\r
-#define Rte_Read_p_o\r
-\r
-// Rte_Receive\r
-#define Rte_Receive_p_o\r
-\r
-// Rte_Call\r
-#define Rte_Call_p_o\r
-\r
-// Rte_Result\r
-#define Rte_Result_p_o\r
-\r
-//Rte_Pim\r
-#define Rte_Pim_name\r
-\r
-// Rte_CData\r
-#define Rte_CData_name\r
-\r
-// Rte_IRead\r
-#define Rte_IRead_re_p_d\r
-\r
-// Rte_IWrite\r
-#define Rte_IWrite_re_p_d\r
-\r
-// Rte_IInvalidate\r
-#define Rte_IInvalidate_re_p_d\r
-\r
-// Rte_IStatus\r
-#define Rte_IStatus_re_p_d\r
-\r
-// Rte_IrvIRead\r
-#define Rte_IrvIRead_re_name\r
-\r
-// TODO: bla bla bla .. more methods\r
-//\r
-\r
-\r
-\r
-\r
#endif /*RTE_H_*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#ifndef CPU_H_\r
-#define CPU_H_\r
-\r
-#include <stdint.h>\r
-#include "stm32f10x.h"\r
-#include "core_cm3.h"\r
-\r
-#define SIMULATOR() (0==0)\r
-\r
-/* Call intrinsic functions directly */\r
-#define Irq_Disable() __disable_irq()\r
-#define Irq_Enable() __enable_irq()\r
-\r
-/* TODO: This is of course wrong */\r
-#define Irq_Save(_flags) _flags =_Irq_Save();\r
-#define Irq_Restore(_flags) _Irq_Restore(_flags);\r
-\r
-\r
-#define Irq_SuspendAll() Irq_Disable()\r
-#define Irq_ResumeAll() Irq_Enable()\r
-\r
-#define Irq_SuspendOs() Irq_Disable()\r
-#define Irq_ResumeOs() Irq_Enable()\r
-\r
-static inline unsigned long _Irq_Save(void)\r
-{\r
- unsigned long val = __get_PRIMASK();\r
- Irq_Disable();\r
- return val;\r
-}\r
-\r
-/*-----------------------------------------------------------------*/\r
-\r
-static inline void _Irq_Restore(unsigned mask) {\r
- __set_PRIMASK(mask);\r
-}\r
-\r
-#define CallService(index,param)\r
-\r
-#endif /* CPU_H_ */\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#ifndef CPU_H_
+#define CPU_H_
+
+#include <stdint.h>
+#include "stm32f10x.h"
+#include "core_cm3.h"
+
+/* Call intrinsic functions directly */
+#define Irq_Disable() __disable_irq()
+#define Irq_Enable() __enable_irq()
+
+#define Irq_Save(_flags) _flags = _Irq_Save();
+#define Irq_Restore(_flags) _Irq_Restore(_flags);
+
+#define Irq_SuspendAll() Irq_Disable()
+#define Irq_ResumeAll() Irq_Enable()
+
+#define Irq_SuspendOs() Irq_Disable()
+#define Irq_ResumeOs() Irq_Enable()
+
+static inline unsigned long _Irq_Save(void)
+{
+ unsigned long val = __get_PRIMASK();
+ Irq_Disable();
+ return val;
+}
+
+/*-----------------------------------------------------------------*/
+
+static inline void _Irq_Restore(unsigned mask) {
+ __set_PRIMASK(mask);
+}
+
+#define CallService(index,param)
+
+#endif /* CPU_H_ */
*/\r
\r
#include "core_cm3.h"\r
-#include "system_stm32f10x.h"\r
+//#include "system_stm32f10x.h"\r
#include <stdint.h>\r
\r
/** @addtogroup Exported_types\r
/* Buffer start/stop */
void *bufStart;
void *bufEnd;
-} CirqBufferType;
+} CirqBufferDynType;
+
+CirqBufferDynType *CirqBuffDynCreate( size_t size, size_t dataSize );
+int CirqBuffDynDestroy(CirqBufferDynType *cPtr );
+int CirqBuffDynPush( CirqBufferDynType *cPtr, void *dataPtr );
+int CirqBuffDynPop(CirqBufferDynType *cPtr, void *dataPtr );
+
+/* TODO: Static implementation */
-/* Dynamic implementation */
-CirqBufferType *CirqBuffDynCreate( size_t size, size_t dataSize );
-int CirqBuffDynDestroy(CirqBufferType *cPtr );
-/* Static implementation */
-CirqBufferType CirqBuffStatCreate(void *buffer, int maxCnt, size_t dataSize);
-int CirqBuffPush( CirqBufferType *cPtr, void *dataPtr );
-int CirqBuffPop(CirqBufferType *cPtr, void *dataPtr );
#endif /* CIRQ_BUFFER_H_ */
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+#ifndef CPU_H\r
+#define CPU_H\r
+\r
+#include "Std_Types.h"\r
+\r
+#define Irq_Save(flags)\r
+#define Irq_Restore(flags)\r
+\r
+#define Irq_Disable()\r
+#define Irq_Enable()\r
+\r
+#define Irq_SuspendAll() Irq_Disable()\r
+#define Irq_ResumeAll() Irq_Enable()\r
+\r
+#define Irq_SuspendOs() Irq_Disable()\r
+#define Irq_ResumeOs() Irq_Enable()\r
+\r
+#endif /* CPU_H */\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#ifndef MBOX_H_
+#define MBOX_H_
+
+#include "cirq_buffer.h"
+
+typedef struct
+{
+ CirqBufferType *cirqPtr;
+} Arc_MBoxType;
+
+
+typedef enum {
+ SOME_ERROR,
+} Arc_MBoxErrType;
+
+Arc_MBoxType* Arc_MBoxCreate( size_t size );
+void Arc_MBoxDestroy( Arc_MBoxType *mPtr );
+int Arc_MBoxPost( Arc_MBoxType *mPtr, void *msg );
+int Arc_MBoxFetch(Arc_MBoxType *mPtr, void *msg);
+
+#endif /* MBOX_H_ */
#endif\r
}\r
\r
-os_error_t os_error;\r
+OsErrorType os_error;\r
\r
//-------------------------------------------------------------------\r
\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef SLEEP_H_\r
+#define SLEEP_H_\r
+\r
+#include "os.h"\r
+\r
+#define SLEEP(_x_) \\r
+do{ \\r
+ uint32_t pval = McuE_EnterCriticalSection(); \\r
+ TaskType task; \\r
+ GetTaskID(&task); \\r
+ Sleep(_x_, task, EVENT_MASK_EVENT_SLEEP_ALARM ); \\r
+ McuE_ExitCriticalSection(pval); \\r
+ WaitEvent(EVENT_MASK_EVENT_SLEEP_ALARM); \\r
+ ClearEvent(EVENT_MASK_EVENT_SLEEP_ALARM); \\r
+}while(0);\r
+\r
+void Sleep(uint32_t nofTicks, TaskType TaskID, EventMaskType Mask );\r
+\r
+#endif /* SLEEP_H_ */\r
# build with:\r
-# make subdir1 - build the subdir1 \r
-# make subdir1/subdir2 - build subdir2\r
-# \r
-# clean:\r
-# Removed all generated files \r
+# $ make BOARDDIR=<board> BDIR=<dir>[,<dir>] CROSS_COMPILE=<gcc> all|clean|clean_all\r
#\r
-# BOARDDIR=<board dir> \r
+# TARGETS\r
+# all: Target when building\r
+# clean: Remove generatated files for a board \r
+# clean_all: Remove all generated files\r
+# help: Print some help\r
+#\r
+# VARIABLES:\r
+# BOARDDIR=<board dir> \r
# Select what board to build for \r
-\r
-# BOARDDIR=<board dir> \r
-# Select what board to build for\r
-# \r
-# Q=[(@)/empty] \r
+# BDIR=<dir>[,<dir>] \r
+# Select what directories to build. The kernel if always built.\r
+# CROSS_COMPILE\r
+# Specify the compiler to use. \r
+# Q=[(@)/empty] \r
# If Q=@ cmd's will not be echoed.\r
-# \r
-# Build\r
-# >make BOARDDIR=mpc551xsim BDIR=system/kernel,examples/simple all \r
-# Clean \r
-# >make BOARDDIR=mpc551xsim BDIR=system/kernel,examples/simple clean\r
+#\r
+# EXAMPLES\r
+# Clean all\r
+# $ make clean_all\r
+#\r
+# Clean for a specific board\r
+# $ make BDIR=mpc551xsim clean\r
+#\r
+# Build the simple example (assuming CROSS_COMPILE set)\r
+# $ make BOARDDIR= mpc551xsim BDIR=examples/simple all\r
#\r
\r
+\r
export UNAME:=$(shell uname)\r
\r
ifneq ($(findstring Darwin,$(UNAME)),)\r
export SED=sed\r
endif\r
\r
-\r
Q?=@\r
export Q\r
export TOPDIR = $(CURDIR)\r
\r
ifneq ($(filter clean_all,$(MAKECMDGOALS)),clean_all)\r
ifeq (${BOARDDIR},)\r
- $(error BOARDDIR is empty) \r
+# $(error BOARDDIR is empty) \r
endif\r
endif\r
\r
# Tools\r
# Ugly thing to make things work under cmd.exe \r
PATH := /usr/bin/:$(PATH) \r
-find := $(shell which find)\r
+#find := $(shell which find)\r
+FIND := $(shell which find)\r
\r
export objdir = obj_$(BOARDDIR)\r
\r
comma:= ,\r
split = $(subst $(comma), ,$(1))\r
dir_cmd_goals := $(call split,$(BDIR))\r
-cmd_cmd_goals := $(filter clean all install,$(MAKECMDGOALS))\r
+cmd_cmd_goals := $(filter all clean config,$(MAKECMDGOALS))\r
+\r
+# Check for CROSS_COMPILE\r
+ifneq ($(cmd_cmd_goals),)\r
+#ifndef CROSS_COMPILE\r
+# $(error CROSS_COMPILE not defined)\r
+#endif\r
+\r
+# Check that the board actually exist\r
+ifdef BOARDDIR\r
+ all_boards := $(subst boards/,,$(shell $(FIND) boards/ -maxdepth 1 -type d))\r
+ ifeq ($(filter $(BOARDDIR),$(all_boards)),)\r
+ $(error no such board: $(BOARDDIR), valid boards are: $(all_boards))\r
+ endif\r
+endif\r
+\r
+# Check BDIR\r
+endif\r
\r
libs:\r
mkdir -p $@\r
\r
+.PHONY all:\r
+\r
all: libs $(dir_cmd_goals)\r
\r
+\r
+test:\r
+ @echo $(all_boards)\r
+\r
show_build:\r
- @echo Building for $(dir_cmd_goals)\r
- @echo BOARDDIR: $(BOARDDIR)\r
- @echo ARCH_FAM/ARCH: $(ARCH_FAM)/$(ARCH)\r
+ @echo "BUILD INFO"\r
+ @echo "BOARDDIR: $(BOARDDIR) [$(origin BOARDDIR)]"\r
+ @echo "BDIR: $(BDIR) [$(origin BDIR)]"\r
+ @echo "CROSS_COMPILE: $(CROSS_COMPILE) [$(origin CROSS_COMPILE)]"\r
+ @echo "cmd_cmd_goals: $(cmd_cmd_goals)"\r
+ \r
\r
-\r
$(dir_cmd_goals) :: show_build FORCE \r
@echo ==========[ $@ ]===========\r
+ @if [ ! -d $@ ]; then echo "No such directory: \"$@\" quitting"; exit 1; fi\r
+@[ -d $@/$(objdir) ] || mkdir -p $@/$(objdir)\r
@chmod 777 $@/$(objdir)\r
$(Q)$(MAKE) -r -C $@/$(objdir) -f $(CURDIR)/scripts/rules.mk ROOTDIR=$(CURDIR) SUBDIR=$@ $(cmd_cmd_goals)\r
\r
FORCE:\r
\r
+.PHONY: boards\r
+boards:\r
+ @find . -type d -name *\r
+\r
clean_all:\r
@find . -type d -name obj_* | xargs rm -rf\r
@find . -type f -name *.a | xargs rm -rf\r
echo Done!\r
\r
+config: $(dir_cmd_goals) \r
+ \r
+.PHONY clean: \r
clean: $(dir_cmd_goals)\r
@echo "Clean:"\r
@echo " Removing objectfiles and libs for ARCH=$(ARCH)"\r
source ${SCRIPT_DIR}/guess_cc.sh
export BDIR=examples/tiny
-make BOARDDIR=et_stm32_stamp clean
-make BOARDDIR=et_stm32_stamp all
+make BOARDDIR=stm32_stm3210c clean
+make BOARDDIR=stm32_stm3210c all
if [ $? -ne 0 ]; then quit 1
fi
-export BDIR=system/kernel/testsystem
-make BOARDDIR=et_stm32_stamp clean
-make BOARDDIR=et_stm32_stamp all
+export BDIR=examples/simple
+make BOARDDIR=stm32_stm3210c clean
+make BOARDDIR=stm32_stm3210c all
if [ $? -ne 0 ]; then quit 1
fi
+
+# Problems memory..
+#export BDIR=system/kernel/testsystem/suite_01,system/kernel/testsystem/suite_02, system/kernel/testsystem/suite_03
+#make BOARDDIR=stm32_stm3210c clean
+#make BOARDDIR=stm32_stm3210c all
+#if [ $? -ne 0 ]; then quit 1
+#fi
+
+
#
# build_ppc
#
+# This script file is quite braindead... remake when time..
+
function quit {
echo
SCRIPT_DIR=`dirname $0`
ARCH=PPC
source ${SCRIPT_DIR}/guess_cc.sh
-
-export BDIR=system/kernel/testsystem
+
+export BDIR=system/kernel/testsystem/suite_01,system/kernel/testsystem/suite_02,,system/kernel/testsystem/suite_03
make BOARDDIR=mpc5554sim clean
make BOARDDIR=mpc5554sim all
if [ $? -ne 0 ]; then quit 1
if [ $? -ne 0 ]; then quit 1
fi
-export BDIR=system/kernel/testsystem,examples/blinker_node
+export examples/blinker_node
make BOARDDIR=mpc5567qrtech clean
make BOARDDIR=mpc5567qrtech all
if [ $? -ne 0 ]; then quit 1
fi
+
+# Build the examples...
+
+export BDIR=examples/blinker_node
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/pwm_node
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/pwm_node2
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/simple
+make BOARDDIR=mpc551xsim clean
+make BOARDDIR=mpc551xsim all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/switch_node
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+export BDIR=examples/tiny
+make BOARDDIR=mpc5516it clean
+make BOARDDIR=mpc5516it all
+if [ $? -ne 0 ]; then quit 1
+fi
+
+
+
+
+
+
+
+
#####\r
\r
inc-y += $(ROOTDIR)/include\r
-#inc-$(CFG_PPC) += $(ROOTDIR)/include/ppc\r
-#inc-$(CFG_ARM) += $(ROOTDIR)/include/arm\r
inc-y += $(ROOTDIR)/include/$(ARCH_FAM)\r
\r
-.PHONY config:\r
\r
-config:\r
+.PHONY clean: \r
+clean: FORCE\r
+ @-rm -f *.o *.d *.h *.elf *.a *.ldp\r
+\r
+.PHONY config: \r
+config: FORCE\r
@echo "board modules:" $(MOD_AVAIL)\r
@echo "example modules:" $(MOD_USE)\r
@echo $(MOD) ${def-y}\r
\r
+FORCE:\r
\r
$(ROOTDIR)/binaries:\r
@mkdir -p $@\r
\r
# build- targets are "end" target that the included makefile want's to build\r
-all: $(build-exe-y) $(build-hex-y) $(build-lib-y) $(ROOTDIR)/binaries\r
- @cp -v $(build-lib-y) $(build-exe-y) $(build-hex-y) $(ROOTDIR)/binaries\r
+.PHONY all:\r
+all: $(build-exe-y) $(build-hex-y) $(build-lib-y) $(build-bin-y) $(ROOTDIR)/binaries\r
+ @cp -v $(build-lib-y) $(build-exe-y) $(build-hex-y) $(build-bin-y) $(ROOTDIR)/binaries\r
\r
-#.PHONY post_process:\r
-#post_process:: $(ROOTDIR)/binaries\r
- \r
\r
# Determine what kind of filetype to build from \r
VPATH += $(ROOTDIR)/$(SUBDIR)/src\r
$(build-hex-y): $(build-exe-y)\r
@echo " >> OBJCOPY $@" \r
$(Q)$(CROSS_COMPILE)objcopy -O ihex $< $@\r
+ \r
+$(build-bin-y): $(build-exe-y)\r
+ @echo " >> OBJCOPY $@" \r
+ $(Q)$(CROSS_COMPILE)objcopy -O binary $< $@ \r
\r
+# Linker\r
# Could use readelf -S instead of parsing the *.map file.\r
$(build-exe-y): $(dep-y) $(obj-y) $(sim-y) $(libitem-y) $(ldcmdfile-y)\r
@echo " >> LD $@"\r
+ifeq ($(CROSS_COMPILE),)\r
+ $(Q)$(CC) $(LDFLAGS) -o $@ $(libpath-y) $(obj-y) $(lib-y) $(libitem-y) \r
+else \r
$(Q)$(LD) $(LDFLAGS) -T $(ldcmdfile-y) -o $@ $(libpath-y) --start-group $(obj-y) $(lib-y) $(libitem-y) --end-group $(LDMAPFILE)\r
ifdef CFG_MC912DG128A\r
@$(CROSS_COMPILE)objdump -h $@ | gawk -f $(ROOTDIR)/scripts/hc1x_memory.awk\r
/^\.data/ { print " data:" $$3+0 " bytes"; rom+=$$3; ram+=$$3}; \\r
/^\.bss/ { print " bss :" $$3+0 " bytes"; ram+=$$3}; \\r
END { print " ROM: ~" rom " bytes"; print " RAM: ~" ram " bytes"}' $(subst .elf,.map,$@)\r
+ifeq ($(BUILD_LOAD_MODULE),y)\r
+ @$(CROSS_COMPILE)objcopy -O srec $@ $@.raw.s19\r
+ srec_cat $@.raw.s19 --crop 0x8008000 0x803fffc --fill 0x00 0x8008000 0x803fffc --l-e-crc32 0x803fffc -o $@.lm.s19\r
+endif\r
+endif\r
endif\r
@echo\r
@echo " >>>>>>> DONE <<<<<<<<<"\r
@echo\r
\r
-\r
+ \r
$(size-exe-y): $(build-exe-y)\r
$(Q)$(OBJDUMP) -h $<\r
@echo TODO: Parse the file....\r
\r
-.PHONY clean:\r
- @-rm -f *.o *.d *.h *.elf *.a *.ldp\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
#include "EcuM.h"\r
#include "Modules.h"\r
#include "string.h"\r
\r
#if (ECUM_INCLUDE_NVRAM_MGR == STD_ON)\r
// Start timer to wait for NVM job to complete\r
- timer = Os_SysTickGetTimeElapsed();\r
+ timer = Os_SysTickGetValue();\r
#endif\r
\r
// Prepare the system to startup RTE\r
// Wait for the NVM job (NvmReadAll) to terminate\r
do {\r
NvM_GetErrorStatus(0, &readAllResult); // Read the multiblock status\r
- } while( (readAllResult == NVM_REQ_PENDING) && !(Os_SysTickGetTimeElapsed() - timer < internal_data.config->EcuMNvramReadAllTimeout) );\r
+ } while( (readAllResult == NVM_REQ_PENDING) && !(Os_SysTickGetValue() - timer < internal_data.config->EcuMNvramReadAllTimeout) );\r
#endif\r
\r
// Initialize drivers that need NVRAM data\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#include "EcuM.h"\r
+\r
+#if defined(USE_CANSM)\r
+extern const CanSM_ConfigType CanSM_Config;\r
+#endif\r
+#if defined(USE_COMM)\r
+extern const ComM_ConfigType ComM_Config;\r
+#endif\r
+#if defined(USE_NM)\r
+extern const Nm_ConfigType Nm_Config;\r
+#endif\r
+#if defined(USE_CANNM)\r
+extern const CanNm_ConfigType CanNm_Config;\r
+#endif\r
+\r
+EcuM_ConfigType EcuMConfig =\r
+{\r
+ .EcuMDefaultShutdownTarget = ECUM_STATE_RESET,\r
+ .EcuMDefaultShutdownMode = 0, // Don't care\r
+ .EcuMDefaultAppMode = OSDEFAULTAPPMODE,\r
+\r
+#if defined(USE_MCU)\r
+ .McuConfig = McuConfigData,\r
+#endif\r
+#if defined(USE_PORT)\r
+ .PortConfig = &PortConfigData,\r
+#endif\r
+#if defined(USE_CAN)\r
+ .CanConfig = &CanConfigData,\r
+#endif\r
+#if defined(USE_CANIF)\r
+ .CanIfConfig = &CanIf_Config,\r
+#endif\r
+#if defined(USE_CANSM)\r
+ .CanSMConfig = &CanSM_Config,\r
+#endif\r
+#if defined(USE_CANNM)\r
+ .CanNmConfig = &CanNm_Config,\r
+#endif\r
+#if defined(USE_COM)\r
+ .ComConfig = &ComConfiguration,\r
+#endif\r
+#if defined(USE_COMM)\r
+ .ComMConfig = &ComM_Config,\r
+#endif\r
+#if defined(USE_NM)\r
+ .NmConfig = &Nm_Config,\r
+#endif\r
+#if defined(USE_PDUR)\r
+ .PduRConfig = &PduR_Config,\r
+#endif\r
+#if defined(USE_DMA)\r
+ .DmaConfig = DmaConfig,\r
+#endif\r
+#if defined(USE_ADC)\r
+ .AdcConfig = AdcConfig,\r
+#endif\r
+#if defined(USE_PWM)\r
+ .PwmConfig = &PwmConfig,\r
+#endif\r
+#if defined(USE_GPT)\r
+ .GptConfig = GptConfigData,\r
+#endif\r
+};\r
+\r
+void EcuM_OnGoOffTwo( void ) {\r
+\r
+}\r
+\r
+void EcuM_AL_SwitchOff( void ) {\r
+\r
+}\r
rv = E_OS_VALUE;\r
goto err;\r
} else {\r
- if( Cycle == 0 ||\r
- (Cycle >= COUNTER_MIN_CYCLE(aPtr)) ||\r
- (Cycle <= COUNTER_MAX(aPtr)) ) {\r
- /* OK */\r
- } else {\r
+ if( Cycle != 0 &&\r
+ ( (Cycle < COUNTER_MIN_CYCLE(aPtr)) ||\r
+ (Cycle > COUNTER_MAX(aPtr)) ) ) {\r
/** @req OS304 */\r
rv = E_OS_VALUE;\r
goto err;\r
\r
OS_STD_END_3(OSServiceId_SetRelAlarm,AlarmId, Increment, Cycle);\r
}\r
+
+/**
+ * The system service occupies the alarm <AlarmID> element.
+ * When <start> ticks are reached, the task assigned to the alarm
+ *
+ * If the absolute value <start> is very close to the current counter
+ * value, the alarm may expire, and the task may become ready or
+ * the alarm-callback may be called before the system service
+ * returns to the user.
+ * If the absolute value <start> already was reached before the
+ * system call, the alarm shall only expire when the absolute value
+ * <start> is reached again, i.e. after the next overrun of the
+ * counter.
+ *
+ * If <cycle> is unequal zero, the alarm element is logged on again
+ * immediately after expiry with the relative value <cycle>.
+ *
+ * The alarm <AlarmID> shall not already be in use.
+ * To change values of alarms already in use the alarm shall be
+ * cancelled first.
+ *
+ * If the alarm is already in use, this call will be ignored and the
+ * error E_OS_STATE is returned.
+ *
+ * Allowed on task level and in ISR, but not in hook routines.
+ *
+ * @param AlarmId
+ * @param Start
+ * @param Cycle
+ * @return
+ */
\r
StatusType SetAbsAlarm(AlarmType AlarmId, TickType Start, TickType Cycle) {\r
\r
\r
Irq_Save(flags);\r
if( aPtr->active == 1 ) {\r
- rv = E_OS_STATE;\r
+ rv = E_OS_STATE;
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
\r
void interrupt( void ) {\r
\r
- apa((void *)0x123);\r
+// apa((void *)0x123);\r
}\r
\r
\r
\r
}\r
\r
+int func3( int a ) {\r
+ if( a == 0) {\r
+ return 5;\r
+ }\r
+ return 4;\r
+}\r
+\r
int func2( void ) {\r
int a;\r
a = 3;\r
\r
func1(5);\r
+ func3(0);\r
\r
return 2;\r
}\r
StatusType IncrementCounter( CounterType counter_id ) {\r
StatusType rv = E_OK;\r
OsCounterType *cPtr;\r
+ uint32_t flags;\r
cPtr = Os_CfgGetCounter(counter_id);\r
\r
+ Irq_Save(flags);\r
/** @req OS376 */\r
if( !IsCounterValid(counter_id) ) {\r
rv = E_OS_ID;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
if( ( cPtr->type != COUNTER_TYPE_SOFT ) ||\r
( counter_id >= Os_CfgGetCounterCnt() ) ) {\r
rv = E_OS_ID;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
Os_AlarmCheck(cPtr);\r
Os_SchTblCheck(cPtr);\r
\r
+ Irq_Restore(flags);\r
+\r
/** @req OS321 */\r
COUNTER_STD_END;\r
}\r
OsPcbType *curr_pcb = get_curr_pcb();\r
StatusType rv = E_OK;\r
\r
+ OS_DEBUG(D_EVENT,"# WaitEvent %s\n",Os_TaskGetCurrent()->name);\r
+\r
if( os_sys.int_nest_cnt != 0 ) {\r
rv = E_OS_CALLEVEL;\r
goto err;\r
goto err;\r
}\r
\r
- if ( Os_TaskOccupiesResouces(curr_pcb) ) {\r
+ if ( Os_TaskOccupiesResources(curr_pcb) ) {\r
rv = E_OS_RESOURCE;\r
goto err;\r
}\r
curr_pcb->ev_wait = Mask;\r
\r
if ( Os_SchedulerResourceIsFree() ) {\r
- POSTTASKHOOK();\r
- Os_TaskMakeWaiting(curr_pcb);\r
- Os_Dispatch(0);\r
+ // Os_TaskMakeWaiting(curr_pcb);\r
+ Os_Dispatch(OP_WAIT_EVENT);\r
+ assert( curr_pcb->state & ST_RUNNING );\r
} else {\r
Os_TaskMakeWaiting(curr_pcb);\r
}\r
OsPcbType *currPcbPtr;\r
uint32_t flags;\r
\r
- dest_pcb = os_get_pcb(TaskID);\r
-\r
+ OS_DEBUG(D_EVENT,"# SetEvent %s\n",Os_TaskGetCurrent()->name);\r
\r
if( TaskID >= Os_CfgGetTaskCnt() ) {\r
rv = E_OS_ID;\r
goto err;\r
}\r
\r
- if( (dest_pcb->state & ST_SUSPENDED ) ) {\r
- rv = E_OS_STATE;\r
- goto err;\r
- }\r
+ dest_pcb = os_get_pcb(TaskID);\r
\r
+#if (OS_STATUS_EXTENDED == STD_ON )\r
if( dest_pcb->proc_type != PROC_EXTENDED ) {\r
rv = E_OS_ACCESS;\r
goto err;\r
}\r
\r
+ if( (dest_pcb->state & ST_SUSPENDED ) ) {\r
+ rv = E_OS_STATE;\r
+ goto err;\r
+ }\r
+#endif\r
+\r
Irq_Save(flags);\r
\r
/* Calling SetEvent causes the task <TaskID> to be transferred\r
(dest_pcb->prio > currPcbPtr->prio) &&\r
(Os_SchedulerResourceIsFree()) )\r
{\r
- Os_Dispatch(0);\r
+ Os_Dispatch(OP_SET_EVENT);\r
}\r
\r
- } else if(dest_pcb->state & ST_READY ) {\r
+ } else if(dest_pcb->state & (ST_READY|ST_RUNNING) ) {\r
/* Hmm, we do nothing */\r
+ } else {\r
+ assert( 0 );\r
}\r
}\r
\r
OS_STD_END_2(OSServiceId_SetEvent,TaskID, Mask);\r
}\r
\r
+\r
+/**\r
+ * This service returns the current state of all event bits of the task\r
+ * <TaskID>, not the events that the task is waiting for.\r
+ * The service may be called from interrupt service routines, task\r
+ * level and some hook routines (see Figure 12-1).\r
+ * The current status of the event mask of task <TaskID> is copied\r
+ * to <Event>.\r
+ *\r
+ * @param TaskId Task whose event mask is to be returned.\r
+ * @param Mask Reference to the memory of the return data.\r
+ * @return\r
+ */\r
StatusType GetEvent( TaskType TaskId, EventMaskRefType Mask) {\r
\r
OsPcbType *dest_pcb;\r
\r
dest_pcb = os_get_pcb(TaskId);\r
\r
- VALIDATE_W_RV(dest_pcb->state & ST_SUSPENDED,E_OS_STATE);\r
VALIDATE_W_RV(dest_pcb->proc_type != PROC_EXTENDED,E_OS_ACCESS);\r
+ VALIDATE_W_RV(dest_pcb->state & ST_SUSPENDED,E_OS_STATE);\r
\r
*Mask = dest_pcb->ev_set;\r
\r
}\r
\r
\r
+/**\r
+ * The events of the extended task calling ClearEvent are cleared\r
+ * according to the event mask <Mask>.\r
+ *\r
+ *\r
+ * @param Mask\r
+ * @return\r
+ */\r
StatusType ClearEvent( EventMaskType Mask) {\r
StatusType rv = E_OK;\r
OsPcbType *pcb;\r
* - Jump to main?!\r
* - De-init for some devices?\r
*\r
- * @param type OS_REBOOT_COLD - Reboot cold. It quite close to reset.\r
+ * @param type OS_REBOOT_COLD - Reboot cold. Soft reset.\r
* OS_REBOOT_WARM - Reboot warm. Does not run init on sections (crt0)\r
*/\r
void Os_ArchReboot( int type );\r
\r
\r
#define PRETASKHOOK() \\r
+ assert( os_sys.curr_pcb->state & ST_RUNNING ); \\r
+ assert( os_sys.curr_pcb->flags == SYS_FLAG_HOOK_STATE_EXPECTING_PRE ); \\r
+ os_sys.curr_pcb->flags = SYS_FLAG_HOOK_STATE_EXPECTING_POST; \\r
if( os_sys.hooks->PreTaskHook != NULL ) { \\r
os_sys.hooks->PreTaskHook(); \\r
}\r
\r
#define POSTTASKHOOK() \\r
+ assert( os_sys.curr_pcb->state & ST_RUNNING ); \\r
+ assert( os_sys.curr_pcb->flags == SYS_FLAG_HOOK_STATE_EXPECTING_POST ); \\r
+ os_sys.curr_pcb->flags = SYS_FLAG_HOOK_STATE_EXPECTING_PRE; \\r
if( os_sys.hooks->PostTaskHook != NULL ) { \\r
os_sys.hooks->PostTaskHook(); \\r
}\r
// resource.c\r
void Os_ResourceGetInternal(void );\r
void Os_ResourceReleaseInternal( void );\r
+void Os_ResourceAlloc( OsResourceType *rPtr, OsPcbType *pcbPtr);\r
+void Os_ResourceFree( OsResourceType *rPtr , OsPcbType *pcbPtr);\r
\r
void Os_ResourceInit( void );\r
\r
+\r
+static inline void Os_ResourceFreeAll( OsPcbType *pcbPtr ) {\r
+ OsResourceType *rPtr;\r
+\r
+ /* Pop the queue */\r
+ TAILQ_FOREACH(rPtr, &pcbPtr->resource_head, listEntry ) {\r
+ Os_ResourceFree(rPtr,pcbPtr);\r
+ }\r
+}\r
+\r
+#if 0\r
/**\r
*\r
* @return 1 - if any resources were found.\r
}\r
return rv;\r
}\r
+#endif\r
\r
-static inline _Bool Os_TaskOccupiesResouces( OsPcbType *pcb ) {\r
+static inline _Bool Os_TaskOccupiesResources( OsPcbType *pcb ) {\r
return !(TAILQ_EMPTY(&pcb->resource_head));\r
}\r
\r
+/*\r
static inline void Os_GetSchedulerResource() {\r
os_sys.scheduler_lock = 1;\r
}\r
static inline void Os_ReleaseSchedulerResource() {\r
os_sys.scheduler_lock = 0;\r
}\r
-\r
+*/\r
+/*\r
static inline _Bool Os_SchedulerResourceIsOccupied() {\r
+#if 0\r
+ return (os_sys.resScheduler.owner != NO_TASK_OWNER );\r
+#else\r
return (os_sys.scheduler_lock == 1);\r
+#endif\r
}\r
+*/\r
+#define NO_TASK_OWNER (TaskType)(~0)\r
\r
static inline _Bool Os_SchedulerResourceIsFree() {\r
+#if 1\r
+ return (os_sys.resScheduler.owner == NO_TASK_OWNER );\r
+#else\r
return (os_sys.scheduler_lock == 0);\r
+#endif\r
}\r
\r
// Create.c\r
void OsTick( void );\r
\r
void *Os_Isr( void *stack, void *pcb_p );\r
-void Os_Dispatch( _Bool force );\r
+void Os_Dispatch( uint32_t op );\r
\r
#define STACK_PATTERN 0x42\r
\r
uint8_t *end = pcbPtr->stack.top;\r
rv = ( *end == STACK_PATTERN);\r
if( !rv ) {\r
- OS_DEBUG(D_TASK,"Stack End Mark is bad for %s curr: %08x curr: %08x\n",\r
+ OS_DEBUG(D_TASK,"Stack End Mark is bad for %s curr: %p curr: %p\n",\r
pcbPtr->name,\r
pcbPtr->stack.curr,\r
pcbPtr->stack.top );\r
# define OS_DEBUG(_mask,...) \\r
do { \\r
if( os_dbg_mask & (_mask) ) { \\r
- printf("[%08u] : ",(unsigned)GetOsTick()); \\r
+ printf("[%08u] : %s %d ",(unsigned)GetOsTick(), __FUNCTION__, __LINE__ ); \\r
printf(__VA_ARGS__ ); \\r
}; \\r
} while(0);\r
} OsStackType;\r
\r
\r
-\r
+#define SYS_FLAG_HOOK_STATE_EXPECTING_PRE 0\r
+#define SYS_FLAG_HOOK_STATE_EXPECTING_POST 1\r
\r
/* We do ISR and TASK the same struct for now */\r
typedef struct OsPcb {\r
OsEventType ev_wait; // TASK\r
OsEventType ev_set; // TASK\r
\r
+ uint32_t flags;\r
+\r
enum OsTaskSchedule scheduling; // TASK\r
/* belongs to this application */\r
struct OsApplication *application;\r
\r
// What resource that are currently held by this task\r
// Typically (1<<RES_xxx) | (1<<RES_yyy)\r
-// uint32_t resourceHolds;\r
+ uint32_t resourceMaskTaken;\r
\r
- TAILQ_HEAD(,OsResource) resource_head; // TASK\r
+ TAILQ_HEAD(head,OsResource) resource_head; // TASK\r
\r
const struct OsRomPcb *pcb_rom_p;\r
\r
SA_LIST_GET(&sPtr->expirePointList, SA_LIST_CNT(&sPtr->expirePointList)-1)->offset);\r
}\r
\r
+void Os_SchTblCheck(OsCounterType *c_p);\r
\r
\r
#endif /*SCHED_TABLE_I_H_*/\r
\r
struct os_conf_global_hook_s;\r
\r
+typedef enum {\r
+ OP_SET_EVENT = 1,\r
+ OP_WAIT_EVENT = 2,\r
+ OP_ACTIVATE_TASK = 4,\r
+ OP_TERMINATE_TASK = 8,\r
+ OP_SCHEDULE = 16,\r
+ OP_CHAIN_TASK = 32,\r
+ OP_RELEASE_RESOURCE = 64,\r
+} OpType ;\r
+\r
typedef struct sys_s {\r
// OsApplicationType *curr_application;\r
/* Current running task*/\r
OsPcbType *curr_pcb;\r
/* List of all tasks */\r
OsPcbType *pcb_list;\r
+\r
+ OsPcbType *chainedPcbPtr;\r
/* Interrupt nested count */\r
uint32 int_nest_cnt;\r
+ /* The current operation */\r
+ uint8_t op;\r
/* Ptr to the interrupt stack */\r
void *int_stack;\r
// The os tick\r
TickType tick;\r
// 1-The scheduler is locked (by GetResource() or something else)\r
- int scheduler_lock;\r
+// int scheduler_lock;\r
/* Hooks */\r
struct OsHooks *hooks;\r
\r
/* Current Application mode */\r
AppModeType appMode;\r
\r
+// uint32_t flags;\r
+\r
uint32_t task_cnt;\r
/* List of all pcb's,\r
* Only needed for non-static configuration of the kernel\r
TAILQ_HEAD(,OsPcb) pcb_head;\r
/* Ready queue */\r
TAILQ_HEAD(,OsPcb) ready_head;\r
+\r
+ /* Occording to OSEK 8.3 RES_SCHEDULER is accessible to all tasks */\r
+ OsResourceType resScheduler;\r
} sys_t;\r
\r
extern sys_t os_sys;\r
// ActivateTask(pid)\r
// SetEvent(pid)\r
static inline void Os_TaskMakeReady( OsPcbType *pcb ) {\r
- if( pcb->state != ST_READY ) {\r
+ if( !( pcb->state & ( ST_READY | ST_RUNNING )) ) {\r
pcb->state = ST_READY;\r
TAILQ_INSERT_TAIL(& os_sys.ready_head,pcb,ready_list);\r
OS_DEBUG(D_TASK,"Added %s to ready list\n",pcb->name);\r
\r
#define os_pcb_get_state(pcb) ((pcb)->state)\r
\r
-void os_swap_context(OsPcbType *old_pcb, OsPcbType *new_pcb );\r
+void Os_TaskSwapContext(OsPcbType *old_pcb, OsPcbType *new_pcb );\r
void Os_TaskSwapContextTo(OsPcbType *old_pcb, OsPcbType *new_pcb );\r
\r
\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-#include "Os.h"\r
-#include "internal.h"\r
-#include "arc.h"\r
-#include "debug.h"\r
-#include "arch.h"\r
-\r
-extern void Os_CfgGetInterruptStackInfo( OsStackType *stack );\r
-extern uint32_t McuE_GetSystemClock( void );\r
-extern OsTickType OsTickFreq;\r
-\r
-sys_t os_sys;\r
-\r
-Os_IntCounterType Os_IntDisableAllCnt;\r
-Os_IntCounterType Os_IntSuspendAllCnt;\r
-Os_IntCounterType Os_IntSuspendOsCnt;\r
-\r
-\r
-/**\r
- * Copy rom pcb data(r_pcb) to ram data\r
- *\r
- * @param pcb ram data\r
- * @param r_pcb rom data\r
- */\r
-\r
-static void os_pcb_rom_copy( OsPcbType *pcb, const OsRomPcbType *r_pcb ) {\r
-\r
-#if 0 //?????\r
- // Check to that the memory is ok\r
- {\r
- int cnt = sizeof(OsPcbType);\r
- for(int i=0;i<cnt;i++) {\r
- if( *((unsigned char *)pcb) != 0 ) {\r
- while(1);\r
- }\r
- }\r
- }\r
-#endif\r
-\r
-// memset(pcb,sizeof(OsPcbType),0);\r
- pcb->pid = r_pcb->pid;\r
- pcb->prio = r_pcb->prio;\r
-#if ( OS_SC3 == STD_ON ) || ( OS_SC4 == STD_ON )\r
- pcb->application = Os_CfgGetApplObj(r_pcb->application_id);\r
-#endif\r
- pcb->entry = r_pcb->entry;\r
- pcb->proc_type = r_pcb->proc_type;\r
- pcb->autostart = r_pcb->autostart;\r
- pcb->stack= r_pcb->stack;\r
- pcb->pcb_rom_p = r_pcb;\r
- pcb->resource_int_p = r_pcb->resource_int_p;\r
- pcb->scheduling = r_pcb->scheduling;\r
- pcb->resourceAccess = r_pcb->resourceAccess;\r
- pcb->activationLimit = r_pcb->activationLimit;\r
-// pcb->app = &app_list[r_pcb->app];\r
-// pcb->app_mask = app_mask[r_pcb->app];\r
- strncpy(pcb->name,r_pcb->name,16);\r
-}\r
-\r
-static _Bool init_os_called = 0;\r
-\r
-/**\r
- * Initialization of kernel structures and start of the first\r
- * task.\r
- */\r
-\r
-void InitOS( void ) {\r
- int i;\r
- OsPcbType *tmp_pcb;\r
- OsStackType int_stack;\r
-\r
- init_os_called = 1;\r
-\r
- DEBUG(DEBUG_LOW,"os_init");\r
-\r
- /* Clear sys */\r
- memset(&os_sys,0,sizeof(sys_t));\r
-\r
- Os_ArchInit();\r
-\r
- // Assign pcb list and init ready queue\r
- os_sys.pcb_list = pcb_list;\r
- TAILQ_INIT(& os_sys.ready_head);\r
- TAILQ_INIT(& os_sys.pcb_head);\r
-\r
- // Calc interrupt stack\r
- Os_CfgGetInterruptStackInfo(&int_stack);\r
- // TODO: 16 is arch dependent\r
- os_sys.int_stack = int_stack.top + int_stack.size - 16;\r
-\r
- // Init counter.. with alarms and schedule tables\r
- Os_CounterInit();\r
- Os_SchTblInit();\r
-\r
- // Put all tasks in the pcb list\r
- // Put the one that belong in the ready queue there\r
- // TODO: we should really hash on priority here to get speed, but I don't care for the moment\r
- // TODO: Isn't this just EXTENED tasks ???\r
- for( i=0; i < Os_CfgGetTaskCnt(); i++) {\r
- tmp_pcb = os_get_pcb(i);\r
-\r
- assert(tmp_pcb->prio<=OS_TASK_PRIORITY_MAX);\r
-\r
- os_pcb_rom_copy(tmp_pcb,os_get_rom_pcb(i));\r
- if( !(tmp_pcb->proc_type & PROC_ISR) ) {\r
- Os_ContextInit(tmp_pcb);\r
- }\r
-\r
- TAILQ_INIT(&tmp_pcb->resource_head);\r
-\r
- Os_AddTask(tmp_pcb);\r
-\r
- DEBUG(DEBUG_LOW,"pid:%d name:%s prio:%d\n",tmp_pcb->pid,tmp_pcb->name,tmp_pcb->prio);\r
- }\r
-\r
- Os_ResourceInit();\r
-\r
- // Now all tasks should be created.\r
-}\r
-\r
-static void os_start( void ) {\r
- OsPcbType *tmp_pcb;\r
-\r
- // We will be setting up interrupts,\r
- // but we don't want them to fire just yet\r
- Irq_Disable();\r
-\r
- assert(init_os_called);\r
-\r
- /* TODO: fix ugly */\r
- /* Call the startup hook */\r
- extern struct OsHooks os_conf_global_hooks;\r
- os_sys.hooks = &os_conf_global_hooks;\r
- if( os_sys.hooks->StartupHook!=NULL ) {\r
- os_sys.hooks->StartupHook();\r
- }\r
-\r
- /* Alarm autostart */\r
- for(int j=0; j < Os_CfgGetAlarmCnt(); j++ ) {\r
- OsAlarmType *alarmPtr;\r
- alarmPtr = Os_CfgGetAlarmObj(j);\r
- if(alarmPtr->autostartPtr != NULL ) {\r
- const OsAlarmAutostartType *autoPtr = alarmPtr->autostartPtr;\r
-\r
- if( os_sys.appMode & autoPtr->appModeRef) {\r
- if( autoPtr->autostartType == ALARM_AUTOSTART_ABSOLUTE ) {\r
- SetAbsAlarm(j,autoPtr->alarmTime, autoPtr->cycleTime);\r
- } else {\r
- SetRelAlarm(j,autoPtr->alarmTime, autoPtr->cycleTime);\r
- }\r
- }\r
- }\r
- }\r
-\r
- Os_SchTblAutostart();\r
-\r
- // Set up the systick interrupt\r
- {\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
- Os_SysTickInit();\r
- Os_SysTickStart(sys_freq/OsTickFreq);\r
- }\r
-\r
- /* Find highest Autostart task */\r
- {\r
- OsPcbType *iterPcbPtr;\r
- OsPriorityType topPrio = -1;\r
-\r
- TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {\r
- if( iterPcbPtr->autostart ) {\r
- if( iterPcbPtr->prio > topPrio ) {\r
- tmp_pcb = iterPcbPtr;\r
- topPrio = iterPcbPtr->prio;\r
- }\r
- }\r
- }\r
- }\r
-\r
- // Swap in prio proc.\r
- {\r
- // FIXME: Do this in a more structured way.. setting os_sys.curr_pcb manually is not the way to go..\r
- os_sys.curr_pcb = tmp_pcb;\r
-\r
- // register this auto-start activation\r
- if (tmp_pcb->proc_type == PROC_BASIC) {\r
- assert(tmp_pcb->activations < tmp_pcb->activationLimit);\r
- tmp_pcb->activations++;\r
- }\r
-\r
- // NOTE! We don't go for os_swap_context() here..\r
- // first arg(NULL) is dummy only\r
- Os_TaskSwapContextTo(NULL,tmp_pcb);\r
- // We should not return here\r
- assert(0);\r
- }\r
-}\r
-#if 0\r
-static void os_start( void ) {\r
-\r
-}\r
-#endif\r
-\r
-#define TEST_DATA 12345\r
-int test_data = TEST_DATA;\r
-int test_bss = 0;\r
-\r
-\r
-void noooo( void ) {\r
- while(1);\r
-}\r
-\r
-extern void EcuM_Init();\r
-int main( void )\r
-{\r
- EcuM_Init();\r
-\r
-}\r
-\r
-/**\r
- * Starts the OS\r
- *\r
- * @param Mode - Application mode to start in\r
- *\r
- */\r
-void StartOS(AppModeType Mode) {\r
-\r
- /* Check link file */\r
- if (TEST_DATA != test_data) {\r
- noooo();\r
- }\r
-\r
- if (test_bss != 0) {\r
- noooo();\r
- }\r
-\r
- os_sys.appMode = Mode;\r
-\r
- Os_CfgValidate();\r
-\r
- os_start();\r
-\r
- /** @req OS424 */\r
- assert(0);\r
-}\r
-\r
-/**\r
- * OS shutdown\r
- *\r
- * @param Error - Reason for shutdown\r
- */\r
-\r
-/** @req OS071 */\r
-void ShutdownOS( StatusType Error ) {\r
-\r
- if( os_sys.hooks->ShutdownHook != NULL ) {\r
- os_sys.hooks->ShutdownHook(Error);\r
- }\r
-\r
- Irq_Disable();\r
- /** @req OS425 */\r
- while(1) { }\r
-\r
-}\r
-\r
-\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include <stdlib.h>
+#include <string.h>
+#include "Os.h"
+#include "internal.h"
+#include "arc.h"
+#include "debug.h"
+#include "arch.h"
+
+extern void Os_CfgGetInterruptStackInfo( OsStackType *stack );
+extern uint32_t McuE_GetSystemClock( void );
+extern OsTickType OsTickFreq;
+
+sys_t os_sys;
+
+Os_IntCounterType Os_IntDisableAllCnt;
+Os_IntCounterType Os_IntSuspendAllCnt;
+Os_IntCounterType Os_IntSuspendOsCnt;
+
+
+/**
+ * Copy rom pcb data(r_pcb) to ram data
+ *
+ * @param pcb ram data
+ * @param r_pcb rom data
+ */
+
+static void os_pcb_rom_copy( OsPcbType *pcb, const OsRomPcbType *r_pcb ) {
+
+#if 0 //?????
+ // Check to that the memory is ok
+ {
+ int cnt = sizeof(OsPcbType);
+ for(int i=0;i<cnt;i++) {
+ if( *((unsigned char *)pcb) != 0 ) {
+ while(1);
+ }
+ }
+ }
+#endif
+
+// memset(pcb,sizeof(OsPcbType),0);
+ pcb->pid = r_pcb->pid;
+ pcb->prio = r_pcb->prio;
+#if ( OS_SC3 == STD_ON ) || ( OS_SC4 == STD_ON )
+ pcb->application = Os_CfgGetApplObj(r_pcb->application_id);
+#endif
+ pcb->entry = r_pcb->entry;
+ pcb->proc_type = r_pcb->proc_type;
+ pcb->autostart = r_pcb->autostart;
+ pcb->stack= r_pcb->stack;
+ pcb->pcb_rom_p = r_pcb;
+ pcb->resource_int_p = r_pcb->resource_int_p;
+ pcb->scheduling = r_pcb->scheduling;
+ pcb->resourceAccess = r_pcb->resourceAccess;
+ pcb->activationLimit = r_pcb->activationLimit;
+// pcb->app = &app_list[r_pcb->app];
+// pcb->app_mask = app_mask[r_pcb->app];
+ strncpy(pcb->name,r_pcb->name,16);
+ pcb->name[15] = '\0';
+}
+
+static _Bool init_os_called = 0;
+
+/**
+ * Initialization of kernel structures and start of the first
+ * task.
+ */
+
+void InitOS( void ) {
+ int i;
+ OsPcbType *tmp_pcb;
+ OsStackType int_stack;
+
+ init_os_called = 1;
+
+ DEBUG(DEBUG_LOW,"os_init");
+
+ /* Clear sys */
+ memset(&os_sys,0,sizeof(sys_t));
+
+ Os_ArchInit();
+
+ // Assign pcb list and init ready queue
+ os_sys.pcb_list = pcb_list;
+ TAILQ_INIT(& os_sys.ready_head);
+ TAILQ_INIT(& os_sys.pcb_head);
+
+ // Calc interrupt stack
+ Os_CfgGetInterruptStackInfo(&int_stack);
+ // TODO: 16 is arch dependent
+ os_sys.int_stack = int_stack.top + int_stack.size - 16;
+
+ // Init counter.. with alarms and schedule tables
+ Os_CounterInit();
+ Os_SchTblInit();
+
+ // Put all tasks in the pcb list
+ // Put the one that belong in the ready queue there
+ // TODO: we should really hash on priority here to get speed, but I don't care for the moment
+ // TODO: Isn't this just EXTENED tasks ???
+ for( i=0; i < Os_CfgGetTaskCnt(); i++) {
+ tmp_pcb = os_get_pcb(i);
+
+ assert(tmp_pcb->prio<=OS_TASK_PRIORITY_MAX);
+
+ os_pcb_rom_copy(tmp_pcb,os_get_rom_pcb(i));
+ if( !(tmp_pcb->proc_type & PROC_ISR) ) {
+ Os_ContextInit(tmp_pcb);
+ }
+
+ TAILQ_INIT(&tmp_pcb->resource_head);
+
+ Os_AddTask(tmp_pcb);
+
+ DEBUG(DEBUG_LOW,"pid:%d name:%s prio:%d\n",tmp_pcb->pid,tmp_pcb->name,tmp_pcb->prio);
+ }
+
+ Os_ResourceInit();
+
+ // Now all tasks should be created.
+}
+
+static void os_start( void ) {
+ OsPcbType *tmp_pcb;
+
+ // We will be setting up interrupts,
+ // but we don't want them to fire just yet
+ Irq_Disable();
+
+ assert(init_os_called);
+
+ /* TODO: fix ugly */
+ /* Call the startup hook */
+ extern struct OsHooks os_conf_global_hooks;
+ os_sys.hooks = &os_conf_global_hooks;
+ if( os_sys.hooks->StartupHook!=NULL ) {
+ os_sys.hooks->StartupHook();
+ }
+
+ /* Alarm autostart */
+ for(int j=0; j < Os_CfgGetAlarmCnt(); j++ ) {
+ OsAlarmType *alarmPtr;
+ alarmPtr = Os_CfgGetAlarmObj(j);
+ if(alarmPtr->autostartPtr != NULL ) {
+ const OsAlarmAutostartType *autoPtr = alarmPtr->autostartPtr;
+
+ if( os_sys.appMode & autoPtr->appModeRef) {
+ if( autoPtr->autostartType == ALARM_AUTOSTART_ABSOLUTE ) {
+ SetAbsAlarm(j,autoPtr->alarmTime, autoPtr->cycleTime);
+ } else {
+ SetRelAlarm(j,autoPtr->alarmTime, autoPtr->cycleTime);
+ }
+ }
+ }
+ }
+
+ Os_SchTblAutostart();
+
+ // Set up the systick interrupt
+ {
+ uint32_t sys_freq = McuE_GetSystemClock();
+ Os_SysTickInit();
+ Os_SysTickStart(sys_freq/OsTickFreq);
+ }
+
+ /* Find highest Autostart task */
+ {
+ OsPcbType *iterPcbPtr;
+ OsPriorityType topPrio = -1;
+
+ TAILQ_FOREACH(iterPcbPtr,& os_sys.pcb_head,pcb_list) {
+ if( iterPcbPtr->autostart ) {
+ if( iterPcbPtr->prio > topPrio ) {
+ tmp_pcb = iterPcbPtr;
+ topPrio = iterPcbPtr->prio;
+ }
+ }
+ }
+ }
+
+ // Swap in prio proc.
+ {
+ // FIXME: Do this in a more structured way.. setting os_sys.curr_pcb manually is not the way to go..
+ os_sys.curr_pcb = tmp_pcb;
+
+ // register this auto-start activation
+ assert(tmp_pcb->activations < tmp_pcb->activationLimit);
+ tmp_pcb->activations++;
+
+ // NOTE! We don't go for os_swap_context() here..
+ // first arg(NULL) is dummy only
+ Os_TaskSwapContextTo(NULL,tmp_pcb);
+ // We should not return here
+ assert(0);
+ }
+}
+#if 0
+static void os_start( void ) {
+
+}
+#endif
+
+#define TEST_DATA 12345
+int test_data = TEST_DATA;
+int test_bss = 0;
+
+
+void noooo( void ) {
+ while(1);
+}
+
+extern void EcuM_Init();
+int main( void )
+{
+ EcuM_Init();
+
+}
+
+/**
+ * Starts the OS
+ *
+ * @param Mode - Application mode to start in
+ *
+ */
+void StartOS(AppModeType Mode) {
+
+ /* Check link file */
+ if (TEST_DATA != test_data) {
+ noooo();
+ }
+
+ if (test_bss != 0) {
+ noooo();
+ }
+
+ os_sys.appMode = Mode;
+
+ Os_CfgValidate();
+
+ os_start();
+
+ /** @req OS424 */
+ assert(0);
+}
+
+/**
+ * OS shutdown
+ *
+ * @param Error - Reason for shutdown
+ */
+
+/** @req OS071 */
+void ShutdownOS( StatusType Error ) {
+
+ if( os_sys.hooks->ShutdownHook != NULL ) {
+ os_sys.hooks->ShutdownHook(Error);
+ }
+
+ Irq_Disable();
+ /** @req OS425 */
+ while(1) { }
+
+}
+
+
+
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#include <sys/types.h>\r
-#include <stdint.h>\r
-#include <string.h>\r
-#include "internal.h"\r
-#include "irq.h"\r
-#if 0\r
-\r
-\r
-#include <stdint.h>\r
-#include <stdlib.h>\r
-#include <assert.h>\r
-#include <sys/queue.h>\r
-#include <string.h>\r
-#include "internal.h"\r
-\r
-#endif\r
-\r
-\r
-// TODO: remove. Make soft links or whatever\r
-#if defined(CFG_ARM_CM3)\r
-#include "irq_types.h"\r
-//#include "stm32f10x.h"\r
-//#include "stm32f10x_arc.h"\r
-#endif\r
-\r
-extern caddr_t *sbrk(int);\r
-\r
-#define os_alloc(_x) sbrk(_x)\r
-\r
-OsPcbType * os_alloc_new_pcb( void ) {\r
- void *h = os_alloc(sizeof(OsPcbType));\r
- memset(h,0,sizeof(OsPcbType));\r
- assert(h!=NULL);\r
- return h;\r
-}\r
-\r
-#if 0\r
-typedef void (*Os_IsrEntryType)(void);\r
-\r
-\r
-typedef Os_IsrInfo_s {\r
- Os_IsrEntryType entry;\r
- uint32_t vector;\r
- uint8_t priority;\r
-} Os_IsrInfoType;\r
-#endif\r
-\r
-\r
-extern TaskType Os_AddTask( OsPcbType *pcb );\r
-\r
-static uint8 stackTop = 0x42;\r
-\r
-TaskType Os_Arc_CreateIsr( void (*entry)(void ), uint8_t prio, const char *name )\r
-{\r
- OsPcbType *pcb = os_alloc_new_pcb();\r
- strncpy(pcb->name,name,TASK_NAME_SIZE);\r
- pcb->vector = -1;\r
- pcb->prio = prio;\r
- /* TODO: map to interrupt controller priority */\r
- assert(prio<=OS_TASK_PRIORITY_MAX);\r
- pcb->proc_type = PROC_ISR2;\r
- pcb->state = ST_SUSPENDED;\r
- pcb->entry = entry;\r
- pcb->stack.top = &stackTop;\r
-\r
- return Os_AddTask(pcb);\r
-}\r
-\r
-\r
-#if defined(CFG_ARM_CM3)\r
-extern void Irq_EOI2(void *pc);\r
-#endif\r
-\r
-\r
-/**\r
- * Handle ISR type 2 interrupts from interrupt controller.\r
- *\r
- * @param stack Ptr to the current stack\r
- * @param vector The vector that took the interrupt\r
- */\r
-void *Os_Isr( void *stack, void *pcb_p ) {\r
- struct OsPcb *pcb;\r
- struct OsPcb *preempted_pcb;\r
-\r
- os_sys.int_nest_cnt++;\r
-\r
- // Save info for preempted pcb\r
- preempted_pcb = get_curr_pcb();\r
- preempted_pcb->stack.curr = stack;\r
- preempted_pcb->state = ST_READY;\r
- OS_DEBUG(D_TASK,"Preempted %s\n",preempted_pcb->name);\r
-\r
- Os_StackPerformCheck(preempted_pcb);\r
-\r
- POSTTASKHOOK();\r
-\r
- pcb = (struct OsPcb *)pcb_p;\r
- pcb->state = ST_RUNNING;\r
- set_curr_pcb(pcb);\r
-\r
- PRETASKHOOK();\r
-\r
- // We should not get here if we're NON\r
- if( pcb->scheduling == NON) {\r
- // TODO:\r
- // assert(0);\r
- while(1);\r
- }\r
-\r
-#ifndef CFG_HCS12D\r
- Irq_Enable();\r
- pcb->entry();\r
- Irq_Disable();\r
-#else\r
- pcb->entry();\r
-#endif\r
-\r
- /** @req OS368 */\r
- if( Os_IrqAnyDisabled() ) {\r
- Os_IrqClearAll();\r
- ERRORHOOK(E_OS_DISABLEDINT);\r
- }\r
-\r
- /** @req OS369 */\r
- Os_ResourceCheckAndRelease(pcb);\r
-\r
- pcb->state = ST_SUSPENDED;\r
- POSTTASKHOOK();\r
-\r
- Irq_EOI();\r
-\r
- --os_sys.int_nest_cnt;\r
-\r
- // TODO: Check stack check marker....\r
- // We have preempted a task\r
- if( (os_sys.int_nest_cnt == 0) && (os_sys.scheduler_lock==0) ) { //&& is_idle_task() ) {\r
- /* If we get here:\r
- * - the preempted task is saved with large context.\r
- * - We are on interrupt stack..( this function )\r
- *\r
- * if we find a new task:\r
- * - just switch in the new context( don't save the old because\r
- * its already saved )\r
- */\r
- OsPcbType *new_pcb;\r
- new_pcb = Os_TaskGetTop();\r
-\r
- Os_StackPerformCheck(new_pcb);\r
-\r
- if( new_pcb != preempted_pcb ) {\r
- OS_DEBUG(D_TASK,"Found candidate %s\n",new_pcb->name);\r
-//#warning Os_TaskSwapContextTo should call the pretaskswaphook\r
-// TODO: This shuould go away!!!!\r
-#if defined(CFG_ARM_CM3)\r
- void *p;\r
- p = &&really_ugly;\r
- Irq_EOI2(p);\r
-really_ugly:\r
-#endif\r
- Os_TaskSwapContextTo(NULL,new_pcb);\r
- } else {\r
- if( new_pcb == NULL ) {\r
- assert(0);\r
- }\r
- preempted_pcb->state = ST_RUNNING;\r
- set_curr_pcb(preempted_pcb);\r
- }\r
- } else {\r
- set_curr_pcb(preempted_pcb);\r
- PRETASKHOOK();\r
- }\r
-\r
- return stack;\r
-}\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include "internal.h"
+#include "irq.h"
+#if 0
+
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <assert.h>
+#include <sys/queue.h>
+#include <string.h>
+#include "internal.h"
+
+#endif
+
+
+// TODO: remove. Make soft links or whatever
+#if defined(CFG_ARM_CM3)
+#include "irq_types.h"
+//#include "stm32f10x.h"
+//#include "stm32f10x_arc.h"
+#endif
+
+extern caddr_t *sbrk(int);
+
+#define os_alloc(_x) sbrk(_x)
+
+OsPcbType * os_alloc_new_pcb( void ) {
+ void *h = os_alloc(sizeof(OsPcbType));
+ memset(h,0,sizeof(OsPcbType));
+ assert(h!=NULL);
+ return h;
+}
+
+#if 0
+typedef void (*Os_IsrEntryType)(void);
+
+
+typedef Os_IsrInfo_s {
+ Os_IsrEntryType entry;
+ uint32_t vector;
+ uint8_t priority;
+} Os_IsrInfoType;
+#endif
+
+
+extern TaskType Os_AddTask( OsPcbType *pcb );
+
+static uint8 stackTop = 0x42;
+
+/**
+ * Creates an ISR dynamically
+ * @param entry
+ * @param prio
+ * @param name
+ *
+ * @return The PID of the ISR created
+ */
+TaskType Os_Arc_CreateIsr( void (*entry)(void ), uint8_t prio, const char *name )
+{
+ OsPcbType *pcb = os_alloc_new_pcb();
+ strncpy(pcb->name,name,TASK_NAME_SIZE);
+ pcb->vector = -1;
+ pcb->prio = prio;
+ /* TODO: map to interrupt controller priority */
+ assert(prio<=OS_TASK_PRIORITY_MAX);
+ pcb->proc_type = PROC_ISR2;
+ pcb->state = ST_SUSPENDED;
+ pcb->entry = entry;
+ pcb->stack.top = &stackTop;
+
+ return Os_AddTask(pcb);
+}
+
+/**
+ * Before we have proper editor for ISR2 use this function to add resources
+ * to an ISR2
+ *
+ * @param isr
+ * @param resource
+ * @return
+ */
+StatusType Os_IsrAddResource( TaskType isr, ResourceType resource ) {
+ return E_OK;
+}
+
+#if defined(CFG_ARM_CM3)
+extern void Irq_EOI2( void );
+#endif
+
+
+/**
+ * Handle ISR type 2 interrupts from interrupt controller.
+ *
+ * @param stack Ptr to the current stack
+ * @param vector The vector that took the interrupt
+ */
+void *Os_Isr( void *stack, void *isr_p ) {
+ struct OsPcb *isrPtr;
+ struct OsPcb *pPtr = NULL;
+
+ os_sys.int_nest_cnt++;
+
+ /* Check if we interrupted a task or ISR */
+ if( os_sys.int_nest_cnt == 1 ) {
+ /* We interrupted a task */
+ POSTTASKHOOK();
+
+ /* Save info for preempted pcb */
+ pPtr = get_curr_pcb();
+ pPtr->stack.curr = stack;
+ pPtr->state = ST_READY;
+ OS_DEBUG(D_TASK,"Preempted %s\n",pPtr->name);
+
+ Os_StackPerformCheck(pPtr);
+ } else {
+ /* We interrupted an ISR */
+ }
+
+ /* Grab the ISR "pcb" */
+ isrPtr = (struct OsPcb *)isr_p;
+ isrPtr->state = ST_RUNNING;
+
+ if( isrPtr->proc_type & ( PROC_EXTENDED | PROC_BASIC ) ) {
+ assert(0);
+ }
+
+#ifndef CFG_HCS12D
+ Irq_Enable();
+ isrPtr->entry();
+ Irq_Disable();
+#else
+ isrPtr->entry();
+#endif
+
+ /* Check so that ISR2 haven't disabled the interrupts */
+ /** @req OS368 */
+ if( Os_IrqAnyDisabled() ) {
+ Os_IrqClearAll();
+ ERRORHOOK(E_OS_DISABLEDINT);
+ }
+
+ /* Check so that the ISR2 have called ReleaseResource() for each GetResource() */
+ /** @req OS369 */
+ if( Os_TaskOccupiesResources(isrPtr) ) {
+ Os_ResourceFreeAll(isrPtr);
+ ERRORHOOK(E_OS_RESOURCE);
+ }
+
+ isrPtr->state = ST_SUSPENDED;
+
+ Irq_EOI();
+
+ --os_sys.int_nest_cnt;
+
+ // We have preempted a task
+ if( (os_sys.int_nest_cnt == 0) ) {
+
+ OsPcbType *new_pcb = Os_TaskGetTop();
+
+ Os_StackPerformCheck(new_pcb);
+
+ if( (new_pcb == os_sys.curr_pcb) ||
+ (os_sys.curr_pcb->scheduling == NON) ||
+ !Os_SchedulerResourceIsFree() )
+ {
+ /* Just bring the preempted task back to running */
+ os_sys.curr_pcb->state = ST_RUNNING;
+ PRETASKHOOK();
+ } else {
+ OS_DEBUG(D_TASK,"Found candidate %s\n",new_pcb->name);
+#if defined(CFG_ARM_CM3)
+ Irq_EOI2();
+#endif
+ Os_TaskSwapContextTo(NULL,new_pcb);
+ }
+ } else {
+ /* We have a nested interrupt, do nothing */
+ }
+
+ return stack;
+}
\r
#VPATH += $(ROOTDIR)/arch/arm/arm_cm3/kernel\r
vpath-y += $(ARCH_PATH-y)/kernel\r
-#obj-y += asm_sample.o\r
+obj-y += asm_sample.o\r
#CFLAGS_asm_sample.o += -O3\r
obj-y += arch_krn.o\r
obj-$(CFG_HCS12D) += arch_irq.o\r
dep-y += asm_offset.h\r
dep-y += kernel_offset.h\r
dep-$(CFG_ARM_CM3) += arch_offset.h\r
-obj-$(CFG_ARM_CM3) += misc.o\r
\r
\r
# ARM assembler generates "define STACK_APA $12". The extra '$' we want to go.\r
\r
#include "Os.h"\r
#include "internal.h"\r
+#include <assert.h>\r
+#include <string.h>\r
+\r
\r
#if !defined(MAX)\r
#define MAX(_x,_y) (((_x) > (_y)) ? (_x) : (_y))\r
#endif\r
\r
+\r
+/*\r
+Resource management at interrupt level is NOT supported\r
+\r
+\r
+Testing\r
+RM:\r
+1. Priority ceiling: Call GetResource() from preemtive\r
+ task and activate a task with higher priority than the ceiling protocol.\r
+ The higher priority task should be swapped in.\r
+2. Verify that you cannot allocate an internal resource with\r
+ a) GetResource()\r
+ b) ReleaseResource()\r
+3. Internal resource. Allocate 1 internal resource to 3 tasks of different\r
+ priorities. Verify that\r
+ a) Higher priority tasks than the group can preement\r
+ b) For tasks which have the same or lower priority as the highest priority within a group,\r
+ the tasks within the group behave like non preemptable tasks ( OSEK 4.6.3)\r
+4. Attempt to release a resource which has a lower ceiling priority\r
+ than the statically assigned priority of the calling task or\r
+ interrupt routine, E_OS_ACCESS\r
+5. The general restriction on some system calls that they are not to be called with resources\r
+ occupied (chapter 8.2) does not apply to internal resources, as internal resources are handled\r
+ within those calls. However, all standard resources have to be released before the internal\r
+ resource can be released (see chapter 8.2, \93LIFO principle\94).\r
+6. Check LIFO order. Return E_OS_ACCESS if not in LIFO order..\r
+7. Test Os_IsrAddResource().\r
+\r
+\r
+task\r
+- GetResource(RES_SCHEDULER) will lock the scheduler even for ISR2\r
+\r
+TODO:\r
+1. task.resourceAccess is already calculated by BSW builder. This is the bitmask\r
+ of what resources is accessable by the task.\r
+2.\r
+\r
+ task.rsrcAccessMask & (1 << RES_SCHEDULER)\r
+\r
+ *
+ */\r
+\r
/* INFO\r
* - If OsTaskSchedule = NON, Task it not preemptable, no internal resource may be assigned to a task\r
* (cause it already have one of prio 32)\r
#define valid_internal_id() (rPtr->nr < Os_CfgGetResourceCnt()) //&& (rPtr->type == RESOURCE_TYPE_INTERNAL) )\r
\r
\r
-static StatusType GetResource_( OsResourceType * );\r
-StatusType ReleaseResource_( OsResourceType * );\r
+void Os_ResourceAlloc( OsResourceType *rPtr, OsPcbType *pcbPtr) {\r
+ /* Save old task prio in resource and set new task prio */\r
+ rPtr->owner = pcbPtr->pid;\r
+ rPtr->old_task_prio = pcbPtr->prio;\r
+ pcbPtr->prio = rPtr->ceiling_priority;\r
+\r
+ if( rPtr->type != RESOURCE_TYPE_INTERNAL ) {\r
+ TAILQ_INSERT_TAIL(&pcbPtr->resource_head, rPtr, listEntry);\r
+ }\r
+}\r
+\r
+void Os_ResourceFree( OsResourceType *rPtr , OsPcbType *pcbPtr) {\r
+ assert( rPtr->owner == pcbPtr->pid );\r
+ rPtr->owner = NO_TASK_OWNER;\r
+ pcbPtr->prio = rPtr->old_task_prio;\r
+\r
+ if( rPtr->type != RESOURCE_TYPE_INTERNAL ) {\r
+ /* The list can't be empty here */\r
+ assert( !TAILQ_EMPTY(&pcbPtr->resource_head) );\r
+\r
+ /* The list should be popped in LIFO order */\r
+ assert( TAILQ_LAST(&pcbPtr->resource_head, head) == rPtr );\r
+\r
+ /* Remove the entry */\r
+ TAILQ_REMOVE(&pcbPtr->resource_head, rPtr, listEntry);\r
+ }\r
+}\r
\r
/**\r
* This call serves to enter critical sections in the code that are\r
* @param ResID\r
* @return\r
*/\r
+\r
+\r
StatusType GetResource( ResourceType ResID ) {\r
StatusType rv = E_OK;\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rPtr;\r
+ uint32_t flags;\r
+\r
+ Irq_Save(flags);\r
\r
if( ResID == RES_SCHEDULER ) {\r
- if ( Os_SchedulerResourceIsOccupied() ) {\r
- rv = E_OS_ACCESS;\r
- goto err;\r
- } else {\r
- Os_GetSchedulerResource();\r
- }\r
+\r
+ rPtr = &os_sys.resScheduler;\r
} else {\r
- if (ResID >= Os_CfgGetResourceCnt()) {\r
+ /* Check we can access it */\r
+ if( (pcbPtr->resourceAccess & (1<< ResID)) == 0 ) {\r
rv = E_OS_ID;\r
goto err;\r
}\r
\r
- OsResourceType *rPtr = Os_CfgGetResource(ResID);\r
- rv = GetResource_(rPtr);\r
+ rPtr = Os_CfgGetResource(ResID);\r
+ }\r
+\r
+ /* Check for invalid configuration */\r
+ if( (rPtr->owner != NO_TASK_OWNER) ||\r
+ (pcbPtr->prio > rPtr->ceiling_priority) )\r
+ {\r
+ rv = E_OS_ACCESS;\r
+ Irq_Restore(flags);\r
+ goto err;\r
}\r
\r
+ Os_ResourceAlloc(rPtr,pcbPtr);\r
+ Irq_Restore(flags);\r
+\r
if (rv != E_OK)\r
goto err;\r
\r
*/\r
\r
StatusType ReleaseResource( ResourceType ResID) {\r
- StatusType rv = E_OK;\r
+ StatusType rv = E_OK;\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rPtr;\r
+ uint32_t flags;\r
\r
+ Irq_Save(flags);\r
if( ResID == RES_SCHEDULER ) {\r
- if ( Os_SchedulerResourceIsFree() ) {\r
- rv = E_OS_NOFUNC;\r
- goto err;\r
- } else {\r
- Os_ReleaseSchedulerResource();\r
- }\r
+ rPtr = &os_sys.resScheduler;\r
} else {\r
- if (ResID >= Os_CfgGetResourceCnt()) {\r
+ /* Check we can access it */\r
+ if( (pcbPtr->resourceAccess & (1<< ResID)) == 0 ) {\r
rv = E_OS_ID;\r
goto err;\r
}\r
-\r
- OsResourceType *rPtr = Os_CfgGetResource(ResID);\r
- rv = ReleaseResource_(rPtr);\r
- }\r
-\r
- if (rv != E_OK)\r
- goto err;\r
-\r
- /* do a rescheduling (in some cases) (see OSEK OS 4.6.1) */\r
- if ( (Os_TaskGetCurrent()->scheduling == FULL) &&\r
- (os_sys.int_nest_cnt == 0) &&\r
- (Os_SchedulerResourceIsFree()) ) {\r
-\r
- OsPcbType* top_pcb = Os_TaskGetTop();\r
-\r
- /* only dispatch if some other ready task has higher prio */\r
- if (top_pcb->prio > Os_TaskGetCurrent()->prio) {\r
- long flags;\r
- Irq_Save(flags);\r
- Os_Dispatch(0);\r
- Irq_Restore(flags);\r
- }\r
- }\r
-\r
- OS_STD_END_1(OSServiceId_ReleaseResource,ResID);\r
-}\r
-\r
-\r
-/**\r
- * Internal GetResource function...\r
- *\r
- * @param rPtr\r
- * @return\r
- */\r
-\r
-static StatusType GetResource_( OsResourceType * rPtr ) {\r
- StatusType rv = E_OK;\r
-\r
- if( rPtr->nr == RES_SCHEDULER ) {\r
- // Lock the scheduler\r
- os_sys.scheduler_lock = 1;\r
+ rPtr = Os_CfgGetResource(ResID);\r
}\r
\r
- /* Check if valid resource */\r
- if( !valid_standard_id() ) {\r
- rv = E_OS_ID;\r
+ /* Check for invalid configuration */\r
+ if( rPtr->owner == NO_TASK_OWNER)\r
+ {\r
+ rv = E_OS_NOFUNC;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
- /* check if we have access\r
- * TODO: This gives access to all resources for ISR2s but we should respect the OsIsrResourceRef [0..*] here.\r
- */\r
- if ( Os_TaskGetCurrent()->proc_type != PROC_ISR2) {\r
- if ( !(Os_TaskGetCurrent()->resourceAccess & (1 << rPtr->nr)) ) {\r
- rv = E_OS_ACCESS;\r
- goto err;\r
- }\r
- }\r
-\r
- /* @req OSEK\r
- * Attempt to get a resource which is already occupied by any task\r
- * or ISR, or the statically assigned priority of the calling task or\r
- * interrupt routine is higher than the calculated ceiling priority,\r
- * E_OS_ACCESS\r
- */\r
- if( (Os_TaskGetCurrent()->prio > rPtr->ceiling_priority )\r
-#if ( OS_SC3 == STD_ON ) || ( OS_SC4 == STD_ON )\r
- || ( get_curr_application_id() != rPtr->application_owner_id)\r
-#endif\r
- || ( rPtr->owner != (TaskType)(-1)))\r
+ if( (pcbPtr->prio < rPtr->ceiling_priority))\r
{\r
rv = E_OS_ACCESS;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
- rPtr->owner = get_curr_pid();\r
- rPtr->old_task_prio = os_pcb_set_prio(Os_TaskGetCurrent() ,rPtr->ceiling_priority);\r
-\r
- if( rPtr->type != RESOURCE_TYPE_INTERNAL ) {\r
- TAILQ_INSERT_TAIL(&Os_TaskGetCurrent()->resource_head, rPtr, listEntry);\r
- }\r
-\r
- goto ok;\r
-err:\r
- ERRORHOOK(rv);\r
-ok:\r
- return rv;\r
-}\r
+ Os_ResourceFree(rPtr,pcbPtr);\r
\r
+ /* do a rescheduling (in some cases) (see OSEK OS 4.6.1) */\r
+ if ( (pcbPtr->scheduling == FULL) &&\r
+ (os_sys.int_nest_cnt == 0) &&\r
+ (Os_SchedulerResourceIsFree()) ) {\r
\r
-/**\r
- * Internal release resource..\r
- * @param rPtr\r
- * @return\r
- */\r
-StatusType ReleaseResource_( OsResourceType * rPtr ) {\r
- if (!valid_standard_id()) {\r
- return E_OS_ID;\r
- }\r
+ OsPcbType* top_pcb = Os_TaskGetTop();\r
\r
- /* check if we have access\r
- * TODO: This gives access to all resources for ISR2s but we should respect the OsIsrResourceRef [0..*] here.\r
- */\r
- if ( Os_TaskGetCurrent()->proc_type != PROC_ISR2) {\r
- if ( !(Os_TaskGetCurrent()->resourceAccess & (1 << rPtr->nr)) ) {\r
- return E_OS_ACCESS;\r
+ /* only dispatch if some other ready task has higher prio */\r
+ if (top_pcb->prio > Os_TaskGetCurrent()->prio) {\r
+ Os_Dispatch(OP_RELEASE_RESOURCE);\r
}\r
}\r
+ Irq_Restore(flags);\r
\r
- /* if we are not holding this resource */\r
- if (rPtr->owner != Os_TaskGetCurrent()->pid) {\r
- return E_OS_NOFUNC;\r
- }\r
-\r
- // Release it...\r
- rPtr->owner = (TaskType) (-1);\r
- TAILQ_REMOVE(&Os_TaskGetCurrent()->resource_head, rPtr, listEntry);\r
- os_pcb_set_prio(Os_TaskGetCurrent(), rPtr->old_task_prio);\r
- return E_OK;\r
+ OS_STD_END_1(OSServiceId_ReleaseResource,ResID);\r
}\r
\r
\r
void Os_ResourceGetInternal( void ) {\r
- OsResourceType *rt = os_get_resource_int_p();\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rt = pcbPtr->resource_int_p;\r
\r
if( rt != NULL ) {\r
OS_DEBUG(D_RESOURCE,"Get IR proc:%s prio:%u old_task_prio:%u\n",\r
get_curr_pcb()->name,\r
(unsigned)rt->ceiling_priority,\r
(unsigned)rt->old_task_prio);\r
- GetResource_(rt);\r
+ Os_ResourceAlloc(rt,pcbPtr);\r
}\r
}\r
\r
void Os_ResourceReleaseInternal( void ) {\r
- OsResourceType *rt = os_get_resource_int_p();\r
+ OsPcbType *pcbPtr = Os_TaskGetCurrent();\r
+ OsResourceType *rt = pcbPtr->resource_int_p;\r
\r
if( rt != NULL ) {\r
OS_DEBUG(D_RESOURCE,"Rel IR proc:%s prio:%u old_task_prio:%u\n",\r
get_curr_pcb()->name,\r
(unsigned)rt->ceiling_priority,\r
(unsigned)rt->old_task_prio);\r
- ReleaseResource_(rt);\r
+ Os_ResourceFree(rt,pcbPtr);\r
}\r
}\r
\r
OsResourceType *rsrc_p;\r
int topPrio;\r
\r
+\r
+ /* For now, assign the scheduler resource here */\r
+ os_sys.resScheduler.ceiling_priority = OS_RES_SCHEDULER_PRIO;\r
+ strcpy(os_sys.resScheduler.id,"RES_SCHEDULER");\r
+ os_sys.resScheduler.nr = RES_SCHEDULER;\r
+ os_sys.resScheduler.owner = NO_TASK_OWNER;\r
+\r
/* Calculate ceiling priority\r
* We make this as simple as possible. The ceiling priority\r
* is set to the same priority as the highest priority task that\r
* access it.\r
+ *\r
+ * Note that this applies both internal and standard resources.\r
* */\r
for( int i=0; i < Os_CfgGetResourceCnt(); i++) {\r
rsrc_p = Os_CfgGetResource(i);\r
for( int pi = 0; pi < Os_CfgGetTaskCnt(); pi++) {\r
\r
pcb_p = os_get_pcb(pi);\r
+\r
+\r
if(pcb_p->resourceAccess & (1<<i) ) {\r
topPrio = MAX(topPrio,pcb_p->prio);\r
}\r
- }\r
- rsrc_p->ceiling_priority = topPrio;\r
- }\r
-\r
\r
-\r
- /* From OSEK:\r
- * Non preemptable tasks are the most common usage of the concept\r
- * of internal resources; they are tasks with a special internal\r
- * resource of highest task priority assigned.\r
- * --> Interpret this as we can set the priority to 32.\r
- *\r
- * Assign an internal resource with prio 32 to the tasks\r
- * with scheduling=NON\r
- *\r
- *\r
- */\r
-#if 0\r
- for( int i=0; i < Os_CfgGetTaskCnt(); i++) {\r
- pcb_p = os_get_pcb(i);\r
- if(pcb_p->scheduling == NON ) {\r
- pcb_p->prio = OS_RES_SCHEDULER_PRIO;\r
+ /* Generator fix, add RES_SCHEDULER */\r
+ pcb_p->resourceAccess |= (1 << RES_SCHEDULER) ;\r
}\r
+ rsrc_p->ceiling_priority = topPrio;\r
}\r
-#endif\r
}\r
\r
return rv;\r
\r
extern TickType GetCountValue( OsCounterType *counter );\r
-void Os_SchTblUpdateState( OsSchTblType *stbl );\r
+\r
+static void Os_SchTblUpdateState( OsSchTblType *stbl );\r
\r
#if 0\r
enum OsScheduleTableSyncStrategy getSyncStrategy( OsSchTblType *stblPtr ) {\r
/** @req OS408 */\r
for(iter=0; iter < SA_LIST_CNT(&sTblPtr->expirePointList) ; iter++) {\r
delta = SA_LIST_GET(&sTblPtr->expirePointList,iter)->offset - delta;\r
- assert( delta >= minCycle );\r
+ /* initial offset may be zero (OS443) */\r
+ if(iter!=0) {\r
+ assert( delta >= minCycle );\r
+ }\r
assert( delta <= maxValue );\r
}\r
\r
/* Check if the expire point have been hit */\r
if( (sched_obj->state == SCHEDULETABLE_RUNNING ||\r
sched_obj->state == SCHEDULETABLE_RUNNING_AND_SYNCHRONOUS ) &&\r
- (c_p->val == sched_obj->expire_val) )\r
+ (c_p->val == sched_obj->expire_val) )\r
{\r
if ( sched_obj->expire_curr_index < SA_LIST_CNT(&sched_obj->expirePointList) ) {\r
- OsScheduleTableExpiryPointType * action;\r
- int i;\r
+ OsScheduleTableExpiryPointType * action;\r
+ int i;\r
\r
- action = SA_LIST_GET(&sched_obj->expirePointList,sched_obj->expire_curr_index);\r
+ action = SA_LIST_GET(&sched_obj->expirePointList,sched_obj->expire_curr_index);\r
\r
- /** @req OS407 */\r
- /** @req OS412 */\r
+ /** @req OS407 */\r
+ /** @req OS412 */\r
\r
- /* According to OS412 activate tasks before events */\r
- for(i=0; i< action->taskListCnt;i++ ) {\r
- ActivateTask(action->taskList[i]);\r
- }\r
+ /* According to OS412 activate tasks before events */\r
+ for(i=0; i< action->taskListCnt;i++ ) {\r
+ ActivateTask(action->taskList[i]);\r
+ }\r
\r
- for(i=0; i< action->eventListCnt;i++ ) {\r
- SetEvent( action->eventList[i].task, action->eventList[i].event);\r
- }\r
+ for(i=0; i< action->eventListCnt;i++ ) {\r
+ SetEvent( action->eventList[i].task, action->eventList[i].event);\r
+ }\r
}\r
// Calc new expire val and state\r
Os_SchTblUpdateState(sched_obj);\r
case SCHTBL_AUTOSTART_RELATIVE:\r
StartScheduleTableRel(j,autoPtr->offset);\r
break;\r
-#if defined(OS_SC2) || defined(OS_SC4)\r
+ #if defined(OS_SC2) || defined(OS_SC4)\r
case SCHTBL_AUTOSTART_SYNCHRONE:\r
/* TODO: */\r
break;\r
-#endif\r
+ #endif\r
default:\r
assert(0); // Illegal value\r
break;\r
*\r
* @param stbl Ptr to a Schedule Table.\r
*/\r
-void Os_SchTblUpdateState( OsSchTblType *stbl ) {\r
+static void Os_SchTblUpdateState( OsSchTblType *stbl ) {\r
\r
TickType delta;\r
TickType initalOffset;\r
OsSchTblType *nextStblPtr;\r
_Bool handleLast = 0;\r
\r
-\r
-\r
if( (stbl->expire_curr_index) == (SA_LIST_CNT(&stbl->expirePointList) - 1) ) {\r
/* We are at the last expiry point */\r
finalOffset = Os_SchTblGetFinalOffset(stbl);\r
*\r
*/\r
void Os_TaskStartExtended( void ) {\r
+\r
OsPcbType *pcb;\r
\r
pcb = Os_TaskGetCurrent();\r
+#if 0\r
Os_ResourceGetInternal();\r
Os_TaskMakeRunning(pcb);\r
+#endif\r
\r
- PRETASKHOOK();\r
+// PRETASKHOOK();\r
\r
Os_ArchFirstCall();\r
\r
+ /* We got back without any TerminateTask() or ChainTask()\r
+ *\r
+ * OSEK:\r
+ * Each task shall terminate itself at the end of its code.\r
+ * Ending the task without a call to TerminateTask or ChainTask\r
+ * is strictly forbidden and causes undefined behaviour.\r
+ *\r
+ * Autosar:\r
+ * OS052, OS069, OS070 and OS239\r
+ * */\r
+\r
/** @req OS239 */\r
Irq_Disable();\r
if( Os_IrqAnyDisabled() ) {\r
Os_IrqClearAll();\r
}\r
\r
-// TODO:Dont I have to check this at terminate task also?\r
+ /** @req OS070 */\r
+ if( Os_TaskOccupiesResources(pcb) ) {\r
+ Os_ResourceFreeAll(pcb);\r
+ }\r
\r
/** @req OS069 */\r
ERRORHOOK(E_OS_MISSINGEND);\r
*/\r
\r
void Os_TaskStartBasic( void ) {\r
+\r
OsPcbType *pcb;\r
\r
pcb = Os_TaskGetCurrent();\r
+#if 0\r
Os_ResourceGetInternal();\r
Os_TaskMakeRunning(pcb);\r
+#endif\r
\r
- PRETASKHOOK();\r
+// PRETASKHOOK();\r
\r
Os_ArchFirstCall();\r
\r
-\r
/** @req OS239 */\r
Irq_Disable();\r
if( Os_IrqAnyDisabled() ) {\r
Os_IrqClearAll();\r
}\r
\r
+ /** @req OS070 */\r
+ if( Os_TaskOccupiesResources(pcb) ) {\r
+ Os_ResourceFreeAll(pcb);\r
+ }\r
+\r
/** @req OS069 */\r
ERRORHOOK(E_OS_MISSINGEND);\r
\r
OsPcbType *top_prio_pcb = NULL;\r
OsPriorityType top_prio = PRIO_ILLEGAL;\r
\r
- OS_DEBUG(D_TASK,"os_find_top_prio_proc\n");\r
+// OS_DEBUG(D_TASK,"os_find_top_prio_proc\n");\r
\r
TAILQ_FOREACH(i_pcb,& os_sys.ready_head,ready_list) {\r
// all ready task are canidates\r
* @param force Force a re-scheduling\r
*\r
*/\r
-void Os_Dispatch( _Bool force ) {\r
+void Os_Dispatch( uint32_t op ) {\r
OsPcbType *pcbPtr;\r
- OsPcbType *currPcbPtr;\r
- (void)force;\r
+ OsPcbType *currPcbPtr = Os_TaskGetCurrent();\r
\r
assert(os_sys.int_nest_cnt == 0);\r
- assert(os_sys.scheduler_lock == 0 );\r
+ assert(Os_SchedulerResourceIsFree());\r
+\r
+ /* When calling post hook we must still be in ST_RUNNING */\r
+ assert( currPcbPtr->state & ST_RUNNING );\r
+ POSTTASKHOOK();\r
+\r
+ /* Go the correct state for running task */\r
+ if( op & ( OP_SET_EVENT | OP_SCHEDULE | OP_RELEASE_RESOURCE )) {\r
+ Os_TaskRunningToReady(currPcbPtr);\r
+ } else if( op & OP_WAIT_EVENT ) {\r
+ Os_TaskMakeWaiting(currPcbPtr);\r
+ } else if( op & OP_ACTIVATE_TASK ) {\r
+ Os_TaskMakeReady(currPcbPtr);\r
+ } else if( op & OP_CHAIN_TASK ) {\r
+ assert( os_sys.chainedPcbPtr != NULL );\r
+\r
+ /* # from chain top\r
+ * ----------------------------------------------------------\r
+ * 1 1 1 1 1->RUNNING\r
+ * 2 1 1 2 1->READY, 2->RUNNING\r
+ * 3 1 2 2 1->SUSPENDED/READY*, 2->RUNNING\r
+ * 4 1 2 3 1->SUSPENDED/READY*, 2->READY , 3-RUNNING\r
+ *\r
+ * *) Depends on the number of activations.\r
+ *\r
+ * - Chained task is always READY when coming from ChainTask()\r
+ */\r
+ if( currPcbPtr != os_sys.chainedPcbPtr ) {\r
+ /* #3 and #4 */\r
+ --currPcbPtr->activations;\r
+ if( currPcbPtr->activations <= 0 ) {\r
+ currPcbPtr->activations = 0;\r
+ Os_TaskMakeSuspended(currPcbPtr);\r
+ } else {\r
+ Os_TaskRunningToReady(currPcbPtr);\r
+ }\r
+ /* Chained task is already in READY */\r
+ }\r
+ os_sys.chainedPcbPtr = NULL;\r
+\r
+ } else if( op & OP_TERMINATE_TASK ) {\r
+ /*@req OSEK TerminateTask\r
+ * In case of tasks with multiple activation requests,\r
+ * terminating the current instance of the task automatically puts the next\r
+ * instance of the same task into the ready state\r
+ */\r
+ --currPcbPtr->activations;\r
+\r
+ if( currPcbPtr->activations <= 0 ) {\r
+ currPcbPtr->activations = 0;\r
+ Os_TaskMakeSuspended(currPcbPtr);\r
+ }\r
+ } else {\r
+ assert(0);\r
+ }\r
\r
pcbPtr = Os_TaskGetTop();\r
- currPcbPtr = Os_TaskGetCurrent();\r
+\r
+\r
+\r
/* Swap if we found any process or are forced (multiple activations)*/\r
if( pcbPtr != currPcbPtr ) {\r
\r
- /* Add us to the ready list */\r
- if( currPcbPtr->state & ST_RUNNING ) {\r
- /** @req OS052 */\r
- POSTTASKHOOK();\r
+ if( (op & OP_CHAIN_TASK) && ( currPcbPtr == os_sys.chainedPcbPtr ) ) {\r
+ /* #2 */\r
Os_TaskRunningToReady(currPcbPtr);\r
}\r
-\r
/*\r
* Swap context\r
*/\r
#endif\r
}\r
#endif\r
+ OS_DEBUG(D_TASK,"Swapping to: %s\n",pcbPtr->name);\r
+ Os_TaskSwapContext(currPcbPtr,pcbPtr);\r
\r
- Os_ArchSwapContext(currPcbPtr,pcbPtr);\r
-\r
- pcbPtr = Os_TaskGetCurrent();\r
- Os_TaskMakeRunning(pcbPtr);\r
+ /* ActivateTask, SetEvent, Schedule, .. */\r
+// pcbPtr = Os_TaskGetCurrent();\r
+// Os_TaskMakeRunning(pcbPtr);\r
+// PRETASKHOOK();\r
\r
- Os_ResourceGetInternal();\r
-\r
- PRETASKHOOK();\r
+// Os_ResourceGetInternal();\r
\r
} else {\r
- /* We want to run the same task, again. This only happens\r
- * when we have multiple activation of a basic task (\r
- * extended tasks have an activation limit of 1)\r
- */\r
-\r
+ OS_DEBUG(D_TASK,"Continuing task %s\n",pcbPtr->name);\r
/* Setup the stack again, and just call the basic task */\r
Os_StackSetup(pcbPtr);\r
+ /* TODO: release and get the internal resource ? */\r
+ Os_TaskMakeRunning(pcbPtr);\r
+ PRETASKHOOK();\r
Os_ArchSetSpAndCall(pcbPtr->stack.curr,Os_TaskStartBasic);\r
+ assert(0);\r
}\r
}\r
\r
-// We come here from\r
-// - os_init\r
\r
-/**\r
- * Called when a task is to be run for the first time.\r
+/*\r
+ * Thoughts on task switching and memory protection\r
+ *\r
+ * If we would have had memory protection:\r
+ * - Applications have their own MMU settings.\r
+ * - Swapping between tasks in same Application does NOT involve the MMU.\r
+ * - When running a non-trusted Application I need will have to:\r
+ * - Run kernel in supervisor mode.\r
+ * - Trap the start of each task\r
+ * - All calls to the kernel will have a trap interface, i.e. Os_ResourceGetInternal(ActivateTask(TASK_ID_foo);\r
+ * - An ISR2:\r
+ * - The interupt is taken, the kernel runs in supervisor mode\r
+ * - If the ISR2 activates\r
+ *\r
+ * Stack design:\r
+ * ALT1: 1 kernel stack...\r
+ * ALT2:\r
+ *\r
+ * Do we need virtual memory??\r
*/\r
-void Os_TaskSwapContextTo(OsPcbType *old_pcb, OsPcbType *new_pcb ) {\r
\r
+void Os_TaskSwapContext(OsPcbType *old_pcb, OsPcbType *new_pcb ) {\r
+ set_curr_pcb(new_pcb);\r
+ Os_ResourceGetInternal();\r
+ Os_TaskMakeRunning(new_pcb);\r
+ /* TODO: The pretask hook is not called with the right stack\r
+ * (it's called on the old task stack, not the new ) */\r
+ PRETASKHOOK();\r
+ Os_ArchSwapContext(old_pcb,new_pcb);\r
+}\r
+\r
+void Os_TaskSwapContextTo(OsPcbType *old_pcb, OsPcbType *new_pcb ) {\r
+ set_curr_pcb(new_pcb);\r
+ Os_ResourceGetInternal();\r
+ Os_TaskMakeRunning(new_pcb);\r
+ PRETASKHOOK();\r
Os_ArchSwapContextTo(old_pcb,new_pcb);\r
- /* TODO: When do we return here ?? */\r
+ assert(0);\r
}\r
\r
\r
* @param task_id Reference to the task which is currently running\r
* @return\r
*/\r
-StatusType GetTaskID( TaskRefType task_id ) {\r
- *task_id = os_sys.curr_pcb->pid;\r
- return E_OK;\r
+StatusType GetTaskID( TaskRefType TaskID ) {\r
+ StatusType rv = E_OK;\r
+ *TaskID = INVALID_TASK;\r
+\r
+\r
+ if( os_sys.curr_pcb->state & ST_RUNNING ) {\r
+ *TaskID = os_sys.curr_pcb->pid;\r
+ } else {\r
+ /* We have no running task, check level */\r
+\r
+ /* Call level is not from the OSEK specification but from the\r
+ * test specification */\r
+ if( os_sys.int_nest_cnt != 0 ) {\r
+ rv = E_OS_CALLEVEL;\r
+ goto err;\r
+ }\r
+ }\r
+err:\r
+ os_error.serviceId= OSServiceId_GetTaskID;\r
+ os_error.param1 = (uint32_t)TaskID;\r
+ return rv;\r
}\r
\r
\r
OsPcbType *pcb = os_get_pcb(TaskID);\r
StatusType rv = E_OK;\r
\r
- OS_DEBUG(D_TASK,"ActivateTask %s\n",pcb->name);\r
+ OS_DEBUG(D_TASK,"# ActivateTask %s\n",pcb->name);\r
\r
#if (OS_STATUS_EXTENDED == STD_ON )\r
+ /* extended */\r
TASK_CHECK_ID(TaskID);\r
+#endif\r
\r
+ Irq_Save(msr);\r
/* @req OS093 ActivateTask */\r
if( Os_IrqAnyDisabled() ) {\r
+ /* Standard */\r
rv = E_OS_DISABLEDINT;\r
goto err;\r
}\r
-#endif\r
-\r
- Irq_Save(msr);\r
-\r
- if( os_pcb_get_state(pcb) == ST_SUSPENDED ) {\r
- pcb->activations++;\r
- Os_Arc_SetCleanContext(pcb);\r
- Os_TaskMakeReady(pcb);\r
- } else {\r
-\r
- if( pcb->proc_type == PROC_EXTENDED ) {\r
- /** @req OSEK Activate task.\r
- * An extended task be activated once. See Chapter 4.3 in OSEK\r
- */\r
- rv = E_OS_LIMIT;\r
- goto err;\r
- }\r
\r
+ pcb->activations++;\r
+ if( os_pcb_get_state(pcb) != ST_SUSPENDED ) {\r
/** @req OSEK_? Too many task activations */\r
- if( pcb->activations == pcb->activationLimit ) {\r
+ if( pcb->activations >= (pcb->activationLimit + 1) ) {\r
+ /* Standard */\r
rv=E_OS_LIMIT;\r
+ Irq_Restore(msr);\r
+ --pcb->activations;\r
goto err;\r
- } else {\r
- pcb->activations++;\r
}\r
+ } else {\r
+ /* We have a suspended task, make it ready for use */\r
+ assert( pcb->activations == 1 );\r
+ Os_Arc_SetCleanContext(pcb);\r
+ Os_TaskMakeReady(pcb);\r
}\r
\r
-\r
/* Preempt only if we are preemptable and target has higher prio than us */\r
if( (Os_TaskGetCurrent()->scheduling == FULL) &&\r
(os_sys.int_nest_cnt == 0) &&\r
(pcb->prio > Os_TaskGetCurrent()->prio) &&\r
(Os_SchedulerResourceIsFree()))\r
{\r
- Os_Dispatch(0);\r
+ Os_Dispatch(OP_ACTIVATE_TASK);\r
}\r
\r
Irq_Restore(msr);\r
StatusType rv = E_OK;\r
uint32_t flags;\r
\r
- OS_DEBUG(D_TASK,"TerminateTask %s\n",curr_pcb->name);\r
+ OS_DEBUG(D_TASK,"# TerminateTask %s\n",curr_pcb->name);\r
\r
#if (OS_STATUS_EXTENDED == STD_ON )\r
\r
goto err;\r
}\r
\r
+#if 0\r
if ( Os_SchedulerResourceIsOccupied() ) {\r
rv = E_OS_RESOURCE;\r
goto err;\r
}\r
+#endif\r
\r
- /** @req OS070 */\r
- if( Os_ResourceCheckAndRelease(curr_pcb) == 1 ) {\r
+ if( Os_TaskOccupiesResources(curr_pcb) ) {\r
+ /* Note! Do NOT release the resource here */\r
rv = E_OS_RESOURCE;\r
goto err;\r
-\r
}\r
\r
-\r
#endif\r
-\r
-\r
Irq_Save(flags);\r
\r
- --curr_pcb->activations;\r
-\r
-\r
-// assert(curr_pcb->activations>=0);\r
-\r
- /*@req OSEK TerminateTask\r
- * In case of tasks with multiple activation requests,\r
- * terminating the current instance of the task automatically puts the next\r
- * instance of the same task into the ready state\r
- */\r
- if( curr_pcb->activations <= 0 ) {\r
- curr_pcb->activations = 0;\r
- POSTTASKHOOK();\r
- Os_TaskMakeSuspended(curr_pcb);\r
- } else {\r
- /* We need to add ourselves to the ready list again,\r
- * with a startup context. */\r
-\r
- /* We are already in ready list..\r
- * This should give us a clean start /tojo */\r
-// Os_Arc_SetCleanContext(curr_pcb);\r
- }\r
-\r
-// Os_ContextReInit(curr_pcb);\r
-\r
/* Force the dispatcher to find something, even if its us */\r
- Os_Dispatch(1);\r
+ Os_Dispatch(OP_TERMINATE_TASK);\r
\r
- Irq_Restore(flags);\r
- // It must find something here...otherwise something is very wrong..\r
assert(0);\r
\r
- rv = E_NOT_OK;\r
- goto err;\r
-\r
-\r
OS_STD_END(OSServiceId_TerminateTask);\r
}\r
\r
OsPcbType *curr_pcb = Os_TaskGetCurrent();\r
StatusType rv = E_OK;\r
uint32_t flags;\r
+ OsPcbType *pcb = os_get_pcb(TaskId);\r
+\r
+\r
+ OS_DEBUG(D_TASK,"# ChainTask %s\n",curr_pcb->name);\r
\r
#if (OS_STATUS_EXTENDED == STD_ON )\r
+ /* extended */\r
TASK_CHECK_ID(TaskId);\r
\r
if( os_sys.int_nest_cnt != 0 ) {\r
- rv = E_OS_CALLEVEL;\r
+ /* extended */\r
+ rv = E_OS_CALLEVEL;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
\r
+#endif\r
+\r
+ Irq_Save(flags);\r
+\r
+#if (OS_STATUS_EXTENDED == STD_ON )\r
+#if 0\r
if ( Os_SchedulerResourceIsOccupied() ) {\r
- rv = E_OS_RESOURCE;\r
+ /* extended */\r
+ rv = E_OS_RESOURCE;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
+#endif\r
\r
- if( Os_ResourceCheckAndRelease(curr_pcb) == 1 ) {\r
- rv = E_OS_RESOURCE;\r
+ if( Os_TaskOccupiesResources(curr_pcb) ) {\r
+ /* extended */\r
+ rv = E_OS_RESOURCE;\r
+ Irq_Restore(flags);\r
goto err;\r
}\r
#endif\r
- OsPcbType *pcb = os_get_pcb(TaskId);\r
-\r
- Irq_Save(flags);\r
-\r
- if (curr_pcb == pcb) {\r
- /* If we are chaining same task Dispatch will give us a clean start */\r
- Os_Dispatch(1);\r
-\r
- Irq_Restore(flags);\r
- /* It must find something here...otherwise something is very wrong.. */\r
- assert(0);\r
\r
- } else {\r
- /* We are chaining another task\r
- * We need to make sure it is in valid state */\r
- if( os_pcb_get_state(pcb) != ST_SUSPENDED ) {\r
- if( pcb->proc_type == PROC_EXTENDED ) {\r
- /** @req OSEK Activate task.\r
- * An extended task be activated once. See Chapter 4.3 in OSEK */\r
- rv = E_OS_LIMIT;\r
- goto err;\r
- }\r
-\r
- /** @req OSEK_? Too many task activations */\r
- if( pcb->activations == pcb->activationLimit ) {\r
- rv=E_OS_LIMIT;\r
- goto err;\r
- }\r
- }\r
-\r
- /* Terminate current task */\r
- --curr_pcb->activations;\r
- if( curr_pcb->activations <= 0 ) {\r
- curr_pcb->activations = 0;\r
- POSTTASKHOOK();\r
- Os_TaskMakeSuspended(curr_pcb);\r
+// if( os_pcb_get_state(pcb) != ST_SUSPENDED ) {\r
+ if (curr_pcb != pcb) {\r
+ /** @req OSEK_? Too many task activations */\r
+ if( (pcb->activations + 1) > pcb->activationLimit ) {\r
+ /* standard */\r
+ rv = E_OS_LIMIT;\r
+ Irq_Restore(flags);\r
+ goto err;\r
}\r
\r
- /* Activate chained task\r
- * We know it's ok here */\r
- pcb->activations++;\r
if( os_pcb_get_state(pcb) == ST_SUSPENDED ) {\r
+ assert( pcb->activations == 0 );\r
+ Os_Arc_SetCleanContext(pcb);\r
Os_TaskMakeReady(pcb);\r
}\r
\r
- if( (os_sys.int_nest_cnt == 0) &&\r
- (Os_SchedulerResourceIsFree()))\r
- {\r
- Os_Dispatch(1);\r
- }\r
-\r
- /* we will only come back here if we had activations left */\r
- assert(curr_pcb->activations > 0);\r
+ pcb->activations++;\r
\r
- /* restart ourselves */\r
- Os_StackSetup(curr_pcb);\r
- Os_ArchSetSpAndCall(curr_pcb->stack.curr, Os_TaskStartBasic);\r
}\r
\r
- Irq_Restore(flags);\r
+ os_sys.chainedPcbPtr = pcb;\r
\r
- if (rv != E_OK) goto err;\r
+ Os_Dispatch(OP_CHAIN_TASK);\r
+\r
+ assert( 0 );\r
\r
OS_STD_END_1(OSServiceId_ChainTask,TaskId);\r
}\r
*\r
*/\r
StatusType Schedule( void ) {\r
-// OsPcbType *pcb;\r
-// OsPcbType *curr_pcb = get_curr_pcb();\r
StatusType rv = E_OK;\r
uint32_t flags;\r
+ OsPcbType *curr_pcb = get_curr_pcb();\r
+\r
+ OS_DEBUG(D_TASK,"# Schedule %s\n",Os_TaskGetCurrent()->name);\r
\r
/* Check that we are not calling from interrupt context */\r
if( os_sys.int_nest_cnt != 0 ) {\r
goto err;\r
}\r
\r
+ if ( Os_TaskOccupiesResources(curr_pcb) ) {\r
+ rv = E_OS_RESOURCE;\r
+ goto err;\r
+ }\r
+\r
+ assert( Os_TaskGetCurrent()->state & ST_RUNNING );\r
+\r
/* We need to figure out if we have an internal resource,\r
* otherwise no re-scheduling.\r
* NON - Have internal resource prio OS_RES_SCHEDULER_PRIO (32+)\r
return E_OK;\r
}\r
\r
-#if 0\r
- if( os_get_resource_int_p() == NULL ) {\r
- /* We do nothing */\r
- return E_OK;\r
- }\r
-#endif\r
-\r
+ Irq_Save(flags);\r
OsPcbType* top_pcb = Os_TaskGetTop();\r
/* only dispatch if some other ready task has higher prio */\r
if (top_pcb->prio > Os_TaskGetCurrent()->prio) {\r
- Irq_Save(flags);\r
- Os_Dispatch(0);\r
- Irq_Restore(flags);\r
+ Os_Dispatch(OP_SCHEDULE);\r
}\r
\r
+ Irq_Restore(flags);\r
// Prevent label warning. Remove this when proper error handling is implemented.\r
if (0) goto err;\r
\r
\r
# Figure out the most of the modules to use.\r
-OPTIMAL_USE = T32_TERM SIMPLE_PRINTF RAMLOG\r
-MOD_USE+=KERNEL MCU $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
+OPTIMAL_USE = RAMLOG\r
+MOD_USE+=KERNEL MCU DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
$(warning $(MOD_USE)) \r
#MOD_USE+=KERNEL MCU T32_TERM SIMPLE_PRINTF RAMLOG\r
\r
* \r
* \r
* Generated by Arctic Studio (http://arccore.com)\r
-* on Wed May 05 23:09:13 CEST 2010\r
+* on Tue Jun 08 08:30:59 CEST 2010\r
*/\r
\r
\r
* \r
* \r
* Generated by Arctic Studio (http://arccore.com)\r
-* on Wed May 05 23:09:13 CEST 2010\r
+* on Tue Jun 08 08:30:59 CEST 2010\r
*/\r
\r
\r
// Isr Id's\r
\r
// Resource Id's\r
-#define RES_ID_int_1 0\r
+#define RES_ID_int_1 0\r
#define RES_ID_std_prio_3 1\r
#define RES_ID_std_prio_4 2\r
#define RES_ID_std_prio_5 3\r
\r
+obj-y+= arc.o\r
# included from rules.mk\r
\r
# =======================================================================\r
# What modules do we use\r
MOD_USE+=KERNEL MCU\r
\r
-MOD_USE+=T32_TERM\r
#MOD_USE+=PROTECTIONHOOK STARTUPHOOK SHUTDOWNHOOK ERRORHOOK 1\r
#MOD_USE+=PRETASKHOOK POSTTASKHOOK\r
CFG+=CONSOLE_T32\r
#libitem-y +=\r
\r
#linkfile\r
-ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+#ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
#ldcmdfile-y = $(ROOTDIR)/$(ARCH_PATH-y)/scripts/linkscript_gcc.ldf\r
\r
inc-y += ..\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
-\r
-#ifndef OS_TEST_H_\r
-#define OS_TEST_H_\r
-\r
-#include "test_framework.h"\r
-#include "debug.h"\r
-\r
-typedef void (*test_func_t)( void );\r
-\r
-#define TEST_FAIL(_text) test_fail((_text), __FILE__, __LINE__, __FUNCTION__ )\r
-#define TEST_OK() test_ok();\r
-#define TEST_ASSERT(_cond) if(!(_cond)) { TEST_FAIL(#_cond); }\r
-#define TEST_RUN() printf("Running test %d\n",test_nr);\r
-\r
-\r
-extern int test_suite;\r
-extern int test_nr;\r
-\r
-#define TASK_ID_ILL 99\r
-#define RES_ID_ILL 99\r
-#define ALARM_ID_ILL 99\r
-#define SCHTBL_ID_ILL 99\r
-#define COUNTER_ID_ILL 99\r
-\r
-#if 1\r
-#define SECTION_SUP\r
-#define SECTION_USER\r
-#else\r
-#define SECTION_SUP __attribute__ ((section(".text_app_sup")))\r
-#define SECTION_USER __attribute__ ((section(".text_app_user")))\r
-#endif\r
-\r
-#define SECTION_BSS_SUPER __attribute__ ((aligned (16),section(".bss")))\r
-#define SECTION_BSS_USER __attribute__ ((aligned (16),section(".bss")))\r
-\r
-#define OS_STR__(x) #x\r
-#define OS_STRSTR__(x) OS_STR__(x)\r
-\r
-#define DECLARE_TEST_BTASK(_nr, _task1, _task2, _task3 ) \\r
- __attribute__ ((section (".test_btask"))) const test_func_t btask_sup_matrix_ ## _nr[3] = { _task1, _task2, _task3 }\r
-\r
-#define DECLARE_TEST_ETASK(_nr, _task1, _task2, _task3 ) \\r
- __attribute__ ((section (".test_etask"))) const test_func_t etask_sup_matrix_ ## _nr[3] = { _task1, _task2, _task3 }\r
-\r
-#define DECLARE_TASKS(_nr) \\r
- void etask_sup_l_##_nr( void ); \\r
- void etask_sup_m_##_nr( void ); \\r
- void etask_sup_h_##_nr( void ); \\r
- void btask_sup_l_##_nr( void ); \\r
- void btask_sup_m_##_nr( void ); \\r
- void btask_sup_h_##_nr( void );\r
-\r
-\r
/*\r
- * Declare tests\r
+ * Contains mostly macros for the test-system. Most macro's have the same\r
+ * name as in embUnit, to make it easier to use.\r
+ *\r
*/\r
\r
-// Test master processes\r
-void OsIdle(void );\r
-void etask_master( void );\r
-void etask_sup_l( void ) SECTION_SUP;\r
-void etask_sup_m( void ) SECTION_SUP;\r
-void etask_sup_h( void ) SECTION_SUP;\r
-\r
-void btask_sup_l( void ) SECTION_SUP;\r
-void btask_sup_m( void ) SECTION_SUP;\r
-void btask_sup_h( void ) SECTION_SUP;\r
-\r
+#ifndef OS_TEST_H_\r
+#define OS_TEST_H_\r
\r
-// Tests\r
-DECLARE_TASKS(01);\r
-DECLARE_TASKS(02);\r
-DECLARE_TASKS(03);\r
-DECLARE_TASKS(04);\r
\r
#endif /* OS_TEST_H_ */\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.10
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Oct 10 21:14:06 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(\r
+ RES_ID_std_1,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_h_full,2048);\r
+DECLARE_STACK(btask_l_full,2048);\r
+DECLARE_STACK(btask_ll_non,2048);\r
+DECLARE_STACK(btask_m_full,2048);\r
+DECLARE_STACK(btask_m_non,2048);\r
+DECLARE_STACK(etask_h_full,2048);\r
+DECLARE_STACK(etask_l_full,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+DECLARE_STACK(etask_m_full_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_ll_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_full,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_non,\r
+ 1,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 5,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ RES_MASK_std_1 | 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full_2,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.10
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Oct 10 21:14:06 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_go 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+#define RES_ID_std_1 0\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+#define RES_MASK_std_1 (1 << 0)\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_h_full 1\r
+#define TASK_ID_btask_l_full 2\r
+#define TASK_ID_btask_ll_non 3\r
+#define TASK_ID_btask_m_full 4\r
+#define TASK_ID_btask_m_non 5\r
+#define TASK_ID_etask_h_full 6\r
+#define TASK_ID_etask_l_full 7\r
+#define TASK_ID_etask_m_full 8\r
+#define TASK_ID_etask_m_full_2 9\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_h_full( void );\r
+void btask_l_full( void );\r
+void btask_ll_non( void );\r
+void btask_m_full( void );\r
+void btask_m_non( void );\r
+void etask_h_full( void );\r
+void etask_l_full( void );\r
+void etask_m_full( void );\r
+void etask_m_full_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 0 \r
+#define OS_TASK_CNT 10\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 1\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 1\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU COMMON NEWLIB DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2">\r
+ <TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE UUID="e56d23e8-11ff-4651-ae2a-9f83a280d47c">\r
+ <SHORT-NAME>config_tm_01</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY />\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="29046d7d-db8b-4f92-afcf-525554458435">\r
+ <SHORT-NAME>config_tm_01</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION />\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/osek_01_tm</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/config_tm_01/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="e3a90a5a-3a2c-4b90-82fa-498d4bf14895">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG />\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="46e7afa2-40d4-4969-9216-dbb68fd7dc71">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="5c123a65-e644-421a-be3b-62886c189f46">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="179b1eed-bae4-4ff9-8101-c81794d849be">\r
+ <SHORT-NAME>etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7934bf2-d3cf-4df2-822a-c872121dcd2b">\r
+ <SHORT-NAME>etask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_tm_01/Os/std_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b1f99972-b3c7-41ec-a1ec-0d4dbe6b2e73">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2f0895f3-1d8a-4169-8fe1-105ff68a3a5a">\r
+ <SHORT-NAME>etask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f120ab09-188b-463b-a9e4-94f60e84f125">\r
+ <SHORT-NAME>btask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c3213aac-578d-4870-9e2a-7b0a731f9ae3">\r
+ <SHORT-NAME>btask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9de6649a-e85b-4a49-a9f4-5055e02480ca">\r
+ <SHORT-NAME>btask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="47b32026-3fe6-4fd5-b26e-fb0faa6bdac3">\r
+ <SHORT-NAME>btask_ll_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="de75266a-d9ea-4225-803f-b8bc02a446bf">\r
+ <SHORT-NAME>go</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="83c2a703-f295-4d91-b3c7-46bc6913e80e">\r
+ <SHORT-NAME>Counter1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="92cc71da-7618-4431-90e4-f8451031d2e7">\r
+ <SHORT-NAME>btask_m_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7f3d401c-7ca7-48e6-8686-bcb663fd878c">\r
+ <SHORT-NAME>etask_m_full_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="84a2cc88-79f3-45cd-bc3b-afcd525ba482">\r
+ <SHORT-NAME>std_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsResource</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsResource/OsResourceProperty</DEFINITION-REF>\r
+ <VALUE>STANDARD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES>\r
+</AUTOSAR>\r
+\r
--- /dev/null
+\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_tm_01.o\r
+obj-y += test_hooks.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+VPATH += ..\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * test.c\r
+ *\r
+ * Created on: 4 aug 2010\r
+ * Author: mahi\r
+ */\r
+\r
+#include "os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+#include "irq.h"\r
+\r
+/*\r
+ * This file tests test requirements OSEK_TM_XX for non-\r
+ *\r
+ *\r
+ * Priorities:\r
+ * ll - low low prio (used for scheduling only)\r
+ * l - low prio\r
+ * m - medium\r
+ * h - high prio\r
+ */\r
+\r
+\r
+enum OsekFixtureNr {\r
+ OSEK_TM_01 = 1,\r
+ OSEK_TM_02,\r
+ OSEK_TM_03,\r
+ OSEK_TM_04,\r
+ OSEK_TM_05,\r
+ OSEK_TM_06,\r
+ OSEK_TM_07,\r
+ OSEK_TM_08,\r
+ OSEK_TM_09,\r
+ OSEK_TM_10,\r
+ OSEK_TM_11,\r
+ OSEK_TM_12,\r
+ OSEK_TM_13,\r
+ OSEK_TM_14,\r
+ OSEK_TM_15,\r
+ OSEK_TM_16,\r
+ OSEK_TM_17,\r
+ OSEK_TM_18,\r
+ OSEK_TM_19,\r
+ OSEK_TM_20,\r
+ OSEK_TM_21,\r
+ OSEK_TM_22,\r
+ OSEK_TM_23,\r
+ OSEK_TM_24,\r
+ OSEK_TM_25,\r
+ OSEK_TM_26,\r
+ OSEK_TM_27,\r
+ OSEK_TM_28,\r
+ OSEK_TM_29,\r
+ OSEK_TM_30,\r
+ OSEK_TM_31,\r
+ OSEK_TM_32,\r
+ OSEK_TM_33,\r
+ OSEK_TM_34,\r
+ OSEK_TM_35,\r
+ OSEK_TM_36,\r
+ OSEK_TM_37,\r
+ OSEK_TM_38,\r
+ OSEK_TM_39,\r
+ OSEK_TM_40,\r
+ OSEK_TM_41,\r
+ OSEK_TM_42,\r
+ OSEK_TM_43,\r
+};\r
+\r
+TestWorldType TestWorld = {0};\r
+\r
+uint32_t testNrNon = 0;\r
+\r
+static uint8_t activations = 0;\r
+\r
+\r
+static void isrSoftInt0( void ) {\r
+ StatusType rv;\r
+ TaskType taskId;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_20:\r
+ TEST_SET_FIXTURE(OSEK_TM_20, SEQ_NR_02);\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OS_CALLEVEL );\r
+ TEST_SET_FIXTURE(OSEK_TM_20, SEQ_NR_03);\r
+ break;\r
+ case OSEK_TM_25:\r
+ TEST_SET_FIXTURE(OSEK_TM_25, SEQ_NR_02);\r
+ rv = ChainTask(TASK_ID_OsIdle);\r
+ TEST_ASSERT( rv == E_OS_CALLEVEL );\r
+ TEST_SET_FIXTURE(OSEK_TM_25, SEQ_NR_03);\r
+ break;\r
+ case OSEK_TM_35:\r
+ TEST_SET_FIXTURE(OSEK_TM_35, SEQ_NR_02);\r
+ rv = Schedule();\r
+ TEST_ASSERT( rv == E_OS_CALLEVEL );\r
+ TEST_SET_FIXTURE(OSEK_TM_35, SEQ_NR_03);\r
+ break;\r
+ case OSEK_TM_37:\r
+ TEST_SET_FIXTURE(OSEK_TM_37, SEQ_NR_02);\r
+ rv = GetTaskID(&taskId);\r
+ TEST_ASSERT( rv == E_OS_CALLEVEL );\r
+ TEST_SET_FIXTURE(OSEK_TM_37, SEQ_NR_03);\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+void OsIdle(void) {\r
+ while(1);\r
+}\r
+\r
+void etask_m_none ( void ) {\r
+ StatusType rv;\r
+ // 2. Call ActivateTask() from non-preemptive task on basic task\r
+ rv = ActivateTask(TASK_ID_btask_m_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+}\r
+\r
+/*\r
+ * ActivationLimit = 2
+ */\r
+void btask_l_full(void) {\r
+ StatusType rv;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_04:\r
+ TEST_SET_FIXTURE(OSEK_TM_04, SEQ_NR_03);\r
+ break;\r
+ case OSEK_TM_10:\r
+ activations++;\r
+ switch( activations ) {\r
+ case 1:\r
+ TEST_SET_FIXTURE(OSEK_TM_10, SEQ_NR_02);\r
+ break;\r
+ case 2:\r
+ TEST_SET_FIXTURE(OSEK_TM_10, SEQ_NR_03);\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ break;\r
+ case OSEK_TM_13:\r
+ { /* 2 activations */\r
+ activations++;\r
+ break;\r
+ }\r
+ case OSEK_TM_28:\r
+ TEST_SET_FIXTURE(OSEK_TM_28, SEQ_NR_05 );\r
+ rv = SetEvent( TASK_ID_etask_m_full,EVENT_MASK_go );\r
+ break;\r
+ case OSEK_TM_30:\r
+ activations++;\r
+ if( activations == 1) {\r
+ TEST_SET_FIXTURE(OSEK_TM_30, SEQ_NR_02);\r
+ } else if( activations == 2) {\r
+ TEST_SET_FIXTURE(OSEK_TM_30, SEQ_NR_03);\r
+ } else {\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ break;\r
+ case OSEK_TM_32:\r
+ activations++;\r
+ if( activations == 1) {\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_05);\r
+ } else if( activations == 2) {\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_06);\r
+ } else {\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ break;\r
+ case OSEK_TM_33:\r
+ TEST_SET_FIXTURE(OSEK_TM_33, SEQ_NR_02);\r
+ rv = ChainTask( TASK_ID_etask_m_full );\r
+ TEST_ASSERT( rv == E_OS_LIMIT );\r
+ TEST_SET_FIXTURE(OSEK_TM_33, SEQ_NR_03);\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ TerminateTask();\r
+}\r
+\r
+/*\r
+ * ActivationLimit = 2
+ */\r
+void btask_m_full( void ) {\r
+ StatusType rv;\r
+ TaskType taskId;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_05:\r
+ TEST_SET_FIXTURE(OSEK_TM_05, SEQ_NR_03);\r
+ break;\r
+\r
+ case OSEK_TM_14:\r
+ activations++;\r
+ switch(activations) {\r
+ case 1:\r
+ TEST_SET_FIXTURE(OSEK_TM_14, SEQ_NR_03 );\r
+ break;\r
+ case 2:\r
+ TEST_SET_FIXTURE(OSEK_TM_14, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ break;\r
+ case OSEK_TM_15:\r
+ activations++;\r
+ switch(activations) {\r
+ case 1:\r
+ rv = GetTaskID(&taskId);\r
+ TEST_ASSERT(rv == E_OK);\r
+ /* Activate ourself */\r
+ rv = ActivateTask(taskId);\r
+ TEST_ASSERT(rv == E_OK);\r
+\r
+ rv = ActivateTask(taskId);\r
+ TEST_ASSERT(rv == E_OS_LIMIT);\r
+ TEST_SET_FIXTURE(OSEK_TM_15, SEQ_NR_02);\r
+ break;\r
+\r
+ case 2:\r
+ TEST_SET_FIXTURE(OSEK_TM_15, SEQ_NR_03);\r
+\r
+ /* back to test task */\r
+ rv = SetEvent(TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+ break;\r
+ case OSEK_TM_28:\r
+ TEST_SET_FIXTURE(OSEK_TM_28, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ TerminateTask();\r
+}\r
+\r
+void etask_h_full( void ) {\r
+ StatusType rv;\r
+ switch(TestWorld.fixtureNr) {\r
+ case OSEK_TM_06:\r
+ TEST_SET_FIXTURE(OSEK_TM_06, SEQ_NR_02 );\r
+ break;\r
+ case OSEK_TM_07:\r
+ TEST_SET_FIXTURE(OSEK_TM_07, SEQ_NR_02 );\r
+ break;\r
+ case OSEK_TM_19:\r
+ TEST_SET_FIXTURE(OSEK_TM_19, SEQ_NR_02 );\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_TM_19, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+ TerminateTask();\r
+}\r
+\r
+void etask_l_full( void ) {\r
+\r
+ switch(TestWorld.fixtureNr) {\r
+ case OSEK_TM_08:\r
+ TEST_SET_FIXTURE(OSEK_TM_08, SEQ_NR_03 );\r
+ break;\r
+ case OSEK_TM_11:\r
+ TEST_SET_FIXTURE(OSEK_TM_11, SEQ_NR_03 );\r
+ break;\r
+ case OSEK_TM_31:\r
+ TEST_SET_FIXTURE(OSEK_TM_31, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+ TerminateTask();\r
+}\r
+\r
+void btask_h_full( void ) {\r
+ StatusType rv;\r
+ TaskType taskId;\r
+\r
+ switch(TestWorld.fixtureNr) {\r
+ case OSEK_TM_02:\r
+ TEST_SET_FIXTURE(OSEK_TM_02, SEQ_NR_02 );\r
+ break;\r
+ case OSEK_TM_03:\r
+ TEST_SET_FIXTURE(OSEK_TM_03, SEQ_NR_02 );\r
+ break;\r
+ case OSEK_TM_10:\r
+ TEST_SET_FIXTURE(OSEK_TM_10, SEQ_NR_02 );\r
+ break;\r
+ case OSEK_TM_12:\r
+ TEST_SET_FIXTURE(OSEK_TM_12, SEQ_NR_03 );\r
+ break;\r
+ case OSEK_TM_28:\r
+ TEST_SET_FIXTURE(OSEK_TM_28, SEQ_NR_02 );\r
+ rv = ActivateTask( TASK_ID_btask_m_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_TM_28, SEQ_NR_03 );\r
+ /* Terminate this task an:\r
+ * 1. run m task\r
+ * 2. run l task\r
+ */\r
+ rv = ChainTask( TASK_ID_btask_l_full );\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ case OSEK_TM_29:\r
+ activations++;\r
+ if( activations == 1) {\r
+ TEST_SET_FIXTURE(OSEK_TM_29, SEQ_NR_02 );\r
+ rv = GetTaskID(&taskId);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ChainTask( taskId );\r
+ TEST_ASSERT( 0 );\r
+ } else if(activations == 2) {\r
+ TEST_SET_FIXTURE(OSEK_TM_29, SEQ_NR_03 );\r
+ } else {\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ break;\r
+ case OSEK_TM_32:\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ TerminateTask();\r
+}\r
+\r
+void etask_m_full_2( void ) {\r
+\r
+ switch(TestWorld.fixtureNr) {\r
+ case OSEK_TM_09:\r
+ TEST_SET_FIXTURE(OSEK_TM_09, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+\r
+ TerminateTask();\r
+}\r
+\r
+\r
+/**\r
+ * Task used for scheduling only.
+ */\r
+void btask_ll_non( void ) {\r
+ StatusType rv;\r
+ /* Used for scheduling ONLY */\r
+ rv = SetEvent(TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+/* Terminate a lower-priority task.\r
+ *\r
+ *\r
+ * */\r
+void TestTaskRunLowerPrio( void ) {\r
+ StatusType rv;\r
+ /* Activate lowest prioriy task */\r
+ rv = ActivateTask(TASK_ID_btask_ll_non);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Let the low prio task run */\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+\r
+void TestActivateAndWait( TaskType task ) {\r
+ StatusType rv;\r
+ rv = ActivateTask(task);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Let the low prio task run */\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void btask_m_non( void ) {\r
+ StatusType rv;\r
+ EventMaskType mask;\r
+ testNrNon = TestWorld.testNr;\r
+ TaskType taskId;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_02:\r
+\r
+ /** @treq OSEK_TM_02\r
+ *\r
+ * Call ActivateTask() from non-preemptive task on suspended basic task\r
+ *\r
+ * No preemption of running task. Activated task becomes ready.\r
+ * Service returns E_OK\r
+ */\r
+ rv = ActivateTask(TASK_ID_btask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Run the higher prio task */\r
+ rv = Schedule();\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+\r
+ case OSEK_TM_06:\r
+ /** @treq OSEK_TM_06\r
+ *\r
+ * Call ActivateTask() from non-preemptive task on suspended extended task\r
+ *\r
+ * No preemption of running task. Activated task becomes ready and its\r
+ * events are cleared. Service returns E_OK
+ */\r
+\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ rv = GetEvent(TASK_ID_etask_h_full,&mask);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( mask == 0);\r
+ /* Run the higher prio task */\r
+ rv = Schedule();\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+\r
+ case OSEK_TM_12:\r
+ /** @treq OSEK_TM_12\r
+ *\r
+ * Call ActivateTask() from non-preemptive task on ready basic task\r
+ * which has not reached max number of activations\r
+ *\r
+ * No preemption of running task. Activation request is queued in ready\r
+ * list. Service returns E_OK\r
+ */\r
+ rv = ActivateTask(TASK_ID_btask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_TM_12, SEQ_NR_02 );\r
+ /* Run the higher prio task */\r
+ rv = Schedule();\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_TM_12, SEQ_NR_04 );\r
+ break;\r
+\r
+ case OSEK_TM_17:\r
+ {\r
+\r
+ /** @treq OSEK_TM_17\r
+ *\r
+ * Call ActivateTask() from non-preemptive task on running basic\r
+ * task which has not reached max number of activations\r
+ *\r
+ * No preemption of running task. Activation request is queued in ready list.\r
+ * Service returns E_OK\r
+ */\r
+ activations++;\r
+ switch( activations ) {\r
+ case 1:\r
+ rv = GetTaskID(&taskId);\r
+ TEST_ASSERT(rv == E_OK);\r
+ /* Run us again */\r
+ rv = ActivateTask(taskId);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_TM_17, SEQ_NR_02 );\r
+ TerminateTask();\r
+ break;\r
+ case 2:\r
+ TEST_SET_FIXTURE(OSEK_TM_17, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ }\r
+ break;\r
+\r
+ case OSEK_TM_32:\r
+\r
+ /** @treq OSEK_TM_32\r
+ *\r
+ * Call ChainTask() from non-preemptive task on ready basic task\r
+ * which has not reached max. Number of activations\r
+ *\r
+ * Running task is terminated, activation request is queued in\r
+ * ready list and ready task with highest priority is executed\r
+ */\r
+ activations = 0;\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_02 );\r
+ /* Activate higher prio task */\r
+ rv = SetEvent(TASK_ID_etask_m_full,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_03 );\r
+ /* Make it READY */\r
+ rv = ActivateTask( TASK_ID_btask_l_full );\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ rv = ChainTask( TASK_ID_btask_l_full );\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ /* Back to etask_m_full */\r
+ rv = SetEvent(TASK_ID_etask_m_full,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TerminateTask();\r
+ TEST_ASSERT( 0 );\r
+}\r
+\r
+/**\r
+ * The master in the tests
+ */\r
+void etask_m_full( void ) {\r
+\r
+ StatusType rv;\r
+ TaskType taskId;\r
+ TaskType isrTask;\r
+ TaskStateType taskState;\r
+\r
+ /** @treq OSEK_TM_01\r
+ *\r
+ * Call ActivateTask() from task-level with invalid task ID\r
+ * (task does not exist)\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_01, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_ILL);\r
+ TEST_ASSERT( rv == E_OS_ID);\r
+\r
+ /* OSEK_TM_02 is in another task */\r
+ TEST_SET_FIXTURE(OSEK_TM_02, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_m_non);\r
+\r
+ /** @treq OSEK_TM_03\r
+ *\r
+ * Call ActivateTask() from preemptive task on basic task which\r
+ * has higher priority than running task.\r
+ *\r
+ * Running task is preempted. Activated task becomes running.\r
+ * Service returns E_OK\r
+ * */\r
+ TEST_SET_FIXTURE(OSEK_TM_03, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_btask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ /* The higher prio task is run prior to getting here */\r
+ TEST_SET_FIXTURE(OSEK_TM_03, SEQ_NR_03 );\r
+\r
+ /** @treq OSEK_TM_04\r
+ *\r
+ * Call ActivateTask() from preemptive task on suspended basic\r
+ * task which has lower priority than running task.\r
+ *\r
+ * No preemption of running task. Activated task becomes ready.\r
+ * Service returns E_OK */\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_04, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_TM_04, SEQ_NR_02 );\r
+\r
+ /* Cleanup, let btask_l_full run */\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_04, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_TM_05\r
+ * Call ActivateTask() from preemptive task on suspended basic\r
+ * task which has equal priority as running task.\r
+ *\r
+ * No preemption of running task. Activated task becomes ready.\r
+ * Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_05, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_btask_m_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_TM_05, SEQ_NR_02 );\r
+\r
+ /* Cleanup, let btask_m_full run */\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_05, SEQ_NR_04 );\r
+\r
+\r
+ /* OSEK_TM_06 is in another task */\r
+ TEST_SET_FIXTURE(OSEK_TM_06, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_m_non);\r
+\r
+ /** @treq OSEK_TM_07\r
+ *\r
+ * Call ActivateTask() from preemptive task on suspended\r
+ * extended task which has higher priority than running task.\r
+ *\r
+ * Running task is preempted. Activated task becomes running and\r
+ * its events are cleared. Service returns E_OK
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_07, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_TM_07, SEQ_NR_03 );\r
+\r
+ /** @treq OSEK_TM_08\r
+ * Call ActivateTask() from preemptive task on suspended\r
+ * extended task which has lower priority than running task.\r
+ *\r
+ * No preemption of running task. Activated task becomes ready\r
+ * and its events are cleared. Service returns E_OK
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_08, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_etask_l_full);\r
+ TEST_SET_FIXTURE(OSEK_TM_08, SEQ_NR_02 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_08, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_TM_09\r
+ *\r
+ * Call ActivateTask() from preemptive task on suspended\r
+ * extended task which has equal priority as running task.\r
+ *\r
+ * No preemption of running task. Activated task becomes\r
+ * ready and its events are cleared. Service returns E_OK.
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_09, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_etask_m_full_2);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_TM_09, SEQ_NR_02 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_09, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_TM_10\r
+ *\r
+ * Call ActivateTask() on ready basic task which has reached max\r
+ * number of activations\r
+ *\r
+ * Service returns E_OS_LIMIT\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_10, SEQ_NR_01 );\r
+ activations = 0;\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OS_LIMIT);\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_10, SEQ_NR_04);\r
+\r
+ /** @treq OSEK_TM_11\r
+ *\r
+ * Call ActivateTask() on ready extended task\r
+ *\r
+ * Service returns E_OS_LIMIT\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_11, SEQ_NR_01 );\r
+ /* Make ready */\r
+ rv = ActivateTask(TASK_ID_etask_l_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_TM_11, SEQ_NR_02 );\r
+ rv = ActivateTask(TASK_ID_etask_l_full);\r
+ TEST_ASSERT( rv == E_OS_LIMIT);\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_11, SEQ_NR_04 );\r
+\r
+ /* OSEK_TM_12 is in another task */\r
+ TEST_SET_FIXTURE(OSEK_TM_12, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_m_non);\r
+\r
+\r
+ /** @treq OSEK_TM_13\r
+ *\r
+ * Call ActivateTask() from preemptive task on ready basic task which has\r
+ * not reached max number of activations and has lower priority than\r
+ * running task\r
+ *\r
+ * No preemption of running task. Activation request is queued in ready\r
+ * list. Service returns E_OK\r
+ */\r
+ activations = 0;\r
+ TEST_SET_FIXTURE(OSEK_TM_13, SEQ_NR_01 );\r
+ /* make ready */\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ /* Activate ready basic task */\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TestTaskRunLowerPrio();\r
+ TEST_ASSERT( activations == 2 );\r
+\r
+\r
+ /** @treq OSEK_TM_14\r
+ *\r
+ * Call ActivateTask() from preemptive task on ready basic task\r
+ * which has not reached max number of activations and has equal\r
+ * priority as running task\r
+ *\r
+ * No preemption of running task.Activation request is queued in ready\r
+ * list. Service returns E_OK\r
+ */\r
+ activations = 0;\r
+ TEST_SET_FIXTURE(OSEK_TM_14, SEQ_NR_01 );\r
+ /* make ready */\r
+ rv = ActivateTask(TASK_ID_btask_m_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ /* Activate ready basic task */\r
+ rv = ActivateTask(TASK_ID_btask_m_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_TM_14, SEQ_NR_02 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_ASSERT( activations == 2 );\r
+ TEST_SET_FIXTURE(OSEK_TM_14, SEQ_NR_05 );\r
+\r
+\r
+ /** @treq OSEK_TM_15\r
+ *\r
+ * Call ActivateTask() on running basic task which has reached max\r
+ * number of activations\r
+ *\r
+ * Service returns E_OS_LIMIT\r
+ */\r
+ /* OSEK_TM_15 is in another task */\r
+ activations = 0;\r
+ TEST_SET_FIXTURE(OSEK_TM_15, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_m_full);\r
+\r
+ /** @treq OSEK_TM_16\r
+ *\r
+ * Call ActivateTask() on running extended task\r
+ *\r
+ * Service returns E_OS_LIMIT\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_16, SEQ_NR_01 );\r
+ rv = GetTaskID(&taskId);\r
+ TEST_ASSERT(rv == E_OK);\r
+ /* Activate ourself */\r
+ rv = ActivateTask(taskId);\r
+ TEST_ASSERT(rv == E_OS_LIMIT);\r
+\r
+ /* OSEK_TM_17 is in another task */\r
+ activations = 0;\r
+ TEST_SET_FIXTURE(OSEK_TM_17, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_m_non);\r
+ TEST_SET_FIXTURE(OSEK_TM_17, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_TM_18\r
+ *\r
+ * Call ActivateTask() from preemptive task on running basic task\r
+ * which has not reached max number of activations\r
+ *\r
+ * No preemption of running task. Activation request is queued in\r
+ * ready list. Service returns E_OK\r
+ */\r
+\r
+ /* This is done in OSEK_TM_15, just record that that the test is OK */\r
+ TEST_SET_FIXTURE(OSEK_TM_18, SEQ_NR_01 );\r
+\r
+ /** @treq OSEK_TM_19\r
+ *\r
+ * Call ActivateTask() on waiting extended task\r
+ *\r
+ * Service returns E_OS_LIMIT\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_19, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_h_full );\r
+ /* etask_h_full should now be waiting */\r
+ TEST_SET_FIXTURE(OSEK_TM_19, SEQ_NR_03 );\r
+\r
+ rv = ActivateTask( TASK_ID_etask_h_full );\r
+ TEST_ASSERT( rv == E_OS_LIMIT );\r
+\r
+ /* Make it terminate */\r
+ rv = SetEvent( TASK_ID_etask_h_full,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_19, SEQ_NR_05 );\r
+\r
+ /** @treq OSEK_TM_20\r
+ *\r
+ * Call TerminateTask() from ISR category 2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ *\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_20, SEQ_NR_01 );\r
+\r
+ /* Create an ISR2 */\r
+ isrTask = Os_Arc_CreateIsr( isrSoftInt0, 8/*prio*/,"soft_0");\r
+ Irq_AttachIsr2(isrTask,NULL, IRQ_SOFTINT_0);\r
+\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_20, SEQ_NR_04);\r
+\r
+ /* OSEK_TM_21 not in Autosar */\r
+ TEST_SET_FIXTURE(OSEK_TM_21, SEQ_NR_01 );\r
+\r
+ /** @treq OSEK_TM_22\r
+ *\r
+ * Call TerminateTask() while still occupying a resource\r
+ *\r
+ * Running task is not terminated.\r
+ * Service returns E_OS_RESOURCE\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_22, SEQ_NR_01 );\r
+ rv = GetResource( RES_ID_std_1 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OS_RESOURCE );\r
+ rv = ReleaseResource( RES_ID_std_1 );\r
+ TEST_SET_FIXTURE(OSEK_TM_22, SEQ_NR_02 );\r
+\r
+ /** @treq OSEK_TM_23\r
+ *\r
+ * Call TerminateTask()\r
+ *\r
+ * Running task is terminated and ready task with highest priority\r
+ * is executed\r
+ */\r
+\r
+ /* This is already verified by the test-system */\r
+ TEST_SET_FIXTURE(OSEK_TM_23, SEQ_NR_01 );\r
+\r
+ /** @treq OSEK_TM_24\r
+ *\r
+ * Call ChainTask() from task-level. Task-ID is invalid (does not exist).\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_24, SEQ_NR_01 );\r
+ rv = ChainTask(TASK_ID_ILL);\r
+ TEST_ASSERT( rv == E_OS_ID );\r
+ TEST_SET_FIXTURE(OSEK_TM_24, SEQ_NR_02 );\r
+\r
+ /** @treq OSEK_TM_25\r
+ *\r
+ * Call ChainTask() from ISR category 2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_25, SEQ_NR_01 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_TM_25, SEQ_NR_04 );\r
+\r
+ /* OSEK_TM_26 not in Autosar */\r
+ TEST_SET_FIXTURE(OSEK_TM_26, SEQ_NR_01 );\r
+\r
+ /** @treq OSEK_TM_27\r
+ *\r
+ * Call ChainTask() while still occupying a resource\r
+ *\r
+ * Running task is not terminated. Service returns E_OS_RESOURCE\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_27, SEQ_NR_01 );\r
+ rv = GetResource( RES_ID_std_1 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ChainTask(TASK_ID_OsIdle);\r
+ TEST_ASSERT( rv == E_OS_RESOURCE );\r
+ rv = ReleaseResource( RES_ID_std_1 );\r
+ TEST_SET_FIXTURE(OSEK_TM_27, SEQ_NR_02 );\r
+\r
+\r
+ /** @treq OSEK_TM_28\r
+ *\r
+ * Call ChainTask() on suspended task\r
+ *\r
+ * Running task is terminated, chained task becomes ready and ready task\r
+ * with highest priority is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_28, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_h_full);\r
+ TEST_SET_FIXTURE(OSEK_TM_28, SEQ_NR_06 );\r
+ /* Cleanup */\r
+ TestTaskRunLowerPrio();\r
+\r
+ /** @treq OSEK_TM_29\r
+ *\r
+ * Call ChainTask() on running task\r
+ *\r
+ * Running task is terminated, chained task becomes ready and ready task\r
+ * with highest priority is executed\r
+ */\r
+ activations = 0;\r
+ TEST_SET_FIXTURE(OSEK_TM_29, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_btask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_TM_29, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_TM_30\r
+ *\r
+ * Call ChainTask() on ready basic task which has reached max number of\r
+ * activations.\r
+ *\r
+ * Running task is not terminated. Service returns E_OS_LIMIT\r
+ */\r
+\r
+ activations = 0;\r
+ TEST_SET_FIXTURE(OSEK_TM_30, SEQ_NR_01 );\r
+ /* First activation */\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* second activation */\r
+ rv = ActivateTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ rv = ChainTask(TASK_ID_btask_l_full);\r
+ TEST_ASSERT( rv == E_OS_LIMIT );\r
+ /* Cleanup */\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_30, SEQ_NR_04);\r
+\r
+ /** @treq OSEK_TM_31\r
+ *\r
+ * Call ChainTask() on ready extended task\r
+ *\r
+ * Running task is not terminated. Service returns E_OS_LIMIT\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_31, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_l_full );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ChainTask( TASK_ID_etask_l_full );\r
+ TEST_ASSERT( rv == E_OS_LIMIT );\r
+ TEST_SET_FIXTURE(OSEK_TM_31, SEQ_NR_02 );\r
+ /* Cleanup */\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_31, SEQ_NR_04);\r
+\r
+ /** @treq OSEK_TM_32\r
+ *\r
+ * Call ChainTask() from non-preemptive task on ready basic task which\r
+ * has not reached max number of activations\r
+ *\r
+ * Running task is terminated, activation request is queued in ready list\r
+ * and ready task with highest priority is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_m_non);\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_04 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_TM_32, SEQ_NR_07);\r
+\r
+ /** @treq OSEK_TM_33\r
+ *\r
+ * Call ChainTask() on waiting extended task\r
+ *\r
+ * Service returns E_OS_LIMIT\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_33, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_l_full);\r
+ TEST_SET_FIXTURE(OSEK_TM_33, SEQ_NR_04);\r
+ TestTaskRunLowerPrio();\r
+\r
+ /** @treq OSEK_TM_34\r
+ *\r
+ * Call Schedule() from task.\r
+ *\r
+ * Ready task with highest priority is executed. Service returns E_OK\r
+ */\r
+ /* Already tested in OSEK_TM_02 */\r
+ TEST_SET_FIXTURE(OSEK_TM_34, SEQ_NR_01 );\r
+\r
+ /** @treq OSEK_TM_35\r
+ *\r
+ * Call Schedule() from ISR category 2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_35, SEQ_NR_01 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_TM_35, SEQ_NR_04 );\r
+\r
+ /* OSEK_TM_36 not an OSEK/Autosar requirement */\r
+ TEST_SET_FIXTURE(OSEK_TM_36, SEQ_NR_01 );\r
+\r
+ /** @treq OSEK_TM_37\r
+ *\r
+ * Call GetTaskID() from ISR category 2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_37, SEQ_NR_01 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_TM_37, SEQ_NR_04 );\r
+\r
+ /* @treq OSEK_TM_38 not an OSEK/Autosar requirement */\r
+ TEST_SET_FIXTURE(OSEK_TM_38, SEQ_NR_01 );\r
+\r
+ /** @treq OSEK_TM_39\r
+ *\r
+ * Call GetTaskID() from task\r
+ *\r
+ * Return task ID of currently running task. Service returns E_OK\r
+ */\r
+ /* Already tested in numerous earlier testcases */\r
+ TEST_SET_FIXTURE(OSEK_TM_39, SEQ_NR_01 );\r
+\r
+\r
+ /** @treq OSEK_TM_40\r
+ *\r
+ * Call GetTaskState() with invalid task ID (task does not exist)\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_TM_40, SEQ_NR_01 );\r
+ rv = GetTaskState(TASK_ID_ILL,&taskState);\r
+ TEST_ASSERT( rv == E_OS_ID );\r
+ TEST_SET_FIXTURE(OSEK_TM_40, SEQ_NR_02 );\r
+\r
+\r
+ /** @treq OSEK_TM_41\r
+ *\r
+ * Call GetTaskState()\r
+ *\r
+ * Return state of queried task. Service returns E_OK\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_TM_41, SEQ_NR_01 );\r
+ rv = GetTaskState(TASK_ID_etask_h_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_SUSPENDED );\r
+ TEST_SET_FIXTURE(OSEK_TM_41, SEQ_NR_02 );\r
+\r
+ rv = GetTaskState(TASK_ID_etask_l_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_SUSPENDED );\r
+ TEST_SET_FIXTURE(OSEK_TM_41, SEQ_NR_03 );\r
+\r
+ rv = GetTaskState(taskId,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_RUNNING );\r
+ TEST_SET_FIXTURE(OSEK_TM_41, SEQ_NR_04 );\r
+\r
+// TestActivateAndWait( TASK_ID_btask_m_non );\r
+\r
+ TestExit(0);\r
+}\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue Sep 28 14:22:25 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = -1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_l_non,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_l_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 4,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue Sep 28 14:22:25 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+\r
+// Counter Id's\r
+\r
+// Counter macros\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_go 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_l_non 1\r
+#define TASK_ID_etask_m_full 2\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_l_non( void );\r
+void etask_m_full( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 0 \r
+#define OS_TASK_CNT 3\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 0\r
+#define OS_EVENTS_CNT 1\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU COMMON NEWLIB DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>config_osek_ip</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="d30db794-36ce-42ce-8658-deb9cfbfc18a">\r
+ <SHORT-NAME>config_osek_ip</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/osek_02_ip</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/NewEcu/SwComposition_NewEcu</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/NewEcu/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="aab85286-8442-4d60-bf6d-a8cdea2f4f7c">\r
+ <SHORT-NAME>SwComposition_NewEcu</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="fb96b9f7-d486-4956-bcf5-03ac6c6e5f78">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.11</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="e38c4f96-a8c1-4489-b907-03eb4441b231">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a7839b8f-1ed1-4f24-b05f-06850836ea32">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="074c4c94-0aa1-4158-9223-7136a526fac0">\r
+ <SHORT-NAME>etask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="c17d3508-e67f-49bd-92fb-8a3a51531b49">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ba3c0023-17f0-46d5-9894-05bf9d6b816d">\r
+ <SHORT-NAME>etask_m_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2779564f-96d6-4d30-b88b-cb1f7291fb76">\r
+ <SHORT-NAME>btask_l_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="86e6d692-1859-4a9e-a625-ab04d091fa8f">\r
+ <SHORT-NAME>btask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8d6c6b17-d4c3-4495-98b6-defe04215c41">\r
+ <SHORT-NAME>etask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b0512773-1a8c-4155-b4a7-67e915370404">\r
+ <SHORT-NAME>go</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5a412088-bb62-49c2-aeb7-12eee9b6fd66">\r
+ <SHORT-NAME>go2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += osek_ip.o\r
+obj-y += test_hooks.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+VPATH += ..\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * Created on: 4 aug 2010\r
+ * Author: mahi\r
+ */\r
+/*\r
+ * This file tests test requirements OSEK_IP_XX.\r
+ * We need only 2 tasks, 1 non-preemtive\r
+ *\r
+ *\r
+ * Priorities:\r
+ * ll - low low prio (used for scheduling only)\r
+ * l - low prio\r
+ * m - medium\r
+ * h - high prio\r
+ */\r
+\r
+\r
+#include "os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+#include "irq.h"\r
+\r
+\r
+\r
+enum OsekFixtureNr {\r
+ OSEK_IP_01 = 1,\r
+ OSEK_IP_02,\r
+ OSEK_IP_03,\r
+ OSEK_IP_04,\r
+ OSEK_IP_05,\r
+ OSEK_IP_06,\r
+ OSEK_IP_07,\r
+ OSEK_IP_08,\r
+ OSEK_IP_09,\r
+ OSEK_IP_10,\r
+ OSEK_IP_11,\r
+ OSEK_IP_12,\r
+};\r
+\r
+TestWorldType TestWorld = {0};\r
+\r
+uint32_t testNrNon = 0;\r
+\r
+static void isrSoftInt1( void ) {\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_IP_07:\r
+ TEST_SET_FIXTURE(OSEK_IP_07, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+}\r
+\r
+static void isrSoftInt0( void ) {\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_IP_07:\r
+ TEST_SET_FIXTURE(OSEK_IP_07, SEQ_NR_02 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_1 );\r
+ break;\r
+ case OSEK_IP_09:\r
+ TEST_SET_FIXTURE(OSEK_IP_09, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+\r
+\r
+void OsIdle(void) {\r
+ while(1);\r
+}\r
+\r
+\r
+void btask_l_non ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_IP_09:\r
+ TEST_SET_FIXTURE(OSEK_IP_09, SEQ_NR_02 );\r
+ /* Make higher prio task ready */\r
+ rv = SetEvent( TASK_ID_etask_m_full,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK ) ;\r
+ TEST_SET_FIXTURE(OSEK_IP_09, SEQ_NR_03 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_IP_09, SEQ_NR_05 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * The master in the tests
+ */\r
+void etask_m_full( void ) {\r
+\r
+ StatusType rv;\r
+ TaskType isrTask;\r
+\r
+ /** @treq OSEK_IP_01\r
+ *\r
+ * Call EnableInterrupt(). All requested interrupts are disabled\r
+ *\r
+ * Enable interrupts. Service returns E_OK\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_IP_01, SEQ_NR_01 );\r
+ /* The API is no longer available in Autosar or OSEK */\r
+\r
+ /** @treq OSEK_IP_02\r
+ *\r
+ * Call EnableInterrupt(). At least one of the requested interrupts is already enabled.\r
+ *\r
+ * Enable interrupts. Service returns E_OS_NOFUNC\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_IP_02, SEQ_NR_01 );\r
+ /* The API is no longer available in Autosar or OSEK */\r
+\r
+ /** @treq OSEK_IP_03\r
+ *\r
+ * Call DisableInterrupt(). All requested interrupts are enabled\r
+ *\r
+ * Disable interrupts. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_03, SEQ_NR_01 );\r
+ /* The API is no longer available in Autosar or OSEK */\r
+\r
+ /** @treq OSEK_IP_04\r
+ *\r
+ * "Call DisableInterrupt(). At least one of the requested interrupts\r
+ * is already disabled"\r
+ *\r
+ * Disable interrupts. Service returns E_OS_NOFUNC\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_04, SEQ_NR_01 );\r
+ /* The API is no longer available in Autosar or OSEK */\r
+\r
+ /** @treq OSEK_IP_05\r
+ *\r
+ * Call GetInterruptDescriptor()\r
+ *\r
+ * "Returns current interrupt descriptor. Service returns E_OK"\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_05, SEQ_NR_01 );\r
+ /* The API is no longer available in Autosar or OSEK */\r
+\r
+ /** @treq OSEK_IP_06\r
+ *\r
+ * Interruption of running task\r
+ *\r
+ * Interrupt is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_06, SEQ_NR_01 );\r
+ /* Already tested in a number of cases in tm suite */\r
+\r
+ /** @treq OSEK_IP_07\r
+ *\r
+ * Interruption of ISR2\r
+ *\r
+ * Interrupt is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_07, SEQ_NR_01 );\r
+ /* Create an ISR2 */\r
+ isrTask = Os_Arc_CreateIsr( isrSoftInt0, 8/*prio*/,"soft_0");\r
+ Irq_AttachIsr2(isrTask,NULL, IRQ_SOFTINT_0);\r
+\r
+ /* Create an ISR2 */\r
+ isrTask = Os_Arc_CreateIsr( isrSoftInt1, 9/*prio*/,"soft_1");\r
+ Irq_AttachIsr2(isrTask,NULL, IRQ_SOFTINT_1);\r
+\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_IP_07, SEQ_NR_04 );\r
+\r
+\r
+ /** @treq OSEK_IP_08\r
+ *\r
+ * Interruption of ISR3\r
+ *\r
+ * Interrupt is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_08, SEQ_NR_01 );\r
+ /* ISR3 is not applicable */\r
+\r
+ /** @treq OSEK_IP_09\r
+ *\r
+ * Return from ISR2. Interrupted task is non-preemptive\r
+ *\r
+ * Execution of interrupted task is continued\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_09, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_btask_l_non );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_IP_09, SEQ_NR_06 );\r
+\r
+ /** @treq OSEK_IP_10\r
+ *\r
+ * Return from ISR3. Interrupted task is non-preemptive\r
+ *\r
+ * Execution of interrupted task is continued\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_10, SEQ_NR_01 );\r
+ /* ISR3 is not applicable */\r
+\r
+ /** @treq OSEK_IP_11\r
+ *\r
+ * Return from ISR2. Interrupted task is preemptive\r
+ *\r
+ * Ready task with highest priority is executed (Rescheduling)\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_11, SEQ_NR_01 );\r
+\r
+\r
+\r
+ /** @treq OSEK_IP_12\r
+ *\r
+ * Return from ISR3. Interrupted task is preemptive\r
+ *\r
+ * Ready task with highest priority is executed (Rescheduling)\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_IP_12, SEQ_NR_01 );\r
+ /* ISR3 is not applicable */\r
+\r
+\r
+ TestExit(0);\r
+}\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Thu Sep 30 13:27:37 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(\r
+ RES_ID_std_1,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_h_full,2048);\r
+DECLARE_STACK(btask_l_full,2048);\r
+DECLARE_STACK(btask_ll_non,2048);\r
+DECLARE_STACK(btask_m_full,2048);\r
+DECLARE_STACK(etask_h_full,2048);\r
+DECLARE_STACK(etask_l_full,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+DECLARE_STACK(etask_m_non,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_ll_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_full,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 5,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ RES_MASK_std_1 | 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_non,\r
+ 5,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Thu Sep 30 13:27:37 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_go 1\r
+#define EVENT_MASK_go2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+#define RES_ID_std_1 0\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+#define RES_MASK_std_1 (1 << 0)\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_h_full 1\r
+#define TASK_ID_btask_l_full 2\r
+#define TASK_ID_btask_ll_non 3\r
+#define TASK_ID_btask_m_full 4\r
+#define TASK_ID_etask_h_full 5\r
+#define TASK_ID_etask_l_full 6\r
+#define TASK_ID_etask_m_full 7\r
+#define TASK_ID_etask_m_non 8\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_h_full( void );\r
+void btask_l_full( void );\r
+void btask_ll_non( void );\r
+void btask_m_full( void );\r
+void etask_h_full( void );\r
+void etask_l_full( void );\r
+void etask_m_full( void );\r
+void etask_m_non( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 0 \r
+#define OS_TASK_CNT 9\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 2\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 1\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU COMMON NEWLIB DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>config_osek_ev</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="5ae9c5b8-fba6-4913-a886-cdb86dc2b884">\r
+ <SHORT-NAME>config_osek_ev</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/osek_03_ev</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/config_osek_ev/SwComposition_config_osek_ev</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/config_osek_ev/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="4bf548b2-edc6-436d-a4df-98a43df64955">\r
+ <SHORT-NAME>SwComposition_config_osek_ev</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="e3a90a5a-3a2c-4b90-82fa-498d4bf14895">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="46e7afa2-40d4-4969-9216-dbb68fd7dc71">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="5c123a65-e644-421a-be3b-62886c189f46">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="179b1eed-bae4-4ff9-8101-c81794d849be">\r
+ <SHORT-NAME>etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7934bf2-d3cf-4df2-822a-c872121dcd2b">\r
+ <SHORT-NAME>etask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_ev/Os/std_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b1f99972-b3c7-41ec-a1ec-0d4dbe6b2e73">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2f0895f3-1d8a-4169-8fe1-105ff68a3a5a">\r
+ <SHORT-NAME>etask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f120ab09-188b-463b-a9e4-94f60e84f125">\r
+ <SHORT-NAME>btask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c3213aac-578d-4870-9e2a-7b0a731f9ae3">\r
+ <SHORT-NAME>btask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9de6649a-e85b-4a49-a9f4-5055e02480ca">\r
+ <SHORT-NAME>btask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="de75266a-d9ea-4225-803f-b8bc02a446bf">\r
+ <SHORT-NAME>go</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="83c2a703-f295-4d91-b3c7-46bc6913e80e">\r
+ <SHORT-NAME>Counter1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="92cc71da-7618-4431-90e4-f8451031d2e7">\r
+ <SHORT-NAME>etask_m_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="647b5042-793f-4f1c-bf5f-94e1bfd38bb0">\r
+ <SHORT-NAME>go2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5173867e-16a5-460a-acdf-1ddd6faeed00">\r
+ <SHORT-NAME>btask_ll_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2daf3826-ed29-470d-bbb7-73cf44e2bb24">\r
+ <SHORT-NAME>std_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsResource</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsResource/OsResourceProperty</DEFINITION-REF>\r
+ <VALUE>STANDARD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE UUID="95a91a77-4b4b-49b2-81af-71ed5700871a">\r
+ <SHORT-NAME>GeneratedSystemSignals</SHORT-NAME>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>Data</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt8</SHORT-NAME>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">256</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt16</SHORT-NAME>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">0</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">65535</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>UInt32</SHORT-NAME>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-2147483648</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">2147483647</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt8</SHORT-NAME>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-128</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">127</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ <INTEGER-TYPE>\r
+ <SHORT-NAME>SInt16</SHORT-NAME>\r
+ <LOWER-LIMIT INTERVAL-TYPE="CLOSED">-32768</LOWER-LIMIT>\r
+ <UPPER-LIMIT INTERVAL-TYPE="CLOSED">32767</UPPER-LIMIT>\r
+ </INTEGER-TYPE>\r
+ </ELEMENTS>\r
+ <SUB-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>IntegerLiterals</SHORT-NAME>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </SUB-PACKAGES>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += osek_ev.o\r
+obj-y += test_hooks.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+VPATH += ..\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * Created on: 4 aug 2010\r
+ * Author: mahi\r
+ */\r
+/*\r
+ * This file tests test requirements OSEK_EV_XX.\r
+ * We need only 2 tasks, 1 non-preemtive\r
+ *\r
+ *\r
+ * Priorities:\r
+ * ll - low low prio (used for scheduling only)\r
+ * l - low prio\r
+ * m - medium\r
+ * h - high prio\r
+ */\r
+\r
+\r
+#include "os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+#include "irq.h"\r
+\r
+\r
+\r
+enum OsekFixtureNr {\r
+ OSEK_EV_01 = 1,\r
+ OSEK_EV_02,\r
+ OSEK_EV_03,\r
+ OSEK_EV_04,\r
+ OSEK_EV_05,\r
+ OSEK_EV_06,\r
+ OSEK_EV_07,\r
+ OSEK_EV_08,\r
+ OSEK_EV_09,\r
+ OSEK_EV_10,\r
+ OSEK_EV_11,\r
+ OSEK_EV_12,\r
+ OSEK_EV_13,\r
+ OSEK_EV_14,\r
+ OSEK_EV_15,\r
+ OSEK_EV_16,\r
+ OSEK_EV_17,\r
+ OSEK_EV_18,\r
+ OSEK_EV_19,\r
+ OSEK_EV_20,\r
+ OSEK_EV_21,\r
+ OSEK_EV_22,\r
+ OSEK_EV_23,\r
+ OSEK_EV_24,\r
+ OSEK_EV_25,\r
+ OSEK_EV_26,\r
+};\r
+\r
+TestWorldType TestWorld = {0};\r
+\r
+uint32_t testNrNon = 0;\r
+\r
+static uint8_t activations = 0;\r
+\r
+static void isrSoftInt1( void ) {\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_07:\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+}\r
+\r
+static void isrSoftInt0( void ) {\r
+ StatusType rv;\r
+ TaskType taskId;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_12:\r
+ TEST_SET_FIXTURE(OSEK_EV_12, SEQ_NR_02 );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OS_CALLEVEL );\r
+ break;\r
+ case OSEK_EV_23:\r
+ TEST_SET_FIXTURE(OSEK_EV_23, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OS_CALLEVEL );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+void TestTaskRunLowerPrio( void ) {\r
+ StatusType rv;\r
+ /* Activate lowest prioriy task */\r
+ rv = ActivateTask(TASK_ID_btask_ll_non);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Let the low prio task run */\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void TestActivateAndWait( TaskType task ) {\r
+ StatusType rv;\r
+ rv = ActivateTask(task);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Let the low prio task run */\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+\r
+void btask_h_full( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_11:\r
+ TEST_SET_FIXTURE(OSEK_EV_11, SEQ_NR_02 );\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OS_ACCESS );\r
+ break;\r
+ case OSEK_EV_21:\r
+ TEST_SET_FIXTURE(OSEK_EV_21, SEQ_NR_02 );\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OS_ACCESS );\r
+ TEST_SET_FIXTURE(OSEK_EV_21, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void etask_h_full( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_08:\r
+ TEST_SET_FIXTURE(OSEK_EV_08, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go | EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_08, SEQ_NR_05 );\r
+ break;\r
+ case OSEK_EV_09:\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_04 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void btask_m_full( void ) {\r
+\r
+}\r
+\r
+void btask_ll_non( void ) {\r
+ StatusType rv;\r
+ /* Used for scheduling ONLY */\r
+ rv = SetEvent(TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+\r
+void OsIdle(void) {\r
+ while(1);\r
+}\r
+\r
+\r
+void btask_l_non ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+void etask_m_non ( void ) {\r
+ StatusType rv;\r
+ TaskStateType taskState;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_04:\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_03 );\r
+ /* Verify that task is in waiting */\r
+ rv = GetTaskState(TASK_ID_etask_m_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_WAITING);\r
+ /* Set the Event */\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Verify state, again */\r
+ rv = GetTaskState(TASK_ID_etask_m_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_READY);\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_04 );\r
+ break;\r
+ case OSEK_EV_05:\r
+ TEST_SET_FIXTURE(OSEK_EV_05, SEQ_NR_03 );\r
+ /* Set event in etask_m_full that it is NOT waiting for */\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_05, SEQ_NR_04 );\r
+ /* Cleanup, and let it run */\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_05, SEQ_NR_05 );\r
+ break;\r
+ case OSEK_EV_09:\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_02 );\r
+ /* make higher prio task ready */\r
+ rv = ActivateTask( TASK_ID_etask_h_full );\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Do the actual SetEvent() test */\r
+ rv = SetEvent( TASK_ID_etask_h_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void btask_l_full ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_09:\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+}\r
+\r
+void etask_l_full ( void ) {\r
+ StatusType rv;\r
+ EventMaskType mask;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_06:\r
+ TEST_SET_FIXTURE(OSEK_EV_06, SEQ_NR_03 );\r
+ /* Set event preempt us */\r
+ rv = SetEvent(TASK_ID_etask_m_full,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_06, SEQ_NR_05 );\r
+ break;\r
+ case OSEK_EV_07:\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_03 );\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_06 );\r
+ break;\r
+ case OSEK_EV_10:\r
+ TEST_SET_FIXTURE(OSEK_EV_10, SEQ_NR_03 );\r
+ break;\r
+ case OSEK_EV_19:\r
+ TEST_SET_FIXTURE(OSEK_EV_19, SEQ_NR_03 );\r
+ rv = ClearEvent( EVENT_MASK_go2 );\r
+ break;\r
+ case OSEK_EV_20:\r
+ TEST_SET_FIXTURE(OSEK_EV_20, SEQ_NR_02 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_20, SEQ_NR_03 );\r
+ rv = GetEvent( TASK_ID_etask_m_full, &mask );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( mask == EVENT_MASK_go2 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ default:\r
+ break;\r
+ }\r
+ TerminateTask();\r
+}\r
+\r
+\r
+/**\r
+ * The master in the tests
+ */\r
+void etask_m_full( void ) {\r
+\r
+ StatusType rv;\r
+ TaskType taskId;\r
+ TaskType isrTask;\r
+ TaskStateType taskState;\r
+ EventMaskType mask;\r
+\r
+ /** @treq OSEK_EV_01\r
+ *\r
+ * Call SetEvent() with invalid Task ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_EV_01, SEQ_NR_01 );\r
+ rv = SetEvent(TASK_ID_ILL,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OS_ID );\r
+\r
+ /** @treq OSEK_EV_02\r
+ *\r
+ * Call SetEvent() for basic task\r
+ *\r
+ * Service returns E_OS_ACCESS\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_EV_02, SEQ_NR_01 );\r
+ rv = SetEvent( TASK_ID_btask_l_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OS_ACCESS );\r
+\r
+\r
+ // --------------------------------------------------------------------\r
+\r
+ /** @treq OSEK_EV_03\r
+ *\r
+ * Call SetEvent() for suspended extended task\r
+ *\r
+ * Service returns E_OS_STATE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_03, SEQ_NR_01 );\r
+ rv = SetEvent( TASK_ID_etask_l_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OS_STATE );\r
+\r
+ /** @treq OSEK_EV_04\r
+ *\r
+ * Call SetEvent() from non-preemptive task on waiting extended\r
+ * task which is waiting for at least one of the requested events\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Waiting task becomes ready Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_m_non );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_05 );\r
+\r
+ /** @treq OSEK_EV_05\r
+ *\r
+ * Call SetEvent() from non-preemptive task on waiting extended\r
+ * task which is not waiting for any of the requested events\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Waiting task doesn\92t become ready. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_05, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_m_non );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_05, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go | EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_05, SEQ_NR_06 );\r
+\r
+ /** @treq OSEK_EV_06\r
+ *\r
+ * Call SetEvent() from preemptive task on waiting extended task which\r
+ * is waiting for at least one of the requested events and has higher\r
+ * priority than running task\r
+ *\r
+ * Requested events are set. Running task becomes ready (is preempted)\r
+ * Waiting task becomes running. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_06, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_l_full );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_06, SEQ_NR_02 );\r
+ /* Let etask__l_full */\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_06, SEQ_NR_04 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_EV_06, SEQ_NR_06 );\r
+\r
+\r
+ /** @treq OSEK_EV_07\r
+ *\r
+ * Call SetEvent() from preemptive task on waiting extended\r
+ * task which is waiting for at least one of the requested\r
+ * events and has equal or lower priority than running task\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Waiting task becomes ready. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_l_full );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_02 );\r
+ /* Let the lowerprio task hit WaitEvent() */\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_04 );\r
+ /* Set the Event, no preempt */\r
+ rv = SetEvent( TASK_ID_etask_l_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_05 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_07 );\r
+\r
+ /** @treq OSEK_EV_08\r
+ *\r
+ * Call SetEvent() from preemptive task on waiting extended\r
+ * task which is not waiting for any of the requested events\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Waiting task doesn\92t become ready. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_08, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_h_full );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_08, SEQ_NR_03 );\r
+ rv = SetEvent( TASK_ID_etask_h_full, EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_08, SEQ_NR_04 );\r
+ /* Cleanup, Let it run */\r
+ rv = SetEvent( TASK_ID_etask_h_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_08, SEQ_NR_06 );\r
+\r
+ /** @treq OSEK_EV_09\r
+ *\r
+ * Call SetEvent() from non-preemptive task on ready extended\r
+ * task.\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Service returns E_OK
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_etask_m_non);\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_05 );\r
+\r
+\r
+ /** @treq OSEK_EV_10\r
+ *\r
+ * Call SetEvent() from preemptive task on ready extended task\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_10, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_l_full );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = SetEvent( TASK_ID_etask_l_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_10, SEQ_NR_02 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_EV_10, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_EV_11\r
+ *\r
+ * Call ClearEvent() from basic task\r
+ *\r
+ * Service returns E_OS_ACCESS\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_11, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_btask_h_full );\r
+ TEST_SET_FIXTURE(OSEK_EV_11, SEQ_NR_03 );\r
+\r
+\r
+ /** @treq OSEK_EV_12\r
+ *\r
+ * Call ClearEvent() from ISR2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ /* Create an ISR2 */\r
+ TEST_SET_FIXTURE(OSEK_EV_12, SEQ_NR_01 );\r
+ isrTask = Os_Arc_CreateIsr( isrSoftInt0, 8/*prio*/,"soft_0");\r
+ Irq_AttachIsr2(isrTask,NULL, IRQ_SOFTINT_0);\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_EV_12, SEQ_NR_03 );\r
+\r
+\r
+ /** @treq OSEK_EV_13\r
+ *\r
+ * Call ClearEvent() from ISR3\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ *\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_13, SEQ_NR_01 );\r
+ /* Not applicatable */\r
+\r
+ /** @treq OSEK_EV_14\r
+ *\r
+ * Call ClearEvent() from extended task\r
+ *\r
+ * Requested events are cleared. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_14, SEQ_NR_01 );\r
+ /* This is already covered in this testsystem */\r
+\r
+ /** @treq OSEK_EV_15\r
+ *\r
+ * Call GetEvent() with invalid Task ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_15, SEQ_NR_01 );\r
+ rv = GetEvent(TASK_ID_ILL, &mask);\r
+ TEST_ASSERT( rv == E_OS_ID );\r
+\r
+ /** @treq OSEK_EV_16\r
+ *\r
+ * Call GetEvent() for basic task\r
+ *\r
+ * Service returns E_OS_ACCESS\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_16, SEQ_NR_01 );\r
+ rv = GetEvent(TASK_ID_btask_h_full, &mask);\r
+ TEST_ASSERT( rv == E_OS_ACCESS);\r
+\r
+ /** @treq OSEK_EV_17\r
+ *\r
+ * Call GetEvent() for suspended extended task\r
+ *\r
+ * Service returns E_OS_STATE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_17, SEQ_NR_01 );\r
+ rv = GetEvent(TASK_ID_etask_h_full, &mask);\r
+ TEST_ASSERT( rv == E_OS_STATE);\r
+\r
+ /** @treq OSEK_EV_18\r
+ *\r
+ * Call GetEvent() for running extended task\r
+ *\r
+ * Return current state of all event bits. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_18, SEQ_NR_01 );\r
+ rv = GetTaskID(&taskId);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = GetEvent(taskId, &mask);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_ASSERT( mask == 0 );\r
+\r
+ /** @treq OSEK_EV_19\r
+ *\r
+ * Call GetEvent() for ready extended task\r
+ *\r
+ * Return current state of all event bits. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_19, SEQ_NR_01 );\r
+ /* Make it ready */\r
+ rv = ActivateTask(TASK_ID_etask_l_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ /* Set an event */\r
+ rv = SetEvent( TASK_ID_etask_l_full, EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ rv = GetEvent( TASK_ID_etask_l_full, &mask );\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_ASSERT( mask == EVENT_MASK_go2 );\r
+\r
+ TEST_SET_FIXTURE(OSEK_EV_19, SEQ_NR_02 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_EV_19, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_EV_20\r
+ *\r
+ * Call GetEvent() for waiting extended task\r
+ *\r
+ * Return current state of all event bits. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_20, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_etask_l_full);\r
+ TEST_SET_FIXTURE(OSEK_EV_20, SEQ_NR_04 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_EV_20, SEQ_NR_05 );\r
+\r
+\r
+ /** @treq OSEK_EV_21\r
+ *\r
+ * Call WaitEvent() from basic task\r
+ *\r
+ * Service returns E_OS_ACCESS\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_21, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_btask_h_full );\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_EV_21, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_EV_22\r
+ *\r
+ * Call WaitEvent() from extended task which occupies a resource\r
+ *\r
+ * Service returns E_OS_RESOURCE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_22, SEQ_NR_01 );\r
+ rv = GetResource(RES_ID_std_1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OS_RESOURCE);\r
+ rv = ReleaseResource(RES_ID_std_1);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ /** @treq OSEK_EV_23\r
+ *\r
+ * Call WaitEvent() from ISR2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_23, SEQ_NR_01 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_EV_23, SEQ_NR_03 );\r
+\r
+\r
+ /** @treq OSEK_EV_24\r
+ * Call WaitEvent() from ISR3\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_24, SEQ_NR_01 );\r
+ /* Not applicable */\r
+\r
+ /** @treq OSEK_EV_25\r
+ *\r
+ * Call WaitEvent() from extended task. None of the events waited for is set\r
+ *\r
+ * Running task becomes waiting and ready task with highest priority is executed Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_25, SEQ_NR_01 );\r
+ /* Already by using TestActivateAndWait() */\r
+\r
+ /** @treq OSEK_EV_26\r
+ *\r
+ * Call WaitEvent() from extended task. At least one event waited for is already set\r
+ *\r
+ * No preemption of running task Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_26, SEQ_NR_01 );\r
+ rv = SetEvent( taskId, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_EV_26, SEQ_NR_02 );\r
+\r
+ TestExit(0);\r
+}\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Mon Oct 04 08:11:07 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(\r
+ RES_ID_int_1,\r
+ RESOURCE_TYPE_INTERNAL,\r
+ 0\r
+ ),\r
+ GEN_RESOURCE(\r
+ RES_ID_int_2,\r
+ RESOURCE_TYPE_INTERNAL,\r
+ 0\r
+ ),\r
+ GEN_RESOURCE(\r
+ RES_ID_std_1,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+ GEN_RESOURCE(\r
+ RES_ID_std_h,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_h_full,2048);\r
+DECLARE_STACK(btask_l_full,2048);\r
+DECLARE_STACK(btask_l_non,2048);\r
+DECLARE_STACK(btask_ll_non,2048);\r
+DECLARE_STACK(btask_m_full,2048);\r
+DECLARE_STACK(btask_m_non,2048);\r
+DECLARE_STACK(etask_h_full,2048);\r
+DECLARE_STACK(etask_l_full,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_h | 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_non,\r
+ 4,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_h | 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_ll_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_full,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_h | 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_non,\r
+ 5,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_h | 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 5,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ RES_MASK_std_1 | 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Mon Oct 04 08:11:07 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_go 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+#define RES_ID_int_1 0\r
+#define RES_ID_int_2 1\r
+#define RES_ID_std_1 2\r
+#define RES_ID_std_h 3\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+#define RES_MASK_int_1 (1 << 0)\r
+#define RES_MASK_int_2 (1 << 1)\r
+#define RES_MASK_std_1 (1 << 2)\r
+#define RES_MASK_std_h (1 << 3)\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_h_full 1\r
+#define TASK_ID_btask_l_full 2\r
+#define TASK_ID_btask_l_non 3\r
+#define TASK_ID_btask_ll_non 4\r
+#define TASK_ID_btask_m_full 5\r
+#define TASK_ID_btask_m_non 6\r
+#define TASK_ID_etask_h_full 7\r
+#define TASK_ID_etask_l_full 8\r
+#define TASK_ID_etask_m_full 9\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_h_full( void );\r
+void btask_l_full( void );\r
+void btask_l_non( void );\r
+void btask_ll_non( void );\r
+void btask_m_full( void );\r
+void btask_m_non( void );\r
+void etask_h_full( void );\r
+void etask_l_full( void );\r
+void etask_m_full( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 0 \r
+#define OS_TASK_CNT 10\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 1\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 4\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_OFF\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU COMMON NEWLIB DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>config_osek_rm</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="1cc76430-48de-4bcf-ba4b-b31323e01607">\r
+ <SHORT-NAME>config_osek_rm</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/osek_04_rm</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/config_osek_rm/SwComposition_config_osek_rm</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/config_osek_rm/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="68ecea8c-16c5-4723-bfcc-fc11f4f72291">\r
+ <SHORT-NAME>SwComposition_config_osek_rm</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="e3a90a5a-3a2c-4b90-82fa-498d4bf14895">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="46e7afa2-40d4-4969-9216-dbb68fd7dc71">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="5c123a65-e644-421a-be3b-62886c189f46">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="179b1eed-bae4-4ff9-8101-c81794d849be">\r
+ <SHORT-NAME>etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c7934bf2-d3cf-4df2-822a-c872121dcd2b">\r
+ <SHORT-NAME>etask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_rm/Os/std_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b1f99972-b3c7-41ec-a1ec-0d4dbe6b2e73">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2f0895f3-1d8a-4169-8fe1-105ff68a3a5a">\r
+ <SHORT-NAME>etask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_rm/Os/std_h</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f120ab09-188b-463b-a9e4-94f60e84f125">\r
+ <SHORT-NAME>btask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_rm/Os/std_h</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c3213aac-578d-4870-9e2a-7b0a731f9ae3">\r
+ <SHORT-NAME>btask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_rm/Os/std_h</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9de6649a-e85b-4a49-a9f4-5055e02480ca">\r
+ <SHORT-NAME>btask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="47b32026-3fe6-4fd5-b26e-fb0faa6bdac3">\r
+ <SHORT-NAME>btask_ll_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="de75266a-d9ea-4225-803f-b8bc02a446bf">\r
+ <SHORT-NAME>go</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="83c2a703-f295-4d91-b3c7-46bc6913e80e">\r
+ <SHORT-NAME>Counter1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="92cc71da-7618-4431-90e4-f8451031d2e7">\r
+ <SHORT-NAME>btask_m_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="84a2cc88-79f3-45cd-bc3b-afcd525ba482">\r
+ <SHORT-NAME>std_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsResource</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsResource/OsResourceProperty</DEFINITION-REF>\r
+ <VALUE>STANDARD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6cec9cf6-c09c-4f41-b460-8d2229152b1a">\r
+ <SHORT-NAME>std_h</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsResource</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsResource/OsResourceProperty</DEFINITION-REF>\r
+ <VALUE>STANDARD</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a7582418-2f8e-4267-ad5a-cfb69d908787">\r
+ <SHORT-NAME>btask_l_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_rm/Os/std_h</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="b54a2fdc-aa48-4397-a4af-9128f3721470">\r
+ <SHORT-NAME>int_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsResource</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsResource/OsResourceProperty</DEFINITION-REF>\r
+ <VALUE>INTERNAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c2429cd6-2b8d-4351-bacc-6b2003b6f05b">\r
+ <SHORT-NAME>int_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsResource</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsResource/OsResourceProperty</DEFINITION-REF>\r
+ <VALUE>INTERNAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_osek_rm.o\r
+obj-y += test_hooks.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+VPATH += ..\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * Created on: 4 aug 2010\r
+ * Author: mahi\r
+ */\r
+/*\r
+ * This file tests test requirements OSEK_RM_XX.\r
+ * We need only 2 tasks, 1 non-preemtive\r
+ *\r
+ *\r
+ * Priorities:\r
+ * ll - low low prio (used for scheduling only)\r
+ * l - low prio\r
+ * m - medium\r
+ * h - high prio\r
+ */\r
+\r
+\r
+#include "os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+#include "irq.h"\r
+\r
+\r
+\r
+enum OsekFixtureNr {\r
+ OSEK_RM_01 = 1,\r
+ OSEK_RM_02,\r
+ OSEK_RM_03,\r
+ OSEK_RM_04,\r
+ OSEK_RM_05,\r
+ OSEK_RM_06,\r
+ OSEK_RM_07,\r
+ OSEK_RM_08,\r
+ OSEK_RM_09,\r
+ OSEK_RM_10,\r
+ OSEK_RM_11,\r
+ OSEK_RM_12,\r
+ OSEK_RM_13,\r
+ OSEK_RM_14,\r
+ OSEK_RM_15,\r
+ OSEK_RM_16,\r
+};\r
+\r
+TestWorldType TestWorld = {0};\r
+\r
+uint32_t testNrNon = 0;\r
+\r
+\r
+void TestTaskRunLowerPrio( void ) {\r
+ StatusType rv;\r
+ /* Activate lowest prioriy task */\r
+ rv = ActivateTask(TASK_ID_btask_ll_non);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Let the low prio task run */\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void TestActivateAndWait( TaskType task ) {\r
+ StatusType rv;\r
+ rv = ActivateTask(task);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Let the low prio task run */\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+#if 0\r
+static void isrSoftInt1( void ) {\r
+ switch ( TestWorld.fixtureNr ) {\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+}\r
+\r
+static void isrSoftInt0( void ) {\r
+ StatusType rv;\r
+ TaskType taskId;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+#endif\r
+\r
+void OsIdle(void) {\r
+ while(1);\r
+}\r
+\r
+\r
+void btask_l_non ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_RM_06:\r
+ TEST_SET_FIXTURE(OSEK_RM_06, SEQ_NR_02 );\r
+ rv = GetResource(RES_ID_std_h);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = ActivateTask( TASK_ID_btask_m_non );\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = Schedule();\r
+ TEST_ASSERT( rv == E_OS_RESOURCE);\r
+ TEST_SET_FIXTURE(OSEK_RM_06, SEQ_NR_03 );\r
+ rv = ReleaseResource(RES_ID_std_h);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_RM_06, SEQ_NR_04 );\r
+ break;\r
+ case OSEK_RM_15:\r
+ TEST_SET_FIXTURE(OSEK_RM_15, SEQ_NR_02 );\r
+ rv = GetResource(RES_SCHEDULER);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = ActivateTask( TASK_ID_btask_m_non );\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = Schedule();\r
+ TEST_ASSERT( rv == E_OS_RESOURCE);\r
+ TEST_SET_FIXTURE(OSEK_RM_15, SEQ_NR_03 );\r
+ rv = ReleaseResource(RES_SCHEDULER);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_RM_15, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void btask_m_non ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_RM_06:\r
+ TEST_SET_FIXTURE(OSEK_RM_06, SEQ_NR_05 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK);\r
+ break;\r
+ case OSEK_RM_07:\r
+ TEST_SET_FIXTURE(OSEK_RM_07, SEQ_NR_04 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK);\r
+ break;\r
+ case OSEK_RM_15:\r
+ TEST_SET_FIXTURE(OSEK_RM_15, SEQ_NR_05 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK);\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+\r
+void btask_h_full ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_RM_08:\r
+ TEST_SET_FIXTURE(OSEK_RM_08, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+}\r
+\r
+void btask_l_full ( void ) {\r
+\r
+}\r
+\r
+void btask_ll_non( void ) {\r
+ StatusType rv;\r
+ /* Used for scheduling ONLY */\r
+ rv = SetEvent(TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void btask_m_full ( void ) {\r
+\r
+}\r
+\r
+void etask_h_full( void ) {\r
+\r
+}\r
+\r
+void etask_l_full( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_RM_07:\r
+ TEST_SET_FIXTURE(OSEK_RM_07, SEQ_NR_02 );\r
+ rv = GetResource(RES_ID_std_h);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = ActivateTask( TASK_ID_btask_m_non );\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_RM_07, SEQ_NR_03 );\r
+ /* reshedule to btask_m_non */\r
+ rv = ReleaseResource(RES_ID_std_h);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_RM_07, SEQ_NR_06 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+\r
+/**\r
+ * The master in the tests
+ */\r
+void etask_m_full( void ) {\r
+\r
+ StatusType rv;\r
+\r
+ /** @treq OSEK_RM_01\r
+ *\r
+ * Call GetResource() from task which has no access to this resource\r
+ *\r
+ * Service returns E_OS_ACCESS\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_01, SEQ_NR_01 );\r
+ rv = GetResource( RES_ID_std_h);\r
+ TEST_ASSERT( rv = E_OS_ACCESS )\r
+\r
+ /** @treq OSEK_RM_02\r
+ *\r
+ * Call GetResource() from task with invalid resource ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_02, SEQ_NR_01 );\r
+ rv = GetResource( RES_ID_ILL);\r
+ TEST_ASSERT( rv = E_OS_ID );\r
+\r
+ /** @treq OSEK_RM_03\r
+ *\r
+ * Call GetResource() from ISR2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_03, SEQ_NR_01 );\r
+ /* This test is not applicable since it is allowed in OSEK\r
+ * to do GetResource() from ISR2
+ */\r
+\r
+ /** @treq OSEK_RM_04\r
+ *\r
+ * Call GetResource() from ISR3\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_04, SEQ_NR_01 );\r
+ /* Not applicable */\r
+\r
+ /** @treq OSEK_RM_05\r
+ *\r
+ * Call GetResource() from task with too many resources occupied in parallel\r
+ *\r
+ * Service returns E_OS_LIMIT\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_05, SEQ_NR_01 );\r
+ /* Not applicable */\r
+\r
+ /** @treq OSEK_RM_06\r
+ *\r
+ * Test Priority Ceiling Protocol:\r
+ * Call GetResource() from non-preemptive task, activate task with priority\r
+ * higher than running task but lower than ceiling priority, and force\r
+ * rescheduling\r
+ *\r
+ * Resource is occupied and running task\92s priority is set to resource\92s\r
+ * ceiling priority. Service returns E_OK. No preemption occurs after\r
+ * activating the task with higher priority and rescheduling\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_06, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_l_non);\r
+ TEST_SET_FIXTURE(OSEK_RM_06, SEQ_NR_06 );\r
+\r
+ /** @treq OSEK_RM_07\r
+ *\r
+ * Test Priority Ceiling Protocol:\r
+ * Call GetResource()from preemptive task, and activate task with priority\r
+ * higher than running task but lower than ceiling priority\r
+ *\r
+ * Resource is occupied and running task\92s priority is set to resource\92s\r
+ * ceiling priority. Service returns E_OK. No preemption occurs after\r
+ * activating the task with higher priority\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_07, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_etask_l_full);\r
+ TEST_SET_FIXTURE(OSEK_RM_07, SEQ_NR_05 );\r
+ TestTaskRunLowerPrio();\r
+ TEST_SET_FIXTURE(OSEK_RM_07, SEQ_NR_07 );\r
+\r
+ /** @treq OSEK_RM_08\r
+ *\r
+ * Call GetResource() for resource RES_SCHEDULER\r
+ *\r
+ * Resource is occupied and running task\92s priority is set to resource\92s\r
+ * ceiling priority. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_08, SEQ_NR_01 );\r
+ rv = GetResource( RES_SCHEDULER );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ActivateTask( TASK_ID_btask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_RM_08, SEQ_NR_02 );\r
+ rv = ReleaseResource( RES_SCHEDULER);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_RM_08, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_RM_09\r
+ *\r
+ * Call ReleaseResource() from task with invalid resource ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_09, SEQ_NR_01 );\r
+ rv = ReleaseResource( RES_ID_ILL);\r
+ TEST_ASSERT( rv == E_OS_ID);\r
+\r
+ /** @treq OSEK_RM_10\r
+ *\r
+ * Call ReleaseResource() from ISR2\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_10, SEQ_NR_01 );\r
+ /* This test is not applicable since it is allowed in OSEK\r
+ * to do GetResource() from ISR2\r
+ */\r
+\r
+ /** @treq OSEK_RM_11\r
+ *\r
+ * Call ReleaseResource() from ISR3\r
+ *\r
+ * Service returns E_OS_CALLEVEL\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_RM_11, SEQ_NR_01 );\r
+ /* Not applicable */\r
+\r
+ /** @treq OSEK_RM_12\r
+ *\r
+ * Call ReleaseResource() from task with resource which is not occupied\r
+ *\r
+ * Service returns E_OS_NOFUNC\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_12, SEQ_NR_01 );\r
+ rv = ReleaseResource( RES_ID_std_1 );\r
+ TEST_ASSERT( rv == E_OS_NOFUNC );\r
+\r
+ /** @treq OSEK_RM_13\r
+ *\r
+ * Call ReleaseResource() from non-preemptive task\r
+ *\r
+ * Resource is released and running task\92s priority is reset.\r
+ * No preemption of running task. Service returns E_OK\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_RM_13, SEQ_NR_01 );\r
+ /* Already covered in OSEK_RM_06 */\r
+\r
+ /** @treq OSEK_RM_14\r
+ *\r
+ * Call ReleaseResource() from preemptive task\r
+ *\r
+ * Resource is released and running task\92s priority is reset.\r
+ * Ready task with highest priority is executed(Rescheduling).\r
+ * Service returns E_OK"\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_14, SEQ_NR_01 );\r
+ /* Already covered in OSEK_RM_07 */\r
+\r
+ /** @treq OSEK_RM_15\r
+ *\r
+ * Call ReleaseResource()from non-preemptive task for resource\r
+ * RES_SCHEDULER\r
+ *\r
+ * Resource is released and running task\92s priority is reset.\r
+ * No preemption of running task. Service returns E_OK\r
+ *\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_15, SEQ_NR_01 );\r
+ TestActivateAndWait(TASK_ID_btask_l_non);\r
+ TEST_SET_FIXTURE(OSEK_RM_15, SEQ_NR_06 );\r
+\r
+ /** @treq OSEK_RM_16\r
+ *\r
+ * Call ReleaseResource()from preemptive task for resource\r
+ * RES_SCHEDULER\r
+ *\r
+ * Resource is released and running task\92s priority is reset.\r
+ * Ready task with highest priority is executed (Rescheduling).\r
+ * Service returns E_OK"\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_RM_16, SEQ_NR_01 );\r
+ /* Already covered in OSEK_RM_08 */\r
+\r
+ TestExit(0);\r
+}\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Oct 10 18:57:50 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_soft1,\r
+ "soft1",\r
+ COUNTER_TYPE_SOFT,\r
+ COUNTER_UNIT_NANO,\r
+ 65535,\r
+ 1,\r
+ 2,\r
+ 0),\r
+ GEN_COUNTER( COUNTER_ID_system_tick,\r
+ "system_tick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_system_tick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_act_etask_h_full,\r
+ "act_etask_h_full",\r
+ COUNTER_ID_soft1,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_etask_h_full,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_act_etask_l_non,\r
+ "act_etask_l_non",\r
+ COUNTER_ID_soft1,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_etask_l_non,\r
+ NULL,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_setev_go_etask_h_full,\r
+ "setev_go_etask_h",\r
+ COUNTER_ID_soft1,\r
+ NULL,\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_h_full,\r
+ EVENT_MASK_go,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_sys_tick_act_etask_h_full,\r
+ "sys_tick_act_eta",\r
+ COUNTER_ID_system_tick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_etask_h_full,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(etask_h_full,2048);\r
+DECLARE_STACK(etask_l_non,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_ETASK(\r
+ etask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_non,\r
+ 4,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 5,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Oct 10 18:57:50 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_act_etask_h_full 0\r
+#define ALARM_ID_act_etask_l_non 1\r
+#define ALARM_ID_setev_go_etask_h_full 2\r
+#define ALARM_ID_sys_tick_act_etask_h_full 3\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_soft1 0\r
+#define COUNTER_ID_system_tick 1\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_soft1 65535\r
+#define OSMAXALLOWEDVALUE_system_tick 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_go 1\r
+#define EVENT_MASK_go2 2\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_etask_h_full 1\r
+#define TASK_ID_etask_l_non 2\r
+#define TASK_ID_etask_m_full 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void etask_h_full( void );\r
+void etask_l_non( void );\r
+void etask_m_full( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 4 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 2\r
+#define OS_EVENTS_CNT 2\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU COMMON NEWLIB DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>config_osek_al</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="5e838401-6c7f-4cc4-a310-85bfa3093061">\r
+ <SHORT-NAME>config_osek_al</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/osek_05_al</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/config_osek_al/SwComposition_config_osek_al</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/config_osek_al/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="4620a8eb-0826-482d-a426-0fddd23516bb">\r
+ <SHORT-NAME>SwComposition_config_osek_al</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="2ddd0584-ca02-4843-8a4b-6ce49338b3b5">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.11</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="dae4ccf8-5356-4f92-99f9-8a7bd8036544">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="80901634-8bf3-4ce8-8561-420ea79862b9">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a382117b-e08f-421f-9c92-761545351b56">\r
+ <SHORT-NAME>act_etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/soft1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b3336daf-4158-43cb-95ca-a0ef89eb4d09">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/etask_h_full</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c85af5eb-5f12-471d-b16c-7915cd495426">\r
+ <SHORT-NAME>soft1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>SOFTWARE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="36def18a-71ba-4f50-a4c5-02bc69c6e1a5">\r
+ <SHORT-NAME>etask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="17733da9-ba24-49e1-971e-da4353b48aa0">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="218dc9e2-9a93-41c5-8b84-062c1cd6c703">\r
+ <SHORT-NAME>etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="43ce4e8d-ca73-44de-bad4-3e8253be43e8">\r
+ <SHORT-NAME>setev_go_etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/soft1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="4aeb20ed-5c69-4158-9117-b4de360aa22b">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/go</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/etask_h_full</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d5f6e102-70af-4857-96fb-46808d1e6050">\r
+ <SHORT-NAME>go</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="176f4b96-0f87-4b4e-87fd-ca8fd2af0d9e">\r
+ <SHORT-NAME>system_tick</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="ca1a3f14-2a6b-4982-9433-2caa410de571">\r
+ <SHORT-NAME>sys_tick_act_etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/system_tick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a915bd71-4685-46c4-94c0-07d9962d8fd4">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/etask_h_full</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a93c6291-acbd-439f-b4f8-391fc898bcc5">\r
+ <SHORT-NAME>etask_l_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e3bfa880-abbd-4a51-9fea-48d5e335182b">\r
+ <SHORT-NAME>act_etask_l_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/soft1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="54afe69a-571f-47c1-95ba-f1fa96b2ca8c">\r
+ <SHORT-NAME>OsAlarmActivateTask</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmActivateTask/OsAlarmActivateTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_osek_al/Os/etask_l_non</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="758b10b6-58a5-42bc-af51-76dd42f82990">\r
+ <SHORT-NAME>go2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_osek_al.o\r
+obj-y += test_hooks.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+VPATH += ..\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * Created on: 4 aug 2010\r
+ * Author: mahi\r
+ */\r
+/*\r
+ * This file tests test requirements OSEK_AL_XX.\r
+ * We need only 2 tasks, 1 non-preemtive\r
+ *\r
+ *\r
+ * Priorities:\r
+ * ll - low low prio (used for scheduling only)\r
+ * l - low prio\r
+ * m - medium\r
+ * h - high prio\r
+ */\r
+\r
+\r
+#include "os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+#include "irq.h"\r
+\r
+\r
+\r
+enum OsekFixtureNr {\r
+ OSEK_AL_01 = 1,\r
+ OSEK_AL_02,\r
+ OSEK_AL_03,\r
+ OSEK_AL_04,\r
+ OSEK_AL_05,\r
+ OSEK_AL_06,\r
+ OSEK_AL_07,\r
+ OSEK_AL_08,\r
+ OSEK_AL_09,\r
+ OSEK_AL_10,\r
+ OSEK_AL_11,\r
+ OSEK_AL_12,\r
+ OSEK_AL_13,\r
+ OSEK_AL_14,\r
+ OSEK_AL_15,\r
+ OSEK_AL_16,\r
+ OSEK_AL_17,\r
+ OSEK_AL_18,\r
+ OSEK_AL_19,\r
+ OSEK_AL_20,\r
+ OSEK_AL_21,\r
+ OSEK_AL_22,\r
+ OSEK_AL_23,\r
+ OSEK_AL_24,\r
+ OSEK_AL_25,\r
+ OSEK_AL_26,\r
+ OSEK_AL_27,\r
+ OSEK_AL_28,\r
+ OSEK_AL_29,\r
+ OSEK_AL_30,\r
+ OSEK_AL_31,\r
+ OSEK_AL_32,\r
+ OSEK_AL_33,\r
+ OSEK_AL_34,\r
+ OSEK_AL_35,\r
+ OSEK_AL_36,\r
+};\r
+\r
+TestWorldType TestWorld = {0};\r
+\r
+uint32_t testNrNon = 0;\r
+\r
+static uint8_t activations = 0;\r
+\r
+#if 0\r
+static void isrSoftInt1( void ) {\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_07:\r
+ TEST_SET_FIXTURE(OSEK_AL_07, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+}\r
+\r
+static void isrSoftInt0( void ) {\r
+ StatusType rv;\r
+ TaskType taskId;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_07:\r
+ TEST_SET_FIXTURE(OSEK_AL_07, SEQ_NR_02 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_1 );\r
+ break;\r
+ case OSEK_TM_09:\r
+ TEST_SET_FIXTURE(OSEK_AL_09, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+#endif\r
+\r
+void OsIdle(void) {\r
+ while(1);\r
+}\r
+\r
+#if 0\r
+void btask_l_non ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_09:\r
+ TEST_SET_FIXTURE(OSEK_AL_09, SEQ_NR_02 );\r
+ /* Make higher prio task ready */\r
+ rv = SetEvent( TASK_ID_etask_m_full,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK ) ;\r
+ TEST_SET_FIXTURE(OSEK_AL_09, SEQ_NR_03 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_AL_09, SEQ_NR_05 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+void etask_m_non ( void ) {\r
+ StatusType rv;\r
+ TaskStateType taskState;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_AL_04:\r
+ TEST_SET_FIXTURE(OSEK_AL_04, SEQ_NR_03 );\r
+ /* Verify that task is in waiting */\r
+ rv = GetTaskState(etask_m_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_WAITING);\r
+ /* Set the Event */\r
+ rv = SetEvent( etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Verify state, again */\r
+ rv = GetTaskState(etask_m_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_READY);\r
+ TEST_SET_FIXTURE(OSEK_AL_04, SEQ_NR_04 );\r
+ break;\r
+ case OSEK_AL_04:\r
+ TEST_SET_FIXTURE(OSEK_AL_04, SEQ_NR_03 );\r
+ rv = SetEvent( etask_m_full, EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_04, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+#endif\r
+\r
+void etask_l_non( void ) {\r
+\r
+ StatusType rv;\r
+ TaskStateType taskState;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_AL_30:\r
+ TEST_SET_FIXTURE(OSEK_AL_30, SEQ_NR_02 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_30, SEQ_NR_03 );\r
+ break;\r
+ case OSEK_AL_32:\r
+ TEST_SET_FIXTURE(OSEK_AL_32, SEQ_NR_03 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+ case OSEK_AL_33:\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_03 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Set event go in etask_h_full, nothing should happen */\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_04 );\r
+\r
+ rv = GetTaskState(TASK_ID_etask_h_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_WAITING );\r
+\r
+ /* Wake up etask_m_full for cleanup */\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_05 );\r
+ break;\r
+ case OSEK_AL_34:\r
+ TEST_SET_FIXTURE(OSEK_AL_34, SEQ_NR_03 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Set event go in etask_h_full */\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_34, SEQ_NR_04 );\r
+\r
+ rv = GetTaskState(TASK_ID_etask_h_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_READY );\r
+\r
+ /* Wake up etask_m_full for cleanup */\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_34, SEQ_NR_05 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+void etask_h_full( void ) {\r
+\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_AL_14:\r
+ TEST_SET_FIXTURE(OSEK_AL_14, SEQ_NR_03 );\r
+ break;\r
+ case OSEK_AL_15:\r
+ TEST_SET_FIXTURE(OSEK_AL_15, SEQ_NR_02 );\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_15, SEQ_NR_04 );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+ case OSEK_AL_23:\r
+ TEST_SET_FIXTURE(OSEK_AL_23, SEQ_NR_03 );\r
+ break;\r
+ case OSEK_AL_24:\r
+ TEST_SET_FIXTURE(OSEK_AL_24, SEQ_NR_02 );\r
+ rv = WaitEvent(EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_24, SEQ_NR_04 );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+ case OSEK_AL_29:\r
+ TEST_SET_FIXTURE(OSEK_AL_29, SEQ_NR_03 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+ case OSEK_AL_30:\r
+ TEST_SET_FIXTURE(OSEK_AL_30, SEQ_NR_04 );\r
+ rv = SetEvent( TASK_ID_etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+ case OSEK_AL_31:\r
+ TEST_SET_FIXTURE(OSEK_AL_31, SEQ_NR_02 );\r
+ break;\r
+ case OSEK_AL_33:\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go2 | EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_07 );\r
+ break;\r
+ case OSEK_AL_34:\r
+ TEST_SET_FIXTURE(OSEK_AL_34, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_34, SEQ_NR_06 );\r
+ break;\r
+ case OSEK_AL_35:\r
+ TEST_SET_FIXTURE(OSEK_AL_35, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go2 | EVENT_MASK_go );\r
+ break;\r
+ case OSEK_AL_36:\r
+ TEST_SET_FIXTURE(OSEK_AL_36, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_SET_FIXTURE(OSEK_AL_36, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+\r
+/**\r
+ * The master in the tests
+ */\r
+void etask_m_full( void ) {\r
+\r
+ StatusType rv;\r
+ TaskType taskId;\r
+ TaskType isrTask;\r
+ TaskStateType taskState;\r
+ TickType tick;\r
+ AlarmBaseType alarmBase;\r
+ EventMaskType eventMask;\r
+\r
+ /** @treq OSEK_AL_01\r
+ *\r
+ * Call GetAlarmBase() with invalid alarm ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_01, SEQ_NR_01 );\r
+ rv = GetAlarmBase(ALARM_ID_ILL,&alarmBase);\r
+ TEST_ASSERT( rv == E_OS_ID);\r
+\r
+ /** @treq OSEK_AL_02\r
+ *\r
+ * Call GetAlarmBase()\r
+ *\r
+ * Return alarm base characteristics. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_02, SEQ_NR_01 );\r
+ rv = GetAlarmBase(ALARM_ID_act_etask_h_full,&alarmBase);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_ASSERT( alarmBase.maxallowedvalue == 65535 );\r
+ TEST_ASSERT( alarmBase.mincycle == 2 );\r
+ TEST_ASSERT( alarmBase.tickperbase == 1 );\r
+\r
+ /** @treq OSEK_AL_03\r
+ *\r
+ * Call GetAlarm() with invalid alarm ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_03, SEQ_NR_01 );\r
+ rv = GetAlarm(ALARM_ID_ILL,&tick);\r
+ TEST_ASSERT( rv == E_OS_ID);\r
+\r
+ /** @treq OSEK_AL_04\r
+ *\r
+ * Call GetAlarm() for alarm which is currently not in use\r
+ *\r
+ * Service returns E_OS_NOFUNC\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_04, SEQ_NR_01 );\r
+ rv = GetAlarm(ALARM_ID_act_etask_h_full,&tick);\r
+ TEST_ASSERT( rv == E_OS_NOFUNC);\r
+\r
+ /** @treq OSEK_AL_05\r
+ *\r
+ * Call GetAlarm() for alarm which will activate a task on expiration\r
+ *\r
+ * Returns number of ticks until expiration. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_05, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_act_etask_h_full,10,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = GetAlarm(ALARM_ID_act_etask_h_full,&tick);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_ASSERT( tick == 10 );\r
+ rv = CancelAlarm(ALARM_ID_act_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ /** @treq OSEK_AL_06\r
+ *\r
+ * Call GetAlarm() for alarm which will set an event on expiration\r
+ *\r
+ * Returns number of ticks until expiration. Service returns E_OK
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_06, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,10,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = GetAlarm(ALARM_ID_setev_go_etask_h_full,&tick);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_ASSERT( tick == 10 );\r
+ rv = CancelAlarm(ALARM_ID_setev_go_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ /** @treq OSEK_AL_07\r
+ *\r
+ * Call SetRelAlarm() with invalid alarm ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_07, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_ILL,10,0);\r
+ TEST_ASSERT( rv == E_OS_ID );\r
+\r
+ /** @treq OSEK_AL_08\r
+ *\r
+ * Call SetRelAlarm() for already activated alarm which will activate a task on expiration\r
+ *\r
+ * Service returns E_OS_STATE
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_08, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_act_etask_h_full,10,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = SetRelAlarm(ALARM_ID_act_etask_h_full,10,0);\r
+ TEST_ASSERT( rv == E_OS_STATE);\r
+ rv = CancelAlarm(ALARM_ID_act_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ /** @treq OSEK_AL_09\r
+ *\r
+ * Call SetRelAlarm() for already activated alarm which will set an\r
+ * event on expiration\r
+ *\r
+ * Service returns E_OS_STATE
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_09, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,10,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,10,0);\r
+ TEST_ASSERT( rv == E_OS_STATE);\r
+ rv = CancelAlarm(ALARM_ID_setev_go_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+\r
+ /** @treq OSEK_AL_10\r
+ *\r
+ * Call SetRelAlarm() with increment value lower than zero\r
+ *\r
+ * Service returns E_OS_VALUE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_10, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,-1,0);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+ /** @treq OSEK_AL_11\r
+ *\r
+ * Call SetRelAlarm() with increment value greater than maxallowedvalue\r
+ *\r
+ * Service returns E_OS_VALUE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_11, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,UINT16_MAX+1,0);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+ /** @treq OSEK_AL_12\r
+ *\r
+ * Call SetRelAlarm() with cycle value lower than mincycle\r
+ *\r
+ * Service returns E_OS_VALUE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_12, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,10,1);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+\r
+ /** @treq OSEK_AL_13\r
+ *\r
+ * Call SetRelAlarm() with cycle value greater than maxallowedvalue\r
+ *\r
+ * Service returns E_OS_VALUE
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_13, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,10,UINT16_MAX+1);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+ /** @treq OSEK_AL_14\r
+ *\r
+ * Call SetRelAlarm() for alarm which will activate a task on expiration\r
+ *\r
+ * Alarm is activated. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_14, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_act_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_14, SEQ_NR_02 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_14, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_AL_15\r
+ *\r
+ * Call SetRelAlarm() for alarm which will set an event on expiration\r
+ *\r
+ * Alarm is activated. Service returns E_OK
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_AL_15, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ /* The task may not be suspended */\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_15, SEQ_NR_03 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_15, SEQ_NR_05 );\r
+\r
+ /** @treq OSEK_AL_16\r
+ *\r
+ * Call SetAbsAlarm() with invalid alarm ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_16, SEQ_NR_01 );\r
+ rv = SetAbsAlarm(ALARM_ID_ILL,2,0);\r
+ TEST_ASSERT( rv == E_OS_ID);\r
+\r
+ /** @treq OSEK_AL_17\r
+ *\r
+ * Call SetAbsAlarm() for already activated alarm which will activate a task on expiration\r
+ *\r
+ * Service returns E_OS_STATE
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_17, SEQ_NR_01 );\r
+ rv = SetAbsAlarm(ALARM_ID_act_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = SetAbsAlarm(ALARM_ID_act_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OS_STATE);\r
+ rv = CancelAlarm(ALARM_ID_act_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ /** @treq OSEK_AL_18\r
+ *\r
+ * Call SetAbsAlarm() for already activated alarm which will set an\r
+ * event on expiration\r
+ *\r
+ * Service returns E_OS_STATE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_18, SEQ_NR_01 );\r
+ rv = SetAbsAlarm(ALARM_ID_setev_go_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = SetAbsAlarm(ALARM_ID_setev_go_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OS_STATE);\r
+ rv = CancelAlarm(ALARM_ID_setev_go_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+\r
+ /** @treq OSEK_AL_19\r
+ *\r
+ * Call SetAbsAlarm() with increment value lower than zero\r
+ *\r
+ * Service returns E_OS_VALUE\r
+ */
+ TEST_SET_FIXTURE(OSEK_AL_19, SEQ_NR_01 );\r
+ rv = SetAbsAlarm(ALARM_ID_setev_go_etask_h_full,-1,0);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+ /** @treq OSEK_AL_20\r
+ *\r
+ * Call SetAbsAlarm() with increment value greater than maxallowedvalue\r
+ *\r
+ * Service returns E_OS_VALUE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_20, SEQ_NR_01 );\r
+ rv = SetAbsAlarm(ALARM_ID_setev_go_etask_h_full,UINT16_MAX+1,0);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+ /** @treq OSEK_AL_21\r
+ *\r
+ * Call SetAbsAlarm() with cycle value lower than mincycle\r
+ *\r
+ * Service returns E_OS_VALUE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_21, SEQ_NR_01 );\r
+ rv = SetAbsAlarm(ALARM_ID_setev_go_etask_h_full,10,1);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+ /** @treq OSEK_AL_22\r
+ *\r
+ * Call SetAbsAlarm() with cycle value greater than maxallowedvalue\r
+ * Service returns E_OS_VALUE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_22, SEQ_NR_01 );\r
+ rv = SetAbsAlarm(ALARM_ID_setev_go_etask_h_full,10,UINT16_MAX+1);\r
+ TEST_ASSERT( rv == E_OS_VALUE);\r
+\r
+ /** @treq OSEK_AL_23\r
+ *\r
+ * Call SetAbsAlarm() for alarm which will activate a task on expiration\r
+ *\r
+ * Alarm is activated. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_23, SEQ_NR_01 );\r
+ rv = GetCounterValue(COUNTER_ID_soft1,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ rv = SetAbsAlarm(ALARM_ID_act_etask_h_full,tick+2,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_23, SEQ_NR_02 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_23, SEQ_NR_04 );\r
+\r
+\r
+ /** @treq OSEK_AL_24\r
+ *\r
+ * Call SetAbsAlarm() for alarm which will set an event on expiration\r
+ *\r
+ * Alarm is activated. Service returns E_OK\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_AL_24, SEQ_NR_01 );\r
+\r
+ rv = GetCounterValue(COUNTER_ID_soft1,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ rv = SetAbsAlarm(ALARM_ID_setev_go_etask_h_full,tick+2,0);\r
+ TEST_ASSERT( rv == E_OK);\r
+ /* The task may not be suspended */\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK);\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_24, SEQ_NR_03 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK);\r
+ TEST_SET_FIXTURE(OSEK_AL_24, SEQ_NR_05 );\r
+\r
+ /** @treq OSEK_AL_25\r
+ *\r
+ * Call CancelAlarm() with invalid alarm ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_25, SEQ_NR_01 );\r
+ rv = CancelAlarm(ALARM_ID_ILL);\r
+ TEST_ASSERT( rv == E_OS_ID );\r
+\r
+ /** @treq OSEK_AL_26\r
+ *\r
+ * Call CancelAlarm() for alarm which is currently not in use\r
+ *\r
+ * Service returns E_OS_NOFUNC\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_26, SEQ_NR_01 );\r
+ rv = CancelAlarm(ALARM_ID_act_etask_h_full);\r
+ TEST_ASSERT( rv == E_OS_NOFUNC );\r
+\r
+ /** @treq OSEK_AL_27\r
+ *\r
+ * Call CancelAlarm() for already activated alarm which will activate a task on expiration\r
+ *\r
+ * Alarm is cancelled. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_27, SEQ_NR_01 );\r
+ /* Already covered by OSEK_AL_05 */\r
+\r
+ /** @treq OSEK_AL_28\r
+ *\r
+ * Call CancelAlarm() for already activated alarm which will set an event on expiration\r
+ *\r
+ * Alarm is cancelled. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_28, SEQ_NR_01 );\r
+ /* Already covered by OSEK_AL_06 */\r
+\r
+ /** @treq OSEK_AL_29\r
+ *\r
+ * Expiration of alarm which activates a task while no tasks are currently running\r
+ *\r
+ * Task is activated
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_29, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_sys_tick_act_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_29, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_29, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_AL_30\r
+ *\r
+ * Expiration of alarm which activates a task while running task is non-preemptive\r
+ *\r
+ * Task is activated. No preemption of running task\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_30, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_act_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ActivateTask(TASK_ID_etask_l_non);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Swap to NON task */\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /** @treq OSEK_AL_31\r
+ *\r
+ * Expiration of alarm which activates a task with higher priority than running task while running task is preemptive\r
+ *\r
+ * Task is activated. Task with highest priority is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_31, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_act_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_31, SEQ_NR_03 );\r
+\r
+ /** @treq OSEK_AL_32\r
+ *\r
+ * Expiration of alarm which activates a task with lower priority than running task while running task is preemptive\r
+ *\r
+ * Task is activated. No preemption of running task.\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_32, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_act_etask_l_non,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_32, SEQ_NR_02 );\r
+ /* Swap to alarm task */\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_32, SEQ_NR_04 );\r
+\r
+ /** @treq OSEK_AL_33\r
+ *\r
+ * Expiration of alarm which sets an event while running task is non-preemptive.\r
+ *\r
+ * Task which owns the event is not waiting for this event and not suspended.Event is set\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /* Activate task that waits for go2 */\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /* Activate the NON task */\r
+ rv = ActivateTask(TASK_ID_etask_l_non);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /* Swap to NON task */\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_06 );\r
+\r
+ /* Cleanup by etask_h_full */\r
+ rv = SetEvent( TASK_ID_etask_h_full, EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_33, SEQ_NR_08 );\r
+ /** @treq OSEK_AL_34\r
+ *\r
+ * Expiration of alarm which sets an event while running task is non-preemptive.\r
+ * Task which owns the event is waiting for this event.\r
+ *\r
+ * Event is set. Task which is owner of the event becomes ready.\r
+ * No preemption of running task\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_34, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /* Activate task that waits for go */\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /* Activate the NON task */\r
+ rv = ActivateTask(TASK_ID_etask_l_non);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /* Swap to NON task */\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ TEST_SET_FIXTURE(OSEK_AL_34, SEQ_NR_07 );\r
+\r
+ /** @treq OSEK_AL_35\r
+ *\r
+ * Expiration of alarm which sets an event while running task is preemptive.\r
+ * Task which owns the event is not waiting for this event and not suspended.\r
+ *\r
+ * Event is set
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_35, SEQ_NR_01 );\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,2,0);\r
+\r
+ /* Activate task that waits for go */\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ TEST_SET_FIXTURE(OSEK_AL_35, SEQ_NR_03 );\r
+ /* Set go event */\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ TEST_SET_FIXTURE(OSEK_AL_35, SEQ_NR_04 );\r
+\r
+ rv = GetEvent(TASK_ID_etask_h_full,&eventMask);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( eventMask == EVENT_MASK_go );\r
+\r
+ /* Cleanup */\r
+ rv = SetEvent(TASK_ID_etask_h_full,EVENT_MASK_go2);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /** @treq OSEK_AL_36\r
+ *\r
+ * Expiration of alarm which sets an event while running task is preemptive.\r
+ * Task which owns the event is waiting for this event.\r
+ *\r
+ * Event is set. Task which is owner of the event becomes ready.\r
+ * Task with highest priority is executed(Rescheduling)\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_AL_36, SEQ_NR_01 );\r
+\r
+ rv = SetRelAlarm(ALARM_ID_setev_go_etask_h_full,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ActivateTask(TASK_ID_etask_h_full);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ TEST_SET_FIXTURE(OSEK_AL_36, SEQ_NR_03 );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = IncrementCounter(COUNTER_ID_soft1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_AL_36, SEQ_NR_05 );\r
+\r
+ TestExit(0);\r
+}\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.4"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE>\r
+ <SHORT-NAME>NewEcu</SHORT-NAME>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="d30db794-36ce-42ce-8658-deb9cfbfc18a">\r
+ <SHORT-NAME>config_osek_ev</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/osek_03_ev</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <ECU-SW-COMPOSITION-REF DEST="ECU-SW-COMPOSITION">/NewEcu/SwComposition_NewEcu</ECU-SW-COMPOSITION-REF>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/NewEcu/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <ECU-SW-COMPOSITION UUID="aab85286-8442-4d60-bf6d-a8cdea2f4f7c">\r
+ <SHORT-NAME>SwComposition_NewEcu</SHORT-NAME>\r
+ </ECU-SW-COMPOSITION>\r
+ <MODULE-CONFIGURATION UUID="fb96b9f7-d486-4956-bcf5-03ac6c6e5f78">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.11</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="e38c4f96-a8c1-4489-b907-03eb4441b231">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a7839b8f-1ed1-4f24-b05f-06850836ea32">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="074c4c94-0aa1-4158-9223-7136a526fac0">\r
+ <SHORT-NAME>Task1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="c17d3508-e67f-49bd-92fb-8a3a51531b49">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Mon Sep 20 16:43:27 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(\r
+ RES_ID_std_1,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_h_full,2048);\r
+DECLARE_STACK(btask_l_full,2048);\r
+DECLARE_STACK(btask_ll_non,2048);\r
+DECLARE_STACK(btask_m_full,2048);\r
+DECLARE_STACK(btask_m_non,2048);\r
+DECLARE_STACK(etask_h_full,2048);\r
+DECLARE_STACK(etask_l_full,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+DECLARE_STACK(etask_m_full_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_ll_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_full,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_non,\r
+ 1,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 5,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ RES_MASK_std_1 | 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full_2,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.11
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Mon Sep 20 16:43:27 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_go 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+#define RES_ID_std_1 0\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+#define RES_MASK_std_1 (1 << 0)\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_h_full 1\r
+#define TASK_ID_btask_l_full 2\r
+#define TASK_ID_btask_ll_non 3\r
+#define TASK_ID_btask_m_full 4\r
+#define TASK_ID_btask_m_non 5\r
+#define TASK_ID_etask_h_full 6\r
+#define TASK_ID_etask_l_full 7\r
+#define TASK_ID_etask_m_full 8\r
+#define TASK_ID_etask_m_full_2 9\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_h_full( void );\r
+void btask_l_full( void );\r
+void btask_ll_non( void );\r
+void btask_m_full( void );\r
+void btask_m_non( void );\r
+void etask_h_full( void );\r
+void etask_l_full( void );\r
+void etask_m_full( void );\r
+void etask_m_full_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 0 \r
+#define OS_TASK_CNT 10\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 1\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 1\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU COMMON NEWLIB DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_02_ip.o\r
+obj-y += test_hooks.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+VPATH += ..\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/*\r
+ * Created on: 4 aug 2010\r
+ * Author: mahi\r
+ */\r
+/*\r
+ * This file tests test requirements OSEK_EV_XX.\r
+ * We need only 2 tasks, 1 non-preemtive\r
+ *\r
+ *\r
+ * Priorities:\r
+ * ll - low low prio (used for scheduling only)\r
+ * l - low prio\r
+ * m - medium\r
+ * h - high prio\r
+ */\r
+\r
+\r
+#include "os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+#include "irq.h"\r
+\r
+\r
+\r
+enum OsekFixtureNr {\r
+ OSEK_EV_01 = 1,\r
+ OSEK_EV_02,\r
+ OSEK_EV_03,\r
+ OSEK_EV_04,\r
+ OSEK_EV_05,\r
+ OSEK_EV_06,\r
+ OSEK_EV_07,\r
+ OSEK_EV_08,\r
+ OSEK_EV_09,\r
+ OSEK_EV_10,\r
+ OSEK_EV_11,\r
+ OSEK_EV_12,\r
+ OSEK_EV_13,\r
+ OSEK_EV_14,\r
+ OSEK_EV_15,\r
+ OSEK_EV_16,\r
+ OSEK_EV_17,\r
+ OSEK_EV_18,\r
+ OSEK_EV_19,\r
+ OSEK_EV_20,\r
+ OSEK_EV_21,\r
+ OSEK_EV_22,\r
+ OSEK_EV_23,\r
+ OSEK_EV_24,\r
+};\r
+\r
+TestWorldType TestWorld = {0};\r
+\r
+uint32_t testNrNon = 0;\r
+\r
+static uint8_t activations = 0;\r
+\r
+static void isrSoftInt1( void ) {\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_07:\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_03 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ break;\r
+ }\r
+}\r
+\r
+static void isrSoftInt0( void ) {\r
+ StatusType rv;\r
+ TaskType taskId;\r
+\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_07:\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_02 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_1 );\r
+ break;\r
+ case OSEK_TM_09:\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+\r
+\r
+void OsIdle(void) {\r
+ while(1);\r
+}\r
+\r
+\r
+void btask_l_non ( void ) {\r
+ StatusType rv;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_TM_09:\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_02 );\r
+ /* Make higher prio task ready */\r
+ rv = SetEvent( TASK_ID_etask_m_full,EVENT_MASK_go);\r
+ TEST_ASSERT( rv == E_OK ) ;\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_03 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_05 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+}\r
+\r
+void etask_m_non ( void ) {\r
+ StatusType rv;\r
+ TaskStateType taskState;\r
+ switch ( TestWorld.fixtureNr ) {\r
+ case OSEK_EV_04:\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_03 );\r
+ /* Verify that task is in waiting */\r
+ rv = GetTaskState(etask_m_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_WAITING);\r
+ /* Set the Event */\r
+ rv = SetEvent( etask_m_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* Verify state, again */\r
+ rv = GetTaskState(etask_m_full,&taskState);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT( taskState == TASK_STATE_READY);\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_04 );\r
+ break;\r
+ case OSEK_EV_04:\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_03 );\r
+ rv = SetEvent( etask_m_full, EVENT_MASK_go2 );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_04 );\r
+ break;\r
+ default:\r
+ TEST_ASSERT( 0 );\r
+ }\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+}\r
+\r
+/**\r
+ * The master in the tests
+ */\r
+void etask_m_full( void ) {\r
+\r
+ StatusType rv;\r
+ TaskType taskId;\r
+ TaskType isrTask;\r
+ TaskStateType taskState;\r
+\r
+ /** @treq OSEK_EV_01\r
+ *\r
+ * Call SetEvent() with invalid Task ID\r
+ *\r
+ * Service returns E_OS_ID\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_EV_01, SEQ_NR_01 );\r
+ rv = SetEvent(TASK_ID_ILL);\r
+ TEST_ASSERT( rv == E_OS_ID );\r
+\r
+ /** @treq OSEK_EV_02\r
+ *\r
+ * Call SetEvent() for basic task\r
+ *\r
+ * Service returns E_OS_ACCESS\r
+ */\r
+\r
+ TEST_SET_FIXTURE(OSEK_EV_02, SEQ_NR_01 );\r
+ rv = SetEvent( TASK_ID_btask_l_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OS_ACCESS );\r
+\r
+\r
+ // --------------------------------------------------------------------\r
+\r
+ /** @treq OSEK_EV_03\r
+ *\r
+ * Call SetEvent() for suspended extended task\r
+ *\r
+ * Service returns E_OS_STATE\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_03, SEQ_NR_01 );\r
+ rv = SetEvent( TASK_ID_etask_l_full, EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OS_STATE );\r
+\r
+ /** @treq OSEK_EV_04\r
+ *\r
+ * Call SetEvent() from non-preemptive task on waiting extended\r
+ * task which is waiting for at least one of the requested events\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Waiting task becomes ready Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_m_non );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_02 );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_04, SEQ_NR_05 );\r
+\r
+ /** @treq OSEK_EV_05\r
+ *\r
+ * Call SetEvent() from non-preemptive task on waiting extended\r
+ * task which is not waiting for any of the requested events\r
+ *\r
+ * Requested events are set. Running task is not preempted.\r
+ * Waiting task doesn\92t become ready. Service returns E_OK\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_05, SEQ_NR_01 );\r
+ rv = ActivateTask( TASK_ID_etask_m_non );\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ /** @treq OSEK_EV_06\r
+ *\r
+ * Interruption of running task\r
+ *\r
+ * Interrupt is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_06, SEQ_NR_01 );\r
+ /* Already tested in a number of cases in tm suite */\r
+\r
+ /** @treq OSEK_EV_07\r
+ *\r
+ * Interruption of ISR2\r
+ *\r
+ * Interrupt is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_01 );\r
+ /* Create an ISR2 */\r
+ isrTask = Os_Arc_CreateIsr( isrSoftInt0, 8/*prio*/,"soft_0");\r
+ Irq_AttachIsr2(isrTask,NULL, IRQ_SOFTINT_0);\r
+\r
+ /* Create an ISR2 */\r
+ isrTask = Os_Arc_CreateIsr( isrSoftInt0, 9/*prio*/,"soft_1");\r
+ Irq_AttachIsr2(isrTask,NULL, IRQ_SOFTINT_1);\r
+\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
+ TEST_SET_FIXTURE(OSEK_EV_07, SEQ_NR_04 );\r
+\r
+\r
+ /** @treq OSEK_EV_08\r
+ *\r
+ * Interruption of ISR3\r
+ *\r
+ * Interrupt is executed\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_08, SEQ_NR_01 );\r
+ /* ISR3 is not applicable */\r
+\r
+ /** @treq OSEK_EV_09\r
+ *\r
+ * Return from ISR2. Interrupted task is non-preemptive\r
+ *\r
+ * Execution of interrupted task is continued\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_01 );\r
+ rv = ActivateTask(TASK_ID_btask_l_non );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = WaitEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = ClearEvent( EVENT_MASK_go );\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_SET_FIXTURE(OSEK_EV_09, SEQ_NR_06 );\r
+\r
+ /** @treq OSEK_EV_10\r
+ *\r
+ * Return from ISR3. Interrupted task is non-preemptive\r
+ *\r
+ * Execution of interrupted task is continued\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_10, SEQ_NR_01 );\r
+ /* ISR3 is not applicable */\r
+\r
+ /** @treq OSEK_EV_11\r
+ *\r
+ * Return from ISR2. Interrupted task is preemptive\r
+ *\r
+ * Ready task with highest priority is executed (Rescheduling)\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_11, SEQ_NR_01 );\r
+\r
+\r
+\r
+ /** @treq OSEK_EV_12\r
+ *\r
+ * Return from ISR3. Interrupted task is preemptive\r
+ *\r
+ * Ready task with highest priority is executed (Rescheduling)\r
+ */\r
+ TEST_SET_FIXTURE(OSEK_EV_12, SEQ_NR_01 );\r
+ /* ISR3 is not applicable */\r
+\r
+\r
+ TestExit(0);\r
+}\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue Jun 08 20:51:20 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_OsTick,\r
+ "OsTick",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+ GEN_COUNTER( COUNTER_ID_soft_1,\r
+ "soft_1",\r
+ COUNTER_TYPE_SOFT,\r
+ COUNTER_UNIT_NANO,\r
+ 65535,\r
+ 1,\r
+ 1,\r
+ 0),\r
+ GEN_COUNTER( COUNTER_ID_soft_2,\r
+ "soft_2",\r
+ COUNTER_TYPE_SOFT,\r
+ COUNTER_UNIT_NANO,\r
+ 65535,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_OsTick;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_c_soft_1_inc_counter_2,\r
+ "c_soft_1_inc_cou",\r
+ COUNTER_ID_soft_1,\r
+ NULL,\r
+ ALARM_ACTION_INCREMENTCOUNTER,\r
+ NULL,\r
+ NULL,\r
+ COUNTER_ID_soft_2 ),\r
+ GEN_ALARM( ALARM_ID_c_soft_1_setevent_etask_m,\r
+ "c_soft_1_seteven",\r
+ COUNTER_ID_soft_1,\r
+ NULL,\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_sup_m,\r
+ EVENT_MASK_notif,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_c_sys_1_setevent_etask_m,\r
+ "c_sys_1_setevent",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_sup_m,\r
+ EVENT_MASK_notif,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_c_sys_activate_btask_h,\r
+ "c_sys_activate_b",\r
+ COUNTER_ID_OsTick,\r
+ NULL,\r
+ ALARM_ACTION_ACTIVATETASK,\r
+ TASK_ID_btask_sup_h,\r
+ NULL,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(\r
+ RES_ID_int_1,\r
+ RESOURCE_TYPE_INTERNAL,\r
+ 0\r
+ ),\r
+ GEN_RESOURCE(\r
+ RES_ID_std_prio_3,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+ GEN_RESOURCE(\r
+ RES_ID_std_prio_4,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+ GEN_RESOURCE(\r
+ RES_ID_std_prio_5,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_sup_h,2048);\r
+DECLARE_STACK(btask_sup_l,2048);\r
+DECLARE_STACK(btask_sup_m,2048);\r
+DECLARE_STACK(etask_master,2048);\r
+DECLARE_STACK(etask_sup_h,2048);\r
+DECLARE_STACK(etask_sup_l,2048);\r
+DECLARE_STACK(etask_sup_m,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_sup_h,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_sup_l,\r
+ 2,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_sup_m,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_master,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_sup_h,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_sup_l,\r
+ 2,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_sup_m,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ RES_MASK_std_prio_3 | RES_MASK_std_prio_4 | RES_MASK_std_prio_5 | 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table data 0\r
+\r
+GEN_SCHTBL_TASK_LIST_HEAD( 0, 5 ) { \r
+ \r
+ TASK_ID_etask_sup_m,\r
+ \r
+};\r
+\r
+\r
+\r
+\r
+GEN_SCHTBL_EVENT_LIST_HEAD( 0, 7 ) {\r
+ \r
+ { \r
+ EVENT_MASK_notif, \r
+ TASK_ID_etask_sup_m \r
+ },\r
+ \r
+};\r
+\r
+\r
+GEN_SCHTBL_TASK_LIST_HEAD( 0, 11 ) { \r
+ \r
+ TASK_ID_etask_sup_m,\r
+ \r
+};\r
+\r
+GEN_SCHTBL_EVENT_LIST_HEAD( 0, 11 ) {\r
+ \r
+ { \r
+ EVENT_MASK_notif, \r
+ TASK_ID_etask_sup_m \r
+ },\r
+ \r
+};\r
+\r
+\r
+GEN_SCHTBL_EXPIRY_POINT_HEAD( 0 ) {\r
+ GEN_SCHTBL_EXPIRY_POINT_W_TASK(0, 5),
+ GEN_SCHTBL_EXPIRY_POINT_W_EVENT(0, 7),
+ GEN_SCHTBL_EXPIRY_POINT_W_TASK_EVENT(0, 11),
+ \r
+};\r
+\r
+\r
+// Table data 1\r
+\r
+GEN_SCHTBL_TASK_LIST_HEAD( 1, 2 ) { \r
+ \r
+ TASK_ID_etask_sup_m,\r
+ \r
+};\r
+\r
+\r
+\r
+GEN_SCHTBL_EXPIRY_POINT_HEAD( 1 ) {\r
+ GEN_SCHTBL_EXPIRY_POINT_W_TASK(1, 2),
+ \r
+};\r
+\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+ GEN_SCHEDULETABLE(\r
+ 0,\r
+ "0",\r
+ COUNTER_ID_soft_1,\r
+ SINGLE_SHOT,\r
+ 15,\r
+ NULL\r
+ ),\r
+ GEN_SCHEDULETABLE(\r
+ 1,\r
+ "1",\r
+ COUNTER_ID_soft_1,\r
+ SINGLE_SHOT,\r
+ 5,\r
+ NULL\r
+ ),\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): MPC551x
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue Jun 08 20:51:20 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_c_soft_1_inc_counter_2 0\r
+#define ALARM_ID_c_soft_1_setevent_etask_m 1\r
+#define ALARM_ID_c_sys_1_setevent_etask_m 2\r
+#define ALARM_ID_c_sys_activate_btask_h 3\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_OsTick 0\r
+#define COUNTER_ID_soft_1 1\r
+#define COUNTER_ID_soft_2 2\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_OsTick 65535\r
+#define OSMAXALLOWEDVALUE_soft_1 65535\r
+#define OSMAXALLOWEDVALUE_soft_2 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_kill 32768\r
+#define EVENT_MASK_notif 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+#define RES_ID_int_1 0\r
+#define RES_ID_std_prio_3 1\r
+#define RES_ID_std_prio_4 2\r
+#define RES_ID_std_prio_5 3\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+#define RES_MASK_int_1 (1 << 0)\r
+#define RES_MASK_std_prio_3 (1 << 1)\r
+#define RES_MASK_std_prio_4 (1 << 2)\r
+#define RES_MASK_std_prio_5 (1 << 3)\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_sup_h 1\r
+#define TASK_ID_btask_sup_l 2\r
+#define TASK_ID_btask_sup_m 3\r
+#define TASK_ID_etask_master 4\r
+#define TASK_ID_etask_sup_h 5\r
+#define TASK_ID_etask_sup_l 6\r
+#define TASK_ID_etask_sup_m 7\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_sup_h( void );\r
+void btask_sup_l( void );\r
+void btask_sup_m( void );\r
+void etask_master( void );\r
+void etask_sup_h( void );\r
+void etask_sup_l( void );\r
+void etask_sup_m( void );\r
+\r
+// Schedule table id's\r
+#define SCHTBL_ID_0 0\r
+#define SCHTBL_ID_1 1\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 4 \r
+#define OS_TASK_CNT 8\r
+#define OS_SCHTBL_CNT 2\r
+#define OS_COUNTER_CNT 3\r
+#define OS_EVENTS_CNT 2\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 4\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+\r
+OPTIMAL_USE = RAMLOG\r
+MOD_USE+=KERNEL MCU DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE UUID="822fb2e1-4171-4ec3-812a-b58265eb646e">\r
+ <SHORT-NAME>testsystem</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="adececfa-6614-4f2a-bc3b-0de7440970a7">\r
+ <SHORT-NAME>config_01</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <REVISION-LABEL>Rev</REVISION-LABEL>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">MPC551x</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/config</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/testsystem/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="9810a6d9-2cc9-4b23-a969-e4662fdc4a40">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.4</SD>\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="c28c1e41-ab85-44af-8c08-8bfe14a614d8">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="225d4007-aaa5-4862-9c24-1c00c1418e51">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="18ffb863-c03b-485d-9d2f-6f3516d63901">\r
+ <SHORT-NAME>int_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsResource</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsResource/OsResourceProperty</DEFINITION-REF>\r
+ <VALUE>INTERNAL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="86681234-fe16-4039-82aa-b7d47e2e38ae">\r
+ <SHORT-NAME>etask_master</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="5f49198a-5604-45b0-b4ea-e5a711e5416f">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1f1560f5-2306-4238-a7a4-50d5bdc6a359">\r
+ <SHORT-NAME>etask_sup_l</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_3</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_4</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_5</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c5691264-811a-4714-8c56-37affb1ba27c">\r
+ <SHORT-NAME>etask_sup_m</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_3</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_4</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_5</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6d2cdf4d-467d-43a0-a7b6-5f23a73fbf12">\r
+ <SHORT-NAME>etask_sup_h</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>6</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_3</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskResourceRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/std_prio_4</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
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+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/OsTick</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="7ebab0c9-e8c1-4371-b439-a901d6122efc">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/notif</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/etask_sup_m</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f6022231-7387-4d18-9833-be28dce71f30">\r
+ <SHORT-NAME>c_soft_1_setevent_etask_m</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/soft_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="f832f963-085b-45f1-a4a5-507e10cef798">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/notif</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/etask_sup_m</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="85e281ff-fa24-4ade-867b-4126a3bc99e2">\r
+ <SHORT-NAME>c_soft_1_inc_counter_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/soft_1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b5cc2bdd-1f43-414d-bea7-d7cb4d559d3b">\r
+ <SHORT-NAME>OsAlarmIncrementCounter</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmIncrementCounter</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmIncrementCounter/OsAlarmIncrementCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/testsystem/Os/soft_2</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f510c7bd-12d7-475b-88cf-387b50e955c9">\r
+ <SHORT-NAME>soft_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>SOFTWARE</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+obj-y+= arc.o\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_master.o\r
+obj-y += test_01_task.o\r
+obj-y += test_02_resource.o\r
+obj-y += test_03_alarm.o\r
+obj-y += test_04_stable.o\r
+obj-y += test_05_const.o\r
+obj-y += test_06_event.o\r
+\r
+obj-y += test_framework.o\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+#MOD_USE+=PROTECTIONHOOK STARTUPHOOK SHUTDOWNHOOK ERRORHOOK 1\r
+#MOD_USE+=PRETASKHOOK POSTTASKHOOK\r
+CFG+=CONSOLE_T32\r
+CFG+=CONSOLE_WINIDEA\r
+\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+\r
+# libs needed by us \r
+#libitem-y +=\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Tests tasks:\r
+ *\r
+ * OSEK\r
+ * - ActivateTask E_OS_ID, E_OS_LIMIT\r
+ * - TerminateTask E_OS_RESOURCE, E_OS_CALLEVEL\r
+ * - ChainTask E_OS_ID, E_OS_LIMIT, E_OS_RESOURCE, E_OS_CALLLEVEL\r
+ * - Schedule E_OS_CALLEVEL, E_OS_RESOURCE\r
+ * - GetTaskID\r
+ * - GetTaskState E_OS_ID\r
+ *\r
+ *\r
+ * Limitations:\r
+ * - No way to detect if in ISR1 or hooks\r
+ * - NON tasks are not tested.\r
+ * - ActivateTask() with own taskid?\r
+ */\r
+\r
+#include "Os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+\r
+int btaskRunCnt = 0;\r
+\r
+static int status_100 = 0;\r
+\r
+void isr_l(void ) {\r
+ StatusType rv;\r
+ switch(test_nr) {\r
+ case 11:\r
+ rv = TerminateTask();\r
+ TEST_ASSERT(rv=E_OS_CALLEVEL);\r
+ break;\r
+ case 12:\r
+ break;\r
+ case 13:\r
+ break;\r
+ default:\r
+ while(1);\r
+ }\r
+}\r
+\r
+void etask_sup_l_01(void) {\r
+ _Bool done = 0;\r
+ StatusType rv;\r
+\r
+ while (!done) {\r
+ TEST_RUN();\r
+\r
+ switch (test_nr) {\r
+ case 1:\r
+ /*@req E_OS_ID ActivateTask */\r
+ rv = ActivateTask(TASK_ID_ILL);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ test_nr = 2;\r
+ break;\r
+ case 2:\r
+ /*@req E_OS_LIMIT ActivateTask\r
+ * Test the activation limit and check that activated task is run\r
+ * the activation limit times */\r
+\r
+ /* Activate higher prio task to do the test */\r
+ rv = ActivateTask(TASK_ID_btask_sup_h);\r
+ TEST_ASSERT(rv == E_OK);\r
+\r
+ /* Was it run activation times? */\r
+ TEST_ASSERT(btaskRunCnt == Os_ArcTest_GetTaskActivationLimit(TASK_ID_btask_sup_m));\r
+ test_nr = 10;\r
+ break;\r
+ case 10:\r
+ /*@req E_OS_RESOURCE TerminateTask\r
+ * Terminate a task that still holds resources\r
+ * This is done in the TASK_ID_btask_sup_m task..\r
+ */\r
+ rv = ActivateTask(TASK_ID_btask_sup_m);\r
+ TEST_ASSERT(rv == E_OK);\r
+ test_nr++;\r
+ break;\r
+ case 11:\r
+ /*@req E_OS_CALLEVEL TerminateTask */\r
+ Os_ArcTest_SetIrqNestLevel(1);\r
+ isr_l();\r
+ Os_ArcTest_SetIrqNestLevel(0);\r
+ test_nr=20;\r
+ break;\r
+\r
+ case 20:\r
+ /*@req E_OS_ID ChainTask */\r
+ rv = ChainTask(TASK_ID_ILL);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ test_nr = 100;\r
+ case 21:\r
+ /*@req E_OS_LIMIT ChainTask */\r
+ case 22:\r
+ /*@req E_OS_RESOURCE ChainTask */\r
+ case 23:\r
+ /*@req E_OS_CALLLEVEL ChainTask */\r
+ break;\r
+\r
+ case 30:\r
+ /*@req E_OS_CALLEVEL Schedule */\r
+ case 31:\r
+ /*@req E_OS_RESOURCE Schedule */\r
+ break;\r
+\r
+ case 100:\r
+ /* Check that tasks as run in priority order and that the oldest task\r
+ * of the same priority should be scheduled first.\r
+ * 1. esup_l: Activate(sup_m)\r
+ * 2. bsup_m: Activate(sup_l) (should not be taken)\r
+ * 3. bsup_m: Activate(sup_h) (taken)\r
+ * 4. bsup_h: Terminate()\r
+ * (We should now have bsup_m, esup_l, bsup_l )\r
+ * 5. bsup_m: Terminate()\r
+ * 6. esup_l : Terminate()\r
+ * 7. bsup_l : Activate(esup_l) (found by dispatcher)\r
+ * 8. esup_l: Back again!!!!\r
+ *\r
+ * */\r
+ if(status_100==6) {\r
+ test_nr=101;\r
+ break;\r
+ }\r
+ btaskRunCnt = 0;\r
+ rv = ActivateTask(TASK_ID_btask_sup_m);\r
+ TEST_ASSERT(status_100=3);\r
+ status_100=4;\r
+ TerminateTask(); // Step 6.\r
+\r
+ // Should never get here since we have restarded ourselves.\r
+ assert(0);\r
+ break;\r
+ case 101:\r
+ /* End Testing of this module */\r
+ TerminateTask();\r
+ break;\r
+ default:\r
+ while(1);\r
+ }\r
+ }\r
+}\r
+\r
+void btask_sup_l_01( void ) {\r
+ switch(test_nr){\r
+ case 100:\r
+ btaskRunCnt++;\r
+ /* Make it go up again */\r
+ TEST_ASSERT(status_100=4);\r
+ status_100=5;\r
+ ActivateTask(TASK_ID_etask_sup_l); // Step 7.\r
+ TEST_ASSERT(status_100=5);\r
+ status_100=6;\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+}\r
+\r
+void btask_sup_m_01( void ) {\r
+ int rv;\r
+ switch(test_nr){\r
+ case 2:\r
+ btaskRunCnt++;\r
+ TerminateTask();\r
+ break;\r
+ case 10:\r
+ rv = GetResource(RES_ID_std_prio_3);\r
+ TEST_ASSERT(rv == E_OK);\r
+\r
+ rv = TerminateTask();\r
+ TEST_ASSERT(rv==E_OS_RESOURCE);\r
+\r
+ rv = ReleaseResource(RES_ID_std_prio_3);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TerminateTask();\r
+ break;\r
+ case 100:\r
+ /* We got here from etask_l, so it should be oldest */\r
+ rv = ActivateTask(TASK_ID_btask_sup_l);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT(status_100==0);\r
+ status_100=1;\r
+ rv = ActivateTask(TASK_ID_btask_sup_h);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT(status_100==2);\r
+ status_100=3;\r
+ break;\r
+ default:\r
+ while(1);\r
+ }\r
+\r
+}\r
+\r
+void btask_sup_h_01(void) {\r
+ StatusType rv;\r
+ int limit;\r
+\r
+ switch (test_nr) {\r
+ case 2:\r
+ /* Activate a basic task to many times */\r
+ limit = Os_ArcTest_GetTaskActivationLimit(TASK_ID_btask_sup_m);\r
+ for (int i = 0; i < limit; i++) {\r
+ rv = ActivateTask(TASK_ID_btask_sup_m);\r
+ TEST_ASSERT(rv == E_OK);\r
+ }\r
+ rv = ActivateTask(TASK_ID_btask_sup_m);\r
+ TEST_ASSERT(rv == E_OS_LIMIT);\r
+ /* Let the us terminate and count the number of times the tasks\r
+ * was actually activated\r
+ *\r
+ * TODO:@req Since the etask and btask have the same priority, who gets scheduled?\r
+ * Oldest is scheduled first..\r
+ * */\r
+ break;\r
+ case 100:\r
+ TEST_ASSERT(status_100==1);\r
+ status_100=2;\r
+ break;\r
+ default:\r
+ while(1);\r
+\r
+ }\r
+}\r
+\r
+DECLARE_TEST_ETASK(01, etask_sup_l_01, NULL, NULL );\r
+DECLARE_TEST_BTASK(01, btask_sup_l_01, btask_sup_m_01, btask_sup_h_01);\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Tests:\r
+ *\r
+ * OSEK:\r
+ * - GetResource E_OS_ID, E_OS_ACCESS\r
+ * - ReleaseResource E_OS_ID, E_OS_ACCESS, E_OS_NOFUNC\r
+ *\r
+ * More tests here:\r
+ * - GetResource(RES_SCHEDULER)\r
+ * - Check the ceiling protocol\r
+ * - Linked resources\r
+ * - Nested allocation of the same resource is forbidden.\r
+ *\r
+ *\r
+ * Limitations:\r
+ * - Internal resources.\r
+ */\r
+\r
+#include "Os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+#include "irq.h"\r
+\r
+\r
+static int isr2RunCnt = 0;\r
+static int taskRunCnt = 0;\r
+\r
+static void isr2( void ) {\r
+ isr2RunCnt++;\r
+ ActivateTask(TASK_ID_btask_sup_m);\r
+#if 0\r
+ {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+ printf("ISR2: %d\n",task);\r
+ }\r
+#endif\r
+}\r
+\r
+static void isr1( void ) {\r
+\r
+}\r
+\r
+void etask_sup_l_02(void) {\r
+ _Bool done = 0;\r
+ StatusType rv;\r
+ TaskType isrTask;\r
+ TaskType task;\r
+\r
+ while (!done) {\r
+ TEST_RUN();\r
+ switch (test_nr) {\r
+ case 1:\r
+ rv = GetResource(RES_ID_std_prio_3);\r
+ TEST_ASSERT(rv == E_OK);\r
+ rv = ReleaseResource(RES_ID_std_prio_3);\r
+ TEST_ASSERT(rv == E_OK);\r
+ test_nr++;\r
+ break;\r
+ case 2:\r
+ /* Get the same resource twice */\r
+ rv = GetResource(RES_ID_std_prio_3);\r
+ TEST_ASSERT(rv == E_OK);\r
+ rv = GetResource(RES_ID_std_prio_3);\r
+ TEST_ASSERT(rv == E_OS_ACCESS);\r
+ test_nr = 10;\r
+ break;\r
+ case 10:\r
+ /* Test RES_SCHEDULER.\r
+ * Since GetResource(RES_SCHEDULER) only locks the\r
+ * scheduler (interrupts are still working) we the interrupt\r
+ * task should trigger a higher prio task, but that should\r
+ * not be swapped in.\r
+ */\r
+\r
+ /* Create an ISR2 */\r
+ isrTask = Os_Arc_CreateIsr( isr2, 4/*prio*/,"soft_0");\r
+ Irq_AttachIsr2(isrTask,NULL,INTC_SSCIR0_CLR0);\r
+ /* Create an ISR1 */\r
+ Irq_AttachIsr1(isr1,NULL,INTC_SSCIR0_CLR1,6);\r
+\r
+ GetTaskID(&task);\r
+ TEST_ASSERT( task == TASK_ID_etask_sup_l );\r
+ /* Lock the scheduler */\r
+ rv = GetResource(RES_SCHEDULER);\r
+ Irq_GenerateSoftInt( INTC_SSCIR0_CLR0 );\r
+\r
+ GetTaskID(&task);\r
+\r
+ TEST_ASSERT( task == TASK_ID_etask_sup_l );\r
+\r
+ /* TODO: Should we re-schedule here? */\r
+ rv = ReleaseResource(RES_SCHEDULER);\r
+ // TODO: ReleaseResource should re-schedule\r
+\r
+ TEST_ASSERT( task == TASK_ID_etask_sup_l );\r
+\r
+// TEST_ASSERT( taskRunCnt == 1 );\r
+ // TODO:\r
+\r
+ test_nr = 100;\r
+ break;\r
+ case 100:\r
+ TerminateTask();\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+void btask_sup_l_02(void) {\r
+}\r
+\r
+void btask_sup_m_02(void) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+\r
+ taskRunCnt++;\r
+ TEST_ASSERT( task == TASK_ID_btask_sup_m );\r
+}\r
+\r
+\r
+DECLARE_TEST_ETASK(02, etask_sup_l_02, NULL, NULL );\r
+DECLARE_TEST_BTASK(02, btask_sup_l_02, btask_sup_m_02, NULL );\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Tests:\r
+ *\r
+ * OSEK\r
+ * - GetAlarmBase E_OS_ID\r
+ * - GetAlarm E_OS_ID, E_OS_NOFUNC\r
+ * - SetRelAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE\r
+ * - SetAbsAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE\r
+ * - CancelAlarm E_OS_ID, E_OS_NOFUNC\r
+ *\r
+ * Autosar\r
+ * - IncrementCounter E_OS_ID\r
+ * - GetCounterValue E_OS_ID\r
+ * - GetElapsedCounterValue E_OS_ID, E_OS_VALUE\r
+ *\r
+ * More tests here:\r
+ *\r
+ * Limitations:\r
+ */\r
+\r
+\r
+#include "Os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+\r
+\r
+void etask_sup_l_03(void) {\r
+ _Bool done = 0;\r
+ StatusType rv;\r
+ AlarmBaseType alarmBase;\r
+ TickType tick;\r
+ TickType tickElapsed;\r
+\r
+ int i;\r
+\r
+ rv = ActivateTask(TASK_ID_etask_sup_m);\r
+ assert( rv == E_OK );\r
+\r
+ while (!done) {\r
+ TEST_RUN();\r
+ switch (test_nr) {\r
+ /*--------------------------------------------------------------------\r
+ * API tests\r
+ *--------------------------------------------------------------------\r
+ */
+ case 1:\r
+ /* GetAlarmBase E_OS_ID */\r
+ rv = GetAlarmBase(ALARM_ID_c_sys_activate_btask_h, &alarmBase);\r
+ TEST_ASSERT(rv == E_OK);\r
+ rv = GetAlarmBase(ALARM_ID_ILL, &alarmBase);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ test_nr++;\r
+ break;\r
+ case 2:\r
+ /* GetAlarm E_OS_ID and E_OS_NO_FUNC */\r
+ rv = GetAlarm(ALARM_ID_c_sys_activate_btask_h,&tick);\r
+ TEST_ASSERT(rv == E_OS_NOFUNC);\r
+ rv = GetAlarm(ALARM_ID_ILL,&tick);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ test_nr++;\r
+ break;\r
+ case 3:\r
+ /* SetRelAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE */\r
+ rv = SetRelAlarm(ALARM_ID_ILL,1,10);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,0,10);\r
+ TEST_ASSERT(rv == E_OS_VALUE);\r
+ rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
+ TEST_ASSERT(rv == E_OK);\r
+ rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
+ TEST_ASSERT(rv == E_OS_STATE);\r
+ rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
+ TEST_ASSERT(rv == E_OK);\r
+ test_nr++;\r
+ break;\r
+ case 4:\r
+ /* SetAbsAlarm E_OS_ID, E_OS_STATE, E_OS_VALUE */\r
+ rv = SetAbsAlarm(ALARM_ID_ILL,1,10);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,\r
+ OSMAXALLOWEDVALUE_soft_1 + 1, 10);\r
+ TEST_ASSERT(rv == E_OS_VALUE);\r
+ rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
+ TEST_ASSERT(rv == E_OK);\r
+ rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,1,10);\r
+ TEST_ASSERT(rv == E_OS_STATE);\r
+ rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
+ TEST_ASSERT(rv == E_OK);\r
+ test_nr++;\r
+ break;\r
+ case 5:\r
+ /* CancelAlarm E_OS_ID, E_OS_NOFUNC */\r
+ rv = CancelAlarm(ALARM_ID_ILL);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
+ TEST_ASSERT(rv == E_OS_NOFUNC);\r
+ test_nr++;\r
+ break;\r
+ case 6:\r
+ /* IncrementCounter E_OS_ID */\r
+ rv = IncrementCounter(COUNTER_ID_ILL);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ test_nr++;\r
+ break;\r
+ case 7:\r
+ /* GetCounterValue E_OS_ID */\r
+ rv = GetCounterValue(COUNTER_ID_ILL,&tick);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ test_nr++;\r
+ break;\r
+ case 8:\r
+ /* GetElapsedCounterValue E_OS_ID, E_OS_VALUE */\r
+ rv = GetElapsedCounterValue(COUNTER_ID_ILL,&tick,&tick);\r
+ TEST_ASSERT(rv == E_OS_ID);\r
+ test_nr = 10;\r
+ break;\r
+\r
+ /*--------------------------------------------------------------------\r
+ * Functional tests, Counters\r
+ *--------------------------------------------------------------------\r
+ * IncrementCounter\r
+ * GetCounterValue\r
+ * GetElapsedCounterValue\r
+ */\r
+ case 10:\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ TEST_ASSERT(rv == E_OK);\r
+ rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
+ TEST_ASSERT(rv == E_OK);\r
+ TEST_ASSERT(tick == 1);\r
+ rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
+ &tick,\r
+ &tickElapsed);\r
+ TEST_ASSERT(tick == 1);\r
+ TEST_ASSERT(tickElapsed == 0);\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ TEST_ASSERT(rv == E_OK);\r
+ rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
+ &tick,\r
+ &tickElapsed);\r
+ TEST_ASSERT(tick == 2);\r
+ TEST_ASSERT(tickElapsed == 1);\r
+\r
+ /* Test max value */\r
+ for( i=0; i< OSMAXALLOWEDVALUE_soft_1 - 2; i++ ) {\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ TEST_ASSERT(rv == E_OK);\r
+ }\r
+\r
+ rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
+ TEST_ASSERT(tick == OSMAXALLOWEDVALUE_soft_1);\r
+\r
+ tick = 0;\r
+ rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
+ &tick,\r
+ &tickElapsed);\r
+\r
+ TEST_ASSERT(tick == OSMAXALLOWEDVALUE_soft_1 );\r
+ TEST_ASSERT(tickElapsed == OSMAXALLOWEDVALUE_soft_1);\r
+\r
+ /* Check that wrapping calculation works */\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetElapsedCounterValue( COUNTER_ID_soft_1,\r
+ &tick,\r
+ &tickElapsed);\r
+\r
+ TEST_ASSERT(tick == 1);\r
+ TEST_ASSERT(tickElapsed == 2);\r
+\r
+ test_nr++;\r
+ break;\r
+\r
+ /*--------------------------------------------------------------------\r
+ * Functional tests, Alarm\r
+ *--------------------------------------------------------------------\r
+ * GetAlarmBase\r
+ * GetAlarm\r
+ * SetRelAlarm\r
+ * SetAbsAlarm\r
+ * CancelAlarm\r
+ */\r
+\r
+ case 11:\r
+ rv = GetAlarmBase(ALARM_ID_c_soft_1_setevent_etask_m, &alarmBase);\r
+ TEST_ASSERT(alarmBase.maxallowedvalue == OSMAXALLOWEDVALUE_soft_1 );\r
+ /* TODO: Fix this in the editor */\r
+ TEST_ASSERT(alarmBase.mincycle == 1 );\r
+ TEST_ASSERT(alarmBase.tickperbase == 1 );\r
+ test_nr++;\r
+ break;\r
+\r
+ case 12:\r
+ /* Test single-shot alarm */\r
+ rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 2 );\r
+\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 1 );\r
+\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OS_NOFUNC );\r
+ test_nr++;\r
+ break;\r
+ case 13:\r
+ /* Test cyclic alarm */\r
+ rv = SetRelAlarm(ALARM_ID_c_soft_1_setevent_etask_m,2,5);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 2 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 1 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 5 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT(tick == 4 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT(tick == 1 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 5 );\r
+\r
+ rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
+ TEST_ASSERT( rv == E_OK );\r
+ test_nr++;\r
+ break;\r
+ case 14:\r
+ /*\r
+ * SetAbsAlarm\r
+ */\r
+\r
+ /* Start from 0 */\r
+ rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
+ for(i=0;i<OSMAXALLOWEDVALUE_soft_1 - tick + 1 ;i++) {\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+ }\r
+\r
+ rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
+ TEST_ASSERT(tick == 0);\r
+\r
+ /* Test single-shot alarm */\r
+ rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,2,0);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 2 );\r
+\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 1 );\r
+\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OS_NOFUNC );\r
+ test_nr++;\r
+ break;\r
+ case 15:\r
+\r
+ /* Start from 1 */\r
+ rv = GetCounterValue(COUNTER_ID_soft_1,&tick);\r
+ for(i=0;i<OSMAXALLOWEDVALUE_soft_1 - tick + 1 ;i++) {\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+ }\r
+ IncrementCounter(COUNTER_ID_soft_1);\r
+\r
+ /* Test cyclic alarm */\r
+ rv = SetAbsAlarm(ALARM_ID_c_soft_1_setevent_etask_m,3,5);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 2 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 1 );\r
+\r
+ /* Trigger the alarm */\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ /* The abs alarm is now a relative alarm cith cycle */\r
+ TEST_ASSERT(tick == 5 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT(tick == 4 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT(tick == 1 );\r
+\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ TEST_ASSERT( rv == E_OK );\r
+ rv = GetAlarm(ALARM_ID_c_soft_1_setevent_etask_m,&tick);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(tick == 5 );\r
+\r
+ rv = CancelAlarm(ALARM_ID_c_soft_1_setevent_etask_m);\r
+ TEST_ASSERT( rv == E_OK );\r
+ test_nr++;\r
+ break;\r
+ case 16:\r
+ test_nr = 100;\r
+ break;\r
+ case 100:\r
+ SetEvent(TASK_ID_etask_sup_m, EVENT_MASK_KILL);\r
+ TerminateTask();\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+void etask_sup_m_03(void) {\r
+\r
+ for(;;) {\r
+\r
+ WaitEvent(EVENT_MASK_NOTIF | EVENT_MASK_KILL );\r
+ switch (test_nr) {\r
+ case 12:\r
+ case 13:\r
+ case 14:\r
+ case 15:\r
+ ClearEvent(EVENT_MASK_NOTIF);\r
+ break;\r
+ case 100:\r
+ TerminateTask();\r
+ break;\r
+ default:\r
+ assert(0);\r
+ }\r
+ }\r
+\r
+}\r
+\r
+void btask_sup_l_03(void) {\r
+}\r
+\r
+\r
+DECLARE_TEST_ETASK(03, etask_sup_l_03, etask_sup_m_03, NULL );\r
+DECLARE_TEST_BTASK(03, btask_sup_l_03, NULL, NULL );\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * From Autosar 3.1\r
+ *\r
+ * Tests:\r
+ * - StartScheduleTableRel E_OS_ID, E_OS_VALUE, E_OS_STATE\r
+ * - StartScheduleTableAbs E_OS_ID, E_OS_VALUE, E_OS_STATE\r
+ * - StopScheduleTable E_OS_ID, E_OS_NO_FUNC\r
+ * - NextScheduleTable E_OS_ID, E_OS_NO_FUNC, E_OS_STATE\r
+ * - GetScheduleTableStatus E_OS_ID,\r
+ *\r
+ * Class 2 and 4\r
+ * - StartScheduleTableSynchrone E_OS_ID, E_OS_STATE\r
+ * - SyncScheduleTable E_OS_ID, E_OS_VALUE, E_OS_STATE\r
+ * - SetScheduleTableAsync E_OS_ID,\r
+ *\r
+ * More tests here:\r
+ *\r
+ * Limitations:\r
+ */\r
+\r
+#include "Os.h"\r
+#include "test_framework.h"\r
+#include "arc.h"\r
+\r
+\r
+static int subTest = 0;\r
+\r
+void etask_sup_l_04(void) {\r
+ _Bool done = 0;\r
+ StatusType rv;\r
+ ScheduleTableStatusType status;\r
+\r
+ while (!done) {\r
+ TEST_RUN();\r
+ switch (test_nr) {\r
+ case 1:\r
+ /* StartScheduleTableRel E_OS_ID, E_OS_VALUE, E_OS_STATE */\r
+ rv = StartScheduleTableRel(SCHTBL_ID_ILL,1);\r
+ TEST_ASSERT(rv==E_OS_ID);\r
+ rv = StartScheduleTableRel(SCHTBL_ID_0,0);\r
+ TEST_ASSERT(rv==E_OS_VALUE);\r
+ rv = StartScheduleTableRel(SCHTBL_ID_0,1);\r
+ TEST_ASSERT(rv==E_OK);\r
+ rv = StartScheduleTableRel(SCHTBL_ID_0,1);\r
+ TEST_ASSERT(rv==E_OS_STATE);\r
+ rv = StopScheduleTable(SCHTBL_ID_0);\r
+ test_nr++;\r
+ break;\r
+ case 2:\r
+ /* StartScheduleTableAbs E_OS_ID, E_OS_VALUE, E_OS_STATE */\r
+ rv = StartScheduleTableAbs(SCHTBL_ID_ILL,1);\r
+ TEST_ASSERT(rv==E_OS_ID);\r
+#if 0\r
+ /* TODO:Must supply an offset bigger than OsCounterMaxAllowedValue */\r
+ StartScheduleTableAbs(SCHTBL_ID_0,0);\r
+ TEST_ASSERT(rv==E_OS_VALUE);\r
+#endif\r
+ rv = StartScheduleTableAbs(SCHTBL_ID_0,1);\r
+ TEST_ASSERT(rv==E_OK);\r
+ rv = StartScheduleTableAbs(SCHTBL_ID_0,1);\r
+ TEST_ASSERT(rv==E_OS_STATE);\r
+ rv = StopScheduleTable(SCHTBL_ID_0);\r
+ test_nr++;\r
+ break;\r
+ case 3:\r
+ /* StopScheduleTable E_OS_ID, E_OS_NO_FUNC */\r
+ rv = StopScheduleTable(SCHTBL_ID_ILL);\r
+ TEST_ASSERT(rv==E_OS_ID);\r
+ rv = StopScheduleTable(SCHTBL_ID_0);\r
+ TEST_ASSERT(rv==E_OS_NOFUNC);\r
+ test_nr++;\r
+ break;\r
+ case 4:\r
+ /* NextScheduleTable E_OS_ID, E_OS_NO_FUNC, E_OS_STATE */\r
+ rv = NextScheduleTable(SCHTBL_ID_ILL, SCHTBL_ID_ILL);\r
+ TEST_ASSERT(rv==E_OS_ID);\r
+ rv = NextScheduleTable(SCHTBL_ID_ILL, SCHTBL_ID_0);\r
+ TEST_ASSERT(rv==E_OS_ID);\r
+ rv = NextScheduleTable(SCHTBL_ID_0, SCHTBL_ID_ILL);\r
+ TEST_ASSERT(rv==E_OS_ID);\r
+\r
+ rv = NextScheduleTable(SCHTBL_ID_0,SCHTBL_ID_0);\r
+ TEST_ASSERT(rv==E_OS_NOFUNC);\r
+\r
+ rv = StartScheduleTableRel(SCHTBL_ID_0,1);\r
+ rv = StartScheduleTableRel(SCHTBL_ID_1,1);\r
+ rv = NextScheduleTable(SCHTBL_ID_0,SCHTBL_ID_1);\r
+ TEST_ASSERT(rv==E_OS_STATE);\r
+\r
+ /* Cleanup */\r
+ rv = StopScheduleTable(SCHTBL_ID_0);\r
+ TEST_ASSERT(rv==E_OK);\r
+ rv = StopScheduleTable(SCHTBL_ID_1);\r
+ TEST_ASSERT(rv==E_OK);\r
+ test_nr = 10;\r
+ break;\r
+ /*--------------------------------------------------------------------\r
+ * Functional tests, ScheduleTables\r
+ *--------------------------------------------------------------------\r
+ * - StartScheduleTableRel\r
+ * - StartScheduleTableAbs\r
+ * - StopScheduleTable\r
+ * - NextScheduleTable\r
+ * - GetScheduleTableStatus\r
+ */\r
+ case 10:\r
+ subTest = 0;\r
+ rv = ActivateTask(TASK_ID_etask_sup_m);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
+ rv = StartScheduleTableRel(SCHTBL_ID_0,2);\r
+ TEST_ASSERT(rv==E_OK);\r
+\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
+\r
+ /* 2+ 5 */\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ subTest = 5;\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+\r
+ /* 2 more for next*/\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ subTest = 7;\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+\r
+ /* 4 more for next*/\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ subTest = 11;\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
+\r
+ /* and the final offset */\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
+\r
+ /* First offset, again. */\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+\r
+ /* TODO: More here */\r
+\r
+ test_nr = 100;\r
+ break;\r
+\r
+\r
+#if 0 /* Working single shot case */\r
+ case 10:\r
+ subTest = 0;\r
+ rv = ActivateTask(TASK_ID_etask_sup_m);\r
+ TEST_ASSERT( rv == E_OK );\r
+\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
+ rv = StartScheduleTableRel(SCHTBL_ID_0,2);\r
+ TEST_ASSERT(rv==E_OK);\r
+\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
+\r
+ /* 2+ 5 */\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ subTest = 5;\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+\r
+ /* 2 more for next*/\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ subTest = 7;\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+\r
+ /* 4 more for next*/\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ subTest = 11;\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_RUNNING );\r
+\r
+ /* and the final offset */\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = IncrementCounter(COUNTER_ID_soft_1);\r
+ rv = GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
+ TEST_ASSERT(rv==E_OK);\r
+ TEST_ASSERT( status == SCHEDULETABLE_STOPPED );\r
+ test_nr = 100;\r
+\r
+ break;\r
+#endif\r
+\r
+\r
+ case 100:\r
+ rv = SetEvent(TASK_ID_etask_sup_m, EVENT_MASK_KILL);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TerminateTask();\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+void etask_sup_m_04(void) {\r
+\r
+ TaskType currTask;\r
+ EventMaskType eventMask;\r
+ GetTaskID(&currTask);\r
+ StatusType rv;\r
+\r
+ for(;;) {\r
+ WaitEvent(EVENT_MASK_NOTIF | EVENT_MASK_KILL );\r
+ switch(test_nr) {\r
+ case 10:\r
+ switch(subTest) {\r
+ case 7:\r
+ case 11:\r
+ printf("etask\n");\r
+ rv = GetEvent(currTask,&eventMask);\r
+ TEST_ASSERT( rv == E_OK );\r
+ TEST_ASSERT(eventMask == EVENT_MASK_NOTIF );\r
+ ClearEvent(EVENT_MASK_NOTIF);\r
+ break;\r
+\r
+ default:\r
+ TEST_ASSERT(0);\r
+ break;\r
+\r
+ }\r
+ break;\r
+ case 100:\r
+ rv = TerminateTask();\r
+ TEST_ASSERT( rv == E_OK );\r
+ break;\r
+\r
+ default:\r
+ TEST_ASSERT(0);\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+\r
+void btask_sup_l_04(void) {\r
+\r
+\r
+\r
+}\r
+\r
+void btask_sup_m_04(void) {\r
+\r
+ switch(test_nr) {\r
+ case 10:\r
+ switch(subTest) {\r
+ case 5:\r
+ case 11:\r
+ printf("btask\n");\r
+ break;\r
+\r
+ default:\r
+ TEST_ASSERT(0);\r
+ break;\r
+ }\r
+\r
+ break;\r
+ }\r
+\r
+}\r
+\r
+\r
+DECLARE_TEST_ETASK(04, etask_sup_l_04, etask_sup_m_04, NULL );\r
+DECLARE_TEST_BTASK(04, btask_sup_l_04, btask_sup_m_04, NULL );\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Tests:\r
+ *\r
+ * OSEK constants\r
+ * - OSMAXALLOWEDVALUE_x\r
+ * - OSTICKSPERBASE_x\r
+ * - OSMINCYCLE_x\r
+ * - OSMAXALLOWEDVALUE\r
+ * - OSTICKSPERBASE\r
+ * - OSMINCYCLE\r
+ * - OSTICKDURATION\r
+ *\r
+ * - INVALID_TASK\r
+ *\r
+ * - OSDEFAULTAPPMODE\r
+ *\r
+ * - OSServiceId_xx\r
+ * - OSErrorGetServiceId\r
+ * - OSError_x1_x2\r
+ *\r
+ * Autosar constants\r
+ *\r
+ * More tests here:\r
+ *\r
+ * Limitations:\r
+ */\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Tests:\r
+ * Ramlog\r
+ *\r
+ * Limitations:\r
+ */\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+/*\r
+ * Tests:\r
+ *\r
+ * OSEK\r
+ * - DisableAllInterrupts\r
+ * - EnableAllInterrupts\r
+ * - SuspendAllInterrupts\r
+ * - ResumeAllInterrupts\r
+ * - SuspendOSInterrupts\r
+ * - ResumeOSInterrupts\r
+ *\r
+ * - GetActiveApplicationMode\r
+ * - StartOS\r
+ * - ShutdownOS\r
+ *\r
+ *\r
+ * Autosar\r
+ *\r
+ * Class 3 and 4\r
+ * - GetApplicationID\r
+ * - GetISRID IVALID_ISR\r
+ * - CallTrustedFunction ...\r
+ * - CheckISRMemoryAccess ...\r
+ * - CheckTaskMemoryAccess\r
+ * - CheckObjectMemoryAccess\r
+ * - CheckObjectOwnership\r
+ * - TerminateApplication\r
+ *\r
+ * Autosar additional tests:\r
+ *\r
+ * Class 2,3,4\r
+ * - ProtectionHook\r
+ *\r
+ * Class 2,4\r
+ * - Timing Protection\r
+ * - Global Time\r
+ *\r
+ * Class 3,4\r
+ * - Memory Protection\r
+ * - Os-Applications\r
+ * - Service Protection\r
+ * - Call trusted function\r
+ *\r
+ * Limitations:\r
+ */\r
+\r
+void intTest( void ) {\r
+\r
+ /* Just call them to its works */\r
+ DisableAllInterrupts();\r
+ EnableAllInterrupts();\r
+\r
+ SuspendAllInterrupts();\r
+ ResumeAllInterrupts();\r
+\r
+ SuspendOSInterrupts();\r
+ ResumeOSInterrupts();\r
+\r
+ /** @req OS092 */\r
+ /* We should be able to call them and they should be ignored */\r
+ EnableAllInterrupts();\r
+ EnableAllInterrupts();\r
+\r
+ ResumeAllInterrupts();\r
+ ResumeAllInterrupts();\r
+\r
+ ResumeOSInterrupts();\r
+ ResumeOSInterrupts();\r
+\r
+ /* No nesting for DisableAllInterrupts() and EnableAllInterrupts */\r
+ DisableAllInterrupts();\r
+ /* No calls allowed here */\r
+ EnableAllInterrupts();\r
+\r
+ /* Nesting allowed for these calls */\r
+ SuspendAllInterrupts();\r
+ SuspendAllInterrupts();\r
+ SuspendOSInterrupts();\r
+ ResumeOSInterrupts();\r
+ ResumeAllInterrupts();\r
+ ResumeAllInterrupts();\r
+\r
+ /* MORE MORE */\r
+\r
+}\r
+\r
+\r
+\r
+\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-/* CONFIGURATION\r
- * - The "etask_master" should be the only autostarted task.\r
- * - It can hold at most 3 extended task and 3 basic tasks. They must be called\r
- * etask_sup_l, etask_sup_m, etask_sup_h,\r
- * btask_sup_l, btask_sup_m, btask_sup_h\r
- */\r
-\r
-\r
-\r
-\r
-\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/* CONFIGURATION
+ * - The "etask_master" should be the only autostarted task.
+ * - It can hold at most 3 extended task and 3 basic tasks. They must be called
+ * etask_sup_l, etask_sup_m, etask_sup_h,
+ * btask_sup_l, btask_sup_m, btask_sup_h
+ */
+
+
+
+
+
#include <stdlib.h>\r
#include "Os.h"\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "Mcu.h"\r
#if defined(USE_GPT)\r
#include "Gpt.h"\r
#endif\r
-\r
+
\r
//#define USE_LDEBUG_PRINTF\r
-#include "debug.h"\r
+#include "debug.h"
#include "arc.h"\r
\r
\r
{\r
/* 01*/ TASK_ID_etask_sup_l,\r
/* 02*/ TASK_ID_etask_sup_l,\r
-/* 03*/ TASK_ID_etask_sup_l,\r
+/* 03*/ TASK_ID_etask_sup_l,
/* 04*/ TASK_ID_etask_sup_l,\r
};\r
\r
{\r
test_nr = 1;\r
printf("-----> Test Suite %02d\n",test_suite);\r
- pid = test_activate_pid_list[test_case];\r
- ActivateTask(pid);\r
- /* We are lowest prio task in the system (apart from idle) so\r
- * all tasks in the test are now terminated...\r
+ pid = test_activate_pid_list[test_case];
+ ActivateTask(pid);
+ /* We are lowest prio task in the system (apart from idle) so
+ * all tasks in the test are now terminated...
*/\r
test_suite++;\r
}\r
-\r
- test_done();\r
-\r
- // Test complete..\r
- while(1);\r
-\r
+
+ // Test complete..
+ TestExit(0);
}\r
-\r
-extern test_func_t etask_sup_matrix[][3];\r
+
+extern test_func_t etask_sup_matrix[][3];
extern test_func_t btask_sup_matrix[][3];\r
\r
//--------------------------------------------------------------------\r
void StartupHook( void ) {\r
// LDEBUG_PRINTF("## StartupHook\n");\r
\r
-#ifdef USE_MCU\r
- uint32_t sys_freq = McuE_GetSystemClock();\r
+#ifdef USE_MCU
+ uint32_t sys_freq = McuE_GetSystemClock();
(void)sys_freq;\r
LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
#endif\r
\r
void ShutdownHook( StatusType Error ) {\r
LDEBUG_PRINTF("## ShutdownHook\n");\r
- const char *err;\r
- err = Arc_StatusToString(Error);\r
- while(1) {\r
- err = err;\r
- }\r
+ const char *err;
+ err = Arc_StatusToString(Error);
+ while(1) {
+ err = err;
+ }
}\r
\r
void ErrorHook( StatusType Error ) {\r
- LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);\r
- const char *err;\r
- err = Arc_StatusToString(Error);\r
-// while(1);\r
+ LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);
+ const char *err;
+ err = Arc_StatusToString(Error);
+// while(1);
}\r
\r
void PreTaskHook( void ) {\r
while(1);\r
}\r
\r
- LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
+ LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);
#if 0\r
{\r
StackInfoType si;\r
Os_Arc_GetStackInfo(task,&si);\r
// LDEBUG_PRINTF("Stack usage %d%% (this=%08x, top=%08x, size=%08x,usage=%08x )\n",OS_STACK_USAGE(&si),si.curr, si.top,si.size,si.usage);\r
- }\r
+ }
#endif\r
}\r
\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue Jun 08 08:23:43 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+ GEN_COUNTER( COUNTER_ID_Counter2,\r
+ "Counter2",\r
+ COUNTER_TYPE_SOFT,\r
+ COUNTER_UNIT_NANO,\r
+ 65535,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm1, ALARM_AUTOSTART_ABSOLUTE, 1, 0, OSDEFAULTAPPMODE );\r
+ \r
+GEN_ALARM_AUTOSTART(ALARM_ID_Alarm2, ALARM_AUTOSTART_ABSOLUTE, 1, 0, OSDEFAULTAPPMODE );\r
+ \r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_Counter2,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm1),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_master,\r
+ EVENT_MASK_Alarm_1,\r
+ NULL ),\r
+ GEN_ALARM( ALARM_ID_Alarm2,\r
+ "Alarm2",\r
+ COUNTER_ID_Counter2,\r
+ GEN_ALARM_AUTOSTART_NAME(ALARM_ID_Alarm2),\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_master,\r
+ EVENT_MASK_Alarm_2,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_2,2048);\r
+DECLARE_STACK(btask_4,2048);\r
+DECLARE_STACK(etask_3,2048);\r
+DECLARE_STACK(etask_5,2048);\r
+DECLARE_STACK(etask_master,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_ETASK(\r
+ btask_2,\r
+ 2,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_BTASK(\r
+ btask_4,\r
+ 4,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_3,\r
+ 3,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_5,\r
+ 5,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_master,\r
+ 10,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table data ScheduleTable_1\r
+\r
+\r
+GEN_SCHTBL_EVENT_LIST_HEAD( 0, 0 ) {\r
+ \r
+ { \r
+ EVENT_MASK_SchTbl_1, \r
+ TASK_ID_etask_master \r
+ },\r
+ \r
+};\r
+\r
+\r
+GEN_SCHTBL_EXPIRY_POINT_HEAD( 0 ) {\r
+ GEN_SCHTBL_EXPIRY_POINT_W_EVENT(0, 0),
+ \r
+};\r
+\r
+GEN_SCHTBL_AUTOSTART(\r
+ 0,\r
+ SCHTBL_AUTOSTART_ABSOLUTE,\r
+ 1, \r
+ OSDEFAULTAPPMODE\r
+);\r
+\r
+// Table data ScheduleTable_2\r
+\r
+\r
+GEN_SCHTBL_EVENT_LIST_HEAD( 1, 0 ) {\r
+ \r
+ { \r
+ EVENT_MASK_SchTbl_2, \r
+ TASK_ID_etask_master \r
+ },\r
+ \r
+};\r
+\r
+\r
+GEN_SCHTBL_EXPIRY_POINT_HEAD( 1 ) {\r
+ GEN_SCHTBL_EXPIRY_POINT_W_EVENT(1, 0),
+ \r
+};\r
+\r
+GEN_SCHTBL_AUTOSTART(\r
+ 1,\r
+ SCHTBL_AUTOSTART_ABSOLUTE,\r
+ 1, \r
+ OSDEFAULTAPPMODE\r
+);\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+ GEN_SCHEDULETABLE(\r
+ 0,\r
+ "ScheduleTable_1",\r
+ COUNTER_ID_Counter2,\r
+ SINGLE_SHOT,\r
+ 10,\r
+ GEN_SCHTBL_AUTOSTART_NAME(0)\r
+ ),\r
+ GEN_SCHEDULETABLE(\r
+ 1,\r
+ "ScheduleTable_2",\r
+ COUNTER_ID_Counter2,\r
+ SINGLE_SHOT,\r
+ 10,\r
+ GEN_SCHTBL_AUTOSTART_NAME(1)\r
+ ),\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Tue Jun 08 08:23:43 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+#define ALARM_ID_Alarm2 1\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+#define COUNTER_ID_Counter2 1\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+#define OSMAXALLOWEDVALUE_Counter2 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_Alarm_1 1\r
+#define EVENT_MASK_Alarm_2 2\r
+#define EVENT_MASK_Event1 1\r
+#define EVENT_MASK_SchTbl_1 4\r
+#define EVENT_MASK_SchTbl_2 8\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_2 1\r
+#define TASK_ID_btask_4 2\r
+#define TASK_ID_etask_3 3\r
+#define TASK_ID_etask_5 4\r
+#define TASK_ID_etask_master 5\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_2( void );\r
+void btask_4( void );\r
+void etask_3( void );\r
+void etask_5( void );\r
+void etask_master( void );\r
+\r
+// Schedule table id's\r
+#define SCHTBL_ID_ScheduleTable_1 0\r
+#define SCHTBL_ID_ScheduleTable_2 1\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 2 \r
+#define OS_TASK_CNT 6\r
+#define OS_SCHTBL_CNT 2\r
+#define OS_COUNTER_CNT 2\r
+#define OS_EVENTS_CNT 5\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE UUID="c33d4e0c-6dad-411a-a350-aabadc4bf0df">\r
+ <SHORT-NAME>suite_02</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="8461e526-eb23-49f1-a321-0a64a6bce731">\r
+ <SHORT-NAME>suite_02</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/suite_02</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/suite_02/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="6656fb2b-da0c-4674-b652-35cfbbeb8858">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
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+ <CONTAINER UUID="b236cee5-5b51-4b4b-a93c-2eb78964d7ff">\r
+ <SHORT-NAME>btask_4</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="4733a77a-c470-4529-a9ae-00c242bbe251">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7e97f4aa-e766-48f0-8cbd-29357df062e3">\r
+ <SHORT-NAME>etask_3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="b71f84b9-4f48-40f3-a6c3-02e2aabb7dcf">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="13e11cb6-2ea8-45df-aca8-5b2c785a419e">\r
+ <SHORT-NAME>etask_5</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>5</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a471975b-1543-41a5-a56c-25affcc0878b">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f8e58cab-67b1-4e2b-a825-ceb98bb85743">\r
+ <SHORT-NAME>etask_master</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>10</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="38d4c454-e3dd-47b5-8a01-a0aee062e796">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="af762c17-2f49-46c2-a380-763ba5b9be79">\r
+ <SHORT-NAME>Alarm_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="4d562e94-c082-4513-a946-71331d918a2f">\r
+ <SHORT-NAME>Alarm_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9ad1eb87-cc43-4fc3-a390-c7839f5cb55f">\r
+ <SHORT-NAME>SchTbl_1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="11c5b9c1-3eb2-4f06-a490-d75d001a72c5">\r
+ <SHORT-NAME>SchTbl_2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+obj-y+= arc.o\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_master.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+/* Tests
+ * Autostart bananza..
+ * 1. Autostart of tasks
+ * 2. Autostart of alarms
+ * 3. Autostart of scheduletables.
+ */
+
+
+
+
+
+#include <stdlib.h>\r
+#include "Os.h"\r
+#include "test_framework.h"\r
+#include "Mcu.h"\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+
+\r
+//#define USE_LDEBUG_PRINTF\r
+#include "debug.h"
+#include "arc.h"\r
+#include "test_framework.h"
+\r
+\r
+#define ERROR_LOG_SIZE 1
+
+typedef struct ErrorEntry {
+ StatusType error;
+ OsErrorType info;
+ TaskType taskId;
+ OsServiceIdType serviceId;
+} ErrorEntryType;
+
+
+typedef struct ErrorLog {
+ int index;
+ ErrorEntryType log[ERROR_LOG_SIZE];
+} ErrorLogType;
+
+ErrorLogType ErrorLog;
+
+ErrorEntryType *errorLogGetEntry( int backlog ) {
+
+
+ int index = ErrorLog.index - backlog;
+
+ if( index < 0 ) {
+ index = ERROR_LOG_SIZE + index;
+ }
+ return &ErrorLog.log[index];
+}
+
+
+static _Bool started[OS_TASK_CNT];
+
+static TaskType prioList[OS_TASK_CNT] = {
+ TASK_ID_etask_master,
+ TASK_ID_etask_5,
+ TASK_ID_btask_4,
+ TASK_ID_etask_3,
+ TASK_ID_btask_2,
+ TASK_ID_OsIdle };
+
+static void setStarted( void ) {
+ TaskType taskId;
+ GetTaskID(&taskId);
+ for(int i=0;i<OS_TASK_CNT;i++) {
+ if( prioList[i] == taskId ) {
+ started[i] ^= 1;
+ break;
+ }
+ }
+}
+
+static _Bool checkStarted( void ) {
+ TaskType taskId;
+ _Bool after = 0;
+
+ GetTaskID(&taskId);
+
+ for(int i=0;i<OS_TASK_CNT;i++) {
+
+ if( after) {
+ if( started[i] == 1 ) {
+ return 0;
+ }
+ } else {
+ if( started[i] == 0 ) {
+ return 0;
+ }
+ }
+
+ // Should be less priority until we hit it.
+ if( prioList[i] == taskId ) {
+ after = 1;
+ }
+
+ }
+ return 1;
+}
+
+
+
+
+
+void validateErrorHook(int backlog, int error, int serviceId,
+ uint32_t param1, uint32_t param2, uint32_t param3,
+ int apiId, int modId ) {
+ ErrorEntryType *entry = errorLogGetEntry(backlog);
+ TEST_ASSERT( error == entry->error );
+ if(param1 != TEST_VALUE_NC ) {
+ TEST_ASSERT(param1 == entry->info.param1 );
+ }
+ if(param2 != TEST_VALUE_NC ) {
+ TEST_ASSERT(param2 == entry->info.param2 );
+ }
+ if(param2 != TEST_VALUE_NC ) {
+ TEST_ASSERT(param3 == entry->info.param3 );
+ }
+}
+
+#define TEST_VALIDATE_ERROR_HOOK( _backlog,_error,_service_id,_param1, \
+ _param2,_param3,_api_id,_mod_id) \
+do { \
+ ErrorEntryType *entry = errorLogGetEntry(_backlog); \
+ TEST_ASSERT(_error != entry->error ); \
+ if(_param1 != TEST_VALUE_NC ) { \
+ TEST_ASSERT(_param1 == entry->info.param1 ); \
+ } \
+ if(_param2 != TEST_VALUE_NC ) { \
+ TEST_ASSERT(_param2 == entry->info.param2 ); \
+ } \
+ if(_param2 != TEST_VALUE_NC ) { \
+ TEST_ASSERT(_param3 == entry->info.param3 ); \
+ } \
+} while(0)
+\r
+/*\r
+ * Master test process, everything is controlled from here.\r
+ */\r
+void etask_master( void ) {
+ StatusType rv;
+ uint32_t mask;
+ TEST_INIT();
+
+ TEST_START("Autostart, priority tasks",test_nr);
+ setStarted();
+ TEST_ASSERT(checkStarted());
+ WaitEvent(EVENT_MASK_Event1);
+ ClearEvent(EVENT_MASK_Event1);
+
+ TEST_NEXT("Autostart, Alarms and Scheduletables",++test_nr);
+
+
+ /* Autostart
+ * SetRelAlarm Increment: Must != 0
+ * SetAbsAlarm No limit
+ * StartScheduleTableAbs
+ * ..
+ * ...
+ *
+ */
+
+
+ rv = IncrementCounter(COUNTER_ID_Counter2);
+
+#if 0
+ validateErrorHook( 0, /* backlog */
+ E_OS_LIMIT, /* error */
+ OSServiceId_ActivateTask, /* Service Id */
+ COUNTER_ID_Counter2, /* param1 */
+ TEST_VALUE_NC, /* param2 */
+ TEST_VALUE_NC, /* param3 */
+ TEST_VALUE_NC, /* API id */
+ TEST_VALUE_NC ); /* Module id */
+#endif
+
+ validateErrorHook( 0,0,0,0, /* backlog */
+ TEST_VALUE_NC, /* param2 */
+ TEST_VALUE_NC, /* param3 */
+ TEST_VALUE_NC, /* API id */
+ TEST_VALUE_NC ); /* Module id */
+
+ mask = EVENT_MASK_Alarm_1 | EVENT_MASK_Alarm_2 | EVENT_MASK_SchTbl_1 | EVENT_MASK_SchTbl_2;
+ WaitEvent( mask );
+
+ TaskType currTask;
+ EventMaskType evMask;
+
+ GetTaskID(&currTask);
+ GetEvent(currTask,&evMask);
+ TEST_ASSERT( evMask == mask);
+
+ TestExit(0);
+}\r
+
+//--------------------------------------------------------------------\r
+\r
+void etask_3( void )\r
+{
+ setStarted();
+ TEST_ASSERT(checkStarted());\r
+ TerminateTask();\r
+}\r
+\r
+void etask_5( void )\r
+{
+ setStarted();
+ TEST_ASSERT(checkStarted());\r
+ TerminateTask();\r
+}\r
+\r
+\r
+//--------------------------------------------------------------------\r
+\r
+void btask_2( void ) {\r
+ setStarted();
+ TEST_ASSERT(checkStarted());
+ TerminateTask();
+}\r
+
+void btask_4( void ) {\r
+ setStarted();
+ TEST_ASSERT(checkStarted());
+ TerminateTask();
+}\r
+\r
+void OsIdle(void ) {
+ setStarted();
+ TEST_ASSERT(checkStarted());
+ SetEvent(TASK_ID_etask_master, EVENT_MASK_Event1);
+ for(;;);\r
+}\r
+\r
+\r
+/* Global hooks */\r
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
+ printf("## ProtectionHook\n");\r
+ return PRO_KILLAPPL;\r
+}\r
+\r
+void StartupHook( void ) {\r
+// LDEBUG_PRINTF("## StartupHook\n");\r
+\r
+#ifdef USE_MCU
+ uint32_t sys_freq = McuE_GetSystemClock();
+ (void)sys_freq;\r
+ LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
+#endif\r
+}\r
+\r
+void ShutdownHook( StatusType Error ) {\r
+ LDEBUG_PRINTF("## ShutdownHook\n");\r
+ const char *err;
+ err = Arc_StatusToString(Error);
+ while(1) {
+ err = err;
+ }
+}\r
+
+
+void ErrorHook( StatusType error ) {
+
+ TaskType task;
+ ErrorEntryType *errEntry;
+
+ GetTaskID(&task);
+
+ OsServiceIdType service = OSErrorGetServiceId();
+
+ /* Grab the arguments to the functions
+ * This is the standard way, see 11.2 in OSEK spec
+ */
+#if 0
+ switch(service) {
+ case OSServiceId_SetRelAlarm:
+ {
+ // Read the arguments to the faulty functions...
+ AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;
+ TickType increment = OSError_SetRelAlarm_Increment;
+ TickType cycle = OSError_SetRelAlarm_Cycle;
+ (void)alarm_id;
+ (void)increment;
+ (void)cycle;
+
+ // ... Handle this some way.
+ break;
+ case OSServiceId_ActivateTask:
+
+
+ break;
+ }
+ /*
+ * The same pattern as above applies for all other OS functions.
+ * See Os.h for names and definitions.
+ */
+
+ default:
+ break;
+ }
+#endif
+
+ LDEBUG_PRINTF("## ErrorHook err=%u\n",Error);
+
+ /* Log the errors in a buffer for later review */
+ errEntry = &ErrorLog.log[ErrorLog.index];
+
+ errEntry->info.param1 = os_error.param1;
+ errEntry->info.param2 = os_error.param2;
+ errEntry->info.param3 = os_error.param3;
+ errEntry->info.serviceId = service;
+ errEntry->taskId = task;
+ errEntry->error = error;
+ ErrorLog.index = (ErrorLog.index + 1) % ERROR_LOG_SIZE ;
+}
+
+#if 0\r
+void ErrorHook( StatusType Error ) {
+
+ LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);
+ const char *err;
+ err = Arc_StatusToString(Error);
+// while(1);
+}\r
+#endif
+\r
+void PreTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+ if( task > 10 ) {\r
+ while(1);\r
+ }\r
+ LDEBUG_PRINTF("## PreTaskHook, taskid=%d\n",task);\r
+}\r
+\r
+void PostTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+ if( task > 10 ) {\r
+ while(1);\r
+ }\r
+\r
+ LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);
+#if 0\r
+ {\r
+ StackInfoType si;\r
+ Os_Arc_GetStackInfo(task,&si);\r
+// LDEBUG_PRINTF("Stack usage %d%% (this=%08x, top=%08x, size=%08x,usage=%08x )\n",OS_STACK_USAGE(&si),si.curr, si.top,si.size,si.usage);\r
+ }
+#endif\r
+}\r
+\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Jul 04 17:25:57 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_h_full,2048);\r
+DECLARE_STACK(btask_h_non,2048);\r
+DECLARE_STACK(btask_l_full,2048);\r
+DECLARE_STACK(btask_l_non,2048);\r
+DECLARE_STACK(btask_m_full,2048);\r
+DECLARE_STACK(btask_m_non,2048);\r
+DECLARE_STACK(etask_h_full,2048);\r
+DECLARE_STACK(etask_h_non,2048);\r
+DECLARE_STACK(etask_l_full,2048);\r
+DECLARE_STACK(etask_l_non,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+DECLARE_STACK(etask_m_non,2048);\r
+DECLARE_STACK(etask_master,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_h_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_h_non,\r
+ 4,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_full,\r
+ 2,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_non,\r
+ 2,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_full,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_h_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_h_non,\r
+ 4,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_full,\r
+ 2,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_non,\r
+ 2,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 3,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_master,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Jul 04 17:25:57 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_kill 8\r
+#define EVENT_MASK_master_notif 1\r
+#define EVENT_MASK_next 16\r
+#define EVENT_MASK_notif 2\r
+#define EVENT_MASK_test 4\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_h_full 1\r
+#define TASK_ID_btask_h_non 2\r
+#define TASK_ID_btask_l_full 3\r
+#define TASK_ID_btask_l_non 4\r
+#define TASK_ID_btask_m_full 5\r
+#define TASK_ID_btask_m_non 6\r
+#define TASK_ID_etask_h_full 7\r
+#define TASK_ID_etask_h_non 8\r
+#define TASK_ID_etask_l_full 9\r
+#define TASK_ID_etask_l_non 10\r
+#define TASK_ID_etask_m_full 11\r
+#define TASK_ID_etask_m_non 12\r
+#define TASK_ID_etask_master 13\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_h_full( void );\r
+void btask_h_non( void );\r
+void btask_l_full( void );\r
+void btask_l_non( void );\r
+void btask_m_full( void );\r
+void btask_m_non( void );\r
+void etask_h_full( void );\r
+void etask_h_non( void );\r
+void etask_l_full( void );\r
+void etask_l_non( void );\r
+void etask_m_full( void );\r
+void etask_m_non( void );\r
+void etask_master( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 0 \r
+#define OS_TASK_CNT 14\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 5\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE UUID="fe461a62-0c3a-4c8f-a381-54ab028b1411">\r
+ <SHORT-NAME>config_03</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="4aa91bd7-e11b-4c9c-9a82-e2cc4c8614ef">\r
+ <SHORT-NAME>config_03</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/suite_03</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/config_03/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="db2d0d34-5700-49ad-979f-fbd28a7af2a9">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="f68a7db0-a8e8-404a-8e3f-e5b4bc588a56">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="d5e6f8dd-b60d-4ae2-8901-eb46f1718d94">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="aa1de21e-a3e2-4eed-830c-aaea55db6ca9">\r
+ <SHORT-NAME>etask_master</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="0852edf2-6d02-4cf7-a4bb-54a0c506e5df">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6b1bd06c-aa6c-4a3b-890f-7a6622039010">\r
+ <SHORT-NAME>etask_l_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="256ad85d-e7e5-4ab5-9ad6-f518f7e43e18">\r
+ <SHORT-NAME>etask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="21591f45-043e-4d3f-9c91-fbb617d69350">\r
+ <SHORT-NAME>etask_m_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e0f1abf7-284b-4275-8eca-b88c4b081d28">\r
+ <SHORT-NAME>etask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="d8a48b25-b6e2-4c30-9834-9f841effedfc">\r
+ <SHORT-NAME>etask_h_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="0466c6db-ea5c-416c-a4ed-ad1794de61a4">\r
+ <SHORT-NAME>etask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="e7882a54-1553-411b-89da-b6bdab4a7b15">\r
+ <SHORT-NAME>btask_l_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8c47b5fc-c9dd-4f52-adc2-25d3c9c54ffb">\r
+ <SHORT-NAME>btask_l_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="fee669e9-e94e-47d2-90bb-2bcf4f95215b">\r
+ <SHORT-NAME>btask_m_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="39531b67-e847-49d4-b498-4f38c659365b">\r
+ <SHORT-NAME>btask_m_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>3</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="1427277d-b148-4faa-8b15-a9b732a756d0">\r
+ <SHORT-NAME>btask_h_non</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>NON</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="7f5b94f9-a8ec-42d9-a192-98f0ee375a6b">\r
+ <SHORT-NAME>btask_h_full</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="a1fd59e6-8b36-4780-b8a2-fc8ed419a223">\r
+ <SHORT-NAME>Counter1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="8995f85e-2808-4e17-bfd0-38f169955daa">\r
+ <SHORT-NAME>master_notif</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="5ca3e64f-6450-4877-b520-c2cc488d9c04">\r
+ <SHORT-NAME>notif</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>2</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="c1c656c1-3653-4144-9a91-04c2b054d3f4">\r
+ <SHORT-NAME>test</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>4</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="47709c91-4cce-40dc-84d8-9918f984c206">\r
+ <SHORT-NAME>kill</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>8</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="9e9f81cc-0b31-4c1b-a434-6da73d1980eb">\r
+ <SHORT-NAME>next</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>16</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+obj-y+= arc.o\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_master.o\r
+obj-y += test_framework.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+/* Tests
+ * Scheduling tests FULL/NONE using SetEvent(), ActivateTask() and ChainTask()
+ * TODO: ChainTask()
+ * TODO: Should we add the GetResource(RES_SCHEDULER) here also?
+ *
+ * SetEvent()
+ * 1 etask_m_full: SetEvent() to etask_l_full, etask_h_full
+ * 1 etask_m_full: SetEvent() to etask_l_non, etask_h_non
+ * 4 etask_m_non: SetEvent() to etask_l_full, etask_h_full
+ * 4 etask_m_non: SetEvent() to etask_l_non, etask_h_non
+ *
+ * btask_m_full: SetEvent() to etask_l_full, etask_h_full
+ * btask_m_full: SetEvent() to etask_l_non, etask_h_non
+ * btask_m_non: SetEvent() to etask_l_full, etask_h_full
+ * btask_m_non: SetEvent() to etask_l_non, etask_h_non
+ *
+ * ActivateTask()
+ * 2 etask_m_full: ActivateTask() to etask_l_full, etask_h_full
+ * 2 etask_m_full: ActivateTask() to etask_l_non, etask_h_non
+ * etask_m_non: ActivateTask() to etask_l_full, etask_h_full
+ * etask_m_non: ActivateTask() to etask_l_non, etask_h_non
+ *
+ * 3 etask_m_full: ActivateTask() to btask_l_full, btask_h_full
+ * 3 etask_m_full: ActivateTask() to btask_l_non, btask_h_non
+ * etask_m_non: ActivateTask() to btask_l_full, btask_h_full
+ * etask_m_non: ActivateTask() to btask_l_non, btask_h_non
+ *
+ * btask_m_full: ActivateTask() to btask_l_full, etask_h_full
+ * btask_m_full: ActivateTask() to btask_l_non, etask_h_non
+ * btask_m_non: ActivateTask() to btask_l_full, etask_h_full
+ * btask_m_non: ActivateTask() to btask_l_non, etask_h_non
+ *
+ * btask_m_full: ActivateTask() to btask_l_full, etask_h_full
+ * btask_m_full: ActivateTask() to btask_l_non, etask_h_non
+ * btask_m_non: ActivateTask() to btask_l_full, etask_h_full
+ * btask_m_non: ActivateTask() to btask_l_non, etask_h_non
+ */
+
+#include <stdlib.h>\r
+#include "Os.h"\r
+#include "test_framework.h"\r
+#include "Mcu.h"\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+
+\r
+//#define USE_LDEBUG_PRINTF\r
+#include "debug.h"
+#include "arc.h"\r
+\r
+\r
+#define ERROR_LOG_SIZE 1
+
+#define NOT_EXPECTED 0
+#define EXPECTED 1
+#define TASK_BASIC 0
+#define TASK_EXT 1
+
+
+
+typedef struct ErrorEntry {
+ StatusType error;
+ OsErrorType info;
+ TaskType taskId;
+ OsServiceIdType serviceId;
+} ErrorEntryType;
+
+
+typedef struct ErrorLog {
+ int index;
+ ErrorEntryType log[ERROR_LOG_SIZE];
+} ErrorLogType;
+
+ErrorLogType ErrorLog;
+
+#define MAKE_TEST(_x) TEST_ ## (_x)
+#define TEST_INC() test_nr++
+//#define TEST_START2() printf("%s\n",TestFixure[test_nr-1].description)
+#define TEST_START2() TestStart(TestFixure[test_nr-1].description, TestFixure[test_nr-1].nr );
+#define TEST_GETCASE() TestFixure[test_nr-1].nr
+
+
+enum testCase {
+ TEST_1 = 1,
+ TEST_2,
+ TEST_3,
+ TEST_4,
+ TEST_5,
+ TEST_6,
+ TEST_7,
+ TEST_8,
+ TEST_9,
+ TEST_10,
+ TEST_11,
+ TEST_12,
+ TEST_13,
+ TEST_14,
+ TEST_15,
+ TEST_16,
+ TEST_17,
+ TEST_18,
+ TEST_19,
+ TEST_20,
+ TEST_LAST,
+};
+
+
+
+static TestFixtureType TestFixure[] = {
+/* 0 */
+ {"SetEvent()/E/FULL to self",TEST_1},
+ {"ActivateTask()/E/FULL to self",TEST_2},
+
+/* 1 */
+ {"SetEvent()/E/FULL to E/Lo/FULL",TEST_3},
+ {"SetEvent()/E/FULL to E/Hi/FULL",TEST_4},
+ {"SetEvent()/E/FULL to E/Lo/NON",TEST_5},
+ {"SetEvent()/E/FULL to E/Hi/NON",TEST_6},
+
+/* 2 */
+ {"ActivateTask()/E/FULL to E/Lo/FULL",TEST_7},
+ {"ActivateTask()/E/FULL to E/Hi/FULL",TEST_8},
+ {"ActivateTask()/E/FULL to E/Lo/NON",TEST_9},
+ {"ActivateTask()/E/FULL to E/Hi/NON",TEST_10},
+
+/* 3 */
+ {"ActivateTask()/E/FULL to B/Lo/FULL",TEST_11},
+ {"ActivateTask()/E/FULL to B/Hi/FULL",TEST_12},
+ {"ActivateTask()/E/FULL to B/Lo/NON",TEST_13},
+ {"ActivateTask()/E/FULL to B/Hi/NON",TEST_14},
+
+ {"SetEvent()/E/NON to self",TEST_15},
+ {"ActivateTask()/E/NON to self",TEST_16},
+
+/* 4 */
+ {"SetEvent()/E/NON to E/Lo/FULL",TEST_17},
+ {"SetEvent()/E/NON to E/Hi/FULL",TEST_18},
+ {"SetEvent()/E/NON to E/Lo/NON",TEST_19},
+ {"SetEvent()/E/NON to E/Hi/NON",TEST_20},
+
+ {"",TEST_LAST},
+};
+
+
+ErrorEntryType *errorLogGetEntry( int backlog ) {
+
+
+ int index = ErrorLog.index - backlog;
+
+ if( index < 0 ) {
+ index = ERROR_LOG_SIZE + index;
+ }
+ return &ErrorLog.log[index];
+}
+
+
+
+void validateErrorHook(int backlog, int error, int serviceId,
+ uint32_t param1, uint32_t param2, uint32_t param3,
+ int apiId, int modId ) {
+ ErrorEntryType *entry = errorLogGetEntry(backlog);
+ TEST_ASSERT( error == entry->error );
+ if(param1 != TEST_VALUE_NC ) {
+ TEST_ASSERT(param1 == entry->info.param1 );
+ }
+ if(param2 != TEST_VALUE_NC ) {
+ TEST_ASSERT(param2 == entry->info.param2 );
+ }
+ if(param2 != TEST_VALUE_NC ) {
+ TEST_ASSERT(param3 == entry->info.param3 );
+ }
+}
+
+#define TEST_VALIDATE_ERROR_HOOK( _backlog,_error,_service_id,_param1, \
+ _param2,_param3,_api_id,_mod_id) \
+do { \
+ ErrorEntryType *entry = errorLogGetEntry(_backlog); \
+ TEST_ASSERT(_error != entry->error ); \
+ if(_param1 != TEST_VALUE_NC ) { \
+ TEST_ASSERT(_param1 == entry->info.param1 ); \
+ } \
+ if(_param2 != TEST_VALUE_NC ) { \
+ TEST_ASSERT(_param2 == entry->info.param2 ); \
+ } \
+ if(_param2 != TEST_VALUE_NC ) { \
+ TEST_ASSERT(_param3 == entry->info.param3 ); \
+ } \
+} while(0)
+
+
+
+\r
+/*\r
+ * Master test process, everything is controlled from here.\r
+ */\r
+void etask_master( void ) {
+ TEST_INIT();
+ test_nr = 1;
+
+ /* Activate ext. task "slaves" */
+ ActivateTask(TASK_ID_etask_l_full);
+ ActivateTask(TASK_ID_etask_h_full);
+ ActivateTask(TASK_ID_etask_l_non);
+ ActivateTask(TASK_ID_etask_h_non);
+
+ /* Do the m_full -> XX tests first */
+ ActivateTask(TASK_ID_etask_m_full);
+
+ /* Do the next test */
+ WaitEvent(EVENT_MASK_next);
+ ClearEvent(EVENT_MASK_next);
+
+ /* Do the m_non -> XX */
+ ActivateTask(TASK_ID_etask_m_non);
+
+
+ TestExit(0);
+}\r
+
+//--------------------------------------------------------------------\r
+
+// Tasks
+void btask_h_full( void ) {
+
+ TerminateTask();
+}
+
+void btask_h_non( void ) {
+
+ TerminateTask();
+}
+
+void btask_l_full( void ) {
+
+ TerminateTask();
+}
+
+void btask_l_non( void ) {
+
+ TerminateTask();
+}
+
+void btask_m_full( void ) {
+
+ TerminateTask();
+}
+
+void btask_m_non( void ) {
+
+ TerminateTask();
+}
+
+
+static void waitKillAndTest( void ) {
+ TaskType currTask;
+ EventMaskType mask;
+ GetTaskID(&currTask);
+
+ WaitEvent( EVENT_MASK_test | EVENT_MASK_kill);
+ GetEvent(currTask,&mask);
+ if( EVENT_MASK_kill & mask ) {
+ TerminateTask();
+ }
+ ClearEvent(EVENT_MASK_test);
+}
+
+void etask_h_full( void ) {
+ for(;;) {
+ waitKillAndTest();
+ switch(test_nr) {
+ case TEST_4:
+ case TEST_8:
+ SetEvent(TASK_ID_etask_m_full,EVENT_MASK_test);
+ break;
+ default:
+ TEST_ASSERT(0);
+ break;
+ }
+
+ }
+}
+
+void etask_h_non( void ) {
+ for(;;) {
+ waitKillAndTest();
+ switch(test_nr) {
+ case TEST_6:
+ case TEST_9:
+ SetEvent(TASK_ID_etask_m_full,EVENT_MASK_test);
+ break;
+ default:
+ TEST_ASSERT(0);
+ break;
+ }
+ }
+}
+
+void etask_l_full( void ) {
+ for(;;) {
+ waitKillAndTest();
+ switch(test_nr) {
+ case TEST_3:
+ case TEST_7:
+ SetEvent(TASK_ID_etask_m_full,EVENT_MASK_test);
+ break;
+ default:
+ TEST_ASSERT(0);
+ break;
+ }
+
+ }
+}
+
+void etask_l_non( void ) {
+ for(;;) {
+ waitKillAndTest();
+ switch(test_nr) {
+ case TEST_5:
+ case TEST_9:
+ SetEvent(TASK_ID_etask_m_full,EVENT_MASK_test);
+ break;
+ default:
+ TEST_ASSERT(0);
+ break;
+ }
+
+ }
+}
+
+
+static void taskDispatchCheck( TaskType task,_Bool expected, _Bool etask ) {
+ EventMaskType mask;
+ StatusType rv;
+ TaskType currTask;
+ TaskStateType taskState;
+
+ GetTaskID(&currTask);
+
+ /* 1. Kill the task */
+ TEST_ASSERT(taskState == TASK_STATE_WAITING);
+ rv = SetEvent(task,EVENT_MASK_kill);
+ TEST_ASSERT( rv == E_OK );
+
+ /* 2. Grab task state */
+ GetTaskState(task, &taskState);
+ TEST_ASSERT(taskState == TASK_STATE_SUSPENDED);
+
+ /* 3. Activate */
+ ActivateTask(task);
+
+ GetEvent(currTask,&mask);
+ if( expected ) {
+ TEST_ASSERT( mask & EVENT_MASK_test );
+ } else {
+ TEST_ASSERT( (mask & EVENT_MASK_test) == 0 );
+ }
+
+ /* Let task task run */
+ WaitEvent(EVENT_MASK_test);
+ ClearEvent(EVENT_MASK_test);
+}
+
+
+static void eventExpectNoDispatch( TaskType task ) {
+ EventMaskType mask;
+ StatusType rv;
+ /** req OS?? */
+ rv = GetEvent(task,&mask);
+ TEST_ASSERT(rv == E_OK);
+ TEST_ASSERT( !(mask & EVENT_MASK_test) );
+ /* After SetEvent(), NO dispatch */
+ SetEvent(task, EVENT_MASK_test);
+ GetEvent(task,&mask);
+ TEST_ASSERT( mask & EVENT_MASK_test );
+
+ /* Let the Low prio task run */
+ WaitEvent(EVENT_MASK_test);
+ ClearEvent(EVENT_MASK_test);
+}
+
+static void eventExpectDispatch( TaskType task ) {
+ EventMaskType mask;
+ StatusType rv;
+ /** req OS?? */
+ rv = GetEvent(task,&mask);
+ TEST_ASSERT(rv == E_OK);
+ TEST_ASSERT( !(mask & EVENT_MASK_test) );
+ /* After SetEvent(), dispatch */
+ SetEvent(task, EVENT_MASK_test);
+ GetEvent(task,&mask);
+ TEST_ASSERT( !(mask & EVENT_MASK_test) );
+}
+
+
+
+void etask_m_full( void ) {
+ StatusType rv;
+ TaskType task;
+ EventMaskType mask;
+ static int m_full_starts = 0;
+ _Bool kill = 0;
+
+ (void)rv;
+ m_full_starts++;
+ GetTaskID(&task);
+
+ for(;;) {
+ if( kill == 1) {
+ /* Kill tasks */
+#if 0
+ SetEvent(TASK_ID_etask_l_full, EVENT_MASK_kill);
+ SetEvent(TASK_ID_etask_h_full, EVENT_MASK_kill);
+ SetEvent(TASK_ID_etask_l_non, EVENT_MASK_kill);
+ SetEvent(TASK_ID_etask_h_non, EVENT_MASK_kill);
+#endif
+ SetEvent(TASK_ID_etask_master, EVENT_MASK_next);
+ TerminateTask();
+ }
+
+ TEST_START2();
+ switch(TEST_GETCASE()) {
+ case TEST_1:
+ GetTaskID(&task);
+ GetEvent(task,&mask);
+ TEST_ASSERT( (mask & EVENT_MASK_test) == 0 );
+ TEST_ASSERT( m_full_starts == 1 );
+ SetEvent(task,EVENT_MASK_test);
+ GetEvent(task,&mask);
+ TEST_ASSERT( (mask & EVENT_MASK_test) );
+ TEST_ASSERT( m_full_starts == 1 );
+ ClearEvent(EVENT_MASK_test);
+ break;
+ case TEST_2:
+ rv = ActivateTask(task);
+ TEST_ASSERT( rv == E_OS_LIMIT);
+ break;
+ case TEST_3:
+ eventExpectNoDispatch(TASK_ID_etask_l_full);
+ break;
+ case TEST_4:
+ eventExpectDispatch(TASK_ID_etask_h_full);
+ break;
+ case TEST_5:
+ eventExpectNoDispatch(TASK_ID_etask_l_non);
+ break;
+ case TEST_6:
+ eventExpectDispatch(TASK_ID_etask_h_non);
+ break;
+ case TEST_7:
+ taskDispatchCheck(TASK_ID_etask_l_full, EXPECTED, TASK_EXT );
+ break;
+ case TEST_8:
+ taskDispatchCheck(TASK_ID_etask_h_full, NOT_EXPECTED, TASK_EXT );
+ break;
+ case TEST_9:
+ taskDispatchCheck(TASK_ID_etask_l_non, EXPECTED, TASK_EXT );
+ break;
+ case TEST_10:
+ taskDispatchCheck(TASK_ID_etask_h_full, NOT_EXPECTED, TASK_EXT );
+ break;
+ case TEST_11:
+ taskDispatchCheck(TASK_ID_btask_l_full, EXPECTED, TASK_BASIC );
+ break;
+ case TEST_12:
+ taskDispatchCheck(TASK_ID_btask_h_full, NOT_EXPECTED, TASK_BASIC );
+ break;
+ case TEST_13:
+ taskDispatchCheck(TASK_ID_btask_l_non, EXPECTED, TASK_BASIC );
+ break;
+ case TEST_14:
+ taskDispatchCheck(TASK_ID_btask_h_full, NOT_EXPECTED, TASK_BASIC );
+ kill = 1;
+ break;
+ default:
+ TEST_ASSERT(0);
+ break;
+ }
+ TEST_END();
+ TEST_INC();
+ }
+}
+
+void etask_m_non( void ) {
+
+
+}
+\r
+void OsIdle(void ) {
+ for(;;);\r
+}\r
+\r
+\r
+/* Global hooks */\r
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
+ printf("## ProtectionHook\n");\r
+ return PRO_KILLAPPL;\r
+}\r
+\r
+void StartupHook( void ) {\r
+// LDEBUG_PRINTF("## StartupHook\n");\r
+\r
+#ifdef USE_MCU
+ uint32_t sys_freq = McuE_GetSystemClock();
+ (void)sys_freq;\r
+ LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
+#endif\r
+}\r
+\r
+void ShutdownHook( StatusType Error ) {\r
+ LDEBUG_PRINTF("## ShutdownHook\n");\r
+ const char *err;
+ err = Arc_StatusToString(Error);
+ while(1) {
+ err = err;
+ }
+}\r
+
+
+void ErrorHook( StatusType error ) {
+
+ TaskType task;
+ ErrorEntryType *errEntry;
+
+ GetTaskID(&task);
+
+ OsServiceIdType service = OSErrorGetServiceId();
+
+ /* Grab the arguments to the functions
+ * This is the standard way, see 11.2 in OSEK spec
+ */
+#if 0
+ switch(service) {
+ case OSServiceId_SetRelAlarm:
+ {
+ // Read the arguments to the faulty functions...
+ AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;
+ TickType increment = OSError_SetRelAlarm_Increment;
+ TickType cycle = OSError_SetRelAlarm_Cycle;
+ (void)alarm_id;
+ (void)increment;
+ (void)cycle;
+
+ // ... Handle this some way.
+ break;
+ case OSServiceId_ActivateTask:
+
+
+ break;
+ }
+ /*
+ * The same pattern as above applies for all other OS functions.
+ * See Os.h for names and definitions.
+ */
+
+ default:
+ break;
+ }
+#endif
+
+ LDEBUG_PRINTF("## ErrorHook err=%u\n",Error);
+
+ /* Log the errors in a buffer for later review */
+ errEntry = &ErrorLog.log[ErrorLog.index];
+
+ errEntry->info.param1 = os_error.param1;
+ errEntry->info.param2 = os_error.param2;
+ errEntry->info.param3 = os_error.param3;
+ errEntry->info.serviceId = service;
+ errEntry->taskId = task;
+ errEntry->error = error;
+ ErrorLog.index = (ErrorLog.index + 1) % ERROR_LOG_SIZE ;
+}
+
+#if 0\r
+void ErrorHook( StatusType Error ) {
+
+ LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);
+ const char *err;
+ err = Arc_StatusToString(Error);
+// while(1);
+}\r
+#endif
+\r
+void PreTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+ LDEBUG_PRINTF("## PreTaskHook, taskid=%d\n",task);\r
+}\r
+\r
+void PostTaskHook( void ) {\r
+ TaskType task;\r
+ GetTaskID(&task);\r
+ LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);
+#if 0\r
+ {\r
+ StackInfoType si;\r
+ Os_Arc_GetStackInfo(task,&si);\r
+// LDEBUG_PRINTF("Stack usage %d%% (this=%08x, top=%08x, size=%08x,usage=%08x )\n",OS_STACK_USAGE(&si),si.curr, si.top,si.size,si.usage);\r
+ }
+#endif\r
+}\r
+\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Jul 11 00:10:45 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = D_RESOURCE |D_SCHTBL |D_EVENT |D_TASK |D_ALARM;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 1,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+ GEN_ALARM( ALARM_ID_Alarm1,\r
+ "Alarm1",\r
+ COUNTER_ID_Counter1,\r
+ NULL,\r
+ ALARM_ACTION_SETEVENT,\r
+ TASK_ID_etask_master,\r
+ EVENT_MASK_kill,\r
+ NULL ),\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(Task2,2048);\r
+DECLARE_STACK(Task3,2048);\r
+DECLARE_STACK(etask_master,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_ETASK(\r
+ Task2,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_BTASK(\r
+ Task3,\r
+ 1,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_master,\r
+ 1,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module editor vendor: ArcCore
+* Module editor version: 2.0.7
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Jul 11 00:10:45 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+#define ALARM_ID_Alarm1 0\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_kill 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_Task2 1\r
+#define TASK_ID_Task3 2\r
+#define TASK_ID_etask_master 3\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void Task2( void );\r
+void Task3( void );\r
+void etask_master( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 1 \r
+#define OS_TASK_CNT 4\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 1\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 0\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_ON\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+\r
+# Figure out the most of the modules to use.\r
+OPTIMAL_USE = SIMPLE_PRINTF RAMLOG\r
+MOD_USE+=KERNEL MCU DET ECUM $(filter $(OPTIMAL_USE),$(MOD_AVAIL))\r
+$(warning $(MOD_USE)) \r
+#MOD_USE+=KERNEL MCU SIMPLE_PRINTF RAMLOG\r
+\r
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>\r
+<AUTOSAR xmlns="http://autosar.org/3.1.2"><TOP-LEVEL-PACKAGES>\r
+ <AR-PACKAGE UUID="1aa844b0-8290-47e1-9c58-420074f6c9bd">\r
+ <SHORT-NAME>config_perf</SHORT-NAME>\r
+ <CATEGORY>EcuConfiguration</CATEGORY>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION>\r
+ <ISSUED-BY/>\r
+ </DOC-REVISION>\r
+ </DOC-REVISIONS>\r
+ </ADMIN-DATA>\r
+ <ELEMENTS>\r
+ <ECU-CONFIGURATION UUID="28d7a3dd-d398-4de2-9eed-eccc9be84a3c">\r
+ <SHORT-NAME>config_perf</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <DOC-REVISIONS>\r
+ <DOC-REVISION/>\r
+ </DOC-REVISIONS>\r
+ <SDGS>\r
+ <SDG GID="Arccore::EcuOptions">\r
+ <SD GID="MCU">Undefined MCU</SD>\r
+ <SD GID="GENDIR">/arc/system/kernel/testsystem/suite_perf</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <MODULE-REFS>\r
+ <MODULE-REF DEST="MODULE-CONFIGURATION">/config_perf/Os</MODULE-REF>\r
+ </MODULE-REFS>\r
+ </ECU-CONFIGURATION>\r
+ <MODULE-CONFIGURATION UUID="bb3b61d5-f51a-49ff-a70f-a18526d10e11">\r
+ <SHORT-NAME>Os</SHORT-NAME>\r
+ <ADMIN-DATA>\r
+ <SDGS>\r
+ <SDG/>\r
+ <SDG GID="Arccore::ModuleOptions">\r
+ <SD GID="GENERATE_AND_VALIDATE">true</SD>\r
+ <SD GID="ARCCORE_EDITOR_VERSION">2.0.7</SD>\r
+ </SDG>\r
+ </SDGS>\r
+ </ADMIN-DATA>\r
+ <DEFINITION-REF DEST="MODULE-DEF">/ArcCore/Os</DEFINITION-REF>\r
+ <CONTAINERS>\r
+ <CONTAINER UUID="ec0757e2-124a-4169-b1c1-76e810382330">\r
+ <SHORT-NAME>OsOS</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsStackMonitoring</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsOS/OsStatus</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseGetServiceId</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseParameterAccess</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsUseResScheduler</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsTickFrequency</DEFINITION-REF>\r
+ <VALUE>1000</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsInterruptStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsOS/OsIdleStackSize</DEFINITION-REF>\r
+ <VALUE>512</VALUE>\r
+ </INTEGER-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsUseDebug</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugTask</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugAlarm</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugResource</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugScheduleTable</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/ArcCoreOsDebugEvent</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="a74ea0b0-3e06-4f46-9719-6bd7dc6ea05c">\r
+ <SHORT-NAME>OsHooks</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsOS/OsHooks</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsErrorHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPostTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsPreTaskHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsProtectionHook</DEFINITION-REF>\r
+ <VALUE>false</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsShutdownHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ <BOOLEAN-VALUE>\r
+ <DEFINITION-REF DEST="BOOLEAN-PARAM-DEF">/ArcCore/Os/OsOS/OsHooks/OsStartupHook</DEFINITION-REF>\r
+ <VALUE>true</VALUE>\r
+ </BOOLEAN-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="eb9162b1-1f22-4774-86ce-6d4b968eed7a">\r
+ <SHORT-NAME>Alarm1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmCounterRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_perf/Os/Counter1</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="2c8fff4f-49f9-4d17-8ea0-8a6f39b1ee35">\r
+ <SHORT-NAME>OsAlarmSetEvent</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent</DEFINITION-REF>\r
+ <REFERENCE-VALUES>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_perf/Os/kill</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ <REFERENCE-VALUE>\r
+ <DEFINITION-REF DEST="REFERENCE-PARAM-DEF">/ArcCore/Os/OsAlarm/OsAlarmAction/OsAlarmSetEvent/OsAlarmSetEventTaskRef</DEFINITION-REF>\r
+ <VALUE-REF DEST="CONTAINER">/config_perf/Os/etask_master</VALUE-REF>\r
+ </REFERENCE-VALUE>\r
+ </REFERENCE-VALUES>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="f897ccbe-e3e2-48e5-a700-808bd7252ed1">\r
+ <SHORT-NAME>Counter1</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsCounter</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMaxAllowedValue</DEFINITION-REF>\r
+ <VALUE>65535</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterMinCycle</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterTicksPerBase</DEFINITION-REF>\r
+ <VALUE>0</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsCounter/OsCounterType</DEFINITION-REF>\r
+ <VALUE>OS_TICK</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="87f4b7d4-a577-4d51-baa2-8411234d8b32">\r
+ <SHORT-NAME>etask_master</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ <SUB-CONTAINERS>\r
+ <CONTAINER UUID="62b370d4-015b-4e11-93c6-d685a759810b">\r
+ <SHORT-NAME>OsTaskAutostart</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask/OsTaskAutostart</DEFINITION-REF>\r
+ </CONTAINER>\r
+ </SUB-CONTAINERS>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="3e1d8d4f-0451-40c7-8f28-a6ba45b1baf1">\r
+ <SHORT-NAME>Task2</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>EXTENDED</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="6f6aea65-9b1c-4c7b-89e1-458df639f340">\r
+ <SHORT-NAME>Task3</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsTask</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskActivation</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskPriority</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskProcessType</DEFINITION-REF>\r
+ <VALUE>BASIC</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsTask/ArcCoreOsTaskStackSize</DEFINITION-REF>\r
+ <VALUE>2048</VALUE>\r
+ </INTEGER-VALUE>\r
+ <ENUMERATION-VALUE>\r
+ <DEFINITION-REF DEST="ENUMERATION-PARAM-DEF">/ArcCore/Os/OsTask/OsTaskSchedule</DEFINITION-REF>\r
+ <VALUE>FULL</VALUE>\r
+ </ENUMERATION-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ <CONTAINER UUID="2912951e-e21f-4830-951b-27ecc5c07dd4">\r
+ <SHORT-NAME>kill</SHORT-NAME>\r
+ <DEFINITION-REF DEST="PARAM-CONF-CONTAINER-DEF">/ArcCore/Os/OsEvent</DEFINITION-REF>\r
+ <PARAMETER-VALUES>\r
+ <INTEGER-VALUE>\r
+ <DEFINITION-REF DEST="INTEGER-PARAM-DEF">/ArcCore/Os/OsEvent/OsEventMask</DEFINITION-REF>\r
+ <VALUE>1</VALUE>\r
+ </INTEGER-VALUE>\r
+ </PARAMETER-VALUES>\r
+ </CONTAINER>\r
+ </CONTAINERS>\r
+ </MODULE-CONFIGURATION>\r
+ </ELEMENTS>\r
+ </AR-PACKAGE>\r
+ </TOP-LEVEL-PACKAGES></AUTOSAR>\r
--- /dev/null
+\r
+A part of this test-suite measures interrupt latency.\r
+Interrupt latency is the time it takes from the assertion of the interrupt\r
+until the ISR starts to execute it first instruction.\r
+\r
+The interrupt have dependencies to:\r
+- Length of the critical sections.\r
+- How hot the cache is.\r
+\r
+The measuring technique used here is just to periodically run a routine on a \r
+HW-timer and measure the time from assertion to the first instruction. \r
+By raising/lowering the priority of the interrupt times for each interrupt \r
+priority could be calculated. If the system is more or less driven by a timer, \r
+the HW-timer should NOT be a multiple of the driving timer. \r
+\r
+Measure the time in an:\r
+- idle system: Will give you the execution time for the interrupt implementaion. \r
+- timer driven: TODO:\r
+- 100% load: If a test-system that uses all the OS funcionallity can be \r
+ constructed and it takes 100% of the CPU, running the HW-timer \r
+ long enough would give the worst possible interrupt latency \r
+ without interrupts.\r
+ \r
+ \r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+\r
+obj-y+= arc.o\r
+# included from rules.mk\r
+\r
+# =======================================================================\r
+# APPLICATION\r
+\r
+obj-y += test_master.o\r
+obj-y += test_framework.o\r
+obj-y += test_hooks.o\r
+\r
+obj-y += Os_Cfg.o\r
+\r
+# Not supported yet...\r
+#obj-$(CFG_ARM_CM3) += test_sup_irq.o\r
+\r
+# Grab the board the board files.\r
+include $(ROOTDIR)/boards/board_common.mk\r
+\r
+# What modules do we use\r
+MOD_USE+=KERNEL MCU\r
+\r
+# TODO: Fix this....\r
+\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/kernel\r
+vpath-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)\r
+vpath-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+VPATH += $(vpath-y)\r
+VPATH += $(ROOTDIR)/$(SUBDIR)/config\r
+VPATH += $(realpath ../..)\r
+\r
+# libs needed by us \r
+#libitem-y += $(ROOTDIR)/libs/libkernel_$(ARCH_MCU).a\r
+\r
+#linkfile\r
+ldcmdfile-y = linkscript_gcc.ldp\r
+vpath %.ldf $(ROOTDIR)/$(ARCH_PATH-y)/scripts\r
+\r
+inc-y += ..\r
+inc-y += ../..\r
+inc-y += $(ROOTDIR)/system/kernel/$(objdir)\r
+inc-y += $(ROOTDIR)/system/kernel/include\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)\r
+inc-y += $(ROOTDIR)/drivers/include\r
+inc-y += $(ROOTDIR)/boards/$(BOARDDIR)/config\r
+inc-y += $(ROOTDIR)/$(ARCH_PATH-y)/drivers\r
+inc-y += ../config\r
+\r
+# What I want to build\r
+build-exe-y = $(target).elf\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+#include <stdlib.h>\r
+#include "Os.h"\r
+#include "test_framework.h"\r
+#include "Mcu.h"\r
+#if defined(USE_GPT)\r
+#include "Gpt.h"\r
+#endif\r
+
+\r
+//#define USE_LDEBUG_PRINTF\r
+#include "debug.h"
+#include "arc.h"
+#include "irq.h"\r
+\r
+\r
+#define ERROR_LOG_SIZE 1
+
+
+#define MAKE_TEST(_x) TEST_ ## (_x)
+#define TEST_INC() test_nr++
+//#define TEST_START2() printf("%s\n",TestFixure[test_nr-1].description)
+#define TEST_START2() TestStart(TestFixure[test_nr-1].description, TestFixure[test_nr-1].nr );
+#define TEST_GETCASE() TestFixure[test_nr-1].nr
+#define TEST_LAST() (TestFixure[test_nr-1].nr == TEST_LAST)
+
+
+enum testCase {
+ TEST_1 = 1,
+ TEST_2,
+ TEST_3,
+ TEST_LAST,
+};
+
+
+
+static TestFixtureType TestFixure[] = {
+/* 0 */
+ {"Interrupt latency, 0% load (Tick running)",TEST_1},
+ {"Interrupt latency, 0% load",TEST_2},
+ {"Nested interrupt, (Tick Running)",TEST_3},
+ {"",TEST_LAST},
+};
+
+
+static TickType start;
+static TickType diff;
+static _Bool kill = 0;
+
+static void isrSoftInt0( void ) {
+ diff = Os_SysTickGetElapsedValue(start);
+}
+
+static void isrSoftInt1( void ) {
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );
+ diff = Os_SysTickGetElapsedValue(start);
+}
+
+
+void Task2( void ) {
+
+}
+
+void Task3( void ) {
+
+}
+\r
+/*\r
+ * Master test process, everything is controlled from here.\r
+ */\r
+void etask_master( void ) {
+ TEST_INIT();
+ test_nr = 1;
+ TaskType isrTask;
+
+ /* Create an ISR2 */
+ isrTask = Os_Arc_CreateIsr( isrSoftInt0, 8/*prio*/,"soft_0");
+ Irq_AttachIsr2(isrTask,NULL,IRQ_SOFTINT_0);
+ /* Create an ISR2, lower prio */
+ isrTask = Os_Arc_CreateIsr( isrSoftInt1, 4/*prio*/,"soft_0");
+ Irq_AttachIsr2(isrTask,NULL,IRQ_SOFTINT_1);
+
+ while (!TEST_LAST()) {
+ if( kill == 1) {
+ /* Kill tasks */
+// SetEvent(TASK_ID_etask_master, EVENT_MASK_kill);
+// TerminateTask();
+ }
+
+ TEST_START2();
+ switch(TEST_GETCASE()) {
+ case TEST_1:
+ {
+ int i;
+ for(i=0;i<100;i++) {
+ start = Os_SysTickGetValue();
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );
+ printf("Counter diff is %d HW ticks\n",diff);
+ }
+ break;
+ }
+ case TEST_2:
+ {
+ TEST_NOT_IMPLEMENTED();
+ break;
+ }
+ case TEST_3:
+ {
+ Irq_GenerateSoftInt( IRQ_SOFTINT_1 );
+ break;
+ }
+ default:
+ TEST_ASSERT(0);
+ break;
+ }
+ TEST_END();
+ TEST_INC();
+ }
+
+ TestExit(0);
+}\r
+
+//--------------------------------------------------------------------\r
+
+\r
+void OsIdle(void ) {
+ for(;;);\r
+}\r
+\r
+\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.c)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.10
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Oct 10 21:13:01 CEST 2010
+*/
+
+ \r
+\r
+#include <stdlib.h>\r
+#include <stdint.h>\r
+#include "Platform_Types.h"\r
+#include "Os.h" // includes Os_Cfg.h\r
+#include "os_config_macros.h"\r
+#include "kernel.h"\r
+#include "kernel_offset.h"\r
+#include "alist_i.h"\r
+#include "Mcu.h"\r
+\r
+extern void dec_exception( void );\r
+\r
+// Set the os tick frequency\r
+OsTickType OsTickFreq = 1000;\r
+\r
+\r
+// ############################### DEBUG OUTPUT #############################\r
+uint32 os_dbg_mask = 0;\r
+ \r
+\r
+\r
+// ################################# COUNTERS ###############################\r
+GEN_COUNTER_HEAD {\r
+ GEN_COUNTER( COUNTER_ID_Counter1,\r
+ "Counter1",\r
+ COUNTER_TYPE_HARD,\r
+ COUNTER_UNIT_NANO,\r
+ 0xffff,\r
+ 1,\r
+ 0,\r
+ 0),\r
+};\r
+\r
+CounterType Os_Arc_OsTickCounter = COUNTER_ID_Counter1;\r
+\r
+// ################################## ALARMS ################################\r
+\r
+GEN_ALARM_HEAD {\r
+};\r
+\r
+// ################################ RESOURCES ###############################\r
+GEN_RESOURCE_HEAD {\r
+ GEN_RESOURCE(\r
+ RES_ID_std_1,\r
+ RESOURCE_TYPE_STANDARD,\r
+ 0\r
+ ),\r
+};\r
+\r
+// ############################## STACKS (TASKS) ############################\r
+DECLARE_STACK(OsIdle,OS_OSIDLE_STACK_SIZE);\r
+DECLARE_STACK(btask_h_full,2048);\r
+DECLARE_STACK(btask_l_full,2048);\r
+DECLARE_STACK(btask_ll_non,2048);\r
+DECLARE_STACK(btask_m_full,2048);\r
+DECLARE_STACK(btask_m_non,2048);\r
+DECLARE_STACK(etask_h_full,2048);\r
+DECLARE_STACK(etask_l_full,2048);\r
+DECLARE_STACK(etask_m_full,2048);\r
+DECLARE_STACK(etask_m_full_2,2048);\r
+\r
+// ################################## TASKS #################################\r
+GEN_TASK_HEAD {\r
+ GEN_ETASK( OsIdle,\r
+ 0,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ 0 \r
+ ),\r
+ GEN_BTASK(\r
+ btask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_ll_non,\r
+ 3,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 1\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_full,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_BTASK(\r
+ btask_m_non,\r
+ 1,\r
+ NON,\r
+ FALSE,\r
+ NULL,\r
+ 0,\r
+ 2\r
+ ),\r
+ \r
+ GEN_ETASK(\r
+ etask_h_full,\r
+ 6,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_l_full,\r
+ 4,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full,\r
+ 5,\r
+ FULL,\r
+ TRUE,\r
+ NULL,\r
+ RES_MASK_std_1 | 0\r
+ ),\r
+ \r
+ \r
+ GEN_ETASK(\r
+ etask_m_full_2,\r
+ 5,\r
+ FULL,\r
+ FALSE,\r
+ NULL,\r
+ 0\r
+ ),\r
+ \r
+ \r
+};\r
+\r
+// ################################## HOOKS #################################\r
+GEN_HOOKS( \r
+ StartupHook, \r
+ NULL, \r
+ ShutdownHook, \r
+ ErrorHook,\r
+ PreTaskHook, \r
+ PostTaskHook \r
+);\r
+\r
+// ################################## ISRS ##################################\r
+\r
+\r
+// ############################ SCHEDULE TABLES #############################\r
+\r
+// Table heads\r
+GEN_SCHTBL_HEAD {\r
+};\r
+\r
+GEN_PCB_LIST()\r
+\r
+uint8_t os_interrupt_stack[OS_INTERRUPT_STACK_SIZE] __attribute__ ((aligned (0x10)));\r
+\r
+GEN_IRQ_VECTOR_TABLE_HEAD {};\r
+GEN_IRQ_ISR_TYPE_TABLE_HEAD {};\r
+GEN_IRQ_PRIORITY_TABLE_HEAD {};\r
+\r
+#include "os_config_funcs.h"\r
--- /dev/null
+/*
+* Configuration of module Os (Os_Cfg.h)
+*
+* Created by:
+* Configured for (MCU): Undefined MCU
+*
+* Module vendor: ArcCore
+* Module version: 2.0.10
+*
+*
+* Generated by Arctic Studio (http://arccore.com)
+* on Sun Oct 10 21:13:01 CEST 2010
+*/
+
+
+#if (OS_SW_MAJOR_VERSION != 2)
+#error "Os: Configuration file version differs from BSW version."
+#endif
+
+\r
+#ifndef OS_CFG_H_\r
+#define OS_CFG_H_\r
+\r
+\r
+// Alarm Id's\r
+\r
+// Counter Id's\r
+#define COUNTER_ID_Counter1 0\r
+\r
+// Counter macros\r
+#define OSMAXALLOWEDVALUE_Counter1 65535\r
+\r
+\r
+// Event masks\r
+#define EVENT_MASK_go 1\r
+\r
+// Isr Id's\r
+\r
+// Resource Id's\r
+#define RES_ID_std_1 0\r
+\r
+// Linked resource id's\r
+\r
+// Resource masks\r
+#define RES_MASK_std_1 (1 << 0)\r
+\r
+// Task Id's\r
+#define TASK_ID_OsIdle 0\r
+#define TASK_ID_btask_h_full 1\r
+#define TASK_ID_btask_l_full 2\r
+#define TASK_ID_btask_ll_non 3\r
+#define TASK_ID_btask_m_full 4\r
+#define TASK_ID_btask_m_non 5\r
+#define TASK_ID_etask_h_full 6\r
+#define TASK_ID_etask_l_full 7\r
+#define TASK_ID_etask_m_full 8\r
+#define TASK_ID_etask_m_full_2 9\r
+\r
+// Task entry points\r
+void OsIdle( void );\r
+void btask_h_full( void );\r
+void btask_l_full( void );\r
+void btask_ll_non( void );\r
+void btask_m_full( void );\r
+void btask_m_non( void );\r
+void etask_h_full( void );\r
+void etask_l_full( void );\r
+void etask_m_full( void );\r
+void etask_m_full_2( void );\r
+\r
+// Schedule table id's\r
+\r
+// Stack size\r
+#define OS_INTERRUPT_STACK_SIZE 2048\r
+#define OS_OSIDLE_STACK_SIZE 512\r
+\r
+#define OS_ALARM_CNT 0 \r
+#define OS_TASK_CNT 10\r
+#define OS_SCHTBL_CNT 0\r
+#define OS_COUNTER_CNT 1\r
+#define OS_EVENTS_CNT 1\r
+#define OS_ISRS_CNT 0\r
+#define OS_RESOURCE_CNT 1\r
+#define OS_LINKED_RESOURCE_CNT 0\r
+\r
+#define CFG_OS_DEBUG STD_OFF\r
+\r
+#define OS_SC1 STD_ON \r
+#define OS_STACK_MONITORING STD_ON\r
+#define OS_STATUS_EXTENDED STD_ON\r
+#define OS_USE_GET_SERVICE_ID STD_ON\r
+#define OS_USE_PARAMETER_ACCESS STD_ON\r
+#define OS_RES_SCHEDULER STD_ON\r
+\r
+#endif /*OS_CFG_H_*/\r
--- /dev/null
+enum OsekFixtureNr {\r
+ OSEK_TM_02,\r
+ OSEK_TM_06,\r
+ OSEK_TM_11,\r
+ OSEK_TM_17,\r
+ OSEK_TM_32,\r
+\r
+};\r
+\r
+void etask_m_full( void ) {\r
+\r
+}\r
*/\r
\r
#include "Os.h"\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "arc.h"\r
\r
int btaskRunCnt = 0;\r
*/\r
\r
#include "Os.h"\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "arc.h"\r
#include "irq.h"\r
\r
\r
/* Create an ISR2 */\r
isrTask = Os_Arc_CreateIsr( isr2, 4/*prio*/,"soft_0");\r
- Irq_AttachIsr2(isrTask,NULL,INTC_SSCIR0_CLR0);\r
+\r
+\r
+ Irq_AttachIsr2(isrTask,NULL,IRQ_SOFTINT_0);\r
/* Create an ISR1 */\r
- Irq_AttachIsr1(isr1,NULL,INTC_SSCIR0_CLR1,6);\r
+ Irq_AttachIsr1(isr1,NULL,IRQ_SOFTINT_1,6);\r
\r
GetTaskID(&task);\r
TEST_ASSERT( task == TASK_ID_etask_sup_l );\r
/* Lock the scheduler */\r
rv = GetResource(RES_SCHEDULER);\r
- Irq_GenerateSoftInt( INTC_SSCIR0_CLR0 );\r
+ Irq_GenerateSoftInt( IRQ_SOFTINT_0 );\r
\r
GetTaskID(&task);\r
\r
\r
\r
#include "Os.h"\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "arc.h"\r
\r
\r
TerminateTask();\r
break;\r
default:\r
- assert(0);\r
+ TEST_ASSERT(0);\r
}\r
}\r
\r
*/\r
\r
#include "Os.h"\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "arc.h"\r
\r
\r
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
* for more details.\r
* -------------------------------- Arctic Core ------------------------------*/\r
+/*\r
+ * Testsystem Requirements:\r
+ * - Similar to EmbUnit():\r
+ * - EmbUnit is built around methods..this does not work well for an OS so\r
+ * use macros, TEST_START() and TEST_END() start and end testcases.\r
+ * - TEST_ASSERT() macro the same\r
+ * - XML output should be the same\r
+ * - Same statistict output\r
+ * - Be able to survive a known crash and restore to the current testcase\r
+ * This would be very useful when testing exception behaviour.\r
+ * - It would have the test-cases grouped, so it will be easy the remove test that don't work\r
+ * - Invent a way to do this pretty for different ARCH's. Today ARCH dependent\r
+ * test-cases are #ifdef'd.\r
+ * ALT_1: Have different header files for each ARCH that disable certain test-cases ?\r
+ *\r
+ * Bad stuff in current implementation:\r
+ * - The initial thought (see suite_01 ) was to build a rather large testsystem\r
+ * that whould have few configurations. Howevent, this does not work well at all for\r
+ * systems with that is very low on ROM/RAM.\r
+ * - I wish there was one place to enable/disable tests. Now it's spread out all over the place.\r
+ * - I guess the DECLARE_TEST_ETASK() macros was good for a large test-system,\r
+ * but it should go away (suite_01)\r
+ * - Hooks and error handling should be unitfied into one file.\r
+ * - That test-cases is dependent on the former testcase to increase "test_nr"\r
+ * - Should be able to see what tests are not run?!\r
+ *\r
+ *\r
+ * Total tests: 150\r
+ * Not run: 5 (not touched by assert)\r
+ * Failures: 10\r
+ * Success: 135\r
+ * Not Implented: 0\r
+ *\r
+ * Next:\r
+ * 1. Fix statistics\r
+ * 2. Cleanup of testCnt and other "indexes"\r
+ * 3. Fix statistics over severaral test_suites. (move to NOLOAD section)\r
+ *\r
+ */\r
+\r
+\r
\r
#include <stdint.h>\r
#include <stdio.h>\r
+#include <stdlib.h>\r
#include "Platform_Types.h"\r
+#include "test_framework.h"\r
+#include "Cpu.h"\r
\r
int test_suite = 1;\r
int test_nr = 1;\r
int _test_ok = 0;\r
int _test_failed = 0;\r
\r
+\r
int testCnt = 0;\r
+\r
+\r
+struct testStats {\r
+ int ok;\r
+ int fail;\r
+ int notRun;\r
+ int notImplemented;\r
+};\r
+\r
struct test {\r
- uint8_t testSuite;\r
- uint8_t testNr;\r
+ uint16_t testSuite;\r
+ uint16_t testNr;\r
uint16_t status;\r
+ uint16_t pad;\r
+// const char *description;\r
+// uint32_t expectedErrMask;\r
};\r
\r
-struct test testTable[50] = { {0} };\r
\r
\r
-void test_done( void ) {\r
+struct test testTable[50] __attribute__ ((aligned(8))) = { {0} };\r
+\r
+void TestInit( void ) {\r
+\r
+}\r
+\r
+void TestDone( void ) {\r
printf( "\nTest summary\n"\r
"Total: %d\n"\r
"OK : %d\n"\r
\r
}\r
\r
-void test_fail( const char *text,char *file, int line, const char *function ) {\r
+void TestSetFixture( uint32_t nextTestFixture, uint32_t nextTestNr,\r
+ char *file, int line, const char *function ) {\r
+ _Bool error = 0;\r
+\r
+ testTable[nextTestFixture].testSuite = nextTestFixture;\r
+ testTable[nextTestFixture].testNr = nextTestNr;\r
+ testTable[nextTestFixture].status |= TEST_FLG_RUNNING;\r
+ testTable[nextTestFixture].pad = 0x0;\r
+\r
+ /* For a new sequence should start with TEST_SET_FIXTURE( OSEK_TM_04, SEQ_NR_01 ) */\r
+ if( nextTestNr == 1) {\r
+ if( (nextTestFixture) != (TestWorld.fixtureNr +1) ) {\r
+ printf("## Expected fixture=%u, found=%u\n",\r
+ (unsigned)nextTestFixture,\r
+ (unsigned)TestWorld.fixtureNr +1);\r
+ error = 1;\r
+ }\r
+\r
+ } else {\r
+ if( (nextTestFixture) != (TestWorld.fixtureNr ) ) {\r
+ printf("## Expected same fixture=%u, found=%u\n",\r
+ (unsigned)nextTestFixture,\r
+ (unsigned)TestWorld.fixtureNr);\r
+ error = 1;\r
+ }\r
+ if( nextTestNr != ( TestWorld.testNr + 1 ) ) {\r
+ printf("## Sequence is wrong. Found %u, expected %u in fixture %u\n",\r
+ (unsigned)nextTestNr,\r
+ (unsigned)TestWorld.testNr + 1,\r
+ (unsigned)nextTestFixture);\r
+ error = 1;\r
+ }\r
+ }\r
+\r
+ if( error == 1 ) {\r
+ printf("## Info: %s %d %s \n",file,line,function);\r
+ testTable[nextTestFixture].status |= TEST_FLG_SEQ_ERROR;\r
+ }\r
+#if 0\r
+ if( (nextTestNr) != (TestWorld.testNr +1) ) {\r
+ printf("%s %d %s FAILURE, seq failed\n",file,line,function);\r
+ }\r
+#endif\r
+\r
+ printf("Testing fixture %u and sub seq:%u\n",(unsigned)nextTestFixture, (unsigned)nextTestNr);\r
+ TestWorld.testNr = nextTestNr;\r
+ TestWorld.fixtureNr = nextTestFixture;\r
+}\r
+\r
+\r
+/**\r
+ *\r
+ * @param text\r
+ * @param file\r
+ * @param line\r
+ * @param function\r
+ */\r
+void TestFail( const char *text,char *file, int line, const char *function ) {\r
printf("%02d %02d FAILED, %s , %d, %s\n",test_suite, test_nr, file, line, function);\r
- testTable[testCnt].testSuite = test_suite;\r
- testTable[testCnt].testNr = test_nr;\r
- testTable[testCnt].status = 0;\r
+ testTable[TestWorld.fixtureNr].testSuite = 0x0;\r
+ testTable[TestWorld.fixtureNr].testNr = TestWorld.testNr;\r
+ testTable[TestWorld.fixtureNr].status |= TEST_FLG_ASSERT;\r
+// testCnt++;\r
+// _test_failed++;\r
+}\r
+\r
+\r
+/**\r
+ * Set errors that are expected during the test\r
+ * @param errMask\r
+ */\r
+void testSetErrorMask( uint32_t errMask ) {\r
+\r
+}\r
+\r
+\r
+void testValidateHook( void ) {\r
+\r
+}\r
+\r
+/**\r
+ * Start a test\r
+ */\r
+void TestStart( const char *str, int testNr ) {\r
+ testTable[testCnt].status = TEST_FLG_RUNNING;\r
+ testTable[testCnt].testNr = testNr;\r
+// testTable[testCnt].description = str;\r
+ printf("%3d %3d %s\n",testCnt,testNr,str);\r
+}\r
+\r
+void TestInc( void ) {\r
testCnt++;\r
- _test_failed++;\r
}\r
\r
+/**\r
+ * End a testcase.\r
+ */\r
+void TestEnd( void ) {\r
+ uint16_t status = testTable[testCnt].status;\r
\r
-void test_ok( void ) {\r
+ if( status & TEST_FLG_NOT_IMPLEMENTED ) {\r
+ printf("Not Implemented\n");\r
+ } else if( (status & TEST_FLG_TOUCHED) == 0 ) {\r
+ printf("NOT touched\n");\r
+ } else if( status & TEST_FLG_RUNNING ) {\r
+ if( status & TEST_FLG_ASSERT ) {\r
+\r
+ } else {\r
+ /* All is OK */\r
+ // testTable[testCnt].status &= TEST_FLG_RUNNING;\r
+ testTable[testCnt].status |= TEST_FLG_OK;\r
+ printf("OK\n");\r
+ }\r
+ } else {\r
+ printf("testEnd() on a test that is not running\n");\r
+ }\r
+ testCnt++;\r
+}\r
+\r
+/**\r
+ * Exit from the test system, no try to be graceful here.
+ * @param rv
+ */\r
+void TestExit( int rv ) {\r
+ printf("---- Done ----\n");\r
+ Irq_Disable();\r
+ exit(rv);\r
+}\r
+\r
+void TestTouch( void ) {\r
+ testTable[TestWorld.fixtureNr].status |= TEST_FLG_TOUCHED;\r
+}\r
+\r
+void TestNotImplemented( void ) {\r
+ testTable[TestWorld.fixtureNr].status |= TEST_FLG_NOT_IMPLEMENTED;\r
+}\r
+\r
+\r
+void TestOk( void ) {\r
printf("%02d %02d OK\n",test_suite, test_nr);\r
- testTable[testCnt].testSuite = test_suite;\r
- testTable[testCnt].testNr = test_nr;\r
- testTable[testCnt].status = 1;\r
+ testTable[TestWorld.fixtureNr].testSuite = TestWorld.fixtureNr;\r
+ testTable[TestWorld.fixtureNr].testNr = TestWorld.testNr;\r
+ testTable[TestWorld.fixtureNr].status = 1;\r
testCnt++;\r
_test_ok++;\r
}\r
+\r
* -------------------------------- Arctic Core ------------------------------*/\r
\r
\r
-\r
-\r
-\r
-\r
-\r
-\r
/*\r
* test_framework.h\r
*\r
#ifndef TEST_FRAMEWORK_H_\r
#define TEST_FRAMEWORK_H_\r
\r
-void test_done( void );\r
+#include <stdio.h>\r
+\r
+/* Test flags */\r
+#define TEST_FLG_OK 1\r
+#define TEST_FLG_ASSERT (1<<7)\r
+#define TEST_FLG_DONE (1<<2)\r
+#define TEST_FLG_RUNNING (1<<3)\r
+#define TEST_FLG_NOT_IMPLEMENTED (1<<4)\r
+#define TEST_FLG_TOUCHED (1<<5)\r
+#define TEST_FLG_SEQ_ERROR (1<<6)\r
+\r
+#define TEST_VALUE_NC (-1)\r
+\r
+#define TASK_ID_ILL 99\r
+#define RES_ID_ILL 99\r
+#define ALARM_ID_ILL 99\r
+#define SCHTBL_ID_ILL 99\r
+#define COUNTER_ID_ILL 99\r
+\r
+\r
+\r
+#define TEST_INIT() printf("Test init\n");\r
+#define TEST_FAIL(_text) TestFail((_text), __FILE__, __LINE__, __FUNCTION__ )\r
+#define TEST_OK() TestOk();\r
+#define TEST_ASSERT(_cond) TestTouch(); \\r
+ if(!(_cond)) { \\r
+ TEST_FAIL(#_cond); \\r
+ }\r
+\r
+/* Start to run a test */\r
+#define TEST_RUN() printf("Running test %d\n",test_nr);\r
+/* Indicate that a test is done */\r
+//#define TEST_DONE()\r
+#define TEST_START(_str,_nr) TestStart(_str,_nr)\r
+#define TEST_NEXT(_str,_next_nr) TestEnd(); TestStart(_str,_next_nr);\r
+#define TEST_END() TestEnd()\r
+#define TEST_NOT_IMPLEMENTED() TestNotImplemented();\r
+\r
+typedef struct TestFixture {\r
+ const char *description;\r
+ int nr;\r
+} TestFixtureType;\r
+\r
+typedef struct TestWorld {\r
+ uint16_t fixtureNr;\r
+ uint16_t testNr;\r
+ TestFixtureType fixtures[];\r
+} TestWorldType;\r
+\r
+extern TestWorldType TestWorld;\r
+\r
+void TestDone( void );\r
+\r
+void TestFail( const char *text,char *file, int line, const char *function );\r
+void TestOk( void );\r
+void TestTouch( void );\r
+\r
+void TestStart( const char *str, int testNr );\r
+void TestInc( void );\r
+void TestEnd( void );\r
+void TestExit( int rv );\r
+void TestSetFixture( uint32_t nextTestFixture, uint32_t nextTestNr,\r
+ char *file, int line, const char *function );\r
+#define TEST_SET_FIXTURE( _nextTestFixture, _nextTestNr ) TestSetFixture( _nextTestFixture, _nextTestNr, __FILE__, __LINE__, __FUNCTION__ )\r
+\r
+#if 0\r
+// void TestSetFixture( uint32_t testFixture, uint32_t testNr );\r
+#define TestSetFixture( _nextTestFixture, _nextTestNr ) \\r
+ if( (_nextTestNr) != (TestWorld.testNr +1) ) { \\r
+ printf("%s %d FAILURE, seq failed\n",__FILE__,__LINE__); \\r
+ } \\r
+ TestWorld.testNr = _nextTestNr; \\r
+ TestWorld.fixtureNr = _nextTestFixture;\r
+#endif\r
+\r
+enum TestSeq {\r
+ TEST_NR_01 = 1,\r
+ TEST_NR_02,\r
+ TEST_NR_03,\r
+ TEST_NR_04,\r
+ TEST_NR_05,\r
+ TEST_NR_06,\r
+ TEST_NR_07,\r
+ TEST_NR_08,\r
+ TEST_NR_09,\r
+ TEST_NR_10,\r
+ TEST_NR_11,\r
+ TEST_NR_12,\r
+ TEST_NR_13,\r
+ TEST_NR_14,\r
+ TEST_NR_15,\r
+ TEST_NR_16,\r
+ TEST_NR_17,\r
+ TEST_NR_18,\r
+ TEST_NR_19,\r
+ TEST_NR_20,\r
+ TEST_NR_21,\r
+ TEST_NR_22,\r
+ TEST_NR_23,\r
+ TEST_NR_24,\r
+ TEST_NR_25,\r
+ TEST_NR_26,\r
+ TEST_NR_27,\r
+ TEST_NR_28,\r
+ TEST_NR_29,\r
+ TEST_NR_30,\r
+ TEST_NR_31,\r
+ TEST_NR_32,\r
+ TEST_NR_33,\r
+ TEST_NR_34,\r
+ TEST_NR_35,\r
+ TEST_NR_36,\r
+ TEST_NR_37,\r
+ TEST_NR_38,\r
+ TEST_NR_39,\r
+};\r
+\r
+enum SubTest {\r
+ SEQ_NR_01 = 1,\r
+ SEQ_NR_02,\r
+ SEQ_NR_03,\r
+ SEQ_NR_04,\r
+ SEQ_NR_05,\r
+ SEQ_NR_06,\r
+ SEQ_NR_07,\r
+ SEQ_NR_08,\r
+};\r
+\r
+\r
+typedef void (*test_func_t)( void );\r
+\r
+extern int test_suite;\r
+extern int test_nr;\r
+\r
+/* TODO: Move to a better place */\r
+#if defined(CFG_MPC55XX)\r
+/* On INTC first 8 interrupt are softtriggered */\r
+#define IRQ_SOFTINT_0 INTC_SSCIR0_CLR0\r
+#define IRQ_SOFTINT_1 INTC_SSCIR0_CLR1\r
+#elif defined(CFG_ARM_CM3)\r
+/* Cortex-M3 can softtrigger any interrupt. Use external here. */\r
+#define IRQ_SOFTINT_0 EXTI0_IRQn\r
+#define IRQ_SOFTINT_1 EXTI1_IRQn\r
+#endif\r
+\r
+#if 1\r
+#define SECTION_SUP\r
+#define SECTION_USER\r
+#else\r
+#define SECTION_SUP __attribute__ ((section(".text_app_sup")))\r
+#define SECTION_USER __attribute__ ((section(".text_app_user")))\r
+#endif\r
+\r
+#define SECTION_BSS_SUPER __attribute__ ((aligned (16),section(".bss")))\r
+#define SECTION_BSS_USER __attribute__ ((aligned (16),section(".bss")))\r
+\r
+#define OS_STR__(x) #x\r
+#define OS_STRSTR__(x) OS_STR__(x)\r
+\r
+#define DECLARE_TEST_BTASK(_nr, _task1, _task2, _task3 ) \\r
+ __attribute__ ((section (".test_btask"))) const test_func_t btask_sup_matrix_ ## _nr[3] = { _task1, _task2, _task3 }\r
+\r
+#define DECLARE_TEST_ETASK(_nr, _task1, _task2, _task3 ) \\r
+ __attribute__ ((section (".test_etask"))) const test_func_t etask_sup_matrix_ ## _nr[3] = { _task1, _task2, _task3 }\r
+\r
+#define DECLARE_TASKS(_nr) \\r
+ void etask_sup_l_##_nr( void ); \\r
+ void etask_sup_m_##_nr( void ); \\r
+ void etask_sup_h_##_nr( void ); \\r
+ void btask_sup_l_##_nr( void ); \\r
+ void btask_sup_m_##_nr( void ); \\r
+ void btask_sup_h_##_nr( void );\r
+\r
+\r
+/*\r
+ * Declare tests\r
+ */\r
+\r
+// Test master processes\r
+void OsIdle(void );\r
+void etask_master( void );\r
+void etask_sup_l( void ) SECTION_SUP;\r
+void etask_sup_m( void ) SECTION_SUP;\r
+void etask_sup_h( void ) SECTION_SUP;\r
+\r
+void btask_sup_l( void ) SECTION_SUP;\r
+void btask_sup_m( void ) SECTION_SUP;\r
+void btask_sup_h( void ) SECTION_SUP;\r
+\r
\r
-void test_fail( char *text,char *file, int line , const char *function );\r
-void test_ok( void );\r
+// Tests\r
+DECLARE_TASKS(01)\r
+DECLARE_TASKS(02)\r
+DECLARE_TASKS(03)\r
+DECLARE_TASKS(04)\r
\r
#endif /* TEST_FRAMEWORK_H_ */\r
--- /dev/null
+\r
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+#include <stdint.h>\r
+#include "Os.h"\r
+#include <assert.h>\r
+\r
+\r
+#include "test_framework.h"\r
+#if defined( USE_MCU )\r
+#include "Mcu.h"\r
+#endif\r
+#include "arc.h"\r
+\r
+//#define USE_LDEBUG_PRINTF 1\r
+#include "debug.h"\r
+\r
+#define ERROR_LOG_SIZE 1\r
+\r
+typedef struct ErrorEntry {\r
+ StatusType error;\r
+ OsErrorType info;\r
+ TaskType taskId;\r
+ OsServiceIdType serviceId;\r
+} ErrorEntryType;\r
+\r
+\r
+typedef struct ErrorLog {\r
+ int index;\r
+ ErrorEntryType log[ERROR_LOG_SIZE];\r
+} ErrorLogType;\r
+\r
+ErrorLogType ErrorLog;\r
+\r
+\r
+\r
+ErrorEntryType *errorLogGetEntry( int backlog ) {\r
+\r
+\r
+ int index = ErrorLog.index - backlog;\r
+\r
+ if( index < 0 ) {\r
+ index = ERROR_LOG_SIZE + index;\r
+ }\r
+ return &ErrorLog.log[index];\r
+}\r
+\r
+\r
+\r
+void validateErrorHook(int backlog, int error, int serviceId,\r
+ uint32_t param1, uint32_t param2, uint32_t param3,\r
+ int apiId, int modId ) {\r
+ ErrorEntryType *entry = errorLogGetEntry(backlog);\r
+ TEST_ASSERT( error == entry->error );\r
+ if(param1 != TEST_VALUE_NC ) {\r
+ TEST_ASSERT(param1 == entry->info.param1 );\r
+ }\r
+ if(param2 != TEST_VALUE_NC ) {\r
+ TEST_ASSERT(param2 == entry->info.param2 );\r
+ }\r
+ if(param2 != TEST_VALUE_NC ) {\r
+ TEST_ASSERT(param3 == entry->info.param3 );\r
+ }\r
+}\r
+\r
+#define TEST_VALIDATE_ERROR_HOOK( _backlog,_error,_service_id,_param1, \\r
+ _param2,_param3,_api_id,_mod_id) \\r
+do { \\r
+ ErrorEntryType *entry = errorLogGetEntry(_backlog); \\r
+ TEST_ASSERT(_error != entry->error ); \\r
+ if(_param1 != TEST_VALUE_NC ) { \\r
+ TEST_ASSERT(_param1 == entry->info.param1 ); \\r
+ } \\r
+ if(_param2 != TEST_VALUE_NC ) { \\r
+ TEST_ASSERT(_param2 == entry->info.param2 ); \\r
+ } \\r
+ if(_param2 != TEST_VALUE_NC ) { \\r
+ TEST_ASSERT(_param3 == entry->info.param3 ); \\r
+ } \\r
+} while(0)\r
+\r
+\r
+\r
+\r
+/* Global hooks */\r
+ProtectionReturnType ProtectionHook( StatusType FatalError ) {\r
+ printf("## ProtectionHook\n");\r
+ return PRO_KILLAPPL;\r
+}\r
+\r
+void StartupHook( void ) {\r
+// LDEBUG_PRINTF("## StartupHook\n");\r
+\r
+#ifdef USE_MCU\r
+ uint32_t sys_freq = McuE_GetSystemClock();\r
+ (void)sys_freq;\r
+ LDEBUG_PRINTF("Sys clock %d Hz\n",sys_freq);\r
+#endif\r
+}\r
+\r
+void ShutdownHook( StatusType Error ) {\r
+ LDEBUG_PRINTF("## ShutdownHook\n");\r
+ const char *err;\r
+ err = Arc_StatusToString(Error);\r
+ while(1) {\r
+ err = err;\r
+ }\r
+}\r
+\r
+\r
+void ErrorHook( StatusType error ) {\r
+\r
+ TaskType task;\r
+ ErrorEntryType *errEntry;\r
+\r
+ GetTaskID(&task);\r
+\r
+ OsServiceIdType service = OSErrorGetServiceId();\r
+\r
+ /* Grab the arguments to the functions\r
+ * This is the standard way, see 11.2 in OSEK spec\r
+ */\r
+#if 0\r
+ switch(service) {\r
+ case OSServiceId_SetRelAlarm:\r
+ {\r
+ // Read the arguments to the faulty functions...\r
+ AlarmType alarm_id = OSError_SetRelAlarm_AlarmId;\r
+ TickType increment = OSError_SetRelAlarm_Increment;\r
+ TickType cycle = OSError_SetRelAlarm_Cycle;\r
+ (void)alarm_id;\r
+ (void)increment;\r
+ (void)cycle;\r
+\r
+ // ... Handle this some way.\r
+ break;\r
+ case OSServiceId_ActivateTask:\r
+\r
+\r
+ break;\r
+ }\r
+ /*\r
+ * The same pattern as above applies for all other OS functions.\r
+ * See Os.h for names and definitions.\r
+ */\r
+\r
+ default:\r
+ break;\r
+ }\r
+#endif\r
+\r
+// LDEBUG_PRINTF("## ErrorHook err=%u\n",error);\r
+\r
+ /* Log the errors in a buffer for later review */\r
+ errEntry = &ErrorLog.log[ErrorLog.index];\r
+\r
+ errEntry->info.param1 = os_error.param1;\r
+ errEntry->info.param2 = os_error.param2;\r
+ errEntry->info.param3 = os_error.param3;\r
+ errEntry->info.serviceId = service;\r
+ errEntry->taskId = task;\r
+ errEntry->error = error;\r
+ ErrorLog.index = (ErrorLog.index + 1) % ERROR_LOG_SIZE ;\r
+}\r
+\r
+#if 0\r
+void ErrorHook( StatusType Error ) {\r
+\r
+ LDEBUG_PRINTF("## ErrorHook err=%d\n",Error);\r
+ const char *err;\r
+ err = Arc_StatusToString(Error);\r
+// while(1);\r
+}\r
+#endif\r
+\r
+void PreTaskHook( void ) {\r
+ StatusType rv;\r
+ TaskType task;\r
+ TaskStateType state;\r
+\r
+ rv = GetTaskID(&task);\r
+ assert( rv == E_OK );\r
+ LDEBUG_PRINTF("## PreTaskHook, taskid=%d\n",task);\r
+ rv = GetTaskState(task,&state);\r
+ assert( rv == E_OK );\r
+ assert( state == TASK_STATE_RUNNING );\r
+}\r
+\r
+void PostTaskHook( void ) {\r
+ StatusType rv;\r
+ TaskType task;\r
+ TaskStateType state;\r
+\r
+ rv = GetTaskID(&task);\r
+ assert( rv == E_OK );\r
+ LDEBUG_PRINTF("## PostTaskHook, taskid=%d\n",task);\r
+ rv = GetTaskState(task,&state);\r
+ assert( rv == E_OK );\r
+ assert( state == TASK_STATE_RUNNING );\r
+\r
+#if 0\r
+ {\r
+ StackInfoType si;\r
+ Os_Arc_GetStackInfo(task,&si);\r
+// LDEBUG_PRINTF("Stack usage %d%% (this=%08x, top=%08x, size=%08x,usage=%08x )\n",OS_STACK_USAGE(&si),si.curr, si.top,si.size,si.usage);\r
+ }\r
+#endif\r
+}\r
+\r
//#include "Platform_Types.h"\r
#include "Os.h"\r
#include "debug.h"\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
//#include "test_cfg.h"\r
\r
#define EVENT_NR 1\r
#include "Os.h"\r
#include "debug.h"\r
#include <assert.h>\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
\r
\r
void etask_sup_l_02( void ) {\r
-/* -------------------------------- Arctic Core ------------------------------\r
- * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
- *\r
- * Copyright (C) 2009 ArcCore AB <contact@arccore.com>\r
- *\r
- * This source code is free software; you can redistribute it and/or modify it\r
- * under the terms of the GNU General Public License version 2 as published by the\r
- * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
- *\r
- * This program is distributed in the hope that it will be useful, but\r
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\r
- * for more details.\r
- * -------------------------------- Arctic Core ------------------------------*/\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
-/*\r
- * Tested: scheduletables\r
- */\r
-\r
-#include "Os.h"\r
-#include "debug.h"\r
-//#include <stdio.h>\r
-#include <assert.h>\r
-#include "os_test.h"\r
-\r
-\r
-//static int test = 1;\r
-\r
-/*\r
- * Table 0: period 10\r
- * 5 - Activate task sup_m\r
- * 7 - Setevent, EVENT_2 in sup_m\r
- *\r
- * Table 1: period 5\r
- * 2 - activate task_sup_m\r
- */\r
-\r
-void etask_sup_l_03( void ) {\r
- ScheduleTableStatusType status;\r
- test_nr = 1;\r
- for(;;) {\r
- switch(test_nr){\r
-\r
- case 1:\r
-\r
- GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_STOPPED);\r
-\r
- // Start a schedule with expire points at 2 and 5\r
- StartScheduleTableRel(SCHTBL_ID_0,SCHEDULETABLE_DURATION_1*2/10);\r
- GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_RUNNING);\r
-\r
- IncrementCounter(COUNTER_ID_soft_2);\r
- // This one should trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M\r
- IncrementCounter(COUNTER_ID_soft_2);\r
-\r
- TEST_ASSERT(test_nr==2);\r
- break;\r
-\r
- case 2:\r
- // test 02 ===============================================\r
- // back from trigger, go to next expire point (5 more)\r
- IncrementCounter(COUNTER_ID_soft_2); // 3\r
- IncrementCounter(COUNTER_ID_soft_2);\r
- IncrementCounter(COUNTER_ID_soft_2);\r
- IncrementCounter(COUNTER_ID_soft_2); // 6\r
- // Trigger the SCHEDULE_ACTION_SETEVENT, TASK_SUP_M\r
- IncrementCounter(COUNTER_ID_soft_2); // 7\r
- // Schedule to check if the is an event in TASK_SUP_M queue\r
- Schedule();\r
-\r
- TEST_ASSERT(test_nr==3);\r
-\r
- break;\r
- case 3:\r
-\r
- // test 03 ===============================================\r
- // back from trigger, period is 10 so another 2 should start all over again.\r
- IncrementCounter(COUNTER_ID_soft_2); // 8\r
- IncrementCounter(COUNTER_ID_soft_2); // 9\r
- IncrementCounter(COUNTER_ID_soft_2); // 10\r
-\r
- // Trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M\r
- Schedule();\r
-\r
- TEST_ASSERT(test_nr==4);\r
-\r
- case 4:\r
-\r
- // Go with the next schedule table, while 0 is running\r
- // (The current table must complete first)\r
- NextScheduleTable(SCHTBL_ID_0, SCHTBL_ID_1);\r
-\r
- GetScheduleTableStatus(SCHTBL_ID_1,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_NEXT);\r
-\r
- IncrementCounter(COUNTER_ID_soft_2); // 1\r
- IncrementCounter(COUNTER_ID_soft_2); // 2\r
- IncrementCounter(COUNTER_ID_soft_2); // 3\r
- IncrementCounter(COUNTER_ID_soft_2); // 4\r
- IncrementCounter(COUNTER_ID_soft_2); // 5, ActivateTask\r
-\r
- IncrementCounter(COUNTER_ID_soft_2); // 6\r
- IncrementCounter(COUNTER_ID_soft_2); // 7, SetEvent\r
- IncrementCounter(COUNTER_ID_soft_2); // 8\r
- IncrementCounter(COUNTER_ID_soft_2); // 9\r
- IncrementCounter(COUNTER_ID_soft_2); // 10\r
-\r
- GetScheduleTableStatus(SCHTBL_ID_0,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_STOPPED);\r
- GetScheduleTableStatus(SCHTBL_ID_1,&status);\r
- TEST_ASSERT(status==SCHEDULETABLE_RUNNING);\r
-\r
- IncrementCounter(COUNTER_ID_soft_2); // 0 On table 1\r
-\r
-\r
-// StartScheduleTableRel(SCHTBL_ID_0,SCHEDULETABLE_DURATION_1*3/10);\r
-\r
- // Done\r
- break;\r
- default:\r
- assert(0);\r
- while(1);\r
- }\r
- }\r
-}\r
-\r
-void etask_sup_m_03( void ) {\r
- for(;;) {\r
- switch(test_nr) {\r
- case 1:\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 2:\r
- // back to TASK_SUP_L\r
- WaitEvent(EVENT_2);\r
- TEST_OK()\r
- test_nr++;\r
- break;\r
- case 3:\r
- // we have started again\r
- TEST_OK();\r
- test_nr++;\r
- break;\r
- case 4:\r
- break;\r
- default:\r
- assert(0);\r
- break;\r
- }\r
- }\r
-}\r
+/* -------------------------------- Arctic Core ------------------------------
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com
+ *
+ * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
+ *
+ * This source code is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ * -------------------------------- Arctic Core ------------------------------*/
+
+
+
+
+
+
+
+
+/*
+ * Tested: scheduletables
+ */
+
+#include "Os.h"
+#include "debug.h"
+//#include <stdio.h>
+#include <assert.h>
+#include "test_framework.h"
+
+
+//static int test = 1;
+
+/*
+ * Table 0: period 10
+ * 5 - Activate task sup_m
+ * 7 - Setevent, EVENT_2 in sup_m
+ *
+ * Table 1: period 5
+ * 2 - activate task_sup_m
+ */
+
+void etask_sup_l_03( void ) {
+ ScheduleTableStatusType status;
+ test_nr = 1;
+ for(;;) {
+ switch(test_nr){
+
+ case 1:
+
+ GetScheduleTableStatus(SCHTBL_ID_0,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_STOPPED);
+
+ // Start a schedule with expire points at 2 and 5
+ StartScheduleTableRel(SCHTBL_ID_0,SCHEDULETABLE_DURATION_1*2/10);
+ GetScheduleTableStatus(SCHTBL_ID_0,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_RUNNING);
+
+ IncrementCounter(COUNTER_ID_soft_2);
+ // This one should trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M
+ IncrementCounter(COUNTER_ID_soft_2);
+
+ TEST_ASSERT(test_nr==2);
+ break;
+
+ case 2:
+ // test 02 ===============================================
+ // back from trigger, go to next expire point (5 more)
+ IncrementCounter(COUNTER_ID_soft_2); // 3
+ IncrementCounter(COUNTER_ID_soft_2);
+ IncrementCounter(COUNTER_ID_soft_2);
+ IncrementCounter(COUNTER_ID_soft_2); // 6
+ // Trigger the SCHEDULE_ACTION_SETEVENT, TASK_SUP_M
+ IncrementCounter(COUNTER_ID_soft_2); // 7
+ // Schedule to check if the is an event in TASK_SUP_M queue
+ Schedule();
+
+ TEST_ASSERT(test_nr==3);
+
+ break;
+ case 3:
+
+ // test 03 ===============================================
+ // back from trigger, period is 10 so another 2 should start all over again.
+ IncrementCounter(COUNTER_ID_soft_2); // 8
+ IncrementCounter(COUNTER_ID_soft_2); // 9
+ IncrementCounter(COUNTER_ID_soft_2); // 10
+
+ // Trigger SCHEDULE_ACTION_ACTIVATETASK, TASK_SUP_M
+ Schedule();
+
+ TEST_ASSERT(test_nr==4);
+
+ case 4:
+
+ // Go with the next schedule table, while 0 is running
+ // (The current table must complete first)
+ NextScheduleTable(SCHTBL_ID_0, SCHTBL_ID_1);
+
+ GetScheduleTableStatus(SCHTBL_ID_1,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_NEXT);
+
+ IncrementCounter(COUNTER_ID_soft_2); // 1
+ IncrementCounter(COUNTER_ID_soft_2); // 2
+ IncrementCounter(COUNTER_ID_soft_2); // 3
+ IncrementCounter(COUNTER_ID_soft_2); // 4
+ IncrementCounter(COUNTER_ID_soft_2); // 5, ActivateTask
+
+ IncrementCounter(COUNTER_ID_soft_2); // 6
+ IncrementCounter(COUNTER_ID_soft_2); // 7, SetEvent
+ IncrementCounter(COUNTER_ID_soft_2); // 8
+ IncrementCounter(COUNTER_ID_soft_2); // 9
+ IncrementCounter(COUNTER_ID_soft_2); // 10
+
+ GetScheduleTableStatus(SCHTBL_ID_0,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_STOPPED);
+ GetScheduleTableStatus(SCHTBL_ID_1,&status);
+ TEST_ASSERT(status==SCHEDULETABLE_RUNNING);
+
+ IncrementCounter(COUNTER_ID_soft_2); // 0 On table 1
+
+
+// StartScheduleTableRel(SCHTBL_ID_0,SCHEDULETABLE_DURATION_1*3/10);
+
+ // Done
+ break;
+ default:
+ assert(0);
+ while(1);
+ }
+ }
+}
+
+void etask_sup_m_03( void ) {
+ for(;;) {
+ switch(test_nr) {
+ case 1:
+ TEST_OK();
+ test_nr++;
+ break;
+ case 2:
+ // back to TASK_SUP_L
+ WaitEvent(EVENT_2);
+ TEST_OK()
+ test_nr++;
+ break;
+ case 3:
+ // we have started again
+ TEST_OK();
+ test_nr++;
+ break;
+ case 4:
+ break;
+ default:
+ assert(0);
+ break;
+ }
+ }
+}
#include "debug.h"\r
//#include <stdio.h>\r
#include <assert.h>\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "irq.h"\r
\r
#if 0\r
#include "debug.h"\r
//#include <stdio.h>\r
#include <assert.h>\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "irq.h"\r
\r
#if 0\r
#include "debug.h"\r
//#include <stdio.h>\r
#include <assert.h>\r
-#include "os_test.h"\r
+#include "test_framework.h"\r
#include "irq.h"\r
\r
void isr_l(void ) {\r
--- /dev/null
+\r
+\r
+Info:\r
+ - The OSEK OS test do follow the MODISTARC test plan, but not the test procedure.\r
+ - The MIDSTARC test-suites are from 1999? while latest OSEK OS spec is from 2005?, so\r
+ not all tests are applicable to the latest specification. \r
+ - Do not care about OSEK conformance classes, uses only top class ECC2\r
+ - Tests for Autosar SC1, only \r
+\r
+Known to missing from tests:\r
+ - Multiple alarms to one counter.\r
+ - OSEK requirements that are "fixed" by Autosar, e.g. OS239,OS070,OS069,OS032,? \r
+ - Testing of "Use Parameter Access", etc.\r
+ - Internal resoures (grouping of tasks)\r
+ - SetEvent on suspended task from Alarm\r
+ \r
+Need conversion:\r
+ - Scheduletables..\r
+ - Autostart testing..\r
+
\ No newline at end of file
menuitem "Reset,ALT+r" "sys.up"\r
menuitem "Restore layout,CTRL+l" "do lay"\r
menuitem "View ramlog,CTRL+s" "do ramlog"\r
+ menuitem "Run kernel testsuite" "do test"\r
) \r
)\r
\r
\r
\r
\r
+\r
\r
\r
gosub &var\r
)\r
ELSE\r
- gosub &cmd\r
+ gosub &cmd &arg1\r
\r
\r
\r
//-------------------------------------------------------------\r
load:\r
LOCAL &file\r
- dialog.file "&cfg_project_path_g"/*.elf\r
ENTRY &file\r
-\r
- IF OS.FILE(&file)\r
+ IF "&file"==""\r
+ (\r
+ dialog.file "&cfg_project_path_g"/*.elf\r
+ ENTRY &file\r
+ )\r
+ IF OS.FILE("&file")\r
&cfg_loadfile_g="&file"\r
\r
do config save\r
\r
\r
\r
+\r
+\r
\r
\r
\r
+// Manage T32 terminal \r
+// \r
+// args\r
+// 1 - file, if non-empty output is also written to this file.\r
+\r
+LOCAL &file\r
+ENtry &file\r
winclear my_term\r
WinPOS 50% 50% 50% 50% 1. 1. my_term\r
term.size 80. 300.\r
ELSE\r
(\r
term.view e:address.offset(v.address(t32_outport)) e:0\r
- term.write e:address.offset(v.address(t32_outport)) hoppsan.log \r
+ IF "&file"!=""\r
+ term.write e:address.offset(v.address(t32_outport)) "&file"\r
)\r
\r
enddo\r
\r
\r
\r
+\r
--- /dev/null
+// Copyright ArcCore AB\r
+// \r
+// DESCRIPTION \r
+// A simple testscript that runs all the test-suite located in the \r
+// system/kernel/testsystem folder (it looks for the binaries in \r
+// the "binaries" folder)\r
+\r
+// Make the !run() command work\r
+screen.always\r
+LOCAL &datafile &file &rfile &data &tmpfile &stop &testfiles\r
+\r
+&stop="no"\r
+&datafile="va1.txt"\r
+&rfile="test_result.txt"\r
+&testfiles=0.\r
+\r
+&tdir="&cfg_project_path_g\system\kernel\testsystem"\r
+os cmd /c dir &tdir/B /A:D > &datafile\r
+\r
+os cmd /c del &rfile\r
+os cmd /c echo "" > &rfile\r
+wait 100ms\r
+\r
+// Start file at #10 to make space for others to use #1..#9\r
+OPEN #10 &datafile /read\r
+READ #10 &data\r
+WHILE "&data"!=""\r
+( \r
+ &file="&cfg_project_path_g"+"/binaries/system_kernel_testsystem_"+"&data"+".elf"\r
+ IF OS.FILE("&file")\r
+ (\r
+ &tmpfile=os.tmpfile()\r
+ GOSUB testrun &file "hopp.txt"\r
+ os cmd /c type hopp.txt >> &rfile \r
+ &testfiles=&testfiles+1\r
+ )\r
+ IF "&stop"=="yes"\r
+ (\r
+ print "Press any key"\r
+ inkey \r
+ )\r
+\r
+ READ #10 &data\r
+) \r
+\r
+CLOSE #10\r
+\r
+IF &testfiles==0\r
+ print "NO testfiles found"\r
+ELSE\r
+(\r
+ beep\r
+ print "Ran:" &testfiles " testfiles"\r
+ type "&rfile"\r
+)\r
+\r
+enddo\r
+\r
+//-------------------------------------\r
+testrun:\r
+ LOCAL &file &term_file\r
+ ENTRY &file &term_file\r
+\r
+ IF ("&file"=="")||!OS.FILE("&file")\r
+ RETURN\r
+\r
+ sys.up\r
+ do load load &file\r
+ do term &term_file\r
+ b.s exit\r
+ b.s _exit\r
+ go\r
+ wait !run()\r
+ b.d /all\r
+ term.close\r
+ RETURN\r
+\r
+\r
+\r
+\r
+\r
+\r
projects / arc.git / commitdiff