\r
#define PORT_NOT_CONFIGURED 0x00000000\r
\r
-#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30) // GIO Emulation B register\r
-#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50) // GIO Pull Select Register A ??\r
-#define PORT_2_BASE ((Port_RegisterType *)0xFFF7B848) // N2HET1\r
+#define PORT_0_BASE ((Port_RegisterType *)0xFFF7BC30)\r
+#define PORT_1_BASE ((Port_RegisterType *)0xFFF7BC50)\r
+#define PORT_2_BASE ((Port_RegisterType *)0xFFF7B848) // N2HET1 Base\r
#define PORT_3_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_4_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
#define PORT_5_BASE ((Port_RegisterType *)PORT_NOT_CONFIGURED)\r
PORT_10_BASE,\r
};\r
\r
-\r
+typedef volatile uint32 PinMuxBase;\r
+\r
+#define PINMUX0 ((PinMuxBase *)0xFFFFEB10)\r
+#define PINMUX1 ((PinMuxBase *)0xFFFFEB14)\r
+#define PINMUX2 ((PinMuxBase *)0xFFFFEB18)\r
+#define PINMUX3 ((PinMuxBase *)0xFFFFEB1C)\r
+#define PINMUX4 ((PinMuxBase *)0xFFFFEB20)\r
+#define PINMUX5 ((PinMuxBase *)0xFFFFEB24)\r
+#define PINMUX6 ((PinMuxBase *)0xFFFFEB28)\r
+#define PINMUX7 ((PinMuxBase *)0xFFFFEB2C)\r
+#define PINMUX8 ((PinMuxBase *)0xFFFFEB30)\r
+#define PINMUX9 ((PinMuxBase *)0xFFFFEB34)\r
+#define PINMUX10 ((PinMuxBase *)0xFFFFEB38)\r
+#define PINMUX11 ((PinMuxBase *)0xFFFFEB3C)\r
+#define PINMUX12 ((PinMuxBase *)0xFFFFEB40)\r
+#define PINMUX13 ((PinMuxBase *)0xFFFFEB44)\r
+#define PINMUX14 ((PinMuxBase *)0xFFFFEB48)\r
+#define PINMUX15 ((PinMuxBase *)0xFFFFEB4C)\r
+#define PINMUX16 ((PinMuxBase *)0xFFFFEB50)\r
+#define PINMUX17 ((PinMuxBase *)0xFFFFEB54)\r
+#define PINMUX18 ((PinMuxBase *)0xFFFFEB58)\r
+#define PINMUX19 ((PinMuxBase *)0xFFFFEB5C)\r
+#define PINMUX20 ((PinMuxBase *)0xFFFFEB60)\r
+#define PINMUX21 ((PinMuxBase *)0xFFFFEB64)\r
+#define PINMUX22 ((PinMuxBase *)0xFFFFEB68)\r
+#define PINMUX23 ((PinMuxBase *)0xFFFFEB6C)\r
+#define PINMUX24 ((PinMuxBase *)0xFFFFEB70)\r
+#define PINMUX25 ((PinMuxBase *)0xFFFFEB74)\r
+#define PINMUX26 ((PinMuxBase *)0xFFFFEB78)\r
+#define PINMUX27 ((PinMuxBase *)0xFFFFEB7C)\r
+#define PINMUX28 ((PinMuxBase *)0xFFFFEB80)\r
+#define PINMUX29 ((PinMuxBase *)0xFFFFEB84)\r
+#define PINMUX30 ((PinMuxBase *)0xFFFFEB88)\r
+\r
+static PinMuxBase * PinMux_Base[] =\r
+{\r
+ PINMUX0,\r
+ PINMUX1,\r
+ PINMUX2,\r
+ PINMUX3,\r
+ PINMUX4,\r
+ PINMUX5,\r
+ PINMUX6,\r
+ PINMUX7,\r
+ PINMUX8,\r
+ PINMUX9,\r
+ PINMUX10,\r
+ PINMUX11,\r
+ PINMUX12,\r
+ PINMUX13,\r
+ PINMUX14,\r
+ PINMUX15,\r
+ PINMUX16,\r
+ PINMUX17,\r
+ PINMUX18,\r
+ PINMUX19,\r
+ PINMUX20,\r
+ PINMUX21,\r
+ PINMUX22,\r
+ PINMUX23,\r
+ PINMUX24,\r
+ PINMUX25,\r
+ PINMUX26,\r
+ PINMUX27,\r
+ PINMUX28,\r
+ PINMUX29,\r
+ PINMUX30\r
+};\r
\r
static Port_StateType _portState = PORT_UNINITIALIZED;\r
static const Port_ConfigType * _configPtr = &PortConfigData;\r
uint32 mask = GET_PIN_MASK(_configPtr->pins[pinNumber].pin);\r
uint16 conf = _configPtr->pins[pinNumber].conf;\r
\r
+ uint32 pinmux = _configPtr->pins[pinNumber].pinmux;\r
+ uint8 pinmuxFunctionNum = _configPtr->pins[pinNumber].pinmuxFunctionNum;\r
+ uint8 pinmuxBaseNum = _configPtr->pins[pinNumber].pinmuxBaseNum;\r
+\r
+ /* Enable Pin Muxing */\r
+ kickerReg->KICKER0 = 0x83E70B13;\r
+ kickerReg->KICKER1 = 0x95A4F1E0;\r
+\r
+ /* ex.: Hack to connect N2HET1[27] (function 2) to pin A9 */\r
+ *PinMux_Base[pinmuxBaseNum] &= (~(0xFF << pinmux));//\r
+ *PinMux_Base[pinmuxBaseNum] |= (~(pinmuxFunctionNum << pinmux));\r
+\r
+ /* Disable Pin Muxing */\r
+ kickerReg->KICKER0 = 0x00000000;\r
+ kickerReg->KICKER1 = 0x00000000;\r
+\r
if (conf & PORT_FUNC) {\r
// Don't do anything, let each driver configure???\r
return;\r
}\r
\r
\r
-\r
void Port_Init(const Port_ConfigType *configType) {\r
VALIDATE_PARAM_CONFIG(configType, PORT_INIT_ID);\r
\r
_configPtr = (Port_ConfigType *)configType;\r
\r
- // Bring GIO register out of reset.\r
+ /* Bring GIO register out of reset. */\r
gioREG->GCR0 = 1;\r
-\r
- /* Hack to connect N2HET1[27] (function 2) to pin A9 */\r
- *(volatile uint32*)0xFFFFEB10 &= ~0xFF000000;\r
- *(volatile uint32*)0xFFFFEB10 |= ~0x04000000;\r
+ gioREG->INTENACLR = 0xFF; // Interrupt Enable Clear Register\r
+ gioREG->LVLCLR = 0xFF; // Interrupt Priority Clear Register\r
\r
for (uint16 i = 0; i < PORT_NUMBER_OF_PINS; i++) {\r
Port_RefreshPin(i);\r
VALIDATE_STATE_INIT(PORT_SET_PIN_DIRECTION_ID);\r
VALIDATE_PARAM_PIN(pin, PORT_SET_PIN_DIRECTION_ID);\r
\r
- uint8 port = GET_PIN_PORT(pin);\r
- uint32 mask = GET_PIN_MASK(pin);\r
+ uint8 port = GET_PIN_PORT(pin); // ex.: LED1 - 0x021b >> 8 = 2 (uint8)\r
+ uint32 mask = GET_PIN_MASK(pin); // ex.: LED1 - 1 << (0x1b) = 0x08000000 (uint32)\r
\r
if (direction & PORT_PIN_IN) {\r
Port_Base[port]->DIR |= mask;\r
VALIDATE_STATE_INIT(PORT_SET_PIN_MODE_ID);\r
VALIDATE_PARAM_PIN(Pin, PORT_SET_PIN_MODE_ID);\r
\r
+ #if (PORT_DEV_ERROR_DETECT == STD_ON)\r
+ Det_ReportError(MODULE_ID_PORT, 0, PORT_SET_PIN_MODE_ID, PORT_E_MODE_UNCHANGEABLE );\r
+ #endif\r
+\r
uint8 port = GET_PIN_PORT(Pin);\r
uint8 pin = GET_PIN_PIN(Pin);\r
uint32 mask = GET_PIN_MASK(Pin);\r