Added SPE support.

diff --git a/arch/ppc/mpc55xx/kernel/arch_krn.sx b/arch/ppc/mpc55xx/kernel/arch_krn.sx
index bf2ab977894aca251c577d7116f916bdc9ebafad..49b8ecff9f7e8b6e0ff542de774f209a7b5cda2c 100644 (file)
--- a/arch/ppc/mpc55xx/kernel/arch_krn.sx
+++ b/arch/ppc/mpc55xx/kernel/arch_krn.sx
@@ -48,13 +48,25 @@
 .extern os_intc_pcb_tbl\r
 .extern os_intc_types_tbl\r
 .extern os_sys\r
+.extern Os_ArchPanic\r
+\r
+#if defined(CFG_VLE)\r
+#define lis            e_lis\r
+#define li             se_li\r
+#define lwz        e_lwz\r
+#define stwu   e_stwu\r
+#define stw            e_stw\r
+#define b              e_b\r
+#define addi   e_addi          /* true ?*/\r
+#define subi   e_subi          /* true ?*/\r
+#endif         \r
 \r
 /* ----------------------------[private define]------------------------------*/\r
 \r
-#define INTC_IACKR_PRC0                0xfff48010  /* MPC551x CPU #0  */ \r
-#define INTC_EOIR_PRC0         0xfff48018  /* MPC551x CPU #0  */\r
-#define INTC_IACKR                     0xfff48010  /* MPC555x         */\r
-#define INTC_EOIR                      0xfff48018  /* MPC555x         */\r
+#define INTC_IACKR_PRC0                0xfff48010 \r
+#define INTC_EOIR_PRC0         0xfff48018\r
+#define INTC_IACKR                     0xfff48010\r
+#define INTC_EOIR                      0xfff48018\r
 #define INTC_SSCIR0                    0xfff48020\r
 \r
 /* ----------------------------[private macro]-------------------------------*/\r
@@ -109,8 +121,8 @@ Os_ArchSwapContext:
        /* Save context indicator */\r
        li              r0,FUNC_PATTERN\r
        stw             r0,FUNC_FRM_PATTERN(sp)\r
-       \r
-       /* Save registers preserved by function call */\r
+\r
+#if defined(CFG_SPE)\r
        stw             r14, FUNC_FRM_R14(sp)\r
        stw             r15, FUNC_FRM_R15(sp)\r
        stw             r16, FUNC_FRM_R16(sp)\r
@@ -130,6 +142,27 @@ Os_ArchSwapContext:
        stw             r30, FUNC_FRM_R30(sp)\r
        stw             r31, FUNC_FRM_R31(sp)\r
 \r
+#else\r
+       /* Save registers preserved by function call */\r
+       stw             r14, FUNC_FRM_R14(sp)\r
+       stw             r15, FUNC_FRM_R15(sp)\r
+       stw             r16, FUNC_FRM_R16(sp)\r
+       stw             r17, FUNC_FRM_R17(sp)\r
+       stw             r18, FUNC_FRM_R18(sp)\r
+       stw             r19, FUNC_FRM_R19(sp)\r
+       stw             r20, FUNC_FRM_R20(sp)\r
+       stw             r21, FUNC_FRM_R21(sp)\r
+       stw             r22, FUNC_FRM_R22(sp)\r
+       stw             r23, FUNC_FRM_R23(sp)\r
+       stw             r24, FUNC_FRM_R24(sp)\r
+       stw             r25, FUNC_FRM_R25(sp)\r
+       stw             r26, FUNC_FRM_R26(sp)\r
+       stw             r27, FUNC_FRM_R27(sp)\r
+       stw             r28, FUNC_FRM_R28(sp)\r
+       stw             r29, FUNC_FRM_R29(sp)\r
+       stw             r30, FUNC_FRM_R30(sp)\r
+       stw             r31, FUNC_FRM_R31(sp)\r
+#endif\r
 \r
        /* Save stack ptr... */\r
        stw             sp,PCB_STACK_CURR_P(r3)\r
@@ -167,6 +200,27 @@ Os_ArchSwapContextTo:
        b               Os_ArchPanic\r
 \r
 restoreFuncContext:\r
+#if defined(CFG_SPE)\r
+       evldd   r14, FUNC_FRM_R14(sp)\r
+       evldd   r15, FUNC_FRM_R15(sp)\r
+       evldd   r16, FUNC_FRM_R16(sp)\r
+       evldd   r17, FUNC_FRM_R17(sp)\r
+       evldd   r18, FUNC_FRM_R18(sp)\r
+       evldd   r19, FUNC_FRM_R19(sp)\r
+       evldd   r20, FUNC_FRM_R20(sp)\r
+       evldd   r21, FUNC_FRM_R21(sp)\r
+       evldd   r22, FUNC_FRM_R22(sp)\r
+       evldd   r23, FUNC_FRM_R23(sp)\r
+       evldd   r24, FUNC_FRM_R24(sp)\r
+       evldd   r25, FUNC_FRM_R25(sp)\r
+       evldd   r26, FUNC_FRM_R26(sp)\r
+       evldd   r27, FUNC_FRM_R27(sp)\r
+       evldd   r28, FUNC_FRM_R28(sp)\r
+       evldd   r29, FUNC_FRM_R29(sp)\r
+       evldd   r30, FUNC_FRM_R30(sp)\r
+       evldd   r31, FUNC_FRM_R31(sp)\r
+       addi    sp,sp,(FUNC_FRM_SIZE)\r
+#else \r
        lwz             r14, FUNC_FRM_R14(sp)\r
        lwz             r15, FUNC_FRM_R15(sp)\r
        lwz             r16, FUNC_FRM_R16(sp)\r
@@ -186,7 +240,7 @@ restoreFuncContext:
        lwz             r30, FUNC_FRM_R30(sp)\r
        lwz             r31, FUNC_FRM_R31(sp)\r
        addi    sp,sp,(FUNC_FRM_SIZE)\r
-       \r
+#endif \r
        /* TODO: Call Os_PosttaskHook()? */\r
        \r
        blr\r
@@ -221,7 +275,59 @@ exception_IVOR4:
        \r
        li              r3,4\r
        stw     r3, EXC_FRM_VECTOR(sp)\r
+#if defined(CFG_SPE)   \r
+\r
+       /* Enable SPE (exceptions turns it off) */\r
+       mfmsr           r3\r
+    oris               r3,r3,0x0200\r
+       mtmsr           r3\r
+       isync\r
+\r
+       /* Create the frame */\r
+       addi    sp,sp,-ISR_FRM_SIZE\r
+       evstdd          r3, ISR_FRM_R3(sp)              /* Save work reg */     \r
+       \r
+       /* SPEFSCR      */\r
+       mfspr           r3,SPR_SPEFSCR\r
+       clrlwi          r3,r3,24                                /* Mask off non-status bits */\r
+       stw                     r3,ISR_FRM_SPE_FSCR(sp)\r
+\r
+       /* Save SPE acc  */\r
+       evsubfw         r3,r3,r3                                /* zero r3 */\r
+       evaddumiaaw r3,r3                                       /* Add r3 = r3 + acc -> r3 = acc */\r
+       evstdd          r3,ISR_FRM_SPE_ACC(r1)\r
        \r
+       evstdd          r0, ISR_FRM_R0(sp)\r
+       evstdd          r4, ISR_FRM_R4(sp)\r
+       evstdd          r5, ISR_FRM_R5(sp)\r
+       evstdd          r6, ISR_FRM_R6(sp)\r
+       evstdd          r7, ISR_FRM_R7(sp)\r
+       evstdd          r8, ISR_FRM_R8(sp)\r
+       evstdd          r9, ISR_FRM_R9(sp)\r
+       evstdd          r10, ISR_FRM_R10(sp)\r
+       evstdd          r11, ISR_FRM_R11(sp)\r
+       evstdd          r12, ISR_FRM_R12(sp)\r
+       evstdd          r14, ISR_FRM_R14(sp)\r
+       evstdd          r15, ISR_FRM_R15(sp)\r
+       evstdd          r16, ISR_FRM_R16(sp)\r
+       evstdd          r17, ISR_FRM_R17(sp)\r
+       evstdd          r18, ISR_FRM_R18(sp)\r
+       evstdd          r19, ISR_FRM_R19(sp)\r
+       evstdd          r20, ISR_FRM_R20(sp)\r
+       evstdd          r21, ISR_FRM_R21(sp)\r
+       evstdd          r22, ISR_FRM_R22(sp)\r
+       evstdd          r23, ISR_FRM_R23(sp)\r
+       evstdd          r24, ISR_FRM_R24(sp)\r
+       evstdd          r25, ISR_FRM_R25(sp)\r
+       evstdd          r26, ISR_FRM_R26(sp)\r
+       evstdd          r27, ISR_FRM_R27(sp)\r
+       evstdd          r28, ISR_FRM_R28(sp)\r
+       evstdd          r29, ISR_FRM_R29(sp)\r
+       evstdd          r30, ISR_FRM_R30(sp)\r
+       addi            sp,sp,8\r
+       evstdd          r31, (ISR_FRM_R31-8)(sp)\r
+       addi            sp,sp,-8\r
+#else\r
        /* Save the ISR frame */\r
        addi    sp,sp,-ISR_FRM_SIZE\r
        stw             r0, ISR_FRM_R0(sp)\r
@@ -252,20 +358,20 @@ exception_IVOR4:
        stw             r29, ISR_FRM_R29(sp)\r
        stw             r30, ISR_FRM_R30(sp)\r
        stw             r31, ISR_FRM_R31(sp)\r
-\r
+#endif\r
        \r
        li              r3,ISR_PATTERN\r
        stw             r3,ISR_FRM_PATTERN(sp)\r
-       // Save the stack so it later can be saved in the pcb   \r
+       /* Save the stack so it later can be saved in the pcb */        \r
        mr              r4,sp                   \r
        \r
-       // Switch to interrupt stack if at depth 0\r
-       // Load the value os_sys.int_nest_cnt\r
+       /* Switch to interrupt stack if at depth 0 */\r
+       /* Load the value os_sys.int_nest_cnt */\r
        LOAD_IND_32(r3,os_sys+SYS_INT_NEST_CNT)\r
        cmpli   0,r3,0\r
        bne-    on_int_stack\r
 \r
-       // Load the interrupt stack\r
+       /* Load the interrupt stack */\r
        LOAD_IND_32(r3,os_sys+SYS_INT_STACK)\r
 \r
 on_int_stack:\r
@@ -279,7 +385,6 @@ on_int_stack:
 #endif\r
        /* Check for 0 entry */\r
        mr              r5,r6\r
-       extrwi  r5,r5,9,21\r
        cmpli   0,r5,0\r
        bne+    vectorOk\r
        /* The entry was 0, call panic */\r
@@ -289,6 +394,7 @@ on_int_stack:
        b               Os_ArchPanic\r
        \r
 vectorOk:\r
+       extrwi  r5,r5,9,21\r
        /* Check for soft INT */\r
        cmpli   0,r5,7\r
        bgt             noSoftInt\r
@@ -315,7 +421,50 @@ noSoftInt:
        mr              sp,r3\r
 \r
        /* Restore */\r
-restoreIsrContext:             \r
+restoreIsrContext:\r
+#if defined(CFG_SPE) \r
+\r
+       // Restore SPE control/status reg.\r
+       lwz             r3,ISR_FRM_SPE_FSCR(sp)\r
+       mtspr   SPR_CSRR0,r3\r
+\r
+       /* Restore SPE acc */\r
+       evldd r3,ISR_FRM_SPE_ACC(r1)\r
+       evmra r3,r3\r
+       \r
+\r
+       evldd   r0, ISR_FRM_R0(sp)\r
+       evldd   r3, ISR_FRM_R4(sp)\r
+       evldd   r4, ISR_FRM_R4(sp)\r
+       evldd   r5, ISR_FRM_R5(sp)\r
+       evldd   r6, ISR_FRM_R6(sp)\r
+       evldd   r7, ISR_FRM_R7(sp)\r
+       evldd   r8, ISR_FRM_R8(sp)\r
+       evldd   r9, ISR_FRM_R9(sp)\r
+       evldd   r10, ISR_FRM_R10(sp)\r
+       evldd   r11, ISR_FRM_R11(sp)\r
+       evldd   r12, ISR_FRM_R12(sp)\r
+       evldd   r14, ISR_FRM_R14(sp)\r
+       evldd   r15, ISR_FRM_R15(sp)\r
+       evldd   r16, ISR_FRM_R16(sp)\r
+       evldd   r17, ISR_FRM_R17(sp)\r
+       evldd   r18, ISR_FRM_R18(sp)\r
+       evldd   r19, ISR_FRM_R19(sp)\r
+       evldd   r20, ISR_FRM_R20(sp)\r
+       evldd   r21, ISR_FRM_R21(sp)\r
+       evldd   r22, ISR_FRM_R22(sp)\r
+       evldd   r23, ISR_FRM_R23(sp)\r
+       evldd   r24, ISR_FRM_R24(sp)\r
+       evldd   r25, ISR_FRM_R25(sp)\r
+       evldd   r26, ISR_FRM_R26(sp)\r
+       evldd   r27, ISR_FRM_R27(sp)\r
+       evldd   r28, ISR_FRM_R28(sp)\r
+       evldd   r29, ISR_FRM_R29(sp)\r
+       evldd   r30, ISR_FRM_R30(sp)\r
+       addi    sp,sp,8\r
+       evldd   r31, (ISR_FRM_R31-8)(sp)\r
+       addi    sp,sp,-8\r
+#else\r
        lwz             r0, ISR_FRM_R0(sp)\r
        lwz             r4, ISR_FRM_R4(sp)\r
        lwz             r5, ISR_FRM_R5(sp)\r
@@ -344,6 +493,7 @@ restoreIsrContext:
        lwz             r29, ISR_FRM_R29(sp)\r
        lwz             r30, ISR_FRM_R30(sp)\r
        lwz             r31, ISR_FRM_R31(sp)\r
+#endif \r
        \r
        /* back to the exception frame */\r
        addi    sp,sp,ISR_FRM_SIZE\r
@@ -374,11 +524,11 @@ exception_IVOR10:
     stwu       r3,-8(sp)\r
     stw        r4,4(sp)\r
 \r
-    # ack dec int\r
+    /* ack dec int */\r
     lis        r3,0x0800\r
     mtspr   SPR_TSR,r3\r
 \r
-    # Set soft int\r
+    /* Set soft int */\r
     li         r4,2\r
     lis     r3, INTC_SSCIR7@ha\r
     stb     r4, INTC_SSCIR7@l(r3)\r
@@ -389,9 +539,6 @@ exception_IVOR10:
     rfi\r
 \r
 \r
-\r
-\r
-\r
 /* Getting here means that the exception stack is started with:\r
  * sp - saved\r
  * r3 - saved and contains the exception number \r
@@ -399,9 +546,11 @@ exception_IVOR10:
 handleException:\r
        b  handleException              \r
        \r
-# Force this jump table to this address to match the\r
-# value written to z1 IVPR\r
+#if defined(__GNUC__)  \r
 .section ".exception_tbl","ax"\r
+#elif defined(__CWCC__)\r
+.section .exception_tbl,4,"rw"\r
+#endif\r
 .balign 0x1000\r
 .global exception_tbl\r
 \r
@@ -423,11 +572,11 @@ exception_tbl:
        EXC_TABLE_CODE(12)\r
        EXC_TABLE_CODE(13)\r
        EXC_TABLE_CODE(14)\r
-\r
-\r
-\r
-// ------------------------------------------------------------------\r
-\r
+#if defined(CFG_SPE)\r
+       EXC_TABLE_CODE(32)\r
+       EXC_TABLE_CODE(33)\r
+       EXC_TABLE_CODE(34)\r
+#endif\r
 \r
 \r
 \r

diff --git a/arch/ppc/mpc55xx/kernel/arch_offset.c b/arch/ppc/mpc55xx/kernel/arch_offset.c
index eb27533ec40f2496f96b9a5c363e47960e116476..49c3c57ce614049ea4f59f91554f2ca6e53d0577 100644 (file)
--- a/arch/ppc/mpc55xx/kernel/arch_offset.c
+++ b/arch/ppc/mpc55xx/kernel/arch_offset.c
@@ -42,6 +42,7 @@ void  oil_foo(void) {
        DECLARE(EXC_FRM_R3,             offsetof(Os_ExceptionFrameType, r3));\r
        DECLARE(EXC_FRM_VECTOR, offsetof(Os_ExceptionFrameType, vector));\r
 \r
+\r
        DECLARE(FUNC_FRM_SIZE,  sizeof(Os_FuncFrameType));\r
        DECLARE(FUNC_FRM_CR, offsetof(Os_FuncFrameType,cr));\r
        DECLARE(FUNC_FRM_LR, offsetof(Os_FuncFrameType,lr));\r
@@ -65,6 +66,12 @@ void  oil_foo(void) {
        DECLARE(FUNC_FRM_R30, offsetof(Os_FuncFrameType,r30));\r
        DECLARE(FUNC_FRM_R31, offsetof(Os_FuncFrameType,r31));\r
 \r
+#if defined(CFG_SPE)\r
+       DECLARE(ISR_FRM_SPE_FSCR, offsetof(Os_IsrFrameType,fscr));\r
+       DECLARE(ISR_FRM_SPE_ACC, offsetof(Os_IsrFrameType,acc));\r
+       DECLARE(ISR_FRM_R3, offsetof(Os_IsrFrameType,acc));\r
+#endif\r
+\r
        DECLARE(ISR_FRM_SIZE,   sizeof(Os_IsrFrameType));\r
        DECLARE(ISR_FRM_R0, offsetof(Os_IsrFrameType,r0));\r
        DECLARE(ISR_FRM_R4, offsetof(Os_IsrFrameType,r4));\r

diff --git a/arch/ppc/mpc55xx/kernel/arch_stack.h b/arch/ppc/mpc55xx/kernel/arch_stack.h
index a1ba356fbe24e9e4cf86ef5d0da8fb339759ff3c..27fee29e4e6f7d0083d3d62cae5501873a4be928 100644 (file)
--- a/arch/ppc/mpc55xx/kernel/arch_stack.h
+++ b/arch/ppc/mpc55xx/kernel/arch_stack.h
@@ -116,6 +116,75 @@ typedef struct {
        uint32_t pad;\r
 } Os_ExceptionFrameType;\r
 \r
+#if defined(CFG_SPE)\r
+typedef struct {\r
+       uint32_t sp;\r
+       uint32_t backchain;\r
+       uint32_t padding;\r
+       uint32_t pattern;\r
+       uint32_t cr;\r
+       uint32_t lr;\r
+       uint64_t r14;\r
+       uint64_t r15;\r
+       uint64_t r16;\r
+       uint64_t r17;\r
+       uint64_t r18;\r
+       uint64_t r19;\r
+       uint64_t r20;\r
+       uint64_t r21;\r
+       uint64_t r22;\r
+       uint64_t r23;\r
+       uint64_t r24;\r
+       uint64_t r25;\r
+       uint64_t r26;\r
+       uint64_t r27;\r
+       uint64_t r28;\r
+       uint64_t r29;\r
+       uint64_t r30;\r
+       uint64_t r31;\r
+} Os_FuncFrameType;\r
+\r
+typedef struct  {\r
+       uint32_t sr;\r
+       uint32_t backchain;\r
+       uint32_t padding;\r
+       uint32_t pattern;\r
+       uint64_t fscr;\r
+       uint64_t acc;\r
+       uint64_t r0;\r
+       /* r1 */\r
+       /* r2 */\r
+       uint64_t r3;\r
+       uint64_t r4;\r
+       uint64_t r5;\r
+       uint64_t r6;\r
+       uint64_t r7;\r
+       uint64_t r8;\r
+       uint64_t r9;\r
+       uint64_t r10;\r
+       uint64_t r11;\r
+       uint64_t r12;\r
+       /* r13 */\r
+       uint64_t r14;\r
+       uint64_t r15;\r
+       uint64_t r16;\r
+       uint64_t r17;\r
+       uint64_t r18;\r
+       uint64_t r19;\r
+       uint64_t r20;\r
+       uint64_t r21;\r
+       uint64_t r22;\r
+       uint64_t r23;\r
+       uint64_t r24;\r
+       uint64_t r25;\r
+       uint64_t r26;\r
+       uint64_t r27;\r
+       uint64_t r28;\r
+       uint64_t r29;\r
+       uint64_t r30;\r
+       uint64_t r31;\r
+} Os_IsrFrameType;\r
+#else\r
 typedef struct {\r
        uint32_t sp;\r
        uint32_t backchain;\r
@@ -151,7 +220,7 @@ typedef struct  {
        uint32_t r0;\r
        /* r1 */\r
        /* r2 */\r
-       /* r3 */\r
+       /* r3, already save in exception frame */\r
        uint32_t r4;\r
        uint32_t r5;\r
        uint32_t r6;\r
@@ -182,41 +251,8 @@ typedef struct  {
        uint32_t r31;       /* 3+32-4 + 1= 31 */\r
 } Os_IsrFrameType;\r
 \r
-struct Os_IsrSpeFrame  {\r
-       uint64_t spefscr;\r
-       uint64_t acc;\r
-       uint64_t r0;\r
-       uint64_t r3;\r
-       uint64_t r4;\r
-       uint64_t r5;\r
-       uint64_t r6;\r
-       uint64_t r7;\r
-       uint64_t r8;\r
-       uint64_t r9;\r
-       uint64_t r10;\r
-       uint64_t r11;\r
-       uint64_t r12;\r
-       uint64_t r13;\r
-       uint64_t r14;\r
-       uint64_t r15;\r
-       uint64_t r16;\r
-       uint64_t r17;\r
-       uint64_t r18;\r
-       uint64_t r19;\r
-       uint64_t r20;\r
-       uint64_t r21;\r
-       uint64_t r22;\r
-       uint64_t r23;\r
-       uint64_t r24;\r
-       uint64_t r25;\r
-       uint64_t r26;\r
-       uint64_t r27;\r
-       uint64_t r28;\r
-       uint64_t r29;\r
-       uint64_t r30;\r
-       uint64_t r31;\r
-       uint32_t pattern;\r
-};\r
+#endif /* defined(CFG_SPE) */\r
+\r
 #endif /* !defined(_ASSEMLBER_) */\r
 \r
 \r

diff --git a/tools/t32/mpc55xx_sim.dll b/tools/t32/mpc55xx_sim.dll
index c0ac64aff4bc1114c3b2947bf874c365970da3fe..8d75ede07daa093aff816e0a5a8243555df3da31 100644 (file)
Binary files a/tools/t32/mpc55xx_sim.dll and b/tools/t32/mpc55xx_sim.dll differ

diff --git a/tools/t32/sim_mpc55xx.cmm b/tools/t32/sim_mpc55xx.cmm
index 22ee9dde364e5230dc44720b5a57816cc53fe026..a5ce7622dfc6c4bd6eaa4e91578ff5cf864fd130 100644 (file)
--- a/tools/t32/sim_mpc55xx.cmm
+++ b/tools/t32/sim_mpc55xx.cmm
@@ -7,7 +7,8 @@
  // arg 2-blaj\r
  // arg 3-debug : 0 \r
  \r
- sim.load mpc55xx_sim.dll 20000 0 0\r
+ sim.load mpc55xx_sim.dll 20000 0 1\r
+// sim.load C:\projects\workspace\t32_sim\Release\mpc55xx_sim.dll 20000 0 1\r
 \r
 enddo\r
 \r
@@ -40,3 +41,5 @@ enddo
 \r
 \r
 \r
+\r
+\r