Added SPI support for MPC5668 and MPC5567. Added DMA config for MPC5567. Added more...

diff --git a/arch/ppc/mpc55xx/drivers/Dma.h b/arch/ppc/mpc55xx/drivers/Dma.h
index 8dc986b49338730b1bf23b4e5ca2810d249e6e5a..da43a2d007f43fe469d2938273c82835151ad627 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Dma.h
+++ b/arch/ppc/mpc55xx/drivers/Dma.h
@@ -14,11 +14,31 @@
  * -------------------------------- Arctic Core ------------------------------*/\r
 \r
 \r
-\r
-\r
-\r
-\r
-\r
+/*\r
+ * Freescale uses two flavors for DMA.\r
+ * 1. eDMA\r
+ * 2. eDMA + DMA_MUX\r
+ *\r
+ * 1. eDMA only (MPC5557, etc)\r
+ *   The "DMA Request Assignments" are used and configured in Dma_Cfg.h using Dma_ChannelType.\r
+ *\r
+ * 2. eDMA + DMA_MUX  (MPC551x , MPC5668, etc )\r
+ *   The eDMA + DMA_MUX the "DMA Request Assignments" are just mappings from the DMA_MUX.\r
+ *   The file Dma.h contains the Dma_MuxChannels\r
+ *\r
+ *\r
+ *  eDMA+DMA_MUX\r
+ *    MPC551x\r
+ *    MPC5668\r
+ *    MPC5605B,MPC5606B,MPC5607B\r
+ *\r
+ *  eDMA\r
+ *    MPC5567\r
+ *\r
+ *  NO DMA\r
+ *    MPC5604B\r
+ *\r
+ */\r
 \r
 #ifndef DMA_H_\r
 #define DMA_H_\r
@@ -28,6 +48,13 @@
 #include "Dma_Cfg.h"\r
 #include "mpc55xx.h"\r
 \r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || (CFG_MPC5606S) || defined(CFG_MPC5668)\r
+#if !defined(CFG_DMA_MUX)\r
+#define CFG_DMA_MUX\r
+#endif\r
+#endif\r
+\r
+#if defined(CFG_DMA_MUX)\r
 \r
 #if defined(CFG_MPC5606S)\r
 typedef enum\r
@@ -109,7 +136,90 @@ typedef enum
   DMA_ALWAYS_REQUESTORS8\r
 }Dma_MuxChannels;\r
 \r
-#else\r
+#elif defined(CFG_MPC5668)\r
+\r
+/* Table 22-4. DMA Source Configuration */\r
+\r
+typedef enum\r
+{\r
+       DMA_CHANNEL_DISABLED,   /* 0 */\r
+       DMA_CHANNEL_RESERVED,\r
+       DMA_SCI_A_COMBTX,\r
+       DMA_SCI_A_COMBRX,\r
+       DMA_SCI_B_COMBTX,\r
+       DMA_SCI_B_COMBRX,\r
+       DMA_SCI_C_COMBTX,\r
+       DMA_SCI_C_COMBRX,\r
+       DMA_SCI_D_COMBTX,\r
+       DMA_SCI_D_COMBRX,\r
+       DMA_SCI_E_COMBTX,\r
+       DMA_SCI_E_COMBRX,\r
+       DMA_SCI_F_COMBTX,\r
+       DMA_SCI_F_COMBRX,\r
+       DMA_SCI_G_COMBTX,\r
+       DMA_SCI_G_COMBRX,\r
+       DMA_SCI_H_COMBTX,\r
+       DMA_SCI_H_COMBRX,\r
+\r
+       DMA_DSPI_A_SR_TFFF,  /* 0x12 */\r
+       DMA_DSPI_A_SR_RFRD,\r
+       DMA_DSPI_B_SR_TFFF,\r
+       DMA_DSPI_B_SR_RFRD,\r
+       DMA_DSPI_E_SR_TFFF,\r
+       DMA_DSPI_E_SR_RFRD,\r
+       DMA_DSPI_F_SR_TFFF,\r
+       DMA_DSPI_F_SR_RFRD,\r
+\r
+       DMA_EMIOS200_FLAG_F0, /* 0x1a */\r
+       DMA_EMIOS200_FLAG_F1,\r
+       DMA_EMIOS200_FLAG_F2,\r
+       DMA_EMIOS200_FLAG_F3,\r
+       DMA_EMIOS200_FLAG_F4,\r
+       DMA_EMIOS200_FLAG_F5,\r
+       DMA_EMIOS200_FLAG_F6,\r
+       DMA_EMIOS200_FLAG_F7,\r
+       DMA_EMIOS200_FLAG_F8,\r
+       DMA_EMIOS200_FLAG_F9,\r
+       DMA_EMIOS200_FLAG_F10,\r
+       DMA_EMIOS200_FLAG_F11,\r
+       DMA_EMIOS200_FLAG_F12,\r
+       DMA_EMIOS200_FLAG_F13,\r
+       DMA_EMIOS200_FLAG_F14,\r
+       DMA_EMIOS200_FLAG_F15,\r
+\r
+       DMA_IIC_A_TX,  /* 0x2a */\r
+       DMA_IIC_A_RX,\r
+       DMA_IIC_B_TX,\r
+       DMA_IIC_B_RX,\r
+\r
+       DMA_SIU_EISR_EIF0, /* 0x2e */\r
+       DMA_SIU_EISR_EIF1,\r
+\r
+       DMA_IIC_C_TX, /* 0x30 */\r
+       DMA_IIC_C_RX,\r
+\r
+       DMA_ADC_A,\r
+\r
+       DMA_IIC_D_TX, /* 0x33 */\r
+       DMA_IIC_D_RX,\r
+\r
+       DMA_SCI_J_COMBTX, /* 0x35 */\r
+       DMA_SCI_J_COMBRX,\r
+       DMA_SCI_K_COMBTX,\r
+       DMA_SCI_K_COMBRX,\r
+       DMA_SCI_L_COMBTX,\r
+       DMA_SCI_L_COMBRX,\r
+       DMA_SCI_M_COMBTX,\r
+       DMA_SCI_M_COMBRX,\r
+\r
+       DMA_ALWAYS_ENABLED_0, /* 0x3d */\r
+       DMA_ALWAYS_ENABLED_1,\r
+       DMA_ALWAYS_ENABLED_2,\r
+} Dma_MuxChannels;\r
+\r
+#elif  defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+/* MPC551x "Table 13-4. DMA Source Configuration" */\r
+\r
 typedef enum\r
 {\r
   DMA_CHANNEL_DISABLED,\r
@@ -188,13 +298,17 @@ typedef enum
 }Dma_MuxChannels;\r
 \r
 #endif\r
+#endif\r
 \r
+\r
+#if defined(CFG_DMA_MUX)\r
 typedef struct\r
 {\r
   vuint8_t DMA_CHANNEL_ENABLE;\r
   vuint8_t DMA_CHANNEL_TRIG_ENABLE;\r
   Dma_MuxChannels DMA_CHANNEL_SOURCE;\r
 } Dma_MuxConfigType;\r
+#endif\r
 \r
 typedef struct\r
 {\r
@@ -221,7 +335,7 @@ typedef enum
 typedef struct\r
 {\r
        // 5567 has no Dma Mux, but maybe this should be left in anyway?\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || (CFG_MPC5606S)\r
+#if defined(CFG_DMA_MUX)\r
   const Dma_MuxConfigType          *dmaMuxConfigPtr;\r
 #endif\r
   const Dma_ChannelConfigType      *dmaChannelConfigPtr;\r

diff --git a/arch/ppc/mpc55xx/drivers/Spi.c b/arch/ppc/mpc55xx/drivers/Spi.c
index 30e881355be7ea95ff5e443f487609ece4983452..e7d1b42acc8910dbe69b4bdbe724c447e668aeb9 100644 (file)
--- a/arch/ppc/mpc55xx/drivers/Spi.c
+++ b/arch/ppc/mpc55xx/drivers/Spi.c
@@ -162,6 +162,22 @@
 #include "isr.h"\r
 /* ----------------------------[private define]------------------------------*/\r
 \r
+#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5668) || defined(CFG_MPC5567)\r
+#define SPI_CONTROLLER_TOTAL_CNT               4\r
+#elif defined(CFG_MPC5604B)\r
+#define SPI_CONTROLLER_TOTAL_CNT               3\r
+#elif defined(CFG_MPC560X)\r
+#define SPI_CONTROLLER_TOTAL_CNT               2\r
+#endif\r
+\r
+#if defined(CFG_MPC560X)\r
+#define DSPI_A_ISR_EOQF DSPI_0_ISR_EOQF\r
+#define DSPI_B_ISR_EOQF DSPI_1_ISR_EOQF\r
+#if defined(CFG_MPC5604B)\r
+#define DSPI_C_ISR_EOQF DSPI_2_ISR_EOQF\r
+#endif\r
+#endif\r
+\r
 #define SPIE_BAD                 (-1)\r
 #define SPIE_OK                                0\r
 #define SPIE_JOB_NOT_DONE   1\r
@@ -1013,7 +1029,7 @@ static void Spi_SetupCTAR(        Spi_HWUnitType unit,
         * --> BR=Fsys/(Baudrate.* 2 )\r
         *\r
         */\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC560X)\r
+\r
        switch(unit) {\r
        case 0:\r
                perClock = PERIPHERAL_CLOCK_DSPI_A;\r
@@ -1021,12 +1037,12 @@ static void Spi_SetupCTAR(      Spi_HWUnitType unit,
        case 1:\r
                perClock = PERIPHERAL_CLOCK_DSPI_B;\r
                break;\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517) || defined(CFG_MPC5604B)\r
+#if (SPI_CONTROLLER_TOTAL_CNT>2)\r
        case 2:\r
                perClock = PERIPHERAL_CLOCK_DSPI_C;\r
                break;\r
 #endif\r
-#if defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
+#if (SPI_CONTROLLER_TOTAL_CNT>3)\r
        case 3:\r
                perClock = PERIPHERAL_CLOCK_DSPI_D;\r
                break;\r
@@ -1035,9 +1051,6 @@ static void Spi_SetupCTAR(        Spi_HWUnitType unit,
                assert(0);\r
                break;\r
        }\r
-#else\r
-#error CPU not supported\r
-#endif\r
        clock = McuE_GetPeripheralClock(perClock);\r
 \r
        DEBUG(DEBUG_MEDIUM,"%s: Peripheral clock at %d Mhz\n",MODULE_NAME,clock);\r
@@ -1236,33 +1249,21 @@ static void Spi_InitController(Spi_UnitType *uPtr ) {
 \r
        // Install EOFQ int..\r
        switch (uPtr->hwUnit) {\r
-#if defined(CFG_MPC560X)\r
-       case 0:\r
-       ISR_INSTALL_ISR2("SPI_A",Spi_Isr_A, DSPI_0_ISR_EOQF, 15, 0);\r
-       break;\r
-       case 1:\r
-       ISR_INSTALL_ISR2("SPI_B",Spi_Isr_B, DSPI_1_ISR_EOQF, 15, 0);\r
-       break;\r
-#if defined(CFG_MPC5604B)\r
-       case 2:\r
-       ISR_INSTALL_ISR2("SPI_C",Spi_Isr_C, DSPI_2_ISR_EOQF, 15, 0);\r
-       break;\r
-#endif\r
-#elif defined(CFG_MPC5516) || defined(CFG_MPC5517)\r
        case 0:\r
        ISR_INSTALL_ISR2("SPI_A",Spi_Isr_A, DSPI_A_ISR_EOQF, 15, 0);\r
        break;\r
        case 1:\r
        ISR_INSTALL_ISR2("SPI_B",Spi_Isr_B, DSPI_B_ISR_EOQF, 15, 0);\r
        break;\r
+#if (SPI_CONTROLLER_TOTAL_CNT > 2)\r
        case 2:\r
-       ISR_INSTALL_ISR2("SPI_A",Spi_Isr_C, DSPI_C_ISR_EOQF, 15, 0);\r
+       ISR_INSTALL_ISR2("SPI_C",Spi_Isr_C, DSPI_C_ISR_EOQF, 15, 0);\r
        break;\r
+#endif\r
+#if (SPI_CONTROLLER_TOTAL_CNT > 3)\r
        case 3:\r
-       ISR_INSTALL_ISR2("SPI_B",Spi_Isr_D, DSPI_D_ISR_EOQF, 15, 0);\r
+       ISR_INSTALL_ISR2("SPI_D",Spi_Isr_D, DSPI_D_ISR_EOQF, 15, 0);\r
        break;\r
-#else\r
-#error ISR NOT installed.\r
 #endif\r
        }\r
 }\r

diff --git a/boards/mpc5567qrtech/config/Dma_Cfg.c b/boards/mpc5567qrtech/config/Dma_Cfg.c
new file mode 100644 (file)
index 0000000..ec15a14
--- /dev/null
+++ b/boards/mpc5567qrtech/config/Dma_Cfg.c
@@ -0,0 +1,82 @@
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009  ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+#warning "This default file may only be used as an example!"\r
+\r
+#include "Dma.h"\r
+\r
+\r
+const Dma_ChannelConfigType DmaChannelConfig [DMA_NUMBER_OF_CHANNELS] =\r
+{\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP0_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP1_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP2_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP3_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP4_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_COMMAND_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_ADC_GROUP5_RESULT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_B_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_B_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_C_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_C_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_D_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_D_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_COMBINED_TRANSMIT_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_SPI_COMBINED_RECEIVE_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_3_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_4_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_8_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_EMIOS_9_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+  { .DMA_CHANNEL_PRIORITY = DMA_TPU_0_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_TPU_1_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_TPU_2_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_TPU_14_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+  { .DMA_CHANNEL_PRIORITY = DMA_TPU_15_CHANNEL, .DMA_CHANNEL_PREEMTION_ENABLE = 1 },\r
+\r
+};\r
+\r
+\r
+const Dma_ConfigType DmaConfig []=\r
+{\r
+  {DmaChannelConfig, DMA_FIXED_PRIORITY_ARBITRATION}\r
+};\r
+\r
+\r

diff --git a/boards/mpc5567qrtech/config/Dma_Cfg.h b/boards/mpc5567qrtech/config/Dma_Cfg.h
new file mode 100644 (file)
index 0000000..c713800
--- /dev/null
+++ b/boards/mpc5567qrtech/config/Dma_Cfg.h
@@ -0,0 +1,71 @@
+/* -------------------------------- Arctic Core ------------------------------\r
+ * Arctic Core - the open source AUTOSAR platform http://arccore.com\r
+ *\r
+ * Copyright (C) 2009  ArcCore AB <contact@arccore.com>\r
+ *\r
+ * This source code is free software; you can redistribute it and/or modify it\r
+ * under the terms of the GNU General Public License version 2 as published by the\r
+ * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.\r
+ *\r
+ * This program is distributed in the hope that it will be useful, but\r
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License\r
+ * for more details.\r
+ * -------------------------------- Arctic Core ------------------------------*/\r
+\r
+#ifndef DMA_CFG_H_\r
+#define DMA_CFG_H_\r
+\r
+// See section 9.4.3 DMA Request Assignments in MPC5567 RM\r
+typedef enum\r
+{\r
+  DMA_ADC_GROUP0_COMMAND_CHANNEL,\r
+  DMA_ADC_GROUP0_RESULT_CHANNEL,\r
+\r
+  DMA_ADC_GROUP1_COMMAND_CHANNEL,\r
+  DMA_ADC_GROUP1_RESULT_CHANNEL,\r
+\r
+  DMA_ADC_GROUP2_COMMAND_CHANNEL,\r
+  DMA_ADC_GROUP2_RESULT_CHANNEL,\r
+\r
+  DMA_ADC_GROUP3_COMMAND_CHANNEL,\r
+  DMA_ADC_GROUP3_RESULT_CHANNEL,\r
+\r
+  DMA_ADC_GROUP4_COMMAND_CHANNEL,\r
+  DMA_ADC_GROUP4_RESULT_CHANNEL,\r
+\r
+  DMA_ADC_GROUP5_COMMAND_CHANNEL,\r
+  DMA_ADC_GROUP5_RESULT_CHANNEL,\r
+\r
+  DMA_SPI_B_TRANSMIT_CHANNEL,\r
+  DMA_SPI_B_RECEIVE_CHANNEL,\r
+\r
+  DMA_SPI_C_TRANSMIT_CHANNEL,\r
+  DMA_SPI_C_RECEIVE_CHANNEL,\r
+\r
+  DMA_SPI_D_TRANSMIT_CHANNEL,\r
+  DMA_SPI_D_RECEIVE_CHANNEL,\r
+\r
+  DMA_SPI_COMBINED_TRANSMIT_CHANNEL,\r
+  DMA_SPI_COMBINED_RECEIVE_CHANNEL,\r
+\r
+  DMA_EMIOS_0_CHANNEL,\r
+  DMA_EMIOS_1_CHANNEL,\r
+  DMA_EMIOS_2_CHANNEL,\r
+  DMA_EMIOS_3_CHANNEL,\r
+  DMA_EMIOS_4_CHANNEL,\r
+  DMA_EMIOS_8_CHANNEL,\r
+  DMA_EMIOS_9_CHANNEL,\r
+\r
+  DMA_TPU_0_CHANNEL,\r
+  DMA_TPU_1_CHANNEL,\r
+  DMA_TPU_2_CHANNEL,\r
+  DMA_TPU_14_CHANNEL,\r
+  DMA_TPU_15_CHANNEL,\r
+\r
+  DMA_NUMBER_OF_CHANNELS\r
+} Dma_ChannelType;\r
+\r
+\r
+\r
+#endif /* DMA_CFG_H_ */\r

diff --git a/makefile b/makefile
index d1ff0a7d6b52c6844a7c4cf24a4ba5122aaba2c1..f2ef423444f951cac662bfdb8be3dcd37fb7e616 100644 (file)
--- a/makefile
+++ b/makefile
@@ -138,7 +138,12 @@ show_build:
        @echo "==========[ BUILD INFO ]==========="\r
        @echo "  BDIR:           $(BDIR) [$(origin BDIR)]"\r
        @echo "  BOARDDIR:       $(BOARDDIR) [$(origin BOARDDIR)]"\r
+       @echo "  COMPILER:       $(COMPILER) [$(origin COMPILER)]"      \r
+ifeq ($(COMPILER),cw)  \r
+       @echo "  CW_COMPILE:     $(CW_COMPILE) [$(origin CW_COMPILE)]"\r
+else \r
        @echo "  CROSS_COMPILE:  $(CROSS_COMPILE) [$(origin CROSS_COMPILE)]"\r
+endif\r
        @echo "  CURDIR:         $(CURDIR)"\r
        @echo "  SELECT_CONSOLE: $(SELECT_CONSOLE) [$(origin SELECT_CONSOLE)]"\r
        \r