Added support for diab5.6. Corrected build config for mpc5516it

[arc.git] / include / ppc / Cpu.h

diff --git a/include/ppc/Cpu.h b/include/ppc/Cpu.h
index ed2f0ae1028fd8f5c0f0346ce2803905882dbef1..be91bfdef767d3b7aef3726b21878d0539c82292 100644 (file)
--- a/include/ppc/Cpu.h
+++ b/include/ppc/Cpu.h
@@ -14,21 +14,15 @@
  * -------------------------------- Arctic Core ------------------------------*/\r
 \r
 \r
-\r
-\r
-\r
-\r
-\r
-\r
-\r
 #ifndef CPU_H\r
 #define CPU_H\r
 \r
 #include "Std_Types.h"\r
 typedef uint32_t imask_t;\r
-#if defined(__DCC__)\r
-#include <diab/ppcasm.h>\r
-#endif\r
+\r
+//#if defined(__DCC__)\r
+//#include <diab/ppcasm.h>\r
+//#endif\r
 \r
 // Used if we are running a T32 instruction set simulator\r
 #define SIMULATOR() (SIU.MIDR.R==0)\r
@@ -144,9 +138,13 @@ typedef uint32_t imask_t;
  * Sets a value to a specific SPR register\r
  */\r
 #if defined(__DCC__)\r
-#define set_spr(spr_nr, val)   (__mtspr(spr_nr,val))\r
+asm void set_spr(uint32 spr_nr, uint32 val)\r
+{\r
+%reg val; con spr_nr\r
+  mtspr spr_nr, val\r
+}\r
 #else\r
-#define set_spr(spr_nr, val) \\r
+# define set_spr(spr_nr, val) \\r
        asm volatile (" mtspr " STRINGIFY__(spr_nr) ",%[_val]" : : [_val] "r" (val))\r
 #endif\r
 /**\r
@@ -156,7 +154,11 @@ typedef uint32_t imask_t;
  */\r
 \r
 #if defined(__DCC__)\r
-#define get_spr(spr_nr)                (__mfspr(spr_nr))\r
+asm uint32 get_spr(uint32 spr_nr)\r
+{\r
+% con spr_nr\r
+  mfspr r3, spr_nr\r
+}\r
 #else\r
 #define get_spr(spr_nr)        CC_EXTENSION \\r
 ({\\r
@@ -171,7 +173,10 @@ typedef uint32_t imask_t;
  * @return\r
  */\r
 #if defined(__DCC__)\r
-#define get_msr()              (__mfmsr())\r
+asm volatile unsigned long get_msr()\r
+{\r
+  mfmsr r3\r
+}\r
 #else\r
 static inline unsigned long get_msr() {\r
        uint32_t msr;\r
@@ -186,9 +191,12 @@ static inline unsigned long get_msr() {
  * @param msr\r
  */\r
 #if defined(__DCC__)\r
-#define set_msr(msr)\\r
-       (__mtmsr(msr));\\r
-       (__isync());\r
+asm volatile void set_msr(unsigned long msr)\r
+{\r
+% reg msr\r
+  mtmsr msr\r
+  isync\r
+}\r
 #else\r
 static inline void set_msr(unsigned long msr) {\r
   asm volatile ("mtmsr %0" : : "r" (msr) );\r
@@ -201,7 +209,11 @@ static inline void set_msr(unsigned long msr) {
 \r
 /* Count the number of consecutive zero bits starting at ppc-bit 0 */\r
 #if defined(__DCC__)\r
-#define cntlzw(val)            (__cntlzw(val))\r
+asm volatile unsigned int cntlzw(unsigned int val)\r
+{\r
+% reg val\r
+  cntlzw r3, val\r
+}\r
 #else\r
 static inline unsigned int cntlzw(unsigned int val)\r
 {\r
@@ -230,14 +242,23 @@ static inline unsigned long _Irq_Disable_save(void)
 }\r
 \r
 /*-----------------------------------------------------------------*/\r
+\r
+static inline void _Irq_Disable_restore(unsigned long flags)\r
+{\r
+       set_msr(flags);\r
+}\r
+\r
+#if 0\r
 #if defined(__DCC__)\r
-#define _Irq_Disable_restore(flags)            (__mtmsr(flags))\r
+#define _Irq_Disable_restore(flags)            (set_msr(flags))\r
 #else\r
 static inline void _Irq_Disable_restore(unsigned long flags)\r
 {\r
+       set_msr(flags);\r
    asm volatile ("mtmsr %0" : : "r" (flags) );\r
 }\r
 #endif\r
+#endif\r
 /*-----------------------------------------------------------------*/\r
 #if defined(__DCC__)\r
 #else\r