1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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19 #include "Std_Types.h"
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22 #if defined(USE_DEM)
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25 #include "mpc55xx.h"
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31 //#define USE_LDEBUG_PRINTF 1
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34 #define SYSCLOCK_SELECT_PLL 0x2
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36 #if defined(CFG_MPC5567)
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37 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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38 ( (_extal) * ((_emfd)+4) / (((_eprediv)+1)*(1<<(_erfd))) )
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39 #elif defined(CFG_MPC560X)
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40 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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41 ( (_extal)*(_emfd) / ((_eprediv+1)*(2<<(_erfd))) )
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43 #define CALC_SYSTEM_CLOCK(_extal,_emfd,_eprediv,_erfd) \
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44 ( (_extal) * ((_emfd)+16) / (((_eprediv)+1)*((_erfd)+1)) )
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47 typedef void (*vfunc_t)();
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49 /* Function declarations. */
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50 static void Mcu_ConfigureFlash(void);
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53 uint32 lossOfLockCnt;
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54 uint32 lossOfClockCnt;
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58 * Type that holds all global data for Mcu
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62 // Set if Mcu_Init() have been called
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65 const Mcu_ConfigType *config;
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66 Mcu_ClockType clockSetting;
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70 /* Development error macros. */
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71 #if ( MCU_DEV_ERROR_DETECT == STD_ON )
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72 #define VALIDATE(_exp,_api,_err ) \
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74 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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78 #define VALIDATE_W_RV(_exp,_api,_err,_rv ) \
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80 Det_ReportError(MODULE_ID_MCU,0,_api,_err); \
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84 #define VALIDATE(_exp,_api,_err )
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85 #define VALIDATE_W_RV(_exp,_api,_err,_rv )
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89 Mcu_GlobalType Mcu_Global =
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92 .config = &McuConfigData[0],
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95 //-------------------------------------------------------------------
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97 void Mcu_LossOfLock( void ){
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98 #if defined(USE_DEM)
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99 Dem_ReportErrorStatus(MCU_E_CLOCK_FAILURE, DEM_EVENT_STATUS_FAILED);
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104 * This interrupt may be triggered more than expected.
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105 * If you are going to use this interrupt, see [Freescale Device Errata MPC5510ACE, Rev. 10 APR 2009, errata ID: 6764].
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108 #if defined(CFG_MPC560X)
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111 Mcu_Global.stats.lossOfLockCnt++;
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113 FMPLL.SYNSR.B.LOLF = 1;
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117 //-------------------------------------------------------------------
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119 void Mcu_LossOfClock( void ){
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120 /* Should report MCU_E_CLOCK_FAILURE with DEM here */
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121 #if defined(CFG_MPC560X)
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124 Mcu_Global.stats.lossOfClockCnt++;
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126 FMPLL.SYNSR.B.LOCF = 1;
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130 #define SPR_PIR 286
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131 #define SPR_PVR 287
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133 #define CORE_PVR_E200Z1 0x81440000UL
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134 #define CORE_PVR_E200Z0 0x81710000UL
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135 #define CORE_PVR_E200Z3 0x81120000UL
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136 #define CORE_PVR_E200Z6 0x81170000UL
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137 #define CORE_PVR_E200Z65 0x81150000UL /* Is actually a 5668 */
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138 #define CORE_PVR_E200Z0H 0x817F0000UL
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150 const cpu_info_t cpu_info_list[] = {
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151 #if defined(CFG_MPC5516)
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154 .pvr = CORE_PVR_E200Z1,
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158 .pvr = CORE_PVR_E200Z0,
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160 #elif defined(CFG_MPC5567)
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163 .pvr = CORE_PVR_E200Z6,
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165 #elif defined(CFG_MPC5633)
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168 .pvr = CORE_PVR_E200Z3,
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170 #elif defined(CFG_MPC5604B)
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172 .name = "MPC5604B",
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173 .pvr = CORE_PVR_E200Z0H,
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175 #elif defined(CFG_MPC5606B)
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177 .name = "MPC5606B",
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178 .pvr = CORE_PVR_E200Z0H,
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180 #elif defined(CFG_MPC5606S)
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182 .name = "MPC5606S",
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183 .pvr = CORE_PVR_E200Z0H,
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185 #elif defined(CFG_MPC5668)
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188 .pvr = CORE_PVR_E200Z65,
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192 .pvr = CORE_PVR_E200Z0,
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197 const core_info_t core_info_list[] = {
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198 #if defined(CFG_MPC5516)
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200 .name = "CORE_E200Z1",
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201 .pvr = CORE_PVR_E200Z1,
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204 .name = "CORE_E200Z1",
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205 .pvr = CORE_PVR_E200Z1,
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207 #elif defined(CFG_MPC5567)
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209 .name = "CORE_E200Z6",
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210 .pvr = CORE_PVR_E200Z6,
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212 #elif defined(CFG_MPC5633)
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214 .name = "CORE_E200Z3",
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215 .pvr = CORE_PVR_E200Z3,
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217 #elif defined(CFG_MPC5604B)
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219 .name = "MPC5604B",
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220 .pvr = CORE_PVR_E200Z0H,
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222 #elif defined(CFG_MPC5606B)
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224 .name = "MPC5606B",
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225 .pvr = CORE_PVR_E200Z0H,
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227 #elif defined(CFG_MPC5606S)
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229 .name = "MPC5606S",
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230 .pvr = CORE_PVR_E200Z0H,
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232 #elif defined(CFG_MPC5668)
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234 .name = "CORE_E200Z65",
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235 .pvr = CORE_PVR_E200Z65,
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238 .name = "CORE_E200Z0",
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239 .pvr = CORE_PVR_E200Z1,
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245 #if !defined(ARRAY_SIZE)
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246 #define ARRAY_SIZE(_x) (sizeof(_x)/sizeof((_x)[0]))
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249 static const cpu_info_t *Mcu_IdentifyCpu(uint32 pvr)
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253 for (i = 0; i < ARRAY_SIZE(cpu_info_list); i++) {
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254 if (cpu_info_list[i].pvr == pvr) {
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255 return &cpu_info_list[i];
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262 static const core_info_t *Mcu_IdentifyCore(uint32 pvr)
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266 for (i = 0; i < ARRAY_SIZE(core_info_list); i++) {
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267 if (core_info_list[i].pvr == pvr) {
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268 return &core_info_list[i];
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275 static uint32 Mcu_CheckCpu( void ) {
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278 const cpu_info_t *cpuType;
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279 const core_info_t *coreType;
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281 // We have to registers to read here, PIR and PVR
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282 // pir = get_spr(SPR_PIR);
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283 pvr = get_spr(SPR_PVR);
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285 cpuType = Mcu_IdentifyCpu(pvr);
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286 coreType = Mcu_IdentifyCore(pvr);
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288 if( (cpuType == NULL) || (coreType == NULL) ) {
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293 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Cpu: %s( 0x%08x )\n",cpuType->name,pvr);
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294 //DEBUG(DEBUG_HIGH,"/drivers/mcu: Core: %s( 0x%08x )\n",coreType->name,pvr);
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299 //-------------------------------------------------------------------
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301 void Mcu_Init(const Mcu_ConfigType *configPtr)
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303 VALIDATE( ( NULL != configPtr ), MCU_INIT_SERVICE_ID, MCU_E_PARAM_CONFIG );
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305 #if defined(CFG_MPC560X)
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306 /* Disable watchdog. Watchdog is enabled default after reset.*/
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307 SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */
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308 SWT.SR.R = 0x0000d928;
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309 SWT.CR.R = 0x8000010A; /* Disable watchdog */
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310 #if defined(USE_WDG)
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311 SWT.TO.R = 0xfa00; /* set the timout to 500ms */
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312 SWT.CR.R = 0x8000011B; /* enable watchdog */
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316 if( !SIMULATOR() ) {
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320 memset(&Mcu_Global.stats,0,sizeof(Mcu_Global.stats));
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323 Mcu_ConfigureFlash();
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325 Mcu_Global.config = configPtr;
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327 #if defined(CFG_MPC560X)
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328 /* Enable DRUN, RUN0, SAFE, RESET modes */
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329 ME.MER.R = 0x0000001D;
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332 Mcu_Global.initRun = 1;
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334 if( Mcu_Global.config->McuClockSrcFailureNotification == TRUE ) {
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335 #if defined(CFG_MPC560X)
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338 ISR_INSTALL_ISR1("LossOfLock", Mcu_LossOfLock, PLL_SYNSR_LOLF, 10 , 0 );
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339 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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340 FMPLL.ESYNCR2.B.LOLIRQ = 1;
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341 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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342 FMPLL.SYNCR.B.LOLIRQ = 1;
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344 ISR_INSTALL_ISR1("LossOfClock", Mcu_LossOfClock, PLL_SYNSR_LOLF, 10 , 0 );
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345 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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346 FMPLL.ESYNCR2.B.LOCIRQ = 1;
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347 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
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348 FMPLL.SYNCR.B.LOCIRQ = 1;
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354 //-------------------------------------------------------------------
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358 Mcu_Global.initRun = FALSE; // Very simple Deinit. Should we do more?
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361 //-------------------------------------------------------------------
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363 Std_ReturnType Mcu_InitRamSection(const Mcu_RamSectionType RamSection)
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365 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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366 VALIDATE_W_RV( ( RamSection <= Mcu_Global.config->McuRamSectors ), MCU_INITRAMSECTION_SERVICE_ID, MCU_E_PARAM_RAMSECTION, E_NOT_OK );
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368 /* NOT SUPPORTED, reason: no support for external RAM */
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373 //-------------------------------------------------------------------
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375 Std_ReturnType Mcu_InitClock(const Mcu_ClockType ClockSetting)
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377 Mcu_ClockSettingConfigType *clockSettingsPtr;
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378 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_INITCLOCK_SERVICE_ID, MCU_E_UNINIT, E_NOT_OK );
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379 VALIDATE_W_RV( ( ClockSetting < Mcu_Global.config->McuClockSettings ), MCU_INITCLOCK_SERVICE_ID, MCU_E_PARAM_CLOCK, E_NOT_OK );
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381 Mcu_Global.clockSetting = ClockSetting;
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382 clockSettingsPtr = &Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting];
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384 // TODO: find out if the 5554 really works like the 5516 here
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385 // All three (16, 54, 67) used to run the same code here though, so i'm sticking it with 5516
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386 #if defined(CFG_MPC5516) || defined(CFG_MPC5554) || defined(CFG_MPC5668)
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388 * Fsys - System frequency ( CPU + all periperals? )
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390 * Fsys = EXTAL_FREQ *( (emfd+16) / ( (eprediv+1) * ( erfd+1 )) ) )
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393 assert((clockSettingsPtr->Pll2>=32) && (clockSettingsPtr->Pll2<=132));
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394 assert( (clockSettingsPtr->Pll1 != 6) &&
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395 (clockSettingsPtr->Pll1 != 8) &&
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396 (clockSettingsPtr->Pll1 < 10) );
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397 assert( clockSettingsPtr->Pll3 & 1); // Must be odd
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398 #elif defined(CFG_MPC5567)
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399 /* 5567 clock info:
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400 * Fsys = EXTAL_FREQ *( (emfd+4) / ( (eprediv+1) * ( 2^erfd )) ) )
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403 assert(clockSettingsPtr->Pll2 < 16);
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404 assert(clockSettingsPtr->Pll1 <= 4);
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405 assert(clockSettingsPtr->Pll3 < 8);
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408 #if defined(USE_LDEBUG_PRINTF)
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410 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
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413 f_sys = CALC_SYSTEM_CLOCK( extal,
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414 clockSettingsPtr->Pll2,
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415 clockSettingsPtr->Pll1,
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416 clockSettingsPtr->Pll3 );
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418 //DEBUG(DEBUG_HIGH,"/drivers/mcu: F_sys will be:%08d Hz\n",f_sys);
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422 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
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424 // set post divider to next valid value to ensure that an overshoot during lock phase
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425 // won't result in a too high freq
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426 FMPLL.ESYNCR2.B.ERFD = (clockSettingsPtr->Pll3 + 1) | 1;
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428 // External crystal PLL mode.
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429 FMPLL.ESYNCR1.B.CLKCFG = 7; //TODO: Hur ställa detta för 5567?
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431 // Write pll parameters.
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432 FMPLL.ESYNCR1.B.EPREDIV = clockSettingsPtr->Pll1;
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433 FMPLL.ESYNCR1.B.EMFD = clockSettingsPtr->Pll2;
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435 while(FMPLL.SYNSR.B.LOCK != 1) {};
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437 FMPLL.ESYNCR2.B.ERFD = clockSettingsPtr->Pll3;
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438 // Connect SYSCLK to FMPLL
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439 SIU.SYSCLK.B.SYSCLKSEL = SYSCLOCK_SELECT_PLL;
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440 #elif defined(CFG_MPC5604B) || defined(CFG_MPC5606B)
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441 // Write pll parameters.
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442 CGM.FMPLL_CR.B.IDF = clockSettingsPtr->Pll1;
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443 CGM.FMPLL_CR.B.NDIV = clockSettingsPtr->Pll2;
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444 CGM.FMPLL_CR.B.ODF = clockSettingsPtr->Pll3;
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446 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
\r
447 ME.RUN[0].R = 0x001F0074;
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448 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
\r
449 ME.RUNPC[1].R = 0x00000010;
\r
450 /* MPC56xxB/S: select ME.RUNPC[1] */
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451 ME.PCTL[68].R = 0x01; //SIUL control
\r
452 ME.PCTL[91].R = 0x01; //RTC/API control
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453 ME.PCTL[92].R = 0x01; //PIT_RTI control
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454 ME.PCTL[72].R = 0x01; //eMIOS0 control
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455 ME.PCTL[73].R = 0x01; //eMIOS1 control
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456 ME.PCTL[16].R = 0x01; //FlexCAN0 control
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457 ME.PCTL[17].R = 0x01; //FlexCAN1 control
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458 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
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459 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
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460 ME.PCTL[32].R = 0x01; //ADC0 control
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461 #if defined(CFG_MPC5606B)
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462 ME.PCTL[33].R = 0x01; //ADC1 control
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464 ME.PCTL[23].R = 0x01; //DMAMUX control
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465 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
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466 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
467 /* Mode Transition to enter RUN0 mode: */
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468 /* Enter RUN0 Mode & Key */
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469 ME.MCTL.R = 0x40005AF0;
\r
470 /* Enter RUN0 Mode & Inverted Key */
\r
471 ME.MCTL.R = 0x4000A50F;
\r
473 /* Wait for mode transition to complete */
\r
474 while (ME.GS.B.S_MTRANS) {}
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475 /* Verify RUN0 is the current mode */
\r
476 while(ME.GS.B.S_CURRENTMODE != 4) {}
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478 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
\r
479 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
\r
480 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
\r
482 SIU.PSMI[0].R = 0x01; /* CAN1RX on PCR43 */
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483 SIU.PSMI[6].R = 0x01; /* CS0/DSPI_0 on PCR15 */
\r
485 #elif defined(CFG_MPC5606S)
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486 // Write pll parameters.
\r
487 CGM.FMPLL[0].CR.B.IDF = clockSettingsPtr->Pll1;
\r
488 CGM.FMPLL[0].CR.B.NDIV = clockSettingsPtr->Pll2;
\r
489 CGM.FMPLL[0].CR.B.ODF = clockSettingsPtr->Pll3;
\r
491 /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */
\r
492 ME.RUN[0].R = 0x001F0074;
\r
493 /* Peri. Cfg. 1 settings: only run in RUN0 mode */
\r
494 ME.RUNPC[1].R = 0x00000010;
\r
495 /* MPC56xxB/S: select ME.RUNPC[1] */
\r
496 ME.PCTL[68].R = 0x01; //SIUL control
\r
497 ME.PCTL[91].R = 0x01; //RTC/API control
\r
498 ME.PCTL[92].R = 0x01; //PIT_RTI control
\r
499 ME.PCTL[72].R = 0x01; //eMIOS0 control
\r
500 ME.PCTL[73].R = 0x01; //eMIOS1 control
\r
501 ME.PCTL[16].R = 0x01; //FlexCAN0 control
\r
502 ME.PCTL[17].R = 0x01; //FlexCAN1 control
\r
503 ME.PCTL[4].R = 0x01; /* MPC56xxB/P/S DSPI0 */
\r
504 ME.PCTL[5].R = 0x01; /* MPC56xxB/P/S DSPI1: */
\r
505 ME.PCTL[32].R = 0x01; //ADC0 control
\r
506 ME.PCTL[23].R = 0x01; //DMAMUX control
\r
507 ME.PCTL[48].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
508 ME.PCTL[49].R = 0x01; /* MPC56xxB/P/S LINFlex */
\r
509 /* Mode Transition to enter RUN0 mode: */
\r
510 /* Enter RUN0 Mode & Key */
\r
511 ME.MCTL.R = 0x40005AF0;
\r
512 /* Enter RUN0 Mode & Inverted Key */
\r
513 ME.MCTL.R = 0x4000A50F;
\r
515 /* Wait for mode transition to complete */
\r
516 while (ME.GS.B.S_MTRANS) {}
\r
517 /* Verify RUN0 is the current mode */
\r
518 while(ME.GS.B.S_CURRENTMODE != 4) {}
\r
520 CGM.SC_DC[0].R = 0x80; /* MPC56xxB/S: Enable peri set 1 sysclk divided by 1 */
\r
521 CGM.SC_DC[1].R = 0x80; /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */
\r
522 CGM.SC_DC[2].R = 0x80; /* MPC56xxB/S: Enable peri set 3 sysclk divided by 1 */
\r
524 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
525 // Partially following the steps in MPC5567 RM..
\r
526 FMPLL.SYNCR.B.DEPTH = 0;
\r
527 FMPLL.SYNCR.B.LOLRE = 0;
\r
528 FMPLL.SYNCR.B.LOLIRQ = 0;
\r
530 FMPLL.SYNCR.B.PREDIV = clockSettingsPtr->Pll1;
\r
531 FMPLL.SYNCR.B.MFD = clockSettingsPtr->Pll2;
\r
532 FMPLL.SYNCR.B.RFD = clockSettingsPtr->Pll3;
\r
534 // Wait for PLL to sync.
\r
535 while (Mcu_GetPllStatus() != MCU_PLL_LOCKED) ;
\r
537 FMPLL.SYNCR.B.LOLIRQ = 1;
\r
543 //-------------------------------------------------------------------
\r
545 void Mcu_DistributePllClock(void)
\r
547 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_UNINIT );
\r
548 #if defined(CFG_MPC560XB)
\r
549 VALIDATE( ( CGM.FMPLL_CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
550 #elif defined(CFG_MPC5606S)
\r
551 VALIDATE( ( CGM.FMPLL[0].CR.B.S_LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
553 VALIDATE( ( FMPLL.SYNSR.B.LOCK == 1 ), MCU_DISTRIBUTEPLLCLOCK_SERVICE_ID, MCU_E_PLL_NOT_LOCKED );
\r
555 /* NOT IMPLEMENTED due to pointless function on this hardware */
\r
559 //-------------------------------------------------------------------
\r
561 Mcu_PllStatusType Mcu_GetPllStatus(void)
\r
563 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETPLLSTATUS_SERVICE_ID, MCU_E_UNINIT, MCU_PLL_STATUS_UNDEFINED );
\r
564 Mcu_PllStatusType rv;
\r
568 #if defined(CFG_MPC560XB)
\r
569 if ( !CGM.FMPLL_CR.B.S_LOCK )
\r
571 rv = MCU_PLL_UNLOCKED;
\r
574 rv = MCU_PLL_LOCKED;
\r
576 #elif defined(CFG_MPC5606S)
\r
577 if ( !CGM.FMPLL[0].CR.B.S_LOCK )
\r
579 rv = MCU_PLL_UNLOCKED;
\r
582 rv = MCU_PLL_LOCKED;
\r
585 if ( !FMPLL.SYNSR.B.LOCK )
\r
587 rv = MCU_PLL_UNLOCKED;
\r
590 rv = MCU_PLL_LOCKED;
\r
596 /* We are running on instruction set simulator. PLL is then always in sync... */
\r
597 rv = MCU_PLL_LOCKED;
\r
603 //-------------------------------------------------------------------
\r
605 Mcu_ResetType Mcu_GetResetReason(void)
\r
609 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_RESET_UNDEFINED );
\r
611 #if defined(CFG_MPC560X)
\r
612 if( RGM.FES.B.F_SOFT ) {
\r
614 } else if( RGM.DES.B.F_SWT ) {
\r
615 rv = MCU_WATCHDOG_RESET;
\r
616 } else if( RGM.DES.B.F_POR ) {
\r
617 rv = MCU_POWER_ON_RESET;
\r
619 rv = MCU_RESET_UNDEFINED;
\r
622 if( SIU.RSR.B.SSRS ) {
\r
624 } else if( SIU.RSR.B.WDRS ) {
\r
625 rv = MCU_WATCHDOG_RESET;
\r
626 } else if( SIU.RSR.B.PORS || SIU.RSR.B.ERS ) {
\r
627 rv = MCU_POWER_ON_RESET;
\r
629 rv = MCU_RESET_UNDEFINED;
\r
636 //-------------------------------------------------------------------
\r
638 Mcu_RawResetType Mcu_GetResetRawValue(void)
\r
640 VALIDATE_W_RV( ( 1 == Mcu_Global.initRun ), MCU_GETRESETREASON_SERVICE_ID, MCU_E_UNINIT, MCU_GETRESETRAWVALUE_UNINIT_RV );
\r
642 if( !Mcu_Global.initRun ) {
\r
643 return MCU_GETRESETRAWVALUE_UNINIT_RV;
\r
646 #if defined(CFG_MPC560X)
\r
657 //-------------------------------------------------------------------
\r
659 #if ( MCU_PERFORM_RESET_API == STD_ON )
\r
660 void Mcu_PerformReset(void)
\r
662 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_PERFORMRESET_SERVICE_ID, MCU_E_UNINIT );
\r
665 #if defined(CFG_MPC560X)
\r
666 ME.MCTL.R = 0x00005AF0;
\r
667 ME.MCTL.R = 0x0000A50F;
\r
669 while (ME.GS.B.S_MTRANS) {}
\r
670 while(ME.GS.B.S_CURRENTMODE != 0) {}
\r
672 SIU.SRCR.B.SSR = 1;
\r
678 //-------------------------------------------------------------------
\r
682 * Application Notes!
\r
683 * - AN3584, "MPC5510 Family Low Power Features"
\r
684 * Since it's not complete also check MPC5668
\r
685 * - AN4150 , "Using Sleep Mode on the MPC5668x" and it's code
\r
690 static void enterLowPower (Mcu_ModeType mcuMode )
\r
692 #if defined(CFG_MPC5668)
\r
694 /* Set the sleep bit; following a WAIT instruction, the device will go to sleep */
\r
695 CRP.PSCR.B.SLEEP = 1;
\r
697 /* 0x1 32k, 0x2 64k, 0x3 128k -- RAMs maintain power */
\r
698 CRP.PSCR.B.RAMSEL = 0x3; // Keep all 128K
\r
700 CRP.Z6VEC.R = (uint32)&McuE_LowPowerRecoverFlash;
\r
701 #if defined(CFG_VLE)
\r
705 /* If we "Mcu_Wakeup()" is located in RAM, set FASTREC */
\r
706 CRP.RECPTR.B.FASTREC = 0;
\r
708 /* Halt everything */
\r
709 SIU.HLT0.R = 0x037FFF3D;
\r
710 SIU.HLT1.R = 0x18000F3C;
\r
711 while((SIU.HLTACK0.R != 0x037FFF3D) && (SIU.HLTACK1.R != 0x18000F3C) && (timeout<3000)){}
\r
713 /* put Z0 in reset if not used for wakeup */
\r
714 CRP.Z0VEC.B.Z0RST = 1;
\r
716 // TODO: Enable_all_internal_pull_devices (PULL_DOWN);
\r
718 /* Save context and execute wait instruction.
\r
720 * Things that matter here are
\r
721 * - Z1VEC, determines where TLB0 will point. TLB0 is written with a
\r
722 * value at startup that 4K aligned to this address.
\r
723 * - LowPower_Sleep() will save a interrupt context so we will return
\r
725 * - For devices with little RAM we don't want to impose the alignment
\r
726 * requirements there. Almost as we have to occupy a 4K block for this..
\r
727 * although the code does not take that much space.
\r
729 McuE_EnterLowPower(mcuMode);
\r
731 /* Clear sleep flags to allow pads to operate */
\r
732 CRP.PSCR.B.SLEEPF = 0x1;
\r
734 #elif defined(CFG_MPC5516)
\r
736 /* Set the sleep bit; following a WAIT instruction, the device will go to sleep */
\r
737 CRP.PSCR.B.SLEEP = 1;
\r
738 /* enable the 1.2V internal regulator when in sleep mode only */
\r
739 CRP.PSCR.B.STOP12EN = 1;
\r
740 /* 0x1 8k, 0x2 16k, 0x3 32k, 0x6 64k -- RAMs maintain power */
\r
741 CRP.PSCR.B.RAMSEL = 0x7; // Keep all 80K
\r
743 CRP.Z1VEC.R = (uint32)&McuE_LowPowerRecoverFlash;
\r
744 #if defined(CFG_VLE)
\r
748 /* If we "Mcu_Wakeup()" is located in RAM, set FASTREC */
\r
749 CRP.RECPRTR.B.FASTREC = 0;
\r
751 /* Halt everything */
\r
752 SIU.HLT.R = 0x3FFFFFFF;
\r
753 while((SIU.HLTACK.R != 0x3FFFFFFF) && (timeout<3000)) {}
\r
755 /* put Z0 in reset if not used for wakeup */
\r
756 CRP.Z0VEC.B.Z0RST = 1;
\r
758 // TODO: Enable_all_internal_pull_devices (PULL_DOWN);
\r
760 /* Save context and execute wait instruction.
\r
762 * Things that matter here are
\r
763 * - Z1VEC, determines where TLB0 will point. TLB0 is written with a
\r
764 * value at startup that 4K aligned to this address.
\r
765 * - LowPower_Sleep() will save a interrupt context so we will return
\r
767 * - For devices with little RAM we don't want to impose the alignment
\r
768 * requirements there. Almost as we have to occupy a 4K block for this..
\r
769 * although the code does not take that much space.
\r
771 McuE_EnterLowPower(mcuMode);
\r
773 /* Clear sleep flags to allow pads to operate */
\r
774 CRP.PSCR.B.SLEEPF = 0x1;
\r
776 /* NOT SUPPORTED */
\r
782 void Mcu_SetMode( Mcu_ModeType mcuMode)
\r
784 VALIDATE( ( 1 == Mcu_Global.initRun ), MCU_SETMODE_SERVICE_ID, MCU_E_UNINIT );
\r
785 // VALIDATE( ( McuMode <= Mcu_Global.config->McuNumberOfMcuModes ), MCU_SETMODE_SERVICE_ID, MCU_E_PARAM_MODE );
\r
788 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
789 if( MCU_MODE_RUN == mcuMode ) {
\r
791 } else if( MCU_MODE_SLEEP == mcuMode ) {
\r
793 * Follows the AN3548 from Freescale
\r
796 #if defined(USE_DMA)
\r
801 /* Set system clock to 16Mhz IRC */
\r
802 SIU.SYSCLK.B.SYSCLKSEL = 0;
\r
804 /* Put flash in low-power mode */
\r
807 /* Put QQADC in low-power mode */
\r
810 /* Set us in SLEEP mode */
\r
811 CRP.PSCR.B.SLEEP = 1;
\r
814 enterLowPower(mcuMode);
\r
817 /* NOT SUPPORTED */
\r
822 //-------------------------------------------------------------------
\r
825 * Get the system clock in Hz. It calculates the clock from the
\r
826 * different register settings in HW.
\r
828 uint32_t McuE_GetSystemClock(void)
\r
831 * System clock calculation
\r
833 * 5516 - f_sys = extal * (emfd+16) / ( (eprediv+1) * ( erfd+1 ));
\r
834 * 5567 - f_sys = extal * (emfd+4) / ( (eprediv+1) * ( 2^erfd ));
\r
835 * 563x - We run in legacy mode = 5567
\r
836 * 5606s - f_sys = extal * emfd / ((eprediv+1)*(2<<(erfd)));
\r
838 #if defined(CFG_MPC5516) || defined(CFG_MPC5668)
\r
839 uint32_t eprediv = FMPLL.ESYNCR1.B.EPREDIV;
\r
840 uint32_t emfd = FMPLL.ESYNCR1.B.EMFD;
\r
841 uint32_t erfd = FMPLL.ESYNCR2.B.ERFD;
\r
842 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567) || defined(CFG_MPC5633)
\r
843 uint32_t eprediv = FMPLL.SYNCR.B.PREDIV;
\r
844 uint32_t emfd = FMPLL.SYNCR.B.MFD;
\r
845 uint32_t erfd = FMPLL.SYNCR.B.RFD;
\r
846 #elif defined(CFG_MPC560XB)
\r
847 uint32_t eprediv = CGM.FMPLL_CR.B.IDF;
\r
848 uint32_t emfd = CGM.FMPLL_CR.B.NDIV;
\r
849 uint32_t erfd = CGM.FMPLL_CR.B.ODF;
\r
850 #elif defined(CFG_MPC5606S)
\r
851 uint32_t eprediv = CGM.FMPLL[0].CR.B.IDF;
\r
852 uint32_t emfd = CGM.FMPLL[0].CR.B.NDIV;
\r
853 uint32_t erfd = CGM.FMPLL[0].CR.B.ODF;
\r
857 uint32 extal = Mcu_Global.config->McuClockSettingConfig[Mcu_Global.clockSetting].McuClockReferencePointFrequency;
\r
859 f_sys = CALC_SYSTEM_CLOCK(extal,emfd,eprediv,erfd);
\r
864 #if defined(CFG_MPC5668)
\r
865 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type) {
\r
866 uint32_t sysClock = McuE_GetSystemClock();
\r
867 vuint32_t prescaler;
\r
871 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
872 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
873 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
874 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
875 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
876 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
877 case PERIPHERAL_CLOCK_DSPI_A:
\r
878 case PERIPHERAL_CLOCK_DSPI_B:
\r
879 case PERIPHERAL_CLOCK_DSPI_C:
\r
880 case PERIPHERAL_CLOCK_DSPI_D:
\r
881 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
883 case PERIPHERAL_CLOCK_ESCI_A:
\r
884 case PERIPHERAL_CLOCK_ESCI_B:
\r
885 case PERIPHERAL_CLOCK_ESCI_C:
\r
886 case PERIPHERAL_CLOCK_ESCI_D:
\r
887 case PERIPHERAL_CLOCK_ESCI_E:
\r
888 case PERIPHERAL_CLOCK_ESCI_F:
\r
889 case PERIPHERAL_CLOCK_IIC_A:
\r
890 case PERIPHERAL_CLOCK_IIC_B:
\r
891 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
893 case PERIPHERAL_CLOCK_ADC_A:
\r
894 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
896 case PERIPHERAL_CLOCK_EMIOS:
\r
897 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
904 return sysClock/(1<<prescaler);
\r
911 * Get the peripheral clock in Hz for a specific device
\r
913 uint32_t McuE_GetPeripheralClock(McuE_PeriperalClock_t type)
\r
915 #if defined(CFG_MPC5567)
\r
916 // No peripheral dividers on 5567.
\r
917 return McuE_GetSystemClock();
\r
919 uint32_t sysClock = McuE_GetSystemClock();
\r
920 vuint32_t prescaler;
\r
922 // See table 3.1, section 3.4.5 Peripheral Clock dividers
\r
925 case PERIPHERAL_CLOCK_FLEXCAN_A:
\r
926 case PERIPHERAL_CLOCK_DSPI_A:
\r
927 #if defined(CFG_MPC5516)
\r
928 prescaler = SIU.SYSCLK.B.LPCLKDIV0;
\r
930 #elif defined(CFG_MPC560X)
\r
931 prescaler = CGM.SC_DC[1].B.DIV;
\r
935 case PERIPHERAL_CLOCK_PIT:
\r
936 case PERIPHERAL_CLOCK_ESCI_A:
\r
937 case PERIPHERAL_CLOCK_IIC_A:
\r
938 #if defined(CFG_MPC5516)
\r
939 prescaler = SIU.SYSCLK.B.LPCLKDIV1;
\r
943 case PERIPHERAL_CLOCK_FLEXCAN_B:
\r
944 case PERIPHERAL_CLOCK_FLEXCAN_C:
\r
945 case PERIPHERAL_CLOCK_FLEXCAN_D:
\r
946 case PERIPHERAL_CLOCK_FLEXCAN_E:
\r
947 case PERIPHERAL_CLOCK_FLEXCAN_F:
\r
948 #if defined(CFG_MPC5516)
\r
949 prescaler = SIU.SYSCLK.B.LPCLKDIV2;
\r
951 #elif defined(CFG_MPC560X)
\r
952 prescaler = CGM.SC_DC[1].B.DIV;
\r
956 case PERIPHERAL_CLOCK_DSPI_B:
\r
957 case PERIPHERAL_CLOCK_DSPI_C:
\r
958 case PERIPHERAL_CLOCK_DSPI_D:
\r
959 case PERIPHERAL_CLOCK_DSPI_E:
\r
960 case PERIPHERAL_CLOCK_DSPI_F:
\r
961 #if defined(CFG_MPC5516)
\r
962 prescaler = SIU.SYSCLK.B.LPCLKDIV3;
\r
966 case PERIPHERAL_CLOCK_ESCI_B:
\r
967 case PERIPHERAL_CLOCK_ESCI_C:
\r
968 case PERIPHERAL_CLOCK_ESCI_D:
\r
969 case PERIPHERAL_CLOCK_ESCI_E:
\r
970 case PERIPHERAL_CLOCK_ESCI_F:
\r
971 case PERIPHERAL_CLOCK_ESCI_G:
\r
972 case PERIPHERAL_CLOCK_ESCI_H:
\r
973 #if defined(CFG_MPC5516)
\r
974 prescaler = SIU.SYSCLK.B.LPCLKDIV4;
\r
978 #if defined(CFG_MPC560X)
\r
979 case PERIPHERAL_CLOCK_LIN_A:
\r
980 case PERIPHERAL_CLOCK_LIN_B:
\r
981 #if defined(CFG_MPC560XB)
\r
982 case PERIPHERAL_CLOCK_LIN_C:
\r
983 case PERIPHERAL_CLOCK_LIN_D:
\r
985 prescaler = CGM.SC_DC[0].B.DIV;
\r
987 case PERIPHERAL_CLOCK_EMIOS_0:
\r
988 prescaler = CGM.SC_DC[2].B.DIV;
\r
990 case PERIPHERAL_CLOCK_EMIOS_1:
\r
991 prescaler = CGM.SC_DC[2].B.DIV;
\r
994 case PERIPHERAL_CLOCK_EMIOS:
\r
995 #if defined(CFG_MPC5516)
\r
996 prescaler = SIU.SYSCLK.B.LPCLKDIV5;
\r
1001 case PERIPHERAL_CLOCK_MLB:
\r
1002 #if defined(CFG_MPC5516)
\r
1003 prescaler = SIU.SYSCLK.B.LPCLKDIV6;
\r
1012 return sysClock/(1<<prescaler);
\r
1018 * Function to setup the internal flash for optimal performance
\r
1021 static void Mcu_ConfigureFlash(void)
\r
1023 /* These flash settings increases the CPU performance of 7 times compared
\r
1024 to reset default settings!! */
\r
1026 #if defined(CFG_MPC5516)
\r
1027 /* Disable pipelined reads when flash options are changed. */
\r
1028 FLASH.MCR.B.PRD = 1;
\r
1030 /* Enable master prefetch for e200z1 and eDMA. */
\r
1031 FLASH.PFCRP0.B.M0PFE = 1;
\r
1032 FLASH.PFCRP0.B.M2PFE = 1;
\r
1034 /* Address pipelining control. Must be set to the same value as RWSC. */
\r
1035 FLASH.PFCRP0.B.APC = 2;
\r
1036 FLASH.PFCRP0.B.RWSC = 2;
\r
1038 /* Write wait states. */
\r
1039 FLASH.PFCRP0.B.WWSC = 1;
\r
1041 /* Enable data prefetch. */
\r
1042 FLASH.PFCRP0.B.DPFEN = 1;
\r
1044 /* Enable instruction prefetch. */
\r
1045 FLASH.PFCRP0.B.IPFEN = 1;
\r
1047 /* Prefetch algorithm. */
\r
1048 /* TODO: Ask Freescale about this option. */
\r
1049 FLASH.PFCRP0.B.PFLIM = 2;
\r
1051 /* Enable line read buffers. */
\r
1052 FLASH.PFCRP0.B.BFEN = 1;
\r
1054 /* Enable pipelined reads again. */
\r
1055 FLASH.MCR.B.PRD = 0;
\r
1056 #elif defined(CFG_MPC5668)
\r
1057 /* Check values from cookbook and MPC5668x Microcontroller Data Sheet */
\r
1059 /* Should probably trim this values */
\r
1060 const typeof(FLASH.PFCRP0.B) val = {.M0PFE = 1, .M2PFE=1, .APC=3,
\r
1061 .RWSC=3, .WWSC =1, .DPFEN =1, .IPFEN = 1, .PFLIM =2,
\r
1063 FLASH.PFCRP0.B = val;
\r
1065 /* Enable pipelined reads again. */
\r
1066 #elif defined(CFG_MPC5554) || defined(CFG_MPC5567)
\r
1067 //TODO: Lägg till flash för mpc5554 &67
\r