arch/ppc/mpc55xx/kernel/irq.h

   1 /* -------------------------------- Arctic Core ------------------------------
   2  * Arctic Core - the open source AUTOSAR platform http://arccore.com
   3  *
   4  * Copyright (C) 2009  ArcCore AB <contact@arccore.com>
   5  *
   6  * This source code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by the
   8  * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  * -------------------------------- Arctic Core ------------------------------*/
  15
  16
  17
  18
  19
  20
  21
  22
  23 /*
  24  * irq.h
  25  *
  26  * Defines some additional types used for mpc55xx
  27  *
  28  *  Created on: Jul 13, 2009
  29  *      Author: mahi
  30  */
  31
  32 #ifndef IRQ_H
  33 #define IRQ_H
  34
  35
  36 typedef enum
  37 {
  38   /* Software interrupts. */
  39   INTC_SSCIR0_CLR0,             // 0
  40   INTC_SSCIR0_CLR1,             // 1
  41   INTC_SSCIR0_CLR2,             // 2
  42   INTC_SSCIR0_CLR3,             // 3
  43   INTC_SSCIR0_CLR4,             // 4
  44   INTC_SSCIR0_CLR5,             // 5
  45   INTC_SSCIR0_CLR6,             // 6
  46   INTC_SSCIR0_CLR7,             // 7
  47   MCM_MSWTIR_SWTIC,             // 8
  48   MCM_ESR_COMB,                 // 9
  49   /* eDMA */
  50   EDMA_ERRL_ERR31_0,    // 10
  51   EDMA_INTL_INT0,               // 11
  52   EDMA_INTL_INT1,
  53   EDMA_INTL_INT2,
  54   EDMA_INTL_INT3,
  55   EDMA_INTL_INT4,
  56   EDMA_INTL_INT5,
  57   EDMA_INTL_INT6,
  58   EDMA_INTL_INT7,
  59   EDMA_INTL_INT8,
  60   EDMA_INTL_INT9,
  61   EDMA_INTL_INT10,
  62   EDMA_INTL_INT11,
  63   EDMA_INTL_INT12,
  64   EDMA_INTL_INT13,
  65   EDMA_INTL_INT14,
  66   EDMA_INTL_INT15,              // 26
  67 #if defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
  68   EDMA_INTL_INT16,
  69   EDMA_INTL_INT17,
  70   EDMA_INTL_INT18,
  71   EDMA_INTL_INT19,              // 30
  72   EDMA_INTL_INT20,
  73   EDMA_INTL_INT21,
  74   EDMA_INTL_INT22,
  75   EDMA_INTL_INT23,
  76   EDMA_INTL_INT24,
  77   EDMA_INTL_INT25,
  78   EDMA_INTL_INT26,
  79   EDMA_INTL_INT27,
  80   EDMA_INTL_INT28,
  81   EDMA_INTL_INT29,
  82   EDMA_INTL_INT30,
  83   EDMA_INTL_INT31,              // 42
  84 #else
  85   RESERVED0,
  86   RESERVED1,
  87   RESERVED2,
  88   RESERVED3,                    // 30
  89   RESERVED4,
  90   RESERVED5,
  91   RESERVED6,
  92   RESERVED7,
  93   RESERVED8,
  94   RESERVED9,
  95   RESERVED10,
  96   RESERVED11,
  97   RESERVED12,
  98   RESERVED13,
  99   RESERVED14,
 100   RESERVED15,                   // 42
 101 #endif
 102
 103 #if defined(CFG_MPC5516)
 104   /* Semahpore's */
 105   SEMAPHORE_INT0,               // 43
 106   SEMAPHORE_INT1,
 107   RESERVED16,
 108   CRP_INTERRUPT,
 109   LVI_INTERRUPT,
 110   IIC_A_IBSR_IBIF,
 111   RESERVED17,
 112 #endif
 113   PLL_SYNSR_LOCF,               // 54-43,  16-50
 114   PLL_SYNSR_LOLF,               // 54-44,  16-51
 115   SIU_OSR_OVER,
 116   /* External interrupts */
 117   SIU_EISR_EIF0,                // 53
 118   SIU_EISR_EIF1,
 119   SIU_EISR_EIF2,
 120   SIU_EISR_EIF3,
 121   SIU_EISR_EIF15_4,             // 54-50, 57
 122
 123   /* eMIOS */
 124   EMISOS200_FLAG_F0,    // 58
 125   EMISOS200_FLAG_F1,
 126   EMISOS200_FLAG_F2,
 127   EMISOS200_FLAG_F3,
 128   EMISOS200_FLAG_F4,
 129   EMISOS200_FLAG_F5,
 130   EMISOS200_FLAG_F6,
 131   EMISOS200_FLAG_F7,
 132   EMISOS200_FLAG_F8,
 133   EMISOS200_FLAG_F9,
 134   EMISOS200_FLAG_F10,
 135   EMISOS200_FLAG_F11,
 136   EMISOS200_FLAG_F12,
 137   EMISOS200_FLAG_F13,
 138   EMISOS200_FLAG_F14,
 139   EMISOS200_FLAG_F15,   // 73
 140 #if defined(CFG_MPC5516)
 141   EMISOS200_FLAG_F16,
 142   EMISOS200_FLAG_F17,
 143   EMISOS200_FLAG_F18,
 144   EMISOS200_FLAG_F19,
 145   EMISOS200_FLAG_F20,
 146   EMISOS200_FLAG_F21,
 147   EMISOS200_FLAG_F22,
 148   EMISOS200_FLAG_F23,   // 16-81
 149 #elif defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
 150   ETPU_GLOBAL,          // 54-67
 151   ETPU_A_CIS_0,
 152   ETPU_A_CIS_1,
 153   ETPU_A_CIS_2,         // 54-70
 154   ETPU_A_CIS_3,
 155   ETPU_A_CIS_4,
 156   ETPU_A_CIS_5,
 157   ETPU_A_CIS_6,
 158   ETPU_A_CIS_7,
 159   ETPU_A_CIS_8,
 160   ETPU_A_CIS_9,
 161   ETPU_A_CIS_10,
 162   ETPU_A_CIS_11,
 163   ETPU_A_CIS_12,        // 54-80
 164   ETPU_A_CIS_13,
 165   ETPU_A_CIS_14,
 166   ETPU_A_CIS_15,
 167   ETPU_A_CIS_16,
 168   ETPU_A_CIS_17,
 169   ETPU_A_CIS_18,
 170   ETPU_A_CIS_19,
 171   ETPU_A_CIS_20,
 172   ETPU_A_CIS_21,
 173   ETPU_A_CIS_22,        // 54-90
 174   ETPU_A_CIS_23,
 175   ETPU_A_CIS_24,
 176   ETPU_A_CIS_25,
 177   ETPU_A_CIS_26,
 178   ETPU_A_CIS_27,
 179   ETPU_A_CIS_28,
 180   ETPU_A_CIS_29,
 181   ETPU_A_CIS_30,
 182   ETPU_A_CIS_31,        // 99
 183 #endif
 184
 185   /* eQADC */
 186   EQADC_FISR_OVER,              // 54-100, 16-82
 187   EQADC_FISR0_NCF0,
 188   EQADC_FISR0_PF0,
 189   EQADC_FISR0_EOQF0,
 190   EQADC_FISR0_CFFF0,
 191   EQADC_FISR0_RFDF0,
 192   EQADC_FISR1_NCF1,
 193   EQADC_FISR1_PF1,
 194   EQADC_FISR1_EOQF1,
 195   EQADC_FISR1_CFFF1,
 196   EQADC_FISR1_RFDF1,    // 110, 92
 197   EQADC_FISR2_NCF2,
 198   EQADC_FISR2_PF2,
 199   EQADC_FISR2_EOQF2,
 200   EQADC_FISR2_CFFF2,
 201   EQADC_FISR2_RFDF2,
 202   EQADC_FISR3_NCF3,
 203   EQADC_FISR3_PF3,
 204   EQADC_FISR3_EOQF3,
 205   EQADC_FISR3_CFFF3,
 206   EQADC_FISR3_RFDF3,    // 120, 102
 207   EQADC_FISR4_NCF4,
 208   EQADC_FISR4_PF4,
 209   EQADC_FISR4_EOQF4,
 210   EQADC_FISR4_CFFF4,
 211   EQADC_FISR4_RFDF4,
 212   EQADC_FISR5_NCF5,
 213   EQADC_FISR5_PF5,
 214   EQADC_FISR5_EOQF5,
 215   EQADC_FISR5_CFFF5,
 216   EQADC_FISR5_RFDF5,    // 130, 112
 217
 218 #if defined(CFG_MPC5516)
 219   /* SCI */
 220   SCI_A_COMB,           // 16-113
 221   SCI_B_COMB,
 222   SCI_C_COMB,
 223   SCI_D_COMB,
 224   /* DSPI A,B */
 225   DSPI_A_ISR_OVER,
 226   DSPI_A_ISR_EOQF,
 227   DSPI_A_ISR_TFFF,
 228   DSPI_A_ISR_TCF,
 229   DSPI_A_ISR_RFDF,
 230   DSPI_B_ISR_OVER,      // 16-122
 231   DSPI_B_ISR_EOQF,
 232   DSPI_B_ISR_TFFF,
 233   DSPI_B_ISR_TCF,
 234   DSPI_B_ISR_RFDF,
 235 #elif defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
 236   DSPI_B_COMB,          // 54-131
 237   DSPI_B_ISR_EOQF,
 238   DSPI_B_ISR_TFFF,
 239   DSPI_B_ISR_TCF,
 240   DSPI_B_ISR_RFDF,      // 54-135
 241   DSPI_C_COMB,
 242   DSPI_C_ISR_EOQF,
 243   DSPI_C_ISR_TFFF,
 244   DSPI_C_ISR_TCF,
 245   DSPI_C_ISR_RFDF,      // 54-140
 246   DSPI_D_COMB,
 247   DSPI_D_ISR_EOQF,
 248   DSPI_D_ISR_TFFF,
 249   DSPI_D_ISR_TCF,
 250   DSPI_D_ISR_RFDF,      // 54-145
 251
 252   ESCI_A_COMB0,
 253   RESERVED0,
 254   RESERVED1,
 255   ESCI_A_COMB1,
 256   RESERVED2,
 257   RESERVED3,            // 54-151
 258 #endif
 259
 260   /* FlexCAN A */
 261
 262   FLEXCAN_A_ESR_BOFF_INT, // 54-152, 16-127
 263   FLEXCAN_A_ESR_ERR_INT,
 264   RESERVED18,
 265   FLEXCAN_A_IFLAG1_BUF0I,
 266   FLEXCAN_A_IFLAG1_BUF1I,
 267   FLEXCAN_A_IFLAG1_BUF2I,
 268   FLEXCAN_A_IFLAG1_BUF3I,
 269   FLEXCAN_A_IFLAG1_BUF4I,
 270   FLEXCAN_A_IFLAG1_BUF5I,
 271   FLEXCAN_A_IFLAG1_BUF6I,
 272   FLEXCAN_A_IFLAG1_BUF7I,
 273   FLEXCAN_A_IFLAG1_BUF8I,
 274   FLEXCAN_A_IFLAG1_BUF9I,
 275   FLEXCAN_A_IFLAG1_BUF10I,
 276   FLEXCAN_A_IFLAG1_BUF11I,
 277   FLEXCAN_A_IFLAG1_BUF12I,
 278   FLEXCAN_A_IFLAG1_BUF13I,
 279   FLEXCAN_A_IFLAG1_BUF14I,
 280   FLEXCAN_A_IFLAG1_BUF15I,
 281   FLEXCAN_A_IFLAG1_BUF31_16I,
 282   FLEXCAN_A_IFLAG1_BUF63_32I,
 283
 284 #if defined(CFG_MPC5516)
 285   /* Periodic interrupt timer */
 286   PIT_PITFLG_RTIF,
 287   PIT_PITFLG_PIT1,
 288   PIT_PITFLG_PIT2,
 289   PIT_PITFLG_PIT3,
 290   PIT_PITFLG_PIT4,
 291   PIT_PITFLG_PIT5,
 292   PIT_PITFLG_PIT6,
 293   PIT_PITFLG_PIT7,
 294   PIT_PITFLG_PIT8,
 295
 296   /* FlexCAN B */
 297   FLEXCAN_B_ESR_BOFF_INT,
 298   FLEXCAN_B_ESR_ERR_INT,
 299   RESERVED19,
 300   FLEXCAN_B_IFLAG1_BUF0I,
 301   FLEXCAN_B_IFLAG1_BUF1I,
 302   FLEXCAN_B_IFLAG1_BUF2I,
 303   FLEXCAN_B_IFLAG1_BUF3I,
 304   FLEXCAN_B_IFLAG1_BUF4I,
 305   FLEXCAN_B_IFLAG1_BUF5I,
 306   FLEXCAN_B_IFLAG1_BUF6I,
 307   FLEXCAN_B_IFLAG1_BUF7I,
 308   FLEXCAN_B_IFLAG1_BUF8I,
 309   FLEXCAN_B_IFLAG1_BUF9I,
 310   FLEXCAN_B_IFLAG1_BUF10I,
 311   FLEXCAN_B_IFLAG1_BUF11I,
 312   FLEXCAN_B_IFLAG1_BUF12I,
 313   FLEXCAN_B_IFLAG1_BUF13I,
 314   FLEXCAN_B_IFLAG1_BUF14I,
 315   FLEXCAN_B_IFLAG1_BUF15I,
 316   FLEXCAN_B_IFLAG1_BUF31_16I,
 317   FLEXCAN_B_IFLAG1_BUF63_32I,
 318   /* FlexCAN C */
 319   FLEXCAN_C_ESR_BOFF_INT,
 320   FLEXCAN_C_ESR_ERR_INT,
 321   RESERVED20,
 322   FLEXCAN_C_IFLAG1_BUF0I,
 323   FLEXCAN_C_IFLAG1_BUF1I,
 324   FLEXCAN_C_IFLAG1_BUF2I,
 325   FLEXCAN_C_IFLAG1_BUF3I,
 326   FLEXCAN_C_IFLAG1_BUF4I,
 327   FLEXCAN_C_IFLAG1_BUF5I,
 328   FLEXCAN_C_IFLAG1_BUF6I,
 329   FLEXCAN_C_IFLAG1_BUF7I,
 330   FLEXCAN_C_IFLAG1_BUF8I,
 331   FLEXCAN_C_IFLAG1_BUF9I,
 332   FLEXCAN_C_IFLAG1_BUF10I,
 333   FLEXCAN_C_IFLAG1_BUF11I,
 334   FLEXCAN_C_IFLAG1_BUF12I,
 335   FLEXCAN_C_IFLAG1_BUF13I,
 336   FLEXCAN_C_IFLAG1_BUF14I,
 337   FLEXCAN_C_IFLAG1_BUF15I,
 338   FLEXCAN_C_IFLAG1_BUF31_16I,
 339   FLEXCAN_C_IFLAG1_BUF63_32I,
 340   /* FlexCAN D */
 341   FLEXCAN_D_ESR_BOFF_INT,
 342   FLEXCAN_D_ESR_ERR_INT,
 343   RESERVED21,
 344   FLEXCAN_D_IFLAG1_BUF0I,
 345   FLEXCAN_D_IFLAG1_BUF1I,
 346   FLEXCAN_D_IFLAG1_BUF2I,
 347   FLEXCAN_D_IFLAG1_BUF3I,
 348   FLEXCAN_D_IFLAG1_BUF4I,
 349   FLEXCAN_D_IFLAG1_BUF5I,
 350   FLEXCAN_D_IFLAG1_BUF6I,
 351   FLEXCAN_D_IFLAG1_BUF7I,
 352   FLEXCAN_D_IFLAG1_BUF8I,
 353   FLEXCAN_D_IFLAG1_BUF9I,
 354   FLEXCAN_D_IFLAG1_BUF10I,
 355   FLEXCAN_D_IFLAG1_BUF11I,
 356   FLEXCAN_D_IFLAG1_BUF12I,
 357   FLEXCAN_D_IFLAG1_BUF13I,
 358   FLEXCAN_D_IFLAG1_BUF14I,
 359   FLEXCAN_D_IFLAG1_BUF15I,
 360   FLEXCAN_D_IFLAG1_BUF31_16I,
 361   FLEXCAN_D_IFLAG1_BUF63_32I,
 362   /* FlexCAN E */
 363   FLEXCAN_E_ESR_BOFF_INT,
 364   FLEXCAN_E_ESR_ERR_INT,
 365   RESERVED22,
 366   FLEXCAN_E_IFLAG1_BUF0I,
 367   FLEXCAN_E_IFLAG1_BUF1I,
 368   FLEXCAN_E_IFLAG1_BUF2I,
 369   FLEXCAN_E_IFLAG1_BUF3I,
 370   FLEXCAN_E_IFLAG1_BUF4I,
 371   FLEXCAN_E_IFLAG1_BUF5I,
 372   FLEXCAN_E_IFLAG1_BUF6I,
 373   FLEXCAN_E_IFLAG1_BUF7I,
 374   FLEXCAN_E_IFLAG1_BUF8I,
 375   FLEXCAN_E_IFLAG1_BUF9I,
 376   FLEXCAN_E_IFLAG1_BUF10I,
 377   FLEXCAN_E_IFLAG1_BUF11I,
 378   FLEXCAN_E_IFLAG1_BUF12I,
 379   FLEXCAN_E_IFLAG1_BUF13I,
 380   FLEXCAN_E_IFLAG1_BUF14I,
 381   FLEXCAN_E_IFLAG1_BUF15I,
 382   FLEXCAN_E_IFLAG1_BUF31_16I,
 383   FLEXCAN_E_IFLAG1_BUF63_32I,
 384   /* FlexCAN F */
 385   FLEXCAN_F_ESR_BOFF_INT,
 386   FLEXCAN_F_ESR_ERR_INT,
 387   RESERVED23,
 388   FLEXCAN_F_IFLAG1_BUF0I,
 389   FLEXCAN_F_IFLAG1_BUF1I,
 390   FLEXCAN_F_IFLAG1_BUF2I,
 391   FLEXCAN_F_IFLAG1_BUF3I,
 392   FLEXCAN_F_IFLAG1_BUF4I,
 393   FLEXCAN_F_IFLAG1_BUF5I,
 394   FLEXCAN_F_IFLAG1_BUF6I,
 395   FLEXCAN_F_IFLAG1_BUF7I,
 396   FLEXCAN_F_IFLAG1_BUF8I,
 397   FLEXCAN_F_IFLAG1_BUF9I,
 398   FLEXCAN_F_IFLAG1_BUF10I,
 399   FLEXCAN_F_IFLAG1_BUF11I,
 400   FLEXCAN_F_IFLAG1_BUF12I,
 401   FLEXCAN_F_IFLAG1_BUF13I,
 402   FLEXCAN_F_IFLAG1_BUF14I,
 403   FLEXCAN_F_IFLAG1_BUF15I,
 404   FLEXCAN_F_IFLAG1_BUF31_16I,
 405   FLEXCAN_F_IFLAG1_BUF63_32I,
 406   RESERVED24,
 407   RESERVED25,
 408   RESERVED26,
 409   RESERVED27,
 410   RESERVED28,
 411   RESERVED29,
 412   RESERVED30,
 413   RESERVED31,
 414   /* SCI */
 415   SCI_E_COMB,
 416   SCI_F_COMB,
 417   SCI_G_COMB,
 418   SCI_H_COMB,
 419   /* DSPI */
 420   DSPI_C_ISR_OVER,
 421   DSPI_C_ISR_EOQF,
 422   DSPI_C_ISR_TFFF,
 423   DSPI_C_ISR_TCF,
 424   DSPI_C_ISR_RFDF,
 425   DSPI_D_ISR_OVER,
 426   DSPI_D_ISR_EOQF,
 427   DSPI_D_ISR_TFFF,
 428   DSPI_D_ISR_TCF,
 429   DSPI_D_ISR_RFDF,
 430   /* Flexray */
 431   FLEXRAY_GLOB,
 432   FLEXRAY_PRIF,
 433   FLEXRAY_CHIF,
 434   FLEXRAY_WUP_IF,
 435   FLEXRAY_FBNE_F,
 436   FLEXRAY_FANE_F,
 437   FLEXRAY_RBIF,
 438   FLEXRAY_TBIF,
 439   RESERVED32,
 440   MLB_SERVICE_REQUEST,
 441   INTC_NUMBER_OF_INTERRUPTS,
 442   /* End of INTC interrupts. The vectors below are used to handle exceptions. */
 443   RESERVED_SPACE_BEFORE_EXCEPTIONS1,
 444   RESERVED_SPACE_BEFORE_EXCEPTIONS2,
 445   RESERVED_SPACE_BEFORE_EXCEPTIONS3,
 446   RESERVED_SPACE_BEFORE_EXCEPTIONS4,
 447   RESERVED_SPACE_BEFORE_EXCEPTIONS5,
 448   RESERVED_SPACE_BEFORE_EXCEPTIONS6,
 449   RESERVED_SPACE_BEFORE_EXCEPTIONS7,
 450   RESERVED_SPACE_BEFORE_EXCEPTIONS8,
 451   RESERVED_SPACE_BEFORE_EXCEPTIONS9,
 452   RESERVED_SPACE_BEFORE_EXCEPTIONS10,
 453   RESERVED_SPACE_BEFORE_EXCEPTIONS11,
 454   RESERVED_SPACE_BEFORE_EXCEPTIONS12,
 455   RESERVED_SPACE_BEFORE_EXCEPTIONS13,
 456   RESERVED_SPACE_BEFORE_EXCEPTIONS14,
 457   RESERVED_SPACE_BEFORE_EXCEPTIONS15,
 458   RESERVED_SPACE_BEFORE_EXCEPTIONS16,
 459   RESERVED_SPACE_BEFORE_EXCEPTIONS17,
 460   RESERVED_SPACE_BEFORE_EXCEPTIONS18,
 461   RESERVED_SPACE_BEFORE_EXCEPTIONS19,
 462   RESERVED_SPACE_BEFORE_EXCEPTIONS20,
 463   RESERVED_SPACE_BEFORE_EXCEPTIONS21,
 464   RESERVED_SPACE_BEFORE_EXCEPTIONS22,
 465   RESERVED_SPACE_BEFORE_EXCEPTIONS23,
 466   RESERVED_SPACE_BEFORE_EXCEPTIONS24,
 467   RESERVED_SPACE_BEFORE_EXCEPTIONS25,
 468 #endif
 469
 470 #if defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633)
 471   /* FlexCAN C */
 472   FLEXCAN_C_ESR_BOFF_INT = 173,
 473   FLEXCAN_C_ESR_ERR_INT,
 474   RESERVED20,
 475   FLEXCAN_C_IFLAG1_BUF0I,
 476   FLEXCAN_C_IFLAG1_BUF1I,
 477   FLEXCAN_C_IFLAG1_BUF2I,
 478   FLEXCAN_C_IFLAG1_BUF3I,
 479   FLEXCAN_C_IFLAG1_BUF4I,
 480   FLEXCAN_C_IFLAG1_BUF5I,
 481   FLEXCAN_C_IFLAG1_BUF6I,
 482   FLEXCAN_C_IFLAG1_BUF7I,
 483   FLEXCAN_C_IFLAG1_BUF8I,
 484   FLEXCAN_C_IFLAG1_BUF9I,
 485   FLEXCAN_C_IFLAG1_BUF10I,
 486   FLEXCAN_C_IFLAG1_BUF11I,
 487   FLEXCAN_C_IFLAG1_BUF12I,
 488   FLEXCAN_C_IFLAG1_BUF13I,
 489   FLEXCAN_C_IFLAG1_BUF14I,
 490   FLEXCAN_C_IFLAG1_BUF15I,
 491   FLEXCAN_C_IFLAG1_BUF31_16I,
 492   FLEXCAN_C_IFLAG1_BUF63_32I,
 493
 494   // ....
 495
 496   // 275
 497   DSPI_A_COMB = 275,            // 54-131
 498   DSPI_A_ISR_EOQF,
 499   DSPI_A_ISR_TFFF,
 500   DSPI_A_ISR_TCF,
 501   DSPI_A_ISR_RFDF,      // 54-135
 502
 503   /* FlexCAN B */
 504   FLEXCAN_B_ESR_BOFF_INT = 280,
 505   FLEXCAN_B_ESR_ERR_INT,
 506   RESERVED21,
 507   FLEXCAN_B_IFLAG1_BUF0I,
 508   FLEXCAN_B_IFLAG1_BUF1I,
 509   FLEXCAN_B_IFLAG1_BUF2I,
 510   FLEXCAN_B_IFLAG1_BUF3I,
 511   FLEXCAN_B_IFLAG1_BUF4I,
 512   FLEXCAN_B_IFLAG1_BUF5I,
 513   FLEXCAN_B_IFLAG1_BUF6I,
 514   FLEXCAN_B_IFLAG1_BUF7I,
 515   FLEXCAN_B_IFLAG1_BUF8I,
 516   FLEXCAN_B_IFLAG1_BUF9I,
 517   FLEXCAN_B_IFLAG1_BUF10I,
 518   FLEXCAN_B_IFLAG1_BUF11I,
 519   FLEXCAN_B_IFLAG1_BUF12I,
 520   FLEXCAN_B_IFLAG1_BUF13I,
 521   FLEXCAN_B_IFLAG1_BUF14I,
 522   FLEXCAN_B_IFLAG1_BUF15I,
 523   FLEXCAN_B_IFLAG1_BUF31_16I,
 524   FLEXCAN_B_IFLAG1_BUF63_32I,
 525
 526   /* FlexCAN D */
 527   FLEXCAN_D_ESR_BOFF_INT = 308,
 528   FLEXCAN_D_ESR_ERR_INT,
 529   RESERVED22,
 530   FLEXCAN_D_IFLAG1_BUF0I,
 531   FLEXCAN_D_IFLAG1_BUF1I,
 532   FLEXCAN_D_IFLAG1_BUF2I,
 533   FLEXCAN_D_IFLAG1_BUF3I,
 534   FLEXCAN_D_IFLAG1_BUF4I,
 535   FLEXCAN_D_IFLAG1_BUF5I,
 536   FLEXCAN_D_IFLAG1_BUF6I,
 537   FLEXCAN_D_IFLAG1_BUF7I,
 538   FLEXCAN_D_IFLAG1_BUF8I,
 539   FLEXCAN_D_IFLAG1_BUF9I,
 540   FLEXCAN_D_IFLAG1_BUF10I,
 541   FLEXCAN_D_IFLAG1_BUF11I,
 542   FLEXCAN_D_IFLAG1_BUF12I,
 543   FLEXCAN_D_IFLAG1_BUF13I,
 544   FLEXCAN_D_IFLAG1_BUF14I,
 545   FLEXCAN_D_IFLAG1_BUF15I,
 546   FLEXCAN_D_IFLAG1_BUF31_16I,
 547   FLEXCAN_D_IFLAG1_BUF63_32I,
 548
 549   /* FlexCAN E */
 550   FLEXCAN_E_ESR_BOFF_INT = 329,
 551   FLEXCAN_E_ESR_ERR_INT,
 552   RESERVED23,
 553   FLEXCAN_E_IFLAG1_BUF0I,
 554   FLEXCAN_E_IFLAG1_BUF1I,
 555   FLEXCAN_E_IFLAG1_BUF2I,
 556   FLEXCAN_E_IFLAG1_BUF3I,
 557   FLEXCAN_E_IFLAG1_BUF4I,
 558   FLEXCAN_E_IFLAG1_BUF5I,
 559   FLEXCAN_E_IFLAG1_BUF6I,
 560   FLEXCAN_E_IFLAG1_BUF7I,
 561   FLEXCAN_E_IFLAG1_BUF8I,
 562   FLEXCAN_E_IFLAG1_BUF9I,
 563   FLEXCAN_E_IFLAG1_BUF10I,
 564   FLEXCAN_E_IFLAG1_BUF11I,
 565   FLEXCAN_E_IFLAG1_BUF12I,
 566   FLEXCAN_E_IFLAG1_BUF13I,
 567   FLEXCAN_E_IFLAG1_BUF14I,
 568   FLEXCAN_E_IFLAG1_BUF15I,
 569   FLEXCAN_E_IFLAG1_BUF31_16I,
 570   FLEXCAN_E_IFLAG1_BUF63_32I,
 571
 572   INTC_NUMBER_OF_INTERRUPTS,
 573
 574   DUMMY_DUMMY = 319,
 575
 576 #endif /* defined(CFG_MPC5554)||defined(CFG_MPC5567)||defined(CFG_MPC5633) */
 577
 578   CRITICAL_INPUT_EXCEPTION,
 579   MACHINE_CHECK_EXCEPTION,
 580   DATA_STORAGE_EXCEPTION,
 581   INSTRUCTION_STORAGE_EXCEPTION,
 582   EXTERNAL_INTERRUPT,                    /* This is the place where the "normal" interrupts will hit the CPU... */
 583   ALIGNMENT_EXCEPTION,
 584   PROGRAM_EXCEPTION,
 585   FLOATING_POINT_EXCEPTION,
 586   SYSTEM_CALL_EXCEPTION,
 587   AUX_EXCEPTION,
 588   DECREMENTER_EXCEPTION,
 589   FIXED_INTERVAL_TIMER_EXCEPTION,
 590   WATCHDOG_TIMER_EXCEPTION,
 591   DATA_TLB_EXCEPTION,
 592   INSTRUCTION_TLB_EXCEPTION,
 593   DEBUG_EXCEPTION,
 594   NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS,
 595 }IrqType;
 596
 597 typedef enum {
 598   PERIPHERAL_CLOCK_FLEXCAN_A,
 599   PERIPHERAL_CLOCK_FLEXCAN_B,
 600   PERIPHERAL_CLOCK_FLEXCAN_C,
 601   PERIPHERAL_CLOCK_FLEXCAN_D,
 602   PERIPHERAL_CLOCK_FLEXCAN_E,
 603   PERIPHERAL_CLOCK_FLEXCAN_F,
 604   PERIPHERAL_CLOCK_PIT,
 605   PERIPHERAL_CLOCK_DSPI_A,
 606   PERIPHERAL_CLOCK_DSPI_B,
 607   PERIPHERAL_CLOCK_DSPI_C,
 608   PERIPHERAL_CLOCK_DSPI_D,
 609   PERIPHERAL_CLOCK_EMIOS,
 610   PERIPHERAL_CLOCK_ESCI_A,
 611   PERIPHERAL_CLOCK_ESCI_B,
 612   PERIPHERAL_CLOCK_ESCI_C,
 613   PERIPHERAL_CLOCK_ESCI_D,
 614   PERIPHERAL_CLOCK_ESCI_E,
 615   PERIPHERAL_CLOCK_ESCI_F,
 616   PERIPHERAL_CLOCK_ESCI_G,
 617   PERIPHERAL_CLOCK_ESCI_H,
 618   PERIPHERAL_CLOCK_IIC_A,
 619   PERIPHERAL_CLOCK_MLB,
 620 } McuE_PeriperalClock_t;
 621
 622
 623 #if defined(CFG_MPC5516)
 624 #define CPU_Z1  0
 625 #define CPU_Z0          1
 626 #endif
 627
 628 typedef enum {
 629         CPU_CORE0,
 630         CPU_CORE1,
 631 } Cpu_t;
 632
 633 #define IRQ_INTERRUPT_OFFSET            0
 634
 635 #endif /* IRQ_H_ */