1 /* -------------------------------- Arctic Core ------------------------------
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2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
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4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
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6 * This source code is free software; you can redistribute it and/or modify it
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7 * under the terms of the GNU General Public License version 2 as published by the
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8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
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10 * This program is distributed in the hope that it will be useful, but
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11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 * -------------------------------- Arctic Core ------------------------------*/
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19 #include "Std_Types.h"
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21 #define __I volatile const /*!< defines 'read only' permissions */
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22 #define __O volatile /*!< defines 'write only' permissions */
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23 #define __IO volatile /*!< defines 'read / write' permissions */
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26 typedef volatile struct vimBase
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28 unsigned : 24U; /* 0x0000 */
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29 unsigned IRQIVEC : 8U; /* 0x0000 */
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30 unsigned : 24U; /* 0x0004 */
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31 unsigned FIQIVEC : 8U; /* 0x0004 */
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32 unsigned : 32U; /* 0x0008 */
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33 unsigned : 32U; /* 0x000C */
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34 unsigned FIRQPR0; /* 0x0010 */
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35 unsigned FIRQPR1; /* 0x0014 */
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36 unsigned FIRQPR2; /* 0x0018 */
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37 unsigned FIRQPR3; /* 0x001C */
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38 unsigned INTREQ0; /* 0x0020 */
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39 unsigned INTREQ1; /* 0x0024 */
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40 unsigned INTREQ2; /* 0x0028 */
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41 unsigned INTREQ3; /* 0x002C */
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42 unsigned REQMASKSET0; /* 0x0030 */
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43 unsigned REQMASKSET1; /* 0x0034 */
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44 unsigned REQMASKSET2; /* 0x0038 */
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45 unsigned REQMASKSET3; /* 0x003C */
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46 unsigned REQMASKCLR0; /* 0x0040 */
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47 unsigned REQMASKCLR1; /* 0x0044 */
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48 unsigned REQMASKCLR2; /* 0x0048 */
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49 unsigned REQMASKCLR3; /* 0x004C */
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50 unsigned WAKEMASKSET0; /* 0x0050 */
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51 unsigned WAKEMASKSET1; /* 0x0054 */
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52 unsigned WAKEMASKSET2; /* 0x0058 */
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53 unsigned WAKEMASKSET3; /* 0x005C */
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54 unsigned WAKEMASKCLR0; /* 0x0060 */
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55 unsigned WAKEMASKCLR1; /* 0x0064 */
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56 unsigned WAKEMASKCLR2; /* 0x0068 */
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57 unsigned WAKEMASKCLR3; /* 0x006C */
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58 unsigned IRQVECREG; /* 0x0070 */
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59 unsigned FIQVECREQ; /* 0x0074 */
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60 unsigned : 9U; /* 0x0078 */
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61 unsigned CAPEVTSRC1 : 7U; /* 0x0078 */
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62 unsigned : 9U; /* 0x0078 */
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63 unsigned CAPEVTSRC0 : 7U; /* 0x0078 */
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64 unsigned : 32U; /* 0x007C */
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65 unsigned char CHANMAP[64U]; /* 0x0080-0x017C */
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68 #define vimREG ((vimBASE_t *)0xFFFFFE00U)
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72 typedef volatile struct rtiBase
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74 unsigned GCTRL; /**< 0x0000: Global Control Register */
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75 unsigned TBCTRL; /**< 0x0004: Timebase Control Register */
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76 unsigned CAPCTRL; /**< 0x0008: Capture Control Register */
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77 unsigned COMPCTRL; /**< 0x000C: Compare Control Register */
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80 unsigned FRCx; /**< 0x0010,0x0030: Free Running Counter x Register */
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81 unsigned UCx; /**< 0x0014,0x0034: Up Counter x Register */
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82 unsigned CPUCx; /**< 0x0018,0x0038: Compare Up Counter x Register */
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83 unsigned : 32; /**< 0x001C,0x003C: Reserved */
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84 unsigned CAFRCx; /**< 0x0020,0x0040: Capture Free Running Counter x Register */
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85 unsigned CAUCx; /**< 0x0024,0x0044: Capture Up Counter x Register */
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86 unsigned : 32; /**< 0x0028,0x0048: Reserved */
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87 unsigned : 32; /**< 0x002C,0x004C: Reserved */
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88 } CNT[2U]; /**< Counter x selection:
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93 unsigned COMPx; /**< 0x0050,0x0058,0x0060,0x0068: Compare x Register */
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94 unsigned UDCPx; /**< 0x0054,0x005C,0x0064,0x006C: Update Compare x Register */
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95 } CMP[4U]; /**< Compare x selection:
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100 unsigned TBLCOMP; /**< 0x0070: External Clock Timebase Low Compare Register */
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101 unsigned TBHCOMP; /**< 0x0074: External Clock Timebase High Compare Register */
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102 unsigned : 32; /**< 0x0078: Reserved */
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103 unsigned : 32; /**< 0x007C: Reserved */
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104 unsigned SETINT; /**< 0x0080: Set/Status Interrupt Register */
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105 unsigned CLEARINT; /**< 0x0084: Clear/Status Interrupt Register */
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106 unsigned INTFLAG; /**< 0x008C: Interrupt Flag Register */
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110 * @brief RTI1 Register Frame Pointer
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112 * This pointer is used by the RTI driver to access the RTI1 registers.
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114 #define rtiREG1 ((rtiBASE_t *)0xFFFFFC00)
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117 enum systemClockSource
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119 SYS_OSC = 0, /**< Alias for oscillator clock Source */
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120 SYS_PLL = 1, /**< Alias for Pll clock Source */
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121 SYS_O32 = 2, /**< Alias for 32 kHz oscillator clock Source */
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122 SYS_EXTERNAL = 3, /**< Alias for external clock Source */
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123 SYS_LPO_LOW = 4, /**< Alias for low power oscillator low clock Source */
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124 SYS_LPO_HIGH = 5, /**< Alias for low power oscillator high clock Source */
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125 SYS_FR_PLL = 6, /**< Alias for flexray pll clock Source */
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126 SYS_VCLK = 9 /**< Alias for synchronous VCLK1 clock Source */
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129 typedef volatile struct systemBase1
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131 unsigned SYSPC1; /* 0x0000 */
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132 unsigned SYSPC2; /* 0x0004 */
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133 unsigned SYSPC3; /* 0x0008 */
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134 unsigned SYSPC4; /* 0x000C */
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135 unsigned SYSPC5; /* 0x0010 */
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136 unsigned SYSPC6; /* 0x0014 */
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137 unsigned SYSPC7; /* 0x0018 */
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138 unsigned SYSPC8; /* 0x001C */
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139 unsigned SYSPC9; /* 0x0020 */
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140 unsigned SSWPLL1; /* 0x0024 */
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141 unsigned SSWPLL2; /* 0x0028 */
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142 unsigned SSWPLL3; /* 0x002C */
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143 unsigned CSDIS; /* 0x0030 */
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144 unsigned CSDISSET; /* 0x0034 */
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145 unsigned CSDISCLR; /* 0x0038 */
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146 unsigned CSDDIS; /* 0x003C */
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147 unsigned CSDDISSET; /* 0x0040 */
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148 unsigned CSDDISCLR; /* 0x0044 */
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149 unsigned GHVSRC; /* 0x0048 */
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150 unsigned VCLKASRC; /* 0x004C */
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151 unsigned RCLKSRC; /* 0x0050 */
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152 unsigned CSVSTAT; /* 0x0054 */
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153 unsigned MSTGCR; /* 0x0058 */
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154 unsigned MINITGCR; /* 0x005C */
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155 unsigned MSINENA; /* 0x0060 */
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156 unsigned MSTFAIL; /* 0x0064 */
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157 unsigned MSTCGSTAT; /* 0x0068 */
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158 unsigned MINISTAT; /* 0x006C */
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159 unsigned PLLCTL1; /* 0x0070 */
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160 unsigned PLLCTL2; /* 0x0074 */
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161 unsigned UERFLAG; /* 0x0078 */
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162 unsigned DIEIDL; /* 0x007C */
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163 unsigned DIEIDH; /* 0x0080 */
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164 unsigned VRCTL; /* 0x0084 */
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165 unsigned LPOMONCTL; /* 0x0088 */
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166 unsigned CLKTEST; /* 0x008C */
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167 unsigned DFTCTRLREG1; /* 0x0090 */
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168 unsigned DFTCTRLREG2; /* 0x0094 */
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169 unsigned : 32U; /* 0x0098 */
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170 unsigned : 32U; /* 0x009C */
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171 unsigned GPREG1; /* 0x00A0 */
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172 unsigned BTRMSEL; /* 0x00A4 */
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173 unsigned IMPFASTS; /* 0x00A8 */
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174 unsigned IMPFTADD; /* 0x00AC */
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175 unsigned SSISR1; /* 0x00B0 */
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176 unsigned SSISR2; /* 0x00B4 */
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177 unsigned SSISR3; /* 0x00B8 */
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178 unsigned SSISR4; /* 0x00BC */
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179 unsigned RAMGCR; /* 0x00C0 */
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180 unsigned BMMCR1; /* 0x00C4 */
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181 unsigned BMMCR2; /* 0x00C8 */
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182 unsigned MMUGCR; /* 0x00CC */
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183 #ifdef _little_endian__
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184 unsigned : 8U; /* 0x00D0 */
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185 unsigned PENA : 1U; /* 0x00D0 */
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186 unsigned : 7U; /* 0x00D0 */
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187 unsigned VCLKR : 4U; /* 0x00D0 */
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188 unsigned : 4U; /* 0x00D0 */
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189 unsigned VCLK2R : 4U; /* 0x00D0 */
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190 unsigned : 4U; /* 0x00D0 */
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192 unsigned : 4U; /* 0x00D0 */
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193 unsigned VCLK2R : 4U; /* 0x00D0 */
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194 unsigned : 4U; /* 0x00D0 */
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195 unsigned VCLKR : 4U; /* 0x00D0 */
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196 unsigned : 7U; /* 0x00D0 */
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197 unsigned PENA : 1U; /* 0x00D0 */
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198 unsigned : 8U; /* 0x00D0 */
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200 unsigned : 32U; /* 0x00D4 */
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201 unsigned DSPGCR; /* 0x00D8 */
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202 unsigned DEVCR1; /* 0x00DC */
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203 unsigned SYSECR; /* 0x00E0 */
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204 unsigned SYSESR; /* 0x00E4 */
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205 unsigned ITIFLAG; /* 0x00E8 */
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206 unsigned GBLSTAT; /* 0x00EC */
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207 unsigned DEV; /* 0x00F0 */
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208 unsigned SSIVEC; /* 0x00F4 */
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209 unsigned SSIF; /* 0x00F8 */
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213 /** @def systemREG1
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214 * @brief System Register Frame 1 Pointer
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216 * This pointer is used by the system driver to access the system frame 1 registers.
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218 #define systemREG1 ((systemBASE1_t *)0xFFFFFF00U)
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222 * @brief Alias name for RTI1CLK PRE clock source
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224 * This is an alias name for the RTI1CLK pre clock source.
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225 * This can be either:
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228 * - 32 kHz Oscillator
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230 * - Low Power Oscillator Low
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231 * - Low Power Oscillator High
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234 #define PRE1 SYS_PLL
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237 * @brief Alias name for RTI2CLK pre clock source
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239 * This is an alias name for the RTI2CLK pre clock source.
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240 * This can be either:
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243 * - 32 kHz Oscillator
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245 * - Low Power Oscillator Low
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246 * - Low Power Oscillator High
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249 #define PRE2 SYS_PLL
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251 typedef volatile struct systemBase2
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253 unsigned PLLCTL3; /* 0x0000 */
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254 unsigned : 32U; /* 0x0004 */
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255 unsigned STCCLKDIV; /* 0x0008 */
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256 unsigned CLKHB_GLBREG; /* 0x000C */
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257 unsigned CLKHB_RTIDREG; /* 0x0010 */
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258 unsigned HBCD_STAT; /* 0x0014 */
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259 unsigned : 32U; /* 0x0018 */
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260 unsigned : 32U; /* 0x001C */
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261 unsigned CLKTRMI1; /* 0x0020 */
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262 unsigned ECPCNTRL0; /* 0x0024 */
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263 unsigned ECPCNTRL1; /* 0x0028 */
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264 unsigned ECPCNTRL2; /* 0x002C */
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265 unsigned ECPCNTRL3; /* 0x0030 */
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269 /** @def systemREG2
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270 * @brief System Register Frame 2 Pointer
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272 * This pointer is used by the system driver to access the system frame 2 registers.
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274 #define systemREG2 ((systemBASE2_t *)0xFFFFE100U)
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276 typedef volatile struct pcrBase
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278 unsigned PMPROTSET0; /* 0x0000 */
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279 unsigned PMPROTSET1; /* 0x0004 */
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280 unsigned : 32U; /* 0x0008 */
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281 unsigned : 32U; /* 0x000C */
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282 unsigned PMPROTCLR0; /* 0x0010 */
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283 unsigned PMPROTCLR1; /* 0x0014 */
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284 unsigned : 32U; /* 0x0018 */
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285 unsigned : 32U; /* 0x001C */
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286 unsigned PPROTSET0; /* 0x0020 */
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287 unsigned PPROTSET1; /* 0x0024 */
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288 unsigned PPROTSET2; /* 0x0028 */
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289 unsigned PPROTSET3; /* 0x002C */
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290 unsigned : 32U; /* 0x0030 */
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291 unsigned : 32U; /* 0x0034 */
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292 unsigned : 32U; /* 0x0038 */
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293 unsigned : 32U; /* 0x003C */
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294 unsigned PPROTCLR0; /* 0x0040 */
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295 unsigned PPROTCLR1; /* 0x0044 */
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296 unsigned PPROTCLR2; /* 0x0048 */
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297 unsigned PPROTCLR3; /* 0x004C */
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298 unsigned : 32U; /* 0x0050 */
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299 unsigned : 32U; /* 0x0054 */
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300 unsigned : 32U; /* 0x0058 */
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301 unsigned : 32U; /* 0x005C */
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302 unsigned PCSPWRDWNSET0; /* 0x0060 */
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303 unsigned PCSPWRDWNSET1; /* 0x0064 */
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304 unsigned : 32U; /* 0x0068 */
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305 unsigned : 32U; /* 0x006C */
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306 unsigned PCSPWRDWNCLR0; /* 0x0070 */
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307 unsigned PCSPWRDWNCLR1; /* 0x0074 */
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308 unsigned : 32U; /* 0x0078 */
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309 unsigned : 32U; /* 0x007C */
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310 unsigned PSPWRDWNSET0; /* 0x0080 */
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311 unsigned PSPWRDWNSET1; /* 0x0084 */
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312 unsigned PSPWRDWNSET2; /* 0x0088 */
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313 unsigned PSPWRDWNSET3; /* 0x008C */
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314 unsigned : 32U; /* 0x0090 */
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315 unsigned : 32U; /* 0x0094 */
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316 unsigned : 32U; /* 0x0098 */
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317 unsigned : 32U; /* 0x009C */
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318 unsigned PSPWRDWNCLR0; /* 0x00A0 */
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319 unsigned PSPWRDWNCLR1; /* 0x00A4 */
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320 unsigned PSPWRDWNCLR2; /* 0x00A8 */
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321 unsigned PSPWRDWNCLR3; /* 0x00AC */
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325 * @brief Pcr Register Frame Pointer
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327 * This pointer is used by the system driver to access the Pcr registers.
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329 #define pcrREG ((pcrBASE_t *)0xFFFFE000U)
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332 /*----------------------------------------------------------------------------*/
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333 /* CAN register definition */
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335 typedef volatile struct
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429 } Can_RegisterType;
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432 #define DCAN1_Base ((Can_RegisterType *)0xFFF7DC00)
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433 #define DCAN2_Base ((Can_RegisterType *)0xFFF7DE00)
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434 #define DCAN3_Base ((Can_RegisterType *)0xFFF7E000)
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438 typedef volatile struct gioBase
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440 unsigned GCR0; /**< 0x0000: Global Control Register */
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441 unsigned PWDN; /**< 0x0004: Power Down Register */
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442 unsigned INTDET; /**< 0x0008: Interrupt Detect Regsiter*/
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443 unsigned POL; /**< 0x000C: Interrupt Polarity Register */
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444 unsigned INTENASET; /**< 0x0010: Interrupt Enable Set Register */
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445 unsigned INTENACLR; /**< 0x0014: Interrupt Enable Clear Register */
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446 unsigned LVLSET; /**< 0x0018: Interrupt Priority Set Register */
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447 unsigned LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */
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448 unsigned FLG; /**< 0x0020: Interrupt Flag Register */
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449 unsigned OFFSET0; /**< 0x0024: Interrupt Offset A Register */
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450 unsigned OFFSET1; /**< 0x0028: Interrupt Offset B Register */
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451 } GIO_Base_RegisterType;
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454 /** @struct gioPort
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455 * @brief GIO Port Register Definition
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457 /** @typedef gioPORT_t
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458 * @brief GIO Port Register Type Definition
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460 * This type is used to access the GIO Port Registers.
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462 typedef volatile struct gioPort
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464 unsigned DIR; /**< 0x0000: Data Direction Register */
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465 unsigned DIN; /**< 0x0004: Data Input Register */
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466 unsigned DOUT; /**< 0x0008: Data Output Register */
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467 unsigned DSET; /**< 0x000C: Data Output Set Register */
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468 unsigned DCLR; /**< 0x0010: Data Output Clear Register */
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469 unsigned PDR; /**< 0x0014: Open Drain Regsiter */
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470 unsigned PULDIS; /**< 0x0018: Pullup Disable Register */
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471 unsigned PSL; /**< 0x001C: Pull Up/Down Selection Register */
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472 } GIO_RegisterType;
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474 #define GIO_PORTA_BASE ((GIO_RegisterType *)0xFFF7BC34)
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475 #define GIO_PORTB_BASE ((GIO_RegisterType *)0xFFF7BC54)
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479 * @brief GIO Register Frame Pointer
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481 * This pointer is used by the GIO driver to access the gio module registers.
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483 #define gioREG ((GIO_Base_RegisterType *)0xFFF7BC00U)
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486 * @brief GIO Port (A) Register Pointer
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488 * Pointer used by the GIO driver to access PORTA
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490 #define gioPORTA ((gioPORT_t *)0xFFF7BC34U)
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493 * @brief GIO Port (B) Register Pointer
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495 * Pointer used by the GIO driver to access PORTB
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497 #define gioPORTB ((gioPORT_t *)0xFFF7BC54U)
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502 __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
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503 __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
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504 __IO uint32_t VAL; /*!< SysTick Current Value Register */
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505 __I uint32_t CALIB; /*!< SysTick Calibration Register */
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509 static inline void __disable_irq() {
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510 __asm volatile("CPSID if");
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512 static inline void __enable_irq() {
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513 __asm volatile("CPSIE if");
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516 static inline unsigned long _Irq_Save(void)
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518 register unsigned long val asm("r0");
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519 asm("mrs r0, cpsr");
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520 asm("and r0, r0, #0xC0"); // Mask the I and F bit of CPSR
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525 static inline void _Irq_Restore(unsigned mask) {
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527 __asm volatile("CPSID i");
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529 __asm volatile("CPSIE i");
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532 __asm volatile("CPSID f");
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534 __asm volatile("CPSIE f");
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538 #endif /* CORE_CR4_H_ */
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