1 /* -------------------------------- Arctic Core ------------------------------
2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
6 * This source code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * -------------------------------- Arctic Core ------------------------------*/
21 #include "stm32f10x.h"
26 extern void *Irq_VectorTable[NUMBER_OF_INTERRUPTS_AND_EXCEPTIONS];
28 void Irq_Init( void ) {
29 NVIC_PriorityGroupConfig(NVIC_PriorityGroup_4);
32 void Irq_EOI( void ) {
36 #define ICSR_VECTACTIVE 0x1ff
39 * Get Active ISR number field.
40 * You can subtract 16 from the VECTACTIVE field to index into the Interrupt
41 * Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority
42 * Registers. INTISR[0] has vector number 16.
45 static uint32_t NVIC_GetActiveVector( void) {
46 return (SCB->ICSR & ICSR_VECTACTIVE);
51 * @param stack_p Ptr to the current stack.
53 * The stack holds C, NVGPR, VGPR and the EXC frame.
56 void *Irq_Entry( void *stack_p )
62 stack = (uint32_t *)stack_p;
64 /* 0. Set the default handler here....
65 * 1. Grab the vector from the interrupt controller
66 * INT_CTRL_ST[VECTACTIVE]
67 * 2. Irq_VectorTable[vector] is odd -> ISR1
68 * Irq_VectorTable[vector] is even-> ISR2
72 vector = NVIC_GetActiveVector();
74 stack = Os_Isr(stack, (void *)Irq_VectorTable[vector]);
80 * Attach an ISR type 1 to the interrupt controller.
87 void Irq_AttachIsr1( void (*entry)(void), void *int_ctrl, uint32_t vector, uint8_t prio) {
89 // TODO: Use NVIC_Init here
91 NVIC_InitTypeDef NVIC_InitStructure;
93 // Enable and configure RCC global IRQ channel
94 NVIC_InitStructure.NVIC_IRQChannel = RCC_IRQn;
95 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
96 NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
97 NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
98 NVIC_Init(&NVIC_InitStructure);
102 static inline int osPrioToCpuPio( uint8_t prio ) {
109 * Attach a ISR type 2 to the interrupt controller.
115 void Irq_AttachIsr2(TaskType tid,void *int_ctrl,IrqType vector ) {
117 NVIC_InitTypeDef irqInit;
119 pcb = os_find_task(tid);
120 Irq_VectorTable[vector+16] = (void *)pcb;
122 irqInit.NVIC_IRQChannel = vector;
123 irqInit.NVIC_IRQChannelPreemptionPriority = osPrioToCpuPio(pcb->prio);
124 irqInit.NVIC_IRQChannelSubPriority = 0;
125 irqInit.NVIC_IRQChannelCmd = ENABLE;
128 // TODO: Same as for AttachIsr1
134 * Generates a soft interrupt, ie sets pending bit.
135 * This could also be implemented using ISPR regs.
139 void Irq_GenerateSoftInt( IrqType vector ) {
141 NVIC->STIR = (vector + 16);
145 * Get the current priority from the interrupt controller.
149 uint8_t Irq_GetCurrentPriority( Cpu_t cpu) {
153 // SCB_ICSR contains the active vector