1 /* -------------------------------- Arctic Core ------------------------------
2 * Arctic Core - the open source AUTOSAR platform http://arccore.com
4 * Copyright (C) 2009 ArcCore AB <contact@arccore.com>
6 * This source code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation; See <http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt>.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * -------------------------------- Arctic Core ------------------------------*/
25 #ifndef USE_CAN_STUB
\r
26 #include "mpc55xx.h"
\r
29 #include "CanIf_Cbk.h"
\r
37 #if defined(USE_KERNEL)
\r
43 /* CONFIGURATION NOTES
\r
44 * ------------------------------------------------------------------
\r
45 * - CanHandleType must be CAN_ARC_HANDLE_TYPE_BASIC
\r
46 * i.e. CanHandleType=CAN_ARC_HANDLE_TYPE_FULL NOT supported
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47 * i.e CanIdValue is NOT supported
\r
48 * - All CanXXXProcessing must be CAN_ARC_PROCESS_TYPE_INTERRUPT
\r
49 * ie CAN_ARC_PROCESS_TYPE_POLLED not supported
\r
50 * - To select the Mailboxes to use in the CAN controller use Can_Arc_MbMask
\r
51 * - HOH's for Tx are global and Rx are for each controller
\r
52 * - CanControllerTimeQuanta is NOT used. The other CanControllerXXX selects
\r
53 * the proper time-quanta
\r
54 * - Can_Arc_MbMask for Tx HOH must NOT overlap Can_Arc_MbMask for Rx.
\r
55 * - ONLY global mask is supported( NOT 14,15 and individual )
\r
56 * - Numbering the CanObjectId for Tx:
\r
57 * To do this correctly there are a number of things that are good to know
\r
58 * 1. HTH's have unique numbers.
\r
59 * 2. One HTH/HRH is maped to one HOH
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60 * 3. The extension Can_Arc_MbMask binds FULL CAN boxes together.
\r
65 * ---------------------
\r
70 * 17 | The use of Can_Arc_MbMask=0x000f0000 binds these to HTH 16
\r
71 * 18 | ( bits 16 to 19 set here )
\r
79 * C - Controller number
\r
83 /* IMPLEMENTATION NOTES
\r
84 * -----------------------------------------------
\r
85 * - A HOH us unique for a controller( not a config-set )
\r
86 * - Hrh's are numbered for each controller from 0
\r
87 * - HOH is numbered for each controller in sequences of 0-31
\r
88 * ( since we have 6 controllers and Hth is only uint8( See Can_Write() proto )
\r
89 * - loopback in HW NOT supported
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90 * - 32 of 64 boxes supported ( limited by Hth type )
\r
91 * - Fifo in HW NOT supported
\r
95 * -----------------------------------------------
\r
96 * - Can Hardware unit - One or multiple Can controllers of the same type.
\r
97 * - Hrh - HOH with receive definitions
\r
98 * - Hth - HOH with transmit definitions
\r
103 * ------------------------------------------------------------------
\r
104 * This controller should really be called FlexCan+ or something because
\r
105 * it's enhanced with:
\r
106 * - A RX Fifo !!!!! ( yep, it's fantastic ;) )
\r
107 * - A better matching process. From 25.4.4
\r
108 * "By programming more than one MB with the same ID, received messages will
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109 * be queued into the MBs. The CPU can examine the time stamp field of the
\r
110 * MBs to determine the order in which the messages arrived."
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112 * Soo, now it seems that Freescale have finally done something right.
\r
115 //-------------------------------------------------------------------
\r
117 // Number of mailboxes used for each controller ( power of 2 only )
\r
118 // ( It's NOT supported to set this to 64 )
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119 #define MAX_NUM_OF_MAILBOXES 32
\r
121 #if defined(CFG_MPC5567)
\r
122 #define GET_CONTROLLER(_controller) \
\r
123 ((struct FLEXCAN2_tag *)(0xFFFC0000 + 0x4000*(_controller)))
\r
125 #define GET_CONTROLLER(_controller) \
\r
126 ((struct FLEXCAN_tag *)(0xFFFC0000 + 0x4000*(_controller)))
\r
129 #define GET_CONTROLLER_CONFIG(_controller) \
\r
130 &Can_Global.config->CanConfigSet->CanController[(_controller)]
\r
132 #define GET_CALLBACKS() \
\r
133 (Can_Global.config->CanConfigSet->CanCallbacks)
\r
135 #define GET_PRIVATE_DATA(_controller) \
\r
136 &CanUnit[_controller]
\r
138 #define GET_CONTROLLER_CNT() (CAN_CONTROLLER_CNT)
\r
140 //-------------------------------------------------------------------
\r
142 #if ( CAN_DEV_ERROR_DETECT == STD_ON )
\r
143 #define VALIDATE(_exp,_api,_err ) \
\r
145 Det_ReportError(MODULE_ID_CAN,0,_api,_err); \
\r
146 return CAN_NOT_OK; \
\r
149 #define VALIDATE_NO_RV(_exp,_api,_err ) \
\r
151 Det_ReportError(MODULE_ID_CAN,0,_api,_err); \
\r
155 #define DET_REPORTERROR(_x,_y,_z,_q) Det_ReportError(_x, _y, _z, _q)
\r
157 #define VALIDATE(_exp,_api,_err )
\r
158 #define VALIDATE_NO_RV(_exp,_api,_err )
\r
159 #define DET_REPORTERROR(_x,_y,_z,_q)
\r
163 #define VALIDATE_DEM_NO_RV(_exp,_err ) \
165 Dem_ReportErrorStatus(_err, DEM_EVENT_STATUS_FAILED); \
169 #define VALIDATE_DEM_NO_RV(_exp,_err )
172 //-------------------------------------------------------------------
\r
174 // Message box status defines
\r
175 #define MB_TX_ONCE 0xc
\r
176 #define MB_INACTIVE 0x8
\r
178 #define MB_ABORT 0x9
\r
180 //-------------------------------------------------------------------
\r
185 } Can_DriverStateType;
\r
191 vuint32_t TWRNINT:1;
\r
192 vuint32_t RWRNINT:1;
\r
193 vuint32_t BIT1ERR:1;
\r
194 vuint32_t BIT0ERR:1;
\r
195 vuint32_t ACKERR:1;
\r
196 vuint32_t CRCERR:1;
\r
197 vuint32_t FRMERR:1;
\r
198 vuint32_t STFERR:1;
\r
203 vuint32_t FLTCONF:2;
\r
205 vuint32_t BOFFINT:1;
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206 vuint32_t ERRINT:1;
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207 vuint32_t WAKINT:1;
\r
209 } ESRType; /* Error and Status Register */
\r
211 #if defined(CFG_MPC5567)
\r
212 typedef struct FLEXCAN2_tag flexcan_t;
\r
214 typedef struct FLEXCAN_tag flexcan_t;
\r
217 // Mapping between HRH and Controller//HOH
\r
218 typedef struct Can_Arc_ObjectHOHMapStruct
\r
220 uint32 HxHRef; // Reference to HRH or HTH
\r
221 CanControllerIdType CanControllerRef; // Reference to controller
\r
222 const Can_HardwareObjectType* CanHOHRef; // Reference to HOH.
\r
223 } Can_Arc_ObjectHOHMapType;
\r
225 /* Type for holding global information used by the driver */
\r
227 Can_DriverStateType initRun;
\r
230 const Can_ConfigType *config;
\r
232 // One bit for each channel that is configured.
\r
233 // Used to determine if validity of a channel
\r
235 // 0 - NOT configured
\r
237 // Maps the a channel id to a configured channel id
\r
238 uint8 channelMap[CAN_CONTROLLER_CNT];
\r
240 // This is a map that maps the HTH:s with the controller and Hoh. It is built
\r
241 // during Can_Init and is used to make things faster during a transmit.
\r
242 Can_Arc_ObjectHOHMapType CanHTHMap[NUM_OF_HTHS];
\r
246 Can_GlobalType Can_Global =
\r
248 .initRun = CAN_UNINIT,
\r
252 /* Type for holding information about each controller */
\r
254 CanIf_ControllerModeType state;
\r
256 // Interrupt masks that is for all Mb's in this controller
\r
257 uint32 Can_Arc_RxMbMask;
\r
258 uint32 Can_Arc_TxMbMask;
\r
260 // Used at IFLG in controller at startup
\r
264 Can_Arc_StatisticsType stats;
\r
266 // Data stored for Txconfirmation callbacks to CanIf
\r
267 PduIdType swPduHandles[MAX_NUM_OF_MAILBOXES];
\r
271 #if defined(CFG_MPC5567)
\r
272 Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =
\r
275 .state = CANIF_CS_UNINIT,
\r
277 .state = CANIF_CS_UNINIT,
\r
279 .state = CANIF_CS_UNINIT,
\r
281 .state = CANIF_CS_UNINIT,
\r
283 .state = CANIF_CS_UNINIT,
\r
287 Can_UnitType CanUnit[CAN_CONTROLLER_CNT] =
\r
290 .state = CANIF_CS_UNINIT,
\r
292 .state = CANIF_CS_UNINIT,
\r
294 .state = CANIF_CS_UNINIT,
\r
296 .state = CANIF_CS_UNINIT,
\r
298 .state = CANIF_CS_UNINIT,
\r
300 .state = CANIF_CS_UNINIT,
\r
305 //-------------------------------------------------------------------
\r
307 //-------------------------------------------------------------------
\r
309 * Function that finds the Hoh( HardwareObjectHandle ) from a Hth
\r
310 * A HTH may connect to one or several HOH's. Just find the first one.
\r
312 * @param hth The transmit handle
\r
313 * @returns Ptr to the Hoh
\r
315 static const Can_HardwareObjectType * Can_FindHoh( Can_Arc_HTHType hth , uint32* controller)
\r
317 const Can_HardwareObjectType *hohObj;
\r
318 const Can_Arc_ObjectHOHMapType *map;
\r
319 const Can_ControllerConfigType *canHwConfig;
\r
321 map = &Can_Global.CanHTHMap[hth];
\r
323 // Verify that this is the correct map
\r
324 if (map->HxHRef != hth)
\r
326 DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);
\r
329 canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[map->CanControllerRef]);
\r
331 hohObj = map->CanHOHRef;
\r
333 // Verify that this is the correct Hoh type
\r
334 if ( hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
\r
336 *controller = map->CanControllerRef;
\r
340 DET_REPORTERROR(MODULE_ID_CAN, 0, 0x6, CAN_E_PARAM_HANDLE);
\r
345 //-------------------------------------------------------------------
\r
347 static void Can_Isr( int unit );
\r
348 static void Can_Err( int unit );
\r
349 static void Can_BusOff( int unit );
\r
351 void Can_A_Isr( void ) { Can_Isr(CAN_CTRL_A); }
\r
352 void Can_B_Isr( void ) { Can_Isr(CAN_CTRL_B); }
\r
353 void Can_C_Isr( void ) { Can_Isr(CAN_CTRL_C); }
\r
354 void Can_D_Isr( void ) { Can_Isr(CAN_CTRL_D); }
\r
355 void Can_E_Isr( void ) { Can_Isr(CAN_CTRL_E); }
\r
356 #if defined(CFG_MPC5567)
\r
358 void Can_F_Isr( void ) { Can_Isr(CAN_CTRL_F); }
\r
361 void Can_A_Err( void ) { Can_Err(CAN_CTRL_A); }
\r
362 void Can_B_Err( void ) { Can_Err(CAN_CTRL_B); }
\r
363 void Can_C_Err( void ) { Can_Err(CAN_CTRL_C); }
\r
364 void Can_D_Err( void ) { Can_Err(CAN_CTRL_D); }
\r
365 void Can_E_Err( void ) { Can_Err(CAN_CTRL_E); }
\r
366 #if defined(CFG_MPC5567)
\r
368 void Can_F_Err( void ) { Can_Err(CAN_CTRL_F); }
\r
371 void Can_A_BusOff( void ) { Can_BusOff(CAN_CTRL_A); }
\r
372 void Can_B_BusOff( void ) { Can_BusOff(CAN_CTRL_B); }
\r
373 void Can_C_BusOff( void ) { Can_BusOff(CAN_CTRL_C); }
\r
374 void Can_D_BusOff( void ) { Can_BusOff(CAN_CTRL_D); }
\r
375 void Can_E_BusOff( void ) { Can_BusOff(CAN_CTRL_E); }
\r
376 #if defined(CFG_MPC5567)
\r
378 void Can_F_BusOff( void ) { Can_BusOff(CAN_CTRL_F); }
\r
380 //-------------------------------------------------------------------
\r
384 * Hardware error ISR for CAN
\r
386 * @param unit CAN controller number( from 0 )
\r
389 static void Can_Err( int unit ) {
\r
390 flexcan_t *canHw = GET_CONTROLLER(unit);
\r
391 Can_Arc_ErrorType err;
\r
395 esr.R = canHw->ESR.R;
\r
397 err.B.ACKERR = esr.B.ACKERR;
\r
398 err.B.BIT0ERR = esr.B.BIT0ERR;
\r
399 err.B.BIT1ERR = esr.B.BIT1ERR;
\r
400 err.B.CRCERR = esr.B.CRCERR;
\r
401 err.B.FRMERR = esr.B.FRMERR;
\r
402 err.B.STFERR = esr.B.STFERR;
\r
403 err.B.RXWRN = esr.B.RXWRN;
\r
404 err.B.TXWRN = esr.B.TXWRN;
\r
406 if (GET_CALLBACKS()->Arc_Error != NULL)
\r
408 GET_CALLBACKS()->Arc_Error(unit, err );
\r
411 canHw->ESR.B.ERRINT = 1;
\r
415 // Uses 25.4.5.1 Transmission Abort Mechanism
\r
416 static void Can_AbortTx( flexcan_t *canHw, Can_UnitType *canUnit ) {
\r
420 // Find our Tx boxes.
\r
421 mbMask = canUnit->Can_Arc_TxMbMask;
\r
423 // Loop over the Mb's set to abort
\r
424 for (; mbMask; mbMask&=~(1<<mbNr)) {
\r
425 mbNr = ilog2(mbMask);
\r
427 canHw->BUF[mbNr].CS.B.CODE = MB_ABORT;
\r
430 if( canHw->BUF[mbNr].CS.B.CODE != MB_ABORT ) {
\r
433 // it's not sent... or being sent.
\r
434 // Just wait for it
\r
436 while( canHw->IFRL.R == (1<<mbNr) )
\r
445 // Ack tx interrupts
\r
446 canHw->IFRL.R = canUnit->Can_Arc_TxMbMask;
\r
447 canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;
\r
450 //-------------------------------------------------------------------
\r
453 * BussOff ISR for CAN
\r
455 * @param unit CAN controller number( from 0 )
\r
457 static void Can_BusOff( int unit ) {
\r
458 flexcan_t *canHw = GET_CONTROLLER(unit);
\r
459 Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
\r
460 Can_Arc_ErrorType err;
\r
463 if ( canHw->ESR.B.TWRNINT )
\r
465 err.B.TXWRN = canHw->ESR.B.TXWRN;
\r
466 canUnit->stats.txErrorCnt++;
\r
467 canHw->ESR.B.TWRNINT = 1;
\r
470 if ( canHw->ESR.B.RWRNINT )
\r
472 err.B.RXWRN = canHw->ESR.B.RXWRN;
\r
473 canUnit->stats.rxErrorCnt++;
\r
474 canHw->ESR.B.RWRNINT = 1;
\r
479 if (GET_CALLBACKS()->Arc_Error != NULL)
\r
481 GET_CALLBACKS()->Arc_Error( unit, err );
\r
485 if( canHw->ESR.B.BOFFINT ) {
\r
487 canUnit->stats.boffCnt++;
\r
488 if (GET_CALLBACKS()->ControllerBusOff != NULL)
\r
490 GET_CALLBACKS()->ControllerBusOff(unit);
\r
492 Can_SetControllerMode(unit, CAN_T_STOP); // CANIF272
\r
494 canHw->ESR.B.BOFFINT = 1;
\r
496 Can_AbortTx( canHw, canUnit ); // CANIF273
\r
500 //-------------------------------------------------------------------
\r
503 * ISR for CAN. Normal Rx/Tx operation
\r
505 * @param unit CAN controller number( from 0 )
\r
507 static void Can_Isr(int unit) {
\r
509 flexcan_t *canHw= GET_CONTROLLER(unit);
\r
510 const Can_ControllerConfigType *canHwConfig= GET_CONTROLLER_CONFIG(Can_Global.channelMap[unit]);
\r
511 uint32 iFlagLow = canHw->IFRL.R;
\r
512 Can_UnitType *canUnit = GET_PRIVATE_DATA(unit);
\r
514 // Read interrupt flags to seeTxConfirmation what interrupt triggered the interrupt
\r
515 if (iFlagLow & canHw->IMRL.R) {
\r
518 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
520 // FIFO code NOT tested
\r
521 if (canHw->MCR.B.FEN) {
\r
524 if (iFlagLow & (1<<7)) {
\r
525 canUnit->stats.fifoOverflow++;
\r
526 canHw->IFRL.B.BUF07I = 1;
\r
530 if (iFlagLow & (1<<6)) {
\r
531 canUnit->stats.fifoWarning++;
\r
532 canHw->IFRL.B.BUF06I = 1;
\r
535 // Pop fifo "realtime"
\r
536 while (canHw->IFRL.B.BUF05I) {
\r
538 // TODO MAHI: Must read the entire data-buffer to unlock??
\r
539 if (GET_CALLBACKS()->RxIndication != NULL)
\r
541 GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,
\r
542 canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );
\r
544 // Clear the interrupt
\r
545 canHw->IFRL.B.BUF05I = 1;
\r
550 const Can_HardwareObjectType *hohObj;
\r
557 // Loop over all the Hoh's
\r
561 hohObj= canHwConfig->Can_Arc_Hoh;
\r
566 mbMask = hohObj->Can_Arc_MbMask & iFlagLow;
\r
568 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
\r
570 // Loop over the Mb's for this Hoh
\r
571 for (; mbMask; mbMask&=~(1<<mbNr)) {
\r
572 mbNr = ilog2(mbMask);
\r
574 // Do the necessary dummy reads to keep controller happy
\r
575 data = canHw->BUF[mbNr].CS.R;
\r
576 data = canHw->BUF[mbNr].DATA.W[0];
\r
578 // According to autosar MSB shuould be set if extended
\r
579 if (hohObj->CanIdType == CAN_ID_TYPE_EXTENDED) {
\r
580 id = canHw->BUF[mbNr].ID.R;
\r
583 id = canHw->BUF[mbNr].ID.B.STD_ID;
\r
586 if (GET_CALLBACKS()->RxIndication != NULL)
\r
588 GET_CALLBACKS()->RxIndication(hohObj->CanObjectId,
\r
590 canHw->BUF[mbNr].CS.B.LENGTH,
\r
591 (uint8 *)&canHw->BUF[mbNr].DATA.W[0] );
\r
593 // Increment statistics
\r
594 canUnit->stats.rxSuccessCnt++;
\r
597 canHw->IFRL.R = (1<<mbNr);
\r
600 } while ( !hohObj->Can_Arc_EOL);
\r
603 hohObj= canHwConfig->Can_Arc_Hoh;
\r
608 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
\r
610 mbMask = hohObj->Can_Arc_MbMask & iFlagLow;
\r
612 // Loop over the Mb's for this Hoh
\r
613 for (; mbMask; mbMask&=~(1<<mbNr)) {
\r
614 mbNr = ilog2(mbMask);
\r
616 if (GET_CALLBACKS()->TxConfirmation != NULL)
\r
618 GET_CALLBACKS()->TxConfirmation(canUnit->swPduHandles[mbNr]);
\r
620 canUnit->swPduHandles[mbNr] = 0; // Is this really necessary ??
\r
623 canUnit->iflagStart |= (1<<mbNr);
\r
624 canHw->IFRL.R = (1<<mbNr);
\r
627 } while ( !hohObj->Can_Arc_EOL);
\r
628 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
632 // Note! Over 32 boxes is not implemented
\r
633 // Other reasons that we end up here
\r
634 // - Interupt on a masked box
\r
637 if (canHwConfig->Can_Arc_Fifo) {
\r
639 * NOT tested at all
\r
641 while (canHw->IFRL.B.BUF05I) {
\r
643 // TODO MAHI: Must read the entire data-buffer to unlock??
\r
644 if (GET_CALLBACKS()->RxIndication != NULL)
\r
646 GET_CALLBACKS()->RxIndication((-1), canHw->BUF[0].ID.B.EXT_ID,
\r
647 canHw->BUF[0].CS.B.LENGTH, (uint8 *)&canHw->BUF[0].DATA.W[0] );
\r
649 // Increment statistics
\r
650 canUnit->stats.rxSuccessCnt++;
\r
652 // Clear the interrupt
\r
653 canHw->IFRL.B.BUF05I = 1;
\r
658 //-------------------------------------------------------------------
\r
660 #if defined(USE_KERNEL)
\r
661 #define INSTALL_HANDLERS( _can_name,_boff,_err,_start,_stop) \
\r
664 tid = Os_Arc_CreateIsr(_can_name ## _BusOff,1/*prio*/,"Can"); \
\r
665 Irq_AttachIsr2(tid,NULL,_boff); \
\r
666 tid = Os_Arc_CreateIsr(_can_name ## _Err,1/*prio*/,"Can"); \
\r
667 Irq_AttachIsr2(tid,NULL,_err); \
\r
668 for(i=_start;i<=_stop;i++) { \
\r
669 tid = Os_Arc_CreateIsr(_can_name ## _Isr,1/*prio*/,"Can"); \
\r
670 Irq_AttachIsr2(tid,NULL,i); \
\r
674 #define INSTALL_HANDLERS( _can_name,_boff,_err,_start,_stop) \
\r
675 Irq_InstallVector(_can_name ## _BusOff, _boff, 1, CPU_Z1); \
\r
676 Irq_InstallVector(_can_name ## _Err, _err, 1, CPU_Z1); \
\r
677 for(i=_start;i<=_stop;i++) { \
\r
678 Irq_InstallVector(_can_name ## _Isr, i, 1, CPU_Z1); \
\r
682 // This initiates ALL can controllers
\r
683 void Can_Init( const Can_ConfigType *config ) {
\r
684 Can_UnitType *canUnit;
\r
685 const Can_ControllerConfigType *canHwConfig;
\r
689 VALIDATE_NO_RV( (Can_Global.initRun == CAN_UNINIT), 0x0, CAN_E_TRANSITION );
\r
690 VALIDATE_NO_RV( (config != NULL ), 0x0, CAN_E_PARAM_POINTER );
\r
693 Can_Global.config = config;
\r
694 Can_Global.initRun = CAN_READY;
\r
697 for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {
\r
698 canHwConfig = GET_CONTROLLER_CONFIG(configId);
\r
699 ctlrId = canHwConfig->CanControllerId;
\r
701 // Assign the configuration channel used later..
\r
702 Can_Global.channelMap[canHwConfig->CanControllerId] = configId;
\r
703 Can_Global.configured |= (1<<ctlrId);
\r
705 canUnit = GET_PRIVATE_DATA(ctlrId);
\r
706 canUnit->state = CANIF_CS_STOPPED;
\r
708 canUnit->lock_cnt = 0;
\r
711 memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
\r
713 Can_InitController(ctlrId, canHwConfig);
\r
715 // Loop through all Hoh:s and map them into the HTHMap
\r
716 const Can_HardwareObjectType* hoh;
\r
717 hoh = canHwConfig->Can_Arc_Hoh;
\r
723 if (hoh->CanObjectType == CAN_OBJECT_TYPE_TRANSMIT)
\r
725 Can_Global.CanHTHMap[hoh->CanObjectId].CanControllerRef = canHwConfig->CanControllerId;
\r
726 Can_Global.CanHTHMap[hoh->CanObjectId].CanHOHRef = hoh;
\r
727 Can_Global.CanHTHMap[hoh->CanObjectId].HxHRef = hoh->CanObjectId;
\r
729 } while (!hoh->Can_Arc_EOL);
\r
732 // Could install handlers depending on HW objects to trap more errors
\r
733 // in configuration
\r
734 #if defined(CFG_MPC5567)
\r
735 switch( canHwConfig->CanControllerId ) {
\r
737 INSTALL_HANDLERS(Can_A, FLEXCAN_A_ESR_BOFF_INT, FLEXCAN_A_ESR_ERR_INT, FLEXCAN_A_IFLAG1_BUF0I, FLEXCAN_A_IFLAG1_BUF31_16I); break;
\r
739 INSTALL_HANDLERS(Can_B, FLEXCAN_B_ESR_BOFF_INT, FLEXCAN_B_ESR_ERR_INT, FLEXCAN_B_IFLAG1_BUF0I, FLEXCAN_B_IFLAG1_BUF31_16I); break;
\r
741 INSTALL_HANDLERS(Can_C, FLEXCAN_C_ESR_BOFF_INT, FLEXCAN_C_ESR_ERR_INT, FLEXCAN_C_IFLAG1_BUF0I, FLEXCAN_C_IFLAG1_BUF31_16I); break;
\r
743 INSTALL_HANDLERS(Can_D, FLEXCAN_D_ESR_BOFF_INT, FLEXCAN_D_ESR_ERR_INT, FLEXCAN_D_IFLAG1_BUF0I, FLEXCAN_D_IFLAG1_BUF31_16I); break;
\r
745 INSTALL_HANDLERS(Can_E, FLEXCAN_E_ESR_BOFF_INT, FLEXCAN_E_ESR_ERR_INT, FLEXCAN_E_IFLAG1_BUF0I, FLEXCAN_E_IFLAG1_BUF31_16I); break;
\r
750 switch( canHwConfig->CanControllerId ) {
\r
752 INSTALL_HANDLERS(Can_A, FLEXCAN_A_ESR_BOFF_INT, FLEXCAN_A_ESR_ERR_INT, FLEXCAN_A_IFLAG1_BUF0I, FLEXCAN_A_IFLAG1_BUF31_16I); break;
\r
754 INSTALL_HANDLERS(Can_B, FLEXCAN_B_ESR_BOFF_INT, FLEXCAN_B_ESR_ERR_INT, FLEXCAN_B_IFLAG1_BUF0I, FLEXCAN_B_IFLAG1_BUF31_16I); break;
\r
756 INSTALL_HANDLERS(Can_C, FLEXCAN_C_ESR_BOFF_INT, FLEXCAN_C_ESR_ERR_INT, FLEXCAN_C_IFLAG1_BUF0I, FLEXCAN_C_IFLAG1_BUF31_16I); break;
\r
758 INSTALL_HANDLERS(Can_D, FLEXCAN_D_ESR_BOFF_INT, FLEXCAN_D_ESR_ERR_INT, FLEXCAN_D_IFLAG1_BUF0I, FLEXCAN_D_IFLAG1_BUF31_16I); break;
\r
760 INSTALL_HANDLERS(Can_E, FLEXCAN_E_ESR_BOFF_INT, FLEXCAN_E_ESR_ERR_INT, FLEXCAN_E_IFLAG1_BUF0I, FLEXCAN_E_IFLAG1_BUF31_16I); break;
\r
762 INSTALL_HANDLERS(Can_F, FLEXCAN_F_ESR_BOFF_INT, FLEXCAN_F_ESR_ERR_INT, FLEXCAN_F_IFLAG1_BUF0I, FLEXCAN_F_IFLAG1_BUF31_16I); break;
\r
771 // Unitialize the module
\r
774 Can_UnitType *canUnit;
\r
775 const Can_ControllerConfigType *canHwConfig;
\r
778 for (int configId=0; configId < CAN_ARC_CTRL_CONFIG_CNT; configId++) {
\r
779 canHwConfig = GET_CONTROLLER_CONFIG(configId);
\r
780 ctlrId = canHwConfig->CanControllerId;
\r
782 canUnit = GET_PRIVATE_DATA(ctlrId);
\r
783 canUnit->state = CANIF_CS_UNINIT;
\r
785 Can_DisableControllerInterrupts(ctlrId);
\r
787 canUnit->lock_cnt = 0;
\r
790 memset(&canUnit->stats, 0, sizeof(Can_Arc_StatisticsType));
\r
793 Can_Global.config = NULL;
\r
794 Can_Global.initRun = CAN_UNINIT;
\r
799 void Can_InitController( uint8 controller, const Can_ControllerConfigType *config) {
\r
807 Can_UnitType *canUnit;
\r
808 uint8 cId = controller;
\r
809 const Can_ControllerConfigType *canHwConfig;
\r
810 const Can_HardwareObjectType *hohObj;
\r
812 VALIDATE_NO_RV( (Can_Global.initRun == CAN_READY), 0x2, CAN_E_UNINIT );
\r
813 VALIDATE_NO_RV( (config != NULL ), 0x2,CAN_E_PARAM_POINTER);
\r
814 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x2, CAN_E_PARAM_CONTROLLER );
\r
816 canUnit = GET_PRIVATE_DATA(controller);
\r
818 VALIDATE_NO_RV( (canUnit->state==CANIF_CS_STOPPED), 0x2, CAN_E_TRANSITION );
\r
820 canHw = GET_CONTROLLER(cId);
\r
821 canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[cId]);
\r
823 // Start this baby up
\r
824 canHw->MCR.B.MDIS = 0;
\r
826 // Wait for it to reset
\r
827 if( !SIMULATOR() ) {
\r
828 // Make a reset so we have a known state
\r
829 canHw->MCR.B.SOFTRST = 1;
\r
830 while( canHw->MCR.B.SOFTRST == 1);
\r
831 // Freeze to write all mem mapped registers ( see 25.4.8.1 )
\r
832 canHw->MCR.B.FRZ = 1;
\r
833 while( canHw->MCR.B.FRZACK == 0);
\r
836 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
838 // FIFO implemenation not tested
\r
839 if( config->Can_Arc_Fifo ) {
\r
840 canHw->MCR.B.FEN = 1; // Enable FIFO
\r
841 canHw->MCR.B.IDAM = 0; // We want extended id's to match with
\r
843 canHw->MCR.B.BCC = 1; // Enable all nice features
\r
845 /* Use Fsys derivate */
\r
846 canHw->CR.B.CLKSRC = 1;
\r
847 canHw->MCR.B.MAXMB = MAX_NUM_OF_MAILBOXES - 1;
\r
849 /* Disable selfreception */
\r
850 canHw->MCR.B.SRXDIS = !config->Can_Arc_Loopback;
\r
852 // Clock calucation
\r
853 // -------------------------------------------------------------------
\r
855 // * 1 TQ = Sclk period( also called SCK )
\r
856 // * Ftq = Fcanclk / ( PRESDIV + 1 ) = Sclk
\r
857 // ( Fcanclk can come from crystal or from the peripheral dividers )
\r
860 // TQ = 1/Ftq = (PRESDIV+1)/Fcanclk --> PRESDIV = (TQ * Fcanclk - 1 )
\r
861 // TQ is between 8 and 25
\r
863 // Calculate the number of timequanta's
\r
864 // From "Protocol Timing"( chap. 25.4.7.4 )
\r
865 tq1 = ( config->CanControllerPropSeg + config->CanControllerSeg1 + 2);
\r
866 tq2 = (config->CanControllerSeg2 + 1);
\r
867 tq = 1 + tq1 + tq2;
\r
869 // Check TQ limitations..
870 VALIDATE_DEM_NO_RV(( (tq1>=4) && (tq1<=16)), CAN_E_TIMEOUT );
\r
871 VALIDATE_DEM_NO_RV(( (tq2>=2) && (tq2<=8)), CAN_E_TIMEOUT );
\r
872 VALIDATE_DEM_NO_RV(( (tq>8) && (tq<25 )), CAN_E_TIMEOUT );
\r
874 // Assume we're using the peripheral clock instead of the crystal.
\r
875 clock = McuE_GetPeripheralClock(config->CanCpuClockRef);
\r
877 canHw->CR.B.PRESDIV = clock/(config->CanControllerBaudRate*1000*tq) - 1;
\r
878 canHw->CR.B.PROPSEG = config->CanControllerPropSeg;
\r
879 canHw->CR.B.PSEG1 = config->CanControllerSeg1;
\r
880 canHw->CR.B.PSEG2 = config->CanControllerSeg2;
\r
881 canHw->CR.B.SMP = 1; // 3 samples better than 1 ??
\r
882 canHw->CR.B.LPB = config->Can_Arc_Loopback;
\r
883 canHw->CR.B.BOFFREC = 1; // Disable bus off recovery
\r
885 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
886 // Check if we use individual masks. If so accept anything(=0) for now
\r
887 if( canHw->MCR.B.BCC ) {
\r
888 i = (config->Can_Arc_Fifo ? 8 : 0 );
\r
890 canHw->RXIMR[i].R = 0;
\r
896 if( config->Can_Arc_Fifo ) {
\r
897 // Clear ID's in FIFO also, MUST set extended bit here
\r
898 uint32_t *fifoId = (uint32_t*)(((uint8_t *)canHw)+0xe0);
\r
899 for(int k=0;k<8;k++) {
\r
900 fifoId[k] = 0x40000000; // accept extended frames
\r
904 // Mark all slots as inactive( depending on fifo )
\r
905 i = (config->Can_Arc_Fifo ? 8 : 0 );
\r
906 for(; i < 63; i++) {
\r
907 //canHw->BUF[i].CS.B.CODE = 0;
\r
908 canHw->BUF[i].CS.R = 0;
\r
909 canHw->BUF[i].ID.R = 0;
\r
913 /* Build a global interrupt/mb mask for all Hoh's */
\r
916 Can_FilterMaskType mask = 0xffffffff;
\r
919 hohObj = canHwConfig->Can_Arc_Hoh;
\r
924 mbMask = hohObj->Can_Arc_MbMask;
\r
927 if (hohObj->CanObjectType == CAN_OBJECT_TYPE_RECEIVE)
\r
929 for(;mbMask;mbMask&=~(1<<mbNr)) {
\r
930 mbNr = ilog2(mbMask);
\r
931 canHw->BUF[mbNr].CS.B.CODE = MB_RX;
\r
932 if ( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED )
\r
934 canHw->BUF[mbNr].CS.B.IDE = 1;
\r
935 canHw->BUF[mbNr].ID.R = *hohObj->CanFilterMaskRef; // Write 29-bit MB IDs
\r
939 canHw->BUF[mbNr].CS.B.IDE = 0;
\r
940 canHw->BUF[mbNr].ID.B.STD_ID = *hohObj->CanFilterMaskRef;
\r
944 // Add to global mask
\r
945 canUnit->Can_Arc_RxMbMask |= hohObj->Can_Arc_MbMask;
\r
946 if( hohObj->CanFilterMaskRef != NULL ) {
\r
947 mask &= *hohObj->CanFilterMaskRef;
\r
952 canUnit->Can_Arc_TxMbMask |= hohObj->Can_Arc_MbMask;
\r
954 } while( !hohObj->Can_Arc_EOL );
\r
958 canHw->RXGMASK.R = mask;
\r
960 canHw->RX14MASK.R = 0;
\r
961 canHw->RX15MASK.R = 0;
\r
964 canUnit->iflagStart = canUnit->Can_Arc_TxMbMask;
\r
966 canUnit->state = CANIF_CS_STOPPED;
\r
967 Can_EnableControllerInterrupts(cId);
\r
973 Can_ReturnType Can_SetControllerMode( uint8 controller, Can_StateTransitionType transition ) {
\r
975 Can_ReturnType rv = CAN_OK;
\r
976 VALIDATE( (controller < GET_CONTROLLER_CNT()), 0x3, CAN_E_PARAM_CONTROLLER );
\r
978 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
980 VALIDATE( (canUnit->state!=CANIF_CS_UNINIT), 0x3, CAN_E_UNINIT );
\r
981 canHw = GET_CONTROLLER(controller);
\r
983 switch(transition )
\r
986 canHw->MCR.B.FRZ = 0;
\r
987 canHw->MCR.B.HALT = 0;
\r
988 canUnit->state = CANIF_CS_STARTED;
\r
989 imask_t state = McuE_EnterCriticalSection();
\r
990 if (canUnit->lock_cnt == 0) // REQ CAN196
\r
991 Can_EnableControllerInterrupts(controller);
\r
992 McuE_ExitCriticalSection(state);
\r
994 case CAN_T_WAKEUP: //CAN267
\r
995 case CAN_T_SLEEP: //CAN258, CAN290
\r
996 // Should be reported to DEM but DET is the next best
\r
997 VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);
\r
1000 canHw->MCR.B.FRZ = 1;
\r
1001 canHw->MCR.B.HALT = 1;
\r
1002 canUnit->state = CANIF_CS_STOPPED;
\r
1003 Can_AbortTx( canHw, canUnit ); // CANIF282
\r
1006 // Should be reported to DEM but DET is the next best
\r
1007 VALIDATE(canUnit->state == CANIF_CS_STOPPED, 0x3, CAN_E_TRANSITION);
\r
1014 void Can_DisableControllerInterrupts( uint8 controller )
\r
1016 Can_UnitType *canUnit;
\r
1019 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x4, CAN_E_PARAM_CONTROLLER );
\r
1021 canUnit = GET_PRIVATE_DATA(controller);
\r
1023 VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x4, CAN_E_UNINIT );
\r
1025 imask_t state = McuE_EnterCriticalSection();
\r
1026 if(canUnit->lock_cnt > 0 )
\r
1028 // Interrupts already disabled
\r
1029 canUnit->lock_cnt++;
\r
1030 McuE_ExitCriticalSection(state);
\r
1033 canUnit->lock_cnt++;
\r
1034 McuE_ExitCriticalSection(state);
\r
1036 /* Don't try to be intelligent, turn everything off */
\r
1037 canHw = GET_CONTROLLER(controller);
\r
1039 /* Turn off the interrupt mailboxes */
\r
1040 canHw->IMRH.R = 0;
\r
1041 canHw->IMRL.R = 0;
\r
1043 /* Turn off the bus off/tx warning/rx warning and error */
\r
1044 canHw->MCR.B.WRNEN = 0; /* Disable warning int */
\r
1045 canHw->CR.B.ERRMSK = 0; /* Disable error interrupt */
\r
1046 canHw->CR.B.BOFFMSK = 0; /* Disable bus-off interrupt */
\r
1047 canHw->CR.B.TWRNMSK = 0; /* Disable Tx warning */
\r
1048 canHw->CR.B.RWRNMSK = 0; /* Disable Rx warning */
\r
1051 void Can_EnableControllerInterrupts( uint8 controller ) {
\r
1052 Can_UnitType *canUnit;
\r
1054 const Can_ControllerConfigType *canHwConfig;
\r
1055 VALIDATE_NO_RV( (controller < GET_CONTROLLER_CNT()), 0x5, CAN_E_PARAM_CONTROLLER );
\r
1057 canUnit = GET_PRIVATE_DATA(controller);
\r
1059 VALIDATE_NO_RV( (canUnit->state!=CANIF_CS_UNINIT), 0x5, CAN_E_UNINIT );
\r
1061 imask_t state = McuE_EnterCriticalSection();
\r
1062 if( canUnit->lock_cnt > 1 )
\r
1064 // IRQ should still be disabled so just decrement counter
\r
1065 canUnit->lock_cnt--;
\r
1066 McuE_ExitCriticalSection(state);
\r
1068 } else if (canUnit->lock_cnt == 1)
\r
1070 canUnit->lock_cnt = 0;
\r
1072 McuE_ExitCriticalSection(state);
\r
1074 canHw = GET_CONTROLLER(controller);
\r
1076 canHwConfig = GET_CONTROLLER_CONFIG(Can_Global.channelMap[controller]);
\r
1078 canHw->IMRH.R = 0;
\r
1079 canHw->IMRL.R = 0;
\r
1081 if( canHwConfig->CanRxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1082 /* Turn on the interrupt mailboxes */
\r
1083 canHw->IMRL.R = canUnit->Can_Arc_RxMbMask;
\r
1086 if( canHwConfig->CanTxProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1087 /* Turn on the interrupt mailboxes */
\r
1088 canHw->IMRL.R |= canUnit->Can_Arc_TxMbMask;
\r
1091 // BusOff here represents all errors and warnings
\r
1092 if( canHwConfig->CanBusOffProcessing == CAN_ARC_PROCESS_TYPE_INTERRUPT ) {
\r
1093 canHw->MCR.B.WRNEN = 1; /* Turn On warning int */
\r
1095 canHw->CR.B.ERRMSK = 1; /* Enable error interrupt */
\r
1096 canHw->CR.B.BOFFMSK = 1; /* Enable bus-off interrupt */
\r
1097 canHw->CR.B.TWRNMSK = 1; /* Enable Tx warning */
\r
1098 canHw->CR.B.RWRNMSK = 1; /* Enable Rx warning */
\r
1104 Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo ) {
\r
1107 Can_ReturnType rv = CAN_OK;
\r
1110 const Can_HardwareObjectType *hohObj;
\r
1111 uint32 controller;
\r
1114 VALIDATE( (Can_Global.initRun == CAN_READY), 0x6, CAN_E_UNINIT );
\r
1115 VALIDATE( (pduInfo != NULL), 0x6, CAN_E_PARAM_POINTER );
\r
1116 VALIDATE( (pduInfo->length <= 8), 0x6, CAN_E_PARAM_DLC );
\r
1117 VALIDATE( (hth < NUM_OF_HTHS ), 0x6, CAN_E_PARAM_HANDLE );
\r
1119 hohObj = Can_FindHoh(hth, &controller);
\r
1120 if (hohObj == NULL)
\r
1121 return CAN_NOT_OK;
\r
1123 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1125 canHw = GET_CONTROLLER(controller);
\r
1126 oldMsr = McuE_EnterCriticalSection();
\r
1127 iflag = canHw->IFRL.R & canUnit->Can_Arc_TxMbMask;
\r
1129 // check for any free box
\r
1130 // Normally we would just use the iflag to get the free box
\r
1131 // but that does not work the first time( iflag == 0 ) so we
\r
1132 // create one( iflagStart )
\r
1133 if( iflag | canUnit->iflagStart ) {
\r
1134 mbNr = ilog2((iflag | canUnit->iflagStart)); // find mb number
\r
1136 canHw->IFRL.R = (1<<mbNr);
\r
1137 canUnit->iflagStart &= ~(1<<mbNr);
\r
1139 // Setup message box type
\r
1140 if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {
\r
1141 canHw->BUF[mbNr].CS.B.IDE = 1;
\r
1142 } else if ( hohObj->CanIdType == CAN_ID_TYPE_STANDARD ) {
\r
1143 canHw->BUF[mbNr].CS.B.IDE = 0;
\r
1145 // No support for mixed in this processor
\r
1150 canHw->BUF[mbNr].CS.B.CODE = MB_INACTIVE; // Hold the transmit buffer inactive
\r
1151 if( hohObj->CanIdType == CAN_ID_TYPE_EXTENDED ) {
\r
1152 canHw->BUF[mbNr].ID.R = pduInfo->id; // Write 29-bit MB IDs
\r
1154 assert( !(pduInfo->id & 0xfffff800) );
\r
1155 canHw->BUF[mbNr].ID.B.STD_ID = pduInfo->id;
\r
1158 #if defined(CFG_MPC5516) || defined(CFG_MPC5517)
\r
1159 canHw->BUF[mbNr].ID.B.PRIO = 1; // Set Local Priority
\r
1162 memset(&canHw->BUF[mbNr].DATA, 0, 8);
\r
1163 memcpy(&canHw->BUF[mbNr].DATA, pduInfo->sdu, pduInfo->length);
\r
1165 canHw->BUF[mbNr].CS.B.SRR = 1;
\r
1166 canHw->BUF[mbNr].CS.B.RTR = 0;
\r
1168 canHw->BUF[mbNr].CS.B.LENGTH = pduInfo->length;
\r
1169 canHw->BUF[mbNr].CS.B.CODE = MB_TX_ONCE; // Write tx once code
\r
1170 timer = canHw->TIMER.R; // Unlock Message buffers
\r
1172 canUnit->stats.txSuccessCnt++;
\r
1174 // Store pdu handle in unit to be used by TxConfirmation
\r
1175 canUnit->swPduHandles[mbNr] = pduInfo->swPduHandle;
\r
1180 McuE_ExitCriticalSection(oldMsr);
\r
1185 void Can_MainFunction_Read( void ) {
\r
1187 /* NOT SUPPORTED */
\r
1190 void Can_MainFunction_BusOff( void ) {
\r
1191 /* Bus-off polling events */
\r
1193 /* NOT SUPPORTED */
\r
1196 void Can_MainFunction_Wakeup( void ) {
\r
1197 /* Wakeup polling events */
\r
1199 /* NOT SUPPORTED */
\r
1204 * Get send/receive/error statistics for a controller
\r
1206 * @param controller The controller
\r
1207 * @param stats Pointer to data to copy statistics to
\r
1210 void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType *stats)
\r
1212 Can_UnitType *canUnit = GET_PRIVATE_DATA(controller);
\r
1213 *stats = canUnit->stats;
\r
1218 #else // Stub all functions for use in simulator environment
\r
1220 #include "Trace.h"
\r
1222 void Can_Init( const Can_ConfigType *Config )
\r
1224 // Do initial configuration of layer here
\r
1227 void Can_InitController( uint8 controller, const Can_ControllerConfigType *config)
\r
1229 // Do initialisation of controller here.
\r
1232 Can_ReturnType Can_SetControllerMode( uint8 Controller, Can_StateTransitionType transition )
\r
1234 // Turn on off controller here depending on transition
\r
1238 Can_ReturnType Can_Write( Can_Arc_HTHType hth, Can_PduType *pduInfo )
\r
1240 // Write to mailbox on controller here.
\r
1241 DEBUG(DEBUG_MEDIUM, "Can_Write(stub): Received data ");
\r
1242 for (int i = 0; i < pduInfo->length; i++) {
\r
1243 DEBUG(DEBUG_MEDIUM, "%d ", pduInfo->sdu[i]);
\r
1245 DEBUG(DEBUG_MEDIUM, "\n");
\r
1250 extern void CanIf_RxIndication(uint8 Hrh, Can_IdType CanId, uint8 CanDlc, const uint8 *CanSduPtr);
\r
1251 Can_ReturnType Can_ReceiveAFrame()
\r
1253 // This function is not part of autosar but needed to feed the stack with data
\r
1254 // from the mailboxes. Normally this is an interrup but probably not in the PCAN case.
\r
1255 uint8 CanSduData[] = {1,2,1,0,0,0,0,0};
\r
1256 CanIf_RxIndication(CAN_HRH_A_1, 3, 8, CanSduData);
\r
1261 void Can_DisableControllerInterrupts( uint8 controller )
\r
1265 void Can_EnableControllerInterrupts( uint8 controller )
\r
1270 // Hth - for Flexcan, the hardware message box number... .We don't care
\r
1271 void Can_Cbk_CheckWakeup( uint8 controller ){}
\r
1273 void Can_MainFunction_Write( void ){}
\r
1274 void Can_MainFunction_Read( void ){}
\r
1275 void Can_MainFunction_BusOff( void ){}
\r
1276 void Can_MainFunction_Wakeup( void ){}
\r
1278 void Can_Arc_GetStatistics( uint8 controller, Can_Arc_StatisticsType * stat){}
\r